1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalAlias.h"
40 #include "llvm/IR/GlobalVariable.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
57 #define DEBUG_TYPE "x86-isel"
59 STATISTIC(NumTailCalls, "Number of tail calls");
61 static cl::opt<bool> ExperimentalVectorWideningLegalization(
62 "x86-experimental-vector-widening-legalization", cl::init(false),
63 cl::desc("Enable an experimental vector type legalization through widening "
64 "rather than promotion."),
67 static cl::opt<bool> ExperimentalVectorShuffleLowering(
68 "x86-experimental-vector-shuffle-lowering", cl::init(false),
69 cl::desc("Enable an experimental vector shuffle lowering code path."),
72 // Forward declarations.
73 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
76 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
77 SelectionDAG &DAG, SDLoc dl,
78 unsigned vectorWidth) {
79 assert((vectorWidth == 128 || vectorWidth == 256) &&
80 "Unsupported vector width");
81 EVT VT = Vec.getValueType();
82 EVT ElVT = VT.getVectorElementType();
83 unsigned Factor = VT.getSizeInBits()/vectorWidth;
84 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
85 VT.getVectorNumElements()/Factor);
87 // Extract from UNDEF is UNDEF.
88 if (Vec.getOpcode() == ISD::UNDEF)
89 return DAG.getUNDEF(ResultVT);
91 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
92 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
94 // This is the index of the first element of the vectorWidth-bit chunk
96 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
99 // If the input is a buildvector just emit a smaller one.
100 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
101 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
102 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
105 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
106 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
112 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
113 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
114 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
115 /// instructions or a simple subregister reference. Idx is an index in the
116 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
117 /// lowering EXTRACT_VECTOR_ELT operations easier.
118 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
119 SelectionDAG &DAG, SDLoc dl) {
120 assert((Vec.getValueType().is256BitVector() ||
121 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
122 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
125 /// Generate a DAG to grab 256-bits from a 512-bit vector.
126 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
129 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
132 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
133 unsigned IdxVal, SelectionDAG &DAG,
134 SDLoc dl, unsigned vectorWidth) {
135 assert((vectorWidth == 128 || vectorWidth == 256) &&
136 "Unsupported vector width");
137 // Inserting UNDEF is Result
138 if (Vec.getOpcode() == ISD::UNDEF)
140 EVT VT = Vec.getValueType();
141 EVT ElVT = VT.getVectorElementType();
142 EVT ResultVT = Result.getValueType();
144 // Insert the relevant vectorWidth bits.
145 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
147 // This is the index of the first element of the vectorWidth-bit chunk
149 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
152 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
153 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
156 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
157 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
158 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
159 /// simple superregister reference. Idx is an index in the 128 bits
160 /// we want. It need not be aligned to a 128-bit bounday. That makes
161 /// lowering INSERT_VECTOR_ELT operations easier.
162 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
163 unsigned IdxVal, SelectionDAG &DAG,
165 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
166 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
169 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
170 unsigned IdxVal, SelectionDAG &DAG,
172 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
173 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
176 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
177 /// instructions. This is used because creating CONCAT_VECTOR nodes of
178 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
179 /// large BUILD_VECTORS.
180 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
181 unsigned NumElems, SelectionDAG &DAG,
183 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
184 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
187 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
188 unsigned NumElems, SelectionDAG &DAG,
190 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
191 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
194 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
195 if (TT.isOSBinFormatMachO()) {
196 if (TT.getArch() == Triple::x86_64)
197 return new X86_64MachoTargetObjectFile();
198 return new TargetLoweringObjectFileMachO();
202 return new X86LinuxTargetObjectFile();
203 if (TT.isOSBinFormatELF())
204 return new TargetLoweringObjectFileELF();
205 if (TT.isKnownWindowsMSVCEnvironment())
206 return new X86WindowsTargetObjectFile();
207 if (TT.isOSBinFormatCOFF())
208 return new TargetLoweringObjectFileCOFF();
209 llvm_unreachable("unknown subtarget type");
212 // FIXME: This should stop caching the target machine as soon as
213 // we can remove resetOperationActions et al.
214 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
215 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
216 Subtarget = &TM.getSubtarget<X86Subtarget>();
217 X86ScalarSSEf64 = Subtarget->hasSSE2();
218 X86ScalarSSEf32 = Subtarget->hasSSE1();
219 TD = getDataLayout();
221 resetOperationActions();
224 void X86TargetLowering::resetOperationActions() {
225 const TargetMachine &TM = getTargetMachine();
226 static bool FirstTimeThrough = true;
228 // If none of the target options have changed, then we don't need to reset the
229 // operation actions.
230 if (!FirstTimeThrough && TO == TM.Options) return;
232 if (!FirstTimeThrough) {
233 // Reinitialize the actions.
235 FirstTimeThrough = false;
240 // Set up the TargetLowering object.
241 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
243 // X86 is weird, it always uses i8 for shift amounts and setcc results.
244 setBooleanContents(ZeroOrOneBooleanContent);
245 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
246 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
248 // For 64-bit since we have so many registers use the ILP scheduler, for
249 // 32-bit code use the register pressure specific scheduling.
250 // For Atom, always use ILP scheduling.
251 if (Subtarget->isAtom())
252 setSchedulingPreference(Sched::ILP);
253 else if (Subtarget->is64Bit())
254 setSchedulingPreference(Sched::ILP);
256 setSchedulingPreference(Sched::RegPressure);
257 const X86RegisterInfo *RegInfo =
258 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
259 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
261 // Bypass expensive divides on Atom when compiling with O2
262 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
263 addBypassSlowDiv(32, 8);
264 if (Subtarget->is64Bit())
265 addBypassSlowDiv(64, 16);
268 if (Subtarget->isTargetKnownWindowsMSVC()) {
269 // Setup Windows compiler runtime calls.
270 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
271 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
272 setLibcallName(RTLIB::SREM_I64, "_allrem");
273 setLibcallName(RTLIB::UREM_I64, "_aullrem");
274 setLibcallName(RTLIB::MUL_I64, "_allmul");
275 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
276 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
277 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
281 // The _ftol2 runtime function has an unusual calling conv, which
282 // is modeled by a special pseudo-instruction.
283 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
284 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
285 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
289 if (Subtarget->isTargetDarwin()) {
290 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
291 setUseUnderscoreSetJmp(false);
292 setUseUnderscoreLongJmp(false);
293 } else if (Subtarget->isTargetWindowsGNU()) {
294 // MS runtime is weird: it exports _setjmp, but longjmp!
295 setUseUnderscoreSetJmp(true);
296 setUseUnderscoreLongJmp(false);
298 setUseUnderscoreSetJmp(true);
299 setUseUnderscoreLongJmp(true);
302 // Set up the register classes.
303 addRegisterClass(MVT::i8, &X86::GR8RegClass);
304 addRegisterClass(MVT::i16, &X86::GR16RegClass);
305 addRegisterClass(MVT::i32, &X86::GR32RegClass);
306 if (Subtarget->is64Bit())
307 addRegisterClass(MVT::i64, &X86::GR64RegClass);
309 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
311 // We don't accept any truncstore of integer registers.
312 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
313 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
314 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
315 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
319 // SETOEQ and SETUNE require checking two conditions.
320 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
321 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
322 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
323 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
324 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
325 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
327 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
329 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
330 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
331 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
336 } else if (!TM.Options.UseSoftFloat) {
337 // We have an algorithm for SSE2->double, and we turn this into a
338 // 64-bit FILD followed by conditional FADD for other targets.
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 // We have an algorithm for SSE2, and we turn this into a 64-bit
341 // FILD for other targets.
342 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
345 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
347 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
348 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
350 if (!TM.Options.UseSoftFloat) {
351 // SSE has no i16 to fp conversion, only i32
352 if (X86ScalarSSEf32) {
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
354 // f32 and f64 cases are Legal, f80 case is not
355 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
365 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
366 // are Legal, f80 is custom lowered.
367 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
368 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
370 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
372 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
375 if (X86ScalarSSEf32) {
376 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
377 // f32 and f64 cases are Legal, f80 case is not
378 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
381 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 // Handle FP_TO_UINT by promoting the destination to a larger signed
386 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
387 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
390 if (Subtarget->is64Bit()) {
391 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
393 } else if (!TM.Options.UseSoftFloat) {
394 // Since AVX is a superset of SSE3, only check for SSE here.
395 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
396 // Expand FP_TO_UINT into a select.
397 // FIXME: We would like to use a Custom expander here eventually to do
398 // the optimal thing for SSE vs. the default expansion in the legalizer.
399 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
401 // With SSE3 we can use fisttpll to convert to a signed i64; without
402 // SSE, we're stuck with a fistpll.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
406 if (isTargetFTOL()) {
407 // Use the _ftol2 runtime function, which has a pseudo-instruction
408 // to handle its weird calling convention.
409 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
412 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
413 if (!X86ScalarSSEf64) {
414 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
415 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
416 if (Subtarget->is64Bit()) {
417 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
418 // Without SSE, i64->f64 goes through memory.
419 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
423 // Scalar integer divide and remainder are lowered to use operations that
424 // produce two results, to match the available instructions. This exposes
425 // the two-result form to trivial CSE, which is able to combine x/y and x%y
426 // into a single instruction.
428 // Scalar integer multiply-high is also lowered to use two-result
429 // operations, to match the available instructions. However, plain multiply
430 // (low) operations are left as Legal, as there are single-result
431 // instructions for this in x86. Using the two-result multiply instructions
432 // when both high and low results are needed must be arranged by dagcombine.
433 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
435 setOperationAction(ISD::MULHS, VT, Expand);
436 setOperationAction(ISD::MULHU, VT, Expand);
437 setOperationAction(ISD::SDIV, VT, Expand);
438 setOperationAction(ISD::UDIV, VT, Expand);
439 setOperationAction(ISD::SREM, VT, Expand);
440 setOperationAction(ISD::UREM, VT, Expand);
442 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
443 setOperationAction(ISD::ADDC, VT, Custom);
444 setOperationAction(ISD::ADDE, VT, Custom);
445 setOperationAction(ISD::SUBC, VT, Custom);
446 setOperationAction(ISD::SUBE, VT, Custom);
449 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
450 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
451 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
452 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
453 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
454 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
455 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
456 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
457 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
458 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
459 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
460 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
461 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
465 if (Subtarget->is64Bit())
466 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
468 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
470 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
471 setOperationAction(ISD::FREM , MVT::f32 , Expand);
472 setOperationAction(ISD::FREM , MVT::f64 , Expand);
473 setOperationAction(ISD::FREM , MVT::f80 , Expand);
474 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
476 // Promote the i8 variants and force them on up to i32 which has a shorter
478 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
479 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
480 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
481 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
482 if (Subtarget->hasBMI()) {
483 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
485 if (Subtarget->is64Bit())
486 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
488 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
489 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
490 if (Subtarget->is64Bit())
491 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
494 if (Subtarget->hasLZCNT()) {
495 // When promoting the i8 variants, force them to i32 for a shorter
497 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
498 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
500 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
503 if (Subtarget->is64Bit())
504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
506 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
507 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
508 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
512 if (Subtarget->is64Bit()) {
513 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
518 // Special handling for half-precision floating point conversions.
519 // If we don't have F16C support, then lower half float conversions
520 // into library calls.
521 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
522 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
523 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
526 // There's never any support for operations beyond MVT::f32.
527 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
528 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
529 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
530 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
532 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
533 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
534 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
535 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
537 if (Subtarget->hasPOPCNT()) {
538 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
540 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
541 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
542 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
543 if (Subtarget->is64Bit())
544 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
547 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
549 if (!Subtarget->hasMOVBE())
550 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
552 // These should be promoted to a larger select which is supported.
553 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
554 // X86 wants to expand cmov itself.
555 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
556 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
557 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
558 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
559 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
560 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
561 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
562 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
563 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
564 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
565 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
566 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
567 if (Subtarget->is64Bit()) {
568 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
569 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
571 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
572 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
573 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
574 // support continuation, user-level threading, and etc.. As a result, no
575 // other SjLj exception interfaces are implemented and please don't build
576 // your own exception handling based on them.
577 // LLVM/Clang supports zero-cost DWARF exception handling.
578 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
579 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
582 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
583 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
584 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
585 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
586 if (Subtarget->is64Bit())
587 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
588 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
589 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
590 if (Subtarget->is64Bit()) {
591 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
592 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
593 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
594 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
595 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
597 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
598 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
599 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
600 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
601 if (Subtarget->is64Bit()) {
602 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
607 if (Subtarget->hasSSE1())
608 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
610 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
612 // Expand certain atomics
613 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
615 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
616 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
617 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
620 if (Subtarget->hasCmpxchg16b()) {
621 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
624 // FIXME - use subtarget debug flags
625 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
626 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
627 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
630 if (Subtarget->is64Bit()) {
631 setExceptionPointerRegister(X86::RAX);
632 setExceptionSelectorRegister(X86::RDX);
634 setExceptionPointerRegister(X86::EAX);
635 setExceptionSelectorRegister(X86::EDX);
637 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
638 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
640 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
641 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
643 setOperationAction(ISD::TRAP, MVT::Other, Legal);
644 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
646 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
647 setOperationAction(ISD::VASTART , MVT::Other, Custom);
648 setOperationAction(ISD::VAEND , MVT::Other, Expand);
649 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
650 // TargetInfo::X86_64ABIBuiltinVaList
651 setOperationAction(ISD::VAARG , MVT::Other, Custom);
652 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
654 // TargetInfo::CharPtrBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Expand);
656 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
659 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
660 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
662 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
663 MVT::i64 : MVT::i32, Custom);
665 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
666 // f32 and f64 use SSE.
667 // Set up the FP register classes.
668 addRegisterClass(MVT::f32, &X86::FR32RegClass);
669 addRegisterClass(MVT::f64, &X86::FR64RegClass);
671 // Use ANDPD to simulate FABS.
672 setOperationAction(ISD::FABS , MVT::f64, Custom);
673 setOperationAction(ISD::FABS , MVT::f32, Custom);
675 // Use XORP to simulate FNEG.
676 setOperationAction(ISD::FNEG , MVT::f64, Custom);
677 setOperationAction(ISD::FNEG , MVT::f32, Custom);
679 // Use ANDPD and ORPD to simulate FCOPYSIGN.
680 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
681 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
683 // Lower this to FGETSIGNx86 plus an AND.
684 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
685 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
687 // We don't support sin/cos/fmod
688 setOperationAction(ISD::FSIN , MVT::f64, Expand);
689 setOperationAction(ISD::FCOS , MVT::f64, Expand);
690 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
691 setOperationAction(ISD::FSIN , MVT::f32, Expand);
692 setOperationAction(ISD::FCOS , MVT::f32, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
695 // Expand FP immediates into loads from the stack, except for the special
697 addLegalFPImmediate(APFloat(+0.0)); // xorpd
698 addLegalFPImmediate(APFloat(+0.0f)); // xorps
699 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
700 // Use SSE for f32, x87 for f64.
701 // Set up the FP register classes.
702 addRegisterClass(MVT::f32, &X86::FR32RegClass);
703 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
705 // Use ANDPS to simulate FABS.
706 setOperationAction(ISD::FABS , MVT::f32, Custom);
708 // Use XORP to simulate FNEG.
709 setOperationAction(ISD::FNEG , MVT::f32, Custom);
711 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
713 // Use ANDPS and ORPS to simulate FCOPYSIGN.
714 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
715 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
717 // We don't support sin/cos/fmod
718 setOperationAction(ISD::FSIN , MVT::f32, Expand);
719 setOperationAction(ISD::FCOS , MVT::f32, Expand);
720 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
722 // Special cases we handle for FP constants.
723 addLegalFPImmediate(APFloat(+0.0f)); // xorps
724 addLegalFPImmediate(APFloat(+0.0)); // FLD0
725 addLegalFPImmediate(APFloat(+1.0)); // FLD1
726 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
727 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
729 if (!TM.Options.UnsafeFPMath) {
730 setOperationAction(ISD::FSIN , MVT::f64, Expand);
731 setOperationAction(ISD::FCOS , MVT::f64, Expand);
732 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
734 } else if (!TM.Options.UseSoftFloat) {
735 // f32 and f64 in x87.
736 // Set up the FP register classes.
737 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
738 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
740 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
741 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
742 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
743 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
745 if (!TM.Options.UnsafeFPMath) {
746 setOperationAction(ISD::FSIN , MVT::f64, Expand);
747 setOperationAction(ISD::FSIN , MVT::f32, Expand);
748 setOperationAction(ISD::FCOS , MVT::f64, Expand);
749 setOperationAction(ISD::FCOS , MVT::f32, Expand);
750 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
751 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
753 addLegalFPImmediate(APFloat(+0.0)); // FLD0
754 addLegalFPImmediate(APFloat(+1.0)); // FLD1
755 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
756 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
757 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
758 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
759 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
760 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
763 // We don't support FMA.
764 setOperationAction(ISD::FMA, MVT::f64, Expand);
765 setOperationAction(ISD::FMA, MVT::f32, Expand);
767 // Long double always uses X87.
768 if (!TM.Options.UseSoftFloat) {
769 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
770 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
771 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
773 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
774 addLegalFPImmediate(TmpFlt); // FLD0
776 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
779 APFloat TmpFlt2(+1.0);
780 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
782 addLegalFPImmediate(TmpFlt2); // FLD1
783 TmpFlt2.changeSign();
784 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
787 if (!TM.Options.UnsafeFPMath) {
788 setOperationAction(ISD::FSIN , MVT::f80, Expand);
789 setOperationAction(ISD::FCOS , MVT::f80, Expand);
790 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
793 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
794 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
795 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
796 setOperationAction(ISD::FRINT, MVT::f80, Expand);
797 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
798 setOperationAction(ISD::FMA, MVT::f80, Expand);
801 // Always use a library call for pow.
802 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
803 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
804 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
806 setOperationAction(ISD::FLOG, MVT::f80, Expand);
807 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
808 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
809 setOperationAction(ISD::FEXP, MVT::f80, Expand);
810 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
812 // First set operation action for all vector types to either promote
813 // (for widening) or expand (for scalarization). Then we will selectively
814 // turn on ones that can be effectively codegen'd.
815 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
816 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
817 MVT VT = (MVT::SimpleValueType)i;
818 setOperationAction(ISD::ADD , VT, Expand);
819 setOperationAction(ISD::SUB , VT, Expand);
820 setOperationAction(ISD::FADD, VT, Expand);
821 setOperationAction(ISD::FNEG, VT, Expand);
822 setOperationAction(ISD::FSUB, VT, Expand);
823 setOperationAction(ISD::MUL , VT, Expand);
824 setOperationAction(ISD::FMUL, VT, Expand);
825 setOperationAction(ISD::SDIV, VT, Expand);
826 setOperationAction(ISD::UDIV, VT, Expand);
827 setOperationAction(ISD::FDIV, VT, Expand);
828 setOperationAction(ISD::SREM, VT, Expand);
829 setOperationAction(ISD::UREM, VT, Expand);
830 setOperationAction(ISD::LOAD, VT, Expand);
831 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
832 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
833 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
834 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
835 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
836 setOperationAction(ISD::FABS, VT, Expand);
837 setOperationAction(ISD::FSIN, VT, Expand);
838 setOperationAction(ISD::FSINCOS, VT, Expand);
839 setOperationAction(ISD::FCOS, VT, Expand);
840 setOperationAction(ISD::FSINCOS, VT, Expand);
841 setOperationAction(ISD::FREM, VT, Expand);
842 setOperationAction(ISD::FMA, VT, Expand);
843 setOperationAction(ISD::FPOWI, VT, Expand);
844 setOperationAction(ISD::FSQRT, VT, Expand);
845 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
846 setOperationAction(ISD::FFLOOR, VT, Expand);
847 setOperationAction(ISD::FCEIL, VT, Expand);
848 setOperationAction(ISD::FTRUNC, VT, Expand);
849 setOperationAction(ISD::FRINT, VT, Expand);
850 setOperationAction(ISD::FNEARBYINT, VT, Expand);
851 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
852 setOperationAction(ISD::MULHS, VT, Expand);
853 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
854 setOperationAction(ISD::MULHU, VT, Expand);
855 setOperationAction(ISD::SDIVREM, VT, Expand);
856 setOperationAction(ISD::UDIVREM, VT, Expand);
857 setOperationAction(ISD::FPOW, VT, Expand);
858 setOperationAction(ISD::CTPOP, VT, Expand);
859 setOperationAction(ISD::CTTZ, VT, Expand);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
861 setOperationAction(ISD::CTLZ, VT, Expand);
862 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
863 setOperationAction(ISD::SHL, VT, Expand);
864 setOperationAction(ISD::SRA, VT, Expand);
865 setOperationAction(ISD::SRL, VT, Expand);
866 setOperationAction(ISD::ROTL, VT, Expand);
867 setOperationAction(ISD::ROTR, VT, Expand);
868 setOperationAction(ISD::BSWAP, VT, Expand);
869 setOperationAction(ISD::SETCC, VT, Expand);
870 setOperationAction(ISD::FLOG, VT, Expand);
871 setOperationAction(ISD::FLOG2, VT, Expand);
872 setOperationAction(ISD::FLOG10, VT, Expand);
873 setOperationAction(ISD::FEXP, VT, Expand);
874 setOperationAction(ISD::FEXP2, VT, Expand);
875 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
876 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
877 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
878 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
879 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
880 setOperationAction(ISD::TRUNCATE, VT, Expand);
881 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
882 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
883 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
884 setOperationAction(ISD::VSELECT, VT, Expand);
885 setOperationAction(ISD::SELECT_CC, VT, Expand);
886 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
887 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
888 setTruncStoreAction(VT,
889 (MVT::SimpleValueType)InnerVT, Expand);
890 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
891 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
893 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
894 // we have to deal with them whether we ask for Expansion or not. Setting
895 // Expand causes its own optimisation problems though, so leave them legal.
896 if (VT.getVectorElementType() == MVT::i1)
897 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
900 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
901 // with -msoft-float, disable use of MMX as well.
902 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
903 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
904 // No operations on x86mmx supported, everything uses intrinsics.
907 // MMX-sized vectors (other than x86mmx) are expected to be expanded
908 // into smaller operations.
909 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
910 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
911 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
912 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
913 setOperationAction(ISD::AND, MVT::v8i8, Expand);
914 setOperationAction(ISD::AND, MVT::v4i16, Expand);
915 setOperationAction(ISD::AND, MVT::v2i32, Expand);
916 setOperationAction(ISD::AND, MVT::v1i64, Expand);
917 setOperationAction(ISD::OR, MVT::v8i8, Expand);
918 setOperationAction(ISD::OR, MVT::v4i16, Expand);
919 setOperationAction(ISD::OR, MVT::v2i32, Expand);
920 setOperationAction(ISD::OR, MVT::v1i64, Expand);
921 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
922 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
923 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
924 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
925 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
926 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
927 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
929 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
930 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
931 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
932 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
933 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
934 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
935 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
936 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
939 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
940 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
942 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
943 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
944 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
945 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
947 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
948 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
949 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
950 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
951 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
952 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
953 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
956 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
957 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
959 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
960 // registers cannot be used even for integer operations.
961 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
962 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
963 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
964 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
966 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
967 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
968 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
969 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
970 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
971 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
972 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
973 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
974 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
975 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
976 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
977 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
978 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
979 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
980 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
981 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
982 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
983 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
984 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
986 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
987 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
989 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
990 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
991 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
992 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
994 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
995 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1000 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1001 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1002 MVT VT = (MVT::SimpleValueType)i;
1003 // Do not attempt to custom lower non-power-of-2 vectors
1004 if (!isPowerOf2_32(VT.getVectorNumElements()))
1006 // Do not attempt to custom lower non-128-bit vectors
1007 if (!VT.is128BitVector())
1009 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1010 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1014 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1015 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1016 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1017 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1018 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1019 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1021 if (Subtarget->is64Bit()) {
1022 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1026 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1027 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1028 MVT VT = (MVT::SimpleValueType)i;
1030 // Do not attempt to promote non-128-bit vectors
1031 if (!VT.is128BitVector())
1034 setOperationAction(ISD::AND, VT, Promote);
1035 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1036 setOperationAction(ISD::OR, VT, Promote);
1037 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1038 setOperationAction(ISD::XOR, VT, Promote);
1039 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1040 setOperationAction(ISD::LOAD, VT, Promote);
1041 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1042 setOperationAction(ISD::SELECT, VT, Promote);
1043 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1046 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1048 // Custom lower v2i64 and v2f64 selects.
1049 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1050 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1051 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1052 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1054 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1055 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1057 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1058 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1059 // As there is no 64-bit GPR available, we need build a special custom
1060 // sequence to convert from v2i32 to v2f32.
1061 if (!Subtarget->is64Bit())
1062 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1064 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1065 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1067 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1069 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1070 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1071 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1074 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1075 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1076 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1077 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1078 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1079 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1080 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1081 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1082 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1083 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1084 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1086 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1087 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1088 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1089 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1090 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1091 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1092 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1093 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1094 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1095 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1097 // FIXME: Do we need to handle scalar-to-vector here?
1098 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1100 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1101 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1102 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1103 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1104 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1105 // There is no BLENDI for byte vectors. We don't need to custom lower
1106 // some vselects for now.
1107 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1109 // i8 and i16 vectors are custom , because the source register and source
1110 // source memory operand types are not the same width. f32 vectors are
1111 // custom since the immediate controlling the insert encodes additional
1113 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1114 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1115 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1116 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1118 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1119 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1120 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1121 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1123 // FIXME: these should be Legal but thats only for the case where
1124 // the index is constant. For now custom expand to deal with that.
1125 if (Subtarget->is64Bit()) {
1126 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1127 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1131 if (Subtarget->hasSSE2()) {
1132 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1133 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1135 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1136 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1138 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1139 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1141 // In the customized shift lowering, the legal cases in AVX2 will be
1143 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1144 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1146 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1147 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1149 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1152 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1153 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1154 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1155 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1156 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1157 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1158 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1160 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1161 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1162 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1164 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1165 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1166 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1167 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1168 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1169 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1170 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1171 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1172 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1173 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1174 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1175 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1177 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1178 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1179 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1180 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1181 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1182 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1183 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1184 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1185 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1186 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1187 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1188 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1190 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1191 // even though v8i16 is a legal type.
1192 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1193 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1194 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1196 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1197 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1198 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1200 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1201 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1203 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1205 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1206 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1208 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1209 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1211 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1212 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1214 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1215 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1216 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1217 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1219 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1220 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1221 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1223 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1224 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1225 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1226 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1228 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1229 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1230 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1231 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1232 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1233 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1234 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1235 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1236 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1237 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1238 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1239 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1241 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1242 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1243 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1244 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1245 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1246 setOperationAction(ISD::FMA, MVT::f32, Legal);
1247 setOperationAction(ISD::FMA, MVT::f64, Legal);
1250 if (Subtarget->hasInt256()) {
1251 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1252 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1253 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1254 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1256 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1257 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1258 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1259 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1261 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1262 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1263 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1264 // Don't lower v32i8 because there is no 128-bit byte mul
1266 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1267 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1268 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1269 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1271 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1272 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1274 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1275 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1276 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1277 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1279 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1280 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1281 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1282 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1284 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1285 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1286 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1287 // Don't lower v32i8 because there is no 128-bit byte mul
1290 // In the customized shift lowering, the legal cases in AVX2 will be
1292 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1293 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1295 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1296 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1298 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1300 // Custom lower several nodes for 256-bit types.
1301 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1302 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1303 MVT VT = (MVT::SimpleValueType)i;
1305 // Extract subvector is special because the value type
1306 // (result) is 128-bit but the source is 256-bit wide.
1307 if (VT.is128BitVector())
1308 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1310 // Do not attempt to custom lower other non-256-bit vectors
1311 if (!VT.is256BitVector())
1314 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1315 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1316 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1317 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1318 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1319 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1320 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1323 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1324 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1325 MVT VT = (MVT::SimpleValueType)i;
1327 // Do not attempt to promote non-256-bit vectors
1328 if (!VT.is256BitVector())
1331 setOperationAction(ISD::AND, VT, Promote);
1332 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1333 setOperationAction(ISD::OR, VT, Promote);
1334 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1335 setOperationAction(ISD::XOR, VT, Promote);
1336 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1337 setOperationAction(ISD::LOAD, VT, Promote);
1338 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1339 setOperationAction(ISD::SELECT, VT, Promote);
1340 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1344 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1345 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1346 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1347 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1348 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1350 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1351 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1352 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1354 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1355 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1356 setOperationAction(ISD::XOR, MVT::i1, Legal);
1357 setOperationAction(ISD::OR, MVT::i1, Legal);
1358 setOperationAction(ISD::AND, MVT::i1, Legal);
1359 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1360 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1361 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1362 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1363 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1364 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1366 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1367 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1368 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1369 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1370 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1371 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1373 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1374 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1375 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1376 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1377 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1378 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1379 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1380 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1382 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1383 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1384 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1385 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1386 if (Subtarget->is64Bit()) {
1387 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1388 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1389 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1390 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1392 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1393 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1394 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1395 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1396 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1397 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1398 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1399 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1400 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1401 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1403 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1404 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1405 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1406 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1407 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1408 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1409 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1410 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1411 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1412 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1413 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1414 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1415 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1417 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1418 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1419 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1420 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1421 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1422 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1424 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1425 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1427 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1429 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1430 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1431 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1432 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1433 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1434 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1435 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1436 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1437 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1439 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1440 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1442 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1443 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1445 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1447 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1448 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1450 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1451 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1453 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1454 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1456 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1457 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1458 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1459 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1460 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1461 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1463 if (Subtarget->hasCDI()) {
1464 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1465 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1468 // Custom lower several nodes.
1469 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1470 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1471 MVT VT = (MVT::SimpleValueType)i;
1473 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1474 // Extract subvector is special because the value type
1475 // (result) is 256/128-bit but the source is 512-bit wide.
1476 if (VT.is128BitVector() || VT.is256BitVector())
1477 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1479 if (VT.getVectorElementType() == MVT::i1)
1480 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1482 // Do not attempt to custom lower other non-512-bit vectors
1483 if (!VT.is512BitVector())
1486 if ( EltSize >= 32) {
1487 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1488 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1489 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1490 setOperationAction(ISD::VSELECT, VT, Legal);
1491 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1492 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1493 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1496 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1497 MVT VT = (MVT::SimpleValueType)i;
1499 // Do not attempt to promote non-256-bit vectors
1500 if (!VT.is512BitVector())
1503 setOperationAction(ISD::SELECT, VT, Promote);
1504 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1508 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1509 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1510 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1513 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1514 // of this type with custom code.
1515 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1516 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1517 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1521 // We want to custom lower some of our intrinsics.
1522 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1523 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1524 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1525 if (!Subtarget->is64Bit())
1526 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1528 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1529 // handle type legalization for these operations here.
1531 // FIXME: We really should do custom legalization for addition and
1532 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1533 // than generic legalization for 64-bit multiplication-with-overflow, though.
1534 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1535 // Add/Sub/Mul with overflow operations are custom lowered.
1537 setOperationAction(ISD::SADDO, VT, Custom);
1538 setOperationAction(ISD::UADDO, VT, Custom);
1539 setOperationAction(ISD::SSUBO, VT, Custom);
1540 setOperationAction(ISD::USUBO, VT, Custom);
1541 setOperationAction(ISD::SMULO, VT, Custom);
1542 setOperationAction(ISD::UMULO, VT, Custom);
1545 // There are no 8-bit 3-address imul/mul instructions
1546 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1547 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1549 if (!Subtarget->is64Bit()) {
1550 // These libcalls are not available in 32-bit.
1551 setLibcallName(RTLIB::SHL_I128, nullptr);
1552 setLibcallName(RTLIB::SRL_I128, nullptr);
1553 setLibcallName(RTLIB::SRA_I128, nullptr);
1556 // Combine sin / cos into one node or libcall if possible.
1557 if (Subtarget->hasSinCos()) {
1558 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1559 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1560 if (Subtarget->isTargetDarwin()) {
1561 // For MacOSX, we don't want to the normal expansion of a libcall to
1562 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1564 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1565 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1569 if (Subtarget->isTargetWin64()) {
1570 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1571 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1572 setOperationAction(ISD::SREM, MVT::i128, Custom);
1573 setOperationAction(ISD::UREM, MVT::i128, Custom);
1574 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1575 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1578 // We have target-specific dag combine patterns for the following nodes:
1579 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1580 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1581 setTargetDAGCombine(ISD::VSELECT);
1582 setTargetDAGCombine(ISD::SELECT);
1583 setTargetDAGCombine(ISD::SHL);
1584 setTargetDAGCombine(ISD::SRA);
1585 setTargetDAGCombine(ISD::SRL);
1586 setTargetDAGCombine(ISD::OR);
1587 setTargetDAGCombine(ISD::AND);
1588 setTargetDAGCombine(ISD::ADD);
1589 setTargetDAGCombine(ISD::FADD);
1590 setTargetDAGCombine(ISD::FSUB);
1591 setTargetDAGCombine(ISD::FMA);
1592 setTargetDAGCombine(ISD::SUB);
1593 setTargetDAGCombine(ISD::LOAD);
1594 setTargetDAGCombine(ISD::STORE);
1595 setTargetDAGCombine(ISD::ZERO_EXTEND);
1596 setTargetDAGCombine(ISD::ANY_EXTEND);
1597 setTargetDAGCombine(ISD::SIGN_EXTEND);
1598 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1599 setTargetDAGCombine(ISD::TRUNCATE);
1600 setTargetDAGCombine(ISD::SINT_TO_FP);
1601 setTargetDAGCombine(ISD::SETCC);
1602 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1603 setTargetDAGCombine(ISD::BUILD_VECTOR);
1604 if (Subtarget->is64Bit())
1605 setTargetDAGCombine(ISD::MUL);
1606 setTargetDAGCombine(ISD::XOR);
1608 computeRegisterProperties();
1610 // On Darwin, -Os means optimize for size without hurting performance,
1611 // do not reduce the limit.
1612 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1613 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1614 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1615 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1616 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1617 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1618 setPrefLoopAlignment(4); // 2^4 bytes.
1620 // Predictable cmov don't hurt on atom because it's in-order.
1621 PredictableSelectIsExpensive = !Subtarget->isAtom();
1623 setPrefFunctionAlignment(4); // 2^4 bytes.
1626 TargetLoweringBase::LegalizeTypeAction
1627 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1628 if (ExperimentalVectorWideningLegalization &&
1629 VT.getVectorNumElements() != 1 &&
1630 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1631 return TypeWidenVector;
1633 return TargetLoweringBase::getPreferredVectorAction(VT);
1636 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1638 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1640 if (Subtarget->hasAVX512())
1641 switch(VT.getVectorNumElements()) {
1642 case 8: return MVT::v8i1;
1643 case 16: return MVT::v16i1;
1646 return VT.changeVectorElementTypeToInteger();
1649 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1650 /// the desired ByVal argument alignment.
1651 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1654 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1655 if (VTy->getBitWidth() == 128)
1657 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1658 unsigned EltAlign = 0;
1659 getMaxByValAlign(ATy->getElementType(), EltAlign);
1660 if (EltAlign > MaxAlign)
1661 MaxAlign = EltAlign;
1662 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1663 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1664 unsigned EltAlign = 0;
1665 getMaxByValAlign(STy->getElementType(i), EltAlign);
1666 if (EltAlign > MaxAlign)
1667 MaxAlign = EltAlign;
1674 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1675 /// function arguments in the caller parameter area. For X86, aggregates
1676 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1677 /// are at 4-byte boundaries.
1678 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1679 if (Subtarget->is64Bit()) {
1680 // Max of 8 and alignment of type.
1681 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1688 if (Subtarget->hasSSE1())
1689 getMaxByValAlign(Ty, Align);
1693 /// getOptimalMemOpType - Returns the target specific optimal type for load
1694 /// and store operations as a result of memset, memcpy, and memmove
1695 /// lowering. If DstAlign is zero that means it's safe to destination
1696 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1697 /// means there isn't a need to check it against alignment requirement,
1698 /// probably because the source does not need to be loaded. If 'IsMemset' is
1699 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1700 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1701 /// source is constant so it does not need to be loaded.
1702 /// It returns EVT::Other if the type should be determined using generic
1703 /// target-independent logic.
1705 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1706 unsigned DstAlign, unsigned SrcAlign,
1707 bool IsMemset, bool ZeroMemset,
1709 MachineFunction &MF) const {
1710 const Function *F = MF.getFunction();
1711 if ((!IsMemset || ZeroMemset) &&
1712 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1713 Attribute::NoImplicitFloat)) {
1715 (Subtarget->isUnalignedMemAccessFast() ||
1716 ((DstAlign == 0 || DstAlign >= 16) &&
1717 (SrcAlign == 0 || SrcAlign >= 16)))) {
1719 if (Subtarget->hasInt256())
1721 if (Subtarget->hasFp256())
1724 if (Subtarget->hasSSE2())
1726 if (Subtarget->hasSSE1())
1728 } else if (!MemcpyStrSrc && Size >= 8 &&
1729 !Subtarget->is64Bit() &&
1730 Subtarget->hasSSE2()) {
1731 // Do not use f64 to lower memcpy if source is string constant. It's
1732 // better to use i32 to avoid the loads.
1736 if (Subtarget->is64Bit() && Size >= 8)
1741 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1743 return X86ScalarSSEf32;
1744 else if (VT == MVT::f64)
1745 return X86ScalarSSEf64;
1750 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
1754 *Fast = Subtarget->isUnalignedMemAccessFast();
1758 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1759 /// current function. The returned value is a member of the
1760 /// MachineJumpTableInfo::JTEntryKind enum.
1761 unsigned X86TargetLowering::getJumpTableEncoding() const {
1762 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1764 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1765 Subtarget->isPICStyleGOT())
1766 return MachineJumpTableInfo::EK_Custom32;
1768 // Otherwise, use the normal jump table encoding heuristics.
1769 return TargetLowering::getJumpTableEncoding();
1773 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1774 const MachineBasicBlock *MBB,
1775 unsigned uid,MCContext &Ctx) const{
1776 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1777 Subtarget->isPICStyleGOT());
1778 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1780 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1781 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1784 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1786 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1787 SelectionDAG &DAG) const {
1788 if (!Subtarget->is64Bit())
1789 // This doesn't have SDLoc associated with it, but is not really the
1790 // same as a Register.
1791 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1795 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1796 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1798 const MCExpr *X86TargetLowering::
1799 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1800 MCContext &Ctx) const {
1801 // X86-64 uses RIP relative addressing based on the jump table label.
1802 if (Subtarget->isPICStyleRIPRel())
1803 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1805 // Otherwise, the reference is relative to the PIC base.
1806 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1809 // FIXME: Why this routine is here? Move to RegInfo!
1810 std::pair<const TargetRegisterClass*, uint8_t>
1811 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1812 const TargetRegisterClass *RRC = nullptr;
1814 switch (VT.SimpleTy) {
1816 return TargetLowering::findRepresentativeClass(VT);
1817 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1818 RRC = Subtarget->is64Bit() ?
1819 (const TargetRegisterClass*)&X86::GR64RegClass :
1820 (const TargetRegisterClass*)&X86::GR32RegClass;
1823 RRC = &X86::VR64RegClass;
1825 case MVT::f32: case MVT::f64:
1826 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1827 case MVT::v4f32: case MVT::v2f64:
1828 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1830 RRC = &X86::VR128RegClass;
1833 return std::make_pair(RRC, Cost);
1836 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1837 unsigned &Offset) const {
1838 if (!Subtarget->isTargetLinux())
1841 if (Subtarget->is64Bit()) {
1842 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1844 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1856 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1857 unsigned DestAS) const {
1858 assert(SrcAS != DestAS && "Expected different address spaces!");
1860 return SrcAS < 256 && DestAS < 256;
1863 //===----------------------------------------------------------------------===//
1864 // Return Value Calling Convention Implementation
1865 //===----------------------------------------------------------------------===//
1867 #include "X86GenCallingConv.inc"
1870 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1871 MachineFunction &MF, bool isVarArg,
1872 const SmallVectorImpl<ISD::OutputArg> &Outs,
1873 LLVMContext &Context) const {
1874 SmallVector<CCValAssign, 16> RVLocs;
1875 CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
1877 return CCInfo.CheckReturn(Outs, RetCC_X86);
1880 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1881 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1886 X86TargetLowering::LowerReturn(SDValue Chain,
1887 CallingConv::ID CallConv, bool isVarArg,
1888 const SmallVectorImpl<ISD::OutputArg> &Outs,
1889 const SmallVectorImpl<SDValue> &OutVals,
1890 SDLoc dl, SelectionDAG &DAG) const {
1891 MachineFunction &MF = DAG.getMachineFunction();
1892 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1894 SmallVector<CCValAssign, 16> RVLocs;
1895 CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
1896 RVLocs, *DAG.getContext());
1897 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1900 SmallVector<SDValue, 6> RetOps;
1901 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1902 // Operand #1 = Bytes To Pop
1903 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1906 // Copy the result values into the output registers.
1907 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1908 CCValAssign &VA = RVLocs[i];
1909 assert(VA.isRegLoc() && "Can only return in registers!");
1910 SDValue ValToCopy = OutVals[i];
1911 EVT ValVT = ValToCopy.getValueType();
1913 // Promote values to the appropriate types
1914 if (VA.getLocInfo() == CCValAssign::SExt)
1915 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1916 else if (VA.getLocInfo() == CCValAssign::ZExt)
1917 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1918 else if (VA.getLocInfo() == CCValAssign::AExt)
1919 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1920 else if (VA.getLocInfo() == CCValAssign::BCvt)
1921 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1923 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1924 "Unexpected FP-extend for return value.");
1926 // If this is x86-64, and we disabled SSE, we can't return FP values,
1927 // or SSE or MMX vectors.
1928 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1929 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1930 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1931 report_fatal_error("SSE register return with SSE disabled");
1933 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1934 // llvm-gcc has never done it right and no one has noticed, so this
1935 // should be OK for now.
1936 if (ValVT == MVT::f64 &&
1937 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1938 report_fatal_error("SSE2 register return with SSE2 disabled");
1940 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1941 // the RET instruction and handled by the FP Stackifier.
1942 if (VA.getLocReg() == X86::ST0 ||
1943 VA.getLocReg() == X86::ST1) {
1944 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1945 // change the value to the FP stack register class.
1946 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1947 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1948 RetOps.push_back(ValToCopy);
1949 // Don't emit a copytoreg.
1953 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1954 // which is returned in RAX / RDX.
1955 if (Subtarget->is64Bit()) {
1956 if (ValVT == MVT::x86mmx) {
1957 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1958 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1959 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1961 // If we don't have SSE2 available, convert to v4f32 so the generated
1962 // register is legal.
1963 if (!Subtarget->hasSSE2())
1964 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1969 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1970 Flag = Chain.getValue(1);
1971 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1974 // The x86-64 ABIs require that for returning structs by value we copy
1975 // the sret argument into %rax/%eax (depending on ABI) for the return.
1976 // Win32 requires us to put the sret argument to %eax as well.
1977 // We saved the argument into a virtual register in the entry block,
1978 // so now we copy the value out and into %rax/%eax.
1979 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1980 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
1981 MachineFunction &MF = DAG.getMachineFunction();
1982 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1983 unsigned Reg = FuncInfo->getSRetReturnReg();
1985 "SRetReturnReg should have been set in LowerFormalArguments().");
1986 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1989 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1990 X86::RAX : X86::EAX;
1991 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1992 Flag = Chain.getValue(1);
1994 // RAX/EAX now acts like a return value.
1995 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1998 RetOps[0] = Chain; // Update chain.
2000 // Add the flag if we have it.
2002 RetOps.push_back(Flag);
2004 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2007 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2008 if (N->getNumValues() != 1)
2010 if (!N->hasNUsesOfValue(1, 0))
2013 SDValue TCChain = Chain;
2014 SDNode *Copy = *N->use_begin();
2015 if (Copy->getOpcode() == ISD::CopyToReg) {
2016 // If the copy has a glue operand, we conservatively assume it isn't safe to
2017 // perform a tail call.
2018 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2020 TCChain = Copy->getOperand(0);
2021 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2024 bool HasRet = false;
2025 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2027 if (UI->getOpcode() != X86ISD::RET_FLAG)
2040 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
2041 ISD::NodeType ExtendKind) const {
2043 // TODO: Is this also valid on 32-bit?
2044 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2045 ReturnMVT = MVT::i8;
2047 ReturnMVT = MVT::i32;
2049 MVT MinVT = getRegisterType(ReturnMVT);
2050 return VT.bitsLT(MinVT) ? MinVT : VT;
2053 /// LowerCallResult - Lower the result values of a call into the
2054 /// appropriate copies out of appropriate physical registers.
2057 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2058 CallingConv::ID CallConv, bool isVarArg,
2059 const SmallVectorImpl<ISD::InputArg> &Ins,
2060 SDLoc dl, SelectionDAG &DAG,
2061 SmallVectorImpl<SDValue> &InVals) const {
2063 // Assign locations to each value returned by this call.
2064 SmallVector<CCValAssign, 16> RVLocs;
2065 bool Is64Bit = Subtarget->is64Bit();
2066 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2067 DAG.getTarget(), RVLocs, *DAG.getContext());
2068 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2070 // Copy all of the result registers out of their specified physreg.
2071 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2072 CCValAssign &VA = RVLocs[i];
2073 EVT CopyVT = VA.getValVT();
2075 // If this is x86-64, and we disabled SSE, we can't return FP values
2076 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2077 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2078 report_fatal_error("SSE register return with SSE disabled");
2083 // If this is a call to a function that returns an fp value on the floating
2084 // point stack, we must guarantee the value is popped from the stack, so
2085 // a CopyFromReg is not good enough - the copy instruction may be eliminated
2086 // if the return value is not used. We use the FpPOP_RETVAL instruction
2088 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
2089 // If we prefer to use the value in xmm registers, copy it out as f80 and
2090 // use a truncate to move it from fp stack reg to xmm reg.
2091 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2092 SDValue Ops[] = { Chain, InFlag };
2093 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2094 MVT::Other, MVT::Glue, Ops), 1);
2095 Val = Chain.getValue(0);
2097 // Round the f80 to the right size, which also moves it to the appropriate
2099 if (CopyVT != VA.getValVT())
2100 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2101 // This truncation won't change the value.
2102 DAG.getIntPtrConstant(1));
2104 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2105 CopyVT, InFlag).getValue(1);
2106 Val = Chain.getValue(0);
2108 InFlag = Chain.getValue(2);
2109 InVals.push_back(Val);
2115 //===----------------------------------------------------------------------===//
2116 // C & StdCall & Fast Calling Convention implementation
2117 //===----------------------------------------------------------------------===//
2118 // StdCall calling convention seems to be standard for many Windows' API
2119 // routines and around. It differs from C calling convention just a little:
2120 // callee should clean up the stack, not caller. Symbols should be also
2121 // decorated in some fancy way :) It doesn't support any vector arguments.
2122 // For info on fast calling convention see Fast Calling Convention (tail call)
2123 // implementation LowerX86_32FastCCCallTo.
2125 /// CallIsStructReturn - Determines whether a call uses struct return
2127 enum StructReturnType {
2132 static StructReturnType
2133 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2135 return NotStructReturn;
2137 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2138 if (!Flags.isSRet())
2139 return NotStructReturn;
2140 if (Flags.isInReg())
2141 return RegStructReturn;
2142 return StackStructReturn;
2145 /// ArgsAreStructReturn - Determines whether a function uses struct
2146 /// return semantics.
2147 static StructReturnType
2148 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2150 return NotStructReturn;
2152 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2153 if (!Flags.isSRet())
2154 return NotStructReturn;
2155 if (Flags.isInReg())
2156 return RegStructReturn;
2157 return StackStructReturn;
2160 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2161 /// by "Src" to address "Dst" with size and alignment information specified by
2162 /// the specific parameter attribute. The copy will be passed as a byval
2163 /// function parameter.
2165 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2166 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2168 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2170 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2171 /*isVolatile*/false, /*AlwaysInline=*/true,
2172 MachinePointerInfo(), MachinePointerInfo());
2175 /// IsTailCallConvention - Return true if the calling convention is one that
2176 /// supports tail call optimization.
2177 static bool IsTailCallConvention(CallingConv::ID CC) {
2178 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2179 CC == CallingConv::HiPE);
2182 /// \brief Return true if the calling convention is a C calling convention.
2183 static bool IsCCallConvention(CallingConv::ID CC) {
2184 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2185 CC == CallingConv::X86_64_SysV);
2188 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2189 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2193 CallingConv::ID CalleeCC = CS.getCallingConv();
2194 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2200 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2201 /// a tailcall target by changing its ABI.
2202 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2203 bool GuaranteedTailCallOpt) {
2204 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2208 X86TargetLowering::LowerMemArgument(SDValue Chain,
2209 CallingConv::ID CallConv,
2210 const SmallVectorImpl<ISD::InputArg> &Ins,
2211 SDLoc dl, SelectionDAG &DAG,
2212 const CCValAssign &VA,
2213 MachineFrameInfo *MFI,
2215 // Create the nodes corresponding to a load from this parameter slot.
2216 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2217 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2218 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2219 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2222 // If value is passed by pointer we have address passed instead of the value
2224 if (VA.getLocInfo() == CCValAssign::Indirect)
2225 ValVT = VA.getLocVT();
2227 ValVT = VA.getValVT();
2229 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2230 // changed with more analysis.
2231 // In case of tail call optimization mark all arguments mutable. Since they
2232 // could be overwritten by lowering of arguments in case of a tail call.
2233 if (Flags.isByVal()) {
2234 unsigned Bytes = Flags.getByValSize();
2235 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2236 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2237 return DAG.getFrameIndex(FI, getPointerTy());
2239 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2240 VA.getLocMemOffset(), isImmutable);
2241 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2242 return DAG.getLoad(ValVT, dl, Chain, FIN,
2243 MachinePointerInfo::getFixedStack(FI),
2244 false, false, false, 0);
2249 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2250 CallingConv::ID CallConv,
2252 const SmallVectorImpl<ISD::InputArg> &Ins,
2255 SmallVectorImpl<SDValue> &InVals)
2257 MachineFunction &MF = DAG.getMachineFunction();
2258 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2260 const Function* Fn = MF.getFunction();
2261 if (Fn->hasExternalLinkage() &&
2262 Subtarget->isTargetCygMing() &&
2263 Fn->getName() == "main")
2264 FuncInfo->setForceFramePointer(true);
2266 MachineFrameInfo *MFI = MF.getFrameInfo();
2267 bool Is64Bit = Subtarget->is64Bit();
2268 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2270 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2271 "Var args not supported with calling convention fastcc, ghc or hipe");
2273 // Assign locations to all of the incoming arguments.
2274 SmallVector<CCValAssign, 16> ArgLocs;
2275 CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
2276 ArgLocs, *DAG.getContext());
2278 // Allocate shadow area for Win64
2280 CCInfo.AllocateStack(32, 8);
2282 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2284 unsigned LastVal = ~0U;
2286 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2287 CCValAssign &VA = ArgLocs[i];
2288 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2290 assert(VA.getValNo() != LastVal &&
2291 "Don't support value assigned to multiple locs yet");
2293 LastVal = VA.getValNo();
2295 if (VA.isRegLoc()) {
2296 EVT RegVT = VA.getLocVT();
2297 const TargetRegisterClass *RC;
2298 if (RegVT == MVT::i32)
2299 RC = &X86::GR32RegClass;
2300 else if (Is64Bit && RegVT == MVT::i64)
2301 RC = &X86::GR64RegClass;
2302 else if (RegVT == MVT::f32)
2303 RC = &X86::FR32RegClass;
2304 else if (RegVT == MVT::f64)
2305 RC = &X86::FR64RegClass;
2306 else if (RegVT.is512BitVector())
2307 RC = &X86::VR512RegClass;
2308 else if (RegVT.is256BitVector())
2309 RC = &X86::VR256RegClass;
2310 else if (RegVT.is128BitVector())
2311 RC = &X86::VR128RegClass;
2312 else if (RegVT == MVT::x86mmx)
2313 RC = &X86::VR64RegClass;
2314 else if (RegVT == MVT::i1)
2315 RC = &X86::VK1RegClass;
2316 else if (RegVT == MVT::v8i1)
2317 RC = &X86::VK8RegClass;
2318 else if (RegVT == MVT::v16i1)
2319 RC = &X86::VK16RegClass;
2320 else if (RegVT == MVT::v32i1)
2321 RC = &X86::VK32RegClass;
2322 else if (RegVT == MVT::v64i1)
2323 RC = &X86::VK64RegClass;
2325 llvm_unreachable("Unknown argument type!");
2327 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2328 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2330 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2331 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2333 if (VA.getLocInfo() == CCValAssign::SExt)
2334 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2335 DAG.getValueType(VA.getValVT()));
2336 else if (VA.getLocInfo() == CCValAssign::ZExt)
2337 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2338 DAG.getValueType(VA.getValVT()));
2339 else if (VA.getLocInfo() == CCValAssign::BCvt)
2340 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2342 if (VA.isExtInLoc()) {
2343 // Handle MMX values passed in XMM regs.
2344 if (RegVT.isVector())
2345 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2347 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2350 assert(VA.isMemLoc());
2351 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2354 // If value is passed via pointer - do a load.
2355 if (VA.getLocInfo() == CCValAssign::Indirect)
2356 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2357 MachinePointerInfo(), false, false, false, 0);
2359 InVals.push_back(ArgValue);
2362 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2363 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2364 // The x86-64 ABIs require that for returning structs by value we copy
2365 // the sret argument into %rax/%eax (depending on ABI) for the return.
2366 // Win32 requires us to put the sret argument to %eax as well.
2367 // Save the argument into a virtual register so that we can access it
2368 // from the return points.
2369 if (Ins[i].Flags.isSRet()) {
2370 unsigned Reg = FuncInfo->getSRetReturnReg();
2372 MVT PtrTy = getPointerTy();
2373 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2374 FuncInfo->setSRetReturnReg(Reg);
2376 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2377 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2383 unsigned StackSize = CCInfo.getNextStackOffset();
2384 // Align stack specially for tail calls.
2385 if (FuncIsMadeTailCallSafe(CallConv,
2386 MF.getTarget().Options.GuaranteedTailCallOpt))
2387 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2389 // If the function takes variable number of arguments, make a frame index for
2390 // the start of the first vararg value... for expansion of llvm.va_start.
2392 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2393 CallConv != CallingConv::X86_ThisCall)) {
2394 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2397 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2399 // FIXME: We should really autogenerate these arrays
2400 static const MCPhysReg GPR64ArgRegsWin64[] = {
2401 X86::RCX, X86::RDX, X86::R8, X86::R9
2403 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2404 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2406 static const MCPhysReg XMMArgRegs64Bit[] = {
2407 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2408 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2410 const MCPhysReg *GPR64ArgRegs;
2411 unsigned NumXMMRegs = 0;
2414 // The XMM registers which might contain var arg parameters are shadowed
2415 // in their paired GPR. So we only need to save the GPR to their home
2417 TotalNumIntRegs = 4;
2418 GPR64ArgRegs = GPR64ArgRegsWin64;
2420 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2421 GPR64ArgRegs = GPR64ArgRegs64Bit;
2423 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2426 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2429 bool NoImplicitFloatOps = Fn->getAttributes().
2430 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2431 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2432 "SSE register cannot be used when SSE is disabled!");
2433 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2434 NoImplicitFloatOps) &&
2435 "SSE register cannot be used when SSE is disabled!");
2436 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2437 !Subtarget->hasSSE1())
2438 // Kernel mode asks for SSE to be disabled, so don't push them
2440 TotalNumXMMRegs = 0;
2443 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
2444 // Get to the caller-allocated home save location. Add 8 to account
2445 // for the return address.
2446 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2447 FuncInfo->setRegSaveFrameIndex(
2448 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2449 // Fixup to set vararg frame on shadow area (4 x i64).
2451 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2453 // For X86-64, if there are vararg parameters that are passed via
2454 // registers, then we must store them to their spots on the stack so
2455 // they may be loaded by deferencing the result of va_next.
2456 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2457 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2458 FuncInfo->setRegSaveFrameIndex(
2459 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2463 // Store the integer parameter registers.
2464 SmallVector<SDValue, 8> MemOps;
2465 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2467 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2468 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2469 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2470 DAG.getIntPtrConstant(Offset));
2471 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2472 &X86::GR64RegClass);
2473 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2475 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2476 MachinePointerInfo::getFixedStack(
2477 FuncInfo->getRegSaveFrameIndex(), Offset),
2479 MemOps.push_back(Store);
2483 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2484 // Now store the XMM (fp + vector) parameter registers.
2485 SmallVector<SDValue, 11> SaveXMMOps;
2486 SaveXMMOps.push_back(Chain);
2488 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2489 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2490 SaveXMMOps.push_back(ALVal);
2492 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2493 FuncInfo->getRegSaveFrameIndex()));
2494 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2495 FuncInfo->getVarArgsFPOffset()));
2497 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2498 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2499 &X86::VR128RegClass);
2500 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2501 SaveXMMOps.push_back(Val);
2503 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2504 MVT::Other, SaveXMMOps));
2507 if (!MemOps.empty())
2508 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2512 // Some CCs need callee pop.
2513 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2514 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2515 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2517 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2518 // If this is an sret function, the return should pop the hidden pointer.
2519 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2520 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2521 argsAreStructReturn(Ins) == StackStructReturn)
2522 FuncInfo->setBytesToPopOnReturn(4);
2526 // RegSaveFrameIndex is X86-64 only.
2527 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2528 if (CallConv == CallingConv::X86_FastCall ||
2529 CallConv == CallingConv::X86_ThisCall)
2530 // fastcc functions can't have varargs.
2531 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2534 FuncInfo->setArgumentStackSize(StackSize);
2540 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2541 SDValue StackPtr, SDValue Arg,
2542 SDLoc dl, SelectionDAG &DAG,
2543 const CCValAssign &VA,
2544 ISD::ArgFlagsTy Flags) const {
2545 unsigned LocMemOffset = VA.getLocMemOffset();
2546 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2547 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2548 if (Flags.isByVal())
2549 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2551 return DAG.getStore(Chain, dl, Arg, PtrOff,
2552 MachinePointerInfo::getStack(LocMemOffset),
2556 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2557 /// optimization is performed and it is required.
2559 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2560 SDValue &OutRetAddr, SDValue Chain,
2561 bool IsTailCall, bool Is64Bit,
2562 int FPDiff, SDLoc dl) const {
2563 // Adjust the Return address stack slot.
2564 EVT VT = getPointerTy();
2565 OutRetAddr = getReturnAddressFrameIndex(DAG);
2567 // Load the "old" Return address.
2568 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2569 false, false, false, 0);
2570 return SDValue(OutRetAddr.getNode(), 1);
2573 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2574 /// optimization is performed and it is required (FPDiff!=0).
2575 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2576 SDValue Chain, SDValue RetAddrFrIdx,
2577 EVT PtrVT, unsigned SlotSize,
2578 int FPDiff, SDLoc dl) {
2579 // Store the return address to the appropriate stack slot.
2580 if (!FPDiff) return Chain;
2581 // Calculate the new stack slot for the return address.
2582 int NewReturnAddrFI =
2583 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2585 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2586 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2587 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2593 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2594 SmallVectorImpl<SDValue> &InVals) const {
2595 SelectionDAG &DAG = CLI.DAG;
2597 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2598 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2599 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2600 SDValue Chain = CLI.Chain;
2601 SDValue Callee = CLI.Callee;
2602 CallingConv::ID CallConv = CLI.CallConv;
2603 bool &isTailCall = CLI.IsTailCall;
2604 bool isVarArg = CLI.IsVarArg;
2606 MachineFunction &MF = DAG.getMachineFunction();
2607 bool Is64Bit = Subtarget->is64Bit();
2608 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2609 StructReturnType SR = callIsStructReturn(Outs);
2610 bool IsSibcall = false;
2612 if (MF.getTarget().Options.DisableTailCalls)
2615 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2617 // Force this to be a tail call. The verifier rules are enough to ensure
2618 // that we can lower this successfully without moving the return address
2621 } else if (isTailCall) {
2622 // Check if it's really possible to do a tail call.
2623 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2624 isVarArg, SR != NotStructReturn,
2625 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2626 Outs, OutVals, Ins, DAG);
2628 // Sibcalls are automatically detected tailcalls which do not require
2630 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2637 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2638 "Var args not supported with calling convention fastcc, ghc or hipe");
2640 // Analyze operands of the call, assigning locations to each operand.
2641 SmallVector<CCValAssign, 16> ArgLocs;
2642 CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
2643 ArgLocs, *DAG.getContext());
2645 // Allocate shadow area for Win64
2647 CCInfo.AllocateStack(32, 8);
2649 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2651 // Get a count of how many bytes are to be pushed on the stack.
2652 unsigned NumBytes = CCInfo.getNextStackOffset();
2654 // This is a sibcall. The memory operands are available in caller's
2655 // own caller's stack.
2657 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2658 IsTailCallConvention(CallConv))
2659 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2662 if (isTailCall && !IsSibcall && !IsMustTail) {
2663 // Lower arguments at fp - stackoffset + fpdiff.
2664 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2665 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2667 FPDiff = NumBytesCallerPushed - NumBytes;
2669 // Set the delta of movement of the returnaddr stackslot.
2670 // But only set if delta is greater than previous delta.
2671 if (FPDiff < X86Info->getTCReturnAddrDelta())
2672 X86Info->setTCReturnAddrDelta(FPDiff);
2675 unsigned NumBytesToPush = NumBytes;
2676 unsigned NumBytesToPop = NumBytes;
2678 // If we have an inalloca argument, all stack space has already been allocated
2679 // for us and be right at the top of the stack. We don't support multiple
2680 // arguments passed in memory when using inalloca.
2681 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2683 assert(ArgLocs.back().getLocMemOffset() == 0 &&
2684 "an inalloca argument must be the only memory argument");
2688 Chain = DAG.getCALLSEQ_START(
2689 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2691 SDValue RetAddrFrIdx;
2692 // Load return address for tail calls.
2693 if (isTailCall && FPDiff)
2694 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2695 Is64Bit, FPDiff, dl);
2697 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2698 SmallVector<SDValue, 8> MemOpChains;
2701 // Walk the register/memloc assignments, inserting copies/loads. In the case
2702 // of tail call optimization arguments are handle later.
2703 const X86RegisterInfo *RegInfo =
2704 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
2705 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2706 // Skip inalloca arguments, they have already been written.
2707 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2708 if (Flags.isInAlloca())
2711 CCValAssign &VA = ArgLocs[i];
2712 EVT RegVT = VA.getLocVT();
2713 SDValue Arg = OutVals[i];
2714 bool isByVal = Flags.isByVal();
2716 // Promote the value if needed.
2717 switch (VA.getLocInfo()) {
2718 default: llvm_unreachable("Unknown loc info!");
2719 case CCValAssign::Full: break;
2720 case CCValAssign::SExt:
2721 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2723 case CCValAssign::ZExt:
2724 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2726 case CCValAssign::AExt:
2727 if (RegVT.is128BitVector()) {
2728 // Special case: passing MMX values in XMM registers.
2729 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2730 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2731 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2733 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2735 case CCValAssign::BCvt:
2736 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2738 case CCValAssign::Indirect: {
2739 // Store the argument.
2740 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2741 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2742 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2743 MachinePointerInfo::getFixedStack(FI),
2750 if (VA.isRegLoc()) {
2751 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2752 if (isVarArg && IsWin64) {
2753 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2754 // shadow reg if callee is a varargs function.
2755 unsigned ShadowReg = 0;
2756 switch (VA.getLocReg()) {
2757 case X86::XMM0: ShadowReg = X86::RCX; break;
2758 case X86::XMM1: ShadowReg = X86::RDX; break;
2759 case X86::XMM2: ShadowReg = X86::R8; break;
2760 case X86::XMM3: ShadowReg = X86::R9; break;
2763 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2765 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2766 assert(VA.isMemLoc());
2767 if (!StackPtr.getNode())
2768 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2770 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2771 dl, DAG, VA, Flags));
2775 if (!MemOpChains.empty())
2776 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2778 if (Subtarget->isPICStyleGOT()) {
2779 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2782 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2783 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2785 // If we are tail calling and generating PIC/GOT style code load the
2786 // address of the callee into ECX. The value in ecx is used as target of
2787 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2788 // for tail calls on PIC/GOT architectures. Normally we would just put the
2789 // address of GOT into ebx and then call target@PLT. But for tail calls
2790 // ebx would be restored (since ebx is callee saved) before jumping to the
2793 // Note: The actual moving to ECX is done further down.
2794 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2795 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2796 !G->getGlobal()->hasProtectedVisibility())
2797 Callee = LowerGlobalAddress(Callee, DAG);
2798 else if (isa<ExternalSymbolSDNode>(Callee))
2799 Callee = LowerExternalSymbol(Callee, DAG);
2803 if (Is64Bit && isVarArg && !IsWin64) {
2804 // From AMD64 ABI document:
2805 // For calls that may call functions that use varargs or stdargs
2806 // (prototype-less calls or calls to functions containing ellipsis (...) in
2807 // the declaration) %al is used as hidden argument to specify the number
2808 // of SSE registers used. The contents of %al do not need to match exactly
2809 // the number of registers, but must be an ubound on the number of SSE
2810 // registers used and is in the range 0 - 8 inclusive.
2812 // Count the number of XMM registers allocated.
2813 static const MCPhysReg XMMArgRegs[] = {
2814 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2815 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2817 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2818 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2819 && "SSE registers cannot be used when SSE is disabled");
2821 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2822 DAG.getConstant(NumXMMRegs, MVT::i8)));
2825 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2826 // don't need this because the eligibility check rejects calls that require
2827 // shuffling arguments passed in memory.
2828 if (!IsSibcall && isTailCall) {
2829 // Force all the incoming stack arguments to be loaded from the stack
2830 // before any new outgoing arguments are stored to the stack, because the
2831 // outgoing stack slots may alias the incoming argument stack slots, and
2832 // the alias isn't otherwise explicit. This is slightly more conservative
2833 // than necessary, because it means that each store effectively depends
2834 // on every argument instead of just those arguments it would clobber.
2835 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2837 SmallVector<SDValue, 8> MemOpChains2;
2840 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2841 CCValAssign &VA = ArgLocs[i];
2844 assert(VA.isMemLoc());
2845 SDValue Arg = OutVals[i];
2846 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2847 // Skip inalloca arguments. They don't require any work.
2848 if (Flags.isInAlloca())
2850 // Create frame index.
2851 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2852 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2853 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2854 FIN = DAG.getFrameIndex(FI, getPointerTy());
2856 if (Flags.isByVal()) {
2857 // Copy relative to framepointer.
2858 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2859 if (!StackPtr.getNode())
2860 StackPtr = DAG.getCopyFromReg(Chain, dl,
2861 RegInfo->getStackRegister(),
2863 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2865 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2869 // Store relative to framepointer.
2870 MemOpChains2.push_back(
2871 DAG.getStore(ArgChain, dl, Arg, FIN,
2872 MachinePointerInfo::getFixedStack(FI),
2877 if (!MemOpChains2.empty())
2878 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2880 // Store the return address to the appropriate stack slot.
2881 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2882 getPointerTy(), RegInfo->getSlotSize(),
2886 // Build a sequence of copy-to-reg nodes chained together with token chain
2887 // and flag operands which copy the outgoing args into registers.
2889 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2890 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2891 RegsToPass[i].second, InFlag);
2892 InFlag = Chain.getValue(1);
2895 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2896 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2897 // In the 64-bit large code model, we have to make all calls
2898 // through a register, since the call instruction's 32-bit
2899 // pc-relative offset may not be large enough to hold the whole
2901 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2902 // If the callee is a GlobalAddress node (quite common, every direct call
2903 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2906 // We should use extra load for direct calls to dllimported functions in
2908 const GlobalValue *GV = G->getGlobal();
2909 if (!GV->hasDLLImportStorageClass()) {
2910 unsigned char OpFlags = 0;
2911 bool ExtraLoad = false;
2912 unsigned WrapperKind = ISD::DELETED_NODE;
2914 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2915 // external symbols most go through the PLT in PIC mode. If the symbol
2916 // has hidden or protected visibility, or if it is static or local, then
2917 // we don't need to use the PLT - we can directly call it.
2918 if (Subtarget->isTargetELF() &&
2919 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
2920 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2921 OpFlags = X86II::MO_PLT;
2922 } else if (Subtarget->isPICStyleStubAny() &&
2923 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2924 (!Subtarget->getTargetTriple().isMacOSX() ||
2925 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2926 // PC-relative references to external symbols should go through $stub,
2927 // unless we're building with the leopard linker or later, which
2928 // automatically synthesizes these stubs.
2929 OpFlags = X86II::MO_DARWIN_STUB;
2930 } else if (Subtarget->isPICStyleRIPRel() &&
2931 isa<Function>(GV) &&
2932 cast<Function>(GV)->getAttributes().
2933 hasAttribute(AttributeSet::FunctionIndex,
2934 Attribute::NonLazyBind)) {
2935 // If the function is marked as non-lazy, generate an indirect call
2936 // which loads from the GOT directly. This avoids runtime overhead
2937 // at the cost of eager binding (and one extra byte of encoding).
2938 OpFlags = X86II::MO_GOTPCREL;
2939 WrapperKind = X86ISD::WrapperRIP;
2943 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2944 G->getOffset(), OpFlags);
2946 // Add a wrapper if needed.
2947 if (WrapperKind != ISD::DELETED_NODE)
2948 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2949 // Add extra indirection if needed.
2951 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2952 MachinePointerInfo::getGOT(),
2953 false, false, false, 0);
2955 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2956 unsigned char OpFlags = 0;
2958 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2959 // external symbols should go through the PLT.
2960 if (Subtarget->isTargetELF() &&
2961 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
2962 OpFlags = X86II::MO_PLT;
2963 } else if (Subtarget->isPICStyleStubAny() &&
2964 (!Subtarget->getTargetTriple().isMacOSX() ||
2965 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2966 // PC-relative references to external symbols should go through $stub,
2967 // unless we're building with the leopard linker or later, which
2968 // automatically synthesizes these stubs.
2969 OpFlags = X86II::MO_DARWIN_STUB;
2972 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2976 // Returns a chain & a flag for retval copy to use.
2977 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2978 SmallVector<SDValue, 8> Ops;
2980 if (!IsSibcall && isTailCall) {
2981 Chain = DAG.getCALLSEQ_END(Chain,
2982 DAG.getIntPtrConstant(NumBytesToPop, true),
2983 DAG.getIntPtrConstant(0, true), InFlag, dl);
2984 InFlag = Chain.getValue(1);
2987 Ops.push_back(Chain);
2988 Ops.push_back(Callee);
2991 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2993 // Add argument registers to the end of the list so that they are known live
2995 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2996 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2997 RegsToPass[i].second.getValueType()));
2999 // Add a register mask operand representing the call-preserved registers.
3000 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3001 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3002 assert(Mask && "Missing call preserved mask for calling convention");
3003 Ops.push_back(DAG.getRegisterMask(Mask));
3005 if (InFlag.getNode())
3006 Ops.push_back(InFlag);
3010 //// If this is the first return lowered for this function, add the regs
3011 //// to the liveout set for the function.
3012 // This isn't right, although it's probably harmless on x86; liveouts
3013 // should be computed from returns not tail calls. Consider a void
3014 // function making a tail call to a function returning int.
3015 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3018 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3019 InFlag = Chain.getValue(1);
3021 // Create the CALLSEQ_END node.
3022 unsigned NumBytesForCalleeToPop;
3023 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3024 DAG.getTarget().Options.GuaranteedTailCallOpt))
3025 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3026 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3027 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3028 SR == StackStructReturn)
3029 // If this is a call to a struct-return function, the callee
3030 // pops the hidden struct pointer, so we have to push it back.
3031 // This is common for Darwin/X86, Linux & Mingw32 targets.
3032 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3033 NumBytesForCalleeToPop = 4;
3035 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3037 // Returns a flag for retval copy to use.
3039 Chain = DAG.getCALLSEQ_END(Chain,
3040 DAG.getIntPtrConstant(NumBytesToPop, true),
3041 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3044 InFlag = Chain.getValue(1);
3047 // Handle result values, copying them out of physregs into vregs that we
3049 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3050 Ins, dl, DAG, InVals);
3053 //===----------------------------------------------------------------------===//
3054 // Fast Calling Convention (tail call) implementation
3055 //===----------------------------------------------------------------------===//
3057 // Like std call, callee cleans arguments, convention except that ECX is
3058 // reserved for storing the tail called function address. Only 2 registers are
3059 // free for argument passing (inreg). Tail call optimization is performed
3061 // * tailcallopt is enabled
3062 // * caller/callee are fastcc
3063 // On X86_64 architecture with GOT-style position independent code only local
3064 // (within module) calls are supported at the moment.
3065 // To keep the stack aligned according to platform abi the function
3066 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3067 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3068 // If a tail called function callee has more arguments than the caller the
3069 // caller needs to make sure that there is room to move the RETADDR to. This is
3070 // achieved by reserving an area the size of the argument delta right after the
3071 // original RETADDR, but before the saved framepointer or the spilled registers
3072 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3084 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3085 /// for a 16 byte align requirement.
3087 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3088 SelectionDAG& DAG) const {
3089 MachineFunction &MF = DAG.getMachineFunction();
3090 const TargetMachine &TM = MF.getTarget();
3091 const X86RegisterInfo *RegInfo =
3092 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
3093 const TargetFrameLowering &TFI = *TM.getFrameLowering();
3094 unsigned StackAlignment = TFI.getStackAlignment();
3095 uint64_t AlignMask = StackAlignment - 1;
3096 int64_t Offset = StackSize;
3097 unsigned SlotSize = RegInfo->getSlotSize();
3098 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3099 // Number smaller than 12 so just add the difference.
3100 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3102 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3103 Offset = ((~AlignMask) & Offset) + StackAlignment +
3104 (StackAlignment-SlotSize);
3109 /// MatchingStackOffset - Return true if the given stack call argument is
3110 /// already available in the same position (relatively) of the caller's
3111 /// incoming argument stack.
3113 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3114 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3115 const X86InstrInfo *TII) {
3116 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3118 if (Arg.getOpcode() == ISD::CopyFromReg) {
3119 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3120 if (!TargetRegisterInfo::isVirtualRegister(VR))
3122 MachineInstr *Def = MRI->getVRegDef(VR);
3125 if (!Flags.isByVal()) {
3126 if (!TII->isLoadFromStackSlot(Def, FI))
3129 unsigned Opcode = Def->getOpcode();
3130 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3131 Def->getOperand(1).isFI()) {
3132 FI = Def->getOperand(1).getIndex();
3133 Bytes = Flags.getByValSize();
3137 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3138 if (Flags.isByVal())
3139 // ByVal argument is passed in as a pointer but it's now being
3140 // dereferenced. e.g.
3141 // define @foo(%struct.X* %A) {
3142 // tail call @bar(%struct.X* byval %A)
3145 SDValue Ptr = Ld->getBasePtr();
3146 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3149 FI = FINode->getIndex();
3150 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3151 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3152 FI = FINode->getIndex();
3153 Bytes = Flags.getByValSize();
3157 assert(FI != INT_MAX);
3158 if (!MFI->isFixedObjectIndex(FI))
3160 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3163 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3164 /// for tail call optimization. Targets which want to do tail call
3165 /// optimization should implement this function.
3167 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3168 CallingConv::ID CalleeCC,
3170 bool isCalleeStructRet,
3171 bool isCallerStructRet,
3173 const SmallVectorImpl<ISD::OutputArg> &Outs,
3174 const SmallVectorImpl<SDValue> &OutVals,
3175 const SmallVectorImpl<ISD::InputArg> &Ins,
3176 SelectionDAG &DAG) const {
3177 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3180 // If -tailcallopt is specified, make fastcc functions tail-callable.
3181 const MachineFunction &MF = DAG.getMachineFunction();
3182 const Function *CallerF = MF.getFunction();
3184 // If the function return type is x86_fp80 and the callee return type is not,
3185 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3186 // perform a tailcall optimization here.
3187 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3190 CallingConv::ID CallerCC = CallerF->getCallingConv();
3191 bool CCMatch = CallerCC == CalleeCC;
3192 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3193 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3195 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3196 if (IsTailCallConvention(CalleeCC) && CCMatch)
3201 // Look for obvious safe cases to perform tail call optimization that do not
3202 // require ABI changes. This is what gcc calls sibcall.
3204 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3205 // emit a special epilogue.
3206 const X86RegisterInfo *RegInfo =
3207 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
3208 if (RegInfo->needsStackRealignment(MF))
3211 // Also avoid sibcall optimization if either caller or callee uses struct
3212 // return semantics.
3213 if (isCalleeStructRet || isCallerStructRet)
3216 // An stdcall/thiscall caller is expected to clean up its arguments; the
3217 // callee isn't going to do that.
3218 // FIXME: this is more restrictive than needed. We could produce a tailcall
3219 // when the stack adjustment matches. For example, with a thiscall that takes
3220 // only one argument.
3221 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3222 CallerCC == CallingConv::X86_ThisCall))
3225 // Do not sibcall optimize vararg calls unless all arguments are passed via
3227 if (isVarArg && !Outs.empty()) {
3229 // Optimizing for varargs on Win64 is unlikely to be safe without
3230 // additional testing.
3231 if (IsCalleeWin64 || IsCallerWin64)
3234 SmallVector<CCValAssign, 16> ArgLocs;
3235 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3236 DAG.getTarget(), ArgLocs, *DAG.getContext());
3238 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3239 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3240 if (!ArgLocs[i].isRegLoc())
3244 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3245 // stack. Therefore, if it's not used by the call it is not safe to optimize
3246 // this into a sibcall.
3247 bool Unused = false;
3248 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3255 SmallVector<CCValAssign, 16> RVLocs;
3256 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3257 DAG.getTarget(), RVLocs, *DAG.getContext());
3258 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3259 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3260 CCValAssign &VA = RVLocs[i];
3261 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3266 // If the calling conventions do not match, then we'd better make sure the
3267 // results are returned in the same way as what the caller expects.
3269 SmallVector<CCValAssign, 16> RVLocs1;
3270 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3271 DAG.getTarget(), RVLocs1, *DAG.getContext());
3272 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3274 SmallVector<CCValAssign, 16> RVLocs2;
3275 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3276 DAG.getTarget(), RVLocs2, *DAG.getContext());
3277 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3279 if (RVLocs1.size() != RVLocs2.size())
3281 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3282 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3284 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3286 if (RVLocs1[i].isRegLoc()) {
3287 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3290 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3296 // If the callee takes no arguments then go on to check the results of the
3298 if (!Outs.empty()) {
3299 // Check if stack adjustment is needed. For now, do not do this if any
3300 // argument is passed on the stack.
3301 SmallVector<CCValAssign, 16> ArgLocs;
3302 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3303 DAG.getTarget(), ArgLocs, *DAG.getContext());
3305 // Allocate shadow area for Win64
3307 CCInfo.AllocateStack(32, 8);
3309 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3310 if (CCInfo.getNextStackOffset()) {
3311 MachineFunction &MF = DAG.getMachineFunction();
3312 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3315 // Check if the arguments are already laid out in the right way as
3316 // the caller's fixed stack objects.
3317 MachineFrameInfo *MFI = MF.getFrameInfo();
3318 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3319 const X86InstrInfo *TII =
3320 static_cast<const X86InstrInfo *>(DAG.getTarget().getInstrInfo());
3321 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3322 CCValAssign &VA = ArgLocs[i];
3323 SDValue Arg = OutVals[i];
3324 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3325 if (VA.getLocInfo() == CCValAssign::Indirect)
3327 if (!VA.isRegLoc()) {
3328 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3335 // If the tailcall address may be in a register, then make sure it's
3336 // possible to register allocate for it. In 32-bit, the call address can
3337 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3338 // callee-saved registers are restored. These happen to be the same
3339 // registers used to pass 'inreg' arguments so watch out for those.
3340 if (!Subtarget->is64Bit() &&
3341 ((!isa<GlobalAddressSDNode>(Callee) &&
3342 !isa<ExternalSymbolSDNode>(Callee)) ||
3343 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3344 unsigned NumInRegs = 0;
3345 // In PIC we need an extra register to formulate the address computation
3347 unsigned MaxInRegs =
3348 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3350 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3351 CCValAssign &VA = ArgLocs[i];
3354 unsigned Reg = VA.getLocReg();
3357 case X86::EAX: case X86::EDX: case X86::ECX:
3358 if (++NumInRegs == MaxInRegs)
3370 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3371 const TargetLibraryInfo *libInfo) const {
3372 return X86::createFastISel(funcInfo, libInfo);
3375 //===----------------------------------------------------------------------===//
3376 // Other Lowering Hooks
3377 //===----------------------------------------------------------------------===//
3379 static bool MayFoldLoad(SDValue Op) {
3380 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3383 static bool MayFoldIntoStore(SDValue Op) {
3384 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3387 static bool isTargetShuffle(unsigned Opcode) {
3389 default: return false;
3390 case X86ISD::PSHUFD:
3391 case X86ISD::PSHUFHW:
3392 case X86ISD::PSHUFLW:
3394 case X86ISD::PALIGNR:
3395 case X86ISD::MOVLHPS:
3396 case X86ISD::MOVLHPD:
3397 case X86ISD::MOVHLPS:
3398 case X86ISD::MOVLPS:
3399 case X86ISD::MOVLPD:
3400 case X86ISD::MOVSHDUP:
3401 case X86ISD::MOVSLDUP:
3402 case X86ISD::MOVDDUP:
3405 case X86ISD::UNPCKL:
3406 case X86ISD::UNPCKH:
3407 case X86ISD::VPERMILP:
3408 case X86ISD::VPERM2X128:
3409 case X86ISD::VPERMI:
3414 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3415 SDValue V1, SelectionDAG &DAG) {
3417 default: llvm_unreachable("Unknown x86 shuffle node");
3418 case X86ISD::MOVSHDUP:
3419 case X86ISD::MOVSLDUP:
3420 case X86ISD::MOVDDUP:
3421 return DAG.getNode(Opc, dl, VT, V1);
3425 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3426 SDValue V1, unsigned TargetMask,
3427 SelectionDAG &DAG) {
3429 default: llvm_unreachable("Unknown x86 shuffle node");
3430 case X86ISD::PSHUFD:
3431 case X86ISD::PSHUFHW:
3432 case X86ISD::PSHUFLW:
3433 case X86ISD::VPERMILP:
3434 case X86ISD::VPERMI:
3435 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3439 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3440 SDValue V1, SDValue V2, unsigned TargetMask,
3441 SelectionDAG &DAG) {
3443 default: llvm_unreachable("Unknown x86 shuffle node");
3444 case X86ISD::PALIGNR:
3446 case X86ISD::VPERM2X128:
3447 return DAG.getNode(Opc, dl, VT, V1, V2,
3448 DAG.getConstant(TargetMask, MVT::i8));
3452 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3453 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3455 default: llvm_unreachable("Unknown x86 shuffle node");
3456 case X86ISD::MOVLHPS:
3457 case X86ISD::MOVLHPD:
3458 case X86ISD::MOVHLPS:
3459 case X86ISD::MOVLPS:
3460 case X86ISD::MOVLPD:
3463 case X86ISD::UNPCKL:
3464 case X86ISD::UNPCKH:
3465 return DAG.getNode(Opc, dl, VT, V1, V2);
3469 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3470 MachineFunction &MF = DAG.getMachineFunction();
3471 const X86RegisterInfo *RegInfo =
3472 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
3473 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3474 int ReturnAddrIndex = FuncInfo->getRAIndex();
3476 if (ReturnAddrIndex == 0) {
3477 // Set up a frame object for the return address.
3478 unsigned SlotSize = RegInfo->getSlotSize();
3479 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3482 FuncInfo->setRAIndex(ReturnAddrIndex);
3485 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3488 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3489 bool hasSymbolicDisplacement) {
3490 // Offset should fit into 32 bit immediate field.
3491 if (!isInt<32>(Offset))
3494 // If we don't have a symbolic displacement - we don't have any extra
3496 if (!hasSymbolicDisplacement)
3499 // FIXME: Some tweaks might be needed for medium code model.
3500 if (M != CodeModel::Small && M != CodeModel::Kernel)
3503 // For small code model we assume that latest object is 16MB before end of 31
3504 // bits boundary. We may also accept pretty large negative constants knowing
3505 // that all objects are in the positive half of address space.
3506 if (M == CodeModel::Small && Offset < 16*1024*1024)
3509 // For kernel code model we know that all object resist in the negative half
3510 // of 32bits address space. We may not accept negative offsets, since they may
3511 // be just off and we may accept pretty large positive ones.
3512 if (M == CodeModel::Kernel && Offset > 0)
3518 /// isCalleePop - Determines whether the callee is required to pop its
3519 /// own arguments. Callee pop is necessary to support tail calls.
3520 bool X86::isCalleePop(CallingConv::ID CallingConv,
3521 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3525 switch (CallingConv) {
3528 case CallingConv::X86_StdCall:
3530 case CallingConv::X86_FastCall:
3532 case CallingConv::X86_ThisCall:
3534 case CallingConv::Fast:
3536 case CallingConv::GHC:
3538 case CallingConv::HiPE:
3543 /// \brief Return true if the condition is an unsigned comparison operation.
3544 static bool isX86CCUnsigned(unsigned X86CC) {
3546 default: llvm_unreachable("Invalid integer condition!");
3547 case X86::COND_E: return true;
3548 case X86::COND_G: return false;
3549 case X86::COND_GE: return false;
3550 case X86::COND_L: return false;
3551 case X86::COND_LE: return false;
3552 case X86::COND_NE: return true;
3553 case X86::COND_B: return true;
3554 case X86::COND_A: return true;
3555 case X86::COND_BE: return true;
3556 case X86::COND_AE: return true;
3558 llvm_unreachable("covered switch fell through?!");
3561 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3562 /// specific condition code, returning the condition code and the LHS/RHS of the
3563 /// comparison to make.
3564 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3565 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3567 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3568 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3569 // X > -1 -> X == 0, jump !sign.
3570 RHS = DAG.getConstant(0, RHS.getValueType());
3571 return X86::COND_NS;
3573 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3574 // X < 0 -> X == 0, jump on sign.
3577 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3579 RHS = DAG.getConstant(0, RHS.getValueType());
3580 return X86::COND_LE;
3584 switch (SetCCOpcode) {
3585 default: llvm_unreachable("Invalid integer condition!");
3586 case ISD::SETEQ: return X86::COND_E;
3587 case ISD::SETGT: return X86::COND_G;
3588 case ISD::SETGE: return X86::COND_GE;
3589 case ISD::SETLT: return X86::COND_L;
3590 case ISD::SETLE: return X86::COND_LE;
3591 case ISD::SETNE: return X86::COND_NE;
3592 case ISD::SETULT: return X86::COND_B;
3593 case ISD::SETUGT: return X86::COND_A;
3594 case ISD::SETULE: return X86::COND_BE;
3595 case ISD::SETUGE: return X86::COND_AE;
3599 // First determine if it is required or is profitable to flip the operands.
3601 // If LHS is a foldable load, but RHS is not, flip the condition.
3602 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3603 !ISD::isNON_EXTLoad(RHS.getNode())) {
3604 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3605 std::swap(LHS, RHS);
3608 switch (SetCCOpcode) {
3614 std::swap(LHS, RHS);
3618 // On a floating point condition, the flags are set as follows:
3620 // 0 | 0 | 0 | X > Y
3621 // 0 | 0 | 1 | X < Y
3622 // 1 | 0 | 0 | X == Y
3623 // 1 | 1 | 1 | unordered
3624 switch (SetCCOpcode) {
3625 default: llvm_unreachable("Condcode should be pre-legalized away");
3627 case ISD::SETEQ: return X86::COND_E;
3628 case ISD::SETOLT: // flipped
3630 case ISD::SETGT: return X86::COND_A;
3631 case ISD::SETOLE: // flipped
3633 case ISD::SETGE: return X86::COND_AE;
3634 case ISD::SETUGT: // flipped
3636 case ISD::SETLT: return X86::COND_B;
3637 case ISD::SETUGE: // flipped
3639 case ISD::SETLE: return X86::COND_BE;
3641 case ISD::SETNE: return X86::COND_NE;
3642 case ISD::SETUO: return X86::COND_P;
3643 case ISD::SETO: return X86::COND_NP;
3645 case ISD::SETUNE: return X86::COND_INVALID;
3649 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3650 /// code. Current x86 isa includes the following FP cmov instructions:
3651 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3652 static bool hasFPCMov(unsigned X86CC) {
3668 /// isFPImmLegal - Returns true if the target can instruction select the
3669 /// specified FP immediate natively. If false, the legalizer will
3670 /// materialize the FP immediate as a load from a constant pool.
3671 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3672 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3673 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3679 /// \brief Returns true if it is beneficial to convert a load of a constant
3680 /// to just the constant itself.
3681 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3683 assert(Ty->isIntegerTy());
3685 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3686 if (BitSize == 0 || BitSize > 64)
3691 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3692 /// the specified range (L, H].
3693 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3694 return (Val < 0) || (Val >= Low && Val < Hi);
3697 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3698 /// specified value.
3699 static bool isUndefOrEqual(int Val, int CmpVal) {
3700 return (Val < 0 || Val == CmpVal);
3703 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3704 /// from position Pos and ending in Pos+Size, falls within the specified
3705 /// sequential range (L, L+Pos]. or is undef.
3706 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3707 unsigned Pos, unsigned Size, int Low) {
3708 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3709 if (!isUndefOrEqual(Mask[i], Low))
3714 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3715 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3716 /// the second operand.
3717 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3718 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3719 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3720 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3721 return (Mask[0] < 2 && Mask[1] < 2);
3725 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3726 /// is suitable for input to PSHUFHW.
3727 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3728 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3731 // Lower quadword copied in order or undef.
3732 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3735 // Upper quadword shuffled.
3736 for (unsigned i = 4; i != 8; ++i)
3737 if (!isUndefOrInRange(Mask[i], 4, 8))
3740 if (VT == MVT::v16i16) {
3741 // Lower quadword copied in order or undef.
3742 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3745 // Upper quadword shuffled.
3746 for (unsigned i = 12; i != 16; ++i)
3747 if (!isUndefOrInRange(Mask[i], 12, 16))
3754 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3755 /// is suitable for input to PSHUFLW.
3756 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3757 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3760 // Upper quadword copied in order.
3761 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3764 // Lower quadword shuffled.
3765 for (unsigned i = 0; i != 4; ++i)
3766 if (!isUndefOrInRange(Mask[i], 0, 4))
3769 if (VT == MVT::v16i16) {
3770 // Upper quadword copied in order.
3771 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3774 // Lower quadword shuffled.
3775 for (unsigned i = 8; i != 12; ++i)
3776 if (!isUndefOrInRange(Mask[i], 8, 12))
3783 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3784 /// is suitable for input to PALIGNR.
3785 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3786 const X86Subtarget *Subtarget) {
3787 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3788 (VT.is256BitVector() && !Subtarget->hasInt256()))
3791 unsigned NumElts = VT.getVectorNumElements();
3792 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3793 unsigned NumLaneElts = NumElts/NumLanes;
3795 // Do not handle 64-bit element shuffles with palignr.
3796 if (NumLaneElts == 2)
3799 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3801 for (i = 0; i != NumLaneElts; ++i) {
3806 // Lane is all undef, go to next lane
3807 if (i == NumLaneElts)
3810 int Start = Mask[i+l];
3812 // Make sure its in this lane in one of the sources
3813 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3814 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3817 // If not lane 0, then we must match lane 0
3818 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3821 // Correct second source to be contiguous with first source
3822 if (Start >= (int)NumElts)
3823 Start -= NumElts - NumLaneElts;
3825 // Make sure we're shifting in the right direction.
3826 if (Start <= (int)(i+l))
3831 // Check the rest of the elements to see if they are consecutive.
3832 for (++i; i != NumLaneElts; ++i) {
3833 int Idx = Mask[i+l];
3835 // Make sure its in this lane
3836 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3837 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3840 // If not lane 0, then we must match lane 0
3841 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3844 if (Idx >= (int)NumElts)
3845 Idx -= NumElts - NumLaneElts;
3847 if (!isUndefOrEqual(Idx, Start+i))
3856 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3857 /// the two vector operands have swapped position.
3858 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3859 unsigned NumElems) {
3860 for (unsigned i = 0; i != NumElems; ++i) {
3864 else if (idx < (int)NumElems)
3865 Mask[i] = idx + NumElems;
3867 Mask[i] = idx - NumElems;
3871 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3872 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3873 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3874 /// reverse of what x86 shuffles want.
3875 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3877 unsigned NumElems = VT.getVectorNumElements();
3878 unsigned NumLanes = VT.getSizeInBits()/128;
3879 unsigned NumLaneElems = NumElems/NumLanes;
3881 if (NumLaneElems != 2 && NumLaneElems != 4)
3884 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3885 bool symetricMaskRequired =
3886 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3888 // VSHUFPSY divides the resulting vector into 4 chunks.
3889 // The sources are also splitted into 4 chunks, and each destination
3890 // chunk must come from a different source chunk.
3892 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3893 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3895 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3896 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3898 // VSHUFPDY divides the resulting vector into 4 chunks.
3899 // The sources are also splitted into 4 chunks, and each destination
3900 // chunk must come from a different source chunk.
3902 // SRC1 => X3 X2 X1 X0
3903 // SRC2 => Y3 Y2 Y1 Y0
3905 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3907 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3908 unsigned HalfLaneElems = NumLaneElems/2;
3909 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3910 for (unsigned i = 0; i != NumLaneElems; ++i) {
3911 int Idx = Mask[i+l];
3912 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3913 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3915 // For VSHUFPSY, the mask of the second half must be the same as the
3916 // first but with the appropriate offsets. This works in the same way as
3917 // VPERMILPS works with masks.
3918 if (!symetricMaskRequired || Idx < 0)
3920 if (MaskVal[i] < 0) {
3921 MaskVal[i] = Idx - l;
3924 if ((signed)(Idx - l) != MaskVal[i])
3932 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3933 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3934 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3935 if (!VT.is128BitVector())
3938 unsigned NumElems = VT.getVectorNumElements();
3943 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3944 return isUndefOrEqual(Mask[0], 6) &&
3945 isUndefOrEqual(Mask[1], 7) &&
3946 isUndefOrEqual(Mask[2], 2) &&
3947 isUndefOrEqual(Mask[3], 3);
3950 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3951 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3953 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3954 if (!VT.is128BitVector())
3957 unsigned NumElems = VT.getVectorNumElements();
3962 return isUndefOrEqual(Mask[0], 2) &&
3963 isUndefOrEqual(Mask[1], 3) &&
3964 isUndefOrEqual(Mask[2], 2) &&
3965 isUndefOrEqual(Mask[3], 3);
3968 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3969 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3970 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3971 if (!VT.is128BitVector())
3974 unsigned NumElems = VT.getVectorNumElements();
3976 if (NumElems != 2 && NumElems != 4)
3979 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3980 if (!isUndefOrEqual(Mask[i], i + NumElems))
3983 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3984 if (!isUndefOrEqual(Mask[i], i))
3990 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3991 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3992 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3993 if (!VT.is128BitVector())
3996 unsigned NumElems = VT.getVectorNumElements();
3998 if (NumElems != 2 && NumElems != 4)
4001 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4002 if (!isUndefOrEqual(Mask[i], i))
4005 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4006 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4012 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4013 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4014 /// i. e: If all but one element come from the same vector.
4015 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4016 // TODO: Deal with AVX's VINSERTPS
4017 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4020 unsigned CorrectPosV1 = 0;
4021 unsigned CorrectPosV2 = 0;
4022 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4023 if (Mask[i] == -1) {
4031 else if (Mask[i] == i + 4)
4035 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4036 // We have 3 elements (undefs count as elements from any vector) from one
4037 // vector, and one from another.
4044 // Some special combinations that can be optimized.
4047 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4048 SelectionDAG &DAG) {
4049 MVT VT = SVOp->getSimpleValueType(0);
4052 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4055 ArrayRef<int> Mask = SVOp->getMask();
4057 // These are the special masks that may be optimized.
4058 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4059 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4060 bool MatchEvenMask = true;
4061 bool MatchOddMask = true;
4062 for (int i=0; i<8; ++i) {
4063 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4064 MatchEvenMask = false;
4065 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4066 MatchOddMask = false;
4069 if (!MatchEvenMask && !MatchOddMask)
4072 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4074 SDValue Op0 = SVOp->getOperand(0);
4075 SDValue Op1 = SVOp->getOperand(1);
4077 if (MatchEvenMask) {
4078 // Shift the second operand right to 32 bits.
4079 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4080 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4082 // Shift the first operand left to 32 bits.
4083 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4084 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4086 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4087 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4090 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4091 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4092 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4093 bool HasInt256, bool V2IsSplat = false) {
4095 assert(VT.getSizeInBits() >= 128 &&
4096 "Unsupported vector type for unpckl");
4098 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4100 unsigned NumOf256BitLanes;
4101 unsigned NumElts = VT.getVectorNumElements();
4102 if (VT.is256BitVector()) {
4103 if (NumElts != 4 && NumElts != 8 &&
4104 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4107 NumOf256BitLanes = 1;
4108 } else if (VT.is512BitVector()) {
4109 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4110 "Unsupported vector type for unpckh");
4112 NumOf256BitLanes = 2;
4115 NumOf256BitLanes = 1;
4118 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4119 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4121 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4122 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4123 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4124 int BitI = Mask[l256*NumEltsInStride+l+i];
4125 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4126 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4128 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4130 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4138 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4139 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4140 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4141 bool HasInt256, bool V2IsSplat = false) {
4142 assert(VT.getSizeInBits() >= 128 &&
4143 "Unsupported vector type for unpckh");
4145 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4147 unsigned NumOf256BitLanes;
4148 unsigned NumElts = VT.getVectorNumElements();
4149 if (VT.is256BitVector()) {
4150 if (NumElts != 4 && NumElts != 8 &&
4151 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4154 NumOf256BitLanes = 1;
4155 } else if (VT.is512BitVector()) {
4156 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4157 "Unsupported vector type for unpckh");
4159 NumOf256BitLanes = 2;
4162 NumOf256BitLanes = 1;
4165 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4166 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4168 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4169 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4170 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4171 int BitI = Mask[l256*NumEltsInStride+l+i];
4172 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4173 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4175 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4177 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4185 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4186 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4188 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4189 unsigned NumElts = VT.getVectorNumElements();
4190 bool Is256BitVec = VT.is256BitVector();
4192 if (VT.is512BitVector())
4194 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4195 "Unsupported vector type for unpckh");
4197 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4198 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4201 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4202 // FIXME: Need a better way to get rid of this, there's no latency difference
4203 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4204 // the former later. We should also remove the "_undef" special mask.
4205 if (NumElts == 4 && Is256BitVec)
4208 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4209 // independently on 128-bit lanes.
4210 unsigned NumLanes = VT.getSizeInBits()/128;
4211 unsigned NumLaneElts = NumElts/NumLanes;
4213 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4214 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4215 int BitI = Mask[l+i];
4216 int BitI1 = Mask[l+i+1];
4218 if (!isUndefOrEqual(BitI, j))
4220 if (!isUndefOrEqual(BitI1, j))
4228 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4229 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4231 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4232 unsigned NumElts = VT.getVectorNumElements();
4234 if (VT.is512BitVector())
4237 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4238 "Unsupported vector type for unpckh");
4240 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4241 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4244 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4245 // independently on 128-bit lanes.
4246 unsigned NumLanes = VT.getSizeInBits()/128;
4247 unsigned NumLaneElts = NumElts/NumLanes;
4249 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4250 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4251 int BitI = Mask[l+i];
4252 int BitI1 = Mask[l+i+1];
4253 if (!isUndefOrEqual(BitI, j))
4255 if (!isUndefOrEqual(BitI1, j))
4262 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4263 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4264 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4265 if (!VT.is512BitVector())
4268 unsigned NumElts = VT.getVectorNumElements();
4269 unsigned HalfSize = NumElts/2;
4270 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4271 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4276 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4277 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4285 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4286 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4287 /// MOVSD, and MOVD, i.e. setting the lowest element.
4288 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4289 if (VT.getVectorElementType().getSizeInBits() < 32)
4291 if (!VT.is128BitVector())
4294 unsigned NumElts = VT.getVectorNumElements();
4296 if (!isUndefOrEqual(Mask[0], NumElts))
4299 for (unsigned i = 1; i != NumElts; ++i)
4300 if (!isUndefOrEqual(Mask[i], i))
4306 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4307 /// as permutations between 128-bit chunks or halves. As an example: this
4309 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4310 /// The first half comes from the second half of V1 and the second half from the
4311 /// the second half of V2.
4312 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4313 if (!HasFp256 || !VT.is256BitVector())
4316 // The shuffle result is divided into half A and half B. In total the two
4317 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4318 // B must come from C, D, E or F.
4319 unsigned HalfSize = VT.getVectorNumElements()/2;
4320 bool MatchA = false, MatchB = false;
4322 // Check if A comes from one of C, D, E, F.
4323 for (unsigned Half = 0; Half != 4; ++Half) {
4324 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4330 // Check if B comes from one of C, D, E, F.
4331 for (unsigned Half = 0; Half != 4; ++Half) {
4332 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4338 return MatchA && MatchB;
4341 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4342 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4343 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4344 MVT VT = SVOp->getSimpleValueType(0);
4346 unsigned HalfSize = VT.getVectorNumElements()/2;
4348 unsigned FstHalf = 0, SndHalf = 0;
4349 for (unsigned i = 0; i < HalfSize; ++i) {
4350 if (SVOp->getMaskElt(i) > 0) {
4351 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4355 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4356 if (SVOp->getMaskElt(i) > 0) {
4357 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4362 return (FstHalf | (SndHalf << 4));
4365 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4366 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4367 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4371 unsigned NumElts = VT.getVectorNumElements();
4373 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4374 for (unsigned i = 0; i != NumElts; ++i) {
4377 Imm8 |= Mask[i] << (i*2);
4382 unsigned LaneSize = 4;
4383 SmallVector<int, 4> MaskVal(LaneSize, -1);
4385 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4386 for (unsigned i = 0; i != LaneSize; ++i) {
4387 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4391 if (MaskVal[i] < 0) {
4392 MaskVal[i] = Mask[i+l] - l;
4393 Imm8 |= MaskVal[i] << (i*2);
4396 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4403 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4404 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4405 /// Note that VPERMIL mask matching is different depending whether theunderlying
4406 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4407 /// to the same elements of the low, but to the higher half of the source.
4408 /// In VPERMILPD the two lanes could be shuffled independently of each other
4409 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4410 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4411 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4412 if (VT.getSizeInBits() < 256 || EltSize < 32)
4414 bool symetricMaskRequired = (EltSize == 32);
4415 unsigned NumElts = VT.getVectorNumElements();
4417 unsigned NumLanes = VT.getSizeInBits()/128;
4418 unsigned LaneSize = NumElts/NumLanes;
4419 // 2 or 4 elements in one lane
4421 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4422 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4423 for (unsigned i = 0; i != LaneSize; ++i) {
4424 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4426 if (symetricMaskRequired) {
4427 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4428 ExpectedMaskVal[i] = Mask[i+l] - l;
4431 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4439 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4440 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4441 /// element of vector 2 and the other elements to come from vector 1 in order.
4442 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4443 bool V2IsSplat = false, bool V2IsUndef = false) {
4444 if (!VT.is128BitVector())
4447 unsigned NumOps = VT.getVectorNumElements();
4448 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4451 if (!isUndefOrEqual(Mask[0], 0))
4454 for (unsigned i = 1; i != NumOps; ++i)
4455 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4456 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4457 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4463 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4464 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4465 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4466 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4467 const X86Subtarget *Subtarget) {
4468 if (!Subtarget->hasSSE3())
4471 unsigned NumElems = VT.getVectorNumElements();
4473 if ((VT.is128BitVector() && NumElems != 4) ||
4474 (VT.is256BitVector() && NumElems != 8) ||
4475 (VT.is512BitVector() && NumElems != 16))
4478 // "i+1" is the value the indexed mask element must have
4479 for (unsigned i = 0; i != NumElems; i += 2)
4480 if (!isUndefOrEqual(Mask[i], i+1) ||
4481 !isUndefOrEqual(Mask[i+1], i+1))
4487 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4488 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4489 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4490 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4491 const X86Subtarget *Subtarget) {
4492 if (!Subtarget->hasSSE3())
4495 unsigned NumElems = VT.getVectorNumElements();
4497 if ((VT.is128BitVector() && NumElems != 4) ||
4498 (VT.is256BitVector() && NumElems != 8) ||
4499 (VT.is512BitVector() && NumElems != 16))
4502 // "i" is the value the indexed mask element must have
4503 for (unsigned i = 0; i != NumElems; i += 2)
4504 if (!isUndefOrEqual(Mask[i], i) ||
4505 !isUndefOrEqual(Mask[i+1], i))
4511 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4512 /// specifies a shuffle of elements that is suitable for input to 256-bit
4513 /// version of MOVDDUP.
4514 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4515 if (!HasFp256 || !VT.is256BitVector())
4518 unsigned NumElts = VT.getVectorNumElements();
4522 for (unsigned i = 0; i != NumElts/2; ++i)
4523 if (!isUndefOrEqual(Mask[i], 0))
4525 for (unsigned i = NumElts/2; i != NumElts; ++i)
4526 if (!isUndefOrEqual(Mask[i], NumElts/2))
4531 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4532 /// specifies a shuffle of elements that is suitable for input to 128-bit
4533 /// version of MOVDDUP.
4534 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4535 if (!VT.is128BitVector())
4538 unsigned e = VT.getVectorNumElements() / 2;
4539 for (unsigned i = 0; i != e; ++i)
4540 if (!isUndefOrEqual(Mask[i], i))
4542 for (unsigned i = 0; i != e; ++i)
4543 if (!isUndefOrEqual(Mask[e+i], i))
4548 /// isVEXTRACTIndex - Return true if the specified
4549 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4550 /// suitable for instruction that extract 128 or 256 bit vectors
4551 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4552 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4553 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4556 // The index should be aligned on a vecWidth-bit boundary.
4558 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4560 MVT VT = N->getSimpleValueType(0);
4561 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4562 bool Result = (Index * ElSize) % vecWidth == 0;
4567 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4568 /// operand specifies a subvector insert that is suitable for input to
4569 /// insertion of 128 or 256-bit subvectors
4570 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4571 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4572 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4574 // The index should be aligned on a vecWidth-bit boundary.
4576 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4578 MVT VT = N->getSimpleValueType(0);
4579 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4580 bool Result = (Index * ElSize) % vecWidth == 0;
4585 bool X86::isVINSERT128Index(SDNode *N) {
4586 return isVINSERTIndex(N, 128);
4589 bool X86::isVINSERT256Index(SDNode *N) {
4590 return isVINSERTIndex(N, 256);
4593 bool X86::isVEXTRACT128Index(SDNode *N) {
4594 return isVEXTRACTIndex(N, 128);
4597 bool X86::isVEXTRACT256Index(SDNode *N) {
4598 return isVEXTRACTIndex(N, 256);
4601 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4602 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4603 /// Handles 128-bit and 256-bit.
4604 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4605 MVT VT = N->getSimpleValueType(0);
4607 assert((VT.getSizeInBits() >= 128) &&
4608 "Unsupported vector type for PSHUF/SHUFP");
4610 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4611 // independently on 128-bit lanes.
4612 unsigned NumElts = VT.getVectorNumElements();
4613 unsigned NumLanes = VT.getSizeInBits()/128;
4614 unsigned NumLaneElts = NumElts/NumLanes;
4616 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4617 "Only supports 2, 4 or 8 elements per lane");
4619 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4621 for (unsigned i = 0; i != NumElts; ++i) {
4622 int Elt = N->getMaskElt(i);
4623 if (Elt < 0) continue;
4624 Elt &= NumLaneElts - 1;
4625 unsigned ShAmt = (i << Shift) % 8;
4626 Mask |= Elt << ShAmt;
4632 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4633 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4634 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4635 MVT VT = N->getSimpleValueType(0);
4637 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4638 "Unsupported vector type for PSHUFHW");
4640 unsigned NumElts = VT.getVectorNumElements();
4643 for (unsigned l = 0; l != NumElts; l += 8) {
4644 // 8 nodes per lane, but we only care about the last 4.
4645 for (unsigned i = 0; i < 4; ++i) {
4646 int Elt = N->getMaskElt(l+i+4);
4647 if (Elt < 0) continue;
4648 Elt &= 0x3; // only 2-bits.
4649 Mask |= Elt << (i * 2);
4656 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4657 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4658 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4659 MVT VT = N->getSimpleValueType(0);
4661 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4662 "Unsupported vector type for PSHUFHW");
4664 unsigned NumElts = VT.getVectorNumElements();
4667 for (unsigned l = 0; l != NumElts; l += 8) {
4668 // 8 nodes per lane, but we only care about the first 4.
4669 for (unsigned i = 0; i < 4; ++i) {
4670 int Elt = N->getMaskElt(l+i);
4671 if (Elt < 0) continue;
4672 Elt &= 0x3; // only 2-bits
4673 Mask |= Elt << (i * 2);
4680 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4681 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4682 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4683 MVT VT = SVOp->getSimpleValueType(0);
4684 unsigned EltSize = VT.is512BitVector() ? 1 :
4685 VT.getVectorElementType().getSizeInBits() >> 3;
4687 unsigned NumElts = VT.getVectorNumElements();
4688 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4689 unsigned NumLaneElts = NumElts/NumLanes;
4693 for (i = 0; i != NumElts; ++i) {
4694 Val = SVOp->getMaskElt(i);
4698 if (Val >= (int)NumElts)
4699 Val -= NumElts - NumLaneElts;
4701 assert(Val - i > 0 && "PALIGNR imm should be positive");
4702 return (Val - i) * EltSize;
4705 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4706 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4707 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4708 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4711 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4713 MVT VecVT = N->getOperand(0).getSimpleValueType();
4714 MVT ElVT = VecVT.getVectorElementType();
4716 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4717 return Index / NumElemsPerChunk;
4720 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4721 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4722 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4723 llvm_unreachable("Illegal insert subvector for VINSERT");
4726 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4728 MVT VecVT = N->getSimpleValueType(0);
4729 MVT ElVT = VecVT.getVectorElementType();
4731 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4732 return Index / NumElemsPerChunk;
4735 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4736 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4737 /// and VINSERTI128 instructions.
4738 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4739 return getExtractVEXTRACTImmediate(N, 128);
4742 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4743 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4744 /// and VINSERTI64x4 instructions.
4745 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4746 return getExtractVEXTRACTImmediate(N, 256);
4749 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4750 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4751 /// and VINSERTI128 instructions.
4752 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4753 return getInsertVINSERTImmediate(N, 128);
4756 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4757 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4758 /// and VINSERTI64x4 instructions.
4759 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4760 return getInsertVINSERTImmediate(N, 256);
4763 /// isZero - Returns true if Elt is a constant integer zero
4764 static bool isZero(SDValue V) {
4765 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4766 return C && C->isNullValue();
4769 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4771 bool X86::isZeroNode(SDValue Elt) {
4774 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4775 return CFP->getValueAPF().isPosZero();
4779 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4780 /// match movhlps. The lower half elements should come from upper half of
4781 /// V1 (and in order), and the upper half elements should come from the upper
4782 /// half of V2 (and in order).
4783 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4784 if (!VT.is128BitVector())
4786 if (VT.getVectorNumElements() != 4)
4788 for (unsigned i = 0, e = 2; i != e; ++i)
4789 if (!isUndefOrEqual(Mask[i], i+2))
4791 for (unsigned i = 2; i != 4; ++i)
4792 if (!isUndefOrEqual(Mask[i], i+4))
4797 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4798 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4800 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4801 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4803 N = N->getOperand(0).getNode();
4804 if (!ISD::isNON_EXTLoad(N))
4807 *LD = cast<LoadSDNode>(N);
4811 // Test whether the given value is a vector value which will be legalized
4813 static bool WillBeConstantPoolLoad(SDNode *N) {
4814 if (N->getOpcode() != ISD::BUILD_VECTOR)
4817 // Check for any non-constant elements.
4818 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4819 switch (N->getOperand(i).getNode()->getOpcode()) {
4821 case ISD::ConstantFP:
4828 // Vectors of all-zeros and all-ones are materialized with special
4829 // instructions rather than being loaded.
4830 return !ISD::isBuildVectorAllZeros(N) &&
4831 !ISD::isBuildVectorAllOnes(N);
4834 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4835 /// match movlp{s|d}. The lower half elements should come from lower half of
4836 /// V1 (and in order), and the upper half elements should come from the upper
4837 /// half of V2 (and in order). And since V1 will become the source of the
4838 /// MOVLP, it must be either a vector load or a scalar load to vector.
4839 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4840 ArrayRef<int> Mask, MVT VT) {
4841 if (!VT.is128BitVector())
4844 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4846 // Is V2 is a vector load, don't do this transformation. We will try to use
4847 // load folding shufps op.
4848 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4851 unsigned NumElems = VT.getVectorNumElements();
4853 if (NumElems != 2 && NumElems != 4)
4855 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4856 if (!isUndefOrEqual(Mask[i], i))
4858 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4859 if (!isUndefOrEqual(Mask[i], i+NumElems))
4864 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4865 /// to an zero vector.
4866 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4867 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4868 SDValue V1 = N->getOperand(0);
4869 SDValue V2 = N->getOperand(1);
4870 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4871 for (unsigned i = 0; i != NumElems; ++i) {
4872 int Idx = N->getMaskElt(i);
4873 if (Idx >= (int)NumElems) {
4874 unsigned Opc = V2.getOpcode();
4875 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4877 if (Opc != ISD::BUILD_VECTOR ||
4878 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4880 } else if (Idx >= 0) {
4881 unsigned Opc = V1.getOpcode();
4882 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4884 if (Opc != ISD::BUILD_VECTOR ||
4885 !X86::isZeroNode(V1.getOperand(Idx)))
4892 /// getZeroVector - Returns a vector of specified type with all zero elements.
4894 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4895 SelectionDAG &DAG, SDLoc dl) {
4896 assert(VT.isVector() && "Expected a vector type");
4898 // Always build SSE zero vectors as <4 x i32> bitcasted
4899 // to their dest type. This ensures they get CSE'd.
4901 if (VT.is128BitVector()) { // SSE
4902 if (Subtarget->hasSSE2()) { // SSE2
4903 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4904 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4906 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4907 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4909 } else if (VT.is256BitVector()) { // AVX
4910 if (Subtarget->hasInt256()) { // AVX2
4911 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4912 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4913 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4915 // 256-bit logic and arithmetic instructions in AVX are all
4916 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4917 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4918 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4919 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4921 } else if (VT.is512BitVector()) { // AVX-512
4922 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4923 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4924 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4925 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4926 } else if (VT.getScalarType() == MVT::i1) {
4927 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4928 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
4929 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
4930 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4932 llvm_unreachable("Unexpected vector type");
4934 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4937 /// getOnesVector - Returns a vector of specified type with all bits set.
4938 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4939 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4940 /// Then bitcast to their original type, ensuring they get CSE'd.
4941 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4943 assert(VT.isVector() && "Expected a vector type");
4945 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4947 if (VT.is256BitVector()) {
4948 if (HasInt256) { // AVX2
4949 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4950 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4952 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4953 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4955 } else if (VT.is128BitVector()) {
4956 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4958 llvm_unreachable("Unexpected vector type");
4960 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4963 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4964 /// that point to V2 points to its first element.
4965 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4966 for (unsigned i = 0; i != NumElems; ++i) {
4967 if (Mask[i] > (int)NumElems) {
4973 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4974 /// operation of specified width.
4975 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4977 unsigned NumElems = VT.getVectorNumElements();
4978 SmallVector<int, 8> Mask;
4979 Mask.push_back(NumElems);
4980 for (unsigned i = 1; i != NumElems; ++i)
4982 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4985 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4986 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4988 unsigned NumElems = VT.getVectorNumElements();
4989 SmallVector<int, 8> Mask;
4990 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4992 Mask.push_back(i + NumElems);
4994 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4997 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4998 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5000 unsigned NumElems = VT.getVectorNumElements();
5001 SmallVector<int, 8> Mask;
5002 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5003 Mask.push_back(i + Half);
5004 Mask.push_back(i + NumElems + Half);
5006 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5009 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5010 // a generic shuffle instruction because the target has no such instructions.
5011 // Generate shuffles which repeat i16 and i8 several times until they can be
5012 // represented by v4f32 and then be manipulated by target suported shuffles.
5013 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5014 MVT VT = V.getSimpleValueType();
5015 int NumElems = VT.getVectorNumElements();
5018 while (NumElems > 4) {
5019 if (EltNo < NumElems/2) {
5020 V = getUnpackl(DAG, dl, VT, V, V);
5022 V = getUnpackh(DAG, dl, VT, V, V);
5023 EltNo -= NumElems/2;
5030 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5031 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5032 MVT VT = V.getSimpleValueType();
5035 if (VT.is128BitVector()) {
5036 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5037 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5038 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5040 } else if (VT.is256BitVector()) {
5041 // To use VPERMILPS to splat scalars, the second half of indicies must
5042 // refer to the higher part, which is a duplication of the lower one,
5043 // because VPERMILPS can only handle in-lane permutations.
5044 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5045 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5047 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5048 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5051 llvm_unreachable("Vector size not supported");
5053 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5056 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5057 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5058 MVT SrcVT = SV->getSimpleValueType(0);
5059 SDValue V1 = SV->getOperand(0);
5062 int EltNo = SV->getSplatIndex();
5063 int NumElems = SrcVT.getVectorNumElements();
5064 bool Is256BitVec = SrcVT.is256BitVector();
5066 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5067 "Unknown how to promote splat for type");
5069 // Extract the 128-bit part containing the splat element and update
5070 // the splat element index when it refers to the higher register.
5072 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5073 if (EltNo >= NumElems/2)
5074 EltNo -= NumElems/2;
5077 // All i16 and i8 vector types can't be used directly by a generic shuffle
5078 // instruction because the target has no such instruction. Generate shuffles
5079 // which repeat i16 and i8 several times until they fit in i32, and then can
5080 // be manipulated by target suported shuffles.
5081 MVT EltVT = SrcVT.getVectorElementType();
5082 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5083 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5085 // Recreate the 256-bit vector and place the same 128-bit vector
5086 // into the low and high part. This is necessary because we want
5087 // to use VPERM* to shuffle the vectors
5089 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5092 return getLegalSplat(DAG, V1, EltNo);
5095 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5096 /// vector of zero or undef vector. This produces a shuffle where the low
5097 /// element of V2 is swizzled into the zero/undef vector, landing at element
5098 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5099 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5101 const X86Subtarget *Subtarget,
5102 SelectionDAG &DAG) {
5103 MVT VT = V2.getSimpleValueType();
5105 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5106 unsigned NumElems = VT.getVectorNumElements();
5107 SmallVector<int, 16> MaskVec;
5108 for (unsigned i = 0; i != NumElems; ++i)
5109 // If this is the insertion idx, put the low elt of V2 here.
5110 MaskVec.push_back(i == Idx ? NumElems : i);
5111 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5114 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5115 /// target specific opcode. Returns true if the Mask could be calculated.
5116 /// Sets IsUnary to true if only uses one source.
5117 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5118 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5119 unsigned NumElems = VT.getVectorNumElements();
5123 switch(N->getOpcode()) {
5125 ImmN = N->getOperand(N->getNumOperands()-1);
5126 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5128 case X86ISD::UNPCKH:
5129 DecodeUNPCKHMask(VT, Mask);
5131 case X86ISD::UNPCKL:
5132 DecodeUNPCKLMask(VT, Mask);
5134 case X86ISD::MOVHLPS:
5135 DecodeMOVHLPSMask(NumElems, Mask);
5137 case X86ISD::MOVLHPS:
5138 DecodeMOVLHPSMask(NumElems, Mask);
5140 case X86ISD::PALIGNR:
5141 ImmN = N->getOperand(N->getNumOperands()-1);
5142 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5144 case X86ISD::PSHUFD:
5145 case X86ISD::VPERMILP:
5146 ImmN = N->getOperand(N->getNumOperands()-1);
5147 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5150 case X86ISD::PSHUFHW:
5151 ImmN = N->getOperand(N->getNumOperands()-1);
5152 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5155 case X86ISD::PSHUFLW:
5156 ImmN = N->getOperand(N->getNumOperands()-1);
5157 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5160 case X86ISD::VPERMI:
5161 ImmN = N->getOperand(N->getNumOperands()-1);
5162 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5166 case X86ISD::MOVSD: {
5167 // The index 0 always comes from the first element of the second source,
5168 // this is why MOVSS and MOVSD are used in the first place. The other
5169 // elements come from the other positions of the first source vector
5170 Mask.push_back(NumElems);
5171 for (unsigned i = 1; i != NumElems; ++i) {
5176 case X86ISD::VPERM2X128:
5177 ImmN = N->getOperand(N->getNumOperands()-1);
5178 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5179 if (Mask.empty()) return false;
5181 case X86ISD::MOVDDUP:
5182 case X86ISD::MOVLHPD:
5183 case X86ISD::MOVLPD:
5184 case X86ISD::MOVLPS:
5185 case X86ISD::MOVSHDUP:
5186 case X86ISD::MOVSLDUP:
5187 // Not yet implemented
5189 default: llvm_unreachable("unknown target shuffle node");
5195 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5196 /// element of the result of the vector shuffle.
5197 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5200 return SDValue(); // Limit search depth.
5202 SDValue V = SDValue(N, 0);
5203 EVT VT = V.getValueType();
5204 unsigned Opcode = V.getOpcode();
5206 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5207 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5208 int Elt = SV->getMaskElt(Index);
5211 return DAG.getUNDEF(VT.getVectorElementType());
5213 unsigned NumElems = VT.getVectorNumElements();
5214 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5215 : SV->getOperand(1);
5216 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5219 // Recurse into target specific vector shuffles to find scalars.
5220 if (isTargetShuffle(Opcode)) {
5221 MVT ShufVT = V.getSimpleValueType();
5222 unsigned NumElems = ShufVT.getVectorNumElements();
5223 SmallVector<int, 16> ShuffleMask;
5226 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5229 int Elt = ShuffleMask[Index];
5231 return DAG.getUNDEF(ShufVT.getVectorElementType());
5233 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5235 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5239 // Actual nodes that may contain scalar elements
5240 if (Opcode == ISD::BITCAST) {
5241 V = V.getOperand(0);
5242 EVT SrcVT = V.getValueType();
5243 unsigned NumElems = VT.getVectorNumElements();
5245 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5249 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5250 return (Index == 0) ? V.getOperand(0)
5251 : DAG.getUNDEF(VT.getVectorElementType());
5253 if (V.getOpcode() == ISD::BUILD_VECTOR)
5254 return V.getOperand(Index);
5259 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5260 /// shuffle operation which come from a consecutively from a zero. The
5261 /// search can start in two different directions, from left or right.
5262 /// We count undefs as zeros until PreferredNum is reached.
5263 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5264 unsigned NumElems, bool ZerosFromLeft,
5266 unsigned PreferredNum = -1U) {
5267 unsigned NumZeros = 0;
5268 for (unsigned i = 0; i != NumElems; ++i) {
5269 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5270 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5274 if (X86::isZeroNode(Elt))
5276 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5277 NumZeros = std::min(NumZeros + 1, PreferredNum);
5285 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5286 /// correspond consecutively to elements from one of the vector operands,
5287 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5289 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5290 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5291 unsigned NumElems, unsigned &OpNum) {
5292 bool SeenV1 = false;
5293 bool SeenV2 = false;
5295 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5296 int Idx = SVOp->getMaskElt(i);
5297 // Ignore undef indicies
5301 if (Idx < (int)NumElems)
5306 // Only accept consecutive elements from the same vector
5307 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5311 OpNum = SeenV1 ? 0 : 1;
5315 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5316 /// logical left shift of a vector.
5317 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5318 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5320 SVOp->getSimpleValueType(0).getVectorNumElements();
5321 unsigned NumZeros = getNumOfConsecutiveZeros(
5322 SVOp, NumElems, false /* check zeros from right */, DAG,
5323 SVOp->getMaskElt(0));
5329 // Considering the elements in the mask that are not consecutive zeros,
5330 // check if they consecutively come from only one of the source vectors.
5332 // V1 = {X, A, B, C} 0
5334 // vector_shuffle V1, V2 <1, 2, 3, X>
5336 if (!isShuffleMaskConsecutive(SVOp,
5337 0, // Mask Start Index
5338 NumElems-NumZeros, // Mask End Index(exclusive)
5339 NumZeros, // Where to start looking in the src vector
5340 NumElems, // Number of elements in vector
5341 OpSrc)) // Which source operand ?
5346 ShVal = SVOp->getOperand(OpSrc);
5350 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5351 /// logical left shift of a vector.
5352 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5353 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5355 SVOp->getSimpleValueType(0).getVectorNumElements();
5356 unsigned NumZeros = getNumOfConsecutiveZeros(
5357 SVOp, NumElems, true /* check zeros from left */, DAG,
5358 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5364 // Considering the elements in the mask that are not consecutive zeros,
5365 // check if they consecutively come from only one of the source vectors.
5367 // 0 { A, B, X, X } = V2
5369 // vector_shuffle V1, V2 <X, X, 4, 5>
5371 if (!isShuffleMaskConsecutive(SVOp,
5372 NumZeros, // Mask Start Index
5373 NumElems, // Mask End Index(exclusive)
5374 0, // Where to start looking in the src vector
5375 NumElems, // Number of elements in vector
5376 OpSrc)) // Which source operand ?
5381 ShVal = SVOp->getOperand(OpSrc);
5385 /// isVectorShift - Returns true if the shuffle can be implemented as a
5386 /// logical left or right shift of a vector.
5387 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5388 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5389 // Although the logic below support any bitwidth size, there are no
5390 // shift instructions which handle more than 128-bit vectors.
5391 if (!SVOp->getSimpleValueType(0).is128BitVector())
5394 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5395 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5401 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5403 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5404 unsigned NumNonZero, unsigned NumZero,
5406 const X86Subtarget* Subtarget,
5407 const TargetLowering &TLI) {
5414 for (unsigned i = 0; i < 16; ++i) {
5415 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5416 if (ThisIsNonZero && First) {
5418 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5420 V = DAG.getUNDEF(MVT::v8i16);
5425 SDValue ThisElt, LastElt;
5426 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5427 if (LastIsNonZero) {
5428 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5429 MVT::i16, Op.getOperand(i-1));
5431 if (ThisIsNonZero) {
5432 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5433 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5434 ThisElt, DAG.getConstant(8, MVT::i8));
5436 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5440 if (ThisElt.getNode())
5441 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5442 DAG.getIntPtrConstant(i/2));
5446 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5449 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5451 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5452 unsigned NumNonZero, unsigned NumZero,
5454 const X86Subtarget* Subtarget,
5455 const TargetLowering &TLI) {
5462 for (unsigned i = 0; i < 8; ++i) {
5463 bool isNonZero = (NonZeros & (1 << i)) != 0;
5467 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5469 V = DAG.getUNDEF(MVT::v8i16);
5472 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5473 MVT::v8i16, V, Op.getOperand(i),
5474 DAG.getIntPtrConstant(i));
5481 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5482 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5483 unsigned NonZeros, unsigned NumNonZero,
5484 unsigned NumZero, SelectionDAG &DAG,
5485 const X86Subtarget *Subtarget,
5486 const TargetLowering &TLI) {
5487 // We know there's at least one non-zero element
5488 unsigned FirstNonZeroIdx = 0;
5489 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5490 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5491 X86::isZeroNode(FirstNonZero)) {
5493 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5496 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5497 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5500 SDValue V = FirstNonZero.getOperand(0);
5501 MVT VVT = V.getSimpleValueType();
5502 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5505 unsigned FirstNonZeroDst =
5506 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5507 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5508 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5509 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5511 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5512 SDValue Elem = Op.getOperand(Idx);
5513 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5516 // TODO: What else can be here? Deal with it.
5517 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5520 // TODO: Some optimizations are still possible here
5521 // ex: Getting one element from a vector, and the rest from another.
5522 if (Elem.getOperand(0) != V)
5525 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5528 else if (IncorrectIdx == -1U) {
5532 // There was already one element with an incorrect index.
5533 // We can't optimize this case to an insertps.
5537 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5539 EVT VT = Op.getSimpleValueType();
5540 unsigned ElementMoveMask = 0;
5541 if (IncorrectIdx == -1U)
5542 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5544 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5546 SDValue InsertpsMask =
5547 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5548 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5554 /// getVShift - Return a vector logical shift node.
5556 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5557 unsigned NumBits, SelectionDAG &DAG,
5558 const TargetLowering &TLI, SDLoc dl) {
5559 assert(VT.is128BitVector() && "Unknown type for VShift");
5560 EVT ShVT = MVT::v2i64;
5561 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5562 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5563 return DAG.getNode(ISD::BITCAST, dl, VT,
5564 DAG.getNode(Opc, dl, ShVT, SrcOp,
5565 DAG.getConstant(NumBits,
5566 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5570 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5572 // Check if the scalar load can be widened into a vector load. And if
5573 // the address is "base + cst" see if the cst can be "absorbed" into
5574 // the shuffle mask.
5575 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5576 SDValue Ptr = LD->getBasePtr();
5577 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5579 EVT PVT = LD->getValueType(0);
5580 if (PVT != MVT::i32 && PVT != MVT::f32)
5585 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5586 FI = FINode->getIndex();
5588 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5589 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5590 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5591 Offset = Ptr.getConstantOperandVal(1);
5592 Ptr = Ptr.getOperand(0);
5597 // FIXME: 256-bit vector instructions don't require a strict alignment,
5598 // improve this code to support it better.
5599 unsigned RequiredAlign = VT.getSizeInBits()/8;
5600 SDValue Chain = LD->getChain();
5601 // Make sure the stack object alignment is at least 16 or 32.
5602 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5603 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5604 if (MFI->isFixedObjectIndex(FI)) {
5605 // Can't change the alignment. FIXME: It's possible to compute
5606 // the exact stack offset and reference FI + adjust offset instead.
5607 // If someone *really* cares about this. That's the way to implement it.
5610 MFI->setObjectAlignment(FI, RequiredAlign);
5614 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5615 // Ptr + (Offset & ~15).
5618 if ((Offset % RequiredAlign) & 3)
5620 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5622 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5623 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5625 int EltNo = (Offset - StartOffset) >> 2;
5626 unsigned NumElems = VT.getVectorNumElements();
5628 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5629 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5630 LD->getPointerInfo().getWithOffset(StartOffset),
5631 false, false, false, 0);
5633 SmallVector<int, 8> Mask;
5634 for (unsigned i = 0; i != NumElems; ++i)
5635 Mask.push_back(EltNo);
5637 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5643 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5644 /// vector of type 'VT', see if the elements can be replaced by a single large
5645 /// load which has the same value as a build_vector whose operands are 'elts'.
5647 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5649 /// FIXME: we'd also like to handle the case where the last elements are zero
5650 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5651 /// There's even a handy isZeroNode for that purpose.
5652 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5653 SDLoc &DL, SelectionDAG &DAG,
5654 bool isAfterLegalize) {
5655 EVT EltVT = VT.getVectorElementType();
5656 unsigned NumElems = Elts.size();
5658 LoadSDNode *LDBase = nullptr;
5659 unsigned LastLoadedElt = -1U;
5661 // For each element in the initializer, see if we've found a load or an undef.
5662 // If we don't find an initial load element, or later load elements are
5663 // non-consecutive, bail out.
5664 for (unsigned i = 0; i < NumElems; ++i) {
5665 SDValue Elt = Elts[i];
5667 if (!Elt.getNode() ||
5668 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5671 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5673 LDBase = cast<LoadSDNode>(Elt.getNode());
5677 if (Elt.getOpcode() == ISD::UNDEF)
5680 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5681 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5686 // If we have found an entire vector of loads and undefs, then return a large
5687 // load of the entire vector width starting at the base pointer. If we found
5688 // consecutive loads for the low half, generate a vzext_load node.
5689 if (LastLoadedElt == NumElems - 1) {
5691 if (isAfterLegalize &&
5692 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5695 SDValue NewLd = SDValue();
5697 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5698 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5699 LDBase->getPointerInfo(),
5700 LDBase->isVolatile(), LDBase->isNonTemporal(),
5701 LDBase->isInvariant(), 0);
5702 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5703 LDBase->getPointerInfo(),
5704 LDBase->isVolatile(), LDBase->isNonTemporal(),
5705 LDBase->isInvariant(), LDBase->getAlignment());
5707 if (LDBase->hasAnyUseOfValue(1)) {
5708 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5710 SDValue(NewLd.getNode(), 1));
5711 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5712 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5713 SDValue(NewLd.getNode(), 1));
5718 if (NumElems == 4 && LastLoadedElt == 1 &&
5719 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5720 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5721 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5723 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5724 LDBase->getPointerInfo(),
5725 LDBase->getAlignment(),
5726 false/*isVolatile*/, true/*ReadMem*/,
5729 // Make sure the newly-created LOAD is in the same position as LDBase in
5730 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5731 // update uses of LDBase's output chain to use the TokenFactor.
5732 if (LDBase->hasAnyUseOfValue(1)) {
5733 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5734 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5735 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5736 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5737 SDValue(ResNode.getNode(), 1));
5740 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5745 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5746 /// to generate a splat value for the following cases:
5747 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5748 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5749 /// a scalar load, or a constant.
5750 /// The VBROADCAST node is returned when a pattern is found,
5751 /// or SDValue() otherwise.
5752 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5753 SelectionDAG &DAG) {
5754 if (!Subtarget->hasFp256())
5757 MVT VT = Op.getSimpleValueType();
5760 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5761 "Unsupported vector type for broadcast.");
5766 switch (Op.getOpcode()) {
5768 // Unknown pattern found.
5771 case ISD::BUILD_VECTOR: {
5772 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5773 BitVector UndefElements;
5774 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5776 // We need a splat of a single value to use broadcast, and it doesn't
5777 // make any sense if the value is only in one element of the vector.
5778 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5782 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5783 Ld.getOpcode() == ISD::ConstantFP);
5785 // Make sure that all of the users of a non-constant load are from the
5786 // BUILD_VECTOR node.
5787 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5792 case ISD::VECTOR_SHUFFLE: {
5793 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5795 // Shuffles must have a splat mask where the first element is
5797 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5800 SDValue Sc = Op.getOperand(0);
5801 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5802 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5804 if (!Subtarget->hasInt256())
5807 // Use the register form of the broadcast instruction available on AVX2.
5808 if (VT.getSizeInBits() >= 256)
5809 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5810 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5813 Ld = Sc.getOperand(0);
5814 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5815 Ld.getOpcode() == ISD::ConstantFP);
5817 // The scalar_to_vector node and the suspected
5818 // load node must have exactly one user.
5819 // Constants may have multiple users.
5821 // AVX-512 has register version of the broadcast
5822 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5823 Ld.getValueType().getSizeInBits() >= 32;
5824 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5831 bool IsGE256 = (VT.getSizeInBits() >= 256);
5833 // Handle the broadcasting a single constant scalar from the constant pool
5834 // into a vector. On Sandybridge it is still better to load a constant vector
5835 // from the constant pool and not to broadcast it from a scalar.
5836 if (ConstSplatVal && Subtarget->hasInt256()) {
5837 EVT CVT = Ld.getValueType();
5838 assert(!CVT.isVector() && "Must not broadcast a vector type");
5839 unsigned ScalarSize = CVT.getSizeInBits();
5841 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5842 const Constant *C = nullptr;
5843 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5844 C = CI->getConstantIntValue();
5845 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5846 C = CF->getConstantFPValue();
5848 assert(C && "Invalid constant type");
5850 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5851 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5852 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5853 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5854 MachinePointerInfo::getConstantPool(),
5855 false, false, false, Alignment);
5857 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5861 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5862 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5864 // Handle AVX2 in-register broadcasts.
5865 if (!IsLoad && Subtarget->hasInt256() &&
5866 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5867 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5869 // The scalar source must be a normal load.
5873 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5874 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5876 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5877 // double since there is no vbroadcastsd xmm
5878 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5879 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5880 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5883 // Unsupported broadcast.
5887 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5888 /// underlying vector and index.
5890 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5892 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5894 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5895 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5898 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5900 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5902 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5903 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5906 // In this case the vector is the extract_subvector expression and the index
5907 // is 2, as specified by the shuffle.
5908 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5909 SDValue ShuffleVec = SVOp->getOperand(0);
5910 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5911 assert(ShuffleVecVT.getVectorElementType() ==
5912 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5914 int ShuffleIdx = SVOp->getMaskElt(Idx);
5915 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5916 ExtractedFromVec = ShuffleVec;
5922 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5923 MVT VT = Op.getSimpleValueType();
5925 // Skip if insert_vec_elt is not supported.
5926 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5927 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5931 unsigned NumElems = Op.getNumOperands();
5935 SmallVector<unsigned, 4> InsertIndices;
5936 SmallVector<int, 8> Mask(NumElems, -1);
5938 for (unsigned i = 0; i != NumElems; ++i) {
5939 unsigned Opc = Op.getOperand(i).getOpcode();
5941 if (Opc == ISD::UNDEF)
5944 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5945 // Quit if more than 1 elements need inserting.
5946 if (InsertIndices.size() > 1)
5949 InsertIndices.push_back(i);
5953 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5954 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5955 // Quit if non-constant index.
5956 if (!isa<ConstantSDNode>(ExtIdx))
5958 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5960 // Quit if extracted from vector of different type.
5961 if (ExtractedFromVec.getValueType() != VT)
5964 if (!VecIn1.getNode())
5965 VecIn1 = ExtractedFromVec;
5966 else if (VecIn1 != ExtractedFromVec) {
5967 if (!VecIn2.getNode())
5968 VecIn2 = ExtractedFromVec;
5969 else if (VecIn2 != ExtractedFromVec)
5970 // Quit if more than 2 vectors to shuffle
5974 if (ExtractedFromVec == VecIn1)
5976 else if (ExtractedFromVec == VecIn2)
5977 Mask[i] = Idx + NumElems;
5980 if (!VecIn1.getNode())
5983 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5984 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5985 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5986 unsigned Idx = InsertIndices[i];
5987 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5988 DAG.getIntPtrConstant(Idx));
5994 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5996 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5998 MVT VT = Op.getSimpleValueType();
5999 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6000 "Unexpected type in LowerBUILD_VECTORvXi1!");
6003 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6004 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6005 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6006 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6009 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6010 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6011 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6012 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6015 bool AllContants = true;
6016 uint64_t Immediate = 0;
6017 int NonConstIdx = -1;
6018 bool IsSplat = true;
6019 unsigned NumNonConsts = 0;
6020 unsigned NumConsts = 0;
6021 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6022 SDValue In = Op.getOperand(idx);
6023 if (In.getOpcode() == ISD::UNDEF)
6025 if (!isa<ConstantSDNode>(In)) {
6026 AllContants = false;
6032 if (cast<ConstantSDNode>(In)->getZExtValue())
6033 Immediate |= (1ULL << idx);
6035 if (In != Op.getOperand(0))
6040 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6041 DAG.getConstant(Immediate, MVT::i16));
6042 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6043 DAG.getIntPtrConstant(0));
6046 if (NumNonConsts == 1 && NonConstIdx != 0) {
6049 SDValue VecAsImm = DAG.getConstant(Immediate,
6050 MVT::getIntegerVT(VT.getSizeInBits()));
6051 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6054 DstVec = DAG.getUNDEF(VT);
6055 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6056 Op.getOperand(NonConstIdx),
6057 DAG.getIntPtrConstant(NonConstIdx));
6059 if (!IsSplat && (NonConstIdx != 0))
6060 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6061 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6064 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6065 DAG.getConstant(-1, SelectVT),
6066 DAG.getConstant(0, SelectVT));
6068 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6069 DAG.getConstant((Immediate | 1), SelectVT),
6070 DAG.getConstant(Immediate, SelectVT));
6071 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6074 /// \brief Return true if \p N implements a horizontal binop and return the
6075 /// operands for the horizontal binop into V0 and V1.
6077 /// This is a helper function of PerformBUILD_VECTORCombine.
6078 /// This function checks that the build_vector \p N in input implements a
6079 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6080 /// operation to match.
6081 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6082 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6083 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6086 /// This function only analyzes elements of \p N whose indices are
6087 /// in range [BaseIdx, LastIdx).
6088 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6090 unsigned BaseIdx, unsigned LastIdx,
6091 SDValue &V0, SDValue &V1) {
6092 EVT VT = N->getValueType(0);
6094 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6095 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6096 "Invalid Vector in input!");
6098 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6099 bool CanFold = true;
6100 unsigned ExpectedVExtractIdx = BaseIdx;
6101 unsigned NumElts = LastIdx - BaseIdx;
6102 V0 = DAG.getUNDEF(VT);
6103 V1 = DAG.getUNDEF(VT);
6105 // Check if N implements a horizontal binop.
6106 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6107 SDValue Op = N->getOperand(i + BaseIdx);
6110 if (Op->getOpcode() == ISD::UNDEF) {
6111 // Update the expected vector extract index.
6112 if (i * 2 == NumElts)
6113 ExpectedVExtractIdx = BaseIdx;
6114 ExpectedVExtractIdx += 2;
6118 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6123 SDValue Op0 = Op.getOperand(0);
6124 SDValue Op1 = Op.getOperand(1);
6126 // Try to match the following pattern:
6127 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6128 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6129 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6130 Op0.getOperand(0) == Op1.getOperand(0) &&
6131 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6132 isa<ConstantSDNode>(Op1.getOperand(1)));
6136 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6137 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6139 if (i * 2 < NumElts) {
6140 if (V0.getOpcode() == ISD::UNDEF)
6141 V0 = Op0.getOperand(0);
6143 if (V1.getOpcode() == ISD::UNDEF)
6144 V1 = Op0.getOperand(0);
6145 if (i * 2 == NumElts)
6146 ExpectedVExtractIdx = BaseIdx;
6149 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6150 if (I0 == ExpectedVExtractIdx)
6151 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6152 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6153 // Try to match the following dag sequence:
6154 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6155 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6159 ExpectedVExtractIdx += 2;
6165 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6166 /// a concat_vector.
6168 /// This is a helper function of PerformBUILD_VECTORCombine.
6169 /// This function expects two 256-bit vectors called V0 and V1.
6170 /// At first, each vector is split into two separate 128-bit vectors.
6171 /// Then, the resulting 128-bit vectors are used to implement two
6172 /// horizontal binary operations.
6174 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6176 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6177 /// the two new horizontal binop.
6178 /// When Mode is set, the first horizontal binop dag node would take as input
6179 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6180 /// horizontal binop dag node would take as input the lower 128-bit of V1
6181 /// and the upper 128-bit of V1.
6183 /// HADD V0_LO, V0_HI
6184 /// HADD V1_LO, V1_HI
6186 /// Otherwise, the first horizontal binop dag node takes as input the lower
6187 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6188 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6190 /// HADD V0_LO, V1_LO
6191 /// HADD V0_HI, V1_HI
6193 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6194 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6195 /// the upper 128-bits of the result.
6196 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6197 SDLoc DL, SelectionDAG &DAG,
6198 unsigned X86Opcode, bool Mode,
6199 bool isUndefLO, bool isUndefHI) {
6200 EVT VT = V0.getValueType();
6201 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6202 "Invalid nodes in input!");
6204 unsigned NumElts = VT.getVectorNumElements();
6205 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6206 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6207 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6208 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6209 EVT NewVT = V0_LO.getValueType();
6211 SDValue LO = DAG.getUNDEF(NewVT);
6212 SDValue HI = DAG.getUNDEF(NewVT);
6215 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6216 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6217 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6218 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6219 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6221 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6222 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6223 V1_LO->getOpcode() != ISD::UNDEF))
6224 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6226 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6227 V1_HI->getOpcode() != ISD::UNDEF))
6228 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6231 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6234 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6235 /// sequence of 'vadd + vsub + blendi'.
6236 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6237 const X86Subtarget *Subtarget) {
6239 EVT VT = BV->getValueType(0);
6240 unsigned NumElts = VT.getVectorNumElements();
6241 SDValue InVec0 = DAG.getUNDEF(VT);
6242 SDValue InVec1 = DAG.getUNDEF(VT);
6244 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6245 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6247 // Don't try to emit a VSELECT that cannot be lowered into a blend.
6248 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6249 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
6252 // Odd-numbered elements in the input build vector are obtained from
6253 // adding two integer/float elements.
6254 // Even-numbered elements in the input build vector are obtained from
6255 // subtracting two integer/float elements.
6256 unsigned ExpectedOpcode = ISD::FSUB;
6257 unsigned NextExpectedOpcode = ISD::FADD;
6258 bool AddFound = false;
6259 bool SubFound = false;
6261 for (unsigned i = 0, e = NumElts; i != e; i++) {
6262 SDValue Op = BV->getOperand(i);
6264 // Skip 'undef' values.
6265 unsigned Opcode = Op.getOpcode();
6266 if (Opcode == ISD::UNDEF) {
6267 std::swap(ExpectedOpcode, NextExpectedOpcode);
6271 // Early exit if we found an unexpected opcode.
6272 if (Opcode != ExpectedOpcode)
6275 SDValue Op0 = Op.getOperand(0);
6276 SDValue Op1 = Op.getOperand(1);
6278 // Try to match the following pattern:
6279 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6280 // Early exit if we cannot match that sequence.
6281 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6282 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6283 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6284 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6285 Op0.getOperand(1) != Op1.getOperand(1))
6288 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6292 // We found a valid add/sub node. Update the information accordingly.
6298 // Update InVec0 and InVec1.
6299 if (InVec0.getOpcode() == ISD::UNDEF)
6300 InVec0 = Op0.getOperand(0);
6301 if (InVec1.getOpcode() == ISD::UNDEF)
6302 InVec1 = Op1.getOperand(0);
6304 // Make sure that operands in input to each add/sub node always
6305 // come from a same pair of vectors.
6306 if (InVec0 != Op0.getOperand(0)) {
6307 if (ExpectedOpcode == ISD::FSUB)
6310 // FADD is commutable. Try to commute the operands
6311 // and then test again.
6312 std::swap(Op0, Op1);
6313 if (InVec0 != Op0.getOperand(0))
6317 if (InVec1 != Op1.getOperand(0))
6320 // Update the pair of expected opcodes.
6321 std::swap(ExpectedOpcode, NextExpectedOpcode);
6324 // Don't try to fold this build_vector into a VSELECT if it has
6325 // too many UNDEF operands.
6326 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6327 InVec1.getOpcode() != ISD::UNDEF) {
6328 // Emit a sequence of vector add and sub followed by a VSELECT.
6329 // The new VSELECT will be lowered into a BLENDI.
6330 // At ISel stage, we pattern-match the sequence 'add + sub + BLENDI'
6331 // and emit a single ADDSUB instruction.
6332 SDValue Sub = DAG.getNode(ExpectedOpcode, DL, VT, InVec0, InVec1);
6333 SDValue Add = DAG.getNode(NextExpectedOpcode, DL, VT, InVec0, InVec1);
6335 // Construct the VSELECT mask.
6336 EVT MaskVT = VT.changeVectorElementTypeToInteger();
6337 EVT SVT = MaskVT.getVectorElementType();
6338 unsigned SVTBits = SVT.getSizeInBits();
6339 SmallVector<SDValue, 8> Ops;
6341 for (unsigned i = 0, e = NumElts; i != e; ++i) {
6342 APInt Value = i & 1 ? APInt::getNullValue(SVTBits) :
6343 APInt::getAllOnesValue(SVTBits);
6344 SDValue Constant = DAG.getConstant(Value, SVT);
6345 Ops.push_back(Constant);
6348 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVT, Ops);
6349 return DAG.getSelect(DL, VT, Mask, Sub, Add);
6355 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6356 const X86Subtarget *Subtarget) {
6358 EVT VT = N->getValueType(0);
6359 unsigned NumElts = VT.getVectorNumElements();
6360 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6361 SDValue InVec0, InVec1;
6363 // Try to match an ADDSUB.
6364 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6365 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6366 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6367 if (Value.getNode())
6371 // Try to match horizontal ADD/SUB.
6372 unsigned NumUndefsLO = 0;
6373 unsigned NumUndefsHI = 0;
6374 unsigned Half = NumElts/2;
6376 // Count the number of UNDEF operands in the build_vector in input.
6377 for (unsigned i = 0, e = Half; i != e; ++i)
6378 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6381 for (unsigned i = Half, e = NumElts; i != e; ++i)
6382 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6385 // Early exit if this is either a build_vector of all UNDEFs or all the
6386 // operands but one are UNDEF.
6387 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6390 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6391 // Try to match an SSE3 float HADD/HSUB.
6392 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6393 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6395 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6396 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6397 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6398 // Try to match an SSSE3 integer HADD/HSUB.
6399 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6400 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6402 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6403 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6406 if (!Subtarget->hasAVX())
6409 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6410 // Try to match an AVX horizontal add/sub of packed single/double
6411 // precision floating point values from 256-bit vectors.
6412 SDValue InVec2, InVec3;
6413 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6414 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6415 ((InVec0.getOpcode() == ISD::UNDEF ||
6416 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6417 ((InVec1.getOpcode() == ISD::UNDEF ||
6418 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6419 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6421 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6422 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6423 ((InVec0.getOpcode() == ISD::UNDEF ||
6424 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6425 ((InVec1.getOpcode() == ISD::UNDEF ||
6426 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6427 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6428 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6429 // Try to match an AVX2 horizontal add/sub of signed integers.
6430 SDValue InVec2, InVec3;
6432 bool CanFold = true;
6434 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6435 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6436 ((InVec0.getOpcode() == ISD::UNDEF ||
6437 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6438 ((InVec1.getOpcode() == ISD::UNDEF ||
6439 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6440 X86Opcode = X86ISD::HADD;
6441 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6442 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6443 ((InVec0.getOpcode() == ISD::UNDEF ||
6444 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6445 ((InVec1.getOpcode() == ISD::UNDEF ||
6446 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6447 X86Opcode = X86ISD::HSUB;
6452 // Fold this build_vector into a single horizontal add/sub.
6453 // Do this only if the target has AVX2.
6454 if (Subtarget->hasAVX2())
6455 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6457 // Do not try to expand this build_vector into a pair of horizontal
6458 // add/sub if we can emit a pair of scalar add/sub.
6459 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6462 // Convert this build_vector into a pair of horizontal binop followed by
6464 bool isUndefLO = NumUndefsLO == Half;
6465 bool isUndefHI = NumUndefsHI == Half;
6466 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6467 isUndefLO, isUndefHI);
6471 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6472 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6474 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6475 X86Opcode = X86ISD::HADD;
6476 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6477 X86Opcode = X86ISD::HSUB;
6478 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6479 X86Opcode = X86ISD::FHADD;
6480 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6481 X86Opcode = X86ISD::FHSUB;
6485 // Don't try to expand this build_vector into a pair of horizontal add/sub
6486 // if we can simply emit a pair of scalar add/sub.
6487 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6490 // Convert this build_vector into two horizontal add/sub followed by
6492 bool isUndefLO = NumUndefsLO == Half;
6493 bool isUndefHI = NumUndefsHI == Half;
6494 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6495 isUndefLO, isUndefHI);
6502 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6505 MVT VT = Op.getSimpleValueType();
6506 MVT ExtVT = VT.getVectorElementType();
6507 unsigned NumElems = Op.getNumOperands();
6509 // Generate vectors for predicate vectors.
6510 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6511 return LowerBUILD_VECTORvXi1(Op, DAG);
6513 // Vectors containing all zeros can be matched by pxor and xorps later
6514 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6515 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6516 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6517 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6520 return getZeroVector(VT, Subtarget, DAG, dl);
6523 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6524 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6525 // vpcmpeqd on 256-bit vectors.
6526 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6527 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6530 if (!VT.is512BitVector())
6531 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6534 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6535 if (Broadcast.getNode())
6538 unsigned EVTBits = ExtVT.getSizeInBits();
6540 unsigned NumZero = 0;
6541 unsigned NumNonZero = 0;
6542 unsigned NonZeros = 0;
6543 bool IsAllConstants = true;
6544 SmallSet<SDValue, 8> Values;
6545 for (unsigned i = 0; i < NumElems; ++i) {
6546 SDValue Elt = Op.getOperand(i);
6547 if (Elt.getOpcode() == ISD::UNDEF)
6550 if (Elt.getOpcode() != ISD::Constant &&
6551 Elt.getOpcode() != ISD::ConstantFP)
6552 IsAllConstants = false;
6553 if (X86::isZeroNode(Elt))
6556 NonZeros |= (1 << i);
6561 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6562 if (NumNonZero == 0)
6563 return DAG.getUNDEF(VT);
6565 // Special case for single non-zero, non-undef, element.
6566 if (NumNonZero == 1) {
6567 unsigned Idx = countTrailingZeros(NonZeros);
6568 SDValue Item = Op.getOperand(Idx);
6570 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6571 // the value are obviously zero, truncate the value to i32 and do the
6572 // insertion that way. Only do this if the value is non-constant or if the
6573 // value is a constant being inserted into element 0. It is cheaper to do
6574 // a constant pool load than it is to do a movd + shuffle.
6575 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6576 (!IsAllConstants || Idx == 0)) {
6577 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6579 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6580 EVT VecVT = MVT::v4i32;
6581 unsigned VecElts = 4;
6583 // Truncate the value (which may itself be a constant) to i32, and
6584 // convert it to a vector with movd (S2V+shuffle to zero extend).
6585 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6586 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6587 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6589 // Now we have our 32-bit value zero extended in the low element of
6590 // a vector. If Idx != 0, swizzle it into place.
6592 SmallVector<int, 4> Mask;
6593 Mask.push_back(Idx);
6594 for (unsigned i = 1; i != VecElts; ++i)
6596 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6599 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6603 // If we have a constant or non-constant insertion into the low element of
6604 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6605 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6606 // depending on what the source datatype is.
6609 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6611 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6612 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6613 if (VT.is256BitVector() || VT.is512BitVector()) {
6614 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6615 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6616 Item, DAG.getIntPtrConstant(0));
6618 assert(VT.is128BitVector() && "Expected an SSE value type!");
6619 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6620 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6621 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6624 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6625 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6626 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6627 if (VT.is256BitVector()) {
6628 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6629 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6631 assert(VT.is128BitVector() && "Expected an SSE value type!");
6632 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6634 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6638 // Is it a vector logical left shift?
6639 if (NumElems == 2 && Idx == 1 &&
6640 X86::isZeroNode(Op.getOperand(0)) &&
6641 !X86::isZeroNode(Op.getOperand(1))) {
6642 unsigned NumBits = VT.getSizeInBits();
6643 return getVShift(true, VT,
6644 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6645 VT, Op.getOperand(1)),
6646 NumBits/2, DAG, *this, dl);
6649 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6652 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6653 // is a non-constant being inserted into an element other than the low one,
6654 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6655 // movd/movss) to move this into the low element, then shuffle it into
6657 if (EVTBits == 32) {
6658 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6660 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6661 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6662 SmallVector<int, 8> MaskVec;
6663 for (unsigned i = 0; i != NumElems; ++i)
6664 MaskVec.push_back(i == Idx ? 0 : 1);
6665 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6669 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6670 if (Values.size() == 1) {
6671 if (EVTBits == 32) {
6672 // Instead of a shuffle like this:
6673 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6674 // Check if it's possible to issue this instead.
6675 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6676 unsigned Idx = countTrailingZeros(NonZeros);
6677 SDValue Item = Op.getOperand(Idx);
6678 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6679 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6684 // A vector full of immediates; various special cases are already
6685 // handled, so this is best done with a single constant-pool load.
6689 // For AVX-length vectors, build the individual 128-bit pieces and use
6690 // shuffles to put them in place.
6691 if (VT.is256BitVector() || VT.is512BitVector()) {
6692 SmallVector<SDValue, 64> V;
6693 for (unsigned i = 0; i != NumElems; ++i)
6694 V.push_back(Op.getOperand(i));
6696 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6698 // Build both the lower and upper subvector.
6699 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6700 makeArrayRef(&V[0], NumElems/2));
6701 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6702 makeArrayRef(&V[NumElems / 2], NumElems/2));
6704 // Recreate the wider vector with the lower and upper part.
6705 if (VT.is256BitVector())
6706 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6707 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6710 // Let legalizer expand 2-wide build_vectors.
6711 if (EVTBits == 64) {
6712 if (NumNonZero == 1) {
6713 // One half is zero or undef.
6714 unsigned Idx = countTrailingZeros(NonZeros);
6715 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6716 Op.getOperand(Idx));
6717 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6722 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6723 if (EVTBits == 8 && NumElems == 16) {
6724 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6726 if (V.getNode()) return V;
6729 if (EVTBits == 16 && NumElems == 8) {
6730 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6732 if (V.getNode()) return V;
6735 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6736 if (EVTBits == 32 && NumElems == 4) {
6737 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6738 NumZero, DAG, Subtarget, *this);
6743 // If element VT is == 32 bits, turn it into a number of shuffles.
6744 SmallVector<SDValue, 8> V(NumElems);
6745 if (NumElems == 4 && NumZero > 0) {
6746 for (unsigned i = 0; i < 4; ++i) {
6747 bool isZero = !(NonZeros & (1 << i));
6749 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6751 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6754 for (unsigned i = 0; i < 2; ++i) {
6755 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6758 V[i] = V[i*2]; // Must be a zero vector.
6761 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6764 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6767 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6772 bool Reverse1 = (NonZeros & 0x3) == 2;
6773 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6777 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6778 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6780 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6783 if (Values.size() > 1 && VT.is128BitVector()) {
6784 // Check for a build vector of consecutive loads.
6785 for (unsigned i = 0; i < NumElems; ++i)
6786 V[i] = Op.getOperand(i);
6788 // Check for elements which are consecutive loads.
6789 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6793 // Check for a build vector from mostly shuffle plus few inserting.
6794 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6798 // For SSE 4.1, use insertps to put the high elements into the low element.
6799 if (getSubtarget()->hasSSE41()) {
6801 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6802 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6804 Result = DAG.getUNDEF(VT);
6806 for (unsigned i = 1; i < NumElems; ++i) {
6807 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6808 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6809 Op.getOperand(i), DAG.getIntPtrConstant(i));
6814 // Otherwise, expand into a number of unpckl*, start by extending each of
6815 // our (non-undef) elements to the full vector width with the element in the
6816 // bottom slot of the vector (which generates no code for SSE).
6817 for (unsigned i = 0; i < NumElems; ++i) {
6818 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6819 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6821 V[i] = DAG.getUNDEF(VT);
6824 // Next, we iteratively mix elements, e.g. for v4f32:
6825 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6826 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6827 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6828 unsigned EltStride = NumElems >> 1;
6829 while (EltStride != 0) {
6830 for (unsigned i = 0; i < EltStride; ++i) {
6831 // If V[i+EltStride] is undef and this is the first round of mixing,
6832 // then it is safe to just drop this shuffle: V[i] is already in the
6833 // right place, the one element (since it's the first round) being
6834 // inserted as undef can be dropped. This isn't safe for successive
6835 // rounds because they will permute elements within both vectors.
6836 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6837 EltStride == NumElems/2)
6840 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6849 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6850 // to create 256-bit vectors from two other 128-bit ones.
6851 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6853 MVT ResVT = Op.getSimpleValueType();
6855 assert((ResVT.is256BitVector() ||
6856 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6858 SDValue V1 = Op.getOperand(0);
6859 SDValue V2 = Op.getOperand(1);
6860 unsigned NumElems = ResVT.getVectorNumElements();
6861 if(ResVT.is256BitVector())
6862 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6864 if (Op.getNumOperands() == 4) {
6865 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6866 ResVT.getVectorNumElements()/2);
6867 SDValue V3 = Op.getOperand(2);
6868 SDValue V4 = Op.getOperand(3);
6869 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6870 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6872 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6875 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6876 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6877 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6878 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6879 Op.getNumOperands() == 4)));
6881 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6882 // from two other 128-bit ones.
6884 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6885 return LowerAVXCONCAT_VECTORS(Op, DAG);
6889 //===----------------------------------------------------------------------===//
6890 // Vector shuffle lowering
6892 // This is an experimental code path for lowering vector shuffles on x86. It is
6893 // designed to handle arbitrary vector shuffles and blends, gracefully
6894 // degrading performance as necessary. It works hard to recognize idiomatic
6895 // shuffles and lower them to optimal instruction patterns without leaving
6896 // a framework that allows reasonably efficient handling of all vector shuffle
6898 //===----------------------------------------------------------------------===//
6900 /// \brief Tiny helper function to identify a no-op mask.
6902 /// This is a somewhat boring predicate function. It checks whether the mask
6903 /// array input, which is assumed to be a single-input shuffle mask of the kind
6904 /// used by the X86 shuffle instructions (not a fully general
6905 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6906 /// in-place shuffle are 'no-op's.
6907 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6908 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6909 if (Mask[i] != -1 && Mask[i] != i)
6914 /// \brief Helper function to classify a mask as a single-input mask.
6916 /// This isn't a generic single-input test because in the vector shuffle
6917 /// lowering we canonicalize single inputs to be the first input operand. This
6918 /// means we can more quickly test for a single input by only checking whether
6919 /// an input from the second operand exists. We also assume that the size of
6920 /// mask corresponds to the size of the input vectors which isn't true in the
6921 /// fully general case.
6922 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6924 if (M >= (int)Mask.size())
6929 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6931 /// This helper function produces an 8-bit shuffle immediate corresponding to
6932 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6933 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6936 /// NB: We rely heavily on "undef" masks preserving the input lane.
6937 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
6938 SelectionDAG &DAG) {
6939 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6940 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6941 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6942 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6943 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6946 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6947 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6948 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6949 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6950 return DAG.getConstant(Imm, MVT::i8);
6953 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
6955 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
6956 /// support for floating point shuffles but not integer shuffles. These
6957 /// instructions will incur a domain crossing penalty on some chips though so
6958 /// it is better to avoid lowering through this for integer vectors where
6960 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
6961 const X86Subtarget *Subtarget,
6962 SelectionDAG &DAG) {
6964 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
6965 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
6966 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
6967 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6968 ArrayRef<int> Mask = SVOp->getMask();
6969 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
6971 if (isSingleInputShuffleMask(Mask)) {
6972 // Straight shuffle of a single input vector. Simulate this by using the
6973 // single input as both of the "inputs" to this instruction..
6974 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
6975 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
6976 DAG.getConstant(SHUFPDMask, MVT::i8));
6978 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
6979 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
6981 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
6982 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
6983 DAG.getConstant(SHUFPDMask, MVT::i8));
6986 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
6988 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
6989 /// the integer unit to minimize domain crossing penalties. However, for blends
6990 /// it falls back to the floating point shuffle operation with appropriate bit
6992 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
6993 const X86Subtarget *Subtarget,
6994 SelectionDAG &DAG) {
6996 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
6997 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
6998 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
6999 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7000 ArrayRef<int> Mask = SVOp->getMask();
7001 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7003 if (isSingleInputShuffleMask(Mask)) {
7004 // Straight shuffle of a single input vector. For everything from SSE2
7005 // onward this has a single fast instruction with no scary immediates.
7006 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7007 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7008 int WidenedMask[4] = {
7009 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7010 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7012 ISD::BITCAST, DL, MVT::v2i64,
7013 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7014 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7017 // We implement this with SHUFPD which is pretty lame because it will likely
7018 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7019 // However, all the alternatives are still more cycles and newer chips don't
7020 // have this problem. It would be really nice if x86 had better shuffles here.
7021 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7022 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7023 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7024 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7027 /// \brief Lower 4-lane 32-bit floating point shuffles.
7029 /// Uses instructions exclusively from the floating point unit to minimize
7030 /// domain crossing penalties, as these are sufficient to implement all v4f32
7032 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7033 const X86Subtarget *Subtarget,
7034 SelectionDAG &DAG) {
7036 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7037 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7038 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7039 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7040 ArrayRef<int> Mask = SVOp->getMask();
7041 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7043 SDValue LowV = V1, HighV = V2;
7044 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7047 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7049 if (NumV2Elements == 0)
7050 // Straight shuffle of a single input vector. We pass the input vector to
7051 // both operands to simulate this with a SHUFPS.
7052 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7053 getV4X86ShuffleImm8ForMask(Mask, DAG));
7055 if (NumV2Elements == 1) {
7057 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7059 // Compute the index adjacent to V2Index and in the same half by toggling
7061 int V2AdjIndex = V2Index ^ 1;
7063 if (Mask[V2AdjIndex] == -1) {
7064 // Handles all the cases where we have a single V2 element and an undef.
7065 // This will only ever happen in the high lanes because we commute the
7066 // vector otherwise.
7068 std::swap(LowV, HighV);
7069 NewMask[V2Index] -= 4;
7071 // Handle the case where the V2 element ends up adjacent to a V1 element.
7072 // To make this work, blend them together as the first step.
7073 int V1Index = V2AdjIndex;
7074 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7075 V2 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V2, V1,
7076 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7078 // Now proceed to reconstruct the final blend as we have the necessary
7079 // high or low half formed.
7086 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7087 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7089 } else if (NumV2Elements == 2) {
7090 if (Mask[0] < 4 && Mask[1] < 4) {
7091 // Handle the easy case where we have V1 in the low lanes and V2 in the
7092 // high lanes. We never see this reversed because we sort the shuffle.
7096 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7097 // trying to place elements directly, just blend them and set up the final
7098 // shuffle to place them.
7100 // The first two blend mask elements are for V1, the second two are for
7102 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7103 Mask[2] < 4 ? Mask[2] : Mask[3],
7104 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7105 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7106 V1 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V2,
7107 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7109 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7112 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7113 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7114 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7115 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7118 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, LowV, HighV,
7119 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7122 /// \brief Lower 4-lane i32 vector shuffles.
7124 /// We try to handle these with integer-domain shuffles where we can, but for
7125 /// blends we use the floating point domain blend instructions.
7126 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7127 const X86Subtarget *Subtarget,
7128 SelectionDAG &DAG) {
7130 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7131 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7132 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7133 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7134 ArrayRef<int> Mask = SVOp->getMask();
7135 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7137 if (isSingleInputShuffleMask(Mask))
7138 // Straight shuffle of a single input vector. For everything from SSE2
7139 // onward this has a single fast instruction with no scary immediates.
7140 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7141 getV4X86ShuffleImm8ForMask(Mask, DAG));
7143 // We implement this with SHUFPS because it can blend from two vectors.
7144 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7145 // up the inputs, bypassing domain shift penalties that we would encur if we
7146 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7148 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7149 DAG.getVectorShuffle(
7151 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7152 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7155 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7156 /// shuffle lowering, and the most complex part.
7158 /// The lowering strategy is to try to form pairs of input lanes which are
7159 /// targeted at the same half of the final vector, and then use a dword shuffle
7160 /// to place them onto the right half, and finally unpack the paired lanes into
7161 /// their final position.
7163 /// The exact breakdown of how to form these dword pairs and align them on the
7164 /// correct sides is really tricky. See the comments within the function for
7165 /// more of the details.
7166 static SDValue lowerV8I16SingleInputVectorShuffle(
7167 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
7168 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7169 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7170 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7171 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7173 SmallVector<int, 4> LoInputs;
7174 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7175 [](int M) { return M >= 0; });
7176 std::sort(LoInputs.begin(), LoInputs.end());
7177 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7178 SmallVector<int, 4> HiInputs;
7179 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7180 [](int M) { return M >= 0; });
7181 std::sort(HiInputs.begin(), HiInputs.end());
7182 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7184 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7185 int NumHToL = LoInputs.size() - NumLToL;
7187 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7188 int NumHToH = HiInputs.size() - NumLToH;
7189 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7190 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7191 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7192 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7194 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7195 // such inputs we can swap two of the dwords across the half mark and end up
7196 // with <=2 inputs to each half in each half. Once there, we can fall through
7197 // to the generic code below. For example:
7199 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7200 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7202 // Before we had 3-1 in the low half and 3-1 in the high half. Afterward, 2-2
7204 auto balanceSides = [&](ArrayRef<int> ThreeInputs, int OneInput,
7205 int ThreeInputHalfSum, int OneInputHalfOffset) {
7206 // Compute the index of dword with only one word among the three inputs in
7207 // a half by taking the sum of the half with three inputs and subtracting
7208 // the sum of the actual three inputs. The difference is the remaining
7210 int DWordA = (ThreeInputHalfSum -
7211 std::accumulate(ThreeInputs.begin(), ThreeInputs.end(), 0)) /
7213 int DWordB = OneInputHalfOffset / 2 + (OneInput / 2 + 1) % 2;
7215 int PSHUFDMask[] = {0, 1, 2, 3};
7216 PSHUFDMask[DWordA] = DWordB;
7217 PSHUFDMask[DWordB] = DWordA;
7218 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7219 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7220 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7221 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7223 // Adjust the mask to match the new locations of A and B.
7225 if (M != -1 && M/2 == DWordA)
7226 M = 2 * DWordB + M % 2;
7227 else if (M != -1 && M/2 == DWordB)
7228 M = 2 * DWordA + M % 2;
7230 // Recurse back into this routine to re-compute state now that this isn't
7231 // a 3 and 1 problem.
7232 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7235 if (NumLToL == 3 && NumHToL == 1)
7236 return balanceSides(LToLInputs, HToLInputs[0], 0 + 1 + 2 + 3, 4);
7237 else if (NumLToL == 1 && NumHToL == 3)
7238 return balanceSides(HToLInputs, LToLInputs[0], 4 + 5 + 6 + 7, 0);
7239 else if (NumLToH == 1 && NumHToH == 3)
7240 return balanceSides(HToHInputs, LToHInputs[0], 4 + 5 + 6 + 7, 0);
7241 else if (NumLToH == 3 && NumHToH == 1)
7242 return balanceSides(LToHInputs, HToHInputs[0], 0 + 1 + 2 + 3, 4);
7244 // At this point there are at most two inputs to the low and high halves from
7245 // each half. That means the inputs can always be grouped into dwords and
7246 // those dwords can then be moved to the correct half with a dword shuffle.
7247 // We use at most one low and one high word shuffle to collect these paired
7248 // inputs into dwords, and finally a dword shuffle to place them.
7249 int PSHUFLMask[4] = {-1, -1, -1, -1};
7250 int PSHUFHMask[4] = {-1, -1, -1, -1};
7251 int PSHUFDMask[4] = {-1, -1, -1, -1};
7253 // First fix the masks for all the inputs that are staying in their
7254 // original halves. This will then dictate the targets of the cross-half
7256 auto fixInPlaceInputs = [&PSHUFDMask](
7257 ArrayRef<int> InPlaceInputs, MutableArrayRef<int> SourceHalfMask,
7258 MutableArrayRef<int> HalfMask, int HalfOffset) {
7259 if (InPlaceInputs.empty())
7261 if (InPlaceInputs.size() == 1) {
7262 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7263 InPlaceInputs[0] - HalfOffset;
7264 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
7268 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
7269 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7270 InPlaceInputs[0] - HalfOffset;
7271 // Put the second input next to the first so that they are packed into
7272 // a dword. We find the adjacent index by toggling the low bit.
7273 int AdjIndex = InPlaceInputs[0] ^ 1;
7274 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
7275 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
7276 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
7278 if (!HToLInputs.empty())
7279 fixInPlaceInputs(LToLInputs, PSHUFLMask, LoMask, 0);
7280 if (!LToHInputs.empty())
7281 fixInPlaceInputs(HToHInputs, PSHUFHMask, HiMask, 4);
7283 // Now gather the cross-half inputs and place them into a free dword of
7284 // their target half.
7285 // FIXME: This operation could almost certainly be simplified dramatically to
7286 // look more like the 3-1 fixing operation.
7287 auto moveInputsToRightHalf = [&PSHUFDMask](
7288 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
7289 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
7290 int SourceOffset, int DestOffset) {
7291 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
7292 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
7294 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
7296 int LowWord = Word & ~1;
7297 int HighWord = Word | 1;
7298 return isWordClobbered(SourceHalfMask, LowWord) ||
7299 isWordClobbered(SourceHalfMask, HighWord);
7302 if (IncomingInputs.empty())
7305 if (ExistingInputs.empty()) {
7306 // Map any dwords with inputs from them into the right half.
7307 for (int Input : IncomingInputs) {
7308 // If the source half mask maps over the inputs, turn those into
7309 // swaps and use the swapped lane.
7310 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
7311 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
7312 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
7313 Input - SourceOffset;
7314 // We have to swap the uses in our half mask in one sweep.
7315 for (int &M : HalfMask)
7316 if (M == SourceHalfMask[Input - SourceOffset])
7318 else if (M == Input)
7319 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7321 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
7322 Input - SourceOffset &&
7323 "Previous placement doesn't match!");
7325 // Note that this correctly re-maps both when we do a swap and when
7326 // we observe the other side of the swap above. We rely on that to
7327 // avoid swapping the members of the input list directly.
7328 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7331 // Map the input's dword into the correct half.
7332 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
7333 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
7335 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
7337 "Previous placement doesn't match!");
7340 // And just directly shift any other-half mask elements to be same-half
7341 // as we will have mirrored the dword containing the element into the
7342 // same position within that half.
7343 for (int &M : HalfMask)
7344 if (M >= SourceOffset && M < SourceOffset + 4) {
7345 M = M - SourceOffset + DestOffset;
7346 assert(M >= 0 && "This should never wrap below zero!");
7351 // Ensure we have the input in a viable dword of its current half. This
7352 // is particularly tricky because the original position may be clobbered
7353 // by inputs being moved and *staying* in that half.
7354 if (IncomingInputs.size() == 1) {
7355 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7356 int InputFixed = std::find(std::begin(SourceHalfMask),
7357 std::end(SourceHalfMask), -1) -
7358 std::begin(SourceHalfMask) + SourceOffset;
7359 SourceHalfMask[InputFixed - SourceOffset] =
7360 IncomingInputs[0] - SourceOffset;
7361 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
7363 IncomingInputs[0] = InputFixed;
7365 } else if (IncomingInputs.size() == 2) {
7366 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
7367 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7368 int SourceDWordBase = !isDWordClobbered(SourceHalfMask, 0) ? 0 : 2;
7369 assert(!isDWordClobbered(SourceHalfMask, SourceDWordBase) &&
7370 "Not all dwords can be clobbered!");
7371 SourceHalfMask[SourceDWordBase] = IncomingInputs[0] - SourceOffset;
7372 SourceHalfMask[SourceDWordBase + 1] = IncomingInputs[1] - SourceOffset;
7373 for (int &M : HalfMask)
7374 if (M == IncomingInputs[0])
7375 M = SourceDWordBase + SourceOffset;
7376 else if (M == IncomingInputs[1])
7377 M = SourceDWordBase + 1 + SourceOffset;
7378 IncomingInputs[0] = SourceDWordBase + SourceOffset;
7379 IncomingInputs[1] = SourceDWordBase + 1 + SourceOffset;
7382 llvm_unreachable("Unhandled input size!");
7385 // Now hoist the DWord down to the right half.
7386 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
7387 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
7388 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
7389 for (int Input : IncomingInputs)
7390 std::replace(HalfMask.begin(), HalfMask.end(), Input,
7391 FreeDWord * 2 + Input % 2);
7393 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask,
7394 /*SourceOffset*/ 4, /*DestOffset*/ 0);
7395 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask,
7396 /*SourceOffset*/ 0, /*DestOffset*/ 4);
7398 // Now enact all the shuffles we've computed to move the inputs into their
7400 if (!isNoopShuffleMask(PSHUFLMask))
7401 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7402 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
7403 if (!isNoopShuffleMask(PSHUFHMask))
7404 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7405 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
7406 if (!isNoopShuffleMask(PSHUFDMask))
7407 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7408 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7409 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7410 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7412 // At this point, each half should contain all its inputs, and we can then
7413 // just shuffle them into their final position.
7414 assert(std::count_if(LoMask.begin(), LoMask.end(),
7415 [](int M) { return M >= 4; }) == 0 &&
7416 "Failed to lift all the high half inputs to the low mask!");
7417 assert(std::count_if(HiMask.begin(), HiMask.end(),
7418 [](int M) { return M >= 0 && M < 4; }) == 0 &&
7419 "Failed to lift all the low half inputs to the high mask!");
7421 // Do a half shuffle for the low mask.
7422 if (!isNoopShuffleMask(LoMask))
7423 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7424 getV4X86ShuffleImm8ForMask(LoMask, DAG));
7426 // Do a half shuffle with the high mask after shifting its values down.
7427 for (int &M : HiMask)
7430 if (!isNoopShuffleMask(HiMask))
7431 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7432 getV4X86ShuffleImm8ForMask(HiMask, DAG));
7437 /// \brief Detect whether the mask pattern should be lowered through
7440 /// This essentially tests whether viewing the mask as an interleaving of two
7441 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
7442 /// lowering it through interleaving is a significantly better strategy.
7443 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
7444 int NumEvenInputs[2] = {0, 0};
7445 int NumOddInputs[2] = {0, 0};
7446 int NumLoInputs[2] = {0, 0};
7447 int NumHiInputs[2] = {0, 0};
7448 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7452 int InputIdx = Mask[i] >= Size;
7455 ++NumLoInputs[InputIdx];
7457 ++NumHiInputs[InputIdx];
7460 ++NumEvenInputs[InputIdx];
7462 ++NumOddInputs[InputIdx];
7465 // The minimum number of cross-input results for both the interleaved and
7466 // split cases. If interleaving results in fewer cross-input results, return
7468 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
7469 NumEvenInputs[0] + NumOddInputs[1]);
7470 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
7471 NumLoInputs[0] + NumHiInputs[1]);
7472 return InterleavedCrosses < SplitCrosses;
7475 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
7477 /// This strategy only works when the inputs from each vector fit into a single
7478 /// half of that vector, and generally there are not so many inputs as to leave
7479 /// the in-place shuffles required highly constrained (and thus expensive). It
7480 /// shifts all the inputs into a single side of both input vectors and then
7481 /// uses an unpack to interleave these inputs in a single vector. At that
7482 /// point, we will fall back on the generic single input shuffle lowering.
7483 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
7485 MutableArrayRef<int> Mask,
7486 const X86Subtarget *Subtarget,
7487 SelectionDAG &DAG) {
7488 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7489 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7490 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
7491 for (int i = 0; i < 8; ++i)
7492 if (Mask[i] >= 0 && Mask[i] < 4)
7493 LoV1Inputs.push_back(i);
7494 else if (Mask[i] >= 4 && Mask[i] < 8)
7495 HiV1Inputs.push_back(i);
7496 else if (Mask[i] >= 8 && Mask[i] < 12)
7497 LoV2Inputs.push_back(i);
7498 else if (Mask[i] >= 12)
7499 HiV2Inputs.push_back(i);
7501 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
7502 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
7505 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
7506 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
7507 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
7509 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
7510 HiV1Inputs.size() + HiV2Inputs.size();
7512 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
7513 ArrayRef<int> HiInputs, bool MoveToLo,
7515 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
7516 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
7517 if (BadInputs.empty())
7520 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
7521 int MoveOffset = MoveToLo ? 0 : 4;
7523 if (GoodInputs.empty()) {
7524 for (int BadInput : BadInputs) {
7525 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
7526 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
7529 if (GoodInputs.size() == 2) {
7530 // If the low inputs are spread across two dwords, pack them into
7532 MoveMask[Mask[GoodInputs[0]] % 2 + MoveOffset] =
7533 Mask[GoodInputs[0]] - MaskOffset;
7534 MoveMask[Mask[GoodInputs[1]] % 2 + MoveOffset] =
7535 Mask[GoodInputs[1]] - MaskOffset;
7536 Mask[GoodInputs[0]] = Mask[GoodInputs[0]] % 2 + MoveOffset + MaskOffset;
7537 Mask[GoodInputs[1]] = Mask[GoodInputs[0]] % 2 + MoveOffset + MaskOffset;
7539 // Otherwise pin the low inputs.
7540 for (int GoodInput : GoodInputs)
7541 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
7545 std::find(std::begin(MoveMask) + MoveOffset, std::end(MoveMask), -1) -
7546 std::begin(MoveMask);
7547 assert(MoveMaskIdx >= MoveOffset && "Established above");
7549 if (BadInputs.size() == 2) {
7550 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
7551 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
7552 MoveMask[MoveMaskIdx + Mask[BadInputs[0]] % 2] =
7553 Mask[BadInputs[0]] - MaskOffset;
7554 MoveMask[MoveMaskIdx + Mask[BadInputs[1]] % 2] =
7555 Mask[BadInputs[1]] - MaskOffset;
7556 Mask[BadInputs[0]] = MoveMaskIdx + Mask[BadInputs[0]] % 2 + MaskOffset;
7557 Mask[BadInputs[1]] = MoveMaskIdx + Mask[BadInputs[1]] % 2 + MaskOffset;
7559 assert(BadInputs.size() == 1 && "All sizes handled");
7560 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
7561 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
7565 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7568 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
7570 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
7573 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
7574 // cross-half traffic in the final shuffle.
7576 // Munge the mask to be a single-input mask after the unpack merges the
7580 M = 2 * (M % 4) + (M / 8);
7582 return DAG.getVectorShuffle(
7583 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7584 DL, MVT::v8i16, V1, V2),
7585 DAG.getUNDEF(MVT::v8i16), Mask);
7588 /// \brief Generic lowering of 8-lane i16 shuffles.
7590 /// This handles both single-input shuffles and combined shuffle/blends with
7591 /// two inputs. The single input shuffles are immediately delegated to
7592 /// a dedicated lowering routine.
7594 /// The blends are lowered in one of three fundamental ways. If there are few
7595 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
7596 /// of the input is significantly cheaper when lowered as an interleaving of
7597 /// the two inputs, try to interleave them. Otherwise, blend the low and high
7598 /// halves of the inputs separately (making them have relatively few inputs)
7599 /// and then concatenate them.
7600 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7601 const X86Subtarget *Subtarget,
7602 SelectionDAG &DAG) {
7604 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
7605 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7606 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7607 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7608 ArrayRef<int> OrigMask = SVOp->getMask();
7609 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7610 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
7611 MutableArrayRef<int> Mask(MaskStorage);
7613 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
7615 auto isV1 = [](int M) { return M >= 0 && M < 8; };
7616 auto isV2 = [](int M) { return M >= 8; };
7618 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
7619 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
7621 if (NumV2Inputs == 0)
7622 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
7624 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
7625 "to be V1-input shuffles.");
7627 if (NumV1Inputs + NumV2Inputs <= 4)
7628 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
7630 // Check whether an interleaving lowering is likely to be more efficient.
7631 // This isn't perfect but it is a strong heuristic that tends to work well on
7632 // the kinds of shuffles that show up in practice.
7634 // FIXME: Handle 1x, 2x, and 4x interleaving.
7635 if (shouldLowerAsInterleaving(Mask)) {
7636 // FIXME: Figure out whether we should pack these into the low or high
7639 int EMask[8], OMask[8];
7640 for (int i = 0; i < 4; ++i) {
7641 EMask[i] = Mask[2*i];
7642 OMask[i] = Mask[2*i + 1];
7647 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
7648 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
7650 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
7653 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7654 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7656 for (int i = 0; i < 4; ++i) {
7657 LoBlendMask[i] = Mask[i];
7658 HiBlendMask[i] = Mask[i + 4];
7661 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
7662 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
7663 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
7664 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
7666 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7667 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
7670 /// \brief Generic lowering of v16i8 shuffles.
7672 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
7673 /// detect any complexity reducing interleaving. If that doesn't help, it uses
7674 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
7675 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
7677 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7678 const X86Subtarget *Subtarget,
7679 SelectionDAG &DAG) {
7681 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
7682 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7683 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7684 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7685 ArrayRef<int> OrigMask = SVOp->getMask();
7686 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
7687 int MaskStorage[16] = {
7688 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7689 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
7690 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
7691 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
7692 MutableArrayRef<int> Mask(MaskStorage);
7693 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
7694 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
7696 // For single-input shuffles, there are some nicer lowering tricks we can use.
7697 if (isSingleInputShuffleMask(Mask)) {
7698 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
7699 // Notably, this handles splat and partial-splat shuffles more efficiently.
7700 // However, it only makes sense if the pre-duplication shuffle simplifies
7701 // things significantly. Currently, this means we need to be able to
7702 // express the pre-duplication shuffle as an i16 shuffle.
7704 // FIXME: We should check for other patterns which can be widened into an
7705 // i16 shuffle as well.
7706 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
7707 for (int i = 0; i < 16; i += 2) {
7708 if (Mask[i] != Mask[i + 1])
7713 auto tryToWidenViaDuplication = [&]() -> SDValue {
7714 if (!canWidenViaDuplication(Mask))
7716 SmallVector<int, 4> LoInputs;
7717 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
7718 [](int M) { return M >= 0 && M < 8; });
7719 std::sort(LoInputs.begin(), LoInputs.end());
7720 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
7722 SmallVector<int, 4> HiInputs;
7723 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
7724 [](int M) { return M >= 8; });
7725 std::sort(HiInputs.begin(), HiInputs.end());
7726 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
7729 bool TargetLo = LoInputs.size() >= HiInputs.size();
7730 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
7731 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
7733 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
7734 SmallDenseMap<int, int, 8> LaneMap;
7735 for (int I : InPlaceInputs) {
7736 PreDupI16Shuffle[I/2] = I/2;
7739 int j = TargetLo ? 0 : 4, je = j + 4;
7740 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
7741 // Check if j is already a shuffle of this input. This happens when
7742 // there are two adjacent bytes after we move the low one.
7743 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
7744 // If we haven't yet mapped the input, search for a slot into which
7746 while (j < je && PreDupI16Shuffle[j] != -1)
7750 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
7753 // Map this input with the i16 shuffle.
7754 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
7757 // Update the lane map based on the mapping we ended up with.
7758 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
7761 ISD::BITCAST, DL, MVT::v16i8,
7762 DAG.getVectorShuffle(MVT::v8i16, DL,
7763 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
7764 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
7766 // Unpack the bytes to form the i16s that will be shuffled into place.
7767 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7768 MVT::v16i8, V1, V1);
7770 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7771 for (int i = 0; i < 16; i += 2) {
7773 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
7774 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
7777 ISD::BITCAST, DL, MVT::v16i8,
7778 DAG.getVectorShuffle(MVT::v8i16, DL,
7779 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
7780 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
7782 if (SDValue V = tryToWidenViaDuplication())
7786 // Check whether an interleaving lowering is likely to be more efficient.
7787 // This isn't perfect but it is a strong heuristic that tends to work well on
7788 // the kinds of shuffles that show up in practice.
7790 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
7791 if (shouldLowerAsInterleaving(Mask)) {
7792 // FIXME: Figure out whether we should pack these into the low or high
7795 int EMask[16], OMask[16];
7796 for (int i = 0; i < 8; ++i) {
7797 EMask[i] = Mask[2*i];
7798 OMask[i] = Mask[2*i + 1];
7803 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
7804 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
7806 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
7809 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7810 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7811 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7812 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7814 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
7815 MutableArrayRef<int> V1HalfBlendMask,
7816 MutableArrayRef<int> V2HalfBlendMask) {
7817 for (int i = 0; i < 8; ++i)
7818 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
7819 V1HalfBlendMask[i] = HalfMask[i];
7821 } else if (HalfMask[i] >= 16) {
7822 V2HalfBlendMask[i] = HalfMask[i] - 16;
7823 HalfMask[i] = i + 8;
7826 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
7827 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
7829 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
7831 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
7832 MutableArrayRef<int> HiBlendMask) {
7834 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
7835 // them out and avoid using UNPCK{L,H} to extract the elements of V as
7837 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
7838 [](int M) { return M >= 0 && M % 2 == 1; }) &&
7839 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
7840 [](int M) { return M >= 0 && M % 2 == 1; })) {
7841 // Use a mask to drop the high bytes.
7842 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
7843 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
7844 DAG.getConstant(0x00FF, MVT::v8i16));
7846 // This will be a single vector shuffle instead of a blend so nuke V2.
7847 V2 = DAG.getUNDEF(MVT::v8i16);
7849 // Squash the masks to point directly into V1.
7850 for (int &M : LoBlendMask)
7853 for (int &M : HiBlendMask)
7857 // Otherwise just unpack the low half of V into V1 and the high half into
7858 // V2 so that we can blend them as i16s.
7859 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7860 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
7861 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7862 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
7865 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
7866 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
7867 return std::make_pair(BlendedLo, BlendedHi);
7869 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
7870 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
7871 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
7873 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
7874 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
7876 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
7879 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
7881 /// This routine breaks down the specific type of 128-bit shuffle and
7882 /// dispatches to the lowering routines accordingly.
7883 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7884 MVT VT, const X86Subtarget *Subtarget,
7885 SelectionDAG &DAG) {
7886 switch (VT.SimpleTy) {
7888 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
7890 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
7892 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
7894 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
7896 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
7898 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
7901 llvm_unreachable("Unimplemented!");
7905 /// \brief Tiny helper function to test whether adjacent masks are sequential.
7906 static bool areAdjacentMasksSequential(ArrayRef<int> Mask) {
7907 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
7908 if (Mask[i] + 1 != Mask[i+1])
7914 /// \brief Top-level lowering for x86 vector shuffles.
7916 /// This handles decomposition, canonicalization, and lowering of all x86
7917 /// vector shuffles. Most of the specific lowering strategies are encapsulated
7918 /// above in helper routines. The canonicalization attempts to widen shuffles
7919 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
7920 /// s.t. only one of the two inputs needs to be tested, etc.
7921 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7922 SelectionDAG &DAG) {
7923 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7924 ArrayRef<int> Mask = SVOp->getMask();
7925 SDValue V1 = Op.getOperand(0);
7926 SDValue V2 = Op.getOperand(1);
7927 MVT VT = Op.getSimpleValueType();
7928 int NumElements = VT.getVectorNumElements();
7931 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7933 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7934 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7935 if (V1IsUndef && V2IsUndef)
7936 return DAG.getUNDEF(VT);
7938 // When we create a shuffle node we put the UNDEF node to second operand,
7939 // but in some cases the first operand may be transformed to UNDEF.
7940 // In this case we should just commute the node.
7942 return DAG.getCommutedVectorShuffle(*SVOp);
7944 // Check for non-undef masks pointing at an undef vector and make the masks
7945 // undef as well. This makes it easier to match the shuffle based solely on
7949 if (M >= NumElements) {
7950 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
7951 for (int &M : NewMask)
7952 if (M >= NumElements)
7954 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
7957 // For integer vector shuffles, try to collapse them into a shuffle of fewer
7958 // lanes but wider integers. We cap this to not form integers larger than i64
7959 // but it might be interesting to form i128 integers to handle flipping the
7960 // low and high halves of AVX 256-bit vectors.
7961 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
7962 areAdjacentMasksSequential(Mask)) {
7963 SmallVector<int, 8> NewMask;
7964 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
7965 NewMask.push_back(Mask[i] / 2);
7967 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
7968 VT.getVectorNumElements() / 2);
7969 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
7970 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
7971 return DAG.getNode(ISD::BITCAST, dl, VT,
7972 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
7975 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
7976 for (int M : SVOp->getMask())
7979 else if (M < NumElements)
7984 // Commute the shuffle as needed such that more elements come from V1 than
7985 // V2. This allows us to match the shuffle pattern strictly on how many
7986 // elements come from V1 without handling the symmetric cases.
7987 if (NumV2Elements > NumV1Elements)
7988 return DAG.getCommutedVectorShuffle(*SVOp);
7990 // When the number of V1 and V2 elements are the same, try to minimize the
7991 // number of uses of V2 in the low half of the vector.
7992 if (NumV1Elements == NumV2Elements) {
7993 int LowV1Elements = 0, LowV2Elements = 0;
7994 for (int M : SVOp->getMask().slice(0, NumElements / 2))
7995 if (M >= NumElements)
7999 if (LowV2Elements > LowV1Elements)
8000 return DAG.getCommutedVectorShuffle(*SVOp);
8003 // For each vector width, delegate to a specialized lowering routine.
8004 if (VT.getSizeInBits() == 128)
8005 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
8007 llvm_unreachable("Unimplemented!");
8011 //===----------------------------------------------------------------------===//
8012 // Legacy vector shuffle lowering
8014 // This code is the legacy code handling vector shuffles until the above
8015 // replaces its functionality and performance.
8016 //===----------------------------------------------------------------------===//
8018 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
8019 bool hasInt256, unsigned *MaskOut = nullptr) {
8020 MVT EltVT = VT.getVectorElementType();
8022 // There is no blend with immediate in AVX-512.
8023 if (VT.is512BitVector())
8026 if (!hasSSE41 || EltVT == MVT::i8)
8028 if (!hasInt256 && VT == MVT::v16i16)
8031 unsigned MaskValue = 0;
8032 unsigned NumElems = VT.getVectorNumElements();
8033 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
8034 unsigned NumLanes = (NumElems - 1) / 8 + 1;
8035 unsigned NumElemsInLane = NumElems / NumLanes;
8037 // Blend for v16i16 should be symetric for the both lanes.
8038 for (unsigned i = 0; i < NumElemsInLane; ++i) {
8040 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
8041 int EltIdx = MaskVals[i];
8043 if ((EltIdx < 0 || EltIdx == (int)i) &&
8044 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
8047 if (((unsigned)EltIdx == (i + NumElems)) &&
8048 (SndLaneEltIdx < 0 ||
8049 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
8050 MaskValue |= (1 << i);
8056 *MaskOut = MaskValue;
8060 // Try to lower a shuffle node into a simple blend instruction.
8061 // This function assumes isBlendMask returns true for this
8062 // SuffleVectorSDNode
8063 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
8065 const X86Subtarget *Subtarget,
8066 SelectionDAG &DAG) {
8067 MVT VT = SVOp->getSimpleValueType(0);
8068 MVT EltVT = VT.getVectorElementType();
8069 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
8070 Subtarget->hasInt256() && "Trying to lower a "
8071 "VECTOR_SHUFFLE to a Blend but "
8072 "with the wrong mask"));
8073 SDValue V1 = SVOp->getOperand(0);
8074 SDValue V2 = SVOp->getOperand(1);
8076 unsigned NumElems = VT.getVectorNumElements();
8078 // Convert i32 vectors to floating point if it is not AVX2.
8079 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
8081 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
8082 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
8084 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
8085 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
8088 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
8089 DAG.getConstant(MaskValue, MVT::i32));
8090 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
8093 /// In vector type \p VT, return true if the element at index \p InputIdx
8094 /// falls on a different 128-bit lane than \p OutputIdx.
8095 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
8096 unsigned OutputIdx) {
8097 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
8098 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
8101 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
8102 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
8103 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
8104 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
8106 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
8107 SelectionDAG &DAG) {
8108 MVT VT = V1.getSimpleValueType();
8109 assert(VT.is128BitVector() || VT.is256BitVector());
8111 MVT EltVT = VT.getVectorElementType();
8112 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
8113 unsigned NumElts = VT.getVectorNumElements();
8115 SmallVector<SDValue, 32> PshufbMask;
8116 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
8117 int InputIdx = MaskVals[OutputIdx];
8118 unsigned InputByteIdx;
8120 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
8121 InputByteIdx = 0x80;
8123 // Cross lane is not allowed.
8124 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
8126 InputByteIdx = InputIdx * EltSizeInBytes;
8127 // Index is an byte offset within the 128-bit lane.
8128 InputByteIdx &= 0xf;
8131 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
8132 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
8133 if (InputByteIdx != 0x80)
8138 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
8140 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
8141 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
8142 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
8145 // v8i16 shuffles - Prefer shuffles in the following order:
8146 // 1. [all] pshuflw, pshufhw, optional move
8147 // 2. [ssse3] 1 x pshufb
8148 // 3. [ssse3] 2 x pshufb + 1 x por
8149 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
8151 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
8152 SelectionDAG &DAG) {
8153 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8154 SDValue V1 = SVOp->getOperand(0);
8155 SDValue V2 = SVOp->getOperand(1);
8157 SmallVector<int, 8> MaskVals;
8159 // Determine if more than 1 of the words in each of the low and high quadwords
8160 // of the result come from the same quadword of one of the two inputs. Undef
8161 // mask values count as coming from any quadword, for better codegen.
8163 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
8164 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
8165 unsigned LoQuad[] = { 0, 0, 0, 0 };
8166 unsigned HiQuad[] = { 0, 0, 0, 0 };
8167 // Indices of quads used.
8168 std::bitset<4> InputQuads;
8169 for (unsigned i = 0; i < 8; ++i) {
8170 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
8171 int EltIdx = SVOp->getMaskElt(i);
8172 MaskVals.push_back(EltIdx);
8181 InputQuads.set(EltIdx / 4);
8184 int BestLoQuad = -1;
8185 unsigned MaxQuad = 1;
8186 for (unsigned i = 0; i < 4; ++i) {
8187 if (LoQuad[i] > MaxQuad) {
8189 MaxQuad = LoQuad[i];
8193 int BestHiQuad = -1;
8195 for (unsigned i = 0; i < 4; ++i) {
8196 if (HiQuad[i] > MaxQuad) {
8198 MaxQuad = HiQuad[i];
8202 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
8203 // of the two input vectors, shuffle them into one input vector so only a
8204 // single pshufb instruction is necessary. If there are more than 2 input
8205 // quads, disable the next transformation since it does not help SSSE3.
8206 bool V1Used = InputQuads[0] || InputQuads[1];
8207 bool V2Used = InputQuads[2] || InputQuads[3];
8208 if (Subtarget->hasSSSE3()) {
8209 if (InputQuads.count() == 2 && V1Used && V2Used) {
8210 BestLoQuad = InputQuads[0] ? 0 : 1;
8211 BestHiQuad = InputQuads[2] ? 2 : 3;
8213 if (InputQuads.count() > 2) {
8219 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
8220 // the shuffle mask. If a quad is scored as -1, that means that it contains
8221 // words from all 4 input quadwords.
8223 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
8225 BestLoQuad < 0 ? 0 : BestLoQuad,
8226 BestHiQuad < 0 ? 1 : BestHiQuad
8228 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
8229 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
8230 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
8231 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
8233 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
8234 // source words for the shuffle, to aid later transformations.
8235 bool AllWordsInNewV = true;
8236 bool InOrder[2] = { true, true };
8237 for (unsigned i = 0; i != 8; ++i) {
8238 int idx = MaskVals[i];
8240 InOrder[i/4] = false;
8241 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
8243 AllWordsInNewV = false;
8247 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
8248 if (AllWordsInNewV) {
8249 for (int i = 0; i != 8; ++i) {
8250 int idx = MaskVals[i];
8253 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
8254 if ((idx != i) && idx < 4)
8256 if ((idx != i) && idx > 3)
8265 // If we've eliminated the use of V2, and the new mask is a pshuflw or
8266 // pshufhw, that's as cheap as it gets. Return the new shuffle.
8267 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
8268 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
8269 unsigned TargetMask = 0;
8270 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
8271 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
8272 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8273 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
8274 getShufflePSHUFLWImmediate(SVOp);
8275 V1 = NewV.getOperand(0);
8276 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
8280 // Promote splats to a larger type which usually leads to more efficient code.
8281 // FIXME: Is this true if pshufb is available?
8282 if (SVOp->isSplat())
8283 return PromoteSplat(SVOp, DAG);
8285 // If we have SSSE3, and all words of the result are from 1 input vector,
8286 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
8287 // is present, fall back to case 4.
8288 if (Subtarget->hasSSSE3()) {
8289 SmallVector<SDValue,16> pshufbMask;
8291 // If we have elements from both input vectors, set the high bit of the
8292 // shuffle mask element to zero out elements that come from V2 in the V1
8293 // mask, and elements that come from V1 in the V2 mask, so that the two
8294 // results can be OR'd together.
8295 bool TwoInputs = V1Used && V2Used;
8296 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
8298 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8300 // Calculate the shuffle mask for the second input, shuffle it, and
8301 // OR it with the first shuffled input.
8302 CommuteVectorShuffleMask(MaskVals, 8);
8303 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
8304 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8305 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8308 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
8309 // and update MaskVals with new element order.
8310 std::bitset<8> InOrder;
8311 if (BestLoQuad >= 0) {
8312 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
8313 for (int i = 0; i != 4; ++i) {
8314 int idx = MaskVals[i];
8317 } else if ((idx / 4) == BestLoQuad) {
8322 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8325 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8326 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8327 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
8329 getShufflePSHUFLWImmediate(SVOp), DAG);
8333 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
8334 // and update MaskVals with the new element order.
8335 if (BestHiQuad >= 0) {
8336 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
8337 for (unsigned i = 4; i != 8; ++i) {
8338 int idx = MaskVals[i];
8341 } else if ((idx / 4) == BestHiQuad) {
8342 MaskV[i] = (idx & 3) + 4;
8346 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8349 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8350 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8351 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
8353 getShufflePSHUFHWImmediate(SVOp), DAG);
8357 // In case BestHi & BestLo were both -1, which means each quadword has a word
8358 // from each of the four input quadwords, calculate the InOrder bitvector now
8359 // before falling through to the insert/extract cleanup.
8360 if (BestLoQuad == -1 && BestHiQuad == -1) {
8362 for (int i = 0; i != 8; ++i)
8363 if (MaskVals[i] < 0 || MaskVals[i] == i)
8367 // The other elements are put in the right place using pextrw and pinsrw.
8368 for (unsigned i = 0; i != 8; ++i) {
8371 int EltIdx = MaskVals[i];
8374 SDValue ExtOp = (EltIdx < 8) ?
8375 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
8376 DAG.getIntPtrConstant(EltIdx)) :
8377 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
8378 DAG.getIntPtrConstant(EltIdx - 8));
8379 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
8380 DAG.getIntPtrConstant(i));
8385 /// \brief v16i16 shuffles
8387 /// FIXME: We only support generation of a single pshufb currently. We can
8388 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
8389 /// well (e.g 2 x pshufb + 1 x por).
8391 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
8392 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8393 SDValue V1 = SVOp->getOperand(0);
8394 SDValue V2 = SVOp->getOperand(1);
8397 if (V2.getOpcode() != ISD::UNDEF)
8400 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
8401 return getPSHUFB(MaskVals, V1, dl, DAG);
8404 // v16i8 shuffles - Prefer shuffles in the following order:
8405 // 1. [ssse3] 1 x pshufb
8406 // 2. [ssse3] 2 x pshufb + 1 x por
8407 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
8408 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
8409 const X86Subtarget* Subtarget,
8410 SelectionDAG &DAG) {
8411 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8412 SDValue V1 = SVOp->getOperand(0);
8413 SDValue V2 = SVOp->getOperand(1);
8415 ArrayRef<int> MaskVals = SVOp->getMask();
8417 // Promote splats to a larger type which usually leads to more efficient code.
8418 // FIXME: Is this true if pshufb is available?
8419 if (SVOp->isSplat())
8420 return PromoteSplat(SVOp, DAG);
8422 // If we have SSSE3, case 1 is generated when all result bytes come from
8423 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
8424 // present, fall back to case 3.
8426 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
8427 if (Subtarget->hasSSSE3()) {
8428 SmallVector<SDValue,16> pshufbMask;
8430 // If all result elements are from one input vector, then only translate
8431 // undef mask values to 0x80 (zero out result) in the pshufb mask.
8433 // Otherwise, we have elements from both input vectors, and must zero out
8434 // elements that come from V2 in the first mask, and V1 in the second mask
8435 // so that we can OR them together.
8436 for (unsigned i = 0; i != 16; ++i) {
8437 int EltIdx = MaskVals[i];
8438 if (EltIdx < 0 || EltIdx >= 16)
8440 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
8442 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
8443 DAG.getNode(ISD::BUILD_VECTOR, dl,
8444 MVT::v16i8, pshufbMask));
8446 // As PSHUFB will zero elements with negative indices, it's safe to ignore
8447 // the 2nd operand if it's undefined or zero.
8448 if (V2.getOpcode() == ISD::UNDEF ||
8449 ISD::isBuildVectorAllZeros(V2.getNode()))
8452 // Calculate the shuffle mask for the second input, shuffle it, and
8453 // OR it with the first shuffled input.
8455 for (unsigned i = 0; i != 16; ++i) {
8456 int EltIdx = MaskVals[i];
8457 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
8458 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
8460 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
8461 DAG.getNode(ISD::BUILD_VECTOR, dl,
8462 MVT::v16i8, pshufbMask));
8463 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8466 // No SSSE3 - Calculate in place words and then fix all out of place words
8467 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
8468 // the 16 different words that comprise the two doublequadword input vectors.
8469 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8470 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
8472 for (int i = 0; i != 8; ++i) {
8473 int Elt0 = MaskVals[i*2];
8474 int Elt1 = MaskVals[i*2+1];
8476 // This word of the result is all undef, skip it.
8477 if (Elt0 < 0 && Elt1 < 0)
8480 // This word of the result is already in the correct place, skip it.
8481 if ((Elt0 == i*2) && (Elt1 == i*2+1))
8484 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
8485 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
8488 // If Elt0 and Elt1 are defined, are consecutive, and can be load
8489 // using a single extract together, load it and store it.
8490 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
8491 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
8492 DAG.getIntPtrConstant(Elt1 / 2));
8493 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
8494 DAG.getIntPtrConstant(i));
8498 // If Elt1 is defined, extract it from the appropriate source. If the
8499 // source byte is not also odd, shift the extracted word left 8 bits
8500 // otherwise clear the bottom 8 bits if we need to do an or.
8502 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
8503 DAG.getIntPtrConstant(Elt1 / 2));
8504 if ((Elt1 & 1) == 0)
8505 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
8507 TLI.getShiftAmountTy(InsElt.getValueType())));
8509 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
8510 DAG.getConstant(0xFF00, MVT::i16));
8512 // If Elt0 is defined, extract it from the appropriate source. If the
8513 // source byte is not also even, shift the extracted word right 8 bits. If
8514 // Elt1 was also defined, OR the extracted values together before
8515 // inserting them in the result.
8517 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
8518 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
8519 if ((Elt0 & 1) != 0)
8520 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
8522 TLI.getShiftAmountTy(InsElt0.getValueType())));
8524 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
8525 DAG.getConstant(0x00FF, MVT::i16));
8526 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
8529 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
8530 DAG.getIntPtrConstant(i));
8532 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
8535 // v32i8 shuffles - Translate to VPSHUFB if possible.
8537 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
8538 const X86Subtarget *Subtarget,
8539 SelectionDAG &DAG) {
8540 MVT VT = SVOp->getSimpleValueType(0);
8541 SDValue V1 = SVOp->getOperand(0);
8542 SDValue V2 = SVOp->getOperand(1);
8544 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
8546 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
8547 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
8548 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
8550 // VPSHUFB may be generated if
8551 // (1) one of input vector is undefined or zeroinitializer.
8552 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
8553 // And (2) the mask indexes don't cross the 128-bit lane.
8554 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
8555 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
8558 if (V1IsAllZero && !V2IsAllZero) {
8559 CommuteVectorShuffleMask(MaskVals, 32);
8562 return getPSHUFB(MaskVals, V1, dl, DAG);
8565 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
8566 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
8567 /// done when every pair / quad of shuffle mask elements point to elements in
8568 /// the right sequence. e.g.
8569 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
8571 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
8572 SelectionDAG &DAG) {
8573 MVT VT = SVOp->getSimpleValueType(0);
8575 unsigned NumElems = VT.getVectorNumElements();
8578 switch (VT.SimpleTy) {
8579 default: llvm_unreachable("Unexpected!");
8582 return SDValue(SVOp, 0);
8583 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
8584 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
8585 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
8586 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
8587 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
8588 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
8591 SmallVector<int, 8> MaskVec;
8592 for (unsigned i = 0; i != NumElems; i += Scale) {
8594 for (unsigned j = 0; j != Scale; ++j) {
8595 int EltIdx = SVOp->getMaskElt(i+j);
8599 StartIdx = (EltIdx / Scale);
8600 if (EltIdx != (int)(StartIdx*Scale + j))
8603 MaskVec.push_back(StartIdx);
8606 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
8607 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
8608 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
8611 /// getVZextMovL - Return a zero-extending vector move low node.
8613 static SDValue getVZextMovL(MVT VT, MVT OpVT,
8614 SDValue SrcOp, SelectionDAG &DAG,
8615 const X86Subtarget *Subtarget, SDLoc dl) {
8616 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
8617 LoadSDNode *LD = nullptr;
8618 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
8619 LD = dyn_cast<LoadSDNode>(SrcOp);
8621 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
8623 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
8624 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
8625 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
8626 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
8627 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
8629 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
8630 return DAG.getNode(ISD::BITCAST, dl, VT,
8631 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
8632 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8640 return DAG.getNode(ISD::BITCAST, dl, VT,
8641 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
8642 DAG.getNode(ISD::BITCAST, dl,
8646 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
8647 /// which could not be matched by any known target speficic shuffle
8649 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
8651 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
8652 if (NewOp.getNode())
8655 MVT VT = SVOp->getSimpleValueType(0);
8657 unsigned NumElems = VT.getVectorNumElements();
8658 unsigned NumLaneElems = NumElems / 2;
8661 MVT EltVT = VT.getVectorElementType();
8662 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
8665 SmallVector<int, 16> Mask;
8666 for (unsigned l = 0; l < 2; ++l) {
8667 // Build a shuffle mask for the output, discovering on the fly which
8668 // input vectors to use as shuffle operands (recorded in InputUsed).
8669 // If building a suitable shuffle vector proves too hard, then bail
8670 // out with UseBuildVector set.
8671 bool UseBuildVector = false;
8672 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
8673 unsigned LaneStart = l * NumLaneElems;
8674 for (unsigned i = 0; i != NumLaneElems; ++i) {
8675 // The mask element. This indexes into the input.
8676 int Idx = SVOp->getMaskElt(i+LaneStart);
8678 // the mask element does not index into any input vector.
8683 // The input vector this mask element indexes into.
8684 int Input = Idx / NumLaneElems;
8686 // Turn the index into an offset from the start of the input vector.
8687 Idx -= Input * NumLaneElems;
8689 // Find or create a shuffle vector operand to hold this input.
8691 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
8692 if (InputUsed[OpNo] == Input)
8693 // This input vector is already an operand.
8695 if (InputUsed[OpNo] < 0) {
8696 // Create a new operand for this input vector.
8697 InputUsed[OpNo] = Input;
8702 if (OpNo >= array_lengthof(InputUsed)) {
8703 // More than two input vectors used! Give up on trying to create a
8704 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
8705 UseBuildVector = true;
8709 // Add the mask index for the new shuffle vector.
8710 Mask.push_back(Idx + OpNo * NumLaneElems);
8713 if (UseBuildVector) {
8714 SmallVector<SDValue, 16> SVOps;
8715 for (unsigned i = 0; i != NumLaneElems; ++i) {
8716 // The mask element. This indexes into the input.
8717 int Idx = SVOp->getMaskElt(i+LaneStart);
8719 SVOps.push_back(DAG.getUNDEF(EltVT));
8723 // The input vector this mask element indexes into.
8724 int Input = Idx / NumElems;
8726 // Turn the index into an offset from the start of the input vector.
8727 Idx -= Input * NumElems;
8729 // Extract the vector element by hand.
8730 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
8731 SVOp->getOperand(Input),
8732 DAG.getIntPtrConstant(Idx)));
8735 // Construct the output using a BUILD_VECTOR.
8736 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
8737 } else if (InputUsed[0] < 0) {
8738 // No input vectors were used! The result is undefined.
8739 Output[l] = DAG.getUNDEF(NVT);
8741 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
8742 (InputUsed[0] % 2) * NumLaneElems,
8744 // If only one input was used, use an undefined vector for the other.
8745 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
8746 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
8747 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
8748 // At least one input vector was used. Create a new shuffle vector.
8749 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
8755 // Concatenate the result back
8756 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
8759 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
8760 /// 4 elements, and match them with several different shuffle types.
8762 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
8763 SDValue V1 = SVOp->getOperand(0);
8764 SDValue V2 = SVOp->getOperand(1);
8766 MVT VT = SVOp->getSimpleValueType(0);
8768 assert(VT.is128BitVector() && "Unsupported vector size");
8770 std::pair<int, int> Locs[4];
8771 int Mask1[] = { -1, -1, -1, -1 };
8772 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
8776 for (unsigned i = 0; i != 4; ++i) {
8777 int Idx = PermMask[i];
8779 Locs[i] = std::make_pair(-1, -1);
8781 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
8783 Locs[i] = std::make_pair(0, NumLo);
8787 Locs[i] = std::make_pair(1, NumHi);
8789 Mask1[2+NumHi] = Idx;
8795 if (NumLo <= 2 && NumHi <= 2) {
8796 // If no more than two elements come from either vector. This can be
8797 // implemented with two shuffles. First shuffle gather the elements.
8798 // The second shuffle, which takes the first shuffle as both of its
8799 // vector operands, put the elements into the right order.
8800 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
8802 int Mask2[] = { -1, -1, -1, -1 };
8804 for (unsigned i = 0; i != 4; ++i)
8805 if (Locs[i].first != -1) {
8806 unsigned Idx = (i < 2) ? 0 : 4;
8807 Idx += Locs[i].first * 2 + Locs[i].second;
8811 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
8814 if (NumLo == 3 || NumHi == 3) {
8815 // Otherwise, we must have three elements from one vector, call it X, and
8816 // one element from the other, call it Y. First, use a shufps to build an
8817 // intermediate vector with the one element from Y and the element from X
8818 // that will be in the same half in the final destination (the indexes don't
8819 // matter). Then, use a shufps to build the final vector, taking the half
8820 // containing the element from Y from the intermediate, and the other half
8823 // Normalize it so the 3 elements come from V1.
8824 CommuteVectorShuffleMask(PermMask, 4);
8828 // Find the element from V2.
8830 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
8831 int Val = PermMask[HiIndex];
8838 Mask1[0] = PermMask[HiIndex];
8840 Mask1[2] = PermMask[HiIndex^1];
8842 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
8845 Mask1[0] = PermMask[0];
8846 Mask1[1] = PermMask[1];
8847 Mask1[2] = HiIndex & 1 ? 6 : 4;
8848 Mask1[3] = HiIndex & 1 ? 4 : 6;
8849 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
8852 Mask1[0] = HiIndex & 1 ? 2 : 0;
8853 Mask1[1] = HiIndex & 1 ? 0 : 2;
8854 Mask1[2] = PermMask[2];
8855 Mask1[3] = PermMask[3];
8860 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
8863 // Break it into (shuffle shuffle_hi, shuffle_lo).
8864 int LoMask[] = { -1, -1, -1, -1 };
8865 int HiMask[] = { -1, -1, -1, -1 };
8867 int *MaskPtr = LoMask;
8868 unsigned MaskIdx = 0;
8871 for (unsigned i = 0; i != 4; ++i) {
8878 int Idx = PermMask[i];
8880 Locs[i] = std::make_pair(-1, -1);
8881 } else if (Idx < 4) {
8882 Locs[i] = std::make_pair(MaskIdx, LoIdx);
8883 MaskPtr[LoIdx] = Idx;
8886 Locs[i] = std::make_pair(MaskIdx, HiIdx);
8887 MaskPtr[HiIdx] = Idx;
8892 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
8893 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
8894 int MaskOps[] = { -1, -1, -1, -1 };
8895 for (unsigned i = 0; i != 4; ++i)
8896 if (Locs[i].first != -1)
8897 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
8898 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
8901 static bool MayFoldVectorLoad(SDValue V) {
8902 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
8903 V = V.getOperand(0);
8905 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
8906 V = V.getOperand(0);
8907 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
8908 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
8909 // BUILD_VECTOR (load), undef
8910 V = V.getOperand(0);
8912 return MayFoldLoad(V);
8916 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
8917 MVT VT = Op.getSimpleValueType();
8919 // Canonizalize to v2f64.
8920 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
8921 return DAG.getNode(ISD::BITCAST, dl, VT,
8922 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
8927 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
8929 SDValue V1 = Op.getOperand(0);
8930 SDValue V2 = Op.getOperand(1);
8931 MVT VT = Op.getSimpleValueType();
8933 assert(VT != MVT::v2i64 && "unsupported shuffle type");
8935 if (HasSSE2 && VT == MVT::v2f64)
8936 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
8938 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
8939 return DAG.getNode(ISD::BITCAST, dl, VT,
8940 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
8941 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
8942 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
8946 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
8947 SDValue V1 = Op.getOperand(0);
8948 SDValue V2 = Op.getOperand(1);
8949 MVT VT = Op.getSimpleValueType();
8951 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
8952 "unsupported shuffle type");
8954 if (V2.getOpcode() == ISD::UNDEF)
8958 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
8962 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
8963 SDValue V1 = Op.getOperand(0);
8964 SDValue V2 = Op.getOperand(1);
8965 MVT VT = Op.getSimpleValueType();
8966 unsigned NumElems = VT.getVectorNumElements();
8968 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
8969 // operand of these instructions is only memory, so check if there's a
8970 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
8972 bool CanFoldLoad = false;
8974 // Trivial case, when V2 comes from a load.
8975 if (MayFoldVectorLoad(V2))
8978 // When V1 is a load, it can be folded later into a store in isel, example:
8979 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
8981 // (MOVLPSmr addr:$src1, VR128:$src2)
8982 // So, recognize this potential and also use MOVLPS or MOVLPD
8983 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
8986 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8988 if (HasSSE2 && NumElems == 2)
8989 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
8992 // If we don't care about the second element, proceed to use movss.
8993 if (SVOp->getMaskElt(1) != -1)
8994 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
8997 // movl and movlp will both match v2i64, but v2i64 is never matched by
8998 // movl earlier because we make it strict to avoid messing with the movlp load
8999 // folding logic (see the code above getMOVLP call). Match it here then,
9000 // this is horrible, but will stay like this until we move all shuffle
9001 // matching to x86 specific nodes. Note that for the 1st condition all
9002 // types are matched with movsd.
9004 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
9005 // as to remove this logic from here, as much as possible
9006 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
9007 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9008 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9011 assert(VT != MVT::v4i32 && "unsupported shuffle type");
9013 // Invert the operand order and use SHUFPS to match it.
9014 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
9015 getShuffleSHUFImmediate(SVOp), DAG);
9018 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
9019 SelectionDAG &DAG) {
9021 MVT VT = Load->getSimpleValueType(0);
9022 MVT EVT = VT.getVectorElementType();
9023 SDValue Addr = Load->getOperand(1);
9024 SDValue NewAddr = DAG.getNode(
9025 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
9026 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
9029 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
9030 DAG.getMachineFunction().getMachineMemOperand(
9031 Load->getMemOperand(), 0, EVT.getStoreSize()));
9035 // It is only safe to call this function if isINSERTPSMask is true for
9036 // this shufflevector mask.
9037 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
9038 SelectionDAG &DAG) {
9039 // Generate an insertps instruction when inserting an f32 from memory onto a
9040 // v4f32 or when copying a member from one v4f32 to another.
9041 // We also use it for transferring i32 from one register to another,
9042 // since it simply copies the same bits.
9043 // If we're transferring an i32 from memory to a specific element in a
9044 // register, we output a generic DAG that will match the PINSRD
9046 MVT VT = SVOp->getSimpleValueType(0);
9047 MVT EVT = VT.getVectorElementType();
9048 SDValue V1 = SVOp->getOperand(0);
9049 SDValue V2 = SVOp->getOperand(1);
9050 auto Mask = SVOp->getMask();
9051 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
9052 "unsupported vector type for insertps/pinsrd");
9054 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
9055 auto FromV2Predicate = [](const int &i) { return i >= 4; };
9056 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
9064 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
9067 // If we have 1 element from each vector, we have to check if we're
9068 // changing V1's element's place. If so, we're done. Otherwise, we
9069 // should assume we're changing V2's element's place and behave
9071 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
9072 if (FromV1 == FromV2 && DestIndex == Mask[DestIndex] % 4) {
9076 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9079 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
9080 "More than one element from V1 and from V2, or no elements from one "
9081 "of the vectors. This case should not have returned true from "
9086 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9089 // Get an index into the source vector in the range [0,4) (the mask is
9090 // in the range [0,8) because it can address V1 and V2)
9091 unsigned SrcIndex = Mask[DestIndex] % 4;
9092 if (MayFoldLoad(From)) {
9093 // Trivial case, when From comes from a load and is only used by the
9094 // shuffle. Make it use insertps from the vector that we need from that
9097 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
9098 if (!NewLoad.getNode())
9101 if (EVT == MVT::f32) {
9102 // Create this as a scalar to vector to match the instruction pattern.
9103 SDValue LoadScalarToVector =
9104 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
9105 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
9106 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
9108 } else { // EVT == MVT::i32
9109 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
9110 // instruction, to match the PINSRD instruction, which loads an i32 to a
9111 // certain vector element.
9112 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
9113 DAG.getConstant(DestIndex, MVT::i32));
9117 // Vector-element-to-vector
9118 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
9119 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
9122 // Reduce a vector shuffle to zext.
9123 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
9124 SelectionDAG &DAG) {
9125 // PMOVZX is only available from SSE41.
9126 if (!Subtarget->hasSSE41())
9129 MVT VT = Op.getSimpleValueType();
9131 // Only AVX2 support 256-bit vector integer extending.
9132 if (!Subtarget->hasInt256() && VT.is256BitVector())
9135 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9137 SDValue V1 = Op.getOperand(0);
9138 SDValue V2 = Op.getOperand(1);
9139 unsigned NumElems = VT.getVectorNumElements();
9141 // Extending is an unary operation and the element type of the source vector
9142 // won't be equal to or larger than i64.
9143 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
9144 VT.getVectorElementType() == MVT::i64)
9147 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
9148 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
9149 while ((1U << Shift) < NumElems) {
9150 if (SVOp->getMaskElt(1U << Shift) == 1)
9153 // The maximal ratio is 8, i.e. from i8 to i64.
9158 // Check the shuffle mask.
9159 unsigned Mask = (1U << Shift) - 1;
9160 for (unsigned i = 0; i != NumElems; ++i) {
9161 int EltIdx = SVOp->getMaskElt(i);
9162 if ((i & Mask) != 0 && EltIdx != -1)
9164 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
9168 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
9169 MVT NeVT = MVT::getIntegerVT(NBits);
9170 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
9172 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
9175 // Simplify the operand as it's prepared to be fed into shuffle.
9176 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
9177 if (V1.getOpcode() == ISD::BITCAST &&
9178 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
9179 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
9180 V1.getOperand(0).getOperand(0)
9181 .getSimpleValueType().getSizeInBits() == SignificantBits) {
9182 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
9183 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
9184 ConstantSDNode *CIdx =
9185 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
9186 // If it's foldable, i.e. normal load with single use, we will let code
9187 // selection to fold it. Otherwise, we will short the conversion sequence.
9188 if (CIdx && CIdx->getZExtValue() == 0 &&
9189 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
9190 MVT FullVT = V.getSimpleValueType();
9191 MVT V1VT = V1.getSimpleValueType();
9192 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
9193 // The "ext_vec_elt" node is wider than the result node.
9194 // In this case we should extract subvector from V.
9195 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
9196 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
9197 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
9198 FullVT.getVectorNumElements()/Ratio);
9199 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
9200 DAG.getIntPtrConstant(0));
9202 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
9206 return DAG.getNode(ISD::BITCAST, DL, VT,
9207 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
9210 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9211 SelectionDAG &DAG) {
9212 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9213 MVT VT = Op.getSimpleValueType();
9215 SDValue V1 = Op.getOperand(0);
9216 SDValue V2 = Op.getOperand(1);
9218 if (isZeroShuffle(SVOp))
9219 return getZeroVector(VT, Subtarget, DAG, dl);
9221 // Handle splat operations
9222 if (SVOp->isSplat()) {
9223 // Use vbroadcast whenever the splat comes from a foldable load
9224 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
9225 if (Broadcast.getNode())
9229 // Check integer expanding shuffles.
9230 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
9231 if (NewOp.getNode())
9234 // If the shuffle can be profitably rewritten as a narrower shuffle, then
9236 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
9238 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9239 if (NewOp.getNode())
9240 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
9241 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
9242 // FIXME: Figure out a cleaner way to do this.
9243 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
9244 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9245 if (NewOp.getNode()) {
9246 MVT NewVT = NewOp.getSimpleValueType();
9247 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
9248 NewVT, true, false))
9249 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
9252 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
9253 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9254 if (NewOp.getNode()) {
9255 MVT NewVT = NewOp.getSimpleValueType();
9256 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
9257 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
9266 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
9267 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9268 SDValue V1 = Op.getOperand(0);
9269 SDValue V2 = Op.getOperand(1);
9270 MVT VT = Op.getSimpleValueType();
9272 unsigned NumElems = VT.getVectorNumElements();
9273 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9274 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9275 bool V1IsSplat = false;
9276 bool V2IsSplat = false;
9277 bool HasSSE2 = Subtarget->hasSSE2();
9278 bool HasFp256 = Subtarget->hasFp256();
9279 bool HasInt256 = Subtarget->hasInt256();
9280 MachineFunction &MF = DAG.getMachineFunction();
9281 bool OptForSize = MF.getFunction()->getAttributes().
9282 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
9284 // Check if we should use the experimental vector shuffle lowering. If so,
9285 // delegate completely to that code path.
9286 if (ExperimentalVectorShuffleLowering)
9287 return lowerVectorShuffle(Op, Subtarget, DAG);
9289 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9291 if (V1IsUndef && V2IsUndef)
9292 return DAG.getUNDEF(VT);
9294 // When we create a shuffle node we put the UNDEF node to second operand,
9295 // but in some cases the first operand may be transformed to UNDEF.
9296 // In this case we should just commute the node.
9298 return DAG.getCommutedVectorShuffle(*SVOp);
9300 // Vector shuffle lowering takes 3 steps:
9302 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
9303 // narrowing and commutation of operands should be handled.
9304 // 2) Matching of shuffles with known shuffle masks to x86 target specific
9306 // 3) Rewriting of unmatched masks into new generic shuffle operations,
9307 // so the shuffle can be broken into other shuffles and the legalizer can
9308 // try the lowering again.
9310 // The general idea is that no vector_shuffle operation should be left to
9311 // be matched during isel, all of them must be converted to a target specific
9314 // Normalize the input vectors. Here splats, zeroed vectors, profitable
9315 // narrowing and commutation of operands should be handled. The actual code
9316 // doesn't include all of those, work in progress...
9317 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
9318 if (NewOp.getNode())
9321 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
9323 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
9324 // unpckh_undef). Only use pshufd if speed is more important than size.
9325 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9326 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9327 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9328 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9330 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
9331 V2IsUndef && MayFoldVectorLoad(V1))
9332 return getMOVDDup(Op, dl, V1, DAG);
9334 if (isMOVHLPS_v_undef_Mask(M, VT))
9335 return getMOVHighToLow(Op, dl, DAG);
9337 // Use to match splats
9338 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
9339 (VT == MVT::v2f64 || VT == MVT::v2i64))
9340 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9342 if (isPSHUFDMask(M, VT)) {
9343 // The actual implementation will match the mask in the if above and then
9344 // during isel it can match several different instructions, not only pshufd
9345 // as its name says, sad but true, emulate the behavior for now...
9346 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
9347 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
9349 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
9351 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
9352 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
9354 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
9355 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
9358 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
9362 if (isPALIGNRMask(M, VT, Subtarget))
9363 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
9364 getShufflePALIGNRImmediate(SVOp),
9367 // Check if this can be converted into a logical shift.
9368 bool isLeft = false;
9371 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
9372 if (isShift && ShVal.hasOneUse()) {
9373 // If the shifted value has multiple uses, it may be cheaper to use
9374 // v_set0 + movlhps or movhlps, etc.
9375 MVT EltVT = VT.getVectorElementType();
9376 ShAmt *= EltVT.getSizeInBits();
9377 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9380 if (isMOVLMask(M, VT)) {
9381 if (ISD::isBuildVectorAllZeros(V1.getNode()))
9382 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
9383 if (!isMOVLPMask(M, VT)) {
9384 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
9385 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9387 if (VT == MVT::v4i32 || VT == MVT::v4f32)
9388 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9392 // FIXME: fold these into legal mask.
9393 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
9394 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
9396 if (isMOVHLPSMask(M, VT))
9397 return getMOVHighToLow(Op, dl, DAG);
9399 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
9400 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
9402 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
9403 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
9405 if (isMOVLPMask(M, VT))
9406 return getMOVLP(Op, dl, DAG, HasSSE2);
9408 if (ShouldXformToMOVHLPS(M, VT) ||
9409 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
9410 return DAG.getCommutedVectorShuffle(*SVOp);
9413 // No better options. Use a vshldq / vsrldq.
9414 MVT EltVT = VT.getVectorElementType();
9415 ShAmt *= EltVT.getSizeInBits();
9416 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9419 bool Commuted = false;
9420 // FIXME: This should also accept a bitcast of a splat? Be careful, not
9421 // 1,1,1,1 -> v8i16 though.
9422 BitVector UndefElements;
9423 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
9424 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
9426 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
9427 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
9430 // Canonicalize the splat or undef, if present, to be on the RHS.
9431 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
9432 CommuteVectorShuffleMask(M, NumElems);
9434 std::swap(V1IsSplat, V2IsSplat);
9438 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
9439 // Shuffling low element of v1 into undef, just return v1.
9442 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
9443 // the instruction selector will not match, so get a canonical MOVL with
9444 // swapped operands to undo the commute.
9445 return getMOVL(DAG, dl, VT, V2, V1);
9448 if (isUNPCKLMask(M, VT, HasInt256))
9449 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9451 if (isUNPCKHMask(M, VT, HasInt256))
9452 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9455 // Normalize mask so all entries that point to V2 points to its first
9456 // element then try to match unpck{h|l} again. If match, return a
9457 // new vector_shuffle with the corrected mask.p
9458 SmallVector<int, 8> NewMask(M.begin(), M.end());
9459 NormalizeMask(NewMask, NumElems);
9460 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
9461 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9462 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
9463 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9467 // Commute is back and try unpck* again.
9468 // FIXME: this seems wrong.
9469 CommuteVectorShuffleMask(M, NumElems);
9471 std::swap(V1IsSplat, V2IsSplat);
9473 if (isUNPCKLMask(M, VT, HasInt256))
9474 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9476 if (isUNPCKHMask(M, VT, HasInt256))
9477 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9480 // Normalize the node to match x86 shuffle ops if needed
9481 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
9482 return DAG.getCommutedVectorShuffle(*SVOp);
9484 // The checks below are all present in isShuffleMaskLegal, but they are
9485 // inlined here right now to enable us to directly emit target specific
9486 // nodes, and remove one by one until they don't return Op anymore.
9488 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
9489 SVOp->getSplatIndex() == 0 && V2IsUndef) {
9490 if (VT == MVT::v2f64 || VT == MVT::v2i64)
9491 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9494 if (isPSHUFHWMask(M, VT, HasInt256))
9495 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
9496 getShufflePSHUFHWImmediate(SVOp),
9499 if (isPSHUFLWMask(M, VT, HasInt256))
9500 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
9501 getShufflePSHUFLWImmediate(SVOp),
9505 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
9507 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
9509 if (isSHUFPMask(M, VT))
9510 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
9511 getShuffleSHUFImmediate(SVOp), DAG);
9513 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9514 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9515 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9516 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9518 //===--------------------------------------------------------------------===//
9519 // Generate target specific nodes for 128 or 256-bit shuffles only
9520 // supported in the AVX instruction set.
9523 // Handle VMOVDDUPY permutations
9524 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
9525 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
9527 // Handle VPERMILPS/D* permutations
9528 if (isVPERMILPMask(M, VT)) {
9529 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
9530 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
9531 getShuffleSHUFImmediate(SVOp), DAG);
9532 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
9533 getShuffleSHUFImmediate(SVOp), DAG);
9537 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
9538 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
9539 Idx*(NumElems/2), DAG, dl);
9541 // Handle VPERM2F128/VPERM2I128 permutations
9542 if (isVPERM2X128Mask(M, VT, HasFp256))
9543 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
9544 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
9546 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
9547 return getINSERTPS(SVOp, dl, DAG);
9550 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
9551 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
9553 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
9554 VT.is512BitVector()) {
9555 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
9556 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
9557 SmallVector<SDValue, 16> permclMask;
9558 for (unsigned i = 0; i != NumElems; ++i) {
9559 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
9562 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
9564 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
9565 return DAG.getNode(X86ISD::VPERMV, dl, VT,
9566 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
9567 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
9568 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
9571 //===--------------------------------------------------------------------===//
9572 // Since no target specific shuffle was selected for this generic one,
9573 // lower it into other known shuffles. FIXME: this isn't true yet, but
9574 // this is the plan.
9577 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
9578 if (VT == MVT::v8i16) {
9579 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
9580 if (NewOp.getNode())
9584 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
9585 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
9586 if (NewOp.getNode())
9590 if (VT == MVT::v16i8) {
9591 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
9592 if (NewOp.getNode())
9596 if (VT == MVT::v32i8) {
9597 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
9598 if (NewOp.getNode())
9602 // Handle all 128-bit wide vectors with 4 elements, and match them with
9603 // several different shuffle types.
9604 if (NumElems == 4 && VT.is128BitVector())
9605 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
9607 // Handle general 256-bit shuffles
9608 if (VT.is256BitVector())
9609 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
9614 // This function assumes its argument is a BUILD_VECTOR of constants or
9615 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
9617 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
9618 unsigned &MaskValue) {
9620 unsigned NumElems = BuildVector->getNumOperands();
9621 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9622 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9623 unsigned NumElemsInLane = NumElems / NumLanes;
9625 // Blend for v16i16 should be symetric for the both lanes.
9626 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9627 SDValue EltCond = BuildVector->getOperand(i);
9628 SDValue SndLaneEltCond =
9629 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
9631 int Lane1Cond = -1, Lane2Cond = -1;
9632 if (isa<ConstantSDNode>(EltCond))
9633 Lane1Cond = !isZero(EltCond);
9634 if (isa<ConstantSDNode>(SndLaneEltCond))
9635 Lane2Cond = !isZero(SndLaneEltCond);
9637 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
9638 // Lane1Cond != 0, means we want the first argument.
9639 // Lane1Cond == 0, means we want the second argument.
9640 // The encoding of this argument is 0 for the first argument, 1
9641 // for the second. Therefore, invert the condition.
9642 MaskValue |= !Lane1Cond << i;
9643 else if (Lane1Cond < 0)
9644 MaskValue |= !Lane2Cond << i;
9651 // Try to lower a vselect node into a simple blend instruction.
9652 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
9653 SelectionDAG &DAG) {
9654 SDValue Cond = Op.getOperand(0);
9655 SDValue LHS = Op.getOperand(1);
9656 SDValue RHS = Op.getOperand(2);
9658 MVT VT = Op.getSimpleValueType();
9659 MVT EltVT = VT.getVectorElementType();
9660 unsigned NumElems = VT.getVectorNumElements();
9662 // There is no blend with immediate in AVX-512.
9663 if (VT.is512BitVector())
9666 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
9668 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
9671 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
9674 // Check the mask for BLEND and build the value.
9675 unsigned MaskValue = 0;
9676 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
9679 // Convert i32 vectors to floating point if it is not AVX2.
9680 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9682 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9683 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9685 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
9686 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
9689 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
9690 DAG.getConstant(MaskValue, MVT::i32));
9691 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
9694 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
9695 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
9696 if (BlendOp.getNode())
9699 // Some types for vselect were previously set to Expand, not Legal or
9700 // Custom. Return an empty SDValue so we fall-through to Expand, after
9701 // the Custom lowering phase.
9702 MVT VT = Op.getSimpleValueType();
9703 switch (VT.SimpleTy) {
9711 // We couldn't create a "Blend with immediate" node.
9712 // This node should still be legal, but we'll have to emit a blendv*
9717 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
9718 MVT VT = Op.getSimpleValueType();
9721 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
9724 if (VT.getSizeInBits() == 8) {
9725 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
9726 Op.getOperand(0), Op.getOperand(1));
9727 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
9728 DAG.getValueType(VT));
9729 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
9732 if (VT.getSizeInBits() == 16) {
9733 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9734 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
9736 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
9737 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
9738 DAG.getNode(ISD::BITCAST, dl,
9742 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
9743 Op.getOperand(0), Op.getOperand(1));
9744 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
9745 DAG.getValueType(VT));
9746 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
9749 if (VT == MVT::f32) {
9750 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
9751 // the result back to FR32 register. It's only worth matching if the
9752 // result has a single use which is a store or a bitcast to i32. And in
9753 // the case of a store, it's not worth it if the index is a constant 0,
9754 // because a MOVSSmr can be used instead, which is smaller and faster.
9755 if (!Op.hasOneUse())
9757 SDNode *User = *Op.getNode()->use_begin();
9758 if ((User->getOpcode() != ISD::STORE ||
9759 (isa<ConstantSDNode>(Op.getOperand(1)) &&
9760 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
9761 (User->getOpcode() != ISD::BITCAST ||
9762 User->getValueType(0) != MVT::i32))
9764 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
9765 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
9768 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
9771 if (VT == MVT::i32 || VT == MVT::i64) {
9772 // ExtractPS/pextrq works with constant index.
9773 if (isa<ConstantSDNode>(Op.getOperand(1)))
9779 /// Extract one bit from mask vector, like v16i1 or v8i1.
9780 /// AVX-512 feature.
9782 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
9783 SDValue Vec = Op.getOperand(0);
9785 MVT VecVT = Vec.getSimpleValueType();
9786 SDValue Idx = Op.getOperand(1);
9787 MVT EltVT = Op.getSimpleValueType();
9789 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
9791 // variable index can't be handled in mask registers,
9792 // extend vector to VR512
9793 if (!isa<ConstantSDNode>(Idx)) {
9794 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
9795 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
9796 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
9797 ExtVT.getVectorElementType(), Ext, Idx);
9798 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
9801 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
9802 const TargetRegisterClass* rc = getRegClassFor(VecVT);
9803 unsigned MaxSift = rc->getSize()*8 - 1;
9804 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
9805 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
9806 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
9807 DAG.getConstant(MaxSift, MVT::i8));
9808 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
9809 DAG.getIntPtrConstant(0));
9813 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
9814 SelectionDAG &DAG) const {
9816 SDValue Vec = Op.getOperand(0);
9817 MVT VecVT = Vec.getSimpleValueType();
9818 SDValue Idx = Op.getOperand(1);
9820 if (Op.getSimpleValueType() == MVT::i1)
9821 return ExtractBitFromMaskVector(Op, DAG);
9823 if (!isa<ConstantSDNode>(Idx)) {
9824 if (VecVT.is512BitVector() ||
9825 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
9826 VecVT.getVectorElementType().getSizeInBits() == 32)) {
9829 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
9830 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
9831 MaskEltVT.getSizeInBits());
9833 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
9834 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
9835 getZeroVector(MaskVT, Subtarget, DAG, dl),
9836 Idx, DAG.getConstant(0, getPointerTy()));
9837 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
9838 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
9839 Perm, DAG.getConstant(0, getPointerTy()));
9844 // If this is a 256-bit vector result, first extract the 128-bit vector and
9845 // then extract the element from the 128-bit vector.
9846 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
9848 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
9849 // Get the 128-bit vector.
9850 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
9851 MVT EltVT = VecVT.getVectorElementType();
9853 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
9855 //if (IdxVal >= NumElems/2)
9856 // IdxVal -= NumElems/2;
9857 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
9858 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
9859 DAG.getConstant(IdxVal, MVT::i32));
9862 assert(VecVT.is128BitVector() && "Unexpected vector length");
9864 if (Subtarget->hasSSE41()) {
9865 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
9870 MVT VT = Op.getSimpleValueType();
9871 // TODO: handle v16i8.
9872 if (VT.getSizeInBits() == 16) {
9873 SDValue Vec = Op.getOperand(0);
9874 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9876 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
9877 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
9878 DAG.getNode(ISD::BITCAST, dl,
9881 // Transform it so it match pextrw which produces a 32-bit result.
9882 MVT EltVT = MVT::i32;
9883 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
9884 Op.getOperand(0), Op.getOperand(1));
9885 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
9886 DAG.getValueType(VT));
9887 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
9890 if (VT.getSizeInBits() == 32) {
9891 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9895 // SHUFPS the element to the lowest double word, then movss.
9896 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
9897 MVT VVT = Op.getOperand(0).getSimpleValueType();
9898 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
9899 DAG.getUNDEF(VVT), Mask);
9900 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
9901 DAG.getIntPtrConstant(0));
9904 if (VT.getSizeInBits() == 64) {
9905 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
9906 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
9907 // to match extract_elt for f64.
9908 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9912 // UNPCKHPD the element to the lowest double word, then movsd.
9913 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
9914 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
9915 int Mask[2] = { 1, -1 };
9916 MVT VVT = Op.getOperand(0).getSimpleValueType();
9917 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
9918 DAG.getUNDEF(VVT), Mask);
9919 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
9920 DAG.getIntPtrConstant(0));
9926 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
9927 MVT VT = Op.getSimpleValueType();
9928 MVT EltVT = VT.getVectorElementType();
9931 SDValue N0 = Op.getOperand(0);
9932 SDValue N1 = Op.getOperand(1);
9933 SDValue N2 = Op.getOperand(2);
9935 if (!VT.is128BitVector())
9938 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
9939 isa<ConstantSDNode>(N2)) {
9941 if (VT == MVT::v8i16)
9942 Opc = X86ISD::PINSRW;
9943 else if (VT == MVT::v16i8)
9944 Opc = X86ISD::PINSRB;
9946 Opc = X86ISD::PINSRB;
9948 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
9950 if (N1.getValueType() != MVT::i32)
9951 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
9952 if (N2.getValueType() != MVT::i32)
9953 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
9954 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
9957 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
9958 // Bits [7:6] of the constant are the source select. This will always be
9959 // zero here. The DAG Combiner may combine an extract_elt index into these
9960 // bits. For example (insert (extract, 3), 2) could be matched by putting
9961 // the '3' into bits [7:6] of X86ISD::INSERTPS.
9962 // Bits [5:4] of the constant are the destination select. This is the
9963 // value of the incoming immediate.
9964 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
9965 // combine either bitwise AND or insert of float 0.0 to set these bits.
9966 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
9967 // Create this as a scalar to vector..
9968 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
9969 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
9972 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
9973 // PINSR* works with constant index.
9979 /// Insert one bit to mask vector, like v16i1 or v8i1.
9980 /// AVX-512 feature.
9982 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
9984 SDValue Vec = Op.getOperand(0);
9985 SDValue Elt = Op.getOperand(1);
9986 SDValue Idx = Op.getOperand(2);
9987 MVT VecVT = Vec.getSimpleValueType();
9989 if (!isa<ConstantSDNode>(Idx)) {
9990 // Non constant index. Extend source and destination,
9991 // insert element and then truncate the result.
9992 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
9993 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
9994 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
9995 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
9996 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
9997 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10000 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10001 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10002 if (Vec.getOpcode() == ISD::UNDEF)
10003 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10004 DAG.getConstant(IdxVal, MVT::i8));
10005 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10006 unsigned MaxSift = rc->getSize()*8 - 1;
10007 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10008 DAG.getConstant(MaxSift, MVT::i8));
10009 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10010 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10011 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10014 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
10015 MVT VT = Op.getSimpleValueType();
10016 MVT EltVT = VT.getVectorElementType();
10018 if (EltVT == MVT::i1)
10019 return InsertBitToMaskVector(Op, DAG);
10022 SDValue N0 = Op.getOperand(0);
10023 SDValue N1 = Op.getOperand(1);
10024 SDValue N2 = Op.getOperand(2);
10026 // If this is a 256-bit vector result, first extract the 128-bit vector,
10027 // insert the element into the extracted half and then place it back.
10028 if (VT.is256BitVector() || VT.is512BitVector()) {
10029 if (!isa<ConstantSDNode>(N2))
10032 // Get the desired 128-bit vector half.
10033 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
10034 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10036 // Insert the element into the desired half.
10037 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
10038 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
10040 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10041 DAG.getConstant(IdxIn128, MVT::i32));
10043 // Insert the changed part back to the 256-bit vector
10044 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10047 if (Subtarget->hasSSE41())
10048 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
10050 if (EltVT == MVT::i8)
10053 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
10054 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10055 // as its second argument.
10056 if (N1.getValueType() != MVT::i32)
10057 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10058 if (N2.getValueType() != MVT::i32)
10059 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10060 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10065 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10067 MVT OpVT = Op.getSimpleValueType();
10069 // If this is a 256-bit vector result, first insert into a 128-bit
10070 // vector and then insert into the 256-bit vector.
10071 if (!OpVT.is128BitVector()) {
10072 // Insert into a 128-bit vector.
10073 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10074 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10075 OpVT.getVectorNumElements() / SizeFactor);
10077 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10079 // Insert the 128-bit vector.
10080 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10083 if (OpVT == MVT::v1i64 &&
10084 Op.getOperand(0).getValueType() == MVT::i64)
10085 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10087 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10088 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10089 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10090 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10093 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10094 // a simple subregister reference or explicit instructions to grab
10095 // upper bits of a vector.
10096 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10097 SelectionDAG &DAG) {
10099 SDValue In = Op.getOperand(0);
10100 SDValue Idx = Op.getOperand(1);
10101 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10102 MVT ResVT = Op.getSimpleValueType();
10103 MVT InVT = In.getSimpleValueType();
10105 if (Subtarget->hasFp256()) {
10106 if (ResVT.is128BitVector() &&
10107 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10108 isa<ConstantSDNode>(Idx)) {
10109 return Extract128BitVector(In, IdxVal, DAG, dl);
10111 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10112 isa<ConstantSDNode>(Idx)) {
10113 return Extract256BitVector(In, IdxVal, DAG, dl);
10119 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10120 // simple superregister reference or explicit instructions to insert
10121 // the upper bits of a vector.
10122 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10123 SelectionDAG &DAG) {
10124 if (Subtarget->hasFp256()) {
10125 SDLoc dl(Op.getNode());
10126 SDValue Vec = Op.getNode()->getOperand(0);
10127 SDValue SubVec = Op.getNode()->getOperand(1);
10128 SDValue Idx = Op.getNode()->getOperand(2);
10130 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
10131 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
10132 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
10133 isa<ConstantSDNode>(Idx)) {
10134 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10135 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10138 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
10139 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
10140 isa<ConstantSDNode>(Idx)) {
10141 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10142 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10148 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10149 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10150 // one of the above mentioned nodes. It has to be wrapped because otherwise
10151 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10152 // be used to form addressing mode. These wrapped nodes will be selected
10155 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10156 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10158 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10159 // global base reg.
10160 unsigned char OpFlag = 0;
10161 unsigned WrapperKind = X86ISD::Wrapper;
10162 CodeModel::Model M = DAG.getTarget().getCodeModel();
10164 if (Subtarget->isPICStyleRIPRel() &&
10165 (M == CodeModel::Small || M == CodeModel::Kernel))
10166 WrapperKind = X86ISD::WrapperRIP;
10167 else if (Subtarget->isPICStyleGOT())
10168 OpFlag = X86II::MO_GOTOFF;
10169 else if (Subtarget->isPICStyleStubPIC())
10170 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10172 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10173 CP->getAlignment(),
10174 CP->getOffset(), OpFlag);
10176 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10177 // With PIC, the address is actually $g + Offset.
10179 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10180 DAG.getNode(X86ISD::GlobalBaseReg,
10181 SDLoc(), getPointerTy()),
10188 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10189 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10191 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10192 // global base reg.
10193 unsigned char OpFlag = 0;
10194 unsigned WrapperKind = X86ISD::Wrapper;
10195 CodeModel::Model M = DAG.getTarget().getCodeModel();
10197 if (Subtarget->isPICStyleRIPRel() &&
10198 (M == CodeModel::Small || M == CodeModel::Kernel))
10199 WrapperKind = X86ISD::WrapperRIP;
10200 else if (Subtarget->isPICStyleGOT())
10201 OpFlag = X86II::MO_GOTOFF;
10202 else if (Subtarget->isPICStyleStubPIC())
10203 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10205 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10208 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10210 // With PIC, the address is actually $g + Offset.
10212 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10213 DAG.getNode(X86ISD::GlobalBaseReg,
10214 SDLoc(), getPointerTy()),
10221 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
10222 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10224 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10225 // global base reg.
10226 unsigned char OpFlag = 0;
10227 unsigned WrapperKind = X86ISD::Wrapper;
10228 CodeModel::Model M = DAG.getTarget().getCodeModel();
10230 if (Subtarget->isPICStyleRIPRel() &&
10231 (M == CodeModel::Small || M == CodeModel::Kernel)) {
10232 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10233 OpFlag = X86II::MO_GOTPCREL;
10234 WrapperKind = X86ISD::WrapperRIP;
10235 } else if (Subtarget->isPICStyleGOT()) {
10236 OpFlag = X86II::MO_GOT;
10237 } else if (Subtarget->isPICStyleStubPIC()) {
10238 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10239 } else if (Subtarget->isPICStyleStubNoDynamic()) {
10240 OpFlag = X86II::MO_DARWIN_NONLAZY;
10243 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10246 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10248 // With PIC, the address is actually $g + Offset.
10249 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10250 !Subtarget->is64Bit()) {
10251 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10252 DAG.getNode(X86ISD::GlobalBaseReg,
10253 SDLoc(), getPointerTy()),
10257 // For symbols that require a load from a stub to get the address, emit the
10259 if (isGlobalStubReference(OpFlag))
10260 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
10261 MachinePointerInfo::getGOT(), false, false, false, 0);
10267 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
10268 // Create the TargetBlockAddressAddress node.
10269 unsigned char OpFlags =
10270 Subtarget->ClassifyBlockAddressReference();
10271 CodeModel::Model M = DAG.getTarget().getCodeModel();
10272 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
10273 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
10275 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
10278 if (Subtarget->isPICStyleRIPRel() &&
10279 (M == CodeModel::Small || M == CodeModel::Kernel))
10280 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10282 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10284 // With PIC, the address is actually $g + Offset.
10285 if (isGlobalRelativeToPICBase(OpFlags)) {
10286 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10287 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10295 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
10296 int64_t Offset, SelectionDAG &DAG) const {
10297 // Create the TargetGlobalAddress node, folding in the constant
10298 // offset if it is legal.
10299 unsigned char OpFlags =
10300 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
10301 CodeModel::Model M = DAG.getTarget().getCodeModel();
10303 if (OpFlags == X86II::MO_NO_FLAG &&
10304 X86::isOffsetSuitableForCodeModel(Offset, M)) {
10305 // A direct static reference to a global.
10306 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
10309 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
10312 if (Subtarget->isPICStyleRIPRel() &&
10313 (M == CodeModel::Small || M == CodeModel::Kernel))
10314 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10316 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10318 // With PIC, the address is actually $g + Offset.
10319 if (isGlobalRelativeToPICBase(OpFlags)) {
10320 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10321 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10325 // For globals that require a load from a stub to get the address, emit the
10327 if (isGlobalStubReference(OpFlags))
10328 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
10329 MachinePointerInfo::getGOT(), false, false, false, 0);
10331 // If there was a non-zero offset that we didn't fold, create an explicit
10332 // addition for it.
10334 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
10335 DAG.getConstant(Offset, getPointerTy()));
10341 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
10342 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
10343 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
10344 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
10348 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
10349 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
10350 unsigned char OperandFlags, bool LocalDynamic = false) {
10351 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10352 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10354 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10355 GA->getValueType(0),
10359 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
10363 SDValue Ops[] = { Chain, TGA, *InFlag };
10364 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10366 SDValue Ops[] = { Chain, TGA };
10367 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10370 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
10371 MFI->setAdjustsStack(true);
10373 SDValue Flag = Chain.getValue(1);
10374 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
10377 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
10379 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10382 SDLoc dl(GA); // ? function entry point might be better
10383 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10384 DAG.getNode(X86ISD::GlobalBaseReg,
10385 SDLoc(), PtrVT), InFlag);
10386 InFlag = Chain.getValue(1);
10388 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
10391 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
10393 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10395 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
10396 X86::RAX, X86II::MO_TLSGD);
10399 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
10405 // Get the start address of the TLS block for this module.
10406 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
10407 .getInfo<X86MachineFunctionInfo>();
10408 MFI->incNumLocalDynamicTLSAccesses();
10412 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
10413 X86II::MO_TLSLD, /*LocalDynamic=*/true);
10416 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10417 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
10418 InFlag = Chain.getValue(1);
10419 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
10420 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
10423 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
10427 unsigned char OperandFlags = X86II::MO_DTPOFF;
10428 unsigned WrapperKind = X86ISD::Wrapper;
10429 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10430 GA->getValueType(0),
10431 GA->getOffset(), OperandFlags);
10432 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10434 // Add x@dtpoff with the base.
10435 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
10438 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
10439 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10440 const EVT PtrVT, TLSModel::Model model,
10441 bool is64Bit, bool isPIC) {
10444 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
10445 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
10446 is64Bit ? 257 : 256));
10448 SDValue ThreadPointer =
10449 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
10450 MachinePointerInfo(Ptr), false, false, false, 0);
10452 unsigned char OperandFlags = 0;
10453 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
10455 unsigned WrapperKind = X86ISD::Wrapper;
10456 if (model == TLSModel::LocalExec) {
10457 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
10458 } else if (model == TLSModel::InitialExec) {
10460 OperandFlags = X86II::MO_GOTTPOFF;
10461 WrapperKind = X86ISD::WrapperRIP;
10463 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
10466 llvm_unreachable("Unexpected model");
10469 // emit "addl x@ntpoff,%eax" (local exec)
10470 // or "addl x@indntpoff,%eax" (initial exec)
10471 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
10473 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
10474 GA->getOffset(), OperandFlags);
10475 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10477 if (model == TLSModel::InitialExec) {
10478 if (isPIC && !is64Bit) {
10479 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
10480 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
10484 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
10485 MachinePointerInfo::getGOT(), false, false, false, 0);
10488 // The address of the thread local variable is the add of the thread
10489 // pointer with the offset of the variable.
10490 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
10494 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
10496 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
10497 const GlobalValue *GV = GA->getGlobal();
10499 if (Subtarget->isTargetELF()) {
10500 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
10503 case TLSModel::GeneralDynamic:
10504 if (Subtarget->is64Bit())
10505 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
10506 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
10507 case TLSModel::LocalDynamic:
10508 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
10509 Subtarget->is64Bit());
10510 case TLSModel::InitialExec:
10511 case TLSModel::LocalExec:
10512 return LowerToTLSExecModel(
10513 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
10514 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
10516 llvm_unreachable("Unknown TLS model.");
10519 if (Subtarget->isTargetDarwin()) {
10520 // Darwin only has one model of TLS. Lower to that.
10521 unsigned char OpFlag = 0;
10522 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
10523 X86ISD::WrapperRIP : X86ISD::Wrapper;
10525 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10526 // global base reg.
10527 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
10528 !Subtarget->is64Bit();
10530 OpFlag = X86II::MO_TLVP_PIC_BASE;
10532 OpFlag = X86II::MO_TLVP;
10534 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
10535 GA->getValueType(0),
10536 GA->getOffset(), OpFlag);
10537 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10539 // With PIC32, the address is actually $g + Offset.
10541 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10542 DAG.getNode(X86ISD::GlobalBaseReg,
10543 SDLoc(), getPointerTy()),
10546 // Lowering the machine isd will make sure everything is in the right
10548 SDValue Chain = DAG.getEntryNode();
10549 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10550 SDValue Args[] = { Chain, Offset };
10551 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
10553 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
10554 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10555 MFI->setAdjustsStack(true);
10557 // And our return value (tls address) is in the standard call return value
10559 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
10560 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
10561 Chain.getValue(1));
10564 if (Subtarget->isTargetKnownWindowsMSVC() ||
10565 Subtarget->isTargetWindowsGNU()) {
10566 // Just use the implicit TLS architecture
10567 // Need to generate someting similar to:
10568 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
10570 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
10571 // mov rcx, qword [rdx+rcx*8]
10572 // mov eax, .tls$:tlsvar
10573 // [rax+rcx] contains the address
10574 // Windows 64bit: gs:0x58
10575 // Windows 32bit: fs:__tls_array
10578 SDValue Chain = DAG.getEntryNode();
10580 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
10581 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
10582 // use its literal value of 0x2C.
10583 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
10584 ? Type::getInt8PtrTy(*DAG.getContext(),
10586 : Type::getInt32PtrTy(*DAG.getContext(),
10590 Subtarget->is64Bit()
10591 ? DAG.getIntPtrConstant(0x58)
10592 : (Subtarget->isTargetWindowsGNU()
10593 ? DAG.getIntPtrConstant(0x2C)
10594 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
10596 SDValue ThreadPointer =
10597 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
10598 MachinePointerInfo(Ptr), false, false, false, 0);
10600 // Load the _tls_index variable
10601 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
10602 if (Subtarget->is64Bit())
10603 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
10604 IDX, MachinePointerInfo(), MVT::i32,
10607 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
10608 false, false, false, 0);
10610 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
10612 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
10614 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
10615 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
10616 false, false, false, 0);
10618 // Get the offset of start of .tls section
10619 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10620 GA->getValueType(0),
10621 GA->getOffset(), X86II::MO_SECREL);
10622 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
10624 // The address of the thread local variable is the add of the thread
10625 // pointer with the offset of the variable.
10626 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
10629 llvm_unreachable("TLS not implemented for this target.");
10632 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
10633 /// and take a 2 x i32 value to shift plus a shift amount.
10634 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
10635 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
10636 MVT VT = Op.getSimpleValueType();
10637 unsigned VTBits = VT.getSizeInBits();
10639 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
10640 SDValue ShOpLo = Op.getOperand(0);
10641 SDValue ShOpHi = Op.getOperand(1);
10642 SDValue ShAmt = Op.getOperand(2);
10643 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
10644 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
10646 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
10647 DAG.getConstant(VTBits - 1, MVT::i8));
10648 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
10649 DAG.getConstant(VTBits - 1, MVT::i8))
10650 : DAG.getConstant(0, VT);
10652 SDValue Tmp2, Tmp3;
10653 if (Op.getOpcode() == ISD::SHL_PARTS) {
10654 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
10655 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
10657 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
10658 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
10661 // If the shift amount is larger or equal than the width of a part we can't
10662 // rely on the results of shld/shrd. Insert a test and select the appropriate
10663 // values for large shift amounts.
10664 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
10665 DAG.getConstant(VTBits, MVT::i8));
10666 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10667 AndNode, DAG.getConstant(0, MVT::i8));
10670 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10671 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
10672 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
10674 if (Op.getOpcode() == ISD::SHL_PARTS) {
10675 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
10676 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
10678 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
10679 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
10682 SDValue Ops[2] = { Lo, Hi };
10683 return DAG.getMergeValues(Ops, dl);
10686 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
10687 SelectionDAG &DAG) const {
10688 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
10690 if (SrcVT.isVector())
10693 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
10694 "Unknown SINT_TO_FP to lower!");
10696 // These are really Legal; return the operand so the caller accepts it as
10698 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
10700 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
10701 Subtarget->is64Bit()) {
10706 unsigned Size = SrcVT.getSizeInBits()/8;
10707 MachineFunction &MF = DAG.getMachineFunction();
10708 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
10709 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10710 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10712 MachinePointerInfo::getFixedStack(SSFI),
10714 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
10717 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
10719 SelectionDAG &DAG) const {
10723 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
10725 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
10727 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
10729 unsigned ByteSize = SrcVT.getSizeInBits()/8;
10731 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
10732 MachineMemOperand *MMO;
10734 int SSFI = FI->getIndex();
10736 DAG.getMachineFunction()
10737 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10738 MachineMemOperand::MOLoad, ByteSize, ByteSize);
10740 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
10741 StackSlot = StackSlot.getOperand(1);
10743 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
10744 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
10746 Tys, Ops, SrcVT, MMO);
10749 Chain = Result.getValue(1);
10750 SDValue InFlag = Result.getValue(2);
10752 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
10753 // shouldn't be necessary except that RFP cannot be live across
10754 // multiple blocks. When stackifier is fixed, they can be uncoupled.
10755 MachineFunction &MF = DAG.getMachineFunction();
10756 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
10757 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
10758 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10759 Tys = DAG.getVTList(MVT::Other);
10761 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
10763 MachineMemOperand *MMO =
10764 DAG.getMachineFunction()
10765 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10766 MachineMemOperand::MOStore, SSFISize, SSFISize);
10768 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
10769 Ops, Op.getValueType(), MMO);
10770 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
10771 MachinePointerInfo::getFixedStack(SSFI),
10772 false, false, false, 0);
10778 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
10779 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
10780 SelectionDAG &DAG) const {
10781 // This algorithm is not obvious. Here it is what we're trying to output:
10784 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
10785 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
10787 haddpd %xmm0, %xmm0
10789 pshufd $0x4e, %xmm0, %xmm1
10795 LLVMContext *Context = DAG.getContext();
10797 // Build some magic constants.
10798 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
10799 Constant *C0 = ConstantDataVector::get(*Context, CV0);
10800 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
10802 SmallVector<Constant*,2> CV1;
10804 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
10805 APInt(64, 0x4330000000000000ULL))));
10807 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
10808 APInt(64, 0x4530000000000000ULL))));
10809 Constant *C1 = ConstantVector::get(CV1);
10810 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
10812 // Load the 64-bit value into an XMM register.
10813 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
10815 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
10816 MachinePointerInfo::getConstantPool(),
10817 false, false, false, 16);
10818 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
10819 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
10822 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
10823 MachinePointerInfo::getConstantPool(),
10824 false, false, false, 16);
10825 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
10826 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
10829 if (Subtarget->hasSSE3()) {
10830 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
10831 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
10833 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
10834 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
10836 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
10837 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
10841 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
10842 DAG.getIntPtrConstant(0));
10845 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
10846 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
10847 SelectionDAG &DAG) const {
10849 // FP constant to bias correct the final result.
10850 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
10853 // Load the 32-bit value into an XMM register.
10854 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
10857 // Zero out the upper parts of the register.
10858 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
10860 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
10861 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
10862 DAG.getIntPtrConstant(0));
10864 // Or the load with the bias.
10865 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
10866 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
10867 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10868 MVT::v2f64, Load)),
10869 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
10870 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10871 MVT::v2f64, Bias)));
10872 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
10873 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
10874 DAG.getIntPtrConstant(0));
10876 // Subtract the bias.
10877 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
10879 // Handle final rounding.
10880 EVT DestVT = Op.getValueType();
10882 if (DestVT.bitsLT(MVT::f64))
10883 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
10884 DAG.getIntPtrConstant(0));
10885 if (DestVT.bitsGT(MVT::f64))
10886 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
10888 // Handle final rounding.
10892 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
10893 SelectionDAG &DAG) const {
10894 SDValue N0 = Op.getOperand(0);
10895 MVT SVT = N0.getSimpleValueType();
10898 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
10899 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
10900 "Custom UINT_TO_FP is not supported!");
10902 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
10903 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
10904 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
10907 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
10908 SelectionDAG &DAG) const {
10909 SDValue N0 = Op.getOperand(0);
10912 if (Op.getValueType().isVector())
10913 return lowerUINT_TO_FP_vec(Op, DAG);
10915 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
10916 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
10917 // the optimization here.
10918 if (DAG.SignBitIsZero(N0))
10919 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
10921 MVT SrcVT = N0.getSimpleValueType();
10922 MVT DstVT = Op.getSimpleValueType();
10923 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
10924 return LowerUINT_TO_FP_i64(Op, DAG);
10925 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
10926 return LowerUINT_TO_FP_i32(Op, DAG);
10927 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
10930 // Make a 64-bit buffer, and use it to build an FILD.
10931 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
10932 if (SrcVT == MVT::i32) {
10933 SDValue WordOff = DAG.getConstant(4, getPointerTy());
10934 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
10935 getPointerTy(), StackSlot, WordOff);
10936 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10937 StackSlot, MachinePointerInfo(),
10939 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
10940 OffsetSlot, MachinePointerInfo(),
10942 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
10946 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
10947 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10948 StackSlot, MachinePointerInfo(),
10950 // For i64 source, we need to add the appropriate power of 2 if the input
10951 // was negative. This is the same as the optimization in
10952 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
10953 // we must be careful to do the computation in x87 extended precision, not
10954 // in SSE. (The generic code can't know it's OK to do this, or how to.)
10955 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
10956 MachineMemOperand *MMO =
10957 DAG.getMachineFunction()
10958 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10959 MachineMemOperand::MOLoad, 8, 8);
10961 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
10962 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
10963 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
10966 APInt FF(32, 0x5F800000ULL);
10968 // Check whether the sign bit is set.
10969 SDValue SignSet = DAG.getSetCC(dl,
10970 getSetCCResultType(*DAG.getContext(), MVT::i64),
10971 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
10974 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
10975 SDValue FudgePtr = DAG.getConstantPool(
10976 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
10979 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
10980 SDValue Zero = DAG.getIntPtrConstant(0);
10981 SDValue Four = DAG.getIntPtrConstant(4);
10982 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
10984 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
10986 // Load the value out, extending it from f32 to f80.
10987 // FIXME: Avoid the extend by constructing the right constant pool?
10988 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
10989 FudgePtr, MachinePointerInfo::getConstantPool(),
10990 MVT::f32, false, false, 4);
10991 // Extend everything to 80 bits to force it to be done on x87.
10992 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
10993 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
10996 std::pair<SDValue,SDValue>
10997 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
10998 bool IsSigned, bool IsReplace) const {
11001 EVT DstTy = Op.getValueType();
11003 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11004 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11008 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11009 DstTy.getSimpleVT() >= MVT::i16 &&
11010 "Unknown FP_TO_INT to lower!");
11012 // These are really Legal.
11013 if (DstTy == MVT::i32 &&
11014 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11015 return std::make_pair(SDValue(), SDValue());
11016 if (Subtarget->is64Bit() &&
11017 DstTy == MVT::i64 &&
11018 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11019 return std::make_pair(SDValue(), SDValue());
11021 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11022 // stack slot, or into the FTOL runtime function.
11023 MachineFunction &MF = DAG.getMachineFunction();
11024 unsigned MemSize = DstTy.getSizeInBits()/8;
11025 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11026 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11029 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11030 Opc = X86ISD::WIN_FTOL;
11032 switch (DstTy.getSimpleVT().SimpleTy) {
11033 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11034 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11035 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11036 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11039 SDValue Chain = DAG.getEntryNode();
11040 SDValue Value = Op.getOperand(0);
11041 EVT TheVT = Op.getOperand(0).getValueType();
11042 // FIXME This causes a redundant load/store if the SSE-class value is already
11043 // in memory, such as if it is on the callstack.
11044 if (isScalarFPTypeInSSEReg(TheVT)) {
11045 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11046 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11047 MachinePointerInfo::getFixedStack(SSFI),
11049 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11051 Chain, StackSlot, DAG.getValueType(TheVT)
11054 MachineMemOperand *MMO =
11055 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11056 MachineMemOperand::MOLoad, MemSize, MemSize);
11057 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11058 Chain = Value.getValue(1);
11059 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11060 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11063 MachineMemOperand *MMO =
11064 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11065 MachineMemOperand::MOStore, MemSize, MemSize);
11067 if (Opc != X86ISD::WIN_FTOL) {
11068 // Build the FP_TO_INT*_IN_MEM
11069 SDValue Ops[] = { Chain, Value, StackSlot };
11070 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11072 return std::make_pair(FIST, StackSlot);
11074 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11075 DAG.getVTList(MVT::Other, MVT::Glue),
11077 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11078 MVT::i32, ftol.getValue(1));
11079 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11080 MVT::i32, eax.getValue(2));
11081 SDValue Ops[] = { eax, edx };
11082 SDValue pair = IsReplace
11083 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11084 : DAG.getMergeValues(Ops, DL);
11085 return std::make_pair(pair, SDValue());
11089 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11090 const X86Subtarget *Subtarget) {
11091 MVT VT = Op->getSimpleValueType(0);
11092 SDValue In = Op->getOperand(0);
11093 MVT InVT = In.getSimpleValueType();
11096 // Optimize vectors in AVX mode:
11099 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11100 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11101 // Concat upper and lower parts.
11104 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11105 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11106 // Concat upper and lower parts.
11109 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11110 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11111 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11114 if (Subtarget->hasInt256())
11115 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11117 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11118 SDValue Undef = DAG.getUNDEF(InVT);
11119 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11120 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11121 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11123 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11124 VT.getVectorNumElements()/2);
11126 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11127 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
11129 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11132 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
11133 SelectionDAG &DAG) {
11134 MVT VT = Op->getSimpleValueType(0);
11135 SDValue In = Op->getOperand(0);
11136 MVT InVT = In.getSimpleValueType();
11138 unsigned int NumElts = VT.getVectorNumElements();
11139 if (NumElts != 8 && NumElts != 16)
11142 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11143 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
11145 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11146 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11147 // Now we have only mask extension
11148 assert(InVT.getVectorElementType() == MVT::i1);
11149 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
11150 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11151 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11152 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11153 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11154 MachinePointerInfo::getConstantPool(),
11155 false, false, false, Alignment);
11157 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
11158 if (VT.is512BitVector())
11160 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
11163 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11164 SelectionDAG &DAG) {
11165 if (Subtarget->hasFp256()) {
11166 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11174 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11175 SelectionDAG &DAG) {
11177 MVT VT = Op.getSimpleValueType();
11178 SDValue In = Op.getOperand(0);
11179 MVT SVT = In.getSimpleValueType();
11181 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
11182 return LowerZERO_EXTEND_AVX512(Op, DAG);
11184 if (Subtarget->hasFp256()) {
11185 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11190 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
11191 VT.getVectorNumElements() != SVT.getVectorNumElements());
11195 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
11197 MVT VT = Op.getSimpleValueType();
11198 SDValue In = Op.getOperand(0);
11199 MVT InVT = In.getSimpleValueType();
11201 if (VT == MVT::i1) {
11202 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
11203 "Invalid scalar TRUNCATE operation");
11204 if (InVT == MVT::i32)
11206 if (InVT.getSizeInBits() == 64)
11207 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
11208 else if (InVT.getSizeInBits() < 32)
11209 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
11210 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
11212 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
11213 "Invalid TRUNCATE operation");
11215 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
11216 if (VT.getVectorElementType().getSizeInBits() >=8)
11217 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
11219 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
11220 unsigned NumElts = InVT.getVectorNumElements();
11221 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
11222 if (InVT.getSizeInBits() < 512) {
11223 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
11224 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
11228 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
11229 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11230 SDValue CP = DAG.getConstantPool(C, getPointerTy());
11231 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11232 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11233 MachinePointerInfo::getConstantPool(),
11234 false, false, false, Alignment);
11235 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
11236 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
11237 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
11240 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
11241 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
11242 if (Subtarget->hasInt256()) {
11243 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
11244 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
11245 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
11247 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
11248 DAG.getIntPtrConstant(0));
11251 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11252 DAG.getIntPtrConstant(0));
11253 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11254 DAG.getIntPtrConstant(2));
11255 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11256 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11257 static const int ShufMask[] = {0, 2, 4, 6};
11258 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
11261 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
11262 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
11263 if (Subtarget->hasInt256()) {
11264 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
11266 SmallVector<SDValue,32> pshufbMask;
11267 for (unsigned i = 0; i < 2; ++i) {
11268 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
11269 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
11270 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
11271 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
11272 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
11273 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
11274 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
11275 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
11276 for (unsigned j = 0; j < 8; ++j)
11277 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
11279 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
11280 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
11281 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
11283 static const int ShufMask[] = {0, 2, -1, -1};
11284 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
11286 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11287 DAG.getIntPtrConstant(0));
11288 return DAG.getNode(ISD::BITCAST, DL, VT, In);
11291 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11292 DAG.getIntPtrConstant(0));
11294 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11295 DAG.getIntPtrConstant(4));
11297 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
11298 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
11300 // The PSHUFB mask:
11301 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
11302 -1, -1, -1, -1, -1, -1, -1, -1};
11304 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
11305 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
11306 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
11308 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11309 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11311 // The MOVLHPS Mask:
11312 static const int ShufMask2[] = {0, 1, 4, 5};
11313 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
11314 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
11317 // Handle truncation of V256 to V128 using shuffles.
11318 if (!VT.is128BitVector() || !InVT.is256BitVector())
11321 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
11323 unsigned NumElems = VT.getVectorNumElements();
11324 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
11326 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
11327 // Prepare truncation shuffle mask
11328 for (unsigned i = 0; i != NumElems; ++i)
11329 MaskVec[i] = i * 2;
11330 SDValue V = DAG.getVectorShuffle(NVT, DL,
11331 DAG.getNode(ISD::BITCAST, DL, NVT, In),
11332 DAG.getUNDEF(NVT), &MaskVec[0]);
11333 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
11334 DAG.getIntPtrConstant(0));
11337 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
11338 SelectionDAG &DAG) const {
11339 assert(!Op.getSimpleValueType().isVector());
11341 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11342 /*IsSigned=*/ true, /*IsReplace=*/ false);
11343 SDValue FIST = Vals.first, StackSlot = Vals.second;
11344 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
11345 if (!FIST.getNode()) return Op;
11347 if (StackSlot.getNode())
11348 // Load the result.
11349 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11350 FIST, StackSlot, MachinePointerInfo(),
11351 false, false, false, 0);
11353 // The node is the result.
11357 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
11358 SelectionDAG &DAG) const {
11359 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11360 /*IsSigned=*/ false, /*IsReplace=*/ false);
11361 SDValue FIST = Vals.first, StackSlot = Vals.second;
11362 assert(FIST.getNode() && "Unexpected failure");
11364 if (StackSlot.getNode())
11365 // Load the result.
11366 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11367 FIST, StackSlot, MachinePointerInfo(),
11368 false, false, false, 0);
11370 // The node is the result.
11374 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
11376 MVT VT = Op.getSimpleValueType();
11377 SDValue In = Op.getOperand(0);
11378 MVT SVT = In.getSimpleValueType();
11380 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
11382 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
11383 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
11384 In, DAG.getUNDEF(SVT)));
11387 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
11388 LLVMContext *Context = DAG.getContext();
11390 MVT VT = Op.getSimpleValueType();
11392 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11393 if (VT.isVector()) {
11394 EltVT = VT.getVectorElementType();
11395 NumElts = VT.getVectorNumElements();
11398 if (EltVT == MVT::f64)
11399 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11400 APInt(64, ~(1ULL << 63))));
11402 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
11403 APInt(32, ~(1U << 31))));
11404 C = ConstantVector::getSplat(NumElts, C);
11405 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11406 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11407 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11408 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11409 MachinePointerInfo::getConstantPool(),
11410 false, false, false, Alignment);
11411 if (VT.isVector()) {
11412 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
11413 return DAG.getNode(ISD::BITCAST, dl, VT,
11414 DAG.getNode(ISD::AND, dl, ANDVT,
11415 DAG.getNode(ISD::BITCAST, dl, ANDVT,
11417 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
11419 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
11422 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
11423 LLVMContext *Context = DAG.getContext();
11425 MVT VT = Op.getSimpleValueType();
11427 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11428 if (VT.isVector()) {
11429 EltVT = VT.getVectorElementType();
11430 NumElts = VT.getVectorNumElements();
11433 if (EltVT == MVT::f64)
11434 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11435 APInt(64, 1ULL << 63)));
11437 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
11438 APInt(32, 1U << 31)));
11439 C = ConstantVector::getSplat(NumElts, C);
11440 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11441 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11442 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11443 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11444 MachinePointerInfo::getConstantPool(),
11445 false, false, false, Alignment);
11446 if (VT.isVector()) {
11447 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
11448 return DAG.getNode(ISD::BITCAST, dl, VT,
11449 DAG.getNode(ISD::XOR, dl, XORVT,
11450 DAG.getNode(ISD::BITCAST, dl, XORVT,
11452 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
11455 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
11458 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
11459 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11460 LLVMContext *Context = DAG.getContext();
11461 SDValue Op0 = Op.getOperand(0);
11462 SDValue Op1 = Op.getOperand(1);
11464 MVT VT = Op.getSimpleValueType();
11465 MVT SrcVT = Op1.getSimpleValueType();
11467 // If second operand is smaller, extend it first.
11468 if (SrcVT.bitsLT(VT)) {
11469 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
11472 // And if it is bigger, shrink it first.
11473 if (SrcVT.bitsGT(VT)) {
11474 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
11478 // At this point the operands and the result should have the same
11479 // type, and that won't be f80 since that is not custom lowered.
11481 // First get the sign bit of second operand.
11482 SmallVector<Constant*,4> CV;
11483 if (SrcVT == MVT::f64) {
11484 const fltSemantics &Sem = APFloat::IEEEdouble;
11485 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
11486 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
11488 const fltSemantics &Sem = APFloat::IEEEsingle;
11489 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
11490 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11491 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11492 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11494 Constant *C = ConstantVector::get(CV);
11495 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
11496 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
11497 MachinePointerInfo::getConstantPool(),
11498 false, false, false, 16);
11499 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
11501 // Shift sign bit right or left if the two operands have different types.
11502 if (SrcVT.bitsGT(VT)) {
11503 // Op0 is MVT::f32, Op1 is MVT::f64.
11504 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
11505 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
11506 DAG.getConstant(32, MVT::i32));
11507 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
11508 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
11509 DAG.getIntPtrConstant(0));
11512 // Clear first operand sign bit.
11514 if (VT == MVT::f64) {
11515 const fltSemantics &Sem = APFloat::IEEEdouble;
11516 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
11517 APInt(64, ~(1ULL << 63)))));
11518 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
11520 const fltSemantics &Sem = APFloat::IEEEsingle;
11521 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
11522 APInt(32, ~(1U << 31)))));
11523 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11524 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11525 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11527 C = ConstantVector::get(CV);
11528 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
11529 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11530 MachinePointerInfo::getConstantPool(),
11531 false, false, false, 16);
11532 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
11534 // Or the value with the sign bit.
11535 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
11538 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
11539 SDValue N0 = Op.getOperand(0);
11541 MVT VT = Op.getSimpleValueType();
11543 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
11544 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
11545 DAG.getConstant(1, VT));
11546 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
11549 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
11551 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
11552 SelectionDAG &DAG) {
11553 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
11555 if (!Subtarget->hasSSE41())
11558 if (!Op->hasOneUse())
11561 SDNode *N = Op.getNode();
11564 SmallVector<SDValue, 8> Opnds;
11565 DenseMap<SDValue, unsigned> VecInMap;
11566 SmallVector<SDValue, 8> VecIns;
11567 EVT VT = MVT::Other;
11569 // Recognize a special case where a vector is casted into wide integer to
11571 Opnds.push_back(N->getOperand(0));
11572 Opnds.push_back(N->getOperand(1));
11574 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
11575 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
11576 // BFS traverse all OR'd operands.
11577 if (I->getOpcode() == ISD::OR) {
11578 Opnds.push_back(I->getOperand(0));
11579 Opnds.push_back(I->getOperand(1));
11580 // Re-evaluate the number of nodes to be traversed.
11581 e += 2; // 2 more nodes (LHS and RHS) are pushed.
11585 // Quit if a non-EXTRACT_VECTOR_ELT
11586 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
11589 // Quit if without a constant index.
11590 SDValue Idx = I->getOperand(1);
11591 if (!isa<ConstantSDNode>(Idx))
11594 SDValue ExtractedFromVec = I->getOperand(0);
11595 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
11596 if (M == VecInMap.end()) {
11597 VT = ExtractedFromVec.getValueType();
11598 // Quit if not 128/256-bit vector.
11599 if (!VT.is128BitVector() && !VT.is256BitVector())
11601 // Quit if not the same type.
11602 if (VecInMap.begin() != VecInMap.end() &&
11603 VT != VecInMap.begin()->first.getValueType())
11605 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
11606 VecIns.push_back(ExtractedFromVec);
11608 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
11611 assert((VT.is128BitVector() || VT.is256BitVector()) &&
11612 "Not extracted from 128-/256-bit vector.");
11614 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
11616 for (DenseMap<SDValue, unsigned>::const_iterator
11617 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
11618 // Quit if not all elements are used.
11619 if (I->second != FullMask)
11623 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
11625 // Cast all vectors into TestVT for PTEST.
11626 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
11627 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
11629 // If more than one full vectors are evaluated, OR them first before PTEST.
11630 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
11631 // Each iteration will OR 2 nodes and append the result until there is only
11632 // 1 node left, i.e. the final OR'd value of all vectors.
11633 SDValue LHS = VecIns[Slot];
11634 SDValue RHS = VecIns[Slot + 1];
11635 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
11638 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
11639 VecIns.back(), VecIns.back());
11642 /// \brief return true if \c Op has a use that doesn't just read flags.
11643 static bool hasNonFlagsUse(SDValue Op) {
11644 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
11646 SDNode *User = *UI;
11647 unsigned UOpNo = UI.getOperandNo();
11648 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
11649 // Look pass truncate.
11650 UOpNo = User->use_begin().getOperandNo();
11651 User = *User->use_begin();
11654 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
11655 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
11661 /// Emit nodes that will be selected as "test Op0,Op0", or something
11663 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
11664 SelectionDAG &DAG) const {
11665 if (Op.getValueType() == MVT::i1)
11666 // KORTEST instruction should be selected
11667 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11668 DAG.getConstant(0, Op.getValueType()));
11670 // CF and OF aren't always set the way we want. Determine which
11671 // of these we need.
11672 bool NeedCF = false;
11673 bool NeedOF = false;
11676 case X86::COND_A: case X86::COND_AE:
11677 case X86::COND_B: case X86::COND_BE:
11680 case X86::COND_G: case X86::COND_GE:
11681 case X86::COND_L: case X86::COND_LE:
11682 case X86::COND_O: case X86::COND_NO: {
11683 // Check if we really need to set the
11684 // Overflow flag. If NoSignedWrap is present
11685 // that is not actually needed.
11686 switch (Op->getOpcode()) {
11691 const BinaryWithFlagsSDNode *BinNode =
11692 cast<BinaryWithFlagsSDNode>(Op.getNode());
11693 if (BinNode->hasNoSignedWrap())
11703 // See if we can use the EFLAGS value from the operand instead of
11704 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
11705 // we prove that the arithmetic won't overflow, we can't use OF or CF.
11706 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
11707 // Emit a CMP with 0, which is the TEST pattern.
11708 //if (Op.getValueType() == MVT::i1)
11709 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
11710 // DAG.getConstant(0, MVT::i1));
11711 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11712 DAG.getConstant(0, Op.getValueType()));
11714 unsigned Opcode = 0;
11715 unsigned NumOperands = 0;
11717 // Truncate operations may prevent the merge of the SETCC instruction
11718 // and the arithmetic instruction before it. Attempt to truncate the operands
11719 // of the arithmetic instruction and use a reduced bit-width instruction.
11720 bool NeedTruncation = false;
11721 SDValue ArithOp = Op;
11722 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
11723 SDValue Arith = Op->getOperand(0);
11724 // Both the trunc and the arithmetic op need to have one user each.
11725 if (Arith->hasOneUse())
11726 switch (Arith.getOpcode()) {
11733 NeedTruncation = true;
11739 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
11740 // which may be the result of a CAST. We use the variable 'Op', which is the
11741 // non-casted variable when we check for possible users.
11742 switch (ArithOp.getOpcode()) {
11744 // Due to an isel shortcoming, be conservative if this add is likely to be
11745 // selected as part of a load-modify-store instruction. When the root node
11746 // in a match is a store, isel doesn't know how to remap non-chain non-flag
11747 // uses of other nodes in the match, such as the ADD in this case. This
11748 // leads to the ADD being left around and reselected, with the result being
11749 // two adds in the output. Alas, even if none our users are stores, that
11750 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
11751 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
11752 // climbing the DAG back to the root, and it doesn't seem to be worth the
11754 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11755 UE = Op.getNode()->use_end(); UI != UE; ++UI)
11756 if (UI->getOpcode() != ISD::CopyToReg &&
11757 UI->getOpcode() != ISD::SETCC &&
11758 UI->getOpcode() != ISD::STORE)
11761 if (ConstantSDNode *C =
11762 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
11763 // An add of one will be selected as an INC.
11764 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
11765 Opcode = X86ISD::INC;
11770 // An add of negative one (subtract of one) will be selected as a DEC.
11771 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
11772 Opcode = X86ISD::DEC;
11778 // Otherwise use a regular EFLAGS-setting add.
11779 Opcode = X86ISD::ADD;
11784 // If we have a constant logical shift that's only used in a comparison
11785 // against zero turn it into an equivalent AND. This allows turning it into
11786 // a TEST instruction later.
11787 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
11788 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
11789 EVT VT = Op.getValueType();
11790 unsigned BitWidth = VT.getSizeInBits();
11791 unsigned ShAmt = Op->getConstantOperandVal(1);
11792 if (ShAmt >= BitWidth) // Avoid undefined shifts.
11794 APInt Mask = ArithOp.getOpcode() == ISD::SRL
11795 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
11796 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
11797 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
11799 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
11800 DAG.getConstant(Mask, VT));
11801 DAG.ReplaceAllUsesWith(Op, New);
11807 // If the primary and result isn't used, don't bother using X86ISD::AND,
11808 // because a TEST instruction will be better.
11809 if (!hasNonFlagsUse(Op))
11815 // Due to the ISEL shortcoming noted above, be conservative if this op is
11816 // likely to be selected as part of a load-modify-store instruction.
11817 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11818 UE = Op.getNode()->use_end(); UI != UE; ++UI)
11819 if (UI->getOpcode() == ISD::STORE)
11822 // Otherwise use a regular EFLAGS-setting instruction.
11823 switch (ArithOp.getOpcode()) {
11824 default: llvm_unreachable("unexpected operator!");
11825 case ISD::SUB: Opcode = X86ISD::SUB; break;
11826 case ISD::XOR: Opcode = X86ISD::XOR; break;
11827 case ISD::AND: Opcode = X86ISD::AND; break;
11829 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
11830 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
11831 if (EFLAGS.getNode())
11834 Opcode = X86ISD::OR;
11848 return SDValue(Op.getNode(), 1);
11854 // If we found that truncation is beneficial, perform the truncation and
11856 if (NeedTruncation) {
11857 EVT VT = Op.getValueType();
11858 SDValue WideVal = Op->getOperand(0);
11859 EVT WideVT = WideVal.getValueType();
11860 unsigned ConvertedOp = 0;
11861 // Use a target machine opcode to prevent further DAGCombine
11862 // optimizations that may separate the arithmetic operations
11863 // from the setcc node.
11864 switch (WideVal.getOpcode()) {
11866 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
11867 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
11868 case ISD::AND: ConvertedOp = X86ISD::AND; break;
11869 case ISD::OR: ConvertedOp = X86ISD::OR; break;
11870 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
11874 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11875 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
11876 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
11877 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
11878 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
11884 // Emit a CMP with 0, which is the TEST pattern.
11885 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11886 DAG.getConstant(0, Op.getValueType()));
11888 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11889 SmallVector<SDValue, 4> Ops;
11890 for (unsigned i = 0; i != NumOperands; ++i)
11891 Ops.push_back(Op.getOperand(i));
11893 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
11894 DAG.ReplaceAllUsesWith(Op, New);
11895 return SDValue(New.getNode(), 1);
11898 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
11900 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
11901 SDLoc dl, SelectionDAG &DAG) const {
11902 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
11903 if (C->getAPIntValue() == 0)
11904 return EmitTest(Op0, X86CC, dl, DAG);
11906 if (Op0.getValueType() == MVT::i1)
11907 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
11910 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
11911 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
11912 // Do the comparison at i32 if it's smaller, besides the Atom case.
11913 // This avoids subregister aliasing issues. Keep the smaller reference
11914 // if we're optimizing for size, however, as that'll allow better folding
11915 // of memory operations.
11916 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
11917 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
11918 AttributeSet::FunctionIndex, Attribute::MinSize) &&
11919 !Subtarget->isAtom()) {
11920 unsigned ExtendOp =
11921 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
11922 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
11923 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
11925 // Use SUB instead of CMP to enable CSE between SUB and CMP.
11926 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
11927 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
11929 return SDValue(Sub.getNode(), 1);
11931 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
11934 /// Convert a comparison if required by the subtarget.
11935 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
11936 SelectionDAG &DAG) const {
11937 // If the subtarget does not support the FUCOMI instruction, floating-point
11938 // comparisons have to be converted.
11939 if (Subtarget->hasCMov() ||
11940 Cmp.getOpcode() != X86ISD::CMP ||
11941 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
11942 !Cmp.getOperand(1).getValueType().isFloatingPoint())
11945 // The instruction selector will select an FUCOM instruction instead of
11946 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
11947 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
11948 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
11950 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
11951 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
11952 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
11953 DAG.getConstant(8, MVT::i8));
11954 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
11955 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
11958 static bool isAllOnes(SDValue V) {
11959 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
11960 return C && C->isAllOnesValue();
11963 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
11964 /// if it's possible.
11965 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
11966 SDLoc dl, SelectionDAG &DAG) const {
11967 SDValue Op0 = And.getOperand(0);
11968 SDValue Op1 = And.getOperand(1);
11969 if (Op0.getOpcode() == ISD::TRUNCATE)
11970 Op0 = Op0.getOperand(0);
11971 if (Op1.getOpcode() == ISD::TRUNCATE)
11972 Op1 = Op1.getOperand(0);
11975 if (Op1.getOpcode() == ISD::SHL)
11976 std::swap(Op0, Op1);
11977 if (Op0.getOpcode() == ISD::SHL) {
11978 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
11979 if (And00C->getZExtValue() == 1) {
11980 // If we looked past a truncate, check that it's only truncating away
11982 unsigned BitWidth = Op0.getValueSizeInBits();
11983 unsigned AndBitWidth = And.getValueSizeInBits();
11984 if (BitWidth > AndBitWidth) {
11986 DAG.computeKnownBits(Op0, Zeros, Ones);
11987 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
11991 RHS = Op0.getOperand(1);
11993 } else if (Op1.getOpcode() == ISD::Constant) {
11994 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
11995 uint64_t AndRHSVal = AndRHS->getZExtValue();
11996 SDValue AndLHS = Op0;
11998 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
11999 LHS = AndLHS.getOperand(0);
12000 RHS = AndLHS.getOperand(1);
12003 // Use BT if the immediate can't be encoded in a TEST instruction.
12004 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12006 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
12010 if (LHS.getNode()) {
12011 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12012 // instruction. Since the shift amount is in-range-or-undefined, we know
12013 // that doing a bittest on the i32 value is ok. We extend to i32 because
12014 // the encoding for the i16 version is larger than the i32 version.
12015 // Also promote i16 to i32 for performance / code size reason.
12016 if (LHS.getValueType() == MVT::i8 ||
12017 LHS.getValueType() == MVT::i16)
12018 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12020 // If the operand types disagree, extend the shift amount to match. Since
12021 // BT ignores high bits (like shifts) we can use anyextend.
12022 if (LHS.getValueType() != RHS.getValueType())
12023 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12025 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12026 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
12027 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12028 DAG.getConstant(Cond, MVT::i8), BT);
12034 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
12036 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
12041 // SSE Condition code mapping:
12050 switch (SetCCOpcode) {
12051 default: llvm_unreachable("Unexpected SETCC condition");
12053 case ISD::SETEQ: SSECC = 0; break;
12055 case ISD::SETGT: Swap = true; // Fallthrough
12057 case ISD::SETOLT: SSECC = 1; break;
12059 case ISD::SETGE: Swap = true; // Fallthrough
12061 case ISD::SETOLE: SSECC = 2; break;
12062 case ISD::SETUO: SSECC = 3; break;
12064 case ISD::SETNE: SSECC = 4; break;
12065 case ISD::SETULE: Swap = true; // Fallthrough
12066 case ISD::SETUGE: SSECC = 5; break;
12067 case ISD::SETULT: Swap = true; // Fallthrough
12068 case ISD::SETUGT: SSECC = 6; break;
12069 case ISD::SETO: SSECC = 7; break;
12071 case ISD::SETONE: SSECC = 8; break;
12074 std::swap(Op0, Op1);
12079 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
12080 // ones, and then concatenate the result back.
12081 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
12082 MVT VT = Op.getSimpleValueType();
12084 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12085 "Unsupported value type for operation");
12087 unsigned NumElems = VT.getVectorNumElements();
12089 SDValue CC = Op.getOperand(2);
12091 // Extract the LHS vectors
12092 SDValue LHS = Op.getOperand(0);
12093 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12094 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12096 // Extract the RHS vectors
12097 SDValue RHS = Op.getOperand(1);
12098 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12099 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12101 // Issue the operation on the smaller types and concatenate the result back
12102 MVT EltVT = VT.getVectorElementType();
12103 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12104 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12105 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
12106 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
12109 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
12110 const X86Subtarget *Subtarget) {
12111 SDValue Op0 = Op.getOperand(0);
12112 SDValue Op1 = Op.getOperand(1);
12113 SDValue CC = Op.getOperand(2);
12114 MVT VT = Op.getSimpleValueType();
12117 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
12118 Op.getValueType().getScalarType() == MVT::i1 &&
12119 "Cannot set masked compare for this operation");
12121 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12123 bool Unsigned = false;
12126 switch (SetCCOpcode) {
12127 default: llvm_unreachable("Unexpected SETCC condition");
12128 case ISD::SETNE: SSECC = 4; break;
12129 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
12130 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
12131 case ISD::SETLT: Swap = true; //fall-through
12132 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
12133 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
12134 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
12135 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
12136 case ISD::SETULE: Unsigned = true; //fall-through
12137 case ISD::SETLE: SSECC = 2; break;
12141 std::swap(Op0, Op1);
12143 return DAG.getNode(Opc, dl, VT, Op0, Op1);
12144 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
12145 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12146 DAG.getConstant(SSECC, MVT::i8));
12149 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
12150 /// operand \p Op1. If non-trivial (for example because it's not constant)
12151 /// return an empty value.
12152 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
12154 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
12158 MVT VT = Op1.getSimpleValueType();
12159 MVT EVT = VT.getVectorElementType();
12160 unsigned n = VT.getVectorNumElements();
12161 SmallVector<SDValue, 8> ULTOp1;
12163 for (unsigned i = 0; i < n; ++i) {
12164 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
12165 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
12168 // Avoid underflow.
12169 APInt Val = Elt->getAPIntValue();
12173 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
12176 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
12179 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
12180 SelectionDAG &DAG) {
12181 SDValue Op0 = Op.getOperand(0);
12182 SDValue Op1 = Op.getOperand(1);
12183 SDValue CC = Op.getOperand(2);
12184 MVT VT = Op.getSimpleValueType();
12185 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12186 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
12191 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
12192 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
12195 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
12196 unsigned Opc = X86ISD::CMPP;
12197 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
12198 assert(VT.getVectorNumElements() <= 16);
12199 Opc = X86ISD::CMPM;
12201 // In the two special cases we can't handle, emit two comparisons.
12204 unsigned CombineOpc;
12205 if (SetCCOpcode == ISD::SETUEQ) {
12206 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
12208 assert(SetCCOpcode == ISD::SETONE);
12209 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
12212 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12213 DAG.getConstant(CC0, MVT::i8));
12214 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12215 DAG.getConstant(CC1, MVT::i8));
12216 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
12218 // Handle all other FP comparisons here.
12219 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12220 DAG.getConstant(SSECC, MVT::i8));
12223 // Break 256-bit integer vector compare into smaller ones.
12224 if (VT.is256BitVector() && !Subtarget->hasInt256())
12225 return Lower256IntVSETCC(Op, DAG);
12227 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
12228 EVT OpVT = Op1.getValueType();
12229 if (Subtarget->hasAVX512()) {
12230 if (Op1.getValueType().is512BitVector() ||
12231 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
12232 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
12234 // In AVX-512 architecture setcc returns mask with i1 elements,
12235 // But there is no compare instruction for i8 and i16 elements.
12236 // We are not talking about 512-bit operands in this case, these
12237 // types are illegal.
12239 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
12240 OpVT.getVectorElementType().getSizeInBits() >= 8))
12241 return DAG.getNode(ISD::TRUNCATE, dl, VT,
12242 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
12245 // We are handling one of the integer comparisons here. Since SSE only has
12246 // GT and EQ comparisons for integer, swapping operands and multiple
12247 // operations may be required for some comparisons.
12249 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
12250 bool Subus = false;
12252 switch (SetCCOpcode) {
12253 default: llvm_unreachable("Unexpected SETCC condition");
12254 case ISD::SETNE: Invert = true;
12255 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
12256 case ISD::SETLT: Swap = true;
12257 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
12258 case ISD::SETGE: Swap = true;
12259 case ISD::SETLE: Opc = X86ISD::PCMPGT;
12260 Invert = true; break;
12261 case ISD::SETULT: Swap = true;
12262 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
12263 FlipSigns = true; break;
12264 case ISD::SETUGE: Swap = true;
12265 case ISD::SETULE: Opc = X86ISD::PCMPGT;
12266 FlipSigns = true; Invert = true; break;
12269 // Special case: Use min/max operations for SETULE/SETUGE
12270 MVT VET = VT.getVectorElementType();
12272 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
12273 || (Subtarget->hasSSE2() && (VET == MVT::i8));
12276 switch (SetCCOpcode) {
12278 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
12279 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
12282 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
12285 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
12286 if (!MinMax && hasSubus) {
12287 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
12289 // t = psubus Op0, Op1
12290 // pcmpeq t, <0..0>
12291 switch (SetCCOpcode) {
12293 case ISD::SETULT: {
12294 // If the comparison is against a constant we can turn this into a
12295 // setule. With psubus, setule does not require a swap. This is
12296 // beneficial because the constant in the register is no longer
12297 // destructed as the destination so it can be hoisted out of a loop.
12298 // Only do this pre-AVX since vpcmp* is no longer destructive.
12299 if (Subtarget->hasAVX())
12301 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
12302 if (ULEOp1.getNode()) {
12304 Subus = true; Invert = false; Swap = false;
12308 // Psubus is better than flip-sign because it requires no inversion.
12309 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
12310 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
12314 Opc = X86ISD::SUBUS;
12320 std::swap(Op0, Op1);
12322 // Check that the operation in question is available (most are plain SSE2,
12323 // but PCMPGTQ and PCMPEQQ have different requirements).
12324 if (VT == MVT::v2i64) {
12325 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
12326 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
12328 // First cast everything to the right type.
12329 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12330 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12332 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12333 // bits of the inputs before performing those operations. The lower
12334 // compare is always unsigned.
12337 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
12339 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
12340 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
12341 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
12342 Sign, Zero, Sign, Zero);
12344 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
12345 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
12347 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
12348 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
12349 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
12351 // Create masks for only the low parts/high parts of the 64 bit integers.
12352 static const int MaskHi[] = { 1, 1, 3, 3 };
12353 static const int MaskLo[] = { 0, 0, 2, 2 };
12354 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
12355 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
12356 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
12358 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
12359 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
12362 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12364 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12367 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
12368 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
12369 // pcmpeqd + pshufd + pand.
12370 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
12372 // First cast everything to the right type.
12373 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12374 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12377 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
12379 // Make sure the lower and upper halves are both all-ones.
12380 static const int Mask[] = { 1, 0, 3, 2 };
12381 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
12382 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
12385 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12387 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12391 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12392 // bits of the inputs before performing those operations.
12394 EVT EltVT = VT.getVectorElementType();
12395 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
12396 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
12397 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
12400 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
12402 // If the logical-not of the result is required, perform that now.
12404 Result = DAG.getNOT(dl, Result, VT);
12407 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
12410 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
12411 getZeroVector(VT, Subtarget, DAG, dl));
12416 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
12418 MVT VT = Op.getSimpleValueType();
12420 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
12422 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
12423 && "SetCC type must be 8-bit or 1-bit integer");
12424 SDValue Op0 = Op.getOperand(0);
12425 SDValue Op1 = Op.getOperand(1);
12427 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
12429 // Optimize to BT if possible.
12430 // Lower (X & (1 << N)) == 0 to BT(X, N).
12431 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
12432 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
12433 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
12434 Op1.getOpcode() == ISD::Constant &&
12435 cast<ConstantSDNode>(Op1)->isNullValue() &&
12436 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12437 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
12438 if (NewSetCC.getNode())
12442 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
12444 if (Op1.getOpcode() == ISD::Constant &&
12445 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
12446 cast<ConstantSDNode>(Op1)->isNullValue()) &&
12447 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12449 // If the input is a setcc, then reuse the input setcc or use a new one with
12450 // the inverted condition.
12451 if (Op0.getOpcode() == X86ISD::SETCC) {
12452 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
12453 bool Invert = (CC == ISD::SETNE) ^
12454 cast<ConstantSDNode>(Op1)->isNullValue();
12458 CCode = X86::GetOppositeBranchCondition(CCode);
12459 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12460 DAG.getConstant(CCode, MVT::i8),
12461 Op0.getOperand(1));
12463 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12467 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
12468 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
12469 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12471 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
12472 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
12475 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
12476 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
12477 if (X86CC == X86::COND_INVALID)
12480 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
12481 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
12482 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12483 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
12485 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12489 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
12490 static bool isX86LogicalCmp(SDValue Op) {
12491 unsigned Opc = Op.getNode()->getOpcode();
12492 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
12493 Opc == X86ISD::SAHF)
12495 if (Op.getResNo() == 1 &&
12496 (Opc == X86ISD::ADD ||
12497 Opc == X86ISD::SUB ||
12498 Opc == X86ISD::ADC ||
12499 Opc == X86ISD::SBB ||
12500 Opc == X86ISD::SMUL ||
12501 Opc == X86ISD::UMUL ||
12502 Opc == X86ISD::INC ||
12503 Opc == X86ISD::DEC ||
12504 Opc == X86ISD::OR ||
12505 Opc == X86ISD::XOR ||
12506 Opc == X86ISD::AND))
12509 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
12515 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
12516 if (V.getOpcode() != ISD::TRUNCATE)
12519 SDValue VOp0 = V.getOperand(0);
12520 unsigned InBits = VOp0.getValueSizeInBits();
12521 unsigned Bits = V.getValueSizeInBits();
12522 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
12525 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
12526 bool addTest = true;
12527 SDValue Cond = Op.getOperand(0);
12528 SDValue Op1 = Op.getOperand(1);
12529 SDValue Op2 = Op.getOperand(2);
12531 EVT VT = Op1.getValueType();
12534 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
12535 // are available. Otherwise fp cmovs get lowered into a less efficient branch
12536 // sequence later on.
12537 if (Cond.getOpcode() == ISD::SETCC &&
12538 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
12539 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
12540 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
12541 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
12542 int SSECC = translateX86FSETCC(
12543 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
12546 if (Subtarget->hasAVX512()) {
12547 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
12548 DAG.getConstant(SSECC, MVT::i8));
12549 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
12551 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
12552 DAG.getConstant(SSECC, MVT::i8));
12553 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
12554 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
12555 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
12559 if (Cond.getOpcode() == ISD::SETCC) {
12560 SDValue NewCond = LowerSETCC(Cond, DAG);
12561 if (NewCond.getNode())
12565 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
12566 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
12567 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
12568 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
12569 if (Cond.getOpcode() == X86ISD::SETCC &&
12570 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
12571 isZero(Cond.getOperand(1).getOperand(1))) {
12572 SDValue Cmp = Cond.getOperand(1);
12574 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
12576 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
12577 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
12578 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
12580 SDValue CmpOp0 = Cmp.getOperand(0);
12581 // Apply further optimizations for special cases
12582 // (select (x != 0), -1, 0) -> neg & sbb
12583 // (select (x == 0), 0, -1) -> neg & sbb
12584 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
12585 if (YC->isNullValue() &&
12586 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
12587 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
12588 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
12589 DAG.getConstant(0, CmpOp0.getValueType()),
12591 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12592 DAG.getConstant(X86::COND_B, MVT::i8),
12593 SDValue(Neg.getNode(), 1));
12597 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
12598 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
12599 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
12601 SDValue Res = // Res = 0 or -1.
12602 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12603 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
12605 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
12606 Res = DAG.getNOT(DL, Res, Res.getValueType());
12608 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
12609 if (!N2C || !N2C->isNullValue())
12610 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
12615 // Look past (and (setcc_carry (cmp ...)), 1).
12616 if (Cond.getOpcode() == ISD::AND &&
12617 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
12618 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
12619 if (C && C->getAPIntValue() == 1)
12620 Cond = Cond.getOperand(0);
12623 // If condition flag is set by a X86ISD::CMP, then use it as the condition
12624 // setting operand in place of the X86ISD::SETCC.
12625 unsigned CondOpcode = Cond.getOpcode();
12626 if (CondOpcode == X86ISD::SETCC ||
12627 CondOpcode == X86ISD::SETCC_CARRY) {
12628 CC = Cond.getOperand(0);
12630 SDValue Cmp = Cond.getOperand(1);
12631 unsigned Opc = Cmp.getOpcode();
12632 MVT VT = Op.getSimpleValueType();
12634 bool IllegalFPCMov = false;
12635 if (VT.isFloatingPoint() && !VT.isVector() &&
12636 !isScalarFPTypeInSSEReg(VT)) // FPStack?
12637 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
12639 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
12640 Opc == X86ISD::BT) { // FIXME
12644 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
12645 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
12646 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
12647 Cond.getOperand(0).getValueType() != MVT::i8)) {
12648 SDValue LHS = Cond.getOperand(0);
12649 SDValue RHS = Cond.getOperand(1);
12650 unsigned X86Opcode;
12653 switch (CondOpcode) {
12654 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
12655 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
12656 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
12657 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
12658 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
12659 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
12660 default: llvm_unreachable("unexpected overflowing operator");
12662 if (CondOpcode == ISD::UMULO)
12663 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
12666 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
12668 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
12670 if (CondOpcode == ISD::UMULO)
12671 Cond = X86Op.getValue(2);
12673 Cond = X86Op.getValue(1);
12675 CC = DAG.getConstant(X86Cond, MVT::i8);
12680 // Look pass the truncate if the high bits are known zero.
12681 if (isTruncWithZeroHighBitsInput(Cond, DAG))
12682 Cond = Cond.getOperand(0);
12684 // We know the result of AND is compared against zero. Try to match
12686 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
12687 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
12688 if (NewSetCC.getNode()) {
12689 CC = NewSetCC.getOperand(0);
12690 Cond = NewSetCC.getOperand(1);
12697 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12698 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
12701 // a < b ? -1 : 0 -> RES = ~setcc_carry
12702 // a < b ? 0 : -1 -> RES = setcc_carry
12703 // a >= b ? -1 : 0 -> RES = setcc_carry
12704 // a >= b ? 0 : -1 -> RES = ~setcc_carry
12705 if (Cond.getOpcode() == X86ISD::SUB) {
12706 Cond = ConvertCmpIfNecessary(Cond, DAG);
12707 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
12709 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
12710 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
12711 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12712 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
12713 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
12714 return DAG.getNOT(DL, Res, Res.getValueType());
12719 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
12720 // widen the cmov and push the truncate through. This avoids introducing a new
12721 // branch during isel and doesn't add any extensions.
12722 if (Op.getValueType() == MVT::i8 &&
12723 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
12724 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
12725 if (T1.getValueType() == T2.getValueType() &&
12726 // Blacklist CopyFromReg to avoid partial register stalls.
12727 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
12728 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
12729 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
12730 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
12734 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
12735 // condition is true.
12736 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
12737 SDValue Ops[] = { Op2, Op1, CC, Cond };
12738 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
12741 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
12742 MVT VT = Op->getSimpleValueType(0);
12743 SDValue In = Op->getOperand(0);
12744 MVT InVT = In.getSimpleValueType();
12747 unsigned int NumElts = VT.getVectorNumElements();
12748 if (NumElts != 8 && NumElts != 16)
12751 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12752 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
12754 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12755 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12757 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
12758 Constant *C = ConstantInt::get(*DAG.getContext(),
12759 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
12761 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
12762 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12763 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
12764 MachinePointerInfo::getConstantPool(),
12765 false, false, false, Alignment);
12766 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
12767 if (VT.is512BitVector())
12769 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
12772 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12773 SelectionDAG &DAG) {
12774 MVT VT = Op->getSimpleValueType(0);
12775 SDValue In = Op->getOperand(0);
12776 MVT InVT = In.getSimpleValueType();
12779 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
12780 return LowerSIGN_EXTEND_AVX512(Op, DAG);
12782 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
12783 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
12784 (VT != MVT::v16i16 || InVT != MVT::v16i8))
12787 if (Subtarget->hasInt256())
12788 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
12790 // Optimize vectors in AVX mode
12791 // Sign extend v8i16 to v8i32 and
12794 // Divide input vector into two parts
12795 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
12796 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
12797 // concat the vectors to original VT
12799 unsigned NumElems = InVT.getVectorNumElements();
12800 SDValue Undef = DAG.getUNDEF(InVT);
12802 SmallVector<int,8> ShufMask1(NumElems, -1);
12803 for (unsigned i = 0; i != NumElems/2; ++i)
12806 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
12808 SmallVector<int,8> ShufMask2(NumElems, -1);
12809 for (unsigned i = 0; i != NumElems/2; ++i)
12810 ShufMask2[i] = i + NumElems/2;
12812 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
12814 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
12815 VT.getVectorNumElements()/2);
12817 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
12818 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
12820 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12823 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
12824 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
12825 // from the AND / OR.
12826 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
12827 Opc = Op.getOpcode();
12828 if (Opc != ISD::OR && Opc != ISD::AND)
12830 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
12831 Op.getOperand(0).hasOneUse() &&
12832 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
12833 Op.getOperand(1).hasOneUse());
12836 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
12837 // 1 and that the SETCC node has a single use.
12838 static bool isXor1OfSetCC(SDValue Op) {
12839 if (Op.getOpcode() != ISD::XOR)
12841 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
12842 if (N1C && N1C->getAPIntValue() == 1) {
12843 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
12844 Op.getOperand(0).hasOneUse();
12849 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
12850 bool addTest = true;
12851 SDValue Chain = Op.getOperand(0);
12852 SDValue Cond = Op.getOperand(1);
12853 SDValue Dest = Op.getOperand(2);
12856 bool Inverted = false;
12858 if (Cond.getOpcode() == ISD::SETCC) {
12859 // Check for setcc([su]{add,sub,mul}o == 0).
12860 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
12861 isa<ConstantSDNode>(Cond.getOperand(1)) &&
12862 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
12863 Cond.getOperand(0).getResNo() == 1 &&
12864 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
12865 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
12866 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
12867 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
12868 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
12869 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
12871 Cond = Cond.getOperand(0);
12873 SDValue NewCond = LowerSETCC(Cond, DAG);
12874 if (NewCond.getNode())
12879 // FIXME: LowerXALUO doesn't handle these!!
12880 else if (Cond.getOpcode() == X86ISD::ADD ||
12881 Cond.getOpcode() == X86ISD::SUB ||
12882 Cond.getOpcode() == X86ISD::SMUL ||
12883 Cond.getOpcode() == X86ISD::UMUL)
12884 Cond = LowerXALUO(Cond, DAG);
12887 // Look pass (and (setcc_carry (cmp ...)), 1).
12888 if (Cond.getOpcode() == ISD::AND &&
12889 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
12890 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
12891 if (C && C->getAPIntValue() == 1)
12892 Cond = Cond.getOperand(0);
12895 // If condition flag is set by a X86ISD::CMP, then use it as the condition
12896 // setting operand in place of the X86ISD::SETCC.
12897 unsigned CondOpcode = Cond.getOpcode();
12898 if (CondOpcode == X86ISD::SETCC ||
12899 CondOpcode == X86ISD::SETCC_CARRY) {
12900 CC = Cond.getOperand(0);
12902 SDValue Cmp = Cond.getOperand(1);
12903 unsigned Opc = Cmp.getOpcode();
12904 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
12905 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
12909 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
12913 // These can only come from an arithmetic instruction with overflow,
12914 // e.g. SADDO, UADDO.
12915 Cond = Cond.getNode()->getOperand(1);
12921 CondOpcode = Cond.getOpcode();
12922 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
12923 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
12924 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
12925 Cond.getOperand(0).getValueType() != MVT::i8)) {
12926 SDValue LHS = Cond.getOperand(0);
12927 SDValue RHS = Cond.getOperand(1);
12928 unsigned X86Opcode;
12931 // Keep this in sync with LowerXALUO, otherwise we might create redundant
12932 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
12934 switch (CondOpcode) {
12935 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
12937 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12939 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
12942 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
12943 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
12945 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12947 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
12950 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
12951 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
12952 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
12953 default: llvm_unreachable("unexpected overflowing operator");
12956 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
12957 if (CondOpcode == ISD::UMULO)
12958 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
12961 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
12963 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
12965 if (CondOpcode == ISD::UMULO)
12966 Cond = X86Op.getValue(2);
12968 Cond = X86Op.getValue(1);
12970 CC = DAG.getConstant(X86Cond, MVT::i8);
12974 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
12975 SDValue Cmp = Cond.getOperand(0).getOperand(1);
12976 if (CondOpc == ISD::OR) {
12977 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
12978 // two branches instead of an explicit OR instruction with a
12980 if (Cmp == Cond.getOperand(1).getOperand(1) &&
12981 isX86LogicalCmp(Cmp)) {
12982 CC = Cond.getOperand(0).getOperand(0);
12983 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
12984 Chain, Dest, CC, Cmp);
12985 CC = Cond.getOperand(1).getOperand(0);
12989 } else { // ISD::AND
12990 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
12991 // two branches instead of an explicit AND instruction with a
12992 // separate test. However, we only do this if this block doesn't
12993 // have a fall-through edge, because this requires an explicit
12994 // jmp when the condition is false.
12995 if (Cmp == Cond.getOperand(1).getOperand(1) &&
12996 isX86LogicalCmp(Cmp) &&
12997 Op.getNode()->hasOneUse()) {
12998 X86::CondCode CCode =
12999 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13000 CCode = X86::GetOppositeBranchCondition(CCode);
13001 CC = DAG.getConstant(CCode, MVT::i8);
13002 SDNode *User = *Op.getNode()->use_begin();
13003 // Look for an unconditional branch following this conditional branch.
13004 // We need this because we need to reverse the successors in order
13005 // to implement FCMP_OEQ.
13006 if (User->getOpcode() == ISD::BR) {
13007 SDValue FalseBB = User->getOperand(1);
13009 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13010 assert(NewBR == User);
13014 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13015 Chain, Dest, CC, Cmp);
13016 X86::CondCode CCode =
13017 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
13018 CCode = X86::GetOppositeBranchCondition(CCode);
13019 CC = DAG.getConstant(CCode, MVT::i8);
13025 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
13026 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
13027 // It should be transformed during dag combiner except when the condition
13028 // is set by a arithmetics with overflow node.
13029 X86::CondCode CCode =
13030 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13031 CCode = X86::GetOppositeBranchCondition(CCode);
13032 CC = DAG.getConstant(CCode, MVT::i8);
13033 Cond = Cond.getOperand(0).getOperand(1);
13035 } else if (Cond.getOpcode() == ISD::SETCC &&
13036 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
13037 // For FCMP_OEQ, we can emit
13038 // two branches instead of an explicit AND instruction with a
13039 // separate test. However, we only do this if this block doesn't
13040 // have a fall-through edge, because this requires an explicit
13041 // jmp when the condition is false.
13042 if (Op.getNode()->hasOneUse()) {
13043 SDNode *User = *Op.getNode()->use_begin();
13044 // Look for an unconditional branch following this conditional branch.
13045 // We need this because we need to reverse the successors in order
13046 // to implement FCMP_OEQ.
13047 if (User->getOpcode() == ISD::BR) {
13048 SDValue FalseBB = User->getOperand(1);
13050 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13051 assert(NewBR == User);
13055 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13056 Cond.getOperand(0), Cond.getOperand(1));
13057 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13058 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13059 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13060 Chain, Dest, CC, Cmp);
13061 CC = DAG.getConstant(X86::COND_P, MVT::i8);
13066 } else if (Cond.getOpcode() == ISD::SETCC &&
13067 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
13068 // For FCMP_UNE, we can emit
13069 // two branches instead of an explicit AND instruction with a
13070 // separate test. However, we only do this if this block doesn't
13071 // have a fall-through edge, because this requires an explicit
13072 // jmp when the condition is false.
13073 if (Op.getNode()->hasOneUse()) {
13074 SDNode *User = *Op.getNode()->use_begin();
13075 // Look for an unconditional branch following this conditional branch.
13076 // We need this because we need to reverse the successors in order
13077 // to implement FCMP_UNE.
13078 if (User->getOpcode() == ISD::BR) {
13079 SDValue FalseBB = User->getOperand(1);
13081 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13082 assert(NewBR == User);
13085 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13086 Cond.getOperand(0), Cond.getOperand(1));
13087 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13088 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13089 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13090 Chain, Dest, CC, Cmp);
13091 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
13101 // Look pass the truncate if the high bits are known zero.
13102 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13103 Cond = Cond.getOperand(0);
13105 // We know the result of AND is compared against zero. Try to match
13107 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13108 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
13109 if (NewSetCC.getNode()) {
13110 CC = NewSetCC.getOperand(0);
13111 Cond = NewSetCC.getOperand(1);
13118 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
13119 CC = DAG.getConstant(X86Cond, MVT::i8);
13120 Cond = EmitTest(Cond, X86Cond, dl, DAG);
13122 Cond = ConvertCmpIfNecessary(Cond, DAG);
13123 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13124 Chain, Dest, CC, Cond);
13127 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
13128 // Calls to _alloca is needed to probe the stack when allocating more than 4k
13129 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
13130 // that the guard pages used by the OS virtual memory manager are allocated in
13131 // correct sequence.
13133 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
13134 SelectionDAG &DAG) const {
13135 MachineFunction &MF = DAG.getMachineFunction();
13136 bool SplitStack = MF.shouldSplitStack();
13137 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
13142 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13143 SDNode* Node = Op.getNode();
13145 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
13146 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
13147 " not tell us which reg is the stack pointer!");
13148 EVT VT = Node->getValueType(0);
13149 SDValue Tmp1 = SDValue(Node, 0);
13150 SDValue Tmp2 = SDValue(Node, 1);
13151 SDValue Tmp3 = Node->getOperand(2);
13152 SDValue Chain = Tmp1.getOperand(0);
13154 // Chain the dynamic stack allocation so that it doesn't modify the stack
13155 // pointer when other instructions are using the stack.
13156 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
13159 SDValue Size = Tmp2.getOperand(1);
13160 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
13161 Chain = SP.getValue(1);
13162 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
13163 const TargetFrameLowering &TFI = *DAG.getTarget().getFrameLowering();
13164 unsigned StackAlign = TFI.getStackAlignment();
13165 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
13166 if (Align > StackAlign)
13167 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
13168 DAG.getConstant(-(uint64_t)Align, VT));
13169 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
13171 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
13172 DAG.getIntPtrConstant(0, true), SDValue(),
13175 SDValue Ops[2] = { Tmp1, Tmp2 };
13176 return DAG.getMergeValues(Ops, dl);
13180 SDValue Chain = Op.getOperand(0);
13181 SDValue Size = Op.getOperand(1);
13182 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
13183 EVT VT = Op.getNode()->getValueType(0);
13185 bool Is64Bit = Subtarget->is64Bit();
13186 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
13189 MachineRegisterInfo &MRI = MF.getRegInfo();
13192 // The 64 bit implementation of segmented stacks needs to clobber both r10
13193 // r11. This makes it impossible to use it along with nested parameters.
13194 const Function *F = MF.getFunction();
13196 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
13198 if (I->hasNestAttr())
13199 report_fatal_error("Cannot use segmented stacks with functions that "
13200 "have nested arguments.");
13203 const TargetRegisterClass *AddrRegClass =
13204 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
13205 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
13206 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
13207 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
13208 DAG.getRegister(Vreg, SPTy));
13209 SDValue Ops1[2] = { Value, Chain };
13210 return DAG.getMergeValues(Ops1, dl);
13213 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
13215 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
13216 Flag = Chain.getValue(1);
13217 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13219 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
13221 const X86RegisterInfo *RegInfo =
13222 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
13223 unsigned SPReg = RegInfo->getStackRegister();
13224 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
13225 Chain = SP.getValue(1);
13228 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
13229 DAG.getConstant(-(uint64_t)Align, VT));
13230 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
13233 SDValue Ops1[2] = { SP, Chain };
13234 return DAG.getMergeValues(Ops1, dl);
13238 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
13239 MachineFunction &MF = DAG.getMachineFunction();
13240 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
13242 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13245 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
13246 // vastart just stores the address of the VarArgsFrameIndex slot into the
13247 // memory location argument.
13248 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13250 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
13251 MachinePointerInfo(SV), false, false, 0);
13255 // gp_offset (0 - 6 * 8)
13256 // fp_offset (48 - 48 + 8 * 16)
13257 // overflow_arg_area (point to parameters coming in memory).
13259 SmallVector<SDValue, 8> MemOps;
13260 SDValue FIN = Op.getOperand(1);
13262 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
13263 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
13265 FIN, MachinePointerInfo(SV), false, false, 0);
13266 MemOps.push_back(Store);
13269 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13270 FIN, DAG.getIntPtrConstant(4));
13271 Store = DAG.getStore(Op.getOperand(0), DL,
13272 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
13274 FIN, MachinePointerInfo(SV, 4), false, false, 0);
13275 MemOps.push_back(Store);
13277 // Store ptr to overflow_arg_area
13278 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13279 FIN, DAG.getIntPtrConstant(4));
13280 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13282 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
13283 MachinePointerInfo(SV, 8),
13285 MemOps.push_back(Store);
13287 // Store ptr to reg_save_area.
13288 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13289 FIN, DAG.getIntPtrConstant(8));
13290 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
13292 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
13293 MachinePointerInfo(SV, 16), false, false, 0);
13294 MemOps.push_back(Store);
13295 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
13298 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
13299 assert(Subtarget->is64Bit() &&
13300 "LowerVAARG only handles 64-bit va_arg!");
13301 assert((Subtarget->isTargetLinux() ||
13302 Subtarget->isTargetDarwin()) &&
13303 "Unhandled target in LowerVAARG");
13304 assert(Op.getNode()->getNumOperands() == 4);
13305 SDValue Chain = Op.getOperand(0);
13306 SDValue SrcPtr = Op.getOperand(1);
13307 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13308 unsigned Align = Op.getConstantOperandVal(3);
13311 EVT ArgVT = Op.getNode()->getValueType(0);
13312 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13313 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
13316 // Decide which area this value should be read from.
13317 // TODO: Implement the AMD64 ABI in its entirety. This simple
13318 // selection mechanism works only for the basic types.
13319 if (ArgVT == MVT::f80) {
13320 llvm_unreachable("va_arg for f80 not yet implemented");
13321 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
13322 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
13323 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
13324 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
13326 llvm_unreachable("Unhandled argument type in LowerVAARG");
13329 if (ArgMode == 2) {
13330 // Sanity Check: Make sure using fp_offset makes sense.
13331 assert(!DAG.getTarget().Options.UseSoftFloat &&
13332 !(DAG.getMachineFunction()
13333 .getFunction()->getAttributes()
13334 .hasAttribute(AttributeSet::FunctionIndex,
13335 Attribute::NoImplicitFloat)) &&
13336 Subtarget->hasSSE1());
13339 // Insert VAARG_64 node into the DAG
13340 // VAARG_64 returns two values: Variable Argument Address, Chain
13341 SmallVector<SDValue, 11> InstOps;
13342 InstOps.push_back(Chain);
13343 InstOps.push_back(SrcPtr);
13344 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
13345 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
13346 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
13347 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
13348 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
13349 VTs, InstOps, MVT::i64,
13350 MachinePointerInfo(SV),
13352 /*Volatile=*/false,
13354 /*WriteMem=*/true);
13355 Chain = VAARG.getValue(1);
13357 // Load the next argument and return it
13358 return DAG.getLoad(ArgVT, dl,
13361 MachinePointerInfo(),
13362 false, false, false, 0);
13365 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
13366 SelectionDAG &DAG) {
13367 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
13368 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
13369 SDValue Chain = Op.getOperand(0);
13370 SDValue DstPtr = Op.getOperand(1);
13371 SDValue SrcPtr = Op.getOperand(2);
13372 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
13373 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
13376 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
13377 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
13379 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
13382 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
13383 // amount is a constant. Takes immediate version of shift as input.
13384 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
13385 SDValue SrcOp, uint64_t ShiftAmt,
13386 SelectionDAG &DAG) {
13387 MVT ElementType = VT.getVectorElementType();
13389 // Fold this packed shift into its first operand if ShiftAmt is 0.
13393 // Check for ShiftAmt >= element width
13394 if (ShiftAmt >= ElementType.getSizeInBits()) {
13395 if (Opc == X86ISD::VSRAI)
13396 ShiftAmt = ElementType.getSizeInBits() - 1;
13398 return DAG.getConstant(0, VT);
13401 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
13402 && "Unknown target vector shift-by-constant node");
13404 // Fold this packed vector shift into a build vector if SrcOp is a
13405 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
13406 if (VT == SrcOp.getSimpleValueType() &&
13407 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
13408 SmallVector<SDValue, 8> Elts;
13409 unsigned NumElts = SrcOp->getNumOperands();
13410 ConstantSDNode *ND;
13413 default: llvm_unreachable(nullptr);
13414 case X86ISD::VSHLI:
13415 for (unsigned i=0; i!=NumElts; ++i) {
13416 SDValue CurrentOp = SrcOp->getOperand(i);
13417 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13418 Elts.push_back(CurrentOp);
13421 ND = cast<ConstantSDNode>(CurrentOp);
13422 const APInt &C = ND->getAPIntValue();
13423 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
13426 case X86ISD::VSRLI:
13427 for (unsigned i=0; i!=NumElts; ++i) {
13428 SDValue CurrentOp = SrcOp->getOperand(i);
13429 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13430 Elts.push_back(CurrentOp);
13433 ND = cast<ConstantSDNode>(CurrentOp);
13434 const APInt &C = ND->getAPIntValue();
13435 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
13438 case X86ISD::VSRAI:
13439 for (unsigned i=0; i!=NumElts; ++i) {
13440 SDValue CurrentOp = SrcOp->getOperand(i);
13441 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13442 Elts.push_back(CurrentOp);
13445 ND = cast<ConstantSDNode>(CurrentOp);
13446 const APInt &C = ND->getAPIntValue();
13447 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
13452 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
13455 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
13458 // getTargetVShiftNode - Handle vector element shifts where the shift amount
13459 // may or may not be a constant. Takes immediate version of shift as input.
13460 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
13461 SDValue SrcOp, SDValue ShAmt,
13462 SelectionDAG &DAG) {
13463 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
13465 // Catch shift-by-constant.
13466 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
13467 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
13468 CShAmt->getZExtValue(), DAG);
13470 // Change opcode to non-immediate version
13472 default: llvm_unreachable("Unknown target vector shift node");
13473 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
13474 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
13475 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
13478 // Need to build a vector containing shift amount
13479 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
13482 ShOps[1] = DAG.getConstant(0, MVT::i32);
13483 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
13484 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
13486 // The return type has to be a 128-bit type with the same element
13487 // type as the input type.
13488 MVT EltVT = VT.getVectorElementType();
13489 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
13491 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
13492 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
13495 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
13497 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
13499 default: return SDValue(); // Don't custom lower most intrinsics.
13500 // Comparison intrinsics.
13501 case Intrinsic::x86_sse_comieq_ss:
13502 case Intrinsic::x86_sse_comilt_ss:
13503 case Intrinsic::x86_sse_comile_ss:
13504 case Intrinsic::x86_sse_comigt_ss:
13505 case Intrinsic::x86_sse_comige_ss:
13506 case Intrinsic::x86_sse_comineq_ss:
13507 case Intrinsic::x86_sse_ucomieq_ss:
13508 case Intrinsic::x86_sse_ucomilt_ss:
13509 case Intrinsic::x86_sse_ucomile_ss:
13510 case Intrinsic::x86_sse_ucomigt_ss:
13511 case Intrinsic::x86_sse_ucomige_ss:
13512 case Intrinsic::x86_sse_ucomineq_ss:
13513 case Intrinsic::x86_sse2_comieq_sd:
13514 case Intrinsic::x86_sse2_comilt_sd:
13515 case Intrinsic::x86_sse2_comile_sd:
13516 case Intrinsic::x86_sse2_comigt_sd:
13517 case Intrinsic::x86_sse2_comige_sd:
13518 case Intrinsic::x86_sse2_comineq_sd:
13519 case Intrinsic::x86_sse2_ucomieq_sd:
13520 case Intrinsic::x86_sse2_ucomilt_sd:
13521 case Intrinsic::x86_sse2_ucomile_sd:
13522 case Intrinsic::x86_sse2_ucomigt_sd:
13523 case Intrinsic::x86_sse2_ucomige_sd:
13524 case Intrinsic::x86_sse2_ucomineq_sd: {
13528 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13529 case Intrinsic::x86_sse_comieq_ss:
13530 case Intrinsic::x86_sse2_comieq_sd:
13531 Opc = X86ISD::COMI;
13534 case Intrinsic::x86_sse_comilt_ss:
13535 case Intrinsic::x86_sse2_comilt_sd:
13536 Opc = X86ISD::COMI;
13539 case Intrinsic::x86_sse_comile_ss:
13540 case Intrinsic::x86_sse2_comile_sd:
13541 Opc = X86ISD::COMI;
13544 case Intrinsic::x86_sse_comigt_ss:
13545 case Intrinsic::x86_sse2_comigt_sd:
13546 Opc = X86ISD::COMI;
13549 case Intrinsic::x86_sse_comige_ss:
13550 case Intrinsic::x86_sse2_comige_sd:
13551 Opc = X86ISD::COMI;
13554 case Intrinsic::x86_sse_comineq_ss:
13555 case Intrinsic::x86_sse2_comineq_sd:
13556 Opc = X86ISD::COMI;
13559 case Intrinsic::x86_sse_ucomieq_ss:
13560 case Intrinsic::x86_sse2_ucomieq_sd:
13561 Opc = X86ISD::UCOMI;
13564 case Intrinsic::x86_sse_ucomilt_ss:
13565 case Intrinsic::x86_sse2_ucomilt_sd:
13566 Opc = X86ISD::UCOMI;
13569 case Intrinsic::x86_sse_ucomile_ss:
13570 case Intrinsic::x86_sse2_ucomile_sd:
13571 Opc = X86ISD::UCOMI;
13574 case Intrinsic::x86_sse_ucomigt_ss:
13575 case Intrinsic::x86_sse2_ucomigt_sd:
13576 Opc = X86ISD::UCOMI;
13579 case Intrinsic::x86_sse_ucomige_ss:
13580 case Intrinsic::x86_sse2_ucomige_sd:
13581 Opc = X86ISD::UCOMI;
13584 case Intrinsic::x86_sse_ucomineq_ss:
13585 case Intrinsic::x86_sse2_ucomineq_sd:
13586 Opc = X86ISD::UCOMI;
13591 SDValue LHS = Op.getOperand(1);
13592 SDValue RHS = Op.getOperand(2);
13593 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
13594 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
13595 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
13596 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13597 DAG.getConstant(X86CC, MVT::i8), Cond);
13598 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
13601 // Arithmetic intrinsics.
13602 case Intrinsic::x86_sse2_pmulu_dq:
13603 case Intrinsic::x86_avx2_pmulu_dq:
13604 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
13605 Op.getOperand(1), Op.getOperand(2));
13607 case Intrinsic::x86_sse41_pmuldq:
13608 case Intrinsic::x86_avx2_pmul_dq:
13609 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
13610 Op.getOperand(1), Op.getOperand(2));
13612 case Intrinsic::x86_sse2_pmulhu_w:
13613 case Intrinsic::x86_avx2_pmulhu_w:
13614 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
13615 Op.getOperand(1), Op.getOperand(2));
13617 case Intrinsic::x86_sse2_pmulh_w:
13618 case Intrinsic::x86_avx2_pmulh_w:
13619 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
13620 Op.getOperand(1), Op.getOperand(2));
13622 // SSE2/AVX2 sub with unsigned saturation intrinsics
13623 case Intrinsic::x86_sse2_psubus_b:
13624 case Intrinsic::x86_sse2_psubus_w:
13625 case Intrinsic::x86_avx2_psubus_b:
13626 case Intrinsic::x86_avx2_psubus_w:
13627 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
13628 Op.getOperand(1), Op.getOperand(2));
13630 // SSE3/AVX horizontal add/sub intrinsics
13631 case Intrinsic::x86_sse3_hadd_ps:
13632 case Intrinsic::x86_sse3_hadd_pd:
13633 case Intrinsic::x86_avx_hadd_ps_256:
13634 case Intrinsic::x86_avx_hadd_pd_256:
13635 case Intrinsic::x86_sse3_hsub_ps:
13636 case Intrinsic::x86_sse3_hsub_pd:
13637 case Intrinsic::x86_avx_hsub_ps_256:
13638 case Intrinsic::x86_avx_hsub_pd_256:
13639 case Intrinsic::x86_ssse3_phadd_w_128:
13640 case Intrinsic::x86_ssse3_phadd_d_128:
13641 case Intrinsic::x86_avx2_phadd_w:
13642 case Intrinsic::x86_avx2_phadd_d:
13643 case Intrinsic::x86_ssse3_phsub_w_128:
13644 case Intrinsic::x86_ssse3_phsub_d_128:
13645 case Intrinsic::x86_avx2_phsub_w:
13646 case Intrinsic::x86_avx2_phsub_d: {
13649 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13650 case Intrinsic::x86_sse3_hadd_ps:
13651 case Intrinsic::x86_sse3_hadd_pd:
13652 case Intrinsic::x86_avx_hadd_ps_256:
13653 case Intrinsic::x86_avx_hadd_pd_256:
13654 Opcode = X86ISD::FHADD;
13656 case Intrinsic::x86_sse3_hsub_ps:
13657 case Intrinsic::x86_sse3_hsub_pd:
13658 case Intrinsic::x86_avx_hsub_ps_256:
13659 case Intrinsic::x86_avx_hsub_pd_256:
13660 Opcode = X86ISD::FHSUB;
13662 case Intrinsic::x86_ssse3_phadd_w_128:
13663 case Intrinsic::x86_ssse3_phadd_d_128:
13664 case Intrinsic::x86_avx2_phadd_w:
13665 case Intrinsic::x86_avx2_phadd_d:
13666 Opcode = X86ISD::HADD;
13668 case Intrinsic::x86_ssse3_phsub_w_128:
13669 case Intrinsic::x86_ssse3_phsub_d_128:
13670 case Intrinsic::x86_avx2_phsub_w:
13671 case Intrinsic::x86_avx2_phsub_d:
13672 Opcode = X86ISD::HSUB;
13675 return DAG.getNode(Opcode, dl, Op.getValueType(),
13676 Op.getOperand(1), Op.getOperand(2));
13679 // SSE2/SSE41/AVX2 integer max/min intrinsics.
13680 case Intrinsic::x86_sse2_pmaxu_b:
13681 case Intrinsic::x86_sse41_pmaxuw:
13682 case Intrinsic::x86_sse41_pmaxud:
13683 case Intrinsic::x86_avx2_pmaxu_b:
13684 case Intrinsic::x86_avx2_pmaxu_w:
13685 case Intrinsic::x86_avx2_pmaxu_d:
13686 case Intrinsic::x86_sse2_pminu_b:
13687 case Intrinsic::x86_sse41_pminuw:
13688 case Intrinsic::x86_sse41_pminud:
13689 case Intrinsic::x86_avx2_pminu_b:
13690 case Intrinsic::x86_avx2_pminu_w:
13691 case Intrinsic::x86_avx2_pminu_d:
13692 case Intrinsic::x86_sse41_pmaxsb:
13693 case Intrinsic::x86_sse2_pmaxs_w:
13694 case Intrinsic::x86_sse41_pmaxsd:
13695 case Intrinsic::x86_avx2_pmaxs_b:
13696 case Intrinsic::x86_avx2_pmaxs_w:
13697 case Intrinsic::x86_avx2_pmaxs_d:
13698 case Intrinsic::x86_sse41_pminsb:
13699 case Intrinsic::x86_sse2_pmins_w:
13700 case Intrinsic::x86_sse41_pminsd:
13701 case Intrinsic::x86_avx2_pmins_b:
13702 case Intrinsic::x86_avx2_pmins_w:
13703 case Intrinsic::x86_avx2_pmins_d: {
13706 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13707 case Intrinsic::x86_sse2_pmaxu_b:
13708 case Intrinsic::x86_sse41_pmaxuw:
13709 case Intrinsic::x86_sse41_pmaxud:
13710 case Intrinsic::x86_avx2_pmaxu_b:
13711 case Intrinsic::x86_avx2_pmaxu_w:
13712 case Intrinsic::x86_avx2_pmaxu_d:
13713 Opcode = X86ISD::UMAX;
13715 case Intrinsic::x86_sse2_pminu_b:
13716 case Intrinsic::x86_sse41_pminuw:
13717 case Intrinsic::x86_sse41_pminud:
13718 case Intrinsic::x86_avx2_pminu_b:
13719 case Intrinsic::x86_avx2_pminu_w:
13720 case Intrinsic::x86_avx2_pminu_d:
13721 Opcode = X86ISD::UMIN;
13723 case Intrinsic::x86_sse41_pmaxsb:
13724 case Intrinsic::x86_sse2_pmaxs_w:
13725 case Intrinsic::x86_sse41_pmaxsd:
13726 case Intrinsic::x86_avx2_pmaxs_b:
13727 case Intrinsic::x86_avx2_pmaxs_w:
13728 case Intrinsic::x86_avx2_pmaxs_d:
13729 Opcode = X86ISD::SMAX;
13731 case Intrinsic::x86_sse41_pminsb:
13732 case Intrinsic::x86_sse2_pmins_w:
13733 case Intrinsic::x86_sse41_pminsd:
13734 case Intrinsic::x86_avx2_pmins_b:
13735 case Intrinsic::x86_avx2_pmins_w:
13736 case Intrinsic::x86_avx2_pmins_d:
13737 Opcode = X86ISD::SMIN;
13740 return DAG.getNode(Opcode, dl, Op.getValueType(),
13741 Op.getOperand(1), Op.getOperand(2));
13744 // SSE/SSE2/AVX floating point max/min intrinsics.
13745 case Intrinsic::x86_sse_max_ps:
13746 case Intrinsic::x86_sse2_max_pd:
13747 case Intrinsic::x86_avx_max_ps_256:
13748 case Intrinsic::x86_avx_max_pd_256:
13749 case Intrinsic::x86_sse_min_ps:
13750 case Intrinsic::x86_sse2_min_pd:
13751 case Intrinsic::x86_avx_min_ps_256:
13752 case Intrinsic::x86_avx_min_pd_256: {
13755 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13756 case Intrinsic::x86_sse_max_ps:
13757 case Intrinsic::x86_sse2_max_pd:
13758 case Intrinsic::x86_avx_max_ps_256:
13759 case Intrinsic::x86_avx_max_pd_256:
13760 Opcode = X86ISD::FMAX;
13762 case Intrinsic::x86_sse_min_ps:
13763 case Intrinsic::x86_sse2_min_pd:
13764 case Intrinsic::x86_avx_min_ps_256:
13765 case Intrinsic::x86_avx_min_pd_256:
13766 Opcode = X86ISD::FMIN;
13769 return DAG.getNode(Opcode, dl, Op.getValueType(),
13770 Op.getOperand(1), Op.getOperand(2));
13773 // AVX2 variable shift intrinsics
13774 case Intrinsic::x86_avx2_psllv_d:
13775 case Intrinsic::x86_avx2_psllv_q:
13776 case Intrinsic::x86_avx2_psllv_d_256:
13777 case Intrinsic::x86_avx2_psllv_q_256:
13778 case Intrinsic::x86_avx2_psrlv_d:
13779 case Intrinsic::x86_avx2_psrlv_q:
13780 case Intrinsic::x86_avx2_psrlv_d_256:
13781 case Intrinsic::x86_avx2_psrlv_q_256:
13782 case Intrinsic::x86_avx2_psrav_d:
13783 case Intrinsic::x86_avx2_psrav_d_256: {
13786 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13787 case Intrinsic::x86_avx2_psllv_d:
13788 case Intrinsic::x86_avx2_psllv_q:
13789 case Intrinsic::x86_avx2_psllv_d_256:
13790 case Intrinsic::x86_avx2_psllv_q_256:
13793 case Intrinsic::x86_avx2_psrlv_d:
13794 case Intrinsic::x86_avx2_psrlv_q:
13795 case Intrinsic::x86_avx2_psrlv_d_256:
13796 case Intrinsic::x86_avx2_psrlv_q_256:
13799 case Intrinsic::x86_avx2_psrav_d:
13800 case Intrinsic::x86_avx2_psrav_d_256:
13804 return DAG.getNode(Opcode, dl, Op.getValueType(),
13805 Op.getOperand(1), Op.getOperand(2));
13808 case Intrinsic::x86_sse2_packssdw_128:
13809 case Intrinsic::x86_sse2_packsswb_128:
13810 case Intrinsic::x86_avx2_packssdw:
13811 case Intrinsic::x86_avx2_packsswb:
13812 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
13813 Op.getOperand(1), Op.getOperand(2));
13815 case Intrinsic::x86_sse2_packuswb_128:
13816 case Intrinsic::x86_sse41_packusdw:
13817 case Intrinsic::x86_avx2_packuswb:
13818 case Intrinsic::x86_avx2_packusdw:
13819 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
13820 Op.getOperand(1), Op.getOperand(2));
13822 case Intrinsic::x86_ssse3_pshuf_b_128:
13823 case Intrinsic::x86_avx2_pshuf_b:
13824 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
13825 Op.getOperand(1), Op.getOperand(2));
13827 case Intrinsic::x86_sse2_pshuf_d:
13828 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
13829 Op.getOperand(1), Op.getOperand(2));
13831 case Intrinsic::x86_sse2_pshufl_w:
13832 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
13833 Op.getOperand(1), Op.getOperand(2));
13835 case Intrinsic::x86_sse2_pshufh_w:
13836 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
13837 Op.getOperand(1), Op.getOperand(2));
13839 case Intrinsic::x86_ssse3_psign_b_128:
13840 case Intrinsic::x86_ssse3_psign_w_128:
13841 case Intrinsic::x86_ssse3_psign_d_128:
13842 case Intrinsic::x86_avx2_psign_b:
13843 case Intrinsic::x86_avx2_psign_w:
13844 case Intrinsic::x86_avx2_psign_d:
13845 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
13846 Op.getOperand(1), Op.getOperand(2));
13848 case Intrinsic::x86_sse41_insertps:
13849 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
13850 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
13852 case Intrinsic::x86_avx_vperm2f128_ps_256:
13853 case Intrinsic::x86_avx_vperm2f128_pd_256:
13854 case Intrinsic::x86_avx_vperm2f128_si_256:
13855 case Intrinsic::x86_avx2_vperm2i128:
13856 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
13857 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
13859 case Intrinsic::x86_avx2_permd:
13860 case Intrinsic::x86_avx2_permps:
13861 // Operands intentionally swapped. Mask is last operand to intrinsic,
13862 // but second operand for node/instruction.
13863 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
13864 Op.getOperand(2), Op.getOperand(1));
13866 case Intrinsic::x86_sse_sqrt_ps:
13867 case Intrinsic::x86_sse2_sqrt_pd:
13868 case Intrinsic::x86_avx_sqrt_ps_256:
13869 case Intrinsic::x86_avx_sqrt_pd_256:
13870 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
13872 // ptest and testp intrinsics. The intrinsic these come from are designed to
13873 // return an integer value, not just an instruction so lower it to the ptest
13874 // or testp pattern and a setcc for the result.
13875 case Intrinsic::x86_sse41_ptestz:
13876 case Intrinsic::x86_sse41_ptestc:
13877 case Intrinsic::x86_sse41_ptestnzc:
13878 case Intrinsic::x86_avx_ptestz_256:
13879 case Intrinsic::x86_avx_ptestc_256:
13880 case Intrinsic::x86_avx_ptestnzc_256:
13881 case Intrinsic::x86_avx_vtestz_ps:
13882 case Intrinsic::x86_avx_vtestc_ps:
13883 case Intrinsic::x86_avx_vtestnzc_ps:
13884 case Intrinsic::x86_avx_vtestz_pd:
13885 case Intrinsic::x86_avx_vtestc_pd:
13886 case Intrinsic::x86_avx_vtestnzc_pd:
13887 case Intrinsic::x86_avx_vtestz_ps_256:
13888 case Intrinsic::x86_avx_vtestc_ps_256:
13889 case Intrinsic::x86_avx_vtestnzc_ps_256:
13890 case Intrinsic::x86_avx_vtestz_pd_256:
13891 case Intrinsic::x86_avx_vtestc_pd_256:
13892 case Intrinsic::x86_avx_vtestnzc_pd_256: {
13893 bool IsTestPacked = false;
13896 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
13897 case Intrinsic::x86_avx_vtestz_ps:
13898 case Intrinsic::x86_avx_vtestz_pd:
13899 case Intrinsic::x86_avx_vtestz_ps_256:
13900 case Intrinsic::x86_avx_vtestz_pd_256:
13901 IsTestPacked = true; // Fallthrough
13902 case Intrinsic::x86_sse41_ptestz:
13903 case Intrinsic::x86_avx_ptestz_256:
13905 X86CC = X86::COND_E;
13907 case Intrinsic::x86_avx_vtestc_ps:
13908 case Intrinsic::x86_avx_vtestc_pd:
13909 case Intrinsic::x86_avx_vtestc_ps_256:
13910 case Intrinsic::x86_avx_vtestc_pd_256:
13911 IsTestPacked = true; // Fallthrough
13912 case Intrinsic::x86_sse41_ptestc:
13913 case Intrinsic::x86_avx_ptestc_256:
13915 X86CC = X86::COND_B;
13917 case Intrinsic::x86_avx_vtestnzc_ps:
13918 case Intrinsic::x86_avx_vtestnzc_pd:
13919 case Intrinsic::x86_avx_vtestnzc_ps_256:
13920 case Intrinsic::x86_avx_vtestnzc_pd_256:
13921 IsTestPacked = true; // Fallthrough
13922 case Intrinsic::x86_sse41_ptestnzc:
13923 case Intrinsic::x86_avx_ptestnzc_256:
13925 X86CC = X86::COND_A;
13929 SDValue LHS = Op.getOperand(1);
13930 SDValue RHS = Op.getOperand(2);
13931 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
13932 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
13933 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
13934 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
13935 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
13937 case Intrinsic::x86_avx512_kortestz_w:
13938 case Intrinsic::x86_avx512_kortestc_w: {
13939 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
13940 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
13941 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
13942 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
13943 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
13944 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
13945 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
13948 // SSE/AVX shift intrinsics
13949 case Intrinsic::x86_sse2_psll_w:
13950 case Intrinsic::x86_sse2_psll_d:
13951 case Intrinsic::x86_sse2_psll_q:
13952 case Intrinsic::x86_avx2_psll_w:
13953 case Intrinsic::x86_avx2_psll_d:
13954 case Intrinsic::x86_avx2_psll_q:
13955 case Intrinsic::x86_sse2_psrl_w:
13956 case Intrinsic::x86_sse2_psrl_d:
13957 case Intrinsic::x86_sse2_psrl_q:
13958 case Intrinsic::x86_avx2_psrl_w:
13959 case Intrinsic::x86_avx2_psrl_d:
13960 case Intrinsic::x86_avx2_psrl_q:
13961 case Intrinsic::x86_sse2_psra_w:
13962 case Intrinsic::x86_sse2_psra_d:
13963 case Intrinsic::x86_avx2_psra_w:
13964 case Intrinsic::x86_avx2_psra_d: {
13967 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13968 case Intrinsic::x86_sse2_psll_w:
13969 case Intrinsic::x86_sse2_psll_d:
13970 case Intrinsic::x86_sse2_psll_q:
13971 case Intrinsic::x86_avx2_psll_w:
13972 case Intrinsic::x86_avx2_psll_d:
13973 case Intrinsic::x86_avx2_psll_q:
13974 Opcode = X86ISD::VSHL;
13976 case Intrinsic::x86_sse2_psrl_w:
13977 case Intrinsic::x86_sse2_psrl_d:
13978 case Intrinsic::x86_sse2_psrl_q:
13979 case Intrinsic::x86_avx2_psrl_w:
13980 case Intrinsic::x86_avx2_psrl_d:
13981 case Intrinsic::x86_avx2_psrl_q:
13982 Opcode = X86ISD::VSRL;
13984 case Intrinsic::x86_sse2_psra_w:
13985 case Intrinsic::x86_sse2_psra_d:
13986 case Intrinsic::x86_avx2_psra_w:
13987 case Intrinsic::x86_avx2_psra_d:
13988 Opcode = X86ISD::VSRA;
13991 return DAG.getNode(Opcode, dl, Op.getValueType(),
13992 Op.getOperand(1), Op.getOperand(2));
13995 // SSE/AVX immediate shift intrinsics
13996 case Intrinsic::x86_sse2_pslli_w:
13997 case Intrinsic::x86_sse2_pslli_d:
13998 case Intrinsic::x86_sse2_pslli_q:
13999 case Intrinsic::x86_avx2_pslli_w:
14000 case Intrinsic::x86_avx2_pslli_d:
14001 case Intrinsic::x86_avx2_pslli_q:
14002 case Intrinsic::x86_sse2_psrli_w:
14003 case Intrinsic::x86_sse2_psrli_d:
14004 case Intrinsic::x86_sse2_psrli_q:
14005 case Intrinsic::x86_avx2_psrli_w:
14006 case Intrinsic::x86_avx2_psrli_d:
14007 case Intrinsic::x86_avx2_psrli_q:
14008 case Intrinsic::x86_sse2_psrai_w:
14009 case Intrinsic::x86_sse2_psrai_d:
14010 case Intrinsic::x86_avx2_psrai_w:
14011 case Intrinsic::x86_avx2_psrai_d: {
14014 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14015 case Intrinsic::x86_sse2_pslli_w:
14016 case Intrinsic::x86_sse2_pslli_d:
14017 case Intrinsic::x86_sse2_pslli_q:
14018 case Intrinsic::x86_avx2_pslli_w:
14019 case Intrinsic::x86_avx2_pslli_d:
14020 case Intrinsic::x86_avx2_pslli_q:
14021 Opcode = X86ISD::VSHLI;
14023 case Intrinsic::x86_sse2_psrli_w:
14024 case Intrinsic::x86_sse2_psrli_d:
14025 case Intrinsic::x86_sse2_psrli_q:
14026 case Intrinsic::x86_avx2_psrli_w:
14027 case Intrinsic::x86_avx2_psrli_d:
14028 case Intrinsic::x86_avx2_psrli_q:
14029 Opcode = X86ISD::VSRLI;
14031 case Intrinsic::x86_sse2_psrai_w:
14032 case Intrinsic::x86_sse2_psrai_d:
14033 case Intrinsic::x86_avx2_psrai_w:
14034 case Intrinsic::x86_avx2_psrai_d:
14035 Opcode = X86ISD::VSRAI;
14038 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
14039 Op.getOperand(1), Op.getOperand(2), DAG);
14042 case Intrinsic::x86_sse42_pcmpistria128:
14043 case Intrinsic::x86_sse42_pcmpestria128:
14044 case Intrinsic::x86_sse42_pcmpistric128:
14045 case Intrinsic::x86_sse42_pcmpestric128:
14046 case Intrinsic::x86_sse42_pcmpistrio128:
14047 case Intrinsic::x86_sse42_pcmpestrio128:
14048 case Intrinsic::x86_sse42_pcmpistris128:
14049 case Intrinsic::x86_sse42_pcmpestris128:
14050 case Intrinsic::x86_sse42_pcmpistriz128:
14051 case Intrinsic::x86_sse42_pcmpestriz128: {
14055 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14056 case Intrinsic::x86_sse42_pcmpistria128:
14057 Opcode = X86ISD::PCMPISTRI;
14058 X86CC = X86::COND_A;
14060 case Intrinsic::x86_sse42_pcmpestria128:
14061 Opcode = X86ISD::PCMPESTRI;
14062 X86CC = X86::COND_A;
14064 case Intrinsic::x86_sse42_pcmpistric128:
14065 Opcode = X86ISD::PCMPISTRI;
14066 X86CC = X86::COND_B;
14068 case Intrinsic::x86_sse42_pcmpestric128:
14069 Opcode = X86ISD::PCMPESTRI;
14070 X86CC = X86::COND_B;
14072 case Intrinsic::x86_sse42_pcmpistrio128:
14073 Opcode = X86ISD::PCMPISTRI;
14074 X86CC = X86::COND_O;
14076 case Intrinsic::x86_sse42_pcmpestrio128:
14077 Opcode = X86ISD::PCMPESTRI;
14078 X86CC = X86::COND_O;
14080 case Intrinsic::x86_sse42_pcmpistris128:
14081 Opcode = X86ISD::PCMPISTRI;
14082 X86CC = X86::COND_S;
14084 case Intrinsic::x86_sse42_pcmpestris128:
14085 Opcode = X86ISD::PCMPESTRI;
14086 X86CC = X86::COND_S;
14088 case Intrinsic::x86_sse42_pcmpistriz128:
14089 Opcode = X86ISD::PCMPISTRI;
14090 X86CC = X86::COND_E;
14092 case Intrinsic::x86_sse42_pcmpestriz128:
14093 Opcode = X86ISD::PCMPESTRI;
14094 X86CC = X86::COND_E;
14097 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14098 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14099 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
14100 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14101 DAG.getConstant(X86CC, MVT::i8),
14102 SDValue(PCMP.getNode(), 1));
14103 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14106 case Intrinsic::x86_sse42_pcmpistri128:
14107 case Intrinsic::x86_sse42_pcmpestri128: {
14109 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
14110 Opcode = X86ISD::PCMPISTRI;
14112 Opcode = X86ISD::PCMPESTRI;
14114 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14115 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14116 return DAG.getNode(Opcode, dl, VTs, NewOps);
14118 case Intrinsic::x86_fma_vfmadd_ps:
14119 case Intrinsic::x86_fma_vfmadd_pd:
14120 case Intrinsic::x86_fma_vfmsub_ps:
14121 case Intrinsic::x86_fma_vfmsub_pd:
14122 case Intrinsic::x86_fma_vfnmadd_ps:
14123 case Intrinsic::x86_fma_vfnmadd_pd:
14124 case Intrinsic::x86_fma_vfnmsub_ps:
14125 case Intrinsic::x86_fma_vfnmsub_pd:
14126 case Intrinsic::x86_fma_vfmaddsub_ps:
14127 case Intrinsic::x86_fma_vfmaddsub_pd:
14128 case Intrinsic::x86_fma_vfmsubadd_ps:
14129 case Intrinsic::x86_fma_vfmsubadd_pd:
14130 case Intrinsic::x86_fma_vfmadd_ps_256:
14131 case Intrinsic::x86_fma_vfmadd_pd_256:
14132 case Intrinsic::x86_fma_vfmsub_ps_256:
14133 case Intrinsic::x86_fma_vfmsub_pd_256:
14134 case Intrinsic::x86_fma_vfnmadd_ps_256:
14135 case Intrinsic::x86_fma_vfnmadd_pd_256:
14136 case Intrinsic::x86_fma_vfnmsub_ps_256:
14137 case Intrinsic::x86_fma_vfnmsub_pd_256:
14138 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14139 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14140 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14141 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14142 case Intrinsic::x86_fma_vfmadd_ps_512:
14143 case Intrinsic::x86_fma_vfmadd_pd_512:
14144 case Intrinsic::x86_fma_vfmsub_ps_512:
14145 case Intrinsic::x86_fma_vfmsub_pd_512:
14146 case Intrinsic::x86_fma_vfnmadd_ps_512:
14147 case Intrinsic::x86_fma_vfnmadd_pd_512:
14148 case Intrinsic::x86_fma_vfnmsub_ps_512:
14149 case Intrinsic::x86_fma_vfnmsub_pd_512:
14150 case Intrinsic::x86_fma_vfmaddsub_ps_512:
14151 case Intrinsic::x86_fma_vfmaddsub_pd_512:
14152 case Intrinsic::x86_fma_vfmsubadd_ps_512:
14153 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
14156 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14157 case Intrinsic::x86_fma_vfmadd_ps:
14158 case Intrinsic::x86_fma_vfmadd_pd:
14159 case Intrinsic::x86_fma_vfmadd_ps_256:
14160 case Intrinsic::x86_fma_vfmadd_pd_256:
14161 case Intrinsic::x86_fma_vfmadd_ps_512:
14162 case Intrinsic::x86_fma_vfmadd_pd_512:
14163 Opc = X86ISD::FMADD;
14165 case Intrinsic::x86_fma_vfmsub_ps:
14166 case Intrinsic::x86_fma_vfmsub_pd:
14167 case Intrinsic::x86_fma_vfmsub_ps_256:
14168 case Intrinsic::x86_fma_vfmsub_pd_256:
14169 case Intrinsic::x86_fma_vfmsub_ps_512:
14170 case Intrinsic::x86_fma_vfmsub_pd_512:
14171 Opc = X86ISD::FMSUB;
14173 case Intrinsic::x86_fma_vfnmadd_ps:
14174 case Intrinsic::x86_fma_vfnmadd_pd:
14175 case Intrinsic::x86_fma_vfnmadd_ps_256:
14176 case Intrinsic::x86_fma_vfnmadd_pd_256:
14177 case Intrinsic::x86_fma_vfnmadd_ps_512:
14178 case Intrinsic::x86_fma_vfnmadd_pd_512:
14179 Opc = X86ISD::FNMADD;
14181 case Intrinsic::x86_fma_vfnmsub_ps:
14182 case Intrinsic::x86_fma_vfnmsub_pd:
14183 case Intrinsic::x86_fma_vfnmsub_ps_256:
14184 case Intrinsic::x86_fma_vfnmsub_pd_256:
14185 case Intrinsic::x86_fma_vfnmsub_ps_512:
14186 case Intrinsic::x86_fma_vfnmsub_pd_512:
14187 Opc = X86ISD::FNMSUB;
14189 case Intrinsic::x86_fma_vfmaddsub_ps:
14190 case Intrinsic::x86_fma_vfmaddsub_pd:
14191 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14192 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14193 case Intrinsic::x86_fma_vfmaddsub_ps_512:
14194 case Intrinsic::x86_fma_vfmaddsub_pd_512:
14195 Opc = X86ISD::FMADDSUB;
14197 case Intrinsic::x86_fma_vfmsubadd_ps:
14198 case Intrinsic::x86_fma_vfmsubadd_pd:
14199 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14200 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14201 case Intrinsic::x86_fma_vfmsubadd_ps_512:
14202 case Intrinsic::x86_fma_vfmsubadd_pd_512:
14203 Opc = X86ISD::FMSUBADD;
14207 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
14208 Op.getOperand(2), Op.getOperand(3));
14213 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14214 SDValue Src, SDValue Mask, SDValue Base,
14215 SDValue Index, SDValue ScaleOp, SDValue Chain,
14216 const X86Subtarget * Subtarget) {
14218 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14219 assert(C && "Invalid scale type");
14220 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14221 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14222 Index.getSimpleValueType().getVectorNumElements());
14224 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14226 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14228 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14229 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
14230 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14231 SDValue Segment = DAG.getRegister(0, MVT::i32);
14232 if (Src.getOpcode() == ISD::UNDEF)
14233 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
14234 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14235 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14236 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
14237 return DAG.getMergeValues(RetOps, dl);
14240 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14241 SDValue Src, SDValue Mask, SDValue Base,
14242 SDValue Index, SDValue ScaleOp, SDValue Chain) {
14244 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14245 assert(C && "Invalid scale type");
14246 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14247 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14248 SDValue Segment = DAG.getRegister(0, MVT::i32);
14249 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14250 Index.getSimpleValueType().getVectorNumElements());
14252 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14254 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14256 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14257 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
14258 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
14259 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14260 return SDValue(Res, 1);
14263 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14264 SDValue Mask, SDValue Base, SDValue Index,
14265 SDValue ScaleOp, SDValue Chain) {
14267 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14268 assert(C && "Invalid scale type");
14269 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14270 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14271 SDValue Segment = DAG.getRegister(0, MVT::i32);
14273 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
14275 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14277 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14279 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14280 //SDVTList VTs = DAG.getVTList(MVT::Other);
14281 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14282 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
14283 return SDValue(Res, 0);
14286 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
14287 // read performance monitor counters (x86_rdpmc).
14288 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
14289 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14290 SmallVectorImpl<SDValue> &Results) {
14291 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14292 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14295 // The ECX register is used to select the index of the performance counter
14297 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
14299 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
14301 // Reads the content of a 64-bit performance counter and returns it in the
14302 // registers EDX:EAX.
14303 if (Subtarget->is64Bit()) {
14304 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14305 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14308 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14309 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14312 Chain = HI.getValue(1);
14314 if (Subtarget->is64Bit()) {
14315 // The EAX register is loaded with the low-order 32 bits. The EDX register
14316 // is loaded with the supported high-order bits of the counter.
14317 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14318 DAG.getConstant(32, MVT::i8));
14319 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14320 Results.push_back(Chain);
14324 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14325 SDValue Ops[] = { LO, HI };
14326 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14327 Results.push_back(Pair);
14328 Results.push_back(Chain);
14331 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
14332 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
14333 // also used to custom lower READCYCLECOUNTER nodes.
14334 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
14335 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14336 SmallVectorImpl<SDValue> &Results) {
14337 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14338 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
14341 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
14342 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
14343 // and the EAX register is loaded with the low-order 32 bits.
14344 if (Subtarget->is64Bit()) {
14345 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14346 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14349 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14350 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14353 SDValue Chain = HI.getValue(1);
14355 if (Opcode == X86ISD::RDTSCP_DAG) {
14356 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14358 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
14359 // the ECX register. Add 'ecx' explicitly to the chain.
14360 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
14362 // Explicitly store the content of ECX at the location passed in input
14363 // to the 'rdtscp' intrinsic.
14364 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
14365 MachinePointerInfo(), false, false, 0);
14368 if (Subtarget->is64Bit()) {
14369 // The EDX register is loaded with the high-order 32 bits of the MSR, and
14370 // the EAX register is loaded with the low-order 32 bits.
14371 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14372 DAG.getConstant(32, MVT::i8));
14373 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14374 Results.push_back(Chain);
14378 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14379 SDValue Ops[] = { LO, HI };
14380 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14381 Results.push_back(Pair);
14382 Results.push_back(Chain);
14385 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
14386 SelectionDAG &DAG) {
14387 SmallVector<SDValue, 2> Results;
14389 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
14391 return DAG.getMergeValues(Results, DL);
14394 enum IntrinsicType {
14395 GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST
14398 struct IntrinsicData {
14399 IntrinsicData(IntrinsicType IType, unsigned IOpc0, unsigned IOpc1)
14400 :Type(IType), Opc0(IOpc0), Opc1(IOpc1) {}
14401 IntrinsicType Type;
14406 std::map < unsigned, IntrinsicData> IntrMap;
14407 static void InitIntinsicsMap() {
14408 static bool Initialized = false;
14411 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
14412 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
14413 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
14414 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
14415 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpd_512,
14416 IntrinsicData(GATHER, X86::VGATHERQPDZrm, 0)));
14417 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpd_512,
14418 IntrinsicData(GATHER, X86::VGATHERDPDZrm, 0)));
14419 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dps_512,
14420 IntrinsicData(GATHER, X86::VGATHERDPSZrm, 0)));
14421 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpi_512,
14422 IntrinsicData(GATHER, X86::VPGATHERQDZrm, 0)));
14423 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpq_512,
14424 IntrinsicData(GATHER, X86::VPGATHERQQZrm, 0)));
14425 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpi_512,
14426 IntrinsicData(GATHER, X86::VPGATHERDDZrm, 0)));
14427 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpq_512,
14428 IntrinsicData(GATHER, X86::VPGATHERDQZrm, 0)));
14430 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qps_512,
14431 IntrinsicData(SCATTER, X86::VSCATTERQPSZmr, 0)));
14432 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpd_512,
14433 IntrinsicData(SCATTER, X86::VSCATTERQPDZmr, 0)));
14434 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpd_512,
14435 IntrinsicData(SCATTER, X86::VSCATTERDPDZmr, 0)));
14436 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dps_512,
14437 IntrinsicData(SCATTER, X86::VSCATTERDPSZmr, 0)));
14438 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpi_512,
14439 IntrinsicData(SCATTER, X86::VPSCATTERQDZmr, 0)));
14440 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpq_512,
14441 IntrinsicData(SCATTER, X86::VPSCATTERQQZmr, 0)));
14442 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpi_512,
14443 IntrinsicData(SCATTER, X86::VPSCATTERDDZmr, 0)));
14444 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpq_512,
14445 IntrinsicData(SCATTER, X86::VPSCATTERDQZmr, 0)));
14447 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qps_512,
14448 IntrinsicData(PREFETCH, X86::VGATHERPF0QPSm,
14449 X86::VGATHERPF1QPSm)));
14450 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qpd_512,
14451 IntrinsicData(PREFETCH, X86::VGATHERPF0QPDm,
14452 X86::VGATHERPF1QPDm)));
14453 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dpd_512,
14454 IntrinsicData(PREFETCH, X86::VGATHERPF0DPDm,
14455 X86::VGATHERPF1DPDm)));
14456 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dps_512,
14457 IntrinsicData(PREFETCH, X86::VGATHERPF0DPSm,
14458 X86::VGATHERPF1DPSm)));
14459 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qps_512,
14460 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPSm,
14461 X86::VSCATTERPF1QPSm)));
14462 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qpd_512,
14463 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPDm,
14464 X86::VSCATTERPF1QPDm)));
14465 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dpd_512,
14466 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPDm,
14467 X86::VSCATTERPF1DPDm)));
14468 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dps_512,
14469 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPSm,
14470 X86::VSCATTERPF1DPSm)));
14471 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_16,
14472 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14473 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_32,
14474 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14475 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_64,
14476 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14477 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_16,
14478 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14479 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_32,
14480 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14481 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_64,
14482 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14483 IntrMap.insert(std::make_pair(Intrinsic::x86_xtest,
14484 IntrinsicData(XTEST, X86ISD::XTEST, 0)));
14485 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtsc,
14486 IntrinsicData(RDTSC, X86ISD::RDTSC_DAG, 0)));
14487 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtscp,
14488 IntrinsicData(RDTSC, X86ISD::RDTSCP_DAG, 0)));
14489 IntrMap.insert(std::make_pair(Intrinsic::x86_rdpmc,
14490 IntrinsicData(RDPMC, X86ISD::RDPMC_DAG, 0)));
14491 Initialized = true;
14494 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14495 SelectionDAG &DAG) {
14496 InitIntinsicsMap();
14497 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
14498 std::map < unsigned, IntrinsicData>::const_iterator itr = IntrMap.find(IntNo);
14499 if (itr == IntrMap.end())
14503 IntrinsicData Intr = itr->second;
14504 switch(Intr.Type) {
14507 // Emit the node with the right value type.
14508 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
14509 SDValue Result = DAG.getNode(Intr.Opc0, dl, VTs, Op.getOperand(0));
14511 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
14512 // Otherwise return the value from Rand, which is always 0, casted to i32.
14513 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
14514 DAG.getConstant(1, Op->getValueType(1)),
14515 DAG.getConstant(X86::COND_B, MVT::i32),
14516 SDValue(Result.getNode(), 1) };
14517 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
14518 DAG.getVTList(Op->getValueType(1), MVT::Glue),
14521 // Return { result, isValid, chain }.
14522 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
14523 SDValue(Result.getNode(), 2));
14526 //gather(v1, mask, index, base, scale);
14527 SDValue Chain = Op.getOperand(0);
14528 SDValue Src = Op.getOperand(2);
14529 SDValue Base = Op.getOperand(3);
14530 SDValue Index = Op.getOperand(4);
14531 SDValue Mask = Op.getOperand(5);
14532 SDValue Scale = Op.getOperand(6);
14533 return getGatherNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
14537 //scatter(base, mask, index, v1, scale);
14538 SDValue Chain = Op.getOperand(0);
14539 SDValue Base = Op.getOperand(2);
14540 SDValue Mask = Op.getOperand(3);
14541 SDValue Index = Op.getOperand(4);
14542 SDValue Src = Op.getOperand(5);
14543 SDValue Scale = Op.getOperand(6);
14544 return getScatterNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
14547 SDValue Hint = Op.getOperand(6);
14549 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
14550 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
14551 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
14552 unsigned Opcode = (HintVal ? Intr.Opc1 : Intr.Opc0);
14553 SDValue Chain = Op.getOperand(0);
14554 SDValue Mask = Op.getOperand(2);
14555 SDValue Index = Op.getOperand(3);
14556 SDValue Base = Op.getOperand(4);
14557 SDValue Scale = Op.getOperand(5);
14558 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
14560 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
14562 SmallVector<SDValue, 2> Results;
14563 getReadTimeStampCounter(Op.getNode(), dl, Intr.Opc0, DAG, Subtarget, Results);
14564 return DAG.getMergeValues(Results, dl);
14566 // Read Performance Monitoring Counters.
14568 SmallVector<SDValue, 2> Results;
14569 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
14570 return DAG.getMergeValues(Results, dl);
14572 // XTEST intrinsics.
14574 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
14575 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
14576 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14577 DAG.getConstant(X86::COND_NE, MVT::i8),
14579 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
14580 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
14581 Ret, SDValue(InTrans.getNode(), 1));
14584 llvm_unreachable("Unknown Intrinsic Type");
14587 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
14588 SelectionDAG &DAG) const {
14589 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
14590 MFI->setReturnAddressIsTaken(true);
14592 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
14595 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14597 EVT PtrVT = getPointerTy();
14600 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
14601 const X86RegisterInfo *RegInfo =
14602 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14603 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
14604 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
14605 DAG.getNode(ISD::ADD, dl, PtrVT,
14606 FrameAddr, Offset),
14607 MachinePointerInfo(), false, false, false, 0);
14610 // Just load the return address.
14611 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
14612 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
14613 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
14616 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
14617 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
14618 MFI->setFrameAddressIsTaken(true);
14620 EVT VT = Op.getValueType();
14621 SDLoc dl(Op); // FIXME probably not meaningful
14622 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14623 const X86RegisterInfo *RegInfo =
14624 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14625 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
14626 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
14627 (FrameReg == X86::EBP && VT == MVT::i32)) &&
14628 "Invalid Frame Register!");
14629 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
14631 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
14632 MachinePointerInfo(),
14633 false, false, false, 0);
14637 // FIXME? Maybe this could be a TableGen attribute on some registers and
14638 // this table could be generated automatically from RegInfo.
14639 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
14641 unsigned Reg = StringSwitch<unsigned>(RegName)
14642 .Case("esp", X86::ESP)
14643 .Case("rsp", X86::RSP)
14647 report_fatal_error("Invalid register name global variable");
14650 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
14651 SelectionDAG &DAG) const {
14652 const X86RegisterInfo *RegInfo =
14653 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14654 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
14657 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
14658 SDValue Chain = Op.getOperand(0);
14659 SDValue Offset = Op.getOperand(1);
14660 SDValue Handler = Op.getOperand(2);
14663 EVT PtrVT = getPointerTy();
14664 const X86RegisterInfo *RegInfo =
14665 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14666 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
14667 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
14668 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
14669 "Invalid Frame Register!");
14670 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
14671 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
14673 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
14674 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
14675 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
14676 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
14678 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
14680 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
14681 DAG.getRegister(StoreAddrReg, PtrVT));
14684 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
14685 SelectionDAG &DAG) const {
14687 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
14688 DAG.getVTList(MVT::i32, MVT::Other),
14689 Op.getOperand(0), Op.getOperand(1));
14692 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
14693 SelectionDAG &DAG) const {
14695 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
14696 Op.getOperand(0), Op.getOperand(1));
14699 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
14700 return Op.getOperand(0);
14703 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
14704 SelectionDAG &DAG) const {
14705 SDValue Root = Op.getOperand(0);
14706 SDValue Trmp = Op.getOperand(1); // trampoline
14707 SDValue FPtr = Op.getOperand(2); // nested function
14708 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
14711 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14712 const TargetRegisterInfo* TRI = DAG.getTarget().getRegisterInfo();
14714 if (Subtarget->is64Bit()) {
14715 SDValue OutChains[6];
14717 // Large code-model.
14718 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
14719 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
14721 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
14722 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
14724 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
14726 // Load the pointer to the nested function into R11.
14727 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
14728 SDValue Addr = Trmp;
14729 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
14730 Addr, MachinePointerInfo(TrmpAddr),
14733 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14734 DAG.getConstant(2, MVT::i64));
14735 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
14736 MachinePointerInfo(TrmpAddr, 2),
14739 // Load the 'nest' parameter value into R10.
14740 // R10 is specified in X86CallingConv.td
14741 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
14742 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14743 DAG.getConstant(10, MVT::i64));
14744 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
14745 Addr, MachinePointerInfo(TrmpAddr, 10),
14748 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14749 DAG.getConstant(12, MVT::i64));
14750 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
14751 MachinePointerInfo(TrmpAddr, 12),
14754 // Jump to the nested function.
14755 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
14756 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14757 DAG.getConstant(20, MVT::i64));
14758 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
14759 Addr, MachinePointerInfo(TrmpAddr, 20),
14762 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
14763 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14764 DAG.getConstant(22, MVT::i64));
14765 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
14766 MachinePointerInfo(TrmpAddr, 22),
14769 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
14771 const Function *Func =
14772 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
14773 CallingConv::ID CC = Func->getCallingConv();
14778 llvm_unreachable("Unsupported calling convention");
14779 case CallingConv::C:
14780 case CallingConv::X86_StdCall: {
14781 // Pass 'nest' parameter in ECX.
14782 // Must be kept in sync with X86CallingConv.td
14783 NestReg = X86::ECX;
14785 // Check that ECX wasn't needed by an 'inreg' parameter.
14786 FunctionType *FTy = Func->getFunctionType();
14787 const AttributeSet &Attrs = Func->getAttributes();
14789 if (!Attrs.isEmpty() && !Func->isVarArg()) {
14790 unsigned InRegCount = 0;
14793 for (FunctionType::param_iterator I = FTy->param_begin(),
14794 E = FTy->param_end(); I != E; ++I, ++Idx)
14795 if (Attrs.hasAttribute(Idx, Attribute::InReg))
14796 // FIXME: should only count parameters that are lowered to integers.
14797 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
14799 if (InRegCount > 2) {
14800 report_fatal_error("Nest register in use - reduce number of inreg"
14806 case CallingConv::X86_FastCall:
14807 case CallingConv::X86_ThisCall:
14808 case CallingConv::Fast:
14809 // Pass 'nest' parameter in EAX.
14810 // Must be kept in sync with X86CallingConv.td
14811 NestReg = X86::EAX;
14815 SDValue OutChains[4];
14816 SDValue Addr, Disp;
14818 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14819 DAG.getConstant(10, MVT::i32));
14820 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
14822 // This is storing the opcode for MOV32ri.
14823 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
14824 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
14825 OutChains[0] = DAG.getStore(Root, dl,
14826 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
14827 Trmp, MachinePointerInfo(TrmpAddr),
14830 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14831 DAG.getConstant(1, MVT::i32));
14832 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
14833 MachinePointerInfo(TrmpAddr, 1),
14836 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
14837 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14838 DAG.getConstant(5, MVT::i32));
14839 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
14840 MachinePointerInfo(TrmpAddr, 5),
14843 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14844 DAG.getConstant(6, MVT::i32));
14845 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
14846 MachinePointerInfo(TrmpAddr, 6),
14849 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
14853 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
14854 SelectionDAG &DAG) const {
14856 The rounding mode is in bits 11:10 of FPSR, and has the following
14858 00 Round to nearest
14863 FLT_ROUNDS, on the other hand, expects the following:
14870 To perform the conversion, we do:
14871 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
14874 MachineFunction &MF = DAG.getMachineFunction();
14875 const TargetMachine &TM = MF.getTarget();
14876 const TargetFrameLowering &TFI = *TM.getFrameLowering();
14877 unsigned StackAlignment = TFI.getStackAlignment();
14878 MVT VT = Op.getSimpleValueType();
14881 // Save FP Control Word to stack slot
14882 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
14883 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14885 MachineMemOperand *MMO =
14886 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14887 MachineMemOperand::MOStore, 2, 2);
14889 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
14890 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
14891 DAG.getVTList(MVT::Other),
14892 Ops, MVT::i16, MMO);
14894 // Load FP Control Word from stack slot
14895 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
14896 MachinePointerInfo(), false, false, false, 0);
14898 // Transform as necessary
14900 DAG.getNode(ISD::SRL, DL, MVT::i16,
14901 DAG.getNode(ISD::AND, DL, MVT::i16,
14902 CWD, DAG.getConstant(0x800, MVT::i16)),
14903 DAG.getConstant(11, MVT::i8));
14905 DAG.getNode(ISD::SRL, DL, MVT::i16,
14906 DAG.getNode(ISD::AND, DL, MVT::i16,
14907 CWD, DAG.getConstant(0x400, MVT::i16)),
14908 DAG.getConstant(9, MVT::i8));
14911 DAG.getNode(ISD::AND, DL, MVT::i16,
14912 DAG.getNode(ISD::ADD, DL, MVT::i16,
14913 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
14914 DAG.getConstant(1, MVT::i16)),
14915 DAG.getConstant(3, MVT::i16));
14917 return DAG.getNode((VT.getSizeInBits() < 16 ?
14918 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
14921 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
14922 MVT VT = Op.getSimpleValueType();
14924 unsigned NumBits = VT.getSizeInBits();
14927 Op = Op.getOperand(0);
14928 if (VT == MVT::i8) {
14929 // Zero extend to i32 since there is not an i8 bsr.
14931 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
14934 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
14935 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
14936 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
14938 // If src is zero (i.e. bsr sets ZF), returns NumBits.
14941 DAG.getConstant(NumBits+NumBits-1, OpVT),
14942 DAG.getConstant(X86::COND_E, MVT::i8),
14945 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
14947 // Finally xor with NumBits-1.
14948 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
14951 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
14955 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
14956 MVT VT = Op.getSimpleValueType();
14958 unsigned NumBits = VT.getSizeInBits();
14961 Op = Op.getOperand(0);
14962 if (VT == MVT::i8) {
14963 // Zero extend to i32 since there is not an i8 bsr.
14965 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
14968 // Issue a bsr (scan bits in reverse).
14969 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
14970 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
14972 // And xor with NumBits-1.
14973 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
14976 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
14980 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
14981 MVT VT = Op.getSimpleValueType();
14982 unsigned NumBits = VT.getSizeInBits();
14984 Op = Op.getOperand(0);
14986 // Issue a bsf (scan bits forward) which also sets EFLAGS.
14987 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
14988 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
14990 // If src is zero (i.e. bsf sets ZF), returns NumBits.
14993 DAG.getConstant(NumBits, VT),
14994 DAG.getConstant(X86::COND_E, MVT::i8),
14997 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
15000 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
15001 // ones, and then concatenate the result back.
15002 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
15003 MVT VT = Op.getSimpleValueType();
15005 assert(VT.is256BitVector() && VT.isInteger() &&
15006 "Unsupported value type for operation");
15008 unsigned NumElems = VT.getVectorNumElements();
15011 // Extract the LHS vectors
15012 SDValue LHS = Op.getOperand(0);
15013 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15014 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15016 // Extract the RHS vectors
15017 SDValue RHS = Op.getOperand(1);
15018 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15019 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15021 MVT EltVT = VT.getVectorElementType();
15022 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15024 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15025 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
15026 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
15029 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
15030 assert(Op.getSimpleValueType().is256BitVector() &&
15031 Op.getSimpleValueType().isInteger() &&
15032 "Only handle AVX 256-bit vector integer operation");
15033 return Lower256IntArith(Op, DAG);
15036 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
15037 assert(Op.getSimpleValueType().is256BitVector() &&
15038 Op.getSimpleValueType().isInteger() &&
15039 "Only handle AVX 256-bit vector integer operation");
15040 return Lower256IntArith(Op, DAG);
15043 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
15044 SelectionDAG &DAG) {
15046 MVT VT = Op.getSimpleValueType();
15048 // Decompose 256-bit ops into smaller 128-bit ops.
15049 if (VT.is256BitVector() && !Subtarget->hasInt256())
15050 return Lower256IntArith(Op, DAG);
15052 SDValue A = Op.getOperand(0);
15053 SDValue B = Op.getOperand(1);
15055 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15056 if (VT == MVT::v4i32) {
15057 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
15058 "Should not custom lower when pmuldq is available!");
15060 // Extract the odd parts.
15061 static const int UnpackMask[] = { 1, -1, 3, -1 };
15062 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
15063 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
15065 // Multiply the even parts.
15066 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15067 // Now multiply odd parts.
15068 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15070 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
15071 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
15073 // Merge the two vectors back together with a shuffle. This expands into 2
15075 static const int ShufMask[] = { 0, 4, 2, 6 };
15076 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
15079 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15080 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15082 // Ahi = psrlqi(a, 32);
15083 // Bhi = psrlqi(b, 32);
15085 // AloBlo = pmuludq(a, b);
15086 // AloBhi = pmuludq(a, Bhi);
15087 // AhiBlo = pmuludq(Ahi, b);
15089 // AloBhi = psllqi(AloBhi, 32);
15090 // AhiBlo = psllqi(AhiBlo, 32);
15091 // return AloBlo + AloBhi + AhiBlo;
15093 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
15094 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
15096 // Bit cast to 32-bit vectors for MULUDQ
15097 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15098 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15099 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
15100 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
15101 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
15102 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
15104 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
15105 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
15106 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
15108 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
15109 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
15111 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
15112 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
15115 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
15116 assert(Subtarget->isTargetWin64() && "Unexpected target");
15117 EVT VT = Op.getValueType();
15118 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
15119 "Unexpected return type for lowering");
15123 switch (Op->getOpcode()) {
15124 default: llvm_unreachable("Unexpected request for libcall!");
15125 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
15126 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
15127 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
15128 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
15129 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
15130 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
15134 SDValue InChain = DAG.getEntryNode();
15136 TargetLowering::ArgListTy Args;
15137 TargetLowering::ArgListEntry Entry;
15138 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
15139 EVT ArgVT = Op->getOperand(i).getValueType();
15140 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
15141 "Unexpected argument type for lowering");
15142 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
15143 Entry.Node = StackPtr;
15144 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
15146 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15147 Entry.Ty = PointerType::get(ArgTy,0);
15148 Entry.isSExt = false;
15149 Entry.isZExt = false;
15150 Args.push_back(Entry);
15153 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
15156 TargetLowering::CallLoweringInfo CLI(DAG);
15157 CLI.setDebugLoc(dl).setChain(InChain)
15158 .setCallee(getLibcallCallingConv(LC),
15159 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
15160 Callee, std::move(Args), 0)
15161 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
15163 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
15164 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
15167 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
15168 SelectionDAG &DAG) {
15169 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
15170 EVT VT = Op0.getValueType();
15173 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
15174 (VT == MVT::v8i32 && Subtarget->hasInt256()));
15176 // PMULxD operations multiply each even value (starting at 0) of LHS with
15177 // the related value of RHS and produce a widen result.
15178 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
15179 // => <2 x i64> <ae|cg>
15181 // In other word, to have all the results, we need to perform two PMULxD:
15182 // 1. one with the even values.
15183 // 2. one with the odd values.
15184 // To achieve #2, with need to place the odd values at an even position.
15186 // Place the odd value at an even position (basically, shift all values 1
15187 // step to the left):
15188 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
15189 // <a|b|c|d> => <b|undef|d|undef>
15190 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
15191 // <e|f|g|h> => <f|undef|h|undef>
15192 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
15194 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
15196 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
15197 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
15199 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
15200 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
15201 // => <2 x i64> <ae|cg>
15202 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
15203 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
15204 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
15205 // => <2 x i64> <bf|dh>
15206 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
15207 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
15209 // Shuffle it back into the right order.
15210 // The internal representation is big endian.
15211 // In other words, a i64 bitcasted to 2 x i32 has its high part at index 0
15212 // and its low part at index 1.
15213 // Moreover, we have: Mul1 = <ae|cg> ; Mul2 = <bf|dh>
15214 // Vector index 0 1 ; 2 3
15215 // We want <ae|bf|cg|dh>
15216 // Vector index 0 2 1 3
15217 // Since each element is seen as 2 x i32, we get:
15218 // high_mask[i] = 2 x vector_index[i]
15219 // low_mask[i] = 2 x vector_index[i] + 1
15220 // where vector_index = {0, Size/2, 1, Size/2 + 1, ...,
15221 // Size/2 - 1, Size/2 + Size/2 - 1}
15222 // where Size is the number of element of the final vector.
15223 SDValue Highs, Lows;
15224 if (VT == MVT::v8i32) {
15225 const int HighMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
15226 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15227 const int LowMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
15228 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15230 const int HighMask[] = {0, 4, 2, 6};
15231 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15232 const int LowMask[] = {1, 5, 3, 7};
15233 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15236 // If we have a signed multiply but no PMULDQ fix up the high parts of a
15237 // unsigned multiply.
15238 if (IsSigned && !Subtarget->hasSSE41()) {
15240 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
15241 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
15242 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
15243 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
15244 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
15246 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
15247 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
15250 // The low part of a MUL_LOHI is supposed to be the first value and the
15251 // high part the second value.
15252 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getValueType(), Lows, Highs);
15255 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
15256 const X86Subtarget *Subtarget) {
15257 MVT VT = Op.getSimpleValueType();
15259 SDValue R = Op.getOperand(0);
15260 SDValue Amt = Op.getOperand(1);
15262 // Optimize shl/srl/sra with constant shift amount.
15263 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
15264 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
15265 uint64_t ShiftAmt = ShiftConst->getZExtValue();
15267 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
15268 (Subtarget->hasInt256() &&
15269 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15270 (Subtarget->hasAVX512() &&
15271 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15272 if (Op.getOpcode() == ISD::SHL)
15273 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15275 if (Op.getOpcode() == ISD::SRL)
15276 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15278 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
15279 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15283 if (VT == MVT::v16i8) {
15284 if (Op.getOpcode() == ISD::SHL) {
15285 // Make a large shift.
15286 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
15287 MVT::v8i16, R, ShiftAmt,
15289 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15290 // Zero out the rightmost bits.
15291 SmallVector<SDValue, 16> V(16,
15292 DAG.getConstant(uint8_t(-1U << ShiftAmt),
15294 return DAG.getNode(ISD::AND, dl, VT, SHL,
15295 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15297 if (Op.getOpcode() == ISD::SRL) {
15298 // Make a large shift.
15299 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
15300 MVT::v8i16, R, ShiftAmt,
15302 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15303 // Zero out the leftmost bits.
15304 SmallVector<SDValue, 16> V(16,
15305 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
15307 return DAG.getNode(ISD::AND, dl, VT, SRL,
15308 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15310 if (Op.getOpcode() == ISD::SRA) {
15311 if (ShiftAmt == 7) {
15312 // R s>> 7 === R s< 0
15313 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15314 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15317 // R s>> a === ((R u>> a) ^ m) - m
15318 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15319 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
15321 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15322 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15323 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15326 llvm_unreachable("Unknown shift opcode.");
15329 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
15330 if (Op.getOpcode() == ISD::SHL) {
15331 // Make a large shift.
15332 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
15333 MVT::v16i16, R, ShiftAmt,
15335 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15336 // Zero out the rightmost bits.
15337 SmallVector<SDValue, 32> V(32,
15338 DAG.getConstant(uint8_t(-1U << ShiftAmt),
15340 return DAG.getNode(ISD::AND, dl, VT, SHL,
15341 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15343 if (Op.getOpcode() == ISD::SRL) {
15344 // Make a large shift.
15345 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
15346 MVT::v16i16, R, ShiftAmt,
15348 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15349 // Zero out the leftmost bits.
15350 SmallVector<SDValue, 32> V(32,
15351 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
15353 return DAG.getNode(ISD::AND, dl, VT, SRL,
15354 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15356 if (Op.getOpcode() == ISD::SRA) {
15357 if (ShiftAmt == 7) {
15358 // R s>> 7 === R s< 0
15359 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15360 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15363 // R s>> a === ((R u>> a) ^ m) - m
15364 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15365 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
15367 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15368 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15369 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15372 llvm_unreachable("Unknown shift opcode.");
15377 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
15378 if (!Subtarget->is64Bit() &&
15379 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
15380 Amt.getOpcode() == ISD::BITCAST &&
15381 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15382 Amt = Amt.getOperand(0);
15383 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
15384 VT.getVectorNumElements();
15385 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
15386 uint64_t ShiftAmt = 0;
15387 for (unsigned i = 0; i != Ratio; ++i) {
15388 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
15392 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
15394 // Check remaining shift amounts.
15395 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
15396 uint64_t ShAmt = 0;
15397 for (unsigned j = 0; j != Ratio; ++j) {
15398 ConstantSDNode *C =
15399 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
15403 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
15405 if (ShAmt != ShiftAmt)
15408 switch (Op.getOpcode()) {
15410 llvm_unreachable("Unknown shift opcode!");
15412 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15415 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15418 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15426 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
15427 const X86Subtarget* Subtarget) {
15428 MVT VT = Op.getSimpleValueType();
15430 SDValue R = Op.getOperand(0);
15431 SDValue Amt = Op.getOperand(1);
15433 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
15434 VT == MVT::v4i32 || VT == MVT::v8i16 ||
15435 (Subtarget->hasInt256() &&
15436 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
15437 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15438 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15440 EVT EltVT = VT.getVectorElementType();
15442 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
15443 unsigned NumElts = VT.getVectorNumElements();
15445 for (i = 0; i != NumElts; ++i) {
15446 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
15450 for (j = i; j != NumElts; ++j) {
15451 SDValue Arg = Amt.getOperand(j);
15452 if (Arg.getOpcode() == ISD::UNDEF) continue;
15453 if (Arg != Amt.getOperand(i))
15456 if (i != NumElts && j == NumElts)
15457 BaseShAmt = Amt.getOperand(i);
15459 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
15460 Amt = Amt.getOperand(0);
15461 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
15462 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
15463 SDValue InVec = Amt.getOperand(0);
15464 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15465 unsigned NumElts = InVec.getValueType().getVectorNumElements();
15467 for (; i != NumElts; ++i) {
15468 SDValue Arg = InVec.getOperand(i);
15469 if (Arg.getOpcode() == ISD::UNDEF) continue;
15473 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
15474 if (ConstantSDNode *C =
15475 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
15476 unsigned SplatIdx =
15477 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
15478 if (C->getZExtValue() == SplatIdx)
15479 BaseShAmt = InVec.getOperand(1);
15482 if (!BaseShAmt.getNode())
15483 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
15484 DAG.getIntPtrConstant(0));
15488 if (BaseShAmt.getNode()) {
15489 if (EltVT.bitsGT(MVT::i32))
15490 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
15491 else if (EltVT.bitsLT(MVT::i32))
15492 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
15494 switch (Op.getOpcode()) {
15496 llvm_unreachable("Unknown shift opcode!");
15498 switch (VT.SimpleTy) {
15499 default: return SDValue();
15508 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
15511 switch (VT.SimpleTy) {
15512 default: return SDValue();
15519 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
15522 switch (VT.SimpleTy) {
15523 default: return SDValue();
15532 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
15538 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
15539 if (!Subtarget->is64Bit() &&
15540 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
15541 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
15542 Amt.getOpcode() == ISD::BITCAST &&
15543 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15544 Amt = Amt.getOperand(0);
15545 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
15546 VT.getVectorNumElements();
15547 std::vector<SDValue> Vals(Ratio);
15548 for (unsigned i = 0; i != Ratio; ++i)
15549 Vals[i] = Amt.getOperand(i);
15550 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
15551 for (unsigned j = 0; j != Ratio; ++j)
15552 if (Vals[j] != Amt.getOperand(i + j))
15555 switch (Op.getOpcode()) {
15557 llvm_unreachable("Unknown shift opcode!");
15559 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
15561 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
15563 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
15570 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
15571 SelectionDAG &DAG) {
15572 MVT VT = Op.getSimpleValueType();
15574 SDValue R = Op.getOperand(0);
15575 SDValue Amt = Op.getOperand(1);
15578 assert(VT.isVector() && "Custom lowering only for vector shifts!");
15579 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
15581 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
15585 V = LowerScalarVariableShift(Op, DAG, Subtarget);
15589 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
15591 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
15592 if (Subtarget->hasInt256()) {
15593 if (Op.getOpcode() == ISD::SRL &&
15594 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
15595 VT == MVT::v4i64 || VT == MVT::v8i32))
15597 if (Op.getOpcode() == ISD::SHL &&
15598 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
15599 VT == MVT::v4i64 || VT == MVT::v8i32))
15601 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
15605 // If possible, lower this packed shift into a vector multiply instead of
15606 // expanding it into a sequence of scalar shifts.
15607 // Do this only if the vector shift count is a constant build_vector.
15608 if (Op.getOpcode() == ISD::SHL &&
15609 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
15610 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
15611 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
15612 SmallVector<SDValue, 8> Elts;
15613 EVT SVT = VT.getScalarType();
15614 unsigned SVTBits = SVT.getSizeInBits();
15615 const APInt &One = APInt(SVTBits, 1);
15616 unsigned NumElems = VT.getVectorNumElements();
15618 for (unsigned i=0; i !=NumElems; ++i) {
15619 SDValue Op = Amt->getOperand(i);
15620 if (Op->getOpcode() == ISD::UNDEF) {
15621 Elts.push_back(Op);
15625 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
15626 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
15627 uint64_t ShAmt = C.getZExtValue();
15628 if (ShAmt >= SVTBits) {
15629 Elts.push_back(DAG.getUNDEF(SVT));
15632 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
15634 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15635 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
15638 // Lower SHL with variable shift amount.
15639 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
15640 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
15642 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
15643 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
15644 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
15645 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
15648 // If possible, lower this shift as a sequence of two shifts by
15649 // constant plus a MOVSS/MOVSD instead of scalarizing it.
15651 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
15653 // Could be rewritten as:
15654 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
15656 // The advantage is that the two shifts from the example would be
15657 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
15658 // the vector shift into four scalar shifts plus four pairs of vector
15660 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
15661 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
15662 unsigned TargetOpcode = X86ISD::MOVSS;
15663 bool CanBeSimplified;
15664 // The splat value for the first packed shift (the 'X' from the example).
15665 SDValue Amt1 = Amt->getOperand(0);
15666 // The splat value for the second packed shift (the 'Y' from the example).
15667 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
15668 Amt->getOperand(2);
15670 // See if it is possible to replace this node with a sequence of
15671 // two shifts followed by a MOVSS/MOVSD
15672 if (VT == MVT::v4i32) {
15673 // Check if it is legal to use a MOVSS.
15674 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
15675 Amt2 == Amt->getOperand(3);
15676 if (!CanBeSimplified) {
15677 // Otherwise, check if we can still simplify this node using a MOVSD.
15678 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
15679 Amt->getOperand(2) == Amt->getOperand(3);
15680 TargetOpcode = X86ISD::MOVSD;
15681 Amt2 = Amt->getOperand(2);
15684 // Do similar checks for the case where the machine value type
15686 CanBeSimplified = Amt1 == Amt->getOperand(1);
15687 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
15688 CanBeSimplified = Amt2 == Amt->getOperand(i);
15690 if (!CanBeSimplified) {
15691 TargetOpcode = X86ISD::MOVSD;
15692 CanBeSimplified = true;
15693 Amt2 = Amt->getOperand(4);
15694 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
15695 CanBeSimplified = Amt1 == Amt->getOperand(i);
15696 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
15697 CanBeSimplified = Amt2 == Amt->getOperand(j);
15701 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
15702 isa<ConstantSDNode>(Amt2)) {
15703 // Replace this node with two shifts followed by a MOVSS/MOVSD.
15704 EVT CastVT = MVT::v4i32;
15706 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
15707 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
15709 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
15710 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
15711 if (TargetOpcode == X86ISD::MOVSD)
15712 CastVT = MVT::v2i64;
15713 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
15714 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
15715 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
15717 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15721 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
15722 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
15725 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
15726 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
15728 // Turn 'a' into a mask suitable for VSELECT
15729 SDValue VSelM = DAG.getConstant(0x80, VT);
15730 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
15731 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
15733 SDValue CM1 = DAG.getConstant(0x0f, VT);
15734 SDValue CM2 = DAG.getConstant(0x3f, VT);
15736 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
15737 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
15738 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
15739 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
15740 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
15743 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
15744 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
15745 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
15747 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
15748 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
15749 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
15750 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
15751 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
15754 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
15755 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
15756 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
15758 // return VSELECT(r, r+r, a);
15759 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
15760 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
15764 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
15765 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
15766 // solution better.
15767 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
15768 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
15770 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
15771 R = DAG.getNode(ExtOpc, dl, NewVT, R);
15772 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
15773 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15774 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
15777 // Decompose 256-bit shifts into smaller 128-bit shifts.
15778 if (VT.is256BitVector()) {
15779 unsigned NumElems = VT.getVectorNumElements();
15780 MVT EltVT = VT.getVectorElementType();
15781 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15783 // Extract the two vectors
15784 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
15785 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
15787 // Recreate the shift amount vectors
15788 SDValue Amt1, Amt2;
15789 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
15790 // Constant shift amount
15791 SmallVector<SDValue, 4> Amt1Csts;
15792 SmallVector<SDValue, 4> Amt2Csts;
15793 for (unsigned i = 0; i != NumElems/2; ++i)
15794 Amt1Csts.push_back(Amt->getOperand(i));
15795 for (unsigned i = NumElems/2; i != NumElems; ++i)
15796 Amt2Csts.push_back(Amt->getOperand(i));
15798 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
15799 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
15801 // Variable shift amount
15802 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
15803 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
15806 // Issue new vector shifts for the smaller types
15807 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
15808 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
15810 // Concatenate the result back
15811 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
15817 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
15818 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
15819 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
15820 // looks for this combo and may remove the "setcc" instruction if the "setcc"
15821 // has only one use.
15822 SDNode *N = Op.getNode();
15823 SDValue LHS = N->getOperand(0);
15824 SDValue RHS = N->getOperand(1);
15825 unsigned BaseOp = 0;
15828 switch (Op.getOpcode()) {
15829 default: llvm_unreachable("Unknown ovf instruction!");
15831 // A subtract of one will be selected as a INC. Note that INC doesn't
15832 // set CF, so we can't do this for UADDO.
15833 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15835 BaseOp = X86ISD::INC;
15836 Cond = X86::COND_O;
15839 BaseOp = X86ISD::ADD;
15840 Cond = X86::COND_O;
15843 BaseOp = X86ISD::ADD;
15844 Cond = X86::COND_B;
15847 // A subtract of one will be selected as a DEC. Note that DEC doesn't
15848 // set CF, so we can't do this for USUBO.
15849 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15851 BaseOp = X86ISD::DEC;
15852 Cond = X86::COND_O;
15855 BaseOp = X86ISD::SUB;
15856 Cond = X86::COND_O;
15859 BaseOp = X86ISD::SUB;
15860 Cond = X86::COND_B;
15863 BaseOp = X86ISD::SMUL;
15864 Cond = X86::COND_O;
15866 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
15867 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
15869 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
15872 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15873 DAG.getConstant(X86::COND_O, MVT::i32),
15874 SDValue(Sum.getNode(), 2));
15876 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
15880 // Also sets EFLAGS.
15881 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
15882 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
15885 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
15886 DAG.getConstant(Cond, MVT::i32),
15887 SDValue(Sum.getNode(), 1));
15889 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
15892 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
15893 SelectionDAG &DAG) const {
15895 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
15896 MVT VT = Op.getSimpleValueType();
15898 if (!Subtarget->hasSSE2() || !VT.isVector())
15901 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
15902 ExtraVT.getScalarType().getSizeInBits();
15904 switch (VT.SimpleTy) {
15905 default: return SDValue();
15908 if (!Subtarget->hasFp256())
15910 if (!Subtarget->hasInt256()) {
15911 // needs to be split
15912 unsigned NumElems = VT.getVectorNumElements();
15914 // Extract the LHS vectors
15915 SDValue LHS = Op.getOperand(0);
15916 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15917 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15919 MVT EltVT = VT.getVectorElementType();
15920 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15922 EVT ExtraEltVT = ExtraVT.getVectorElementType();
15923 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
15924 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
15926 SDValue Extra = DAG.getValueType(ExtraVT);
15928 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
15929 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
15931 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
15936 SDValue Op0 = Op.getOperand(0);
15937 SDValue Op00 = Op0.getOperand(0);
15939 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
15940 if (Op0.getOpcode() == ISD::BITCAST &&
15941 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
15942 // (sext (vzext x)) -> (vsext x)
15943 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
15944 if (Tmp1.getNode()) {
15945 EVT ExtraEltVT = ExtraVT.getVectorElementType();
15946 // This folding is only valid when the in-reg type is a vector of i8,
15948 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
15949 ExtraEltVT == MVT::i32) {
15950 SDValue Tmp1Op0 = Tmp1.getOperand(0);
15951 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
15952 "This optimization is invalid without a VZEXT.");
15953 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
15959 // If the above didn't work, then just use Shift-Left + Shift-Right.
15960 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
15962 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
15968 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
15969 SelectionDAG &DAG) {
15971 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
15972 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
15973 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
15974 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
15976 // The only fence that needs an instruction is a sequentially-consistent
15977 // cross-thread fence.
15978 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
15979 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
15980 // no-sse2). There isn't any reason to disable it if the target processor
15982 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
15983 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
15985 SDValue Chain = Op.getOperand(0);
15986 SDValue Zero = DAG.getConstant(0, MVT::i32);
15988 DAG.getRegister(X86::ESP, MVT::i32), // Base
15989 DAG.getTargetConstant(1, MVT::i8), // Scale
15990 DAG.getRegister(0, MVT::i32), // Index
15991 DAG.getTargetConstant(0, MVT::i32), // Disp
15992 DAG.getRegister(0, MVT::i32), // Segment.
15996 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
15997 return SDValue(Res, 0);
16000 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
16001 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
16004 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
16005 SelectionDAG &DAG) {
16006 MVT T = Op.getSimpleValueType();
16010 switch(T.SimpleTy) {
16011 default: llvm_unreachable("Invalid value type!");
16012 case MVT::i8: Reg = X86::AL; size = 1; break;
16013 case MVT::i16: Reg = X86::AX; size = 2; break;
16014 case MVT::i32: Reg = X86::EAX; size = 4; break;
16016 assert(Subtarget->is64Bit() && "Node not type legal!");
16017 Reg = X86::RAX; size = 8;
16020 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
16021 Op.getOperand(2), SDValue());
16022 SDValue Ops[] = { cpIn.getValue(0),
16025 DAG.getTargetConstant(size, MVT::i8),
16026 cpIn.getValue(1) };
16027 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16028 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
16029 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
16033 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
16034 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
16035 MVT::i32, cpOut.getValue(2));
16036 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
16037 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16039 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
16040 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
16041 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
16045 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
16046 SelectionDAG &DAG) {
16047 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
16048 MVT DstVT = Op.getSimpleValueType();
16050 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
16051 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16052 if (DstVT != MVT::f64)
16053 // This conversion needs to be expanded.
16056 SDValue InVec = Op->getOperand(0);
16058 unsigned NumElts = SrcVT.getVectorNumElements();
16059 EVT SVT = SrcVT.getVectorElementType();
16061 // Widen the vector in input in the case of MVT::v2i32.
16062 // Example: from MVT::v2i32 to MVT::v4i32.
16063 SmallVector<SDValue, 16> Elts;
16064 for (unsigned i = 0, e = NumElts; i != e; ++i)
16065 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
16066 DAG.getIntPtrConstant(i)));
16068 // Explicitly mark the extra elements as Undef.
16069 SDValue Undef = DAG.getUNDEF(SVT);
16070 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
16071 Elts.push_back(Undef);
16073 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16074 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
16075 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
16076 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
16077 DAG.getIntPtrConstant(0));
16080 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
16081 Subtarget->hasMMX() && "Unexpected custom BITCAST");
16082 assert((DstVT == MVT::i64 ||
16083 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
16084 "Unexpected custom BITCAST");
16085 // i64 <=> MMX conversions are Legal.
16086 if (SrcVT==MVT::i64 && DstVT.isVector())
16088 if (DstVT==MVT::i64 && SrcVT.isVector())
16090 // MMX <=> MMX conversions are Legal.
16091 if (SrcVT.isVector() && DstVT.isVector())
16093 // All other conversions need to be expanded.
16097 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
16098 SDNode *Node = Op.getNode();
16100 EVT T = Node->getValueType(0);
16101 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
16102 DAG.getConstant(0, T), Node->getOperand(2));
16103 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
16104 cast<AtomicSDNode>(Node)->getMemoryVT(),
16105 Node->getOperand(0),
16106 Node->getOperand(1), negOp,
16107 cast<AtomicSDNode>(Node)->getMemOperand(),
16108 cast<AtomicSDNode>(Node)->getOrdering(),
16109 cast<AtomicSDNode>(Node)->getSynchScope());
16112 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
16113 SDNode *Node = Op.getNode();
16115 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16117 // Convert seq_cst store -> xchg
16118 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
16119 // FIXME: On 32-bit, store -> fist or movq would be more efficient
16120 // (The only way to get a 16-byte store is cmpxchg16b)
16121 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
16122 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
16123 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
16124 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
16125 cast<AtomicSDNode>(Node)->getMemoryVT(),
16126 Node->getOperand(0),
16127 Node->getOperand(1), Node->getOperand(2),
16128 cast<AtomicSDNode>(Node)->getMemOperand(),
16129 cast<AtomicSDNode>(Node)->getOrdering(),
16130 cast<AtomicSDNode>(Node)->getSynchScope());
16131 return Swap.getValue(1);
16133 // Other atomic stores have a simple pattern.
16137 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
16138 EVT VT = Op.getNode()->getSimpleValueType(0);
16140 // Let legalize expand this if it isn't a legal type yet.
16141 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
16144 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16147 bool ExtraOp = false;
16148 switch (Op.getOpcode()) {
16149 default: llvm_unreachable("Invalid code");
16150 case ISD::ADDC: Opc = X86ISD::ADD; break;
16151 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
16152 case ISD::SUBC: Opc = X86ISD::SUB; break;
16153 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
16157 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16159 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16160 Op.getOperand(1), Op.getOperand(2));
16163 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
16164 SelectionDAG &DAG) {
16165 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
16167 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
16168 // which returns the values as { float, float } (in XMM0) or
16169 // { double, double } (which is returned in XMM0, XMM1).
16171 SDValue Arg = Op.getOperand(0);
16172 EVT ArgVT = Arg.getValueType();
16173 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16175 TargetLowering::ArgListTy Args;
16176 TargetLowering::ArgListEntry Entry;
16180 Entry.isSExt = false;
16181 Entry.isZExt = false;
16182 Args.push_back(Entry);
16184 bool isF64 = ArgVT == MVT::f64;
16185 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
16186 // the small struct {f32, f32} is returned in (eax, edx). For f64,
16187 // the results are returned via SRet in memory.
16188 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
16189 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16190 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
16192 Type *RetTy = isF64
16193 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
16194 : (Type*)VectorType::get(ArgTy, 4);
16196 TargetLowering::CallLoweringInfo CLI(DAG);
16197 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
16198 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
16200 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
16203 // Returned in xmm0 and xmm1.
16204 return CallResult.first;
16206 // Returned in bits 0:31 and 32:64 xmm0.
16207 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16208 CallResult.first, DAG.getIntPtrConstant(0));
16209 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16210 CallResult.first, DAG.getIntPtrConstant(1));
16211 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
16212 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
16215 /// LowerOperation - Provide custom lowering hooks for some operations.
16217 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
16218 switch (Op.getOpcode()) {
16219 default: llvm_unreachable("Should not custom lower this!");
16220 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
16221 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
16222 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
16223 return LowerCMP_SWAP(Op, Subtarget, DAG);
16224 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
16225 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
16226 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
16227 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
16228 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
16229 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
16230 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
16231 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
16232 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
16233 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
16234 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
16235 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
16236 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
16237 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
16238 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
16239 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
16240 case ISD::SHL_PARTS:
16241 case ISD::SRA_PARTS:
16242 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
16243 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
16244 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
16245 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
16246 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
16247 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
16248 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
16249 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
16250 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
16251 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
16252 case ISD::FABS: return LowerFABS(Op, DAG);
16253 case ISD::FNEG: return LowerFNEG(Op, DAG);
16254 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
16255 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
16256 case ISD::SETCC: return LowerSETCC(Op, DAG);
16257 case ISD::SELECT: return LowerSELECT(Op, DAG);
16258 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
16259 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
16260 case ISD::VASTART: return LowerVASTART(Op, DAG);
16261 case ISD::VAARG: return LowerVAARG(Op, DAG);
16262 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
16263 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
16264 case ISD::INTRINSIC_VOID:
16265 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
16266 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
16267 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
16268 case ISD::FRAME_TO_ARGS_OFFSET:
16269 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
16270 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
16271 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
16272 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
16273 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
16274 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
16275 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
16276 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
16277 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
16278 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
16279 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
16280 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
16281 case ISD::UMUL_LOHI:
16282 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
16285 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
16291 case ISD::UMULO: return LowerXALUO(Op, DAG);
16292 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
16293 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
16297 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
16298 case ISD::ADD: return LowerADD(Op, DAG);
16299 case ISD::SUB: return LowerSUB(Op, DAG);
16300 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
16304 static void ReplaceATOMIC_LOAD(SDNode *Node,
16305 SmallVectorImpl<SDValue> &Results,
16306 SelectionDAG &DAG) {
16308 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16310 // Convert wide load -> cmpxchg8b/cmpxchg16b
16311 // FIXME: On 32-bit, load -> fild or movq would be more efficient
16312 // (The only way to get a 16-byte load is cmpxchg16b)
16313 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
16314 SDValue Zero = DAG.getConstant(0, VT);
16315 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
16317 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
16318 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
16319 cast<AtomicSDNode>(Node)->getMemOperand(),
16320 cast<AtomicSDNode>(Node)->getOrdering(),
16321 cast<AtomicSDNode>(Node)->getOrdering(),
16322 cast<AtomicSDNode>(Node)->getSynchScope());
16323 Results.push_back(Swap.getValue(0));
16324 Results.push_back(Swap.getValue(2));
16327 /// ReplaceNodeResults - Replace a node with an illegal result type
16328 /// with a new node built out of custom code.
16329 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
16330 SmallVectorImpl<SDValue>&Results,
16331 SelectionDAG &DAG) const {
16333 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16334 switch (N->getOpcode()) {
16336 llvm_unreachable("Do not know how to custom type legalize this operation!");
16337 case ISD::SIGN_EXTEND_INREG:
16342 // We don't want to expand or promote these.
16349 case ISD::UDIVREM: {
16350 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
16351 Results.push_back(V);
16354 case ISD::FP_TO_SINT:
16355 case ISD::FP_TO_UINT: {
16356 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
16358 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
16361 std::pair<SDValue,SDValue> Vals =
16362 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
16363 SDValue FIST = Vals.first, StackSlot = Vals.second;
16364 if (FIST.getNode()) {
16365 EVT VT = N->getValueType(0);
16366 // Return a load from the stack slot.
16367 if (StackSlot.getNode())
16368 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
16369 MachinePointerInfo(),
16370 false, false, false, 0));
16372 Results.push_back(FIST);
16376 case ISD::UINT_TO_FP: {
16377 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16378 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
16379 N->getValueType(0) != MVT::v2f32)
16381 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
16383 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
16385 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
16386 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
16387 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
16388 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
16389 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
16390 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
16393 case ISD::FP_ROUND: {
16394 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
16396 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
16397 Results.push_back(V);
16400 case ISD::INTRINSIC_W_CHAIN: {
16401 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
16403 default : llvm_unreachable("Do not know how to custom type "
16404 "legalize this intrinsic operation!");
16405 case Intrinsic::x86_rdtsc:
16406 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
16408 case Intrinsic::x86_rdtscp:
16409 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
16411 case Intrinsic::x86_rdpmc:
16412 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
16415 case ISD::READCYCLECOUNTER: {
16416 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
16419 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
16420 EVT T = N->getValueType(0);
16421 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
16422 bool Regs64bit = T == MVT::i128;
16423 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
16424 SDValue cpInL, cpInH;
16425 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
16426 DAG.getConstant(0, HalfT));
16427 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
16428 DAG.getConstant(1, HalfT));
16429 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
16430 Regs64bit ? X86::RAX : X86::EAX,
16432 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
16433 Regs64bit ? X86::RDX : X86::EDX,
16434 cpInH, cpInL.getValue(1));
16435 SDValue swapInL, swapInH;
16436 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
16437 DAG.getConstant(0, HalfT));
16438 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
16439 DAG.getConstant(1, HalfT));
16440 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
16441 Regs64bit ? X86::RBX : X86::EBX,
16442 swapInL, cpInH.getValue(1));
16443 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
16444 Regs64bit ? X86::RCX : X86::ECX,
16445 swapInH, swapInL.getValue(1));
16446 SDValue Ops[] = { swapInH.getValue(0),
16448 swapInH.getValue(1) };
16449 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16450 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
16451 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
16452 X86ISD::LCMPXCHG8_DAG;
16453 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
16454 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
16455 Regs64bit ? X86::RAX : X86::EAX,
16456 HalfT, Result.getValue(1));
16457 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
16458 Regs64bit ? X86::RDX : X86::EDX,
16459 HalfT, cpOutL.getValue(2));
16460 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
16462 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
16463 MVT::i32, cpOutH.getValue(2));
16465 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16466 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16467 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
16469 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
16470 Results.push_back(Success);
16471 Results.push_back(EFLAGS.getValue(1));
16474 case ISD::ATOMIC_SWAP:
16475 case ISD::ATOMIC_LOAD_ADD:
16476 case ISD::ATOMIC_LOAD_SUB:
16477 case ISD::ATOMIC_LOAD_AND:
16478 case ISD::ATOMIC_LOAD_OR:
16479 case ISD::ATOMIC_LOAD_XOR:
16480 case ISD::ATOMIC_LOAD_NAND:
16481 case ISD::ATOMIC_LOAD_MIN:
16482 case ISD::ATOMIC_LOAD_MAX:
16483 case ISD::ATOMIC_LOAD_UMIN:
16484 case ISD::ATOMIC_LOAD_UMAX:
16485 // Delegate to generic TypeLegalization. Situations we can really handle
16486 // should have already been dealt with by X86AtomicExpand.cpp.
16488 case ISD::ATOMIC_LOAD: {
16489 ReplaceATOMIC_LOAD(N, Results, DAG);
16492 case ISD::BITCAST: {
16493 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16494 EVT DstVT = N->getValueType(0);
16495 EVT SrcVT = N->getOperand(0)->getValueType(0);
16497 if (SrcVT != MVT::f64 ||
16498 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
16501 unsigned NumElts = DstVT.getVectorNumElements();
16502 EVT SVT = DstVT.getVectorElementType();
16503 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16504 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
16505 MVT::v2f64, N->getOperand(0));
16506 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
16508 if (ExperimentalVectorWideningLegalization) {
16509 // If we are legalizing vectors by widening, we already have the desired
16510 // legal vector type, just return it.
16511 Results.push_back(ToVecInt);
16515 SmallVector<SDValue, 8> Elts;
16516 for (unsigned i = 0, e = NumElts; i != e; ++i)
16517 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
16518 ToVecInt, DAG.getIntPtrConstant(i)));
16520 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
16525 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
16527 default: return nullptr;
16528 case X86ISD::BSF: return "X86ISD::BSF";
16529 case X86ISD::BSR: return "X86ISD::BSR";
16530 case X86ISD::SHLD: return "X86ISD::SHLD";
16531 case X86ISD::SHRD: return "X86ISD::SHRD";
16532 case X86ISD::FAND: return "X86ISD::FAND";
16533 case X86ISD::FANDN: return "X86ISD::FANDN";
16534 case X86ISD::FOR: return "X86ISD::FOR";
16535 case X86ISD::FXOR: return "X86ISD::FXOR";
16536 case X86ISD::FSRL: return "X86ISD::FSRL";
16537 case X86ISD::FILD: return "X86ISD::FILD";
16538 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
16539 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
16540 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
16541 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
16542 case X86ISD::FLD: return "X86ISD::FLD";
16543 case X86ISD::FST: return "X86ISD::FST";
16544 case X86ISD::CALL: return "X86ISD::CALL";
16545 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
16546 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
16547 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
16548 case X86ISD::BT: return "X86ISD::BT";
16549 case X86ISD::CMP: return "X86ISD::CMP";
16550 case X86ISD::COMI: return "X86ISD::COMI";
16551 case X86ISD::UCOMI: return "X86ISD::UCOMI";
16552 case X86ISD::CMPM: return "X86ISD::CMPM";
16553 case X86ISD::CMPMU: return "X86ISD::CMPMU";
16554 case X86ISD::SETCC: return "X86ISD::SETCC";
16555 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
16556 case X86ISD::FSETCC: return "X86ISD::FSETCC";
16557 case X86ISD::CMOV: return "X86ISD::CMOV";
16558 case X86ISD::BRCOND: return "X86ISD::BRCOND";
16559 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
16560 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
16561 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
16562 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
16563 case X86ISD::Wrapper: return "X86ISD::Wrapper";
16564 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
16565 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
16566 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
16567 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
16568 case X86ISD::PINSRB: return "X86ISD::PINSRB";
16569 case X86ISD::PINSRW: return "X86ISD::PINSRW";
16570 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
16571 case X86ISD::ANDNP: return "X86ISD::ANDNP";
16572 case X86ISD::PSIGN: return "X86ISD::PSIGN";
16573 case X86ISD::BLENDV: return "X86ISD::BLENDV";
16574 case X86ISD::BLENDI: return "X86ISD::BLENDI";
16575 case X86ISD::SUBUS: return "X86ISD::SUBUS";
16576 case X86ISD::HADD: return "X86ISD::HADD";
16577 case X86ISD::HSUB: return "X86ISD::HSUB";
16578 case X86ISD::FHADD: return "X86ISD::FHADD";
16579 case X86ISD::FHSUB: return "X86ISD::FHSUB";
16580 case X86ISD::UMAX: return "X86ISD::UMAX";
16581 case X86ISD::UMIN: return "X86ISD::UMIN";
16582 case X86ISD::SMAX: return "X86ISD::SMAX";
16583 case X86ISD::SMIN: return "X86ISD::SMIN";
16584 case X86ISD::FMAX: return "X86ISD::FMAX";
16585 case X86ISD::FMIN: return "X86ISD::FMIN";
16586 case X86ISD::FMAXC: return "X86ISD::FMAXC";
16587 case X86ISD::FMINC: return "X86ISD::FMINC";
16588 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
16589 case X86ISD::FRCP: return "X86ISD::FRCP";
16590 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
16591 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
16592 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
16593 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
16594 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
16595 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
16596 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
16597 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
16598 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
16599 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
16600 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
16601 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
16602 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
16603 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
16604 case X86ISD::VZEXT: return "X86ISD::VZEXT";
16605 case X86ISD::VSEXT: return "X86ISD::VSEXT";
16606 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
16607 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
16608 case X86ISD::VINSERT: return "X86ISD::VINSERT";
16609 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
16610 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
16611 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
16612 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
16613 case X86ISD::VSHL: return "X86ISD::VSHL";
16614 case X86ISD::VSRL: return "X86ISD::VSRL";
16615 case X86ISD::VSRA: return "X86ISD::VSRA";
16616 case X86ISD::VSHLI: return "X86ISD::VSHLI";
16617 case X86ISD::VSRLI: return "X86ISD::VSRLI";
16618 case X86ISD::VSRAI: return "X86ISD::VSRAI";
16619 case X86ISD::CMPP: return "X86ISD::CMPP";
16620 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
16621 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
16622 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
16623 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
16624 case X86ISD::ADD: return "X86ISD::ADD";
16625 case X86ISD::SUB: return "X86ISD::SUB";
16626 case X86ISD::ADC: return "X86ISD::ADC";
16627 case X86ISD::SBB: return "X86ISD::SBB";
16628 case X86ISD::SMUL: return "X86ISD::SMUL";
16629 case X86ISD::UMUL: return "X86ISD::UMUL";
16630 case X86ISD::INC: return "X86ISD::INC";
16631 case X86ISD::DEC: return "X86ISD::DEC";
16632 case X86ISD::OR: return "X86ISD::OR";
16633 case X86ISD::XOR: return "X86ISD::XOR";
16634 case X86ISD::AND: return "X86ISD::AND";
16635 case X86ISD::BEXTR: return "X86ISD::BEXTR";
16636 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
16637 case X86ISD::PTEST: return "X86ISD::PTEST";
16638 case X86ISD::TESTP: return "X86ISD::TESTP";
16639 case X86ISD::TESTM: return "X86ISD::TESTM";
16640 case X86ISD::TESTNM: return "X86ISD::TESTNM";
16641 case X86ISD::KORTEST: return "X86ISD::KORTEST";
16642 case X86ISD::PACKSS: return "X86ISD::PACKSS";
16643 case X86ISD::PACKUS: return "X86ISD::PACKUS";
16644 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
16645 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
16646 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
16647 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
16648 case X86ISD::SHUFP: return "X86ISD::SHUFP";
16649 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
16650 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
16651 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
16652 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
16653 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
16654 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
16655 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
16656 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
16657 case X86ISD::MOVSD: return "X86ISD::MOVSD";
16658 case X86ISD::MOVSS: return "X86ISD::MOVSS";
16659 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
16660 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
16661 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
16662 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
16663 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
16664 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
16665 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
16666 case X86ISD::VPERMV: return "X86ISD::VPERMV";
16667 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
16668 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
16669 case X86ISD::VPERMI: return "X86ISD::VPERMI";
16670 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
16671 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
16672 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
16673 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
16674 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
16675 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
16676 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
16677 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
16678 case X86ISD::SAHF: return "X86ISD::SAHF";
16679 case X86ISD::RDRAND: return "X86ISD::RDRAND";
16680 case X86ISD::RDSEED: return "X86ISD::RDSEED";
16681 case X86ISD::FMADD: return "X86ISD::FMADD";
16682 case X86ISD::FMSUB: return "X86ISD::FMSUB";
16683 case X86ISD::FNMADD: return "X86ISD::FNMADD";
16684 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
16685 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
16686 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
16687 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
16688 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
16689 case X86ISD::XTEST: return "X86ISD::XTEST";
16693 // isLegalAddressingMode - Return true if the addressing mode represented
16694 // by AM is legal for this target, for a load/store of the specified type.
16695 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
16697 // X86 supports extremely general addressing modes.
16698 CodeModel::Model M = getTargetMachine().getCodeModel();
16699 Reloc::Model R = getTargetMachine().getRelocationModel();
16701 // X86 allows a sign-extended 32-bit immediate field as a displacement.
16702 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
16707 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
16709 // If a reference to this global requires an extra load, we can't fold it.
16710 if (isGlobalStubReference(GVFlags))
16713 // If BaseGV requires a register for the PIC base, we cannot also have a
16714 // BaseReg specified.
16715 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
16718 // If lower 4G is not available, then we must use rip-relative addressing.
16719 if ((M != CodeModel::Small || R != Reloc::Static) &&
16720 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
16724 switch (AM.Scale) {
16730 // These scales always work.
16735 // These scales are formed with basereg+scalereg. Only accept if there is
16740 default: // Other stuff never works.
16747 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
16748 unsigned Bits = Ty->getScalarSizeInBits();
16750 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
16751 // particularly cheaper than those without.
16755 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
16756 // variable shifts just as cheap as scalar ones.
16757 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
16760 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
16761 // fully general vector.
16765 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
16766 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
16768 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
16769 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
16770 return NumBits1 > NumBits2;
16773 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
16774 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
16777 if (!isTypeLegal(EVT::getEVT(Ty1)))
16780 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
16782 // Assuming the caller doesn't have a zeroext or signext return parameter,
16783 // truncation all the way down to i1 is valid.
16787 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
16788 return isInt<32>(Imm);
16791 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
16792 // Can also use sub to handle negated immediates.
16793 return isInt<32>(Imm);
16796 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
16797 if (!VT1.isInteger() || !VT2.isInteger())
16799 unsigned NumBits1 = VT1.getSizeInBits();
16800 unsigned NumBits2 = VT2.getSizeInBits();
16801 return NumBits1 > NumBits2;
16804 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
16805 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
16806 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
16809 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
16810 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
16811 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
16814 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
16815 EVT VT1 = Val.getValueType();
16816 if (isZExtFree(VT1, VT2))
16819 if (Val.getOpcode() != ISD::LOAD)
16822 if (!VT1.isSimple() || !VT1.isInteger() ||
16823 !VT2.isSimple() || !VT2.isInteger())
16826 switch (VT1.getSimpleVT().SimpleTy) {
16831 // X86 has 8, 16, and 32-bit zero-extending loads.
16839 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
16840 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
16843 VT = VT.getScalarType();
16845 if (!VT.isSimple())
16848 switch (VT.getSimpleVT().SimpleTy) {
16859 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
16860 // i16 instructions are longer (0x66 prefix) and potentially slower.
16861 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
16864 /// isShuffleMaskLegal - Targets can use this to indicate that they only
16865 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
16866 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
16867 /// are assumed to be legal.
16869 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
16871 if (!VT.isSimple())
16874 MVT SVT = VT.getSimpleVT();
16876 // Very little shuffling can be done for 64-bit vectors right now.
16877 if (VT.getSizeInBits() == 64)
16880 // If this is a single-input shuffle with no 128 bit lane crossings we can
16881 // lower it into pshufb.
16882 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
16883 (SVT.is256BitVector() && Subtarget->hasInt256())) {
16884 bool isLegal = true;
16885 for (unsigned I = 0, E = M.size(); I != E; ++I) {
16886 if (M[I] >= (int)SVT.getVectorNumElements() ||
16887 ShuffleCrosses128bitLane(SVT, I, M[I])) {
16896 // FIXME: blends, shifts.
16897 return (SVT.getVectorNumElements() == 2 ||
16898 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
16899 isMOVLMask(M, SVT) ||
16900 isMOVHLPSMask(M, SVT) ||
16901 isSHUFPMask(M, SVT) ||
16902 isPSHUFDMask(M, SVT) ||
16903 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
16904 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
16905 isPALIGNRMask(M, SVT, Subtarget) ||
16906 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
16907 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
16908 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
16909 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
16910 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
16914 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
16916 if (!VT.isSimple())
16919 MVT SVT = VT.getSimpleVT();
16920 unsigned NumElts = SVT.getVectorNumElements();
16921 // FIXME: This collection of masks seems suspect.
16924 if (NumElts == 4 && SVT.is128BitVector()) {
16925 return (isMOVLMask(Mask, SVT) ||
16926 isCommutedMOVLMask(Mask, SVT, true) ||
16927 isSHUFPMask(Mask, SVT) ||
16928 isSHUFPMask(Mask, SVT, /* Commuted */ true));
16933 //===----------------------------------------------------------------------===//
16934 // X86 Scheduler Hooks
16935 //===----------------------------------------------------------------------===//
16937 /// Utility function to emit xbegin specifying the start of an RTM region.
16938 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
16939 const TargetInstrInfo *TII) {
16940 DebugLoc DL = MI->getDebugLoc();
16942 const BasicBlock *BB = MBB->getBasicBlock();
16943 MachineFunction::iterator I = MBB;
16946 // For the v = xbegin(), we generate
16957 MachineBasicBlock *thisMBB = MBB;
16958 MachineFunction *MF = MBB->getParent();
16959 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
16960 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
16961 MF->insert(I, mainMBB);
16962 MF->insert(I, sinkMBB);
16964 // Transfer the remainder of BB and its successor edges to sinkMBB.
16965 sinkMBB->splice(sinkMBB->begin(), MBB,
16966 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
16967 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
16971 // # fallthrough to mainMBB
16972 // # abortion to sinkMBB
16973 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
16974 thisMBB->addSuccessor(mainMBB);
16975 thisMBB->addSuccessor(sinkMBB);
16979 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
16980 mainMBB->addSuccessor(sinkMBB);
16983 // EAX is live into the sinkMBB
16984 sinkMBB->addLiveIn(X86::EAX);
16985 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
16986 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
16989 MI->eraseFromParent();
16993 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
16994 // or XMM0_V32I8 in AVX all of this code can be replaced with that
16995 // in the .td file.
16996 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
16997 const TargetInstrInfo *TII) {
16999 switch (MI->getOpcode()) {
17000 default: llvm_unreachable("illegal opcode!");
17001 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
17002 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
17003 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
17004 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
17005 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
17006 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
17007 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
17008 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
17011 DebugLoc dl = MI->getDebugLoc();
17012 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17014 unsigned NumArgs = MI->getNumOperands();
17015 for (unsigned i = 1; i < NumArgs; ++i) {
17016 MachineOperand &Op = MI->getOperand(i);
17017 if (!(Op.isReg() && Op.isImplicit()))
17018 MIB.addOperand(Op);
17020 if (MI->hasOneMemOperand())
17021 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17023 BuildMI(*BB, MI, dl,
17024 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17025 .addReg(X86::XMM0);
17027 MI->eraseFromParent();
17031 // FIXME: Custom handling because TableGen doesn't support multiple implicit
17032 // defs in an instruction pattern
17033 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
17034 const TargetInstrInfo *TII) {
17036 switch (MI->getOpcode()) {
17037 default: llvm_unreachable("illegal opcode!");
17038 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
17039 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
17040 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
17041 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
17042 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
17043 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
17044 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
17045 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
17048 DebugLoc dl = MI->getDebugLoc();
17049 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17051 unsigned NumArgs = MI->getNumOperands(); // remove the results
17052 for (unsigned i = 1; i < NumArgs; ++i) {
17053 MachineOperand &Op = MI->getOperand(i);
17054 if (!(Op.isReg() && Op.isImplicit()))
17055 MIB.addOperand(Op);
17057 if (MI->hasOneMemOperand())
17058 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17060 BuildMI(*BB, MI, dl,
17061 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17064 MI->eraseFromParent();
17068 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
17069 const TargetInstrInfo *TII,
17070 const X86Subtarget* Subtarget) {
17071 DebugLoc dl = MI->getDebugLoc();
17073 // Address into RAX/EAX, other two args into ECX, EDX.
17074 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
17075 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
17076 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
17077 for (int i = 0; i < X86::AddrNumOperands; ++i)
17078 MIB.addOperand(MI->getOperand(i));
17080 unsigned ValOps = X86::AddrNumOperands;
17081 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
17082 .addReg(MI->getOperand(ValOps).getReg());
17083 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
17084 .addReg(MI->getOperand(ValOps+1).getReg());
17086 // The instruction doesn't actually take any operands though.
17087 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
17089 MI->eraseFromParent(); // The pseudo is gone now.
17093 MachineBasicBlock *
17094 X86TargetLowering::EmitVAARG64WithCustomInserter(
17096 MachineBasicBlock *MBB) const {
17097 // Emit va_arg instruction on X86-64.
17099 // Operands to this pseudo-instruction:
17100 // 0 ) Output : destination address (reg)
17101 // 1-5) Input : va_list address (addr, i64mem)
17102 // 6 ) ArgSize : Size (in bytes) of vararg type
17103 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
17104 // 8 ) Align : Alignment of type
17105 // 9 ) EFLAGS (implicit-def)
17107 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
17108 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
17110 unsigned DestReg = MI->getOperand(0).getReg();
17111 MachineOperand &Base = MI->getOperand(1);
17112 MachineOperand &Scale = MI->getOperand(2);
17113 MachineOperand &Index = MI->getOperand(3);
17114 MachineOperand &Disp = MI->getOperand(4);
17115 MachineOperand &Segment = MI->getOperand(5);
17116 unsigned ArgSize = MI->getOperand(6).getImm();
17117 unsigned ArgMode = MI->getOperand(7).getImm();
17118 unsigned Align = MI->getOperand(8).getImm();
17120 // Memory Reference
17121 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
17122 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17123 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17125 // Machine Information
17126 const TargetInstrInfo *TII = MBB->getParent()->getTarget().getInstrInfo();
17127 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
17128 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
17129 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
17130 DebugLoc DL = MI->getDebugLoc();
17132 // struct va_list {
17135 // i64 overflow_area (address)
17136 // i64 reg_save_area (address)
17138 // sizeof(va_list) = 24
17139 // alignment(va_list) = 8
17141 unsigned TotalNumIntRegs = 6;
17142 unsigned TotalNumXMMRegs = 8;
17143 bool UseGPOffset = (ArgMode == 1);
17144 bool UseFPOffset = (ArgMode == 2);
17145 unsigned MaxOffset = TotalNumIntRegs * 8 +
17146 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
17148 /* Align ArgSize to a multiple of 8 */
17149 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
17150 bool NeedsAlign = (Align > 8);
17152 MachineBasicBlock *thisMBB = MBB;
17153 MachineBasicBlock *overflowMBB;
17154 MachineBasicBlock *offsetMBB;
17155 MachineBasicBlock *endMBB;
17157 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
17158 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
17159 unsigned OffsetReg = 0;
17161 if (!UseGPOffset && !UseFPOffset) {
17162 // If we only pull from the overflow region, we don't create a branch.
17163 // We don't need to alter control flow.
17164 OffsetDestReg = 0; // unused
17165 OverflowDestReg = DestReg;
17167 offsetMBB = nullptr;
17168 overflowMBB = thisMBB;
17171 // First emit code to check if gp_offset (or fp_offset) is below the bound.
17172 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
17173 // If not, pull from overflow_area. (branch to overflowMBB)
17178 // offsetMBB overflowMBB
17183 // Registers for the PHI in endMBB
17184 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
17185 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
17187 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17188 MachineFunction *MF = MBB->getParent();
17189 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17190 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17191 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17193 MachineFunction::iterator MBBIter = MBB;
17196 // Insert the new basic blocks
17197 MF->insert(MBBIter, offsetMBB);
17198 MF->insert(MBBIter, overflowMBB);
17199 MF->insert(MBBIter, endMBB);
17201 // Transfer the remainder of MBB and its successor edges to endMBB.
17202 endMBB->splice(endMBB->begin(), thisMBB,
17203 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
17204 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
17206 // Make offsetMBB and overflowMBB successors of thisMBB
17207 thisMBB->addSuccessor(offsetMBB);
17208 thisMBB->addSuccessor(overflowMBB);
17210 // endMBB is a successor of both offsetMBB and overflowMBB
17211 offsetMBB->addSuccessor(endMBB);
17212 overflowMBB->addSuccessor(endMBB);
17214 // Load the offset value into a register
17215 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17216 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
17220 .addDisp(Disp, UseFPOffset ? 4 : 0)
17221 .addOperand(Segment)
17222 .setMemRefs(MMOBegin, MMOEnd);
17224 // Check if there is enough room left to pull this argument.
17225 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
17227 .addImm(MaxOffset + 8 - ArgSizeA8);
17229 // Branch to "overflowMBB" if offset >= max
17230 // Fall through to "offsetMBB" otherwise
17231 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
17232 .addMBB(overflowMBB);
17235 // In offsetMBB, emit code to use the reg_save_area.
17237 assert(OffsetReg != 0);
17239 // Read the reg_save_area address.
17240 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
17241 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
17246 .addOperand(Segment)
17247 .setMemRefs(MMOBegin, MMOEnd);
17249 // Zero-extend the offset
17250 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
17251 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
17254 .addImm(X86::sub_32bit);
17256 // Add the offset to the reg_save_area to get the final address.
17257 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
17258 .addReg(OffsetReg64)
17259 .addReg(RegSaveReg);
17261 // Compute the offset for the next argument
17262 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17263 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
17265 .addImm(UseFPOffset ? 16 : 8);
17267 // Store it back into the va_list.
17268 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
17272 .addDisp(Disp, UseFPOffset ? 4 : 0)
17273 .addOperand(Segment)
17274 .addReg(NextOffsetReg)
17275 .setMemRefs(MMOBegin, MMOEnd);
17278 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
17283 // Emit code to use overflow area
17286 // Load the overflow_area address into a register.
17287 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
17288 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
17293 .addOperand(Segment)
17294 .setMemRefs(MMOBegin, MMOEnd);
17296 // If we need to align it, do so. Otherwise, just copy the address
17297 // to OverflowDestReg.
17299 // Align the overflow address
17300 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
17301 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
17303 // aligned_addr = (addr + (align-1)) & ~(align-1)
17304 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
17305 .addReg(OverflowAddrReg)
17308 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
17310 .addImm(~(uint64_t)(Align-1));
17312 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
17313 .addReg(OverflowAddrReg);
17316 // Compute the next overflow address after this argument.
17317 // (the overflow address should be kept 8-byte aligned)
17318 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
17319 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
17320 .addReg(OverflowDestReg)
17321 .addImm(ArgSizeA8);
17323 // Store the new overflow address.
17324 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
17329 .addOperand(Segment)
17330 .addReg(NextAddrReg)
17331 .setMemRefs(MMOBegin, MMOEnd);
17333 // If we branched, emit the PHI to the front of endMBB.
17335 BuildMI(*endMBB, endMBB->begin(), DL,
17336 TII->get(X86::PHI), DestReg)
17337 .addReg(OffsetDestReg).addMBB(offsetMBB)
17338 .addReg(OverflowDestReg).addMBB(overflowMBB);
17341 // Erase the pseudo instruction
17342 MI->eraseFromParent();
17347 MachineBasicBlock *
17348 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
17350 MachineBasicBlock *MBB) const {
17351 // Emit code to save XMM registers to the stack. The ABI says that the
17352 // number of registers to save is given in %al, so it's theoretically
17353 // possible to do an indirect jump trick to avoid saving all of them,
17354 // however this code takes a simpler approach and just executes all
17355 // of the stores if %al is non-zero. It's less code, and it's probably
17356 // easier on the hardware branch predictor, and stores aren't all that
17357 // expensive anyway.
17359 // Create the new basic blocks. One block contains all the XMM stores,
17360 // and one block is the final destination regardless of whether any
17361 // stores were performed.
17362 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17363 MachineFunction *F = MBB->getParent();
17364 MachineFunction::iterator MBBIter = MBB;
17366 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
17367 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
17368 F->insert(MBBIter, XMMSaveMBB);
17369 F->insert(MBBIter, EndMBB);
17371 // Transfer the remainder of MBB and its successor edges to EndMBB.
17372 EndMBB->splice(EndMBB->begin(), MBB,
17373 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17374 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
17376 // The original block will now fall through to the XMM save block.
17377 MBB->addSuccessor(XMMSaveMBB);
17378 // The XMMSaveMBB will fall through to the end block.
17379 XMMSaveMBB->addSuccessor(EndMBB);
17381 // Now add the instructions.
17382 const TargetInstrInfo *TII = MBB->getParent()->getTarget().getInstrInfo();
17383 DebugLoc DL = MI->getDebugLoc();
17385 unsigned CountReg = MI->getOperand(0).getReg();
17386 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
17387 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
17389 if (!Subtarget->isTargetWin64()) {
17390 // If %al is 0, branch around the XMM save block.
17391 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
17392 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
17393 MBB->addSuccessor(EndMBB);
17396 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
17397 // that was just emitted, but clearly shouldn't be "saved".
17398 assert((MI->getNumOperands() <= 3 ||
17399 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
17400 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
17401 && "Expected last argument to be EFLAGS");
17402 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
17403 // In the XMM save block, save all the XMM argument registers.
17404 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
17405 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
17406 MachineMemOperand *MMO =
17407 F->getMachineMemOperand(
17408 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
17409 MachineMemOperand::MOStore,
17410 /*Size=*/16, /*Align=*/16);
17411 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
17412 .addFrameIndex(RegSaveFrameIndex)
17413 .addImm(/*Scale=*/1)
17414 .addReg(/*IndexReg=*/0)
17415 .addImm(/*Disp=*/Offset)
17416 .addReg(/*Segment=*/0)
17417 .addReg(MI->getOperand(i).getReg())
17418 .addMemOperand(MMO);
17421 MI->eraseFromParent(); // The pseudo instruction is gone now.
17426 // The EFLAGS operand of SelectItr might be missing a kill marker
17427 // because there were multiple uses of EFLAGS, and ISel didn't know
17428 // which to mark. Figure out whether SelectItr should have had a
17429 // kill marker, and set it if it should. Returns the correct kill
17431 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
17432 MachineBasicBlock* BB,
17433 const TargetRegisterInfo* TRI) {
17434 // Scan forward through BB for a use/def of EFLAGS.
17435 MachineBasicBlock::iterator miI(std::next(SelectItr));
17436 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
17437 const MachineInstr& mi = *miI;
17438 if (mi.readsRegister(X86::EFLAGS))
17440 if (mi.definesRegister(X86::EFLAGS))
17441 break; // Should have kill-flag - update below.
17444 // If we hit the end of the block, check whether EFLAGS is live into a
17446 if (miI == BB->end()) {
17447 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
17448 sEnd = BB->succ_end();
17449 sItr != sEnd; ++sItr) {
17450 MachineBasicBlock* succ = *sItr;
17451 if (succ->isLiveIn(X86::EFLAGS))
17456 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
17457 // out. SelectMI should have a kill flag on EFLAGS.
17458 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
17462 MachineBasicBlock *
17463 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
17464 MachineBasicBlock *BB) const {
17465 const TargetInstrInfo *TII = BB->getParent()->getTarget().getInstrInfo();
17466 DebugLoc DL = MI->getDebugLoc();
17468 // To "insert" a SELECT_CC instruction, we actually have to insert the
17469 // diamond control-flow pattern. The incoming instruction knows the
17470 // destination vreg to set, the condition code register to branch on, the
17471 // true/false values to select between, and a branch opcode to use.
17472 const BasicBlock *LLVM_BB = BB->getBasicBlock();
17473 MachineFunction::iterator It = BB;
17479 // cmpTY ccX, r1, r2
17481 // fallthrough --> copy0MBB
17482 MachineBasicBlock *thisMBB = BB;
17483 MachineFunction *F = BB->getParent();
17484 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
17485 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
17486 F->insert(It, copy0MBB);
17487 F->insert(It, sinkMBB);
17489 // If the EFLAGS register isn't dead in the terminator, then claim that it's
17490 // live into the sink and copy blocks.
17491 const TargetRegisterInfo* TRI = BB->getParent()->getTarget().getRegisterInfo();
17492 if (!MI->killsRegister(X86::EFLAGS) &&
17493 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
17494 copy0MBB->addLiveIn(X86::EFLAGS);
17495 sinkMBB->addLiveIn(X86::EFLAGS);
17498 // Transfer the remainder of BB and its successor edges to sinkMBB.
17499 sinkMBB->splice(sinkMBB->begin(), BB,
17500 std::next(MachineBasicBlock::iterator(MI)), BB->end());
17501 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
17503 // Add the true and fallthrough blocks as its successors.
17504 BB->addSuccessor(copy0MBB);
17505 BB->addSuccessor(sinkMBB);
17507 // Create the conditional branch instruction.
17509 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
17510 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
17513 // %FalseValue = ...
17514 // # fallthrough to sinkMBB
17515 copy0MBB->addSuccessor(sinkMBB);
17518 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
17520 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17521 TII->get(X86::PHI), MI->getOperand(0).getReg())
17522 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
17523 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
17525 MI->eraseFromParent(); // The pseudo instruction is gone now.
17529 MachineBasicBlock *
17530 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
17531 bool Is64Bit) const {
17532 MachineFunction *MF = BB->getParent();
17533 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
17534 DebugLoc DL = MI->getDebugLoc();
17535 const BasicBlock *LLVM_BB = BB->getBasicBlock();
17537 assert(MF->shouldSplitStack());
17539 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
17540 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
17543 // ... [Till the alloca]
17544 // If stacklet is not large enough, jump to mallocMBB
17547 // Allocate by subtracting from RSP
17548 // Jump to continueMBB
17551 // Allocate by call to runtime
17555 // [rest of original BB]
17558 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17559 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17560 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17562 MachineRegisterInfo &MRI = MF->getRegInfo();
17563 const TargetRegisterClass *AddrRegClass =
17564 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
17566 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
17567 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
17568 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
17569 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
17570 sizeVReg = MI->getOperand(1).getReg(),
17571 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
17573 MachineFunction::iterator MBBIter = BB;
17576 MF->insert(MBBIter, bumpMBB);
17577 MF->insert(MBBIter, mallocMBB);
17578 MF->insert(MBBIter, continueMBB);
17580 continueMBB->splice(continueMBB->begin(), BB,
17581 std::next(MachineBasicBlock::iterator(MI)), BB->end());
17582 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
17584 // Add code to the main basic block to check if the stack limit has been hit,
17585 // and if so, jump to mallocMBB otherwise to bumpMBB.
17586 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
17587 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
17588 .addReg(tmpSPVReg).addReg(sizeVReg);
17589 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
17590 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
17591 .addReg(SPLimitVReg);
17592 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
17594 // bumpMBB simply decreases the stack pointer, since we know the current
17595 // stacklet has enough space.
17596 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
17597 .addReg(SPLimitVReg);
17598 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
17599 .addReg(SPLimitVReg);
17600 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
17602 // Calls into a routine in libgcc to allocate more space from the heap.
17603 const uint32_t *RegMask =
17604 MF->getTarget().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
17606 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
17608 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
17609 .addExternalSymbol("__morestack_allocate_stack_space")
17610 .addRegMask(RegMask)
17611 .addReg(X86::RDI, RegState::Implicit)
17612 .addReg(X86::RAX, RegState::ImplicitDefine);
17614 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
17616 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
17617 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
17618 .addExternalSymbol("__morestack_allocate_stack_space")
17619 .addRegMask(RegMask)
17620 .addReg(X86::EAX, RegState::ImplicitDefine);
17624 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
17627 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
17628 .addReg(Is64Bit ? X86::RAX : X86::EAX);
17629 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
17631 // Set up the CFG correctly.
17632 BB->addSuccessor(bumpMBB);
17633 BB->addSuccessor(mallocMBB);
17634 mallocMBB->addSuccessor(continueMBB);
17635 bumpMBB->addSuccessor(continueMBB);
17637 // Take care of the PHI nodes.
17638 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
17639 MI->getOperand(0).getReg())
17640 .addReg(mallocPtrVReg).addMBB(mallocMBB)
17641 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
17643 // Delete the original pseudo instruction.
17644 MI->eraseFromParent();
17647 return continueMBB;
17650 MachineBasicBlock *
17651 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
17652 MachineBasicBlock *BB) const {
17653 const TargetInstrInfo *TII = BB->getParent()->getTarget().getInstrInfo();
17654 DebugLoc DL = MI->getDebugLoc();
17656 assert(!Subtarget->isTargetMacho());
17658 // The lowering is pretty easy: we're just emitting the call to _alloca. The
17659 // non-trivial part is impdef of ESP.
17661 if (Subtarget->isTargetWin64()) {
17662 if (Subtarget->isTargetCygMing()) {
17663 // ___chkstk(Mingw64):
17664 // Clobbers R10, R11, RAX and EFLAGS.
17666 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
17667 .addExternalSymbol("___chkstk")
17668 .addReg(X86::RAX, RegState::Implicit)
17669 .addReg(X86::RSP, RegState::Implicit)
17670 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
17671 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
17672 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
17674 // __chkstk(MSVCRT): does not update stack pointer.
17675 // Clobbers R10, R11 and EFLAGS.
17676 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
17677 .addExternalSymbol("__chkstk")
17678 .addReg(X86::RAX, RegState::Implicit)
17679 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
17680 // RAX has the offset to be subtracted from RSP.
17681 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
17686 const char *StackProbeSymbol =
17687 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
17689 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
17690 .addExternalSymbol(StackProbeSymbol)
17691 .addReg(X86::EAX, RegState::Implicit)
17692 .addReg(X86::ESP, RegState::Implicit)
17693 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
17694 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
17695 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
17698 MI->eraseFromParent(); // The pseudo instruction is gone now.
17702 MachineBasicBlock *
17703 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
17704 MachineBasicBlock *BB) const {
17705 // This is pretty easy. We're taking the value that we received from
17706 // our load from the relocation, sticking it in either RDI (x86-64)
17707 // or EAX and doing an indirect call. The return value will then
17708 // be in the normal return register.
17709 MachineFunction *F = BB->getParent();
17710 const X86InstrInfo *TII
17711 = static_cast<const X86InstrInfo*>(F->getTarget().getInstrInfo());
17712 DebugLoc DL = MI->getDebugLoc();
17714 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
17715 assert(MI->getOperand(3).isGlobal() && "This should be a global");
17717 // Get a register mask for the lowered call.
17718 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
17719 // proper register mask.
17720 const uint32_t *RegMask =
17721 F->getTarget().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
17722 if (Subtarget->is64Bit()) {
17723 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
17724 TII->get(X86::MOV64rm), X86::RDI)
17726 .addImm(0).addReg(0)
17727 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
17728 MI->getOperand(3).getTargetFlags())
17730 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
17731 addDirectMem(MIB, X86::RDI);
17732 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
17733 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
17734 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
17735 TII->get(X86::MOV32rm), X86::EAX)
17737 .addImm(0).addReg(0)
17738 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
17739 MI->getOperand(3).getTargetFlags())
17741 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
17742 addDirectMem(MIB, X86::EAX);
17743 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
17745 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
17746 TII->get(X86::MOV32rm), X86::EAX)
17747 .addReg(TII->getGlobalBaseReg(F))
17748 .addImm(0).addReg(0)
17749 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
17750 MI->getOperand(3).getTargetFlags())
17752 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
17753 addDirectMem(MIB, X86::EAX);
17754 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
17757 MI->eraseFromParent(); // The pseudo instruction is gone now.
17761 MachineBasicBlock *
17762 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
17763 MachineBasicBlock *MBB) const {
17764 DebugLoc DL = MI->getDebugLoc();
17765 MachineFunction *MF = MBB->getParent();
17766 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
17767 MachineRegisterInfo &MRI = MF->getRegInfo();
17769 const BasicBlock *BB = MBB->getBasicBlock();
17770 MachineFunction::iterator I = MBB;
17773 // Memory Reference
17774 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17775 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17778 unsigned MemOpndSlot = 0;
17780 unsigned CurOp = 0;
17782 DstReg = MI->getOperand(CurOp++).getReg();
17783 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
17784 assert(RC->hasType(MVT::i32) && "Invalid destination!");
17785 unsigned mainDstReg = MRI.createVirtualRegister(RC);
17786 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
17788 MemOpndSlot = CurOp;
17790 MVT PVT = getPointerTy();
17791 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
17792 "Invalid Pointer Size!");
17794 // For v = setjmp(buf), we generate
17797 // buf[LabelOffset] = restoreMBB
17798 // SjLjSetup restoreMBB
17804 // v = phi(main, restore)
17809 MachineBasicBlock *thisMBB = MBB;
17810 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17811 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17812 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
17813 MF->insert(I, mainMBB);
17814 MF->insert(I, sinkMBB);
17815 MF->push_back(restoreMBB);
17817 MachineInstrBuilder MIB;
17819 // Transfer the remainder of BB and its successor edges to sinkMBB.
17820 sinkMBB->splice(sinkMBB->begin(), MBB,
17821 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17822 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17825 unsigned PtrStoreOpc = 0;
17826 unsigned LabelReg = 0;
17827 const int64_t LabelOffset = 1 * PVT.getStoreSize();
17828 Reloc::Model RM = MF->getTarget().getRelocationModel();
17829 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
17830 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
17832 // Prepare IP either in reg or imm.
17833 if (!UseImmLabel) {
17834 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
17835 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
17836 LabelReg = MRI.createVirtualRegister(PtrRC);
17837 if (Subtarget->is64Bit()) {
17838 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
17842 .addMBB(restoreMBB)
17845 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
17846 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
17847 .addReg(XII->getGlobalBaseReg(MF))
17850 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
17854 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
17856 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
17857 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
17858 if (i == X86::AddrDisp)
17859 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
17861 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
17864 MIB.addReg(LabelReg);
17866 MIB.addMBB(restoreMBB);
17867 MIB.setMemRefs(MMOBegin, MMOEnd);
17869 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
17870 .addMBB(restoreMBB);
17872 const X86RegisterInfo *RegInfo =
17873 static_cast<const X86RegisterInfo*>(MF->getTarget().getRegisterInfo());
17874 MIB.addRegMask(RegInfo->getNoPreservedMask());
17875 thisMBB->addSuccessor(mainMBB);
17876 thisMBB->addSuccessor(restoreMBB);
17880 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
17881 mainMBB->addSuccessor(sinkMBB);
17884 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17885 TII->get(X86::PHI), DstReg)
17886 .addReg(mainDstReg).addMBB(mainMBB)
17887 .addReg(restoreDstReg).addMBB(restoreMBB);
17890 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
17891 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
17892 restoreMBB->addSuccessor(sinkMBB);
17894 MI->eraseFromParent();
17898 MachineBasicBlock *
17899 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
17900 MachineBasicBlock *MBB) const {
17901 DebugLoc DL = MI->getDebugLoc();
17902 MachineFunction *MF = MBB->getParent();
17903 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
17904 MachineRegisterInfo &MRI = MF->getRegInfo();
17906 // Memory Reference
17907 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17908 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17910 MVT PVT = getPointerTy();
17911 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
17912 "Invalid Pointer Size!");
17914 const TargetRegisterClass *RC =
17915 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
17916 unsigned Tmp = MRI.createVirtualRegister(RC);
17917 // Since FP is only updated here but NOT referenced, it's treated as GPR.
17918 const X86RegisterInfo *RegInfo =
17919 static_cast<const X86RegisterInfo*>(MF->getTarget().getRegisterInfo());
17920 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
17921 unsigned SP = RegInfo->getStackRegister();
17923 MachineInstrBuilder MIB;
17925 const int64_t LabelOffset = 1 * PVT.getStoreSize();
17926 const int64_t SPOffset = 2 * PVT.getStoreSize();
17928 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
17929 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
17932 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
17933 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
17934 MIB.addOperand(MI->getOperand(i));
17935 MIB.setMemRefs(MMOBegin, MMOEnd);
17937 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
17938 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
17939 if (i == X86::AddrDisp)
17940 MIB.addDisp(MI->getOperand(i), LabelOffset);
17942 MIB.addOperand(MI->getOperand(i));
17944 MIB.setMemRefs(MMOBegin, MMOEnd);
17946 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
17947 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
17948 if (i == X86::AddrDisp)
17949 MIB.addDisp(MI->getOperand(i), SPOffset);
17951 MIB.addOperand(MI->getOperand(i));
17953 MIB.setMemRefs(MMOBegin, MMOEnd);
17955 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
17957 MI->eraseFromParent();
17961 // Replace 213-type (isel default) FMA3 instructions with 231-type for
17962 // accumulator loops. Writing back to the accumulator allows the coalescer
17963 // to remove extra copies in the loop.
17964 MachineBasicBlock *
17965 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
17966 MachineBasicBlock *MBB) const {
17967 MachineOperand &AddendOp = MI->getOperand(3);
17969 // Bail out early if the addend isn't a register - we can't switch these.
17970 if (!AddendOp.isReg())
17973 MachineFunction &MF = *MBB->getParent();
17974 MachineRegisterInfo &MRI = MF.getRegInfo();
17976 // Check whether the addend is defined by a PHI:
17977 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
17978 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
17979 if (!AddendDef.isPHI())
17982 // Look for the following pattern:
17984 // %addend = phi [%entry, 0], [%loop, %result]
17986 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
17990 // %addend = phi [%entry, 0], [%loop, %result]
17992 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
17994 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
17995 assert(AddendDef.getOperand(i).isReg());
17996 MachineOperand PHISrcOp = AddendDef.getOperand(i);
17997 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
17998 if (&PHISrcInst == MI) {
17999 // Found a matching instruction.
18000 unsigned NewFMAOpc = 0;
18001 switch (MI->getOpcode()) {
18002 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
18003 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
18004 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
18005 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
18006 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
18007 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
18008 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
18009 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
18010 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
18011 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
18012 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
18013 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
18014 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
18015 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
18016 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
18017 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
18018 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
18019 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
18020 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
18021 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
18022 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
18023 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
18024 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
18025 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
18026 default: llvm_unreachable("Unrecognized FMA variant.");
18029 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
18030 MachineInstrBuilder MIB =
18031 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
18032 .addOperand(MI->getOperand(0))
18033 .addOperand(MI->getOperand(3))
18034 .addOperand(MI->getOperand(2))
18035 .addOperand(MI->getOperand(1));
18036 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
18037 MI->eraseFromParent();
18044 MachineBasicBlock *
18045 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
18046 MachineBasicBlock *BB) const {
18047 switch (MI->getOpcode()) {
18048 default: llvm_unreachable("Unexpected instr type to insert");
18049 case X86::TAILJMPd64:
18050 case X86::TAILJMPr64:
18051 case X86::TAILJMPm64:
18052 llvm_unreachable("TAILJMP64 would not be touched here.");
18053 case X86::TCRETURNdi64:
18054 case X86::TCRETURNri64:
18055 case X86::TCRETURNmi64:
18057 case X86::WIN_ALLOCA:
18058 return EmitLoweredWinAlloca(MI, BB);
18059 case X86::SEG_ALLOCA_32:
18060 return EmitLoweredSegAlloca(MI, BB, false);
18061 case X86::SEG_ALLOCA_64:
18062 return EmitLoweredSegAlloca(MI, BB, true);
18063 case X86::TLSCall_32:
18064 case X86::TLSCall_64:
18065 return EmitLoweredTLSCall(MI, BB);
18066 case X86::CMOV_GR8:
18067 case X86::CMOV_FR32:
18068 case X86::CMOV_FR64:
18069 case X86::CMOV_V4F32:
18070 case X86::CMOV_V2F64:
18071 case X86::CMOV_V2I64:
18072 case X86::CMOV_V8F32:
18073 case X86::CMOV_V4F64:
18074 case X86::CMOV_V4I64:
18075 case X86::CMOV_V16F32:
18076 case X86::CMOV_V8F64:
18077 case X86::CMOV_V8I64:
18078 case X86::CMOV_GR16:
18079 case X86::CMOV_GR32:
18080 case X86::CMOV_RFP32:
18081 case X86::CMOV_RFP64:
18082 case X86::CMOV_RFP80:
18083 return EmitLoweredSelect(MI, BB);
18085 case X86::FP32_TO_INT16_IN_MEM:
18086 case X86::FP32_TO_INT32_IN_MEM:
18087 case X86::FP32_TO_INT64_IN_MEM:
18088 case X86::FP64_TO_INT16_IN_MEM:
18089 case X86::FP64_TO_INT32_IN_MEM:
18090 case X86::FP64_TO_INT64_IN_MEM:
18091 case X86::FP80_TO_INT16_IN_MEM:
18092 case X86::FP80_TO_INT32_IN_MEM:
18093 case X86::FP80_TO_INT64_IN_MEM: {
18094 MachineFunction *F = BB->getParent();
18095 const TargetInstrInfo *TII = F->getTarget().getInstrInfo();
18096 DebugLoc DL = MI->getDebugLoc();
18098 // Change the floating point control register to use "round towards zero"
18099 // mode when truncating to an integer value.
18100 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
18101 addFrameReference(BuildMI(*BB, MI, DL,
18102 TII->get(X86::FNSTCW16m)), CWFrameIdx);
18104 // Load the old value of the high byte of the control word...
18106 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
18107 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
18110 // Set the high part to be round to zero...
18111 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
18114 // Reload the modified control word now...
18115 addFrameReference(BuildMI(*BB, MI, DL,
18116 TII->get(X86::FLDCW16m)), CWFrameIdx);
18118 // Restore the memory image of control word to original value
18119 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
18122 // Get the X86 opcode to use.
18124 switch (MI->getOpcode()) {
18125 default: llvm_unreachable("illegal opcode!");
18126 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
18127 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
18128 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
18129 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
18130 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
18131 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
18132 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
18133 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
18134 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
18138 MachineOperand &Op = MI->getOperand(0);
18140 AM.BaseType = X86AddressMode::RegBase;
18141 AM.Base.Reg = Op.getReg();
18143 AM.BaseType = X86AddressMode::FrameIndexBase;
18144 AM.Base.FrameIndex = Op.getIndex();
18146 Op = MI->getOperand(1);
18148 AM.Scale = Op.getImm();
18149 Op = MI->getOperand(2);
18151 AM.IndexReg = Op.getImm();
18152 Op = MI->getOperand(3);
18153 if (Op.isGlobal()) {
18154 AM.GV = Op.getGlobal();
18156 AM.Disp = Op.getImm();
18158 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
18159 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
18161 // Reload the original control word now.
18162 addFrameReference(BuildMI(*BB, MI, DL,
18163 TII->get(X86::FLDCW16m)), CWFrameIdx);
18165 MI->eraseFromParent(); // The pseudo instruction is gone now.
18168 // String/text processing lowering.
18169 case X86::PCMPISTRM128REG:
18170 case X86::VPCMPISTRM128REG:
18171 case X86::PCMPISTRM128MEM:
18172 case X86::VPCMPISTRM128MEM:
18173 case X86::PCMPESTRM128REG:
18174 case X86::VPCMPESTRM128REG:
18175 case X86::PCMPESTRM128MEM:
18176 case X86::VPCMPESTRM128MEM:
18177 assert(Subtarget->hasSSE42() &&
18178 "Target must have SSE4.2 or AVX features enabled");
18179 return EmitPCMPSTRM(MI, BB, BB->getParent()->getTarget().getInstrInfo());
18181 // String/text processing lowering.
18182 case X86::PCMPISTRIREG:
18183 case X86::VPCMPISTRIREG:
18184 case X86::PCMPISTRIMEM:
18185 case X86::VPCMPISTRIMEM:
18186 case X86::PCMPESTRIREG:
18187 case X86::VPCMPESTRIREG:
18188 case X86::PCMPESTRIMEM:
18189 case X86::VPCMPESTRIMEM:
18190 assert(Subtarget->hasSSE42() &&
18191 "Target must have SSE4.2 or AVX features enabled");
18192 return EmitPCMPSTRI(MI, BB, BB->getParent()->getTarget().getInstrInfo());
18194 // Thread synchronization.
18196 return EmitMonitor(MI, BB, BB->getParent()->getTarget().getInstrInfo(), Subtarget);
18200 return EmitXBegin(MI, BB, BB->getParent()->getTarget().getInstrInfo());
18202 case X86::VASTART_SAVE_XMM_REGS:
18203 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
18205 case X86::VAARG_64:
18206 return EmitVAARG64WithCustomInserter(MI, BB);
18208 case X86::EH_SjLj_SetJmp32:
18209 case X86::EH_SjLj_SetJmp64:
18210 return emitEHSjLjSetJmp(MI, BB);
18212 case X86::EH_SjLj_LongJmp32:
18213 case X86::EH_SjLj_LongJmp64:
18214 return emitEHSjLjLongJmp(MI, BB);
18216 case TargetOpcode::STACKMAP:
18217 case TargetOpcode::PATCHPOINT:
18218 return emitPatchPoint(MI, BB);
18220 case X86::VFMADDPDr213r:
18221 case X86::VFMADDPSr213r:
18222 case X86::VFMADDSDr213r:
18223 case X86::VFMADDSSr213r:
18224 case X86::VFMSUBPDr213r:
18225 case X86::VFMSUBPSr213r:
18226 case X86::VFMSUBSDr213r:
18227 case X86::VFMSUBSSr213r:
18228 case X86::VFNMADDPDr213r:
18229 case X86::VFNMADDPSr213r:
18230 case X86::VFNMADDSDr213r:
18231 case X86::VFNMADDSSr213r:
18232 case X86::VFNMSUBPDr213r:
18233 case X86::VFNMSUBPSr213r:
18234 case X86::VFNMSUBSDr213r:
18235 case X86::VFNMSUBSSr213r:
18236 case X86::VFMADDPDr213rY:
18237 case X86::VFMADDPSr213rY:
18238 case X86::VFMSUBPDr213rY:
18239 case X86::VFMSUBPSr213rY:
18240 case X86::VFNMADDPDr213rY:
18241 case X86::VFNMADDPSr213rY:
18242 case X86::VFNMSUBPDr213rY:
18243 case X86::VFNMSUBPSr213rY:
18244 return emitFMA3Instr(MI, BB);
18248 //===----------------------------------------------------------------------===//
18249 // X86 Optimization Hooks
18250 //===----------------------------------------------------------------------===//
18252 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
18255 const SelectionDAG &DAG,
18256 unsigned Depth) const {
18257 unsigned BitWidth = KnownZero.getBitWidth();
18258 unsigned Opc = Op.getOpcode();
18259 assert((Opc >= ISD::BUILTIN_OP_END ||
18260 Opc == ISD::INTRINSIC_WO_CHAIN ||
18261 Opc == ISD::INTRINSIC_W_CHAIN ||
18262 Opc == ISD::INTRINSIC_VOID) &&
18263 "Should use MaskedValueIsZero if you don't know whether Op"
18264 " is a target node!");
18266 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
18280 // These nodes' second result is a boolean.
18281 if (Op.getResNo() == 0)
18284 case X86ISD::SETCC:
18285 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
18287 case ISD::INTRINSIC_WO_CHAIN: {
18288 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
18289 unsigned NumLoBits = 0;
18292 case Intrinsic::x86_sse_movmsk_ps:
18293 case Intrinsic::x86_avx_movmsk_ps_256:
18294 case Intrinsic::x86_sse2_movmsk_pd:
18295 case Intrinsic::x86_avx_movmsk_pd_256:
18296 case Intrinsic::x86_mmx_pmovmskb:
18297 case Intrinsic::x86_sse2_pmovmskb_128:
18298 case Intrinsic::x86_avx2_pmovmskb: {
18299 // High bits of movmskp{s|d}, pmovmskb are known zero.
18301 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
18302 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
18303 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
18304 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
18305 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
18306 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
18307 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
18308 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
18310 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
18319 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
18321 const SelectionDAG &,
18322 unsigned Depth) const {
18323 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
18324 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
18325 return Op.getValueType().getScalarType().getSizeInBits();
18331 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
18332 /// node is a GlobalAddress + offset.
18333 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
18334 const GlobalValue* &GA,
18335 int64_t &Offset) const {
18336 if (N->getOpcode() == X86ISD::Wrapper) {
18337 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
18338 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
18339 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
18343 return TargetLowering::isGAPlusOffset(N, GA, Offset);
18346 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
18347 /// same as extracting the high 128-bit part of 256-bit vector and then
18348 /// inserting the result into the low part of a new 256-bit vector
18349 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
18350 EVT VT = SVOp->getValueType(0);
18351 unsigned NumElems = VT.getVectorNumElements();
18353 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
18354 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
18355 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18356 SVOp->getMaskElt(j) >= 0)
18362 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
18363 /// same as extracting the low 128-bit part of 256-bit vector and then
18364 /// inserting the result into the high part of a new 256-bit vector
18365 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
18366 EVT VT = SVOp->getValueType(0);
18367 unsigned NumElems = VT.getVectorNumElements();
18369 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
18370 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
18371 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18372 SVOp->getMaskElt(j) >= 0)
18378 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
18379 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
18380 TargetLowering::DAGCombinerInfo &DCI,
18381 const X86Subtarget* Subtarget) {
18383 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
18384 SDValue V1 = SVOp->getOperand(0);
18385 SDValue V2 = SVOp->getOperand(1);
18386 EVT VT = SVOp->getValueType(0);
18387 unsigned NumElems = VT.getVectorNumElements();
18389 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
18390 V2.getOpcode() == ISD::CONCAT_VECTORS) {
18394 // V UNDEF BUILD_VECTOR UNDEF
18396 // CONCAT_VECTOR CONCAT_VECTOR
18399 // RESULT: V + zero extended
18401 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
18402 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
18403 V1.getOperand(1).getOpcode() != ISD::UNDEF)
18406 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
18409 // To match the shuffle mask, the first half of the mask should
18410 // be exactly the first vector, and all the rest a splat with the
18411 // first element of the second one.
18412 for (unsigned i = 0; i != NumElems/2; ++i)
18413 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
18414 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
18417 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
18418 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
18419 if (Ld->hasNUsesOfValue(1, 0)) {
18420 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
18421 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
18423 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
18425 Ld->getPointerInfo(),
18426 Ld->getAlignment(),
18427 false/*isVolatile*/, true/*ReadMem*/,
18428 false/*WriteMem*/);
18430 // Make sure the newly-created LOAD is in the same position as Ld in
18431 // terms of dependency. We create a TokenFactor for Ld and ResNode,
18432 // and update uses of Ld's output chain to use the TokenFactor.
18433 if (Ld->hasAnyUseOfValue(1)) {
18434 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18435 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
18436 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
18437 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
18438 SDValue(ResNode.getNode(), 1));
18441 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
18445 // Emit a zeroed vector and insert the desired subvector on its
18447 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18448 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
18449 return DCI.CombineTo(N, InsV);
18452 //===--------------------------------------------------------------------===//
18453 // Combine some shuffles into subvector extracts and inserts:
18456 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
18457 if (isShuffleHigh128VectorInsertLow(SVOp)) {
18458 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
18459 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
18460 return DCI.CombineTo(N, InsV);
18463 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
18464 if (isShuffleLow128VectorInsertHigh(SVOp)) {
18465 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
18466 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
18467 return DCI.CombineTo(N, InsV);
18473 /// \brief Get the PSHUF-style mask from PSHUF node.
18475 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
18476 /// PSHUF-style masks that can be reused with such instructions.
18477 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
18478 SmallVector<int, 4> Mask;
18480 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
18484 switch (N.getOpcode()) {
18485 case X86ISD::PSHUFD:
18487 case X86ISD::PSHUFLW:
18490 case X86ISD::PSHUFHW:
18491 Mask.erase(Mask.begin(), Mask.begin() + 4);
18492 for (int &M : Mask)
18496 llvm_unreachable("No valid shuffle instruction found!");
18500 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
18502 /// We walk up the chain and look for a combinable shuffle, skipping over
18503 /// shuffles that we could hoist this shuffle's transformation past without
18504 /// altering anything.
18505 static bool combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
18507 TargetLowering::DAGCombinerInfo &DCI) {
18508 assert(N.getOpcode() == X86ISD::PSHUFD &&
18509 "Called with something other than an x86 128-bit half shuffle!");
18512 // Walk up a single-use chain looking for a combinable shuffle.
18513 SDValue V = N.getOperand(0);
18514 for (; V.hasOneUse(); V = V.getOperand(0)) {
18515 switch (V.getOpcode()) {
18517 return false; // Nothing combined!
18520 // Skip bitcasts as we always know the type for the target specific
18524 case X86ISD::PSHUFD:
18525 // Found another dword shuffle.
18528 case X86ISD::PSHUFLW:
18529 // Check that the low words (being shuffled) are the identity in the
18530 // dword shuffle, and the high words are self-contained.
18531 if (Mask[0] != 0 || Mask[1] != 1 ||
18532 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
18537 case X86ISD::PSHUFHW:
18538 // Check that the high words (being shuffled) are the identity in the
18539 // dword shuffle, and the low words are self-contained.
18540 if (Mask[2] != 2 || Mask[3] != 3 ||
18541 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
18546 case X86ISD::UNPCKL:
18547 case X86ISD::UNPCKH:
18548 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
18549 // shuffle into a preceding word shuffle.
18550 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
18553 // Search for a half-shuffle which we can combine with.
18554 unsigned CombineOp =
18555 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
18556 if (V.getOperand(0) != V.getOperand(1) ||
18557 !V->isOnlyUserOf(V.getOperand(0).getNode()))
18559 V = V.getOperand(0);
18561 switch (V.getOpcode()) {
18563 return false; // Nothing to combine.
18565 case X86ISD::PSHUFLW:
18566 case X86ISD::PSHUFHW:
18567 if (V.getOpcode() == CombineOp)
18572 V = V.getOperand(0);
18576 } while (V.hasOneUse());
18579 // Break out of the loop if we break out of the switch.
18583 if (!V.hasOneUse())
18584 // We fell out of the loop without finding a viable combining instruction.
18587 // Record the old value to use in RAUW-ing.
18590 // Merge this node's mask and our incoming mask.
18591 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
18592 for (int &M : Mask)
18594 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
18595 getV4X86ShuffleImm8ForMask(Mask, DAG));
18597 // It is possible that one of the combinable shuffles was completely absorbed
18598 // by the other, just replace it and revisit all users in that case.
18599 if (Old.getNode() == V.getNode()) {
18600 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo=*/true);
18604 // Replace N with its operand as we're going to combine that shuffle away.
18605 DAG.ReplaceAllUsesWith(N, N.getOperand(0));
18607 // Replace the combinable shuffle with the combined one, updating all users
18608 // so that we re-evaluate the chain here.
18609 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
18613 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
18615 /// We walk up the chain, skipping shuffles of the other half and looking
18616 /// through shuffles which switch halves trying to find a shuffle of the same
18617 /// pair of dwords.
18618 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
18620 TargetLowering::DAGCombinerInfo &DCI) {
18622 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
18623 "Called with something other than an x86 128-bit half shuffle!");
18625 unsigned CombineOpcode = N.getOpcode();
18627 // Walk up a single-use chain looking for a combinable shuffle.
18628 SDValue V = N.getOperand(0);
18629 for (; V.hasOneUse(); V = V.getOperand(0)) {
18630 switch (V.getOpcode()) {
18632 return false; // Nothing combined!
18635 // Skip bitcasts as we always know the type for the target specific
18639 case X86ISD::PSHUFLW:
18640 case X86ISD::PSHUFHW:
18641 if (V.getOpcode() == CombineOpcode)
18644 // Other-half shuffles are no-ops.
18647 case X86ISD::PSHUFD: {
18648 // We can only handle pshufd if the half we are combining either stays in
18649 // its half, or switches to the other half. Bail if one of these isn't
18651 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
18652 int DOffset = CombineOpcode == X86ISD::PSHUFLW ? 0 : 2;
18653 if (!((VMask[DOffset + 0] < 2 && VMask[DOffset + 1] < 2) ||
18654 (VMask[DOffset + 0] >= 2 && VMask[DOffset + 1] >= 2)))
18657 // Map the mask through the pshufd and keep walking up the chain.
18658 for (int i = 0; i < 4; ++i)
18659 Mask[i] = 2 * (VMask[DOffset + Mask[i] / 2] % 2) + Mask[i] % 2;
18661 // Switch halves if the pshufd does.
18663 VMask[DOffset + Mask[0] / 2] < 2 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
18667 // Break out of the loop if we break out of the switch.
18671 if (!V.hasOneUse())
18672 // We fell out of the loop without finding a viable combining instruction.
18675 // Record the old value to use in RAUW-ing.
18678 // Merge this node's mask and our incoming mask (adjusted to account for all
18679 // the pshufd instructions encountered).
18680 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
18681 for (int &M : Mask)
18683 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
18684 getV4X86ShuffleImm8ForMask(Mask, DAG));
18686 // Replace N with its operand as we're going to combine that shuffle away.
18687 DAG.ReplaceAllUsesWith(N, N.getOperand(0));
18689 // Replace the combinable shuffle with the combined one, updating all users
18690 // so that we re-evaluate the chain here.
18691 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
18695 /// \brief Try to combine x86 target specific shuffles.
18696 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
18697 TargetLowering::DAGCombinerInfo &DCI,
18698 const X86Subtarget *Subtarget) {
18700 MVT VT = N.getSimpleValueType();
18701 SmallVector<int, 4> Mask;
18703 switch (N.getOpcode()) {
18704 case X86ISD::PSHUFD:
18705 case X86ISD::PSHUFLW:
18706 case X86ISD::PSHUFHW:
18707 Mask = getPSHUFShuffleMask(N);
18708 assert(Mask.size() == 4);
18714 // Nuke no-op shuffles that show up after combining.
18715 if (isNoopShuffleMask(Mask))
18716 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
18718 // Look for simplifications involving one or two shuffle instructions.
18719 SDValue V = N.getOperand(0);
18720 switch (N.getOpcode()) {
18723 case X86ISD::PSHUFLW:
18724 case X86ISD::PSHUFHW:
18725 assert(VT == MVT::v8i16);
18728 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
18729 return SDValue(); // We combined away this shuffle, so we're done.
18731 // See if this reduces to a PSHUFD which is no more expensive and can
18732 // combine with more operations.
18733 if (Mask[0] % 2 == 0 && Mask[2] % 2 == 0 &&
18734 areAdjacentMasksSequential(Mask)) {
18735 int DMask[] = {-1, -1, -1, -1};
18736 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
18737 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
18738 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
18739 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
18740 DCI.AddToWorklist(V.getNode());
18741 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
18742 getV4X86ShuffleImm8ForMask(DMask, DAG));
18743 DCI.AddToWorklist(V.getNode());
18744 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
18747 // Look for shuffle patterns which can be implemented as a single unpack.
18748 // FIXME: This doesn't handle the location of the PSHUFD generically, and
18749 // only works when we have a PSHUFD followed by two half-shuffles.
18750 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
18751 (V.getOpcode() == X86ISD::PSHUFLW ||
18752 V.getOpcode() == X86ISD::PSHUFHW) &&
18753 V.getOpcode() != N.getOpcode() &&
18755 SDValue D = V.getOperand(0);
18756 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
18757 D = D.getOperand(0);
18758 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
18759 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
18760 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
18761 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
18762 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
18764 for (int i = 0; i < 4; ++i) {
18765 WordMask[i + NOffset] = Mask[i] + NOffset;
18766 WordMask[i + VOffset] = VMask[i] + VOffset;
18768 // Map the word mask through the DWord mask.
18770 for (int i = 0; i < 8; ++i)
18771 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
18772 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
18773 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
18774 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
18775 std::begin(UnpackLoMask)) ||
18776 std::equal(std::begin(MappedMask), std::end(MappedMask),
18777 std::begin(UnpackHiMask))) {
18778 // We can replace all three shuffles with an unpack.
18779 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
18780 DCI.AddToWorklist(V.getNode());
18781 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
18783 DL, MVT::v8i16, V, V);
18790 case X86ISD::PSHUFD:
18791 if (combineRedundantDWordShuffle(N, Mask, DAG, DCI))
18792 return SDValue(); // We combined away this shuffle.
18800 /// PerformShuffleCombine - Performs several different shuffle combines.
18801 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
18802 TargetLowering::DAGCombinerInfo &DCI,
18803 const X86Subtarget *Subtarget) {
18805 SDValue N0 = N->getOperand(0);
18806 SDValue N1 = N->getOperand(1);
18807 EVT VT = N->getValueType(0);
18809 // Don't create instructions with illegal types after legalize types has run.
18810 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18811 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
18814 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
18815 if (Subtarget->hasFp256() && VT.is256BitVector() &&
18816 N->getOpcode() == ISD::VECTOR_SHUFFLE)
18817 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
18819 // During Type Legalization, when promoting illegal vector types,
18820 // the backend might introduce new shuffle dag nodes and bitcasts.
18822 // This code performs the following transformation:
18823 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
18824 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
18826 // We do this only if both the bitcast and the BINOP dag nodes have
18827 // one use. Also, perform this transformation only if the new binary
18828 // operation is legal. This is to avoid introducing dag nodes that
18829 // potentially need to be further expanded (or custom lowered) into a
18830 // less optimal sequence of dag nodes.
18831 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
18832 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
18833 N0.getOpcode() == ISD::BITCAST) {
18834 SDValue BC0 = N0.getOperand(0);
18835 EVT SVT = BC0.getValueType();
18836 unsigned Opcode = BC0.getOpcode();
18837 unsigned NumElts = VT.getVectorNumElements();
18839 if (BC0.hasOneUse() && SVT.isVector() &&
18840 SVT.getVectorNumElements() * 2 == NumElts &&
18841 TLI.isOperationLegal(Opcode, VT)) {
18842 bool CanFold = false;
18854 unsigned SVTNumElts = SVT.getVectorNumElements();
18855 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
18856 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
18857 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
18858 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
18859 CanFold = SVOp->getMaskElt(i) < 0;
18862 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
18863 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
18864 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
18865 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
18870 // Only handle 128 wide vector from here on.
18871 if (!VT.is128BitVector())
18874 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
18875 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
18876 // consecutive, non-overlapping, and in the right order.
18877 SmallVector<SDValue, 16> Elts;
18878 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
18879 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
18881 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
18885 if (isTargetShuffle(N->getOpcode())) {
18887 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
18888 if (Shuffle.getNode())
18895 /// PerformTruncateCombine - Converts truncate operation to
18896 /// a sequence of vector shuffle operations.
18897 /// It is possible when we truncate 256-bit vector to 128-bit vector
18898 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
18899 TargetLowering::DAGCombinerInfo &DCI,
18900 const X86Subtarget *Subtarget) {
18904 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
18905 /// specific shuffle of a load can be folded into a single element load.
18906 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
18907 /// shuffles have been customed lowered so we need to handle those here.
18908 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
18909 TargetLowering::DAGCombinerInfo &DCI) {
18910 if (DCI.isBeforeLegalizeOps())
18913 SDValue InVec = N->getOperand(0);
18914 SDValue EltNo = N->getOperand(1);
18916 if (!isa<ConstantSDNode>(EltNo))
18919 EVT VT = InVec.getValueType();
18921 bool HasShuffleIntoBitcast = false;
18922 if (InVec.getOpcode() == ISD::BITCAST) {
18923 // Don't duplicate a load with other uses.
18924 if (!InVec.hasOneUse())
18926 EVT BCVT = InVec.getOperand(0).getValueType();
18927 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
18929 InVec = InVec.getOperand(0);
18930 HasShuffleIntoBitcast = true;
18933 if (!isTargetShuffle(InVec.getOpcode()))
18936 // Don't duplicate a load with other uses.
18937 if (!InVec.hasOneUse())
18940 SmallVector<int, 16> ShuffleMask;
18942 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
18946 // Select the input vector, guarding against out of range extract vector.
18947 unsigned NumElems = VT.getVectorNumElements();
18948 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
18949 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
18950 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
18951 : InVec.getOperand(1);
18953 // If inputs to shuffle are the same for both ops, then allow 2 uses
18954 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
18956 if (LdNode.getOpcode() == ISD::BITCAST) {
18957 // Don't duplicate a load with other uses.
18958 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
18961 AllowedUses = 1; // only allow 1 load use if we have a bitcast
18962 LdNode = LdNode.getOperand(0);
18965 if (!ISD::isNormalLoad(LdNode.getNode()))
18968 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
18970 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
18973 if (HasShuffleIntoBitcast) {
18974 // If there's a bitcast before the shuffle, check if the load type and
18975 // alignment is valid.
18976 unsigned Align = LN0->getAlignment();
18977 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18978 unsigned NewAlign = TLI.getDataLayout()->
18979 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
18981 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
18985 // All checks match so transform back to vector_shuffle so that DAG combiner
18986 // can finish the job
18989 // Create shuffle node taking into account the case that its a unary shuffle
18990 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
18991 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
18992 InVec.getOperand(0), Shuffle,
18994 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
18995 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
18999 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
19000 /// generation and convert it from being a bunch of shuffles and extracts
19001 /// to a simple store and scalar loads to extract the elements.
19002 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
19003 TargetLowering::DAGCombinerInfo &DCI) {
19004 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
19005 if (NewOp.getNode())
19008 SDValue InputVector = N->getOperand(0);
19010 // Detect whether we are trying to convert from mmx to i32 and the bitcast
19011 // from mmx to v2i32 has a single usage.
19012 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
19013 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
19014 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
19015 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
19016 N->getValueType(0),
19017 InputVector.getNode()->getOperand(0));
19019 // Only operate on vectors of 4 elements, where the alternative shuffling
19020 // gets to be more expensive.
19021 if (InputVector.getValueType() != MVT::v4i32)
19024 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
19025 // single use which is a sign-extend or zero-extend, and all elements are
19027 SmallVector<SDNode *, 4> Uses;
19028 unsigned ExtractedElements = 0;
19029 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
19030 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
19031 if (UI.getUse().getResNo() != InputVector.getResNo())
19034 SDNode *Extract = *UI;
19035 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
19038 if (Extract->getValueType(0) != MVT::i32)
19040 if (!Extract->hasOneUse())
19042 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
19043 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
19045 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
19048 // Record which element was extracted.
19049 ExtractedElements |=
19050 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
19052 Uses.push_back(Extract);
19055 // If not all the elements were used, this may not be worthwhile.
19056 if (ExtractedElements != 15)
19059 // Ok, we've now decided to do the transformation.
19060 SDLoc dl(InputVector);
19062 // Store the value to a temporary stack slot.
19063 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
19064 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
19065 MachinePointerInfo(), false, false, 0);
19067 // Replace each use (extract) with a load of the appropriate element.
19068 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
19069 UE = Uses.end(); UI != UE; ++UI) {
19070 SDNode *Extract = *UI;
19072 // cOMpute the element's address.
19073 SDValue Idx = Extract->getOperand(1);
19075 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
19076 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
19077 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19078 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
19080 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
19081 StackPtr, OffsetVal);
19083 // Load the scalar.
19084 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
19085 ScalarAddr, MachinePointerInfo(),
19086 false, false, false, 0);
19088 // Replace the exact with the load.
19089 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
19092 // The replacement was made in place; don't return anything.
19096 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
19097 static std::pair<unsigned, bool>
19098 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
19099 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
19100 if (!VT.isVector())
19101 return std::make_pair(0, false);
19103 bool NeedSplit = false;
19104 switch (VT.getSimpleVT().SimpleTy) {
19105 default: return std::make_pair(0, false);
19109 if (!Subtarget->hasAVX2())
19111 if (!Subtarget->hasAVX())
19112 return std::make_pair(0, false);
19117 if (!Subtarget->hasSSE2())
19118 return std::make_pair(0, false);
19121 // SSE2 has only a small subset of the operations.
19122 bool hasUnsigned = Subtarget->hasSSE41() ||
19123 (Subtarget->hasSSE2() && VT == MVT::v16i8);
19124 bool hasSigned = Subtarget->hasSSE41() ||
19125 (Subtarget->hasSSE2() && VT == MVT::v8i16);
19127 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19130 // Check for x CC y ? x : y.
19131 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19132 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19137 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
19140 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
19143 Opc = hasSigned ? X86ISD::SMIN : 0; break;
19146 Opc = hasSigned ? X86ISD::SMAX : 0; break;
19148 // Check for x CC y ? y : x -- a min/max with reversed arms.
19149 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
19150 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
19155 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
19158 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
19161 Opc = hasSigned ? X86ISD::SMAX : 0; break;
19164 Opc = hasSigned ? X86ISD::SMIN : 0; break;
19168 return std::make_pair(Opc, NeedSplit);
19172 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
19173 const X86Subtarget *Subtarget) {
19175 SDValue Cond = N->getOperand(0);
19176 SDValue LHS = N->getOperand(1);
19177 SDValue RHS = N->getOperand(2);
19179 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
19180 SDValue CondSrc = Cond->getOperand(0);
19181 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
19182 Cond = CondSrc->getOperand(0);
19185 MVT VT = N->getSimpleValueType(0);
19186 MVT EltVT = VT.getVectorElementType();
19187 unsigned NumElems = VT.getVectorNumElements();
19188 // There is no blend with immediate in AVX-512.
19189 if (VT.is512BitVector())
19192 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
19194 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
19197 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
19200 unsigned MaskValue = 0;
19201 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
19204 SmallVector<int, 8> ShuffleMask(NumElems, -1);
19205 for (unsigned i = 0; i < NumElems; ++i) {
19206 // Be sure we emit undef where we can.
19207 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
19208 ShuffleMask[i] = -1;
19210 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
19213 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
19216 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
19218 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
19219 TargetLowering::DAGCombinerInfo &DCI,
19220 const X86Subtarget *Subtarget) {
19222 SDValue Cond = N->getOperand(0);
19223 // Get the LHS/RHS of the select.
19224 SDValue LHS = N->getOperand(1);
19225 SDValue RHS = N->getOperand(2);
19226 EVT VT = LHS.getValueType();
19227 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19229 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
19230 // instructions match the semantics of the common C idiom x<y?x:y but not
19231 // x<=y?x:y, because of how they handle negative zero (which can be
19232 // ignored in unsafe-math mode).
19233 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
19234 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
19235 (Subtarget->hasSSE2() ||
19236 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
19237 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19239 unsigned Opcode = 0;
19240 // Check for x CC y ? x : y.
19241 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19242 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19246 // Converting this to a min would handle NaNs incorrectly, and swapping
19247 // the operands would cause it to handle comparisons between positive
19248 // and negative zero incorrectly.
19249 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
19250 if (!DAG.getTarget().Options.UnsafeFPMath &&
19251 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
19253 std::swap(LHS, RHS);
19255 Opcode = X86ISD::FMIN;
19258 // Converting this to a min would handle comparisons between positive
19259 // and negative zero incorrectly.
19260 if (!DAG.getTarget().Options.UnsafeFPMath &&
19261 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
19263 Opcode = X86ISD::FMIN;
19266 // Converting this to a min would handle both negative zeros and NaNs
19267 // incorrectly, but we can swap the operands to fix both.
19268 std::swap(LHS, RHS);
19272 Opcode = X86ISD::FMIN;
19276 // Converting this to a max would handle comparisons between positive
19277 // and negative zero incorrectly.
19278 if (!DAG.getTarget().Options.UnsafeFPMath &&
19279 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
19281 Opcode = X86ISD::FMAX;
19284 // Converting this to a max would handle NaNs incorrectly, and swapping
19285 // the operands would cause it to handle comparisons between positive
19286 // and negative zero incorrectly.
19287 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
19288 if (!DAG.getTarget().Options.UnsafeFPMath &&
19289 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
19291 std::swap(LHS, RHS);
19293 Opcode = X86ISD::FMAX;
19296 // Converting this to a max would handle both negative zeros and NaNs
19297 // incorrectly, but we can swap the operands to fix both.
19298 std::swap(LHS, RHS);
19302 Opcode = X86ISD::FMAX;
19305 // Check for x CC y ? y : x -- a min/max with reversed arms.
19306 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
19307 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
19311 // Converting this to a min would handle comparisons between positive
19312 // and negative zero incorrectly, and swapping the operands would
19313 // cause it to handle NaNs incorrectly.
19314 if (!DAG.getTarget().Options.UnsafeFPMath &&
19315 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
19316 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
19318 std::swap(LHS, RHS);
19320 Opcode = X86ISD::FMIN;
19323 // Converting this to a min would handle NaNs incorrectly.
19324 if (!DAG.getTarget().Options.UnsafeFPMath &&
19325 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
19327 Opcode = X86ISD::FMIN;
19330 // Converting this to a min would handle both negative zeros and NaNs
19331 // incorrectly, but we can swap the operands to fix both.
19332 std::swap(LHS, RHS);
19336 Opcode = X86ISD::FMIN;
19340 // Converting this to a max would handle NaNs incorrectly.
19341 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
19343 Opcode = X86ISD::FMAX;
19346 // Converting this to a max would handle comparisons between positive
19347 // and negative zero incorrectly, and swapping the operands would
19348 // cause it to handle NaNs incorrectly.
19349 if (!DAG.getTarget().Options.UnsafeFPMath &&
19350 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
19351 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
19353 std::swap(LHS, RHS);
19355 Opcode = X86ISD::FMAX;
19358 // Converting this to a max would handle both negative zeros and NaNs
19359 // incorrectly, but we can swap the operands to fix both.
19360 std::swap(LHS, RHS);
19364 Opcode = X86ISD::FMAX;
19370 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
19373 EVT CondVT = Cond.getValueType();
19374 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
19375 CondVT.getVectorElementType() == MVT::i1) {
19376 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
19377 // lowering on AVX-512. In this case we convert it to
19378 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
19379 // The same situation for all 128 and 256-bit vectors of i8 and i16
19380 EVT OpVT = LHS.getValueType();
19381 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
19382 (OpVT.getVectorElementType() == MVT::i8 ||
19383 OpVT.getVectorElementType() == MVT::i16)) {
19384 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
19385 DCI.AddToWorklist(Cond.getNode());
19386 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
19389 // If this is a select between two integer constants, try to do some
19391 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
19392 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
19393 // Don't do this for crazy integer types.
19394 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
19395 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
19396 // so that TrueC (the true value) is larger than FalseC.
19397 bool NeedsCondInvert = false;
19399 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
19400 // Efficiently invertible.
19401 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
19402 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
19403 isa<ConstantSDNode>(Cond.getOperand(1))))) {
19404 NeedsCondInvert = true;
19405 std::swap(TrueC, FalseC);
19408 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
19409 if (FalseC->getAPIntValue() == 0 &&
19410 TrueC->getAPIntValue().isPowerOf2()) {
19411 if (NeedsCondInvert) // Invert the condition if needed.
19412 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
19413 DAG.getConstant(1, Cond.getValueType()));
19415 // Zero extend the condition if needed.
19416 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
19418 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
19419 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
19420 DAG.getConstant(ShAmt, MVT::i8));
19423 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
19424 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
19425 if (NeedsCondInvert) // Invert the condition if needed.
19426 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
19427 DAG.getConstant(1, Cond.getValueType()));
19429 // Zero extend the condition if needed.
19430 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
19431 FalseC->getValueType(0), Cond);
19432 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
19433 SDValue(FalseC, 0));
19436 // Optimize cases that will turn into an LEA instruction. This requires
19437 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
19438 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
19439 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
19440 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
19442 bool isFastMultiplier = false;
19444 switch ((unsigned char)Diff) {
19446 case 1: // result = add base, cond
19447 case 2: // result = lea base( , cond*2)
19448 case 3: // result = lea base(cond, cond*2)
19449 case 4: // result = lea base( , cond*4)
19450 case 5: // result = lea base(cond, cond*4)
19451 case 8: // result = lea base( , cond*8)
19452 case 9: // result = lea base(cond, cond*8)
19453 isFastMultiplier = true;
19458 if (isFastMultiplier) {
19459 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
19460 if (NeedsCondInvert) // Invert the condition if needed.
19461 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
19462 DAG.getConstant(1, Cond.getValueType()));
19464 // Zero extend the condition if needed.
19465 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
19467 // Scale the condition by the difference.
19469 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
19470 DAG.getConstant(Diff, Cond.getValueType()));
19472 // Add the base if non-zero.
19473 if (FalseC->getAPIntValue() != 0)
19474 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
19475 SDValue(FalseC, 0));
19482 // Canonicalize max and min:
19483 // (x > y) ? x : y -> (x >= y) ? x : y
19484 // (x < y) ? x : y -> (x <= y) ? x : y
19485 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
19486 // the need for an extra compare
19487 // against zero. e.g.
19488 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
19490 // testl %edi, %edi
19492 // cmovgl %edi, %eax
19496 // cmovsl %eax, %edi
19497 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
19498 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19499 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19500 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19505 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
19506 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
19507 Cond.getOperand(0), Cond.getOperand(1), NewCC);
19508 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
19513 // Early exit check
19514 if (!TLI.isTypeLegal(VT))
19517 // Match VSELECTs into subs with unsigned saturation.
19518 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
19519 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
19520 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
19521 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
19522 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19524 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
19525 // left side invert the predicate to simplify logic below.
19527 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
19529 CC = ISD::getSetCCInverse(CC, true);
19530 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
19534 if (Other.getNode() && Other->getNumOperands() == 2 &&
19535 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
19536 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
19537 SDValue CondRHS = Cond->getOperand(1);
19539 // Look for a general sub with unsigned saturation first.
19540 // x >= y ? x-y : 0 --> subus x, y
19541 // x > y ? x-y : 0 --> subus x, y
19542 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
19543 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
19544 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
19546 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
19547 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
19548 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
19549 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
19550 // If the RHS is a constant we have to reverse the const
19551 // canonicalization.
19552 // x > C-1 ? x+-C : 0 --> subus x, C
19553 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
19554 CondRHSConst->getAPIntValue() ==
19555 (-OpRHSConst->getAPIntValue() - 1))
19556 return DAG.getNode(
19557 X86ISD::SUBUS, DL, VT, OpLHS,
19558 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
19560 // Another special case: If C was a sign bit, the sub has been
19561 // canonicalized into a xor.
19562 // FIXME: Would it be better to use computeKnownBits to determine
19563 // whether it's safe to decanonicalize the xor?
19564 // x s< 0 ? x^C : 0 --> subus x, C
19565 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
19566 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
19567 OpRHSConst->getAPIntValue().isSignBit())
19568 // Note that we have to rebuild the RHS constant here to ensure we
19569 // don't rely on particular values of undef lanes.
19570 return DAG.getNode(
19571 X86ISD::SUBUS, DL, VT, OpLHS,
19572 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
19577 // Try to match a min/max vector operation.
19578 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
19579 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
19580 unsigned Opc = ret.first;
19581 bool NeedSplit = ret.second;
19583 if (Opc && NeedSplit) {
19584 unsigned NumElems = VT.getVectorNumElements();
19585 // Extract the LHS vectors
19586 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
19587 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
19589 // Extract the RHS vectors
19590 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
19591 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
19593 // Create min/max for each subvector
19594 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
19595 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
19597 // Merge the result
19598 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
19600 return DAG.getNode(Opc, DL, VT, LHS, RHS);
19603 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
19604 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
19605 // Check if SETCC has already been promoted
19606 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
19607 // Check that condition value type matches vselect operand type
19610 assert(Cond.getValueType().isVector() &&
19611 "vector select expects a vector selector!");
19613 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
19614 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
19616 if (!TValIsAllOnes && !FValIsAllZeros) {
19617 // Try invert the condition if true value is not all 1s and false value
19619 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
19620 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
19622 if (TValIsAllZeros || FValIsAllOnes) {
19623 SDValue CC = Cond.getOperand(2);
19624 ISD::CondCode NewCC =
19625 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
19626 Cond.getOperand(0).getValueType().isInteger());
19627 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
19628 std::swap(LHS, RHS);
19629 TValIsAllOnes = FValIsAllOnes;
19630 FValIsAllZeros = TValIsAllZeros;
19634 if (TValIsAllOnes || FValIsAllZeros) {
19637 if (TValIsAllOnes && FValIsAllZeros)
19639 else if (TValIsAllOnes)
19640 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
19641 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
19642 else if (FValIsAllZeros)
19643 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
19644 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
19646 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
19650 // Try to fold this VSELECT into a MOVSS/MOVSD
19651 if (N->getOpcode() == ISD::VSELECT &&
19652 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
19653 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
19654 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
19655 bool CanFold = false;
19656 unsigned NumElems = Cond.getNumOperands();
19660 if (isZero(Cond.getOperand(0))) {
19663 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
19664 // fold (vselect <0,-1> -> (movsd A, B)
19665 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
19666 CanFold = isAllOnes(Cond.getOperand(i));
19667 } else if (isAllOnes(Cond.getOperand(0))) {
19671 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
19672 // fold (vselect <-1,0> -> (movsd B, A)
19673 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
19674 CanFold = isZero(Cond.getOperand(i));
19678 if (VT == MVT::v4i32 || VT == MVT::v4f32)
19679 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
19680 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
19683 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
19684 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
19685 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
19686 // (v2i64 (bitcast B)))))
19688 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
19689 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
19690 // (v2f64 (bitcast B)))))
19692 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
19693 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
19694 // (v2i64 (bitcast A)))))
19696 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
19697 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
19698 // (v2f64 (bitcast A)))))
19700 CanFold = (isZero(Cond.getOperand(0)) &&
19701 isZero(Cond.getOperand(1)) &&
19702 isAllOnes(Cond.getOperand(2)) &&
19703 isAllOnes(Cond.getOperand(3)));
19705 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
19706 isAllOnes(Cond.getOperand(1)) &&
19707 isZero(Cond.getOperand(2)) &&
19708 isZero(Cond.getOperand(3))) {
19710 std::swap(LHS, RHS);
19714 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
19715 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
19716 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
19717 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
19719 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
19725 // If we know that this node is legal then we know that it is going to be
19726 // matched by one of the SSE/AVX BLEND instructions. These instructions only
19727 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
19728 // to simplify previous instructions.
19729 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
19730 !DCI.isBeforeLegalize() &&
19731 // We explicitly check against v8i16 and v16i16 because, although
19732 // they're marked as Custom, they might only be legal when Cond is a
19733 // build_vector of constants. This will be taken care in a later
19735 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
19736 VT != MVT::v8i16)) {
19737 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
19739 // Don't optimize vector selects that map to mask-registers.
19743 // Check all uses of that condition operand to check whether it will be
19744 // consumed by non-BLEND instructions, which may depend on all bits are set
19746 for (SDNode::use_iterator I = Cond->use_begin(),
19747 E = Cond->use_end(); I != E; ++I)
19748 if (I->getOpcode() != ISD::VSELECT)
19749 // TODO: Add other opcodes eventually lowered into BLEND.
19752 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
19753 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
19755 APInt KnownZero, KnownOne;
19756 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
19757 DCI.isBeforeLegalizeOps());
19758 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
19759 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
19760 DCI.CommitTargetLoweringOpt(TLO);
19763 // We should generate an X86ISD::BLENDI from a vselect if its argument
19764 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
19765 // constants. This specific pattern gets generated when we split a
19766 // selector for a 512 bit vector in a machine without AVX512 (but with
19767 // 256-bit vectors), during legalization:
19769 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
19771 // Iff we find this pattern and the build_vectors are built from
19772 // constants, we translate the vselect into a shuffle_vector that we
19773 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
19774 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
19775 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
19776 if (Shuffle.getNode())
19783 // Check whether a boolean test is testing a boolean value generated by
19784 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
19787 // Simplify the following patterns:
19788 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
19789 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
19790 // to (Op EFLAGS Cond)
19792 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
19793 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
19794 // to (Op EFLAGS !Cond)
19796 // where Op could be BRCOND or CMOV.
19798 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
19799 // Quit if not CMP and SUB with its value result used.
19800 if (Cmp.getOpcode() != X86ISD::CMP &&
19801 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
19804 // Quit if not used as a boolean value.
19805 if (CC != X86::COND_E && CC != X86::COND_NE)
19808 // Check CMP operands. One of them should be 0 or 1 and the other should be
19809 // an SetCC or extended from it.
19810 SDValue Op1 = Cmp.getOperand(0);
19811 SDValue Op2 = Cmp.getOperand(1);
19814 const ConstantSDNode* C = nullptr;
19815 bool needOppositeCond = (CC == X86::COND_E);
19816 bool checkAgainstTrue = false; // Is it a comparison against 1?
19818 if ((C = dyn_cast<ConstantSDNode>(Op1)))
19820 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
19822 else // Quit if all operands are not constants.
19825 if (C->getZExtValue() == 1) {
19826 needOppositeCond = !needOppositeCond;
19827 checkAgainstTrue = true;
19828 } else if (C->getZExtValue() != 0)
19829 // Quit if the constant is neither 0 or 1.
19832 bool truncatedToBoolWithAnd = false;
19833 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
19834 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
19835 SetCC.getOpcode() == ISD::TRUNCATE ||
19836 SetCC.getOpcode() == ISD::AND) {
19837 if (SetCC.getOpcode() == ISD::AND) {
19839 ConstantSDNode *CS;
19840 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
19841 CS->getZExtValue() == 1)
19843 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
19844 CS->getZExtValue() == 1)
19848 SetCC = SetCC.getOperand(OpIdx);
19849 truncatedToBoolWithAnd = true;
19851 SetCC = SetCC.getOperand(0);
19854 switch (SetCC.getOpcode()) {
19855 case X86ISD::SETCC_CARRY:
19856 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
19857 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
19858 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
19859 // truncated to i1 using 'and'.
19860 if (checkAgainstTrue && !truncatedToBoolWithAnd)
19862 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
19863 "Invalid use of SETCC_CARRY!");
19865 case X86ISD::SETCC:
19866 // Set the condition code or opposite one if necessary.
19867 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
19868 if (needOppositeCond)
19869 CC = X86::GetOppositeBranchCondition(CC);
19870 return SetCC.getOperand(1);
19871 case X86ISD::CMOV: {
19872 // Check whether false/true value has canonical one, i.e. 0 or 1.
19873 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
19874 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
19875 // Quit if true value is not a constant.
19878 // Quit if false value is not a constant.
19880 SDValue Op = SetCC.getOperand(0);
19881 // Skip 'zext' or 'trunc' node.
19882 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
19883 Op.getOpcode() == ISD::TRUNCATE)
19884 Op = Op.getOperand(0);
19885 // A special case for rdrand/rdseed, where 0 is set if false cond is
19887 if ((Op.getOpcode() != X86ISD::RDRAND &&
19888 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
19891 // Quit if false value is not the constant 0 or 1.
19892 bool FValIsFalse = true;
19893 if (FVal && FVal->getZExtValue() != 0) {
19894 if (FVal->getZExtValue() != 1)
19896 // If FVal is 1, opposite cond is needed.
19897 needOppositeCond = !needOppositeCond;
19898 FValIsFalse = false;
19900 // Quit if TVal is not the constant opposite of FVal.
19901 if (FValIsFalse && TVal->getZExtValue() != 1)
19903 if (!FValIsFalse && TVal->getZExtValue() != 0)
19905 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
19906 if (needOppositeCond)
19907 CC = X86::GetOppositeBranchCondition(CC);
19908 return SetCC.getOperand(3);
19915 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
19916 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
19917 TargetLowering::DAGCombinerInfo &DCI,
19918 const X86Subtarget *Subtarget) {
19921 // If the flag operand isn't dead, don't touch this CMOV.
19922 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
19925 SDValue FalseOp = N->getOperand(0);
19926 SDValue TrueOp = N->getOperand(1);
19927 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
19928 SDValue Cond = N->getOperand(3);
19930 if (CC == X86::COND_E || CC == X86::COND_NE) {
19931 switch (Cond.getOpcode()) {
19935 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
19936 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
19937 return (CC == X86::COND_E) ? FalseOp : TrueOp;
19943 Flags = checkBoolTestSetCCCombine(Cond, CC);
19944 if (Flags.getNode() &&
19945 // Extra check as FCMOV only supports a subset of X86 cond.
19946 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
19947 SDValue Ops[] = { FalseOp, TrueOp,
19948 DAG.getConstant(CC, MVT::i8), Flags };
19949 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
19952 // If this is a select between two integer constants, try to do some
19953 // optimizations. Note that the operands are ordered the opposite of SELECT
19955 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
19956 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
19957 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
19958 // larger than FalseC (the false value).
19959 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
19960 CC = X86::GetOppositeBranchCondition(CC);
19961 std::swap(TrueC, FalseC);
19962 std::swap(TrueOp, FalseOp);
19965 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
19966 // This is efficient for any integer data type (including i8/i16) and
19968 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
19969 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19970 DAG.getConstant(CC, MVT::i8), Cond);
19972 // Zero extend the condition if needed.
19973 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
19975 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
19976 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
19977 DAG.getConstant(ShAmt, MVT::i8));
19978 if (N->getNumValues() == 2) // Dead flag value?
19979 return DCI.CombineTo(N, Cond, SDValue());
19983 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
19984 // for any integer data type, including i8/i16.
19985 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
19986 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19987 DAG.getConstant(CC, MVT::i8), Cond);
19989 // Zero extend the condition if needed.
19990 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
19991 FalseC->getValueType(0), Cond);
19992 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
19993 SDValue(FalseC, 0));
19995 if (N->getNumValues() == 2) // Dead flag value?
19996 return DCI.CombineTo(N, Cond, SDValue());
20000 // Optimize cases that will turn into an LEA instruction. This requires
20001 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20002 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20003 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20004 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20006 bool isFastMultiplier = false;
20008 switch ((unsigned char)Diff) {
20010 case 1: // result = add base, cond
20011 case 2: // result = lea base( , cond*2)
20012 case 3: // result = lea base(cond, cond*2)
20013 case 4: // result = lea base( , cond*4)
20014 case 5: // result = lea base(cond, cond*4)
20015 case 8: // result = lea base( , cond*8)
20016 case 9: // result = lea base(cond, cond*8)
20017 isFastMultiplier = true;
20022 if (isFastMultiplier) {
20023 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20024 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
20025 DAG.getConstant(CC, MVT::i8), Cond);
20026 // Zero extend the condition if needed.
20027 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
20029 // Scale the condition by the difference.
20031 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
20032 DAG.getConstant(Diff, Cond.getValueType()));
20034 // Add the base if non-zero.
20035 if (FalseC->getAPIntValue() != 0)
20036 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20037 SDValue(FalseC, 0));
20038 if (N->getNumValues() == 2) // Dead flag value?
20039 return DCI.CombineTo(N, Cond, SDValue());
20046 // Handle these cases:
20047 // (select (x != c), e, c) -> select (x != c), e, x),
20048 // (select (x == c), c, e) -> select (x == c), x, e)
20049 // where the c is an integer constant, and the "select" is the combination
20050 // of CMOV and CMP.
20052 // The rationale for this change is that the conditional-move from a constant
20053 // needs two instructions, however, conditional-move from a register needs
20054 // only one instruction.
20056 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
20057 // some instruction-combining opportunities. This opt needs to be
20058 // postponed as late as possible.
20060 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
20061 // the DCI.xxxx conditions are provided to postpone the optimization as
20062 // late as possible.
20064 ConstantSDNode *CmpAgainst = nullptr;
20065 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
20066 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
20067 !isa<ConstantSDNode>(Cond.getOperand(0))) {
20069 if (CC == X86::COND_NE &&
20070 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
20071 CC = X86::GetOppositeBranchCondition(CC);
20072 std::swap(TrueOp, FalseOp);
20075 if (CC == X86::COND_E &&
20076 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
20077 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
20078 DAG.getConstant(CC, MVT::i8), Cond };
20079 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
20087 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
20088 const X86Subtarget *Subtarget) {
20089 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
20091 default: return SDValue();
20092 // SSE/AVX/AVX2 blend intrinsics.
20093 case Intrinsic::x86_avx2_pblendvb:
20094 case Intrinsic::x86_avx2_pblendw:
20095 case Intrinsic::x86_avx2_pblendd_128:
20096 case Intrinsic::x86_avx2_pblendd_256:
20097 // Don't try to simplify this intrinsic if we don't have AVX2.
20098 if (!Subtarget->hasAVX2())
20101 case Intrinsic::x86_avx_blend_pd_256:
20102 case Intrinsic::x86_avx_blend_ps_256:
20103 case Intrinsic::x86_avx_blendv_pd_256:
20104 case Intrinsic::x86_avx_blendv_ps_256:
20105 // Don't try to simplify this intrinsic if we don't have AVX.
20106 if (!Subtarget->hasAVX())
20109 case Intrinsic::x86_sse41_pblendw:
20110 case Intrinsic::x86_sse41_blendpd:
20111 case Intrinsic::x86_sse41_blendps:
20112 case Intrinsic::x86_sse41_blendvps:
20113 case Intrinsic::x86_sse41_blendvpd:
20114 case Intrinsic::x86_sse41_pblendvb: {
20115 SDValue Op0 = N->getOperand(1);
20116 SDValue Op1 = N->getOperand(2);
20117 SDValue Mask = N->getOperand(3);
20119 // Don't try to simplify this intrinsic if we don't have SSE4.1.
20120 if (!Subtarget->hasSSE41())
20123 // fold (blend A, A, Mask) -> A
20126 // fold (blend A, B, allZeros) -> A
20127 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
20129 // fold (blend A, B, allOnes) -> B
20130 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
20133 // Simplify the case where the mask is a constant i32 value.
20134 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
20135 if (C->isNullValue())
20137 if (C->isAllOnesValue())
20144 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
20145 case Intrinsic::x86_sse2_psrai_w:
20146 case Intrinsic::x86_sse2_psrai_d:
20147 case Intrinsic::x86_avx2_psrai_w:
20148 case Intrinsic::x86_avx2_psrai_d:
20149 case Intrinsic::x86_sse2_psra_w:
20150 case Intrinsic::x86_sse2_psra_d:
20151 case Intrinsic::x86_avx2_psra_w:
20152 case Intrinsic::x86_avx2_psra_d: {
20153 SDValue Op0 = N->getOperand(1);
20154 SDValue Op1 = N->getOperand(2);
20155 EVT VT = Op0.getValueType();
20156 assert(VT.isVector() && "Expected a vector type!");
20158 if (isa<BuildVectorSDNode>(Op1))
20159 Op1 = Op1.getOperand(0);
20161 if (!isa<ConstantSDNode>(Op1))
20164 EVT SVT = VT.getVectorElementType();
20165 unsigned SVTBits = SVT.getSizeInBits();
20167 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
20168 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
20169 uint64_t ShAmt = C.getZExtValue();
20171 // Don't try to convert this shift into a ISD::SRA if the shift
20172 // count is bigger than or equal to the element size.
20173 if (ShAmt >= SVTBits)
20176 // Trivial case: if the shift count is zero, then fold this
20177 // into the first operand.
20181 // Replace this packed shift intrinsic with a target independent
20183 SDValue Splat = DAG.getConstant(C, VT);
20184 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
20189 /// PerformMulCombine - Optimize a single multiply with constant into two
20190 /// in order to implement it with two cheaper instructions, e.g.
20191 /// LEA + SHL, LEA + LEA.
20192 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
20193 TargetLowering::DAGCombinerInfo &DCI) {
20194 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
20197 EVT VT = N->getValueType(0);
20198 if (VT != MVT::i64)
20201 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
20204 uint64_t MulAmt = C->getZExtValue();
20205 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
20208 uint64_t MulAmt1 = 0;
20209 uint64_t MulAmt2 = 0;
20210 if ((MulAmt % 9) == 0) {
20212 MulAmt2 = MulAmt / 9;
20213 } else if ((MulAmt % 5) == 0) {
20215 MulAmt2 = MulAmt / 5;
20216 } else if ((MulAmt % 3) == 0) {
20218 MulAmt2 = MulAmt / 3;
20221 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
20224 if (isPowerOf2_64(MulAmt2) &&
20225 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
20226 // If second multiplifer is pow2, issue it first. We want the multiply by
20227 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
20229 std::swap(MulAmt1, MulAmt2);
20232 if (isPowerOf2_64(MulAmt1))
20233 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
20234 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
20236 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
20237 DAG.getConstant(MulAmt1, VT));
20239 if (isPowerOf2_64(MulAmt2))
20240 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
20241 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
20243 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
20244 DAG.getConstant(MulAmt2, VT));
20246 // Do not add new nodes to DAG combiner worklist.
20247 DCI.CombineTo(N, NewMul, false);
20252 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
20253 SDValue N0 = N->getOperand(0);
20254 SDValue N1 = N->getOperand(1);
20255 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
20256 EVT VT = N0.getValueType();
20258 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
20259 // since the result of setcc_c is all zero's or all ones.
20260 if (VT.isInteger() && !VT.isVector() &&
20261 N1C && N0.getOpcode() == ISD::AND &&
20262 N0.getOperand(1).getOpcode() == ISD::Constant) {
20263 SDValue N00 = N0.getOperand(0);
20264 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
20265 ((N00.getOpcode() == ISD::ANY_EXTEND ||
20266 N00.getOpcode() == ISD::ZERO_EXTEND) &&
20267 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
20268 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
20269 APInt ShAmt = N1C->getAPIntValue();
20270 Mask = Mask.shl(ShAmt);
20272 return DAG.getNode(ISD::AND, SDLoc(N), VT,
20273 N00, DAG.getConstant(Mask, VT));
20277 // Hardware support for vector shifts is sparse which makes us scalarize the
20278 // vector operations in many cases. Also, on sandybridge ADD is faster than
20280 // (shl V, 1) -> add V,V
20281 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
20282 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
20283 assert(N0.getValueType().isVector() && "Invalid vector shift type");
20284 // We shift all of the values by one. In many cases we do not have
20285 // hardware support for this operation. This is better expressed as an ADD
20287 if (N1SplatC->getZExtValue() == 1)
20288 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
20294 /// \brief Returns a vector of 0s if the node in input is a vector logical
20295 /// shift by a constant amount which is known to be bigger than or equal
20296 /// to the vector element size in bits.
20297 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
20298 const X86Subtarget *Subtarget) {
20299 EVT VT = N->getValueType(0);
20301 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
20302 (!Subtarget->hasInt256() ||
20303 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
20306 SDValue Amt = N->getOperand(1);
20308 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
20309 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
20310 APInt ShiftAmt = AmtSplat->getAPIntValue();
20311 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
20313 // SSE2/AVX2 logical shifts always return a vector of 0s
20314 // if the shift amount is bigger than or equal to
20315 // the element size. The constant shift amount will be
20316 // encoded as a 8-bit immediate.
20317 if (ShiftAmt.trunc(8).uge(MaxAmount))
20318 return getZeroVector(VT, Subtarget, DAG, DL);
20324 /// PerformShiftCombine - Combine shifts.
20325 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
20326 TargetLowering::DAGCombinerInfo &DCI,
20327 const X86Subtarget *Subtarget) {
20328 if (N->getOpcode() == ISD::SHL) {
20329 SDValue V = PerformSHLCombine(N, DAG);
20330 if (V.getNode()) return V;
20333 if (N->getOpcode() != ISD::SRA) {
20334 // Try to fold this logical shift into a zero vector.
20335 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
20336 if (V.getNode()) return V;
20342 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
20343 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
20344 // and friends. Likewise for OR -> CMPNEQSS.
20345 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
20346 TargetLowering::DAGCombinerInfo &DCI,
20347 const X86Subtarget *Subtarget) {
20350 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
20351 // we're requiring SSE2 for both.
20352 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
20353 SDValue N0 = N->getOperand(0);
20354 SDValue N1 = N->getOperand(1);
20355 SDValue CMP0 = N0->getOperand(1);
20356 SDValue CMP1 = N1->getOperand(1);
20359 // The SETCCs should both refer to the same CMP.
20360 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
20363 SDValue CMP00 = CMP0->getOperand(0);
20364 SDValue CMP01 = CMP0->getOperand(1);
20365 EVT VT = CMP00.getValueType();
20367 if (VT == MVT::f32 || VT == MVT::f64) {
20368 bool ExpectingFlags = false;
20369 // Check for any users that want flags:
20370 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
20371 !ExpectingFlags && UI != UE; ++UI)
20372 switch (UI->getOpcode()) {
20377 ExpectingFlags = true;
20379 case ISD::CopyToReg:
20380 case ISD::SIGN_EXTEND:
20381 case ISD::ZERO_EXTEND:
20382 case ISD::ANY_EXTEND:
20386 if (!ExpectingFlags) {
20387 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
20388 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
20390 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
20391 X86::CondCode tmp = cc0;
20396 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
20397 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
20398 // FIXME: need symbolic constants for these magic numbers.
20399 // See X86ATTInstPrinter.cpp:printSSECC().
20400 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
20401 if (Subtarget->hasAVX512()) {
20402 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
20403 CMP01, DAG.getConstant(x86cc, MVT::i8));
20404 if (N->getValueType(0) != MVT::i1)
20405 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
20409 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
20410 CMP00.getValueType(), CMP00, CMP01,
20411 DAG.getConstant(x86cc, MVT::i8));
20413 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
20414 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
20416 if (is64BitFP && !Subtarget->is64Bit()) {
20417 // On a 32-bit target, we cannot bitcast the 64-bit float to a
20418 // 64-bit integer, since that's not a legal type. Since
20419 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
20420 // bits, but can do this little dance to extract the lowest 32 bits
20421 // and work with those going forward.
20422 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
20424 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
20426 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
20427 Vector32, DAG.getIntPtrConstant(0));
20431 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
20432 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
20433 DAG.getConstant(1, IntVT));
20434 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
20435 return OneBitOfTruth;
20443 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
20444 /// so it can be folded inside ANDNP.
20445 static bool CanFoldXORWithAllOnes(const SDNode *N) {
20446 EVT VT = N->getValueType(0);
20448 // Match direct AllOnes for 128 and 256-bit vectors
20449 if (ISD::isBuildVectorAllOnes(N))
20452 // Look through a bit convert.
20453 if (N->getOpcode() == ISD::BITCAST)
20454 N = N->getOperand(0).getNode();
20456 // Sometimes the operand may come from a insert_subvector building a 256-bit
20458 if (VT.is256BitVector() &&
20459 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
20460 SDValue V1 = N->getOperand(0);
20461 SDValue V2 = N->getOperand(1);
20463 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
20464 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
20465 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
20466 ISD::isBuildVectorAllOnes(V2.getNode()))
20473 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
20474 // register. In most cases we actually compare or select YMM-sized registers
20475 // and mixing the two types creates horrible code. This method optimizes
20476 // some of the transition sequences.
20477 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
20478 TargetLowering::DAGCombinerInfo &DCI,
20479 const X86Subtarget *Subtarget) {
20480 EVT VT = N->getValueType(0);
20481 if (!VT.is256BitVector())
20484 assert((N->getOpcode() == ISD::ANY_EXTEND ||
20485 N->getOpcode() == ISD::ZERO_EXTEND ||
20486 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
20488 SDValue Narrow = N->getOperand(0);
20489 EVT NarrowVT = Narrow->getValueType(0);
20490 if (!NarrowVT.is128BitVector())
20493 if (Narrow->getOpcode() != ISD::XOR &&
20494 Narrow->getOpcode() != ISD::AND &&
20495 Narrow->getOpcode() != ISD::OR)
20498 SDValue N0 = Narrow->getOperand(0);
20499 SDValue N1 = Narrow->getOperand(1);
20502 // The Left side has to be a trunc.
20503 if (N0.getOpcode() != ISD::TRUNCATE)
20506 // The type of the truncated inputs.
20507 EVT WideVT = N0->getOperand(0)->getValueType(0);
20511 // The right side has to be a 'trunc' or a constant vector.
20512 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
20513 ConstantSDNode *RHSConstSplat = nullptr;
20514 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
20515 RHSConstSplat = RHSBV->getConstantSplatNode();
20516 if (!RHSTrunc && !RHSConstSplat)
20519 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20521 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
20524 // Set N0 and N1 to hold the inputs to the new wide operation.
20525 N0 = N0->getOperand(0);
20526 if (RHSConstSplat) {
20527 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
20528 SDValue(RHSConstSplat, 0));
20529 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
20530 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
20531 } else if (RHSTrunc) {
20532 N1 = N1->getOperand(0);
20535 // Generate the wide operation.
20536 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
20537 unsigned Opcode = N->getOpcode();
20539 case ISD::ANY_EXTEND:
20541 case ISD::ZERO_EXTEND: {
20542 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
20543 APInt Mask = APInt::getAllOnesValue(InBits);
20544 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
20545 return DAG.getNode(ISD::AND, DL, VT,
20546 Op, DAG.getConstant(Mask, VT));
20548 case ISD::SIGN_EXTEND:
20549 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
20550 Op, DAG.getValueType(NarrowVT));
20552 llvm_unreachable("Unexpected opcode");
20556 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
20557 TargetLowering::DAGCombinerInfo &DCI,
20558 const X86Subtarget *Subtarget) {
20559 EVT VT = N->getValueType(0);
20560 if (DCI.isBeforeLegalizeOps())
20563 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
20567 // Create BEXTR instructions
20568 // BEXTR is ((X >> imm) & (2**size-1))
20569 if (VT == MVT::i32 || VT == MVT::i64) {
20570 SDValue N0 = N->getOperand(0);
20571 SDValue N1 = N->getOperand(1);
20574 // Check for BEXTR.
20575 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
20576 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
20577 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
20578 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
20579 if (MaskNode && ShiftNode) {
20580 uint64_t Mask = MaskNode->getZExtValue();
20581 uint64_t Shift = ShiftNode->getZExtValue();
20582 if (isMask_64(Mask)) {
20583 uint64_t MaskSize = CountPopulation_64(Mask);
20584 if (Shift + MaskSize <= VT.getSizeInBits())
20585 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
20586 DAG.getConstant(Shift | (MaskSize << 8), VT));
20594 // Want to form ANDNP nodes:
20595 // 1) In the hopes of then easily combining them with OR and AND nodes
20596 // to form PBLEND/PSIGN.
20597 // 2) To match ANDN packed intrinsics
20598 if (VT != MVT::v2i64 && VT != MVT::v4i64)
20601 SDValue N0 = N->getOperand(0);
20602 SDValue N1 = N->getOperand(1);
20605 // Check LHS for vnot
20606 if (N0.getOpcode() == ISD::XOR &&
20607 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
20608 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
20609 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
20611 // Check RHS for vnot
20612 if (N1.getOpcode() == ISD::XOR &&
20613 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
20614 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
20615 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
20620 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
20621 TargetLowering::DAGCombinerInfo &DCI,
20622 const X86Subtarget *Subtarget) {
20623 if (DCI.isBeforeLegalizeOps())
20626 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
20630 SDValue N0 = N->getOperand(0);
20631 SDValue N1 = N->getOperand(1);
20632 EVT VT = N->getValueType(0);
20634 // look for psign/blend
20635 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
20636 if (!Subtarget->hasSSSE3() ||
20637 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
20640 // Canonicalize pandn to RHS
20641 if (N0.getOpcode() == X86ISD::ANDNP)
20643 // or (and (m, y), (pandn m, x))
20644 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
20645 SDValue Mask = N1.getOperand(0);
20646 SDValue X = N1.getOperand(1);
20648 if (N0.getOperand(0) == Mask)
20649 Y = N0.getOperand(1);
20650 if (N0.getOperand(1) == Mask)
20651 Y = N0.getOperand(0);
20653 // Check to see if the mask appeared in both the AND and ANDNP and
20657 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
20658 // Look through mask bitcast.
20659 if (Mask.getOpcode() == ISD::BITCAST)
20660 Mask = Mask.getOperand(0);
20661 if (X.getOpcode() == ISD::BITCAST)
20662 X = X.getOperand(0);
20663 if (Y.getOpcode() == ISD::BITCAST)
20664 Y = Y.getOperand(0);
20666 EVT MaskVT = Mask.getValueType();
20668 // Validate that the Mask operand is a vector sra node.
20669 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
20670 // there is no psrai.b
20671 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
20672 unsigned SraAmt = ~0;
20673 if (Mask.getOpcode() == ISD::SRA) {
20674 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
20675 if (auto *AmtConst = AmtBV->getConstantSplatNode())
20676 SraAmt = AmtConst->getZExtValue();
20677 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
20678 SDValue SraC = Mask.getOperand(1);
20679 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
20681 if ((SraAmt + 1) != EltBits)
20686 // Now we know we at least have a plendvb with the mask val. See if
20687 // we can form a psignb/w/d.
20688 // psign = x.type == y.type == mask.type && y = sub(0, x);
20689 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
20690 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
20691 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
20692 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
20693 "Unsupported VT for PSIGN");
20694 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
20695 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
20697 // PBLENDVB only available on SSE 4.1
20698 if (!Subtarget->hasSSE41())
20701 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
20703 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
20704 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
20705 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
20706 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
20707 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
20711 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
20714 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
20715 MachineFunction &MF = DAG.getMachineFunction();
20716 bool OptForSize = MF.getFunction()->getAttributes().
20717 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
20719 // SHLD/SHRD instructions have lower register pressure, but on some
20720 // platforms they have higher latency than the equivalent
20721 // series of shifts/or that would otherwise be generated.
20722 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
20723 // have higher latencies and we are not optimizing for size.
20724 if (!OptForSize && Subtarget->isSHLDSlow())
20727 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
20729 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
20731 if (!N0.hasOneUse() || !N1.hasOneUse())
20734 SDValue ShAmt0 = N0.getOperand(1);
20735 if (ShAmt0.getValueType() != MVT::i8)
20737 SDValue ShAmt1 = N1.getOperand(1);
20738 if (ShAmt1.getValueType() != MVT::i8)
20740 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
20741 ShAmt0 = ShAmt0.getOperand(0);
20742 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
20743 ShAmt1 = ShAmt1.getOperand(0);
20746 unsigned Opc = X86ISD::SHLD;
20747 SDValue Op0 = N0.getOperand(0);
20748 SDValue Op1 = N1.getOperand(0);
20749 if (ShAmt0.getOpcode() == ISD::SUB) {
20750 Opc = X86ISD::SHRD;
20751 std::swap(Op0, Op1);
20752 std::swap(ShAmt0, ShAmt1);
20755 unsigned Bits = VT.getSizeInBits();
20756 if (ShAmt1.getOpcode() == ISD::SUB) {
20757 SDValue Sum = ShAmt1.getOperand(0);
20758 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
20759 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
20760 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
20761 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
20762 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
20763 return DAG.getNode(Opc, DL, VT,
20765 DAG.getNode(ISD::TRUNCATE, DL,
20768 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
20769 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
20771 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
20772 return DAG.getNode(Opc, DL, VT,
20773 N0.getOperand(0), N1.getOperand(0),
20774 DAG.getNode(ISD::TRUNCATE, DL,
20781 // Generate NEG and CMOV for integer abs.
20782 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
20783 EVT VT = N->getValueType(0);
20785 // Since X86 does not have CMOV for 8-bit integer, we don't convert
20786 // 8-bit integer abs to NEG and CMOV.
20787 if (VT.isInteger() && VT.getSizeInBits() == 8)
20790 SDValue N0 = N->getOperand(0);
20791 SDValue N1 = N->getOperand(1);
20794 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
20795 // and change it to SUB and CMOV.
20796 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
20797 N0.getOpcode() == ISD::ADD &&
20798 N0.getOperand(1) == N1 &&
20799 N1.getOpcode() == ISD::SRA &&
20800 N1.getOperand(0) == N0.getOperand(0))
20801 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
20802 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
20803 // Generate SUB & CMOV.
20804 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
20805 DAG.getConstant(0, VT), N0.getOperand(0));
20807 SDValue Ops[] = { N0.getOperand(0), Neg,
20808 DAG.getConstant(X86::COND_GE, MVT::i8),
20809 SDValue(Neg.getNode(), 1) };
20810 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
20815 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
20816 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
20817 TargetLowering::DAGCombinerInfo &DCI,
20818 const X86Subtarget *Subtarget) {
20819 if (DCI.isBeforeLegalizeOps())
20822 if (Subtarget->hasCMov()) {
20823 SDValue RV = performIntegerAbsCombine(N, DAG);
20831 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
20832 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
20833 TargetLowering::DAGCombinerInfo &DCI,
20834 const X86Subtarget *Subtarget) {
20835 LoadSDNode *Ld = cast<LoadSDNode>(N);
20836 EVT RegVT = Ld->getValueType(0);
20837 EVT MemVT = Ld->getMemoryVT();
20839 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20840 unsigned RegSz = RegVT.getSizeInBits();
20842 // On Sandybridge unaligned 256bit loads are inefficient.
20843 ISD::LoadExtType Ext = Ld->getExtensionType();
20844 unsigned Alignment = Ld->getAlignment();
20845 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
20846 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
20847 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
20848 unsigned NumElems = RegVT.getVectorNumElements();
20852 SDValue Ptr = Ld->getBasePtr();
20853 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
20855 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
20857 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
20858 Ld->getPointerInfo(), Ld->isVolatile(),
20859 Ld->isNonTemporal(), Ld->isInvariant(),
20861 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
20862 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
20863 Ld->getPointerInfo(), Ld->isVolatile(),
20864 Ld->isNonTemporal(), Ld->isInvariant(),
20865 std::min(16U, Alignment));
20866 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20868 Load2.getValue(1));
20870 SDValue NewVec = DAG.getUNDEF(RegVT);
20871 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
20872 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
20873 return DCI.CombineTo(N, NewVec, TF, true);
20876 // If this is a vector EXT Load then attempt to optimize it using a
20877 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
20878 // expansion is still better than scalar code.
20879 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
20880 // emit a shuffle and a arithmetic shift.
20881 // TODO: It is possible to support ZExt by zeroing the undef values
20882 // during the shuffle phase or after the shuffle.
20883 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
20884 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
20885 assert(MemVT != RegVT && "Cannot extend to the same type");
20886 assert(MemVT.isVector() && "Must load a vector from memory");
20888 unsigned NumElems = RegVT.getVectorNumElements();
20889 unsigned MemSz = MemVT.getSizeInBits();
20890 assert(RegSz > MemSz && "Register size must be greater than the mem size");
20892 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
20895 // All sizes must be a power of two.
20896 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
20899 // Attempt to load the original value using scalar loads.
20900 // Find the largest scalar type that divides the total loaded size.
20901 MVT SclrLoadTy = MVT::i8;
20902 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
20903 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
20904 MVT Tp = (MVT::SimpleValueType)tp;
20905 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
20910 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
20911 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
20913 SclrLoadTy = MVT::f64;
20915 // Calculate the number of scalar loads that we need to perform
20916 // in order to load our vector from memory.
20917 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
20918 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
20921 unsigned loadRegZize = RegSz;
20922 if (Ext == ISD::SEXTLOAD && RegSz == 256)
20925 // Represent our vector as a sequence of elements which are the
20926 // largest scalar that we can load.
20927 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
20928 loadRegZize/SclrLoadTy.getSizeInBits());
20930 // Represent the data using the same element type that is stored in
20931 // memory. In practice, we ''widen'' MemVT.
20933 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
20934 loadRegZize/MemVT.getScalarType().getSizeInBits());
20936 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
20937 "Invalid vector type");
20939 // We can't shuffle using an illegal type.
20940 if (!TLI.isTypeLegal(WideVecVT))
20943 SmallVector<SDValue, 8> Chains;
20944 SDValue Ptr = Ld->getBasePtr();
20945 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
20946 TLI.getPointerTy());
20947 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
20949 for (unsigned i = 0; i < NumLoads; ++i) {
20950 // Perform a single load.
20951 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
20952 Ptr, Ld->getPointerInfo(),
20953 Ld->isVolatile(), Ld->isNonTemporal(),
20954 Ld->isInvariant(), Ld->getAlignment());
20955 Chains.push_back(ScalarLoad.getValue(1));
20956 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
20957 // another round of DAGCombining.
20959 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
20961 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
20962 ScalarLoad, DAG.getIntPtrConstant(i));
20964 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
20967 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
20969 // Bitcast the loaded value to a vector of the original element type, in
20970 // the size of the target vector type.
20971 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
20972 unsigned SizeRatio = RegSz/MemSz;
20974 if (Ext == ISD::SEXTLOAD) {
20975 // If we have SSE4.1 we can directly emit a VSEXT node.
20976 if (Subtarget->hasSSE41()) {
20977 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
20978 return DCI.CombineTo(N, Sext, TF, true);
20981 // Otherwise we'll shuffle the small elements in the high bits of the
20982 // larger type and perform an arithmetic shift. If the shift is not legal
20983 // it's better to scalarize.
20984 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
20987 // Redistribute the loaded elements into the different locations.
20988 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
20989 for (unsigned i = 0; i != NumElems; ++i)
20990 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
20992 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
20993 DAG.getUNDEF(WideVecVT),
20996 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
20998 // Build the arithmetic shift.
20999 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
21000 MemVT.getVectorElementType().getSizeInBits();
21001 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
21002 DAG.getConstant(Amt, RegVT));
21004 return DCI.CombineTo(N, Shuff, TF, true);
21007 // Redistribute the loaded elements into the different locations.
21008 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
21009 for (unsigned i = 0; i != NumElems; ++i)
21010 ShuffleVec[i*SizeRatio] = i;
21012 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
21013 DAG.getUNDEF(WideVecVT),
21016 // Bitcast to the requested type.
21017 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
21018 // Replace the original load with the new sequence
21019 // and return the new chain.
21020 return DCI.CombineTo(N, Shuff, TF, true);
21026 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
21027 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
21028 const X86Subtarget *Subtarget) {
21029 StoreSDNode *St = cast<StoreSDNode>(N);
21030 EVT VT = St->getValue().getValueType();
21031 EVT StVT = St->getMemoryVT();
21033 SDValue StoredVal = St->getOperand(1);
21034 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21036 // If we are saving a concatenation of two XMM registers, perform two stores.
21037 // On Sandy Bridge, 256-bit memory operations are executed by two
21038 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
21039 // memory operation.
21040 unsigned Alignment = St->getAlignment();
21041 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
21042 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
21043 StVT == VT && !IsAligned) {
21044 unsigned NumElems = VT.getVectorNumElements();
21048 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
21049 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
21051 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
21052 SDValue Ptr0 = St->getBasePtr();
21053 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
21055 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
21056 St->getPointerInfo(), St->isVolatile(),
21057 St->isNonTemporal(), Alignment);
21058 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
21059 St->getPointerInfo(), St->isVolatile(),
21060 St->isNonTemporal(),
21061 std::min(16U, Alignment));
21062 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
21065 // Optimize trunc store (of multiple scalars) to shuffle and store.
21066 // First, pack all of the elements in one place. Next, store to memory
21067 // in fewer chunks.
21068 if (St->isTruncatingStore() && VT.isVector()) {
21069 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21070 unsigned NumElems = VT.getVectorNumElements();
21071 assert(StVT != VT && "Cannot truncate to the same type");
21072 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
21073 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
21075 // From, To sizes and ElemCount must be pow of two
21076 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
21077 // We are going to use the original vector elt for storing.
21078 // Accumulated smaller vector elements must be a multiple of the store size.
21079 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
21081 unsigned SizeRatio = FromSz / ToSz;
21083 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
21085 // Create a type on which we perform the shuffle
21086 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
21087 StVT.getScalarType(), NumElems*SizeRatio);
21089 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
21091 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
21092 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
21093 for (unsigned i = 0; i != NumElems; ++i)
21094 ShuffleVec[i] = i * SizeRatio;
21096 // Can't shuffle using an illegal type.
21097 if (!TLI.isTypeLegal(WideVecVT))
21100 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
21101 DAG.getUNDEF(WideVecVT),
21103 // At this point all of the data is stored at the bottom of the
21104 // register. We now need to save it to mem.
21106 // Find the largest store unit
21107 MVT StoreType = MVT::i8;
21108 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
21109 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
21110 MVT Tp = (MVT::SimpleValueType)tp;
21111 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
21115 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
21116 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
21117 (64 <= NumElems * ToSz))
21118 StoreType = MVT::f64;
21120 // Bitcast the original vector into a vector of store-size units
21121 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
21122 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
21123 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
21124 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
21125 SmallVector<SDValue, 8> Chains;
21126 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
21127 TLI.getPointerTy());
21128 SDValue Ptr = St->getBasePtr();
21130 // Perform one or more big stores into memory.
21131 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
21132 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
21133 StoreType, ShuffWide,
21134 DAG.getIntPtrConstant(i));
21135 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
21136 St->getPointerInfo(), St->isVolatile(),
21137 St->isNonTemporal(), St->getAlignment());
21138 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
21139 Chains.push_back(Ch);
21142 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
21145 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
21146 // the FP state in cases where an emms may be missing.
21147 // A preferable solution to the general problem is to figure out the right
21148 // places to insert EMMS. This qualifies as a quick hack.
21150 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
21151 if (VT.getSizeInBits() != 64)
21154 const Function *F = DAG.getMachineFunction().getFunction();
21155 bool NoImplicitFloatOps = F->getAttributes().
21156 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
21157 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
21158 && Subtarget->hasSSE2();
21159 if ((VT.isVector() ||
21160 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
21161 isa<LoadSDNode>(St->getValue()) &&
21162 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
21163 St->getChain().hasOneUse() && !St->isVolatile()) {
21164 SDNode* LdVal = St->getValue().getNode();
21165 LoadSDNode *Ld = nullptr;
21166 int TokenFactorIndex = -1;
21167 SmallVector<SDValue, 8> Ops;
21168 SDNode* ChainVal = St->getChain().getNode();
21169 // Must be a store of a load. We currently handle two cases: the load
21170 // is a direct child, and it's under an intervening TokenFactor. It is
21171 // possible to dig deeper under nested TokenFactors.
21172 if (ChainVal == LdVal)
21173 Ld = cast<LoadSDNode>(St->getChain());
21174 else if (St->getValue().hasOneUse() &&
21175 ChainVal->getOpcode() == ISD::TokenFactor) {
21176 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
21177 if (ChainVal->getOperand(i).getNode() == LdVal) {
21178 TokenFactorIndex = i;
21179 Ld = cast<LoadSDNode>(St->getValue());
21181 Ops.push_back(ChainVal->getOperand(i));
21185 if (!Ld || !ISD::isNormalLoad(Ld))
21188 // If this is not the MMX case, i.e. we are just turning i64 load/store
21189 // into f64 load/store, avoid the transformation if there are multiple
21190 // uses of the loaded value.
21191 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
21196 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
21197 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
21199 if (Subtarget->is64Bit() || F64IsLegal) {
21200 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
21201 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
21202 Ld->getPointerInfo(), Ld->isVolatile(),
21203 Ld->isNonTemporal(), Ld->isInvariant(),
21204 Ld->getAlignment());
21205 SDValue NewChain = NewLd.getValue(1);
21206 if (TokenFactorIndex != -1) {
21207 Ops.push_back(NewChain);
21208 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
21210 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
21211 St->getPointerInfo(),
21212 St->isVolatile(), St->isNonTemporal(),
21213 St->getAlignment());
21216 // Otherwise, lower to two pairs of 32-bit loads / stores.
21217 SDValue LoAddr = Ld->getBasePtr();
21218 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
21219 DAG.getConstant(4, MVT::i32));
21221 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
21222 Ld->getPointerInfo(),
21223 Ld->isVolatile(), Ld->isNonTemporal(),
21224 Ld->isInvariant(), Ld->getAlignment());
21225 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
21226 Ld->getPointerInfo().getWithOffset(4),
21227 Ld->isVolatile(), Ld->isNonTemporal(),
21229 MinAlign(Ld->getAlignment(), 4));
21231 SDValue NewChain = LoLd.getValue(1);
21232 if (TokenFactorIndex != -1) {
21233 Ops.push_back(LoLd);
21234 Ops.push_back(HiLd);
21235 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
21238 LoAddr = St->getBasePtr();
21239 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
21240 DAG.getConstant(4, MVT::i32));
21242 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
21243 St->getPointerInfo(),
21244 St->isVolatile(), St->isNonTemporal(),
21245 St->getAlignment());
21246 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
21247 St->getPointerInfo().getWithOffset(4),
21249 St->isNonTemporal(),
21250 MinAlign(St->getAlignment(), 4));
21251 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
21256 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
21257 /// and return the operands for the horizontal operation in LHS and RHS. A
21258 /// horizontal operation performs the binary operation on successive elements
21259 /// of its first operand, then on successive elements of its second operand,
21260 /// returning the resulting values in a vector. For example, if
21261 /// A = < float a0, float a1, float a2, float a3 >
21263 /// B = < float b0, float b1, float b2, float b3 >
21264 /// then the result of doing a horizontal operation on A and B is
21265 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
21266 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
21267 /// A horizontal-op B, for some already available A and B, and if so then LHS is
21268 /// set to A, RHS to B, and the routine returns 'true'.
21269 /// Note that the binary operation should have the property that if one of the
21270 /// operands is UNDEF then the result is UNDEF.
21271 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
21272 // Look for the following pattern: if
21273 // A = < float a0, float a1, float a2, float a3 >
21274 // B = < float b0, float b1, float b2, float b3 >
21276 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
21277 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
21278 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
21279 // which is A horizontal-op B.
21281 // At least one of the operands should be a vector shuffle.
21282 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
21283 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
21286 MVT VT = LHS.getSimpleValueType();
21288 assert((VT.is128BitVector() || VT.is256BitVector()) &&
21289 "Unsupported vector type for horizontal add/sub");
21291 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
21292 // operate independently on 128-bit lanes.
21293 unsigned NumElts = VT.getVectorNumElements();
21294 unsigned NumLanes = VT.getSizeInBits()/128;
21295 unsigned NumLaneElts = NumElts / NumLanes;
21296 assert((NumLaneElts % 2 == 0) &&
21297 "Vector type should have an even number of elements in each lane");
21298 unsigned HalfLaneElts = NumLaneElts/2;
21300 // View LHS in the form
21301 // LHS = VECTOR_SHUFFLE A, B, LMask
21302 // If LHS is not a shuffle then pretend it is the shuffle
21303 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
21304 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
21307 SmallVector<int, 16> LMask(NumElts);
21308 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
21309 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
21310 A = LHS.getOperand(0);
21311 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
21312 B = LHS.getOperand(1);
21313 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
21314 std::copy(Mask.begin(), Mask.end(), LMask.begin());
21316 if (LHS.getOpcode() != ISD::UNDEF)
21318 for (unsigned i = 0; i != NumElts; ++i)
21322 // Likewise, view RHS in the form
21323 // RHS = VECTOR_SHUFFLE C, D, RMask
21325 SmallVector<int, 16> RMask(NumElts);
21326 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
21327 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
21328 C = RHS.getOperand(0);
21329 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
21330 D = RHS.getOperand(1);
21331 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
21332 std::copy(Mask.begin(), Mask.end(), RMask.begin());
21334 if (RHS.getOpcode() != ISD::UNDEF)
21336 for (unsigned i = 0; i != NumElts; ++i)
21340 // Check that the shuffles are both shuffling the same vectors.
21341 if (!(A == C && B == D) && !(A == D && B == C))
21344 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
21345 if (!A.getNode() && !B.getNode())
21348 // If A and B occur in reverse order in RHS, then "swap" them (which means
21349 // rewriting the mask).
21351 CommuteVectorShuffleMask(RMask, NumElts);
21353 // At this point LHS and RHS are equivalent to
21354 // LHS = VECTOR_SHUFFLE A, B, LMask
21355 // RHS = VECTOR_SHUFFLE A, B, RMask
21356 // Check that the masks correspond to performing a horizontal operation.
21357 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
21358 for (unsigned i = 0; i != NumLaneElts; ++i) {
21359 int LIdx = LMask[i+l], RIdx = RMask[i+l];
21361 // Ignore any UNDEF components.
21362 if (LIdx < 0 || RIdx < 0 ||
21363 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
21364 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
21367 // Check that successive elements are being operated on. If not, this is
21368 // not a horizontal operation.
21369 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
21370 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
21371 if (!(LIdx == Index && RIdx == Index + 1) &&
21372 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
21377 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
21378 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
21382 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
21383 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
21384 const X86Subtarget *Subtarget) {
21385 EVT VT = N->getValueType(0);
21386 SDValue LHS = N->getOperand(0);
21387 SDValue RHS = N->getOperand(1);
21389 // Try to synthesize horizontal adds from adds of shuffles.
21390 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
21391 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
21392 isHorizontalBinOp(LHS, RHS, true))
21393 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
21397 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
21398 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
21399 const X86Subtarget *Subtarget) {
21400 EVT VT = N->getValueType(0);
21401 SDValue LHS = N->getOperand(0);
21402 SDValue RHS = N->getOperand(1);
21404 // Try to synthesize horizontal subs from subs of shuffles.
21405 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
21406 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
21407 isHorizontalBinOp(LHS, RHS, false))
21408 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
21412 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
21413 /// X86ISD::FXOR nodes.
21414 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
21415 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
21416 // F[X]OR(0.0, x) -> x
21417 // F[X]OR(x, 0.0) -> x
21418 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
21419 if (C->getValueAPF().isPosZero())
21420 return N->getOperand(1);
21421 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
21422 if (C->getValueAPF().isPosZero())
21423 return N->getOperand(0);
21427 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
21428 /// X86ISD::FMAX nodes.
21429 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
21430 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
21432 // Only perform optimizations if UnsafeMath is used.
21433 if (!DAG.getTarget().Options.UnsafeFPMath)
21436 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
21437 // into FMINC and FMAXC, which are Commutative operations.
21438 unsigned NewOp = 0;
21439 switch (N->getOpcode()) {
21440 default: llvm_unreachable("unknown opcode");
21441 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
21442 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
21445 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
21446 N->getOperand(0), N->getOperand(1));
21449 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
21450 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
21451 // FAND(0.0, x) -> 0.0
21452 // FAND(x, 0.0) -> 0.0
21453 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
21454 if (C->getValueAPF().isPosZero())
21455 return N->getOperand(0);
21456 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
21457 if (C->getValueAPF().isPosZero())
21458 return N->getOperand(1);
21462 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
21463 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
21464 // FANDN(x, 0.0) -> 0.0
21465 // FANDN(0.0, x) -> x
21466 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
21467 if (C->getValueAPF().isPosZero())
21468 return N->getOperand(1);
21469 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
21470 if (C->getValueAPF().isPosZero())
21471 return N->getOperand(1);
21475 static SDValue PerformBTCombine(SDNode *N,
21477 TargetLowering::DAGCombinerInfo &DCI) {
21478 // BT ignores high bits in the bit index operand.
21479 SDValue Op1 = N->getOperand(1);
21480 if (Op1.hasOneUse()) {
21481 unsigned BitWidth = Op1.getValueSizeInBits();
21482 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
21483 APInt KnownZero, KnownOne;
21484 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
21485 !DCI.isBeforeLegalizeOps());
21486 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21487 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
21488 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
21489 DCI.CommitTargetLoweringOpt(TLO);
21494 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
21495 SDValue Op = N->getOperand(0);
21496 if (Op.getOpcode() == ISD::BITCAST)
21497 Op = Op.getOperand(0);
21498 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
21499 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
21500 VT.getVectorElementType().getSizeInBits() ==
21501 OpVT.getVectorElementType().getSizeInBits()) {
21502 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
21507 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
21508 const X86Subtarget *Subtarget) {
21509 EVT VT = N->getValueType(0);
21510 if (!VT.isVector())
21513 SDValue N0 = N->getOperand(0);
21514 SDValue N1 = N->getOperand(1);
21515 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
21518 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
21519 // both SSE and AVX2 since there is no sign-extended shift right
21520 // operation on a vector with 64-bit elements.
21521 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
21522 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
21523 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
21524 N0.getOpcode() == ISD::SIGN_EXTEND)) {
21525 SDValue N00 = N0.getOperand(0);
21527 // EXTLOAD has a better solution on AVX2,
21528 // it may be replaced with X86ISD::VSEXT node.
21529 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
21530 if (!ISD::isNormalLoad(N00.getNode()))
21533 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
21534 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
21536 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
21542 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
21543 TargetLowering::DAGCombinerInfo &DCI,
21544 const X86Subtarget *Subtarget) {
21545 if (!DCI.isBeforeLegalizeOps())
21548 if (!Subtarget->hasFp256())
21551 EVT VT = N->getValueType(0);
21552 if (VT.isVector() && VT.getSizeInBits() == 256) {
21553 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
21561 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
21562 const X86Subtarget* Subtarget) {
21564 EVT VT = N->getValueType(0);
21566 // Let legalize expand this if it isn't a legal type yet.
21567 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
21570 EVT ScalarVT = VT.getScalarType();
21571 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
21572 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
21575 SDValue A = N->getOperand(0);
21576 SDValue B = N->getOperand(1);
21577 SDValue C = N->getOperand(2);
21579 bool NegA = (A.getOpcode() == ISD::FNEG);
21580 bool NegB = (B.getOpcode() == ISD::FNEG);
21581 bool NegC = (C.getOpcode() == ISD::FNEG);
21583 // Negative multiplication when NegA xor NegB
21584 bool NegMul = (NegA != NegB);
21586 A = A.getOperand(0);
21588 B = B.getOperand(0);
21590 C = C.getOperand(0);
21594 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
21596 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
21598 return DAG.getNode(Opcode, dl, VT, A, B, C);
21601 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
21602 TargetLowering::DAGCombinerInfo &DCI,
21603 const X86Subtarget *Subtarget) {
21604 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
21605 // (and (i32 x86isd::setcc_carry), 1)
21606 // This eliminates the zext. This transformation is necessary because
21607 // ISD::SETCC is always legalized to i8.
21609 SDValue N0 = N->getOperand(0);
21610 EVT VT = N->getValueType(0);
21612 if (N0.getOpcode() == ISD::AND &&
21614 N0.getOperand(0).hasOneUse()) {
21615 SDValue N00 = N0.getOperand(0);
21616 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
21617 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
21618 if (!C || C->getZExtValue() != 1)
21620 return DAG.getNode(ISD::AND, dl, VT,
21621 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
21622 N00.getOperand(0), N00.getOperand(1)),
21623 DAG.getConstant(1, VT));
21627 if (N0.getOpcode() == ISD::TRUNCATE &&
21629 N0.getOperand(0).hasOneUse()) {
21630 SDValue N00 = N0.getOperand(0);
21631 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
21632 return DAG.getNode(ISD::AND, dl, VT,
21633 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
21634 N00.getOperand(0), N00.getOperand(1)),
21635 DAG.getConstant(1, VT));
21638 if (VT.is256BitVector()) {
21639 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
21647 // Optimize x == -y --> x+y == 0
21648 // x != -y --> x+y != 0
21649 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
21650 const X86Subtarget* Subtarget) {
21651 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
21652 SDValue LHS = N->getOperand(0);
21653 SDValue RHS = N->getOperand(1);
21654 EVT VT = N->getValueType(0);
21657 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
21658 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
21659 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
21660 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
21661 LHS.getValueType(), RHS, LHS.getOperand(1));
21662 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
21663 addV, DAG.getConstant(0, addV.getValueType()), CC);
21665 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
21666 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
21667 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
21668 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
21669 RHS.getValueType(), LHS, RHS.getOperand(1));
21670 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
21671 addV, DAG.getConstant(0, addV.getValueType()), CC);
21674 if (VT.getScalarType() == MVT::i1) {
21675 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
21676 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
21677 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
21678 if (!IsSEXT0 && !IsVZero0)
21680 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
21681 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
21682 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
21684 if (!IsSEXT1 && !IsVZero1)
21687 if (IsSEXT0 && IsVZero1) {
21688 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
21689 if (CC == ISD::SETEQ)
21690 return DAG.getNOT(DL, LHS.getOperand(0), VT);
21691 return LHS.getOperand(0);
21693 if (IsSEXT1 && IsVZero0) {
21694 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
21695 if (CC == ISD::SETEQ)
21696 return DAG.getNOT(DL, RHS.getOperand(0), VT);
21697 return RHS.getOperand(0);
21704 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
21705 const X86Subtarget *Subtarget) {
21707 MVT VT = N->getOperand(1)->getSimpleValueType(0);
21708 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
21709 "X86insertps is only defined for v4x32");
21711 SDValue Ld = N->getOperand(1);
21712 if (MayFoldLoad(Ld)) {
21713 // Extract the countS bits from the immediate so we can get the proper
21714 // address when narrowing the vector load to a specific element.
21715 // When the second source op is a memory address, interps doesn't use
21716 // countS and just gets an f32 from that address.
21717 unsigned DestIndex =
21718 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
21719 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
21723 // Create this as a scalar to vector to match the instruction pattern.
21724 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
21725 // countS bits are ignored when loading from memory on insertps, which
21726 // means we don't need to explicitly set them to 0.
21727 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
21728 LoadScalarToVector, N->getOperand(2));
21731 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
21732 // as "sbb reg,reg", since it can be extended without zext and produces
21733 // an all-ones bit which is more useful than 0/1 in some cases.
21734 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
21737 return DAG.getNode(ISD::AND, DL, VT,
21738 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
21739 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
21740 DAG.getConstant(1, VT));
21741 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
21742 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
21743 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
21744 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
21747 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
21748 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
21749 TargetLowering::DAGCombinerInfo &DCI,
21750 const X86Subtarget *Subtarget) {
21752 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
21753 SDValue EFLAGS = N->getOperand(1);
21755 if (CC == X86::COND_A) {
21756 // Try to convert COND_A into COND_B in an attempt to facilitate
21757 // materializing "setb reg".
21759 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
21760 // cannot take an immediate as its first operand.
21762 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
21763 EFLAGS.getValueType().isInteger() &&
21764 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
21765 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
21766 EFLAGS.getNode()->getVTList(),
21767 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
21768 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
21769 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
21773 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
21774 // a zext and produces an all-ones bit which is more useful than 0/1 in some
21776 if (CC == X86::COND_B)
21777 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
21781 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
21782 if (Flags.getNode()) {
21783 SDValue Cond = DAG.getConstant(CC, MVT::i8);
21784 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
21790 // Optimize branch condition evaluation.
21792 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
21793 TargetLowering::DAGCombinerInfo &DCI,
21794 const X86Subtarget *Subtarget) {
21796 SDValue Chain = N->getOperand(0);
21797 SDValue Dest = N->getOperand(1);
21798 SDValue EFLAGS = N->getOperand(3);
21799 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
21803 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
21804 if (Flags.getNode()) {
21805 SDValue Cond = DAG.getConstant(CC, MVT::i8);
21806 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
21813 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
21814 SelectionDAG &DAG) {
21815 // Take advantage of vector comparisons producing 0 or -1 in each lane to
21816 // optimize away operation when it's from a constant.
21818 // The general transformation is:
21819 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
21820 // AND(VECTOR_CMP(x,y), constant2)
21821 // constant2 = UNARYOP(constant)
21823 // Early exit if this isn't a vector operation, the operand of the
21824 // unary operation isn't a bitwise AND, or if the sizes of the operations
21825 // aren't the same.
21826 EVT VT = N->getValueType(0);
21827 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
21828 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
21829 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
21832 // Now check that the other operand of the AND is a constant. We could
21833 // make the transformation for non-constant splats as well, but it's unclear
21834 // that would be a benefit as it would not eliminate any operations, just
21835 // perform one more step in scalar code before moving to the vector unit.
21836 if (BuildVectorSDNode *BV =
21837 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
21838 // Bail out if the vector isn't a constant.
21839 if (!BV->isConstant())
21842 // Everything checks out. Build up the new and improved node.
21844 EVT IntVT = BV->getValueType(0);
21845 // Create a new constant of the appropriate type for the transformed
21847 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
21848 // The AND node needs bitcasts to/from an integer vector type around it.
21849 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
21850 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
21851 N->getOperand(0)->getOperand(0), MaskConst);
21852 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
21859 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
21860 const X86TargetLowering *XTLI) {
21861 // First try to optimize away the conversion entirely when it's
21862 // conditionally from a constant. Vectors only.
21863 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
21864 if (Res != SDValue())
21867 // Now move on to more general possibilities.
21868 SDValue Op0 = N->getOperand(0);
21869 EVT InVT = Op0->getValueType(0);
21871 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
21872 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
21874 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
21875 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
21876 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
21879 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
21880 // a 32-bit target where SSE doesn't support i64->FP operations.
21881 if (Op0.getOpcode() == ISD::LOAD) {
21882 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
21883 EVT VT = Ld->getValueType(0);
21884 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
21885 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
21886 !XTLI->getSubtarget()->is64Bit() &&
21888 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
21889 Ld->getChain(), Op0, DAG);
21890 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
21897 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
21898 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
21899 X86TargetLowering::DAGCombinerInfo &DCI) {
21900 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
21901 // the result is either zero or one (depending on the input carry bit).
21902 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
21903 if (X86::isZeroNode(N->getOperand(0)) &&
21904 X86::isZeroNode(N->getOperand(1)) &&
21905 // We don't have a good way to replace an EFLAGS use, so only do this when
21907 SDValue(N, 1).use_empty()) {
21909 EVT VT = N->getValueType(0);
21910 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
21911 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
21912 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
21913 DAG.getConstant(X86::COND_B,MVT::i8),
21915 DAG.getConstant(1, VT));
21916 return DCI.CombineTo(N, Res1, CarryOut);
21922 // fold (add Y, (sete X, 0)) -> adc 0, Y
21923 // (add Y, (setne X, 0)) -> sbb -1, Y
21924 // (sub (sete X, 0), Y) -> sbb 0, Y
21925 // (sub (setne X, 0), Y) -> adc -1, Y
21926 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
21929 // Look through ZExts.
21930 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
21931 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
21934 SDValue SetCC = Ext.getOperand(0);
21935 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
21938 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
21939 if (CC != X86::COND_E && CC != X86::COND_NE)
21942 SDValue Cmp = SetCC.getOperand(1);
21943 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
21944 !X86::isZeroNode(Cmp.getOperand(1)) ||
21945 !Cmp.getOperand(0).getValueType().isInteger())
21948 SDValue CmpOp0 = Cmp.getOperand(0);
21949 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
21950 DAG.getConstant(1, CmpOp0.getValueType()));
21952 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
21953 if (CC == X86::COND_NE)
21954 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
21955 DL, OtherVal.getValueType(), OtherVal,
21956 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
21957 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
21958 DL, OtherVal.getValueType(), OtherVal,
21959 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
21962 /// PerformADDCombine - Do target-specific dag combines on integer adds.
21963 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
21964 const X86Subtarget *Subtarget) {
21965 EVT VT = N->getValueType(0);
21966 SDValue Op0 = N->getOperand(0);
21967 SDValue Op1 = N->getOperand(1);
21969 // Try to synthesize horizontal adds from adds of shuffles.
21970 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
21971 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
21972 isHorizontalBinOp(Op0, Op1, true))
21973 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
21975 return OptimizeConditionalInDecrement(N, DAG);
21978 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
21979 const X86Subtarget *Subtarget) {
21980 SDValue Op0 = N->getOperand(0);
21981 SDValue Op1 = N->getOperand(1);
21983 // X86 can't encode an immediate LHS of a sub. See if we can push the
21984 // negation into a preceding instruction.
21985 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
21986 // If the RHS of the sub is a XOR with one use and a constant, invert the
21987 // immediate. Then add one to the LHS of the sub so we can turn
21988 // X-Y -> X+~Y+1, saving one register.
21989 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
21990 isa<ConstantSDNode>(Op1.getOperand(1))) {
21991 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
21992 EVT VT = Op0.getValueType();
21993 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
21995 DAG.getConstant(~XorC, VT));
21996 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
21997 DAG.getConstant(C->getAPIntValue()+1, VT));
22001 // Try to synthesize horizontal adds from adds of shuffles.
22002 EVT VT = N->getValueType(0);
22003 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
22004 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
22005 isHorizontalBinOp(Op0, Op1, true))
22006 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
22008 return OptimizeConditionalInDecrement(N, DAG);
22011 /// performVZEXTCombine - Performs build vector combines
22012 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
22013 TargetLowering::DAGCombinerInfo &DCI,
22014 const X86Subtarget *Subtarget) {
22015 // (vzext (bitcast (vzext (x)) -> (vzext x)
22016 SDValue In = N->getOperand(0);
22017 while (In.getOpcode() == ISD::BITCAST)
22018 In = In.getOperand(0);
22020 if (In.getOpcode() != X86ISD::VZEXT)
22023 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
22027 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
22028 DAGCombinerInfo &DCI) const {
22029 SelectionDAG &DAG = DCI.DAG;
22030 switch (N->getOpcode()) {
22032 case ISD::EXTRACT_VECTOR_ELT:
22033 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
22035 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
22036 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
22037 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
22038 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
22039 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
22040 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
22043 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
22044 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
22045 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
22046 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
22047 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
22048 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
22049 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
22050 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
22051 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
22053 case X86ISD::FOR: return PerformFORCombine(N, DAG);
22055 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
22056 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
22057 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
22058 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
22059 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
22060 case ISD::ANY_EXTEND:
22061 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
22062 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
22063 case ISD::SIGN_EXTEND_INREG:
22064 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
22065 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
22066 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
22067 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
22068 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
22069 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
22070 case X86ISD::SHUFP: // Handle all target specific shuffles
22071 case X86ISD::PALIGNR:
22072 case X86ISD::UNPCKH:
22073 case X86ISD::UNPCKL:
22074 case X86ISD::MOVHLPS:
22075 case X86ISD::MOVLHPS:
22076 case X86ISD::PSHUFD:
22077 case X86ISD::PSHUFHW:
22078 case X86ISD::PSHUFLW:
22079 case X86ISD::MOVSS:
22080 case X86ISD::MOVSD:
22081 case X86ISD::VPERMILP:
22082 case X86ISD::VPERM2X128:
22083 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
22084 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
22085 case ISD::INTRINSIC_WO_CHAIN:
22086 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
22087 case X86ISD::INSERTPS:
22088 return PerformINSERTPSCombine(N, DAG, Subtarget);
22089 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
22095 /// isTypeDesirableForOp - Return true if the target has native support for
22096 /// the specified value type and it is 'desirable' to use the type for the
22097 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
22098 /// instruction encodings are longer and some i16 instructions are slow.
22099 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
22100 if (!isTypeLegal(VT))
22102 if (VT != MVT::i16)
22109 case ISD::SIGN_EXTEND:
22110 case ISD::ZERO_EXTEND:
22111 case ISD::ANY_EXTEND:
22124 /// IsDesirableToPromoteOp - This method query the target whether it is
22125 /// beneficial for dag combiner to promote the specified node. If true, it
22126 /// should return the desired promotion type by reference.
22127 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
22128 EVT VT = Op.getValueType();
22129 if (VT != MVT::i16)
22132 bool Promote = false;
22133 bool Commute = false;
22134 switch (Op.getOpcode()) {
22137 LoadSDNode *LD = cast<LoadSDNode>(Op);
22138 // If the non-extending load has a single use and it's not live out, then it
22139 // might be folded.
22140 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
22141 Op.hasOneUse()*/) {
22142 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
22143 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
22144 // The only case where we'd want to promote LOAD (rather then it being
22145 // promoted as an operand is when it's only use is liveout.
22146 if (UI->getOpcode() != ISD::CopyToReg)
22153 case ISD::SIGN_EXTEND:
22154 case ISD::ZERO_EXTEND:
22155 case ISD::ANY_EXTEND:
22160 SDValue N0 = Op.getOperand(0);
22161 // Look out for (store (shl (load), x)).
22162 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
22175 SDValue N0 = Op.getOperand(0);
22176 SDValue N1 = Op.getOperand(1);
22177 if (!Commute && MayFoldLoad(N1))
22179 // Avoid disabling potential load folding opportunities.
22180 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
22182 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
22192 //===----------------------------------------------------------------------===//
22193 // X86 Inline Assembly Support
22194 //===----------------------------------------------------------------------===//
22197 // Helper to match a string separated by whitespace.
22198 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
22199 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
22201 for (unsigned i = 0, e = args.size(); i != e; ++i) {
22202 StringRef piece(*args[i]);
22203 if (!s.startswith(piece)) // Check if the piece matches.
22206 s = s.substr(piece.size());
22207 StringRef::size_type pos = s.find_first_not_of(" \t");
22208 if (pos == 0) // We matched a prefix.
22216 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
22219 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
22221 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
22222 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
22223 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
22224 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
22226 if (AsmPieces.size() == 3)
22228 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
22235 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
22236 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
22238 std::string AsmStr = IA->getAsmString();
22240 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
22241 if (!Ty || Ty->getBitWidth() % 16 != 0)
22244 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
22245 SmallVector<StringRef, 4> AsmPieces;
22246 SplitString(AsmStr, AsmPieces, ";\n");
22248 switch (AsmPieces.size()) {
22249 default: return false;
22251 // FIXME: this should verify that we are targeting a 486 or better. If not,
22252 // we will turn this bswap into something that will be lowered to logical
22253 // ops instead of emitting the bswap asm. For now, we don't support 486 or
22254 // lower so don't worry about this.
22256 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
22257 matchAsm(AsmPieces[0], "bswapl", "$0") ||
22258 matchAsm(AsmPieces[0], "bswapq", "$0") ||
22259 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
22260 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
22261 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
22262 // No need to check constraints, nothing other than the equivalent of
22263 // "=r,0" would be valid here.
22264 return IntrinsicLowering::LowerToByteSwap(CI);
22267 // rorw $$8, ${0:w} --> llvm.bswap.i16
22268 if (CI->getType()->isIntegerTy(16) &&
22269 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
22270 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
22271 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
22273 const std::string &ConstraintsStr = IA->getConstraintString();
22274 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
22275 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
22276 if (clobbersFlagRegisters(AsmPieces))
22277 return IntrinsicLowering::LowerToByteSwap(CI);
22281 if (CI->getType()->isIntegerTy(32) &&
22282 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
22283 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
22284 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
22285 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
22287 const std::string &ConstraintsStr = IA->getConstraintString();
22288 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
22289 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
22290 if (clobbersFlagRegisters(AsmPieces))
22291 return IntrinsicLowering::LowerToByteSwap(CI);
22294 if (CI->getType()->isIntegerTy(64)) {
22295 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
22296 if (Constraints.size() >= 2 &&
22297 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
22298 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
22299 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
22300 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
22301 matchAsm(AsmPieces[1], "bswap", "%edx") &&
22302 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
22303 return IntrinsicLowering::LowerToByteSwap(CI);
22311 /// getConstraintType - Given a constraint letter, return the type of
22312 /// constraint it is for this target.
22313 X86TargetLowering::ConstraintType
22314 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
22315 if (Constraint.size() == 1) {
22316 switch (Constraint[0]) {
22327 return C_RegisterClass;
22351 return TargetLowering::getConstraintType(Constraint);
22354 /// Examine constraint type and operand type and determine a weight value.
22355 /// This object must already have been set up with the operand type
22356 /// and the current alternative constraint selected.
22357 TargetLowering::ConstraintWeight
22358 X86TargetLowering::getSingleConstraintMatchWeight(
22359 AsmOperandInfo &info, const char *constraint) const {
22360 ConstraintWeight weight = CW_Invalid;
22361 Value *CallOperandVal = info.CallOperandVal;
22362 // If we don't have a value, we can't do a match,
22363 // but allow it at the lowest weight.
22364 if (!CallOperandVal)
22366 Type *type = CallOperandVal->getType();
22367 // Look at the constraint type.
22368 switch (*constraint) {
22370 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
22381 if (CallOperandVal->getType()->isIntegerTy())
22382 weight = CW_SpecificReg;
22387 if (type->isFloatingPointTy())
22388 weight = CW_SpecificReg;
22391 if (type->isX86_MMXTy() && Subtarget->hasMMX())
22392 weight = CW_SpecificReg;
22396 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
22397 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
22398 weight = CW_Register;
22401 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
22402 if (C->getZExtValue() <= 31)
22403 weight = CW_Constant;
22407 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22408 if (C->getZExtValue() <= 63)
22409 weight = CW_Constant;
22413 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22414 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
22415 weight = CW_Constant;
22419 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22420 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
22421 weight = CW_Constant;
22425 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22426 if (C->getZExtValue() <= 3)
22427 weight = CW_Constant;
22431 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22432 if (C->getZExtValue() <= 0xff)
22433 weight = CW_Constant;
22438 if (dyn_cast<ConstantFP>(CallOperandVal)) {
22439 weight = CW_Constant;
22443 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22444 if ((C->getSExtValue() >= -0x80000000LL) &&
22445 (C->getSExtValue() <= 0x7fffffffLL))
22446 weight = CW_Constant;
22450 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22451 if (C->getZExtValue() <= 0xffffffff)
22452 weight = CW_Constant;
22459 /// LowerXConstraint - try to replace an X constraint, which matches anything,
22460 /// with another that has more specific requirements based on the type of the
22461 /// corresponding operand.
22462 const char *X86TargetLowering::
22463 LowerXConstraint(EVT ConstraintVT) const {
22464 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
22465 // 'f' like normal targets.
22466 if (ConstraintVT.isFloatingPoint()) {
22467 if (Subtarget->hasSSE2())
22469 if (Subtarget->hasSSE1())
22473 return TargetLowering::LowerXConstraint(ConstraintVT);
22476 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
22477 /// vector. If it is invalid, don't add anything to Ops.
22478 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
22479 std::string &Constraint,
22480 std::vector<SDValue>&Ops,
22481 SelectionDAG &DAG) const {
22484 // Only support length 1 constraints for now.
22485 if (Constraint.length() > 1) return;
22487 char ConstraintLetter = Constraint[0];
22488 switch (ConstraintLetter) {
22491 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22492 if (C->getZExtValue() <= 31) {
22493 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22499 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22500 if (C->getZExtValue() <= 63) {
22501 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22507 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22508 if (isInt<8>(C->getSExtValue())) {
22509 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22515 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22516 if (C->getZExtValue() <= 255) {
22517 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22523 // 32-bit signed value
22524 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22525 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
22526 C->getSExtValue())) {
22527 // Widen to 64 bits here to get it sign extended.
22528 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
22531 // FIXME gcc accepts some relocatable values here too, but only in certain
22532 // memory models; it's complicated.
22537 // 32-bit unsigned value
22538 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22539 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
22540 C->getZExtValue())) {
22541 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22545 // FIXME gcc accepts some relocatable values here too, but only in certain
22546 // memory models; it's complicated.
22550 // Literal immediates are always ok.
22551 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
22552 // Widen to 64 bits here to get it sign extended.
22553 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
22557 // In any sort of PIC mode addresses need to be computed at runtime by
22558 // adding in a register or some sort of table lookup. These can't
22559 // be used as immediates.
22560 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
22563 // If we are in non-pic codegen mode, we allow the address of a global (with
22564 // an optional displacement) to be used with 'i'.
22565 GlobalAddressSDNode *GA = nullptr;
22566 int64_t Offset = 0;
22568 // Match either (GA), (GA+C), (GA+C1+C2), etc.
22570 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
22571 Offset += GA->getOffset();
22573 } else if (Op.getOpcode() == ISD::ADD) {
22574 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
22575 Offset += C->getZExtValue();
22576 Op = Op.getOperand(0);
22579 } else if (Op.getOpcode() == ISD::SUB) {
22580 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
22581 Offset += -C->getZExtValue();
22582 Op = Op.getOperand(0);
22587 // Otherwise, this isn't something we can handle, reject it.
22591 const GlobalValue *GV = GA->getGlobal();
22592 // If we require an extra load to get this address, as in PIC mode, we
22593 // can't accept it.
22594 if (isGlobalStubReference(
22595 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
22598 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
22599 GA->getValueType(0), Offset);
22604 if (Result.getNode()) {
22605 Ops.push_back(Result);
22608 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
22611 std::pair<unsigned, const TargetRegisterClass*>
22612 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
22614 // First, see if this is a constraint that directly corresponds to an LLVM
22616 if (Constraint.size() == 1) {
22617 // GCC Constraint Letters
22618 switch (Constraint[0]) {
22620 // TODO: Slight differences here in allocation order and leaving
22621 // RIP in the class. Do they matter any more here than they do
22622 // in the normal allocation?
22623 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
22624 if (Subtarget->is64Bit()) {
22625 if (VT == MVT::i32 || VT == MVT::f32)
22626 return std::make_pair(0U, &X86::GR32RegClass);
22627 if (VT == MVT::i16)
22628 return std::make_pair(0U, &X86::GR16RegClass);
22629 if (VT == MVT::i8 || VT == MVT::i1)
22630 return std::make_pair(0U, &X86::GR8RegClass);
22631 if (VT == MVT::i64 || VT == MVT::f64)
22632 return std::make_pair(0U, &X86::GR64RegClass);
22635 // 32-bit fallthrough
22636 case 'Q': // Q_REGS
22637 if (VT == MVT::i32 || VT == MVT::f32)
22638 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
22639 if (VT == MVT::i16)
22640 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
22641 if (VT == MVT::i8 || VT == MVT::i1)
22642 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
22643 if (VT == MVT::i64)
22644 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
22646 case 'r': // GENERAL_REGS
22647 case 'l': // INDEX_REGS
22648 if (VT == MVT::i8 || VT == MVT::i1)
22649 return std::make_pair(0U, &X86::GR8RegClass);
22650 if (VT == MVT::i16)
22651 return std::make_pair(0U, &X86::GR16RegClass);
22652 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
22653 return std::make_pair(0U, &X86::GR32RegClass);
22654 return std::make_pair(0U, &X86::GR64RegClass);
22655 case 'R': // LEGACY_REGS
22656 if (VT == MVT::i8 || VT == MVT::i1)
22657 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
22658 if (VT == MVT::i16)
22659 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
22660 if (VT == MVT::i32 || !Subtarget->is64Bit())
22661 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
22662 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
22663 case 'f': // FP Stack registers.
22664 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
22665 // value to the correct fpstack register class.
22666 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
22667 return std::make_pair(0U, &X86::RFP32RegClass);
22668 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
22669 return std::make_pair(0U, &X86::RFP64RegClass);
22670 return std::make_pair(0U, &X86::RFP80RegClass);
22671 case 'y': // MMX_REGS if MMX allowed.
22672 if (!Subtarget->hasMMX()) break;
22673 return std::make_pair(0U, &X86::VR64RegClass);
22674 case 'Y': // SSE_REGS if SSE2 allowed
22675 if (!Subtarget->hasSSE2()) break;
22677 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
22678 if (!Subtarget->hasSSE1()) break;
22680 switch (VT.SimpleTy) {
22682 // Scalar SSE types.
22685 return std::make_pair(0U, &X86::FR32RegClass);
22688 return std::make_pair(0U, &X86::FR64RegClass);
22696 return std::make_pair(0U, &X86::VR128RegClass);
22704 return std::make_pair(0U, &X86::VR256RegClass);
22709 return std::make_pair(0U, &X86::VR512RegClass);
22715 // Use the default implementation in TargetLowering to convert the register
22716 // constraint into a member of a register class.
22717 std::pair<unsigned, const TargetRegisterClass*> Res;
22718 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
22720 // Not found as a standard register?
22722 // Map st(0) -> st(7) -> ST0
22723 if (Constraint.size() == 7 && Constraint[0] == '{' &&
22724 tolower(Constraint[1]) == 's' &&
22725 tolower(Constraint[2]) == 't' &&
22726 Constraint[3] == '(' &&
22727 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
22728 Constraint[5] == ')' &&
22729 Constraint[6] == '}') {
22731 Res.first = X86::ST0+Constraint[4]-'0';
22732 Res.second = &X86::RFP80RegClass;
22736 // GCC allows "st(0)" to be called just plain "st".
22737 if (StringRef("{st}").equals_lower(Constraint)) {
22738 Res.first = X86::ST0;
22739 Res.second = &X86::RFP80RegClass;
22744 if (StringRef("{flags}").equals_lower(Constraint)) {
22745 Res.first = X86::EFLAGS;
22746 Res.second = &X86::CCRRegClass;
22750 // 'A' means EAX + EDX.
22751 if (Constraint == "A") {
22752 Res.first = X86::EAX;
22753 Res.second = &X86::GR32_ADRegClass;
22759 // Otherwise, check to see if this is a register class of the wrong value
22760 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
22761 // turn into {ax},{dx}.
22762 if (Res.second->hasType(VT))
22763 return Res; // Correct type already, nothing to do.
22765 // All of the single-register GCC register classes map their values onto
22766 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
22767 // really want an 8-bit or 32-bit register, map to the appropriate register
22768 // class and return the appropriate register.
22769 if (Res.second == &X86::GR16RegClass) {
22770 if (VT == MVT::i8 || VT == MVT::i1) {
22771 unsigned DestReg = 0;
22772 switch (Res.first) {
22774 case X86::AX: DestReg = X86::AL; break;
22775 case X86::DX: DestReg = X86::DL; break;
22776 case X86::CX: DestReg = X86::CL; break;
22777 case X86::BX: DestReg = X86::BL; break;
22780 Res.first = DestReg;
22781 Res.second = &X86::GR8RegClass;
22783 } else if (VT == MVT::i32 || VT == MVT::f32) {
22784 unsigned DestReg = 0;
22785 switch (Res.first) {
22787 case X86::AX: DestReg = X86::EAX; break;
22788 case X86::DX: DestReg = X86::EDX; break;
22789 case X86::CX: DestReg = X86::ECX; break;
22790 case X86::BX: DestReg = X86::EBX; break;
22791 case X86::SI: DestReg = X86::ESI; break;
22792 case X86::DI: DestReg = X86::EDI; break;
22793 case X86::BP: DestReg = X86::EBP; break;
22794 case X86::SP: DestReg = X86::ESP; break;
22797 Res.first = DestReg;
22798 Res.second = &X86::GR32RegClass;
22800 } else if (VT == MVT::i64 || VT == MVT::f64) {
22801 unsigned DestReg = 0;
22802 switch (Res.first) {
22804 case X86::AX: DestReg = X86::RAX; break;
22805 case X86::DX: DestReg = X86::RDX; break;
22806 case X86::CX: DestReg = X86::RCX; break;
22807 case X86::BX: DestReg = X86::RBX; break;
22808 case X86::SI: DestReg = X86::RSI; break;
22809 case X86::DI: DestReg = X86::RDI; break;
22810 case X86::BP: DestReg = X86::RBP; break;
22811 case X86::SP: DestReg = X86::RSP; break;
22814 Res.first = DestReg;
22815 Res.second = &X86::GR64RegClass;
22818 } else if (Res.second == &X86::FR32RegClass ||
22819 Res.second == &X86::FR64RegClass ||
22820 Res.second == &X86::VR128RegClass ||
22821 Res.second == &X86::VR256RegClass ||
22822 Res.second == &X86::FR32XRegClass ||
22823 Res.second == &X86::FR64XRegClass ||
22824 Res.second == &X86::VR128XRegClass ||
22825 Res.second == &X86::VR256XRegClass ||
22826 Res.second == &X86::VR512RegClass) {
22827 // Handle references to XMM physical registers that got mapped into the
22828 // wrong class. This can happen with constraints like {xmm0} where the
22829 // target independent register mapper will just pick the first match it can
22830 // find, ignoring the required type.
22832 if (VT == MVT::f32 || VT == MVT::i32)
22833 Res.second = &X86::FR32RegClass;
22834 else if (VT == MVT::f64 || VT == MVT::i64)
22835 Res.second = &X86::FR64RegClass;
22836 else if (X86::VR128RegClass.hasType(VT))
22837 Res.second = &X86::VR128RegClass;
22838 else if (X86::VR256RegClass.hasType(VT))
22839 Res.second = &X86::VR256RegClass;
22840 else if (X86::VR512RegClass.hasType(VT))
22841 Res.second = &X86::VR512RegClass;
22847 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
22849 // Scaling factors are not free at all.
22850 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
22851 // will take 2 allocations in the out of order engine instead of 1
22852 // for plain addressing mode, i.e. inst (reg1).
22854 // vaddps (%rsi,%drx), %ymm0, %ymm1
22855 // Requires two allocations (one for the load, one for the computation)
22857 // vaddps (%rsi), %ymm0, %ymm1
22858 // Requires just 1 allocation, i.e., freeing allocations for other operations
22859 // and having less micro operations to execute.
22861 // For some X86 architectures, this is even worse because for instance for
22862 // stores, the complex addressing mode forces the instruction to use the
22863 // "load" ports instead of the dedicated "store" port.
22864 // E.g., on Haswell:
22865 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
22866 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
22867 if (isLegalAddressingMode(AM, Ty))
22868 // Scale represents reg2 * scale, thus account for 1
22869 // as soon as we use a second register.
22870 return AM.Scale != 0;
22874 bool X86TargetLowering::isTargetFTOL() const {
22875 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();