1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
71 const X86Subtarget &STI)
72 : TargetLowering(TM), Subtarget(&STI) {
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
77 // Set up the TargetLowering object.
78 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
203 // are Legal, f80 is custom lowered.
204 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
207 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
209 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
210 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
212 if (X86ScalarSSEf32) {
213 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
214 // f32 and f64 cases are Legal, f80 case is not
215 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
221 // Handle FP_TO_UINT by promoting the destination to a larger signed
223 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
224 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
225 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
227 if (Subtarget->is64Bit()) {
228 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
229 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
230 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
233 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
234 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 } else if (!Subtarget->useSoftFloat()) {
237 // Since AVX is a superset of SSE3, only check for SSE here.
238 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
239 // Expand FP_TO_UINT into a select.
240 // FIXME: We would like to use a Custom expander here eventually to do
241 // the optimal thing for SSE vs. the default expansion in the legalizer.
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
244 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
249 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
252 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
253 if (!X86ScalarSSEf64) {
254 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
255 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
258 // Without SSE, i64->f64 goes through memory.
259 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
263 // Scalar integer divide and remainder are lowered to use operations that
264 // produce two results, to match the available instructions. This exposes
265 // the two-result form to trivial CSE, which is able to combine x/y and x%y
266 // into a single instruction.
268 // Scalar integer multiply-high is also lowered to use two-result
269 // operations, to match the available instructions. However, plain multiply
270 // (low) operations are left as Legal, as there are single-result
271 // instructions for this in x86. Using the two-result multiply instructions
272 // when both high and low results are needed must be arranged by dagcombine.
273 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
275 setOperationAction(ISD::MULHS, VT, Expand);
276 setOperationAction(ISD::MULHU, VT, Expand);
277 setOperationAction(ISD::SDIV, VT, Expand);
278 setOperationAction(ISD::UDIV, VT, Expand);
279 setOperationAction(ISD::SREM, VT, Expand);
280 setOperationAction(ISD::UREM, VT, Expand);
282 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
283 setOperationAction(ISD::ADDC, VT, Custom);
284 setOperationAction(ISD::ADDE, VT, Custom);
285 setOperationAction(ISD::SUBC, VT, Custom);
286 setOperationAction(ISD::SUBE, VT, Custom);
289 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
290 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
291 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
292 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
293 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
294 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
295 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
296 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
298 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
299 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
300 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
301 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
305 if (Subtarget->is64Bit())
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
307 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
308 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
309 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
310 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
312 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
313 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
314 // is. We should promote the value to 64-bits to solve this.
315 // This is what the CRT headers do - `fmodf` is an inline header
316 // function casting to f64 and calling `fmod`.
317 setOperationAction(ISD::FREM , MVT::f32 , Promote);
319 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->isTarget64BitLP64()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit()) {
502 setOperationAction(ISD::VAARG , MVT::Other, Custom);
503 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
505 // TargetInfo::CharPtrBuiltinVaList
506 setOperationAction(ISD::VAARG , MVT::Other, Expand);
507 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
510 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
511 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
513 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
515 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
516 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
517 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
519 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
520 // f32 and f64 use SSE.
521 // Set up the FP register classes.
522 addRegisterClass(MVT::f32, &X86::FR32RegClass);
523 addRegisterClass(MVT::f64, &X86::FR64RegClass);
525 // Use ANDPD to simulate FABS.
526 setOperationAction(ISD::FABS , MVT::f64, Custom);
527 setOperationAction(ISD::FABS , MVT::f32, Custom);
529 // Use XORP to simulate FNEG.
530 setOperationAction(ISD::FNEG , MVT::f64, Custom);
531 setOperationAction(ISD::FNEG , MVT::f32, Custom);
533 // Use ANDPD and ORPD to simulate FCOPYSIGN.
534 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
535 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
537 // Lower this to FGETSIGNx86 plus an AND.
538 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
539 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
541 // We don't support sin/cos/fmod
542 setOperationAction(ISD::FSIN , MVT::f64, Expand);
543 setOperationAction(ISD::FCOS , MVT::f64, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
545 setOperationAction(ISD::FSIN , MVT::f32, Expand);
546 setOperationAction(ISD::FCOS , MVT::f32, Expand);
547 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
549 // Expand FP immediates into loads from the stack, except for the special
551 addLegalFPImmediate(APFloat(+0.0)); // xorpd
552 addLegalFPImmediate(APFloat(+0.0f)); // xorps
553 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
554 // Use SSE for f32, x87 for f64.
555 // Set up the FP register classes.
556 addRegisterClass(MVT::f32, &X86::FR32RegClass);
557 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
559 // Use ANDPS to simulate FABS.
560 setOperationAction(ISD::FABS , MVT::f32, Custom);
562 // Use XORP to simulate FNEG.
563 setOperationAction(ISD::FNEG , MVT::f32, Custom);
565 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
567 // Use ANDPS and ORPS to simulate FCOPYSIGN.
568 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
569 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
571 // We don't support sin/cos/fmod
572 setOperationAction(ISD::FSIN , MVT::f32, Expand);
573 setOperationAction(ISD::FCOS , MVT::f32, Expand);
574 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
576 // Special cases we handle for FP constants.
577 addLegalFPImmediate(APFloat(+0.0f)); // xorps
578 addLegalFPImmediate(APFloat(+0.0)); // FLD0
579 addLegalFPImmediate(APFloat(+1.0)); // FLD1
580 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
581 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
583 if (!TM.Options.UnsafeFPMath) {
584 setOperationAction(ISD::FSIN , MVT::f64, Expand);
585 setOperationAction(ISD::FCOS , MVT::f64, Expand);
586 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
588 } else if (!Subtarget->useSoftFloat()) {
589 // f32 and f64 in x87.
590 // Set up the FP register classes.
591 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
592 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
594 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
595 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
596 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
599 if (!TM.Options.UnsafeFPMath) {
600 setOperationAction(ISD::FSIN , MVT::f64, Expand);
601 setOperationAction(ISD::FSIN , MVT::f32, Expand);
602 setOperationAction(ISD::FCOS , MVT::f64, Expand);
603 setOperationAction(ISD::FCOS , MVT::f32, Expand);
604 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
607 addLegalFPImmediate(APFloat(+0.0)); // FLD0
608 addLegalFPImmediate(APFloat(+1.0)); // FLD1
609 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
610 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
611 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
612 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
613 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
614 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
617 // We don't support FMA.
618 setOperationAction(ISD::FMA, MVT::f64, Expand);
619 setOperationAction(ISD::FMA, MVT::f32, Expand);
621 // Long double always uses X87.
622 if (!Subtarget->useSoftFloat()) {
623 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
624 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
625 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
627 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
628 addLegalFPImmediate(TmpFlt); // FLD0
630 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
633 APFloat TmpFlt2(+1.0);
634 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
636 addLegalFPImmediate(TmpFlt2); // FLD1
637 TmpFlt2.changeSign();
638 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
641 if (!TM.Options.UnsafeFPMath) {
642 setOperationAction(ISD::FSIN , MVT::f80, Expand);
643 setOperationAction(ISD::FCOS , MVT::f80, Expand);
644 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
647 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
648 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
649 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
650 setOperationAction(ISD::FRINT, MVT::f80, Expand);
651 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
652 setOperationAction(ISD::FMA, MVT::f80, Expand);
655 // Always use a library call for pow.
656 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
657 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
660 setOperationAction(ISD::FLOG, MVT::f80, Expand);
661 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
663 setOperationAction(ISD::FEXP, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
665 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
666 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
668 // First set operation action for all vector types to either promote
669 // (for widening) or expand (for scalarization). Then we will selectively
670 // turn on ones that can be effectively codegen'd.
671 for (MVT VT : MVT::vector_valuetypes()) {
672 setOperationAction(ISD::ADD , VT, Expand);
673 setOperationAction(ISD::SUB , VT, Expand);
674 setOperationAction(ISD::FADD, VT, Expand);
675 setOperationAction(ISD::FNEG, VT, Expand);
676 setOperationAction(ISD::FSUB, VT, Expand);
677 setOperationAction(ISD::MUL , VT, Expand);
678 setOperationAction(ISD::FMUL, VT, Expand);
679 setOperationAction(ISD::SDIV, VT, Expand);
680 setOperationAction(ISD::UDIV, VT, Expand);
681 setOperationAction(ISD::FDIV, VT, Expand);
682 setOperationAction(ISD::SREM, VT, Expand);
683 setOperationAction(ISD::UREM, VT, Expand);
684 setOperationAction(ISD::LOAD, VT, Expand);
685 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
686 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
687 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
688 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
689 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::FABS, VT, Expand);
691 setOperationAction(ISD::FSIN, VT, Expand);
692 setOperationAction(ISD::FSINCOS, VT, Expand);
693 setOperationAction(ISD::FCOS, VT, Expand);
694 setOperationAction(ISD::FSINCOS, VT, Expand);
695 setOperationAction(ISD::FREM, VT, Expand);
696 setOperationAction(ISD::FMA, VT, Expand);
697 setOperationAction(ISD::FPOWI, VT, Expand);
698 setOperationAction(ISD::FSQRT, VT, Expand);
699 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
700 setOperationAction(ISD::FFLOOR, VT, Expand);
701 setOperationAction(ISD::FCEIL, VT, Expand);
702 setOperationAction(ISD::FTRUNC, VT, Expand);
703 setOperationAction(ISD::FRINT, VT, Expand);
704 setOperationAction(ISD::FNEARBYINT, VT, Expand);
705 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
706 setOperationAction(ISD::MULHS, VT, Expand);
707 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
708 setOperationAction(ISD::MULHU, VT, Expand);
709 setOperationAction(ISD::SDIVREM, VT, Expand);
710 setOperationAction(ISD::UDIVREM, VT, Expand);
711 setOperationAction(ISD::FPOW, VT, Expand);
712 setOperationAction(ISD::CTPOP, VT, Expand);
713 setOperationAction(ISD::CTTZ, VT, Expand);
714 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
715 setOperationAction(ISD::CTLZ, VT, Expand);
716 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
717 setOperationAction(ISD::SHL, VT, Expand);
718 setOperationAction(ISD::SRA, VT, Expand);
719 setOperationAction(ISD::SRL, VT, Expand);
720 setOperationAction(ISD::ROTL, VT, Expand);
721 setOperationAction(ISD::ROTR, VT, Expand);
722 setOperationAction(ISD::BSWAP, VT, Expand);
723 setOperationAction(ISD::SETCC, VT, Expand);
724 setOperationAction(ISD::FLOG, VT, Expand);
725 setOperationAction(ISD::FLOG2, VT, Expand);
726 setOperationAction(ISD::FLOG10, VT, Expand);
727 setOperationAction(ISD::FEXP, VT, Expand);
728 setOperationAction(ISD::FEXP2, VT, Expand);
729 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
730 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
731 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
732 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
734 setOperationAction(ISD::TRUNCATE, VT, Expand);
735 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
736 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
737 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
738 setOperationAction(ISD::VSELECT, VT, Expand);
739 setOperationAction(ISD::SELECT_CC, VT, Expand);
740 for (MVT InnerVT : MVT::vector_valuetypes()) {
741 setTruncStoreAction(InnerVT, VT, Expand);
743 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
744 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
746 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
747 // types, we have to deal with them whether we ask for Expansion or not.
748 // Setting Expand causes its own optimisation problems though, so leave
750 if (VT.getVectorElementType() == MVT::i1)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
753 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
754 // split/scalarized right now.
755 if (VT.getVectorElementType() == MVT::f16)
756 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
760 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
761 // with -msoft-float, disable use of MMX as well.
762 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
763 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
764 // No operations on x86mmx supported, everything uses intrinsics.
767 // MMX-sized vectors (other than x86mmx) are expected to be expanded
768 // into smaller operations.
769 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
770 setOperationAction(ISD::MULHS, MMXTy, Expand);
771 setOperationAction(ISD::AND, MMXTy, Expand);
772 setOperationAction(ISD::OR, MMXTy, Expand);
773 setOperationAction(ISD::XOR, MMXTy, Expand);
774 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
775 setOperationAction(ISD::SELECT, MMXTy, Expand);
776 setOperationAction(ISD::BITCAST, MMXTy, Expand);
778 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
780 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
781 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
783 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
784 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
785 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
786 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
787 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
788 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
789 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
790 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
791 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
792 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
793 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
794 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
795 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
796 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
799 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
800 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
802 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
803 // registers cannot be used even for integer operations.
804 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
805 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
806 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
807 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
809 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
810 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
811 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
812 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
813 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
814 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
815 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
816 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
817 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
819 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
820 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
821 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
822 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
823 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
824 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
825 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
826 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
827 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
828 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
829 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
830 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
831 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
833 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
834 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
835 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
836 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
838 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
839 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
840 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
841 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
843 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
849 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
854 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
857 // ISD::CTTZ v2i64 - scalarization is faster.
858 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
861 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
863 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
864 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
865 MVT VT = (MVT::SimpleValueType)i;
866 // Do not attempt to custom lower non-power-of-2 vectors
867 if (!isPowerOf2_32(VT.getVectorNumElements()))
869 // Do not attempt to custom lower non-128-bit vectors
870 if (!VT.is128BitVector())
872 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
873 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
874 setOperationAction(ISD::VSELECT, VT, Custom);
875 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
878 // We support custom legalizing of sext and anyext loads for specific
879 // memory vector types which we can load as a scalar (or sequence of
880 // scalars) and extend in-register to a legal 128-bit vector type. For sext
881 // loads these must work with a single scalar load.
882 for (MVT VT : MVT::integer_vector_valuetypes()) {
883 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
886 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
887 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
888 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
889 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
890 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
891 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
898 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
899 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
901 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
903 if (Subtarget->is64Bit()) {
904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
905 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
908 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
909 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
910 MVT VT = (MVT::SimpleValueType)i;
912 // Do not attempt to promote non-128-bit vectors
913 if (!VT.is128BitVector())
916 setOperationAction(ISD::AND, VT, Promote);
917 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
918 setOperationAction(ISD::OR, VT, Promote);
919 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
920 setOperationAction(ISD::XOR, VT, Promote);
921 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
922 setOperationAction(ISD::LOAD, VT, Promote);
923 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
924 setOperationAction(ISD::SELECT, VT, Promote);
925 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
928 // Custom lower v2i64 and v2f64 selects.
929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
937 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
939 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
940 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
941 // As there is no 64-bit GPR available, we need build a special custom
942 // sequence to convert from v2i32 to v2f32.
943 if (!Subtarget->is64Bit())
944 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
946 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
947 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
949 for (MVT VT : MVT::fp_vector_valuetypes())
950 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
952 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
953 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
954 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
957 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
958 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
959 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
960 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
961 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
962 setOperationAction(ISD::FRINT, RoundedTy, Legal);
963 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
966 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
967 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
968 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
969 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
970 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
971 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
972 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
973 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
975 // FIXME: Do we need to handle scalar-to-vector here?
976 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
978 // We directly match byte blends in the backend as they match the VSELECT
980 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
982 // SSE41 brings specific instructions for doing vector sign extend even in
983 // cases where we don't have SRA.
984 for (MVT VT : MVT::integer_vector_valuetypes()) {
985 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
986 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
987 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
990 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
991 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
992 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
993 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
994 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
995 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
996 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
998 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
999 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1000 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1001 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1002 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1003 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1005 // i8 and i16 vectors are custom because the source register and source
1006 // source memory operand types are not the same width. f32 vectors are
1007 // custom since the immediate controlling the insert encodes additional
1009 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1012 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1015 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1016 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1019 // FIXME: these should be Legal, but that's only for the case where
1020 // the index is constant. For now custom expand to deal with that.
1021 if (Subtarget->is64Bit()) {
1022 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1027 if (Subtarget->hasSSE2()) {
1028 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1029 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1030 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1032 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1035 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1036 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1038 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1039 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1041 // In the customized shift lowering, the legal cases in AVX2 will be
1043 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1044 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1046 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1047 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1049 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1050 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1053 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1054 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1059 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1061 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1063 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1065 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1075 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1076 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1078 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1088 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1089 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1091 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1092 // even though v8i16 is a legal type.
1093 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1094 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1095 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1097 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1098 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1099 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1102 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1104 for (MVT VT : MVT::fp_vector_valuetypes())
1105 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1107 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1108 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1110 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1111 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1113 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1114 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1119 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1122 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1123 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1125 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1126 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1127 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1129 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1130 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1131 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1133 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1134 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1135 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1136 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1138 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1139 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1140 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1141 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1143 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1144 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1145 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1146 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1147 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1148 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1149 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1150 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1152 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1153 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1154 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1155 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1156 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1157 setOperationAction(ISD::FMA, MVT::f32, Legal);
1158 setOperationAction(ISD::FMA, MVT::f64, Legal);
1161 if (Subtarget->hasInt256()) {
1162 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1163 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1164 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1165 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1167 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1168 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1169 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1170 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1172 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1173 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1174 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1175 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1177 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1178 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1179 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1180 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1182 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1183 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1184 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1185 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1186 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1187 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1188 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1189 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1190 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1191 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1192 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1193 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1195 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1196 // when we have a 256bit-wide blend with immediate.
1197 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1199 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1201 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1202 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1203 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1204 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1205 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1209 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1210 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1212 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1214 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1215 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1216 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1217 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1220 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1221 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1224 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1225 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1226 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1231 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1232 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1233 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1234 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1235 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1238 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1239 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1240 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1243 // In the customized shift lowering, the legal cases in AVX2 will be
1245 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1246 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1248 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1254 // Custom lower several nodes for 256-bit types.
1255 for (MVT VT : MVT::vector_valuetypes()) {
1256 if (VT.getScalarSizeInBits() >= 32) {
1257 setOperationAction(ISD::MLOAD, VT, Legal);
1258 setOperationAction(ISD::MSTORE, VT, Legal);
1260 // Extract subvector is special because the value type
1261 // (result) is 128-bit but the source is 256-bit wide.
1262 if (VT.is128BitVector()) {
1263 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1265 // Do not attempt to custom lower other non-256-bit vectors
1266 if (!VT.is256BitVector())
1269 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1270 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1271 setOperationAction(ISD::VSELECT, VT, Custom);
1272 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1274 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1275 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1276 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1279 if (Subtarget->hasInt256())
1280 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1282 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1283 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1284 MVT VT = (MVT::SimpleValueType)i;
1286 // Do not attempt to promote non-256-bit vectors
1287 if (!VT.is256BitVector())
1290 setOperationAction(ISD::AND, VT, Promote);
1291 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1292 setOperationAction(ISD::OR, VT, Promote);
1293 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1294 setOperationAction(ISD::XOR, VT, Promote);
1295 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1296 setOperationAction(ISD::LOAD, VT, Promote);
1297 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1298 setOperationAction(ISD::SELECT, VT, Promote);
1299 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1303 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1304 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1309 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1310 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1311 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1313 for (MVT VT : MVT::fp_vector_valuetypes())
1314 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1316 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1317 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1318 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1319 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1320 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1321 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1322 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1323 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1324 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1325 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1326 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1327 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1329 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1330 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1331 setOperationAction(ISD::XOR, MVT::i1, Legal);
1332 setOperationAction(ISD::OR, MVT::i1, Legal);
1333 setOperationAction(ISD::AND, MVT::i1, Legal);
1334 setOperationAction(ISD::SUB, MVT::i1, Custom);
1335 setOperationAction(ISD::ADD, MVT::i1, Custom);
1336 setOperationAction(ISD::MUL, MVT::i1, Custom);
1337 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1338 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1339 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1340 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1341 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1343 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1344 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1345 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1346 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1347 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1348 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1350 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1352 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1353 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1354 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1355 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1356 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1357 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1359 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1360 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1361 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1362 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1363 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1364 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1365 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1366 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1367 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1368 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1369 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1370 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1371 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1372 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1373 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1374 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1376 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1377 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1378 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1379 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1380 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1381 if (Subtarget->hasVLX()){
1382 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1383 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1384 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1385 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1386 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1388 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1389 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1390 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1391 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1392 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1394 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1395 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1396 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1397 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1398 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1399 if (Subtarget->hasDQI()) {
1400 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1401 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1403 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1404 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1405 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1406 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1407 if (Subtarget->hasVLX()) {
1408 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1409 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1412 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1418 if (Subtarget->hasVLX()) {
1419 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1421 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1422 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1425 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1426 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1428 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1434 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1439 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1440 if (Subtarget->hasDQI()) {
1441 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1442 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1444 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1445 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1446 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1447 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1448 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1449 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1450 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1451 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1452 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1453 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1455 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1457 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1458 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1461 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1464 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1466 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1467 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1468 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1469 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1470 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1471 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1472 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1475 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1476 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1478 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1479 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1480 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1481 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1482 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1483 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1484 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1485 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1487 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1488 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1490 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1491 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1493 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1495 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1496 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1498 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1499 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1501 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1502 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1504 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1505 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1506 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1507 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1508 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1509 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1511 if (Subtarget->hasCDI()) {
1512 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1513 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1517 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1518 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1519 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1520 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1521 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Custom);
1522 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Custom);
1523 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Custom);
1524 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Custom);
1526 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1527 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1529 if (Subtarget->hasVLX()) {
1530 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1531 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1532 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1533 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1534 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1535 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1536 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1537 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1539 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1540 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1541 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1542 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1544 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1545 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1546 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1547 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1548 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Custom);
1549 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Custom);
1550 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Custom);
1551 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Custom);
1553 } // Subtarget->hasCDI()
1555 if (Subtarget->hasDQI()) {
1556 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1557 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1558 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1560 // Custom lower several nodes.
1561 for (MVT VT : MVT::vector_valuetypes()) {
1562 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1564 setOperationAction(ISD::AND, VT, Legal);
1565 setOperationAction(ISD::OR, VT, Legal);
1566 setOperationAction(ISD::XOR, VT, Legal);
1568 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1569 setOperationAction(ISD::MGATHER, VT, Custom);
1570 setOperationAction(ISD::MSCATTER, VT, Custom);
1572 // Extract subvector is special because the value type
1573 // (result) is 256/128-bit but the source is 512-bit wide.
1574 if (VT.is128BitVector() || VT.is256BitVector()) {
1575 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1577 if (VT.getVectorElementType() == MVT::i1)
1578 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1580 // Do not attempt to custom lower other non-512-bit vectors
1581 if (!VT.is512BitVector())
1584 if (EltSize >= 32) {
1585 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1586 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1587 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1588 setOperationAction(ISD::VSELECT, VT, Legal);
1589 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1590 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1591 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1592 setOperationAction(ISD::MLOAD, VT, Legal);
1593 setOperationAction(ISD::MSTORE, VT, Legal);
1596 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1597 MVT VT = (MVT::SimpleValueType)i;
1599 // Do not attempt to promote non-512-bit vectors.
1600 if (!VT.is512BitVector())
1603 setOperationAction(ISD::SELECT, VT, Promote);
1604 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1608 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1609 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1610 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1612 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1613 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1615 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1616 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1617 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1618 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1619 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1620 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1621 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1622 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1623 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1624 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1625 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1626 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Legal);
1627 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Legal);
1628 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1629 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1630 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1631 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1632 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1633 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1634 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1635 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1636 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1637 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1638 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1639 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1640 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1641 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1642 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1643 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1644 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1645 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1646 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1647 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1648 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1649 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1650 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1651 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1652 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1653 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1654 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1655 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1657 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1658 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1659 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1660 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1661 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1662 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1663 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1664 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1666 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1667 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1668 if (Subtarget->hasVLX())
1669 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1671 if (Subtarget->hasCDI()) {
1672 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1673 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1674 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Custom);
1675 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);
1678 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1679 const MVT VT = (MVT::SimpleValueType)i;
1681 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1683 // Do not attempt to promote non-512-bit vectors.
1684 if (!VT.is512BitVector())
1688 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1689 setOperationAction(ISD::VSELECT, VT, Legal);
1694 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1695 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1696 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1698 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1699 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1700 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1701 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1702 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1703 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1704 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1705 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1706 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1707 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1708 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1709 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1711 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1712 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1713 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1714 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1715 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1716 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1717 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1718 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1720 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1721 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1722 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1723 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1724 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1725 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1726 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1727 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1730 // We want to custom lower some of our intrinsics.
1731 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1732 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1733 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1734 if (!Subtarget->is64Bit())
1735 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1737 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1738 // handle type legalization for these operations here.
1740 // FIXME: We really should do custom legalization for addition and
1741 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1742 // than generic legalization for 64-bit multiplication-with-overflow, though.
1743 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1744 // Add/Sub/Mul with overflow operations are custom lowered.
1746 setOperationAction(ISD::SADDO, VT, Custom);
1747 setOperationAction(ISD::UADDO, VT, Custom);
1748 setOperationAction(ISD::SSUBO, VT, Custom);
1749 setOperationAction(ISD::USUBO, VT, Custom);
1750 setOperationAction(ISD::SMULO, VT, Custom);
1751 setOperationAction(ISD::UMULO, VT, Custom);
1754 if (!Subtarget->is64Bit()) {
1755 // These libcalls are not available in 32-bit.
1756 setLibcallName(RTLIB::SHL_I128, nullptr);
1757 setLibcallName(RTLIB::SRL_I128, nullptr);
1758 setLibcallName(RTLIB::SRA_I128, nullptr);
1761 // Combine sin / cos into one node or libcall if possible.
1762 if (Subtarget->hasSinCos()) {
1763 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1764 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1765 if (Subtarget->isTargetDarwin()) {
1766 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1767 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1768 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1769 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1773 if (Subtarget->isTargetWin64()) {
1774 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1775 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1776 setOperationAction(ISD::SREM, MVT::i128, Custom);
1777 setOperationAction(ISD::UREM, MVT::i128, Custom);
1778 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1779 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1782 // We have target-specific dag combine patterns for the following nodes:
1783 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1784 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1785 setTargetDAGCombine(ISD::BITCAST);
1786 setTargetDAGCombine(ISD::VSELECT);
1787 setTargetDAGCombine(ISD::SELECT);
1788 setTargetDAGCombine(ISD::SHL);
1789 setTargetDAGCombine(ISD::SRA);
1790 setTargetDAGCombine(ISD::SRL);
1791 setTargetDAGCombine(ISD::OR);
1792 setTargetDAGCombine(ISD::AND);
1793 setTargetDAGCombine(ISD::ADD);
1794 setTargetDAGCombine(ISD::FADD);
1795 setTargetDAGCombine(ISD::FSUB);
1796 setTargetDAGCombine(ISD::FMA);
1797 setTargetDAGCombine(ISD::SUB);
1798 setTargetDAGCombine(ISD::LOAD);
1799 setTargetDAGCombine(ISD::MLOAD);
1800 setTargetDAGCombine(ISD::STORE);
1801 setTargetDAGCombine(ISD::MSTORE);
1802 setTargetDAGCombine(ISD::ZERO_EXTEND);
1803 setTargetDAGCombine(ISD::ANY_EXTEND);
1804 setTargetDAGCombine(ISD::SIGN_EXTEND);
1805 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1806 setTargetDAGCombine(ISD::SINT_TO_FP);
1807 setTargetDAGCombine(ISD::UINT_TO_FP);
1808 setTargetDAGCombine(ISD::SETCC);
1809 setTargetDAGCombine(ISD::BUILD_VECTOR);
1810 setTargetDAGCombine(ISD::MUL);
1811 setTargetDAGCombine(ISD::XOR);
1813 computeRegisterProperties(Subtarget->getRegisterInfo());
1815 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1816 MaxStoresPerMemsetOptSize = 8;
1817 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1818 MaxStoresPerMemcpyOptSize = 4;
1819 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1820 MaxStoresPerMemmoveOptSize = 4;
1821 setPrefLoopAlignment(4); // 2^4 bytes.
1823 // A predictable cmov does not hurt on an in-order CPU.
1824 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1825 PredictableSelectIsExpensive = !Subtarget->isAtom();
1826 EnableExtLdPromotion = true;
1827 setPrefFunctionAlignment(4); // 2^4 bytes.
1829 verifyIntrinsicTables();
1832 // This has so far only been implemented for 64-bit MachO.
1833 bool X86TargetLowering::useLoadStackGuardNode() const {
1834 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1837 TargetLoweringBase::LegalizeTypeAction
1838 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1839 if (ExperimentalVectorWideningLegalization &&
1840 VT.getVectorNumElements() != 1 &&
1841 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1842 return TypeWidenVector;
1844 return TargetLoweringBase::getPreferredVectorAction(VT);
1847 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1850 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1852 const unsigned NumElts = VT.getVectorNumElements();
1853 const EVT EltVT = VT.getVectorElementType();
1854 if (VT.is512BitVector()) {
1855 if (Subtarget->hasAVX512())
1856 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1857 EltVT == MVT::f32 || EltVT == MVT::f64)
1859 case 8: return MVT::v8i1;
1860 case 16: return MVT::v16i1;
1862 if (Subtarget->hasBWI())
1863 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1865 case 32: return MVT::v32i1;
1866 case 64: return MVT::v64i1;
1870 if (VT.is256BitVector() || VT.is128BitVector()) {
1871 if (Subtarget->hasVLX())
1872 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1873 EltVT == MVT::f32 || EltVT == MVT::f64)
1875 case 2: return MVT::v2i1;
1876 case 4: return MVT::v4i1;
1877 case 8: return MVT::v8i1;
1879 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1880 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1882 case 8: return MVT::v8i1;
1883 case 16: return MVT::v16i1;
1884 case 32: return MVT::v32i1;
1888 return VT.changeVectorElementTypeToInteger();
1891 /// Helper for getByValTypeAlignment to determine
1892 /// the desired ByVal argument alignment.
1893 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1896 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1897 if (VTy->getBitWidth() == 128)
1899 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1900 unsigned EltAlign = 0;
1901 getMaxByValAlign(ATy->getElementType(), EltAlign);
1902 if (EltAlign > MaxAlign)
1903 MaxAlign = EltAlign;
1904 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1905 for (auto *EltTy : STy->elements()) {
1906 unsigned EltAlign = 0;
1907 getMaxByValAlign(EltTy, EltAlign);
1908 if (EltAlign > MaxAlign)
1909 MaxAlign = EltAlign;
1916 /// Return the desired alignment for ByVal aggregate
1917 /// function arguments in the caller parameter area. For X86, aggregates
1918 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1919 /// are at 4-byte boundaries.
1920 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1921 const DataLayout &DL) const {
1922 if (Subtarget->is64Bit()) {
1923 // Max of 8 and alignment of type.
1924 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1931 if (Subtarget->hasSSE1())
1932 getMaxByValAlign(Ty, Align);
1936 /// Returns the target specific optimal type for load
1937 /// and store operations as a result of memset, memcpy, and memmove
1938 /// lowering. If DstAlign is zero that means it's safe to destination
1939 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1940 /// means there isn't a need to check it against alignment requirement,
1941 /// probably because the source does not need to be loaded. If 'IsMemset' is
1942 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1943 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1944 /// source is constant so it does not need to be loaded.
1945 /// It returns EVT::Other if the type should be determined using generic
1946 /// target-independent logic.
1948 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1949 unsigned DstAlign, unsigned SrcAlign,
1950 bool IsMemset, bool ZeroMemset,
1952 MachineFunction &MF) const {
1953 const Function *F = MF.getFunction();
1954 if ((!IsMemset || ZeroMemset) &&
1955 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1957 (!Subtarget->isUnalignedMem16Slow() ||
1958 ((DstAlign == 0 || DstAlign >= 16) &&
1959 (SrcAlign == 0 || SrcAlign >= 16)))) {
1961 // FIXME: Check if unaligned 32-byte accesses are slow.
1962 if (Subtarget->hasInt256())
1964 if (Subtarget->hasFp256())
1967 if (Subtarget->hasSSE2())
1969 if (Subtarget->hasSSE1())
1971 } else if (!MemcpyStrSrc && Size >= 8 &&
1972 !Subtarget->is64Bit() &&
1973 Subtarget->hasSSE2()) {
1974 // Do not use f64 to lower memcpy if source is string constant. It's
1975 // better to use i32 to avoid the loads.
1979 // This is a compromise. If we reach here, unaligned accesses may be slow on
1980 // this target. However, creating smaller, aligned accesses could be even
1981 // slower and would certainly be a lot more code.
1982 if (Subtarget->is64Bit() && Size >= 8)
1987 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1989 return X86ScalarSSEf32;
1990 else if (VT == MVT::f64)
1991 return X86ScalarSSEf64;
1996 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
2001 switch (VT.getSizeInBits()) {
2003 // 8-byte and under are always assumed to be fast.
2007 *Fast = !Subtarget->isUnalignedMem16Slow();
2010 *Fast = !Subtarget->isUnalignedMem32Slow();
2012 // TODO: What about AVX-512 (512-bit) accesses?
2015 // Misaligned accesses of any size are always allowed.
2019 /// Return the entry encoding for a jump table in the
2020 /// current function. The returned value is a member of the
2021 /// MachineJumpTableInfo::JTEntryKind enum.
2022 unsigned X86TargetLowering::getJumpTableEncoding() const {
2023 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2025 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2026 Subtarget->isPICStyleGOT())
2027 return MachineJumpTableInfo::EK_Custom32;
2029 // Otherwise, use the normal jump table encoding heuristics.
2030 return TargetLowering::getJumpTableEncoding();
2033 bool X86TargetLowering::useSoftFloat() const {
2034 return Subtarget->useSoftFloat();
2038 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2039 const MachineBasicBlock *MBB,
2040 unsigned uid,MCContext &Ctx) const{
2041 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2042 Subtarget->isPICStyleGOT());
2043 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2045 return MCSymbolRefExpr::create(MBB->getSymbol(),
2046 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2049 /// Returns relocation base for the given PIC jumptable.
2050 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2051 SelectionDAG &DAG) const {
2052 if (!Subtarget->is64Bit())
2053 // This doesn't have SDLoc associated with it, but is not really the
2054 // same as a Register.
2055 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2056 getPointerTy(DAG.getDataLayout()));
2060 /// This returns the relocation base for the given PIC jumptable,
2061 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2062 const MCExpr *X86TargetLowering::
2063 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2064 MCContext &Ctx) const {
2065 // X86-64 uses RIP relative addressing based on the jump table label.
2066 if (Subtarget->isPICStyleRIPRel())
2067 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2069 // Otherwise, the reference is relative to the PIC base.
2070 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2073 std::pair<const TargetRegisterClass *, uint8_t>
2074 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2076 const TargetRegisterClass *RRC = nullptr;
2078 switch (VT.SimpleTy) {
2080 return TargetLowering::findRepresentativeClass(TRI, VT);
2081 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2082 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2085 RRC = &X86::VR64RegClass;
2087 case MVT::f32: case MVT::f64:
2088 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2089 case MVT::v4f32: case MVT::v2f64:
2090 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2092 RRC = &X86::VR128RegClass;
2095 return std::make_pair(RRC, Cost);
2098 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2099 unsigned &Offset) const {
2100 if (!Subtarget->isTargetLinux())
2103 if (Subtarget->is64Bit()) {
2104 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2106 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2118 /// Android provides a fixed TLS slot for the SafeStack pointer.
2119 /// See the definition of TLS_SLOT_SAFESTACK in
2120 /// https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2121 bool X86TargetLowering::getSafeStackPointerLocation(unsigned &AddressSpace,
2122 unsigned &Offset) const {
2123 if (!Subtarget->isTargetAndroid())
2126 if (Subtarget->is64Bit()) {
2127 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2129 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2141 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2142 unsigned DestAS) const {
2143 assert(SrcAS != DestAS && "Expected different address spaces!");
2145 return SrcAS < 256 && DestAS < 256;
2148 //===----------------------------------------------------------------------===//
2149 // Return Value Calling Convention Implementation
2150 //===----------------------------------------------------------------------===//
2152 #include "X86GenCallingConv.inc"
2154 bool X86TargetLowering::CanLowerReturn(
2155 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2156 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2157 SmallVector<CCValAssign, 16> RVLocs;
2158 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2159 return CCInfo.CheckReturn(Outs, RetCC_X86);
2162 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2163 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2168 X86TargetLowering::LowerReturn(SDValue Chain,
2169 CallingConv::ID CallConv, bool isVarArg,
2170 const SmallVectorImpl<ISD::OutputArg> &Outs,
2171 const SmallVectorImpl<SDValue> &OutVals,
2172 SDLoc dl, SelectionDAG &DAG) const {
2173 MachineFunction &MF = DAG.getMachineFunction();
2174 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2176 SmallVector<CCValAssign, 16> RVLocs;
2177 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2178 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2181 SmallVector<SDValue, 6> RetOps;
2182 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2183 // Operand #1 = Bytes To Pop
2184 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2187 // Copy the result values into the output registers.
2188 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2189 CCValAssign &VA = RVLocs[i];
2190 assert(VA.isRegLoc() && "Can only return in registers!");
2191 SDValue ValToCopy = OutVals[i];
2192 EVT ValVT = ValToCopy.getValueType();
2194 // Promote values to the appropriate types.
2195 if (VA.getLocInfo() == CCValAssign::SExt)
2196 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2197 else if (VA.getLocInfo() == CCValAssign::ZExt)
2198 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2199 else if (VA.getLocInfo() == CCValAssign::AExt) {
2200 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2201 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2203 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2205 else if (VA.getLocInfo() == CCValAssign::BCvt)
2206 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2208 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2209 "Unexpected FP-extend for return value.");
2211 // If this is x86-64, and we disabled SSE, we can't return FP values,
2212 // or SSE or MMX vectors.
2213 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2214 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2215 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2216 report_fatal_error("SSE register return with SSE disabled");
2218 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2219 // llvm-gcc has never done it right and no one has noticed, so this
2220 // should be OK for now.
2221 if (ValVT == MVT::f64 &&
2222 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2223 report_fatal_error("SSE2 register return with SSE2 disabled");
2225 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2226 // the RET instruction and handled by the FP Stackifier.
2227 if (VA.getLocReg() == X86::FP0 ||
2228 VA.getLocReg() == X86::FP1) {
2229 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2230 // change the value to the FP stack register class.
2231 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2232 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2233 RetOps.push_back(ValToCopy);
2234 // Don't emit a copytoreg.
2238 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2239 // which is returned in RAX / RDX.
2240 if (Subtarget->is64Bit()) {
2241 if (ValVT == MVT::x86mmx) {
2242 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2243 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2244 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2246 // If we don't have SSE2 available, convert to v4f32 so the generated
2247 // register is legal.
2248 if (!Subtarget->hasSSE2())
2249 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2254 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2255 Flag = Chain.getValue(1);
2256 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2259 // All x86 ABIs require that for returning structs by value we copy
2260 // the sret argument into %rax/%eax (depending on ABI) for the return.
2261 // We saved the argument into a virtual register in the entry block,
2262 // so now we copy the value out and into %rax/%eax.
2264 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2265 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2266 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2267 // either case FuncInfo->setSRetReturnReg() will have been called.
2268 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2269 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2270 getPointerTy(MF.getDataLayout()));
2273 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2274 X86::RAX : X86::EAX;
2275 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2276 Flag = Chain.getValue(1);
2278 // RAX/EAX now acts like a return value.
2280 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2283 RetOps[0] = Chain; // Update chain.
2285 // Add the flag if we have it.
2287 RetOps.push_back(Flag);
2289 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2292 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2293 if (N->getNumValues() != 1)
2295 if (!N->hasNUsesOfValue(1, 0))
2298 SDValue TCChain = Chain;
2299 SDNode *Copy = *N->use_begin();
2300 if (Copy->getOpcode() == ISD::CopyToReg) {
2301 // If the copy has a glue operand, we conservatively assume it isn't safe to
2302 // perform a tail call.
2303 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2305 TCChain = Copy->getOperand(0);
2306 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2309 bool HasRet = false;
2310 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2312 if (UI->getOpcode() != X86ISD::RET_FLAG)
2314 // If we are returning more than one value, we can definitely
2315 // not make a tail call see PR19530
2316 if (UI->getNumOperands() > 4)
2318 if (UI->getNumOperands() == 4 &&
2319 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2332 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2333 ISD::NodeType ExtendKind) const {
2335 // TODO: Is this also valid on 32-bit?
2336 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2337 ReturnMVT = MVT::i8;
2339 ReturnMVT = MVT::i32;
2341 EVT MinVT = getRegisterType(Context, ReturnMVT);
2342 return VT.bitsLT(MinVT) ? MinVT : VT;
2345 /// Lower the result values of a call into the
2346 /// appropriate copies out of appropriate physical registers.
2349 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2350 CallingConv::ID CallConv, bool isVarArg,
2351 const SmallVectorImpl<ISD::InputArg> &Ins,
2352 SDLoc dl, SelectionDAG &DAG,
2353 SmallVectorImpl<SDValue> &InVals) const {
2355 // Assign locations to each value returned by this call.
2356 SmallVector<CCValAssign, 16> RVLocs;
2357 bool Is64Bit = Subtarget->is64Bit();
2358 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2360 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2362 // Copy all of the result registers out of their specified physreg.
2363 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2364 CCValAssign &VA = RVLocs[i];
2365 EVT CopyVT = VA.getLocVT();
2367 // If this is x86-64, and we disabled SSE, we can't return FP values
2368 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2369 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2370 report_fatal_error("SSE register return with SSE disabled");
2373 // If we prefer to use the value in xmm registers, copy it out as f80 and
2374 // use a truncate to move it from fp stack reg to xmm reg.
2375 bool RoundAfterCopy = false;
2376 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2377 isScalarFPTypeInSSEReg(VA.getValVT())) {
2379 RoundAfterCopy = (CopyVT != VA.getLocVT());
2382 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2383 CopyVT, InFlag).getValue(1);
2384 SDValue Val = Chain.getValue(0);
2387 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2388 // This truncation won't change the value.
2389 DAG.getIntPtrConstant(1, dl));
2391 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2392 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2394 InFlag = Chain.getValue(2);
2395 InVals.push_back(Val);
2401 //===----------------------------------------------------------------------===//
2402 // C & StdCall & Fast Calling Convention implementation
2403 //===----------------------------------------------------------------------===//
2404 // StdCall calling convention seems to be standard for many Windows' API
2405 // routines and around. It differs from C calling convention just a little:
2406 // callee should clean up the stack, not caller. Symbols should be also
2407 // decorated in some fancy way :) It doesn't support any vector arguments.
2408 // For info on fast calling convention see Fast Calling Convention (tail call)
2409 // implementation LowerX86_32FastCCCallTo.
2411 /// CallIsStructReturn - Determines whether a call uses struct return
2413 enum StructReturnType {
2418 static StructReturnType
2419 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2421 return NotStructReturn;
2423 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2424 if (!Flags.isSRet())
2425 return NotStructReturn;
2426 if (Flags.isInReg())
2427 return RegStructReturn;
2428 return StackStructReturn;
2431 /// Determines whether a function uses struct return semantics.
2432 static StructReturnType
2433 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2435 return NotStructReturn;
2437 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2438 if (!Flags.isSRet())
2439 return NotStructReturn;
2440 if (Flags.isInReg())
2441 return RegStructReturn;
2442 return StackStructReturn;
2445 /// Make a copy of an aggregate at address specified by "Src" to address
2446 /// "Dst" with size and alignment information specified by the specific
2447 /// parameter attribute. The copy will be passed as a byval function parameter.
2449 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2450 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2452 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2454 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2455 /*isVolatile*/false, /*AlwaysInline=*/true,
2456 /*isTailCall*/false,
2457 MachinePointerInfo(), MachinePointerInfo());
2460 /// Return true if the calling convention is one that
2461 /// supports tail call optimization.
2462 static bool IsTailCallConvention(CallingConv::ID CC) {
2463 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2464 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2467 /// \brief Return true if the calling convention is a C calling convention.
2468 static bool IsCCallConvention(CallingConv::ID CC) {
2469 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2470 CC == CallingConv::X86_64_SysV);
2473 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2475 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2476 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2480 CallingConv::ID CalleeCC = CS.getCallingConv();
2481 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2487 /// Return true if the function is being made into
2488 /// a tailcall target by changing its ABI.
2489 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2490 bool GuaranteedTailCallOpt) {
2491 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2495 X86TargetLowering::LowerMemArgument(SDValue Chain,
2496 CallingConv::ID CallConv,
2497 const SmallVectorImpl<ISD::InputArg> &Ins,
2498 SDLoc dl, SelectionDAG &DAG,
2499 const CCValAssign &VA,
2500 MachineFrameInfo *MFI,
2502 // Create the nodes corresponding to a load from this parameter slot.
2503 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2504 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2505 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2506 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2509 // If value is passed by pointer we have address passed instead of the value
2511 bool ExtendedInMem = VA.isExtInLoc() &&
2512 VA.getValVT().getScalarType() == MVT::i1;
2514 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2515 ValVT = VA.getLocVT();
2517 ValVT = VA.getValVT();
2519 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2520 // changed with more analysis.
2521 // In case of tail call optimization mark all arguments mutable. Since they
2522 // could be overwritten by lowering of arguments in case of a tail call.
2523 if (Flags.isByVal()) {
2524 unsigned Bytes = Flags.getByValSize();
2525 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2526 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2527 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2529 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2530 VA.getLocMemOffset(), isImmutable);
2531 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2532 SDValue Val = DAG.getLoad(
2533 ValVT, dl, Chain, FIN,
2534 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2536 return ExtendedInMem ?
2537 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2541 // FIXME: Get this from tablegen.
2542 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2543 const X86Subtarget *Subtarget) {
2544 assert(Subtarget->is64Bit());
2546 if (Subtarget->isCallingConvWin64(CallConv)) {
2547 static const MCPhysReg GPR64ArgRegsWin64[] = {
2548 X86::RCX, X86::RDX, X86::R8, X86::R9
2550 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2553 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2554 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2556 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2559 // FIXME: Get this from tablegen.
2560 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2561 CallingConv::ID CallConv,
2562 const X86Subtarget *Subtarget) {
2563 assert(Subtarget->is64Bit());
2564 if (Subtarget->isCallingConvWin64(CallConv)) {
2565 // The XMM registers which might contain var arg parameters are shadowed
2566 // in their paired GPR. So we only need to save the GPR to their home
2568 // TODO: __vectorcall will change this.
2572 const Function *Fn = MF.getFunction();
2573 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2574 bool isSoftFloat = Subtarget->useSoftFloat();
2575 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2576 "SSE register cannot be used when SSE is disabled!");
2577 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2578 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2582 static const MCPhysReg XMMArgRegs64Bit[] = {
2583 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2584 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2586 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2589 SDValue X86TargetLowering::LowerFormalArguments(
2590 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2591 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2592 SmallVectorImpl<SDValue> &InVals) const {
2593 MachineFunction &MF = DAG.getMachineFunction();
2594 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2595 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2597 const Function* Fn = MF.getFunction();
2598 if (Fn->hasExternalLinkage() &&
2599 Subtarget->isTargetCygMing() &&
2600 Fn->getName() == "main")
2601 FuncInfo->setForceFramePointer(true);
2603 MachineFrameInfo *MFI = MF.getFrameInfo();
2604 bool Is64Bit = Subtarget->is64Bit();
2605 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2607 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2608 "Var args not supported with calling convention fastcc, ghc or hipe");
2610 // Assign locations to all of the incoming arguments.
2611 SmallVector<CCValAssign, 16> ArgLocs;
2612 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2614 // Allocate shadow area for Win64
2616 CCInfo.AllocateStack(32, 8);
2618 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2620 unsigned LastVal = ~0U;
2622 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2623 CCValAssign &VA = ArgLocs[i];
2624 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2626 assert(VA.getValNo() != LastVal &&
2627 "Don't support value assigned to multiple locs yet");
2629 LastVal = VA.getValNo();
2631 if (VA.isRegLoc()) {
2632 EVT RegVT = VA.getLocVT();
2633 const TargetRegisterClass *RC;
2634 if (RegVT == MVT::i32)
2635 RC = &X86::GR32RegClass;
2636 else if (Is64Bit && RegVT == MVT::i64)
2637 RC = &X86::GR64RegClass;
2638 else if (RegVT == MVT::f32)
2639 RC = &X86::FR32RegClass;
2640 else if (RegVT == MVT::f64)
2641 RC = &X86::FR64RegClass;
2642 else if (RegVT.is512BitVector())
2643 RC = &X86::VR512RegClass;
2644 else if (RegVT.is256BitVector())
2645 RC = &X86::VR256RegClass;
2646 else if (RegVT.is128BitVector())
2647 RC = &X86::VR128RegClass;
2648 else if (RegVT == MVT::x86mmx)
2649 RC = &X86::VR64RegClass;
2650 else if (RegVT == MVT::i1)
2651 RC = &X86::VK1RegClass;
2652 else if (RegVT == MVT::v8i1)
2653 RC = &X86::VK8RegClass;
2654 else if (RegVT == MVT::v16i1)
2655 RC = &X86::VK16RegClass;
2656 else if (RegVT == MVT::v32i1)
2657 RC = &X86::VK32RegClass;
2658 else if (RegVT == MVT::v64i1)
2659 RC = &X86::VK64RegClass;
2661 llvm_unreachable("Unknown argument type!");
2663 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2664 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2666 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2667 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2669 if (VA.getLocInfo() == CCValAssign::SExt)
2670 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2671 DAG.getValueType(VA.getValVT()));
2672 else if (VA.getLocInfo() == CCValAssign::ZExt)
2673 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2674 DAG.getValueType(VA.getValVT()));
2675 else if (VA.getLocInfo() == CCValAssign::BCvt)
2676 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2678 if (VA.isExtInLoc()) {
2679 // Handle MMX values passed in XMM regs.
2680 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2681 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2683 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2686 assert(VA.isMemLoc());
2687 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2690 // If value is passed via pointer - do a load.
2691 if (VA.getLocInfo() == CCValAssign::Indirect)
2692 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2693 MachinePointerInfo(), false, false, false, 0);
2695 InVals.push_back(ArgValue);
2698 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2699 // All x86 ABIs require that for returning structs by value we copy the
2700 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2701 // the argument into a virtual register so that we can access it from the
2703 if (Ins[i].Flags.isSRet()) {
2704 unsigned Reg = FuncInfo->getSRetReturnReg();
2706 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2707 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2708 FuncInfo->setSRetReturnReg(Reg);
2710 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2711 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2716 unsigned StackSize = CCInfo.getNextStackOffset();
2717 // Align stack specially for tail calls.
2718 if (FuncIsMadeTailCallSafe(CallConv,
2719 MF.getTarget().Options.GuaranteedTailCallOpt))
2720 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2722 // If the function takes variable number of arguments, make a frame index for
2723 // the start of the first vararg value... for expansion of llvm.va_start. We
2724 // can skip this if there are no va_start calls.
2725 if (MFI->hasVAStart() &&
2726 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2727 CallConv != CallingConv::X86_ThisCall))) {
2728 FuncInfo->setVarArgsFrameIndex(
2729 MFI->CreateFixedObject(1, StackSize, true));
2732 MachineModuleInfo &MMI = MF.getMMI();
2734 // Figure out if XMM registers are in use.
2735 assert(!(Subtarget->useSoftFloat() &&
2736 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2737 "SSE register cannot be used when SSE is disabled!");
2739 // 64-bit calling conventions support varargs and register parameters, so we
2740 // have to do extra work to spill them in the prologue.
2741 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2742 // Find the first unallocated argument registers.
2743 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2744 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2745 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2746 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2747 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2748 "SSE register cannot be used when SSE is disabled!");
2750 // Gather all the live in physical registers.
2751 SmallVector<SDValue, 6> LiveGPRs;
2752 SmallVector<SDValue, 8> LiveXMMRegs;
2754 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2755 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2757 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2759 if (!ArgXMMs.empty()) {
2760 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2761 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2762 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2763 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2764 LiveXMMRegs.push_back(
2765 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2770 // Get to the caller-allocated home save location. Add 8 to account
2771 // for the return address.
2772 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2773 FuncInfo->setRegSaveFrameIndex(
2774 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2775 // Fixup to set vararg frame on shadow area (4 x i64).
2777 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2779 // For X86-64, if there are vararg parameters that are passed via
2780 // registers, then we must store them to their spots on the stack so
2781 // they may be loaded by deferencing the result of va_next.
2782 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2783 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2784 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2785 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2788 // Store the integer parameter registers.
2789 SmallVector<SDValue, 8> MemOps;
2790 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2791 getPointerTy(DAG.getDataLayout()));
2792 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2793 for (SDValue Val : LiveGPRs) {
2794 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2795 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2797 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2798 MachinePointerInfo::getFixedStack(
2799 DAG.getMachineFunction(),
2800 FuncInfo->getRegSaveFrameIndex(), Offset),
2802 MemOps.push_back(Store);
2806 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2807 // Now store the XMM (fp + vector) parameter registers.
2808 SmallVector<SDValue, 12> SaveXMMOps;
2809 SaveXMMOps.push_back(Chain);
2810 SaveXMMOps.push_back(ALVal);
2811 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2812 FuncInfo->getRegSaveFrameIndex(), dl));
2813 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2814 FuncInfo->getVarArgsFPOffset(), dl));
2815 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2817 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2818 MVT::Other, SaveXMMOps));
2821 if (!MemOps.empty())
2822 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2825 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2826 // Find the largest legal vector type.
2827 MVT VecVT = MVT::Other;
2828 // FIXME: Only some x86_32 calling conventions support AVX512.
2829 if (Subtarget->hasAVX512() &&
2830 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2831 CallConv == CallingConv::Intel_OCL_BI)))
2832 VecVT = MVT::v16f32;
2833 else if (Subtarget->hasAVX())
2835 else if (Subtarget->hasSSE2())
2838 // We forward some GPRs and some vector types.
2839 SmallVector<MVT, 2> RegParmTypes;
2840 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2841 RegParmTypes.push_back(IntVT);
2842 if (VecVT != MVT::Other)
2843 RegParmTypes.push_back(VecVT);
2845 // Compute the set of forwarded registers. The rest are scratch.
2846 SmallVectorImpl<ForwardedRegister> &Forwards =
2847 FuncInfo->getForwardedMustTailRegParms();
2848 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2850 // Conservatively forward AL on x86_64, since it might be used for varargs.
2851 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2852 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2853 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2856 // Copy all forwards from physical to virtual registers.
2857 for (ForwardedRegister &F : Forwards) {
2858 // FIXME: Can we use a less constrained schedule?
2859 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2860 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2861 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2865 // Some CCs need callee pop.
2866 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2867 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2868 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2870 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2871 // If this is an sret function, the return should pop the hidden pointer.
2872 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2873 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2874 argsAreStructReturn(Ins) == StackStructReturn)
2875 FuncInfo->setBytesToPopOnReturn(4);
2879 // RegSaveFrameIndex is X86-64 only.
2880 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2881 if (CallConv == CallingConv::X86_FastCall ||
2882 CallConv == CallingConv::X86_ThisCall)
2883 // fastcc functions can't have varargs.
2884 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2887 FuncInfo->setArgumentStackSize(StackSize);
2889 if (MMI.hasWinEHFuncInfo(Fn)) {
2891 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2892 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2893 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2894 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2895 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2896 MachinePointerInfo::getFixedStack(
2897 DAG.getMachineFunction(), UnwindHelpFI),
2898 /*isVolatile=*/true,
2899 /*isNonTemporal=*/false, /*Alignment=*/0);
2901 // Functions using Win32 EH are considered to have opaque SP adjustments
2902 // to force local variables to be addressed from the frame or base
2904 MFI->setHasOpaqueSPAdjustment(true);
2912 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2913 SDValue StackPtr, SDValue Arg,
2914 SDLoc dl, SelectionDAG &DAG,
2915 const CCValAssign &VA,
2916 ISD::ArgFlagsTy Flags) const {
2917 unsigned LocMemOffset = VA.getLocMemOffset();
2918 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2919 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2921 if (Flags.isByVal())
2922 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2924 return DAG.getStore(
2925 Chain, dl, Arg, PtrOff,
2926 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2930 /// Emit a load of return address if tail call
2931 /// optimization is performed and it is required.
2933 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2934 SDValue &OutRetAddr, SDValue Chain,
2935 bool IsTailCall, bool Is64Bit,
2936 int FPDiff, SDLoc dl) const {
2937 // Adjust the Return address stack slot.
2938 EVT VT = getPointerTy(DAG.getDataLayout());
2939 OutRetAddr = getReturnAddressFrameIndex(DAG);
2941 // Load the "old" Return address.
2942 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2943 false, false, false, 0);
2944 return SDValue(OutRetAddr.getNode(), 1);
2947 /// Emit a store of the return address if tail call
2948 /// optimization is performed and it is required (FPDiff!=0).
2949 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2950 SDValue Chain, SDValue RetAddrFrIdx,
2951 EVT PtrVT, unsigned SlotSize,
2952 int FPDiff, SDLoc dl) {
2953 // Store the return address to the appropriate stack slot.
2954 if (!FPDiff) return Chain;
2955 // Calculate the new stack slot for the return address.
2956 int NewReturnAddrFI =
2957 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2959 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2960 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2961 MachinePointerInfo::getFixedStack(
2962 DAG.getMachineFunction(), NewReturnAddrFI),
2967 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2968 /// operation of specified width.
2969 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
2971 unsigned NumElems = VT.getVectorNumElements();
2972 SmallVector<int, 8> Mask;
2973 Mask.push_back(NumElems);
2974 for (unsigned i = 1; i != NumElems; ++i)
2976 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2980 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2981 SmallVectorImpl<SDValue> &InVals) const {
2982 SelectionDAG &DAG = CLI.DAG;
2984 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2985 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2986 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2987 SDValue Chain = CLI.Chain;
2988 SDValue Callee = CLI.Callee;
2989 CallingConv::ID CallConv = CLI.CallConv;
2990 bool &isTailCall = CLI.IsTailCall;
2991 bool isVarArg = CLI.IsVarArg;
2993 MachineFunction &MF = DAG.getMachineFunction();
2994 bool Is64Bit = Subtarget->is64Bit();
2995 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2996 StructReturnType SR = callIsStructReturn(Outs);
2997 bool IsSibcall = false;
2998 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2999 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
3001 if (Attr.getValueAsString() == "true")
3004 if (Subtarget->isPICStyleGOT() &&
3005 !MF.getTarget().Options.GuaranteedTailCallOpt) {
3006 // If we are using a GOT, disable tail calls to external symbols with
3007 // default visibility. Tail calling such a symbol requires using a GOT
3008 // relocation, which forces early binding of the symbol. This breaks code
3009 // that require lazy function symbol resolution. Using musttail or
3010 // GuaranteedTailCallOpt will override this.
3011 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3012 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3013 G->getGlobal()->hasDefaultVisibility()))
3017 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3019 // Force this to be a tail call. The verifier rules are enough to ensure
3020 // that we can lower this successfully without moving the return address
3023 } else if (isTailCall) {
3024 // Check if it's really possible to do a tail call.
3025 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3026 isVarArg, SR != NotStructReturn,
3027 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3028 Outs, OutVals, Ins, DAG);
3030 // Sibcalls are automatically detected tailcalls which do not require
3032 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3039 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
3040 "Var args not supported with calling convention fastcc, ghc or hipe");
3042 // Analyze operands of the call, assigning locations to each operand.
3043 SmallVector<CCValAssign, 16> ArgLocs;
3044 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3046 // Allocate shadow area for Win64
3048 CCInfo.AllocateStack(32, 8);
3050 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3052 // Get a count of how many bytes are to be pushed on the stack.
3053 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3055 // This is a sibcall. The memory operands are available in caller's
3056 // own caller's stack.
3058 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3059 IsTailCallConvention(CallConv))
3060 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3063 if (isTailCall && !IsSibcall && !IsMustTail) {
3064 // Lower arguments at fp - stackoffset + fpdiff.
3065 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3067 FPDiff = NumBytesCallerPushed - NumBytes;
3069 // Set the delta of movement of the returnaddr stackslot.
3070 // But only set if delta is greater than previous delta.
3071 if (FPDiff < X86Info->getTCReturnAddrDelta())
3072 X86Info->setTCReturnAddrDelta(FPDiff);
3075 unsigned NumBytesToPush = NumBytes;
3076 unsigned NumBytesToPop = NumBytes;
3078 // If we have an inalloca argument, all stack space has already been allocated
3079 // for us and be right at the top of the stack. We don't support multiple
3080 // arguments passed in memory when using inalloca.
3081 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3083 if (!ArgLocs.back().isMemLoc())
3084 report_fatal_error("cannot use inalloca attribute on a register "
3086 if (ArgLocs.back().getLocMemOffset() != 0)
3087 report_fatal_error("any parameter with the inalloca attribute must be "
3088 "the only memory argument");
3092 Chain = DAG.getCALLSEQ_START(
3093 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3095 SDValue RetAddrFrIdx;
3096 // Load return address for tail calls.
3097 if (isTailCall && FPDiff)
3098 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3099 Is64Bit, FPDiff, dl);
3101 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3102 SmallVector<SDValue, 8> MemOpChains;
3105 // Walk the register/memloc assignments, inserting copies/loads. In the case
3106 // of tail call optimization arguments are handle later.
3107 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3108 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3109 // Skip inalloca arguments, they have already been written.
3110 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3111 if (Flags.isInAlloca())
3114 CCValAssign &VA = ArgLocs[i];
3115 EVT RegVT = VA.getLocVT();
3116 SDValue Arg = OutVals[i];
3117 bool isByVal = Flags.isByVal();
3119 // Promote the value if needed.
3120 switch (VA.getLocInfo()) {
3121 default: llvm_unreachable("Unknown loc info!");
3122 case CCValAssign::Full: break;
3123 case CCValAssign::SExt:
3124 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3126 case CCValAssign::ZExt:
3127 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3129 case CCValAssign::AExt:
3130 if (Arg.getValueType().isVector() &&
3131 Arg.getValueType().getScalarType() == MVT::i1)
3132 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3133 else if (RegVT.is128BitVector()) {
3134 // Special case: passing MMX values in XMM registers.
3135 Arg = DAG.getBitcast(MVT::i64, Arg);
3136 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3137 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3139 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3141 case CCValAssign::BCvt:
3142 Arg = DAG.getBitcast(RegVT, Arg);
3144 case CCValAssign::Indirect: {
3145 // Store the argument.
3146 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3147 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3148 Chain = DAG.getStore(
3149 Chain, dl, Arg, SpillSlot,
3150 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3157 if (VA.isRegLoc()) {
3158 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3159 if (isVarArg && IsWin64) {
3160 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3161 // shadow reg if callee is a varargs function.
3162 unsigned ShadowReg = 0;
3163 switch (VA.getLocReg()) {
3164 case X86::XMM0: ShadowReg = X86::RCX; break;
3165 case X86::XMM1: ShadowReg = X86::RDX; break;
3166 case X86::XMM2: ShadowReg = X86::R8; break;
3167 case X86::XMM3: ShadowReg = X86::R9; break;
3170 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3172 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3173 assert(VA.isMemLoc());
3174 if (!StackPtr.getNode())
3175 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3176 getPointerTy(DAG.getDataLayout()));
3177 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3178 dl, DAG, VA, Flags));
3182 if (!MemOpChains.empty())
3183 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3185 if (Subtarget->isPICStyleGOT()) {
3186 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3189 RegsToPass.push_back(std::make_pair(
3190 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3191 getPointerTy(DAG.getDataLayout()))));
3193 // If we are tail calling and generating PIC/GOT style code load the
3194 // address of the callee into ECX. The value in ecx is used as target of
3195 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3196 // for tail calls on PIC/GOT architectures. Normally we would just put the
3197 // address of GOT into ebx and then call target@PLT. But for tail calls
3198 // ebx would be restored (since ebx is callee saved) before jumping to the
3201 // Note: The actual moving to ECX is done further down.
3202 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3203 if (G && !G->getGlobal()->hasLocalLinkage() &&
3204 G->getGlobal()->hasDefaultVisibility())
3205 Callee = LowerGlobalAddress(Callee, DAG);
3206 else if (isa<ExternalSymbolSDNode>(Callee))
3207 Callee = LowerExternalSymbol(Callee, DAG);
3211 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3212 // From AMD64 ABI document:
3213 // For calls that may call functions that use varargs or stdargs
3214 // (prototype-less calls or calls to functions containing ellipsis (...) in
3215 // the declaration) %al is used as hidden argument to specify the number
3216 // of SSE registers used. The contents of %al do not need to match exactly
3217 // the number of registers, but must be an ubound on the number of SSE
3218 // registers used and is in the range 0 - 8 inclusive.
3220 // Count the number of XMM registers allocated.
3221 static const MCPhysReg XMMArgRegs[] = {
3222 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3223 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3225 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3226 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3227 && "SSE registers cannot be used when SSE is disabled");
3229 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3230 DAG.getConstant(NumXMMRegs, dl,
3234 if (isVarArg && IsMustTail) {
3235 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3236 for (const auto &F : Forwards) {
3237 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3238 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3242 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3243 // don't need this because the eligibility check rejects calls that require
3244 // shuffling arguments passed in memory.
3245 if (!IsSibcall && isTailCall) {
3246 // Force all the incoming stack arguments to be loaded from the stack
3247 // before any new outgoing arguments are stored to the stack, because the
3248 // outgoing stack slots may alias the incoming argument stack slots, and
3249 // the alias isn't otherwise explicit. This is slightly more conservative
3250 // than necessary, because it means that each store effectively depends
3251 // on every argument instead of just those arguments it would clobber.
3252 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3254 SmallVector<SDValue, 8> MemOpChains2;
3257 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3258 CCValAssign &VA = ArgLocs[i];
3261 assert(VA.isMemLoc());
3262 SDValue Arg = OutVals[i];
3263 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3264 // Skip inalloca arguments. They don't require any work.
3265 if (Flags.isInAlloca())
3267 // Create frame index.
3268 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3269 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3270 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3271 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3273 if (Flags.isByVal()) {
3274 // Copy relative to framepointer.
3275 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3276 if (!StackPtr.getNode())
3277 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3278 getPointerTy(DAG.getDataLayout()));
3279 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3282 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3286 // Store relative to framepointer.
3287 MemOpChains2.push_back(DAG.getStore(
3288 ArgChain, dl, Arg, FIN,
3289 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3294 if (!MemOpChains2.empty())
3295 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3297 // Store the return address to the appropriate stack slot.
3298 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3299 getPointerTy(DAG.getDataLayout()),
3300 RegInfo->getSlotSize(), FPDiff, dl);
3303 // Build a sequence of copy-to-reg nodes chained together with token chain
3304 // and flag operands which copy the outgoing args into registers.
3306 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3307 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3308 RegsToPass[i].second, InFlag);
3309 InFlag = Chain.getValue(1);
3312 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3313 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3314 // In the 64-bit large code model, we have to make all calls
3315 // through a register, since the call instruction's 32-bit
3316 // pc-relative offset may not be large enough to hold the whole
3318 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3319 // If the callee is a GlobalAddress node (quite common, every direct call
3320 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3322 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3324 // We should use extra load for direct calls to dllimported functions in
3326 const GlobalValue *GV = G->getGlobal();
3327 if (!GV->hasDLLImportStorageClass()) {
3328 unsigned char OpFlags = 0;
3329 bool ExtraLoad = false;
3330 unsigned WrapperKind = ISD::DELETED_NODE;
3332 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3333 // external symbols most go through the PLT in PIC mode. If the symbol
3334 // has hidden or protected visibility, or if it is static or local, then
3335 // we don't need to use the PLT - we can directly call it.
3336 if (Subtarget->isTargetELF() &&
3337 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3338 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3339 OpFlags = X86II::MO_PLT;
3340 } else if (Subtarget->isPICStyleStubAny() &&
3341 !GV->isStrongDefinitionForLinker() &&
3342 (!Subtarget->getTargetTriple().isMacOSX() ||
3343 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3344 // PC-relative references to external symbols should go through $stub,
3345 // unless we're building with the leopard linker or later, which
3346 // automatically synthesizes these stubs.
3347 OpFlags = X86II::MO_DARWIN_STUB;
3348 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3349 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3350 // If the function is marked as non-lazy, generate an indirect call
3351 // which loads from the GOT directly. This avoids runtime overhead
3352 // at the cost of eager binding (and one extra byte of encoding).
3353 OpFlags = X86II::MO_GOTPCREL;
3354 WrapperKind = X86ISD::WrapperRIP;
3358 Callee = DAG.getTargetGlobalAddress(
3359 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3361 // Add a wrapper if needed.
3362 if (WrapperKind != ISD::DELETED_NODE)
3363 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3364 getPointerTy(DAG.getDataLayout()), Callee);
3365 // Add extra indirection if needed.
3367 Callee = DAG.getLoad(
3368 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3369 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3372 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3373 unsigned char OpFlags = 0;
3375 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3376 // external symbols should go through the PLT.
3377 if (Subtarget->isTargetELF() &&
3378 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3379 OpFlags = X86II::MO_PLT;
3380 } else if (Subtarget->isPICStyleStubAny() &&
3381 (!Subtarget->getTargetTriple().isMacOSX() ||
3382 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3383 // PC-relative references to external symbols should go through $stub,
3384 // unless we're building with the leopard linker or later, which
3385 // automatically synthesizes these stubs.
3386 OpFlags = X86II::MO_DARWIN_STUB;
3389 Callee = DAG.getTargetExternalSymbol(
3390 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3391 } else if (Subtarget->isTarget64BitILP32() &&
3392 Callee->getValueType(0) == MVT::i32) {
3393 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3394 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3397 // Returns a chain & a flag for retval copy to use.
3398 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3399 SmallVector<SDValue, 8> Ops;
3401 if (!IsSibcall && isTailCall) {
3402 Chain = DAG.getCALLSEQ_END(Chain,
3403 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3404 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3405 InFlag = Chain.getValue(1);
3408 Ops.push_back(Chain);
3409 Ops.push_back(Callee);
3412 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3414 // Add argument registers to the end of the list so that they are known live
3416 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3417 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3418 RegsToPass[i].second.getValueType()));
3420 // Add a register mask operand representing the call-preserved registers.
3421 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3422 assert(Mask && "Missing call preserved mask for calling convention");
3424 // If this is an invoke in a 32-bit function using a funclet-based
3425 // personality, assume the function clobbers all registers. If an exception
3426 // is thrown, the runtime will not restore CSRs.
3427 // FIXME: Model this more precisely so that we can register allocate across
3428 // the normal edge and spill and fill across the exceptional edge.
3429 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3430 const Function *CallerFn = MF.getFunction();
3431 EHPersonality Pers =
3432 CallerFn->hasPersonalityFn()
3433 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3434 : EHPersonality::Unknown;
3435 if (isFuncletEHPersonality(Pers))
3436 Mask = RegInfo->getNoPreservedMask();
3439 Ops.push_back(DAG.getRegisterMask(Mask));
3441 if (InFlag.getNode())
3442 Ops.push_back(InFlag);
3446 //// If this is the first return lowered for this function, add the regs
3447 //// to the liveout set for the function.
3448 // This isn't right, although it's probably harmless on x86; liveouts
3449 // should be computed from returns not tail calls. Consider a void
3450 // function making a tail call to a function returning int.
3451 MF.getFrameInfo()->setHasTailCall();
3452 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3455 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3456 InFlag = Chain.getValue(1);
3458 // Create the CALLSEQ_END node.
3459 unsigned NumBytesForCalleeToPop;
3460 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3461 DAG.getTarget().Options.GuaranteedTailCallOpt))
3462 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3463 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3464 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3465 SR == StackStructReturn)
3466 // If this is a call to a struct-return function, the callee
3467 // pops the hidden struct pointer, so we have to push it back.
3468 // This is common for Darwin/X86, Linux & Mingw32 targets.
3469 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3470 NumBytesForCalleeToPop = 4;
3472 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3474 // Returns a flag for retval copy to use.
3476 Chain = DAG.getCALLSEQ_END(Chain,
3477 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3478 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3481 InFlag = Chain.getValue(1);
3484 // Handle result values, copying them out of physregs into vregs that we
3486 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3487 Ins, dl, DAG, InVals);
3490 //===----------------------------------------------------------------------===//
3491 // Fast Calling Convention (tail call) implementation
3492 //===----------------------------------------------------------------------===//
3494 // Like std call, callee cleans arguments, convention except that ECX is
3495 // reserved for storing the tail called function address. Only 2 registers are
3496 // free for argument passing (inreg). Tail call optimization is performed
3498 // * tailcallopt is enabled
3499 // * caller/callee are fastcc
3500 // On X86_64 architecture with GOT-style position independent code only local
3501 // (within module) calls are supported at the moment.
3502 // To keep the stack aligned according to platform abi the function
3503 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3504 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3505 // If a tail called function callee has more arguments than the caller the
3506 // caller needs to make sure that there is room to move the RETADDR to. This is
3507 // achieved by reserving an area the size of the argument delta right after the
3508 // original RETADDR, but before the saved framepointer or the spilled registers
3509 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3521 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3524 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3525 SelectionDAG& DAG) const {
3526 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3527 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3528 unsigned StackAlignment = TFI.getStackAlignment();
3529 uint64_t AlignMask = StackAlignment - 1;
3530 int64_t Offset = StackSize;
3531 unsigned SlotSize = RegInfo->getSlotSize();
3532 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3533 // Number smaller than 12 so just add the difference.
3534 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3536 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3537 Offset = ((~AlignMask) & Offset) + StackAlignment +
3538 (StackAlignment-SlotSize);
3543 /// Return true if the given stack call argument is already available in the
3544 /// same position (relatively) of the caller's incoming argument stack.
3546 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3547 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3548 const X86InstrInfo *TII) {
3549 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3551 if (Arg.getOpcode() == ISD::CopyFromReg) {
3552 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3553 if (!TargetRegisterInfo::isVirtualRegister(VR))
3555 MachineInstr *Def = MRI->getVRegDef(VR);
3558 if (!Flags.isByVal()) {
3559 if (!TII->isLoadFromStackSlot(Def, FI))
3562 unsigned Opcode = Def->getOpcode();
3563 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3564 Opcode == X86::LEA64_32r) &&
3565 Def->getOperand(1).isFI()) {
3566 FI = Def->getOperand(1).getIndex();
3567 Bytes = Flags.getByValSize();
3571 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3572 if (Flags.isByVal())
3573 // ByVal argument is passed in as a pointer but it's now being
3574 // dereferenced. e.g.
3575 // define @foo(%struct.X* %A) {
3576 // tail call @bar(%struct.X* byval %A)
3579 SDValue Ptr = Ld->getBasePtr();
3580 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3583 FI = FINode->getIndex();
3584 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3585 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3586 FI = FINode->getIndex();
3587 Bytes = Flags.getByValSize();
3591 assert(FI != INT_MAX);
3592 if (!MFI->isFixedObjectIndex(FI))
3594 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3597 /// Check whether the call is eligible for tail call optimization. Targets
3598 /// that want to do tail call optimization should implement this function.
3599 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3600 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3601 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3602 const SmallVectorImpl<ISD::OutputArg> &Outs,
3603 const SmallVectorImpl<SDValue> &OutVals,
3604 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3605 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3608 // If -tailcallopt is specified, make fastcc functions tail-callable.
3609 const MachineFunction &MF = DAG.getMachineFunction();
3610 const Function *CallerF = MF.getFunction();
3612 // If the function return type is x86_fp80 and the callee return type is not,
3613 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3614 // perform a tailcall optimization here.
3615 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3618 CallingConv::ID CallerCC = CallerF->getCallingConv();
3619 bool CCMatch = CallerCC == CalleeCC;
3620 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3621 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3623 // Win64 functions have extra shadow space for argument homing. Don't do the
3624 // sibcall if the caller and callee have mismatched expectations for this
3626 if (IsCalleeWin64 != IsCallerWin64)
3629 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3630 if (IsTailCallConvention(CalleeCC) && CCMatch)
3635 // Look for obvious safe cases to perform tail call optimization that do not
3636 // require ABI changes. This is what gcc calls sibcall.
3638 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3639 // emit a special epilogue.
3640 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3641 if (RegInfo->needsStackRealignment(MF))
3644 // Also avoid sibcall optimization if either caller or callee uses struct
3645 // return semantics.
3646 if (isCalleeStructRet || isCallerStructRet)
3649 // An stdcall/thiscall caller is expected to clean up its arguments; the
3650 // callee isn't going to do that.
3651 // FIXME: this is more restrictive than needed. We could produce a tailcall
3652 // when the stack adjustment matches. For example, with a thiscall that takes
3653 // only one argument.
3654 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3655 CallerCC == CallingConv::X86_ThisCall))
3658 // Do not sibcall optimize vararg calls unless all arguments are passed via
3660 if (isVarArg && !Outs.empty()) {
3662 // Optimizing for varargs on Win64 is unlikely to be safe without
3663 // additional testing.
3664 if (IsCalleeWin64 || IsCallerWin64)
3667 SmallVector<CCValAssign, 16> ArgLocs;
3668 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3671 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3672 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3673 if (!ArgLocs[i].isRegLoc())
3677 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3678 // stack. Therefore, if it's not used by the call it is not safe to optimize
3679 // this into a sibcall.
3680 bool Unused = false;
3681 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3688 SmallVector<CCValAssign, 16> RVLocs;
3689 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3691 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3692 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3693 CCValAssign &VA = RVLocs[i];
3694 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3699 // If the calling conventions do not match, then we'd better make sure the
3700 // results are returned in the same way as what the caller expects.
3702 SmallVector<CCValAssign, 16> RVLocs1;
3703 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3705 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3707 SmallVector<CCValAssign, 16> RVLocs2;
3708 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3710 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3712 if (RVLocs1.size() != RVLocs2.size())
3714 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3715 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3717 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3719 if (RVLocs1[i].isRegLoc()) {
3720 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3723 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3729 // If the callee takes no arguments then go on to check the results of the
3731 if (!Outs.empty()) {
3732 // Check if stack adjustment is needed. For now, do not do this if any
3733 // argument is passed on the stack.
3734 SmallVector<CCValAssign, 16> ArgLocs;
3735 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3738 // Allocate shadow area for Win64
3740 CCInfo.AllocateStack(32, 8);
3742 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3743 if (CCInfo.getNextStackOffset()) {
3744 MachineFunction &MF = DAG.getMachineFunction();
3745 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3748 // Check if the arguments are already laid out in the right way as
3749 // the caller's fixed stack objects.
3750 MachineFrameInfo *MFI = MF.getFrameInfo();
3751 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3752 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3753 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3754 CCValAssign &VA = ArgLocs[i];
3755 SDValue Arg = OutVals[i];
3756 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3757 if (VA.getLocInfo() == CCValAssign::Indirect)
3759 if (!VA.isRegLoc()) {
3760 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3767 // If the tailcall address may be in a register, then make sure it's
3768 // possible to register allocate for it. In 32-bit, the call address can
3769 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3770 // callee-saved registers are restored. These happen to be the same
3771 // registers used to pass 'inreg' arguments so watch out for those.
3772 if (!Subtarget->is64Bit() &&
3773 ((!isa<GlobalAddressSDNode>(Callee) &&
3774 !isa<ExternalSymbolSDNode>(Callee)) ||
3775 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3776 unsigned NumInRegs = 0;
3777 // In PIC we need an extra register to formulate the address computation
3779 unsigned MaxInRegs =
3780 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3782 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3783 CCValAssign &VA = ArgLocs[i];
3786 unsigned Reg = VA.getLocReg();
3789 case X86::EAX: case X86::EDX: case X86::ECX:
3790 if (++NumInRegs == MaxInRegs)
3802 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3803 const TargetLibraryInfo *libInfo) const {
3804 return X86::createFastISel(funcInfo, libInfo);
3807 //===----------------------------------------------------------------------===//
3808 // Other Lowering Hooks
3809 //===----------------------------------------------------------------------===//
3811 static bool MayFoldLoad(SDValue Op) {
3812 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3815 static bool MayFoldIntoStore(SDValue Op) {
3816 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3819 static bool isTargetShuffle(unsigned Opcode) {
3821 default: return false;
3822 case X86ISD::BLENDI:
3823 case X86ISD::PSHUFB:
3824 case X86ISD::PSHUFD:
3825 case X86ISD::PSHUFHW:
3826 case X86ISD::PSHUFLW:
3828 case X86ISD::PALIGNR:
3829 case X86ISD::MOVLHPS:
3830 case X86ISD::MOVLHPD:
3831 case X86ISD::MOVHLPS:
3832 case X86ISD::MOVLPS:
3833 case X86ISD::MOVLPD:
3834 case X86ISD::MOVSHDUP:
3835 case X86ISD::MOVSLDUP:
3836 case X86ISD::MOVDDUP:
3839 case X86ISD::UNPCKL:
3840 case X86ISD::UNPCKH:
3841 case X86ISD::VPERMILPI:
3842 case X86ISD::VPERM2X128:
3843 case X86ISD::VPERMI:
3844 case X86ISD::VPERMV:
3845 case X86ISD::VPERMV3:
3850 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3851 SDValue V1, unsigned TargetMask,
3852 SelectionDAG &DAG) {
3854 default: llvm_unreachable("Unknown x86 shuffle node");
3855 case X86ISD::PSHUFD:
3856 case X86ISD::PSHUFHW:
3857 case X86ISD::PSHUFLW:
3858 case X86ISD::VPERMILPI:
3859 case X86ISD::VPERMI:
3860 return DAG.getNode(Opc, dl, VT, V1,
3861 DAG.getConstant(TargetMask, dl, MVT::i8));
3865 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3866 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3868 default: llvm_unreachable("Unknown x86 shuffle node");
3869 case X86ISD::MOVLHPS:
3870 case X86ISD::MOVLHPD:
3871 case X86ISD::MOVHLPS:
3872 case X86ISD::MOVLPS:
3873 case X86ISD::MOVLPD:
3876 case X86ISD::UNPCKL:
3877 case X86ISD::UNPCKH:
3878 return DAG.getNode(Opc, dl, VT, V1, V2);
3882 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3883 MachineFunction &MF = DAG.getMachineFunction();
3884 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3885 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3886 int ReturnAddrIndex = FuncInfo->getRAIndex();
3888 if (ReturnAddrIndex == 0) {
3889 // Set up a frame object for the return address.
3890 unsigned SlotSize = RegInfo->getSlotSize();
3891 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3894 FuncInfo->setRAIndex(ReturnAddrIndex);
3897 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3900 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3901 bool hasSymbolicDisplacement) {
3902 // Offset should fit into 32 bit immediate field.
3903 if (!isInt<32>(Offset))
3906 // If we don't have a symbolic displacement - we don't have any extra
3908 if (!hasSymbolicDisplacement)
3911 // FIXME: Some tweaks might be needed for medium code model.
3912 if (M != CodeModel::Small && M != CodeModel::Kernel)
3915 // For small code model we assume that latest object is 16MB before end of 31
3916 // bits boundary. We may also accept pretty large negative constants knowing
3917 // that all objects are in the positive half of address space.
3918 if (M == CodeModel::Small && Offset < 16*1024*1024)
3921 // For kernel code model we know that all object resist in the negative half
3922 // of 32bits address space. We may not accept negative offsets, since they may
3923 // be just off and we may accept pretty large positive ones.
3924 if (M == CodeModel::Kernel && Offset >= 0)
3930 /// Determines whether the callee is required to pop its own arguments.
3931 /// Callee pop is necessary to support tail calls.
3932 bool X86::isCalleePop(CallingConv::ID CallingConv,
3933 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3935 if (IsTailCallConvention(CallingConv))
3936 return IsVarArg ? false : TailCallOpt;
3938 switch (CallingConv) {
3941 case CallingConv::X86_StdCall:
3942 case CallingConv::X86_FastCall:
3943 case CallingConv::X86_ThisCall:
3948 /// \brief Return true if the condition is an unsigned comparison operation.
3949 static bool isX86CCUnsigned(unsigned X86CC) {
3951 default: llvm_unreachable("Invalid integer condition!");
3952 case X86::COND_E: return true;
3953 case X86::COND_G: return false;
3954 case X86::COND_GE: return false;
3955 case X86::COND_L: return false;
3956 case X86::COND_LE: return false;
3957 case X86::COND_NE: return true;
3958 case X86::COND_B: return true;
3959 case X86::COND_A: return true;
3960 case X86::COND_BE: return true;
3961 case X86::COND_AE: return true;
3963 llvm_unreachable("covered switch fell through?!");
3966 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3967 /// condition code, returning the condition code and the LHS/RHS of the
3968 /// comparison to make.
3969 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3970 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3972 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3973 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3974 // X > -1 -> X == 0, jump !sign.
3975 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3976 return X86::COND_NS;
3978 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3979 // X < 0 -> X == 0, jump on sign.
3982 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3984 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3985 return X86::COND_LE;
3989 switch (SetCCOpcode) {
3990 default: llvm_unreachable("Invalid integer condition!");
3991 case ISD::SETEQ: return X86::COND_E;
3992 case ISD::SETGT: return X86::COND_G;
3993 case ISD::SETGE: return X86::COND_GE;
3994 case ISD::SETLT: return X86::COND_L;
3995 case ISD::SETLE: return X86::COND_LE;
3996 case ISD::SETNE: return X86::COND_NE;
3997 case ISD::SETULT: return X86::COND_B;
3998 case ISD::SETUGT: return X86::COND_A;
3999 case ISD::SETULE: return X86::COND_BE;
4000 case ISD::SETUGE: return X86::COND_AE;
4004 // First determine if it is required or is profitable to flip the operands.
4006 // If LHS is a foldable load, but RHS is not, flip the condition.
4007 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4008 !ISD::isNON_EXTLoad(RHS.getNode())) {
4009 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4010 std::swap(LHS, RHS);
4013 switch (SetCCOpcode) {
4019 std::swap(LHS, RHS);
4023 // On a floating point condition, the flags are set as follows:
4025 // 0 | 0 | 0 | X > Y
4026 // 0 | 0 | 1 | X < Y
4027 // 1 | 0 | 0 | X == Y
4028 // 1 | 1 | 1 | unordered
4029 switch (SetCCOpcode) {
4030 default: llvm_unreachable("Condcode should be pre-legalized away");
4032 case ISD::SETEQ: return X86::COND_E;
4033 case ISD::SETOLT: // flipped
4035 case ISD::SETGT: return X86::COND_A;
4036 case ISD::SETOLE: // flipped
4038 case ISD::SETGE: return X86::COND_AE;
4039 case ISD::SETUGT: // flipped
4041 case ISD::SETLT: return X86::COND_B;
4042 case ISD::SETUGE: // flipped
4044 case ISD::SETLE: return X86::COND_BE;
4046 case ISD::SETNE: return X86::COND_NE;
4047 case ISD::SETUO: return X86::COND_P;
4048 case ISD::SETO: return X86::COND_NP;
4050 case ISD::SETUNE: return X86::COND_INVALID;
4054 /// Is there a floating point cmov for the specific X86 condition code?
4055 /// Current x86 isa includes the following FP cmov instructions:
4056 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4057 static bool hasFPCMov(unsigned X86CC) {
4073 /// Returns true if the target can instruction select the
4074 /// specified FP immediate natively. If false, the legalizer will
4075 /// materialize the FP immediate as a load from a constant pool.
4076 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4077 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4078 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4084 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4085 ISD::LoadExtType ExtTy,
4087 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4088 // relocation target a movq or addq instruction: don't let the load shrink.
4089 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4090 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4091 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4092 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4096 /// \brief Returns true if it is beneficial to convert a load of a constant
4097 /// to just the constant itself.
4098 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4100 assert(Ty->isIntegerTy());
4102 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4103 if (BitSize == 0 || BitSize > 64)
4108 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4109 unsigned Index) const {
4110 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4113 return (Index == 0 || Index == ResVT.getVectorNumElements());
4116 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4117 // Speculate cttz only if we can directly use TZCNT.
4118 return Subtarget->hasBMI();
4121 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4122 // Speculate ctlz only if we can directly use LZCNT.
4123 return Subtarget->hasLZCNT();
4126 /// Return true if every element in Mask, beginning
4127 /// from position Pos and ending in Pos+Size is undef.
4128 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4129 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4135 /// Return true if Val is undef or if its value falls within the
4136 /// specified range (L, H].
4137 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4138 return (Val < 0) || (Val >= Low && Val < Hi);
4141 /// Val is either less than zero (undef) or equal to the specified value.
4142 static bool isUndefOrEqual(int Val, int CmpVal) {
4143 return (Val < 0 || Val == CmpVal);
4146 /// Return true if every element in Mask, beginning
4147 /// from position Pos and ending in Pos+Size, falls within the specified
4148 /// sequential range (Low, Low+Size]. or is undef.
4149 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4150 unsigned Pos, unsigned Size, int Low) {
4151 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4152 if (!isUndefOrEqual(Mask[i], Low))
4157 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4158 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4159 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4160 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4161 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4164 // The index should be aligned on a vecWidth-bit boundary.
4166 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4168 MVT VT = N->getSimpleValueType(0);
4169 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4170 bool Result = (Index * ElSize) % vecWidth == 0;
4175 /// Return true if the specified INSERT_SUBVECTOR
4176 /// operand specifies a subvector insert that is suitable for input to
4177 /// insertion of 128 or 256-bit subvectors
4178 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4179 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4180 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4182 // The index should be aligned on a vecWidth-bit boundary.
4184 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4186 MVT VT = N->getSimpleValueType(0);
4187 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4188 bool Result = (Index * ElSize) % vecWidth == 0;
4193 bool X86::isVINSERT128Index(SDNode *N) {
4194 return isVINSERTIndex(N, 128);
4197 bool X86::isVINSERT256Index(SDNode *N) {
4198 return isVINSERTIndex(N, 256);
4201 bool X86::isVEXTRACT128Index(SDNode *N) {
4202 return isVEXTRACTIndex(N, 128);
4205 bool X86::isVEXTRACT256Index(SDNode *N) {
4206 return isVEXTRACTIndex(N, 256);
4209 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4210 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4211 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4212 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4215 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4217 MVT VecVT = N->getOperand(0).getSimpleValueType();
4218 MVT ElVT = VecVT.getVectorElementType();
4220 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4221 return Index / NumElemsPerChunk;
4224 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4225 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4226 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4227 llvm_unreachable("Illegal insert subvector for VINSERT");
4230 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4232 MVT VecVT = N->getSimpleValueType(0);
4233 MVT ElVT = VecVT.getVectorElementType();
4235 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4236 return Index / NumElemsPerChunk;
4239 /// Return the appropriate immediate to extract the specified
4240 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4241 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4242 return getExtractVEXTRACTImmediate(N, 128);
4245 /// Return the appropriate immediate to extract the specified
4246 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4247 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4248 return getExtractVEXTRACTImmediate(N, 256);
4251 /// Return the appropriate immediate to insert at the specified
4252 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4253 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4254 return getInsertVINSERTImmediate(N, 128);
4257 /// Return the appropriate immediate to insert at the specified
4258 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4259 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4260 return getInsertVINSERTImmediate(N, 256);
4263 /// Returns true if V is a constant integer zero.
4264 static bool isZero(SDValue V) {
4265 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4266 return C && C->isNullValue();
4269 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4270 bool X86::isZeroNode(SDValue Elt) {
4273 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4274 return CFP->getValueAPF().isPosZero();
4278 // Build a vector of constants
4279 // Use an UNDEF node if MaskElt == -1.
4280 // Spilt 64-bit constants in the 32-bit mode.
4281 static SDValue getConstVector(ArrayRef<int> Values, EVT VT,
4283 SDLoc dl, bool IsMask = false) {
4285 SmallVector<SDValue, 32> Ops;
4288 EVT ConstVecVT = VT;
4289 unsigned NumElts = VT.getVectorNumElements();
4290 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4291 if (!In64BitMode && VT.getScalarType() == MVT::i64) {
4292 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4296 EVT EltVT = ConstVecVT.getScalarType();
4297 for (unsigned i = 0; i < NumElts; ++i) {
4298 bool IsUndef = Values[i] < 0 && IsMask;
4299 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4300 DAG.getConstant(Values[i], dl, EltVT);
4301 Ops.push_back(OpNode);
4303 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4304 DAG.getConstant(0, dl, EltVT));
4306 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4308 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4312 /// Returns a vector of specified type with all zero elements.
4313 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4314 SelectionDAG &DAG, SDLoc dl) {
4315 assert(VT.isVector() && "Expected a vector type");
4317 // Always build SSE zero vectors as <4 x i32> bitcasted
4318 // to their dest type. This ensures they get CSE'd.
4320 if (VT.is128BitVector()) { // SSE
4321 if (Subtarget->hasSSE2()) { // SSE2
4322 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4323 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4325 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4326 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4328 } else if (VT.is256BitVector()) { // AVX
4329 if (Subtarget->hasInt256()) { // AVX2
4330 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4331 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4332 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4334 // 256-bit logic and arithmetic instructions in AVX are all
4335 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4336 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4337 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4338 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4340 } else if (VT.is512BitVector()) { // AVX-512
4341 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4342 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4343 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4344 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4345 } else if (VT.getScalarType() == MVT::i1) {
4347 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4348 && "Unexpected vector type");
4349 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4350 && "Unexpected vector type");
4351 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4352 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4353 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4355 llvm_unreachable("Unexpected vector type");
4357 return DAG.getBitcast(VT, Vec);
4360 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4361 SelectionDAG &DAG, SDLoc dl,
4362 unsigned vectorWidth) {
4363 assert((vectorWidth == 128 || vectorWidth == 256) &&
4364 "Unsupported vector width");
4365 EVT VT = Vec.getValueType();
4366 EVT ElVT = VT.getVectorElementType();
4367 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4368 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4369 VT.getVectorNumElements()/Factor);
4371 // Extract from UNDEF is UNDEF.
4372 if (Vec.getOpcode() == ISD::UNDEF)
4373 return DAG.getUNDEF(ResultVT);
4375 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4376 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4378 // This is the index of the first element of the vectorWidth-bit chunk
4380 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4383 // If the input is a buildvector just emit a smaller one.
4384 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4385 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4386 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4389 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4390 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4393 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4394 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4395 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4396 /// instructions or a simple subregister reference. Idx is an index in the
4397 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4398 /// lowering EXTRACT_VECTOR_ELT operations easier.
4399 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4400 SelectionDAG &DAG, SDLoc dl) {
4401 assert((Vec.getValueType().is256BitVector() ||
4402 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4403 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4406 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4407 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4408 SelectionDAG &DAG, SDLoc dl) {
4409 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4410 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4413 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4414 unsigned IdxVal, SelectionDAG &DAG,
4415 SDLoc dl, unsigned vectorWidth) {
4416 assert((vectorWidth == 128 || vectorWidth == 256) &&
4417 "Unsupported vector width");
4418 // Inserting UNDEF is Result
4419 if (Vec.getOpcode() == ISD::UNDEF)
4421 EVT VT = Vec.getValueType();
4422 EVT ElVT = VT.getVectorElementType();
4423 EVT ResultVT = Result.getValueType();
4425 // Insert the relevant vectorWidth bits.
4426 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4428 // This is the index of the first element of the vectorWidth-bit chunk
4430 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4433 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4434 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4437 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4438 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4439 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4440 /// simple superregister reference. Idx is an index in the 128 bits
4441 /// we want. It need not be aligned to a 128-bit boundary. That makes
4442 /// lowering INSERT_VECTOR_ELT operations easier.
4443 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4444 SelectionDAG &DAG, SDLoc dl) {
4445 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4447 // For insertion into the zero index (low half) of a 256-bit vector, it is
4448 // more efficient to generate a blend with immediate instead of an insert*128.
4449 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4450 // extend the subvector to the size of the result vector. Make sure that
4451 // we are not recursing on that node by checking for undef here.
4452 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4453 Result.getOpcode() != ISD::UNDEF) {
4454 EVT ResultVT = Result.getValueType();
4455 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4456 SDValue Undef = DAG.getUNDEF(ResultVT);
4457 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4460 // The blend instruction, and therefore its mask, depend on the data type.
4461 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4462 if (ScalarType.isFloatingPoint()) {
4463 // Choose either vblendps (float) or vblendpd (double).
4464 unsigned ScalarSize = ScalarType.getSizeInBits();
4465 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4466 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4467 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4468 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4471 const X86Subtarget &Subtarget =
4472 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4474 // AVX2 is needed for 256-bit integer blend support.
4475 // Integers must be cast to 32-bit because there is only vpblendd;
4476 // vpblendw can't be used for this because it has a handicapped mask.
4478 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4479 // is still more efficient than using the wrong domain vinsertf128 that
4480 // will be created by InsertSubVector().
4481 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4483 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4484 Vec256 = DAG.getBitcast(CastVT, Vec256);
4485 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4486 return DAG.getBitcast(ResultVT, Vec256);
4489 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4492 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4493 SelectionDAG &DAG, SDLoc dl) {
4494 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4495 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4498 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4499 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4500 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4501 /// large BUILD_VECTORS.
4502 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4503 unsigned NumElems, SelectionDAG &DAG,
4505 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4506 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4509 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4510 unsigned NumElems, SelectionDAG &DAG,
4512 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4513 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4516 /// Returns a vector of specified type with all bits set.
4517 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4518 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4519 /// Then bitcast to their original type, ensuring they get CSE'd.
4520 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4521 SelectionDAG &DAG, SDLoc dl) {
4522 assert(VT.isVector() && "Expected a vector type");
4524 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4526 if (VT.is512BitVector()) {
4527 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4528 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4529 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4530 } else if (VT.is256BitVector()) {
4531 if (Subtarget->hasInt256()) { // AVX2
4532 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4533 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4535 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4536 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4538 } else if (VT.is128BitVector()) {
4539 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4541 llvm_unreachable("Unexpected vector type");
4543 return DAG.getBitcast(VT, Vec);
4546 /// Returns a vector_shuffle node for an unpackl operation.
4547 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4549 unsigned NumElems = VT.getVectorNumElements();
4550 SmallVector<int, 8> Mask;
4551 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4553 Mask.push_back(i + NumElems);
4555 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4558 /// Returns a vector_shuffle node for an unpackh operation.
4559 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4561 unsigned NumElems = VT.getVectorNumElements();
4562 SmallVector<int, 8> Mask;
4563 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4564 Mask.push_back(i + Half);
4565 Mask.push_back(i + NumElems + Half);
4567 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4570 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4571 /// This produces a shuffle where the low element of V2 is swizzled into the
4572 /// zero/undef vector, landing at element Idx.
4573 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4574 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4576 const X86Subtarget *Subtarget,
4577 SelectionDAG &DAG) {
4578 MVT VT = V2.getSimpleValueType();
4580 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4581 unsigned NumElems = VT.getVectorNumElements();
4582 SmallVector<int, 16> MaskVec;
4583 for (unsigned i = 0; i != NumElems; ++i)
4584 // If this is the insertion idx, put the low elt of V2 here.
4585 MaskVec.push_back(i == Idx ? NumElems : i);
4586 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4589 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4590 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4591 /// uses one source. Note that this will set IsUnary for shuffles which use a
4592 /// single input multiple times, and in those cases it will
4593 /// adjust the mask to only have indices within that single input.
4594 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4595 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4596 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4597 unsigned NumElems = VT.getVectorNumElements();
4601 bool IsFakeUnary = false;
4602 switch(N->getOpcode()) {
4603 case X86ISD::BLENDI:
4604 ImmN = N->getOperand(N->getNumOperands()-1);
4605 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4608 ImmN = N->getOperand(N->getNumOperands()-1);
4609 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4610 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4612 case X86ISD::UNPCKH:
4613 DecodeUNPCKHMask(VT, Mask);
4614 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4616 case X86ISD::UNPCKL:
4617 DecodeUNPCKLMask(VT, Mask);
4618 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4620 case X86ISD::MOVHLPS:
4621 DecodeMOVHLPSMask(NumElems, Mask);
4622 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4624 case X86ISD::MOVLHPS:
4625 DecodeMOVLHPSMask(NumElems, Mask);
4626 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4628 case X86ISD::PALIGNR:
4629 ImmN = N->getOperand(N->getNumOperands()-1);
4630 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4632 case X86ISD::PSHUFD:
4633 case X86ISD::VPERMILPI:
4634 ImmN = N->getOperand(N->getNumOperands()-1);
4635 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4638 case X86ISD::PSHUFHW:
4639 ImmN = N->getOperand(N->getNumOperands()-1);
4640 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4643 case X86ISD::PSHUFLW:
4644 ImmN = N->getOperand(N->getNumOperands()-1);
4645 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4648 case X86ISD::PSHUFB: {
4650 SDValue MaskNode = N->getOperand(1);
4651 while (MaskNode->getOpcode() == ISD::BITCAST)
4652 MaskNode = MaskNode->getOperand(0);
4654 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4655 // If we have a build-vector, then things are easy.
4656 EVT VT = MaskNode.getValueType();
4657 assert(VT.isVector() &&
4658 "Can't produce a non-vector with a build_vector!");
4659 if (!VT.isInteger())
4662 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4664 SmallVector<uint64_t, 32> RawMask;
4665 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4666 SDValue Op = MaskNode->getOperand(i);
4667 if (Op->getOpcode() == ISD::UNDEF) {
4668 RawMask.push_back((uint64_t)SM_SentinelUndef);
4671 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4674 APInt MaskElement = CN->getAPIntValue();
4676 // We now have to decode the element which could be any integer size and
4677 // extract each byte of it.
4678 for (int j = 0; j < NumBytesPerElement; ++j) {
4679 // Note that this is x86 and so always little endian: the low byte is
4680 // the first byte of the mask.
4681 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4682 MaskElement = MaskElement.lshr(8);
4685 DecodePSHUFBMask(RawMask, Mask);
4689 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4693 SDValue Ptr = MaskLoad->getBasePtr();
4694 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4695 Ptr->getOpcode() == X86ISD::WrapperRIP)
4696 Ptr = Ptr->getOperand(0);
4698 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4699 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4702 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4703 DecodePSHUFBMask(C, Mask);
4711 case X86ISD::VPERMI:
4712 ImmN = N->getOperand(N->getNumOperands()-1);
4713 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4718 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4720 case X86ISD::VPERM2X128:
4721 ImmN = N->getOperand(N->getNumOperands()-1);
4722 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4723 if (Mask.empty()) return false;
4724 // Mask only contains negative index if an element is zero.
4725 if (std::any_of(Mask.begin(), Mask.end(),
4726 [](int M){ return M == SM_SentinelZero; }))
4729 case X86ISD::MOVSLDUP:
4730 DecodeMOVSLDUPMask(VT, Mask);
4733 case X86ISD::MOVSHDUP:
4734 DecodeMOVSHDUPMask(VT, Mask);
4737 case X86ISD::MOVDDUP:
4738 DecodeMOVDDUPMask(VT, Mask);
4741 case X86ISD::MOVLHPD:
4742 case X86ISD::MOVLPD:
4743 case X86ISD::MOVLPS:
4744 // Not yet implemented
4746 case X86ISD::VPERMV: {
4748 SDValue MaskNode = N->getOperand(0);
4749 while (MaskNode->getOpcode() == ISD::BITCAST)
4750 MaskNode = MaskNode->getOperand(0);
4752 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4753 SmallVector<uint64_t, 32> RawMask;
4754 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4755 // If we have a build-vector, then things are easy.
4756 assert(MaskNode.getValueType().isInteger() &&
4757 MaskNode.getValueType().getVectorNumElements() ==
4758 VT.getVectorNumElements());
4760 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4761 SDValue Op = MaskNode->getOperand(i);
4762 if (Op->getOpcode() == ISD::UNDEF)
4763 RawMask.push_back((uint64_t)SM_SentinelUndef);
4764 else if (isa<ConstantSDNode>(Op)) {
4765 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4766 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4770 DecodeVPERMVMask(RawMask, Mask);
4773 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4774 unsigned NumEltsInMask = MaskNode->getNumOperands();
4775 MaskNode = MaskNode->getOperand(0);
4776 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4778 APInt MaskEltValue = CN->getAPIntValue();
4779 for (unsigned i = 0; i < NumEltsInMask; ++i)
4780 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4781 DecodeVPERMVMask(RawMask, Mask);
4784 // It may be a scalar load
4787 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4791 SDValue Ptr = MaskLoad->getBasePtr();
4792 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4793 Ptr->getOpcode() == X86ISD::WrapperRIP)
4794 Ptr = Ptr->getOperand(0);
4796 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4797 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4800 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4802 DecodeVPERMVMask(C, VT, Mask);
4809 case X86ISD::VPERMV3: {
4811 SDValue MaskNode = N->getOperand(1);
4812 while (MaskNode->getOpcode() == ISD::BITCAST)
4813 MaskNode = MaskNode->getOperand(1);
4815 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4816 // If we have a build-vector, then things are easy.
4817 assert(MaskNode.getValueType().isInteger() &&
4818 MaskNode.getValueType().getVectorNumElements() ==
4819 VT.getVectorNumElements());
4821 SmallVector<uint64_t, 32> RawMask;
4822 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4824 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4825 SDValue Op = MaskNode->getOperand(i);
4826 if (Op->getOpcode() == ISD::UNDEF)
4827 RawMask.push_back((uint64_t)SM_SentinelUndef);
4829 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4832 APInt MaskElement = CN->getAPIntValue();
4833 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4836 DecodeVPERMV3Mask(RawMask, Mask);
4840 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4844 SDValue Ptr = MaskLoad->getBasePtr();
4845 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4846 Ptr->getOpcode() == X86ISD::WrapperRIP)
4847 Ptr = Ptr->getOperand(0);
4849 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4850 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4853 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4855 DecodeVPERMV3Mask(C, VT, Mask);
4862 default: llvm_unreachable("unknown target shuffle node");
4865 // If we have a fake unary shuffle, the shuffle mask is spread across two
4866 // inputs that are actually the same node. Re-map the mask to always point
4867 // into the first input.
4870 if (M >= (int)Mask.size())
4876 /// Returns the scalar element that will make up the ith
4877 /// element of the result of the vector shuffle.
4878 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4881 return SDValue(); // Limit search depth.
4883 SDValue V = SDValue(N, 0);
4884 EVT VT = V.getValueType();
4885 unsigned Opcode = V.getOpcode();
4887 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4888 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4889 int Elt = SV->getMaskElt(Index);
4892 return DAG.getUNDEF(VT.getVectorElementType());
4894 unsigned NumElems = VT.getVectorNumElements();
4895 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4896 : SV->getOperand(1);
4897 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4900 // Recurse into target specific vector shuffles to find scalars.
4901 if (isTargetShuffle(Opcode)) {
4902 MVT ShufVT = V.getSimpleValueType();
4903 unsigned NumElems = ShufVT.getVectorNumElements();
4904 SmallVector<int, 16> ShuffleMask;
4907 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4910 int Elt = ShuffleMask[Index];
4912 return DAG.getUNDEF(ShufVT.getVectorElementType());
4914 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4916 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4920 // Actual nodes that may contain scalar elements
4921 if (Opcode == ISD::BITCAST) {
4922 V = V.getOperand(0);
4923 EVT SrcVT = V.getValueType();
4924 unsigned NumElems = VT.getVectorNumElements();
4926 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4930 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4931 return (Index == 0) ? V.getOperand(0)
4932 : DAG.getUNDEF(VT.getVectorElementType());
4934 if (V.getOpcode() == ISD::BUILD_VECTOR)
4935 return V.getOperand(Index);
4940 /// Custom lower build_vector of v16i8.
4941 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4942 unsigned NumNonZero, unsigned NumZero,
4944 const X86Subtarget* Subtarget,
4945 const TargetLowering &TLI) {
4953 // SSE4.1 - use PINSRB to insert each byte directly.
4954 if (Subtarget->hasSSE41()) {
4955 for (unsigned i = 0; i < 16; ++i) {
4956 bool isNonZero = (NonZeros & (1 << i)) != 0;
4960 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4962 V = DAG.getUNDEF(MVT::v16i8);
4965 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4966 MVT::v16i8, V, Op.getOperand(i),
4967 DAG.getIntPtrConstant(i, dl));
4974 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4975 for (unsigned i = 0; i < 16; ++i) {
4976 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4977 if (ThisIsNonZero && First) {
4979 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4981 V = DAG.getUNDEF(MVT::v8i16);
4986 SDValue ThisElt, LastElt;
4987 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4988 if (LastIsNonZero) {
4989 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4990 MVT::i16, Op.getOperand(i-1));
4992 if (ThisIsNonZero) {
4993 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4994 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4995 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4997 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5001 if (ThisElt.getNode())
5002 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5003 DAG.getIntPtrConstant(i/2, dl));
5007 return DAG.getBitcast(MVT::v16i8, V);
5010 /// Custom lower build_vector of v8i16.
5011 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5012 unsigned NumNonZero, unsigned NumZero,
5014 const X86Subtarget* Subtarget,
5015 const TargetLowering &TLI) {
5022 for (unsigned i = 0; i < 8; ++i) {
5023 bool isNonZero = (NonZeros & (1 << i)) != 0;
5027 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5029 V = DAG.getUNDEF(MVT::v8i16);
5032 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5033 MVT::v8i16, V, Op.getOperand(i),
5034 DAG.getIntPtrConstant(i, dl));
5041 /// Custom lower build_vector of v4i32 or v4f32.
5042 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5043 const X86Subtarget *Subtarget,
5044 const TargetLowering &TLI) {
5045 // Find all zeroable elements.
5046 std::bitset<4> Zeroable;
5047 for (int i=0; i < 4; ++i) {
5048 SDValue Elt = Op->getOperand(i);
5049 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5051 assert(Zeroable.size() - Zeroable.count() > 1 &&
5052 "We expect at least two non-zero elements!");
5054 // We only know how to deal with build_vector nodes where elements are either
5055 // zeroable or extract_vector_elt with constant index.
5056 SDValue FirstNonZero;
5057 unsigned FirstNonZeroIdx;
5058 for (unsigned i=0; i < 4; ++i) {
5061 SDValue Elt = Op->getOperand(i);
5062 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5063 !isa<ConstantSDNode>(Elt.getOperand(1)))
5065 // Make sure that this node is extracting from a 128-bit vector.
5066 MVT VT = Elt.getOperand(0).getSimpleValueType();
5067 if (!VT.is128BitVector())
5069 if (!FirstNonZero.getNode()) {
5071 FirstNonZeroIdx = i;
5075 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5076 SDValue V1 = FirstNonZero.getOperand(0);
5077 MVT VT = V1.getSimpleValueType();
5079 // See if this build_vector can be lowered as a blend with zero.
5081 unsigned EltMaskIdx, EltIdx;
5083 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5084 if (Zeroable[EltIdx]) {
5085 // The zero vector will be on the right hand side.
5086 Mask[EltIdx] = EltIdx+4;
5090 Elt = Op->getOperand(EltIdx);
5091 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5092 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5093 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5095 Mask[EltIdx] = EltIdx;
5099 // Let the shuffle legalizer deal with blend operations.
5100 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5101 if (V1.getSimpleValueType() != VT)
5102 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5103 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5106 // See if we can lower this build_vector to a INSERTPS.
5107 if (!Subtarget->hasSSE41())
5110 SDValue V2 = Elt.getOperand(0);
5111 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5114 bool CanFold = true;
5115 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5119 SDValue Current = Op->getOperand(i);
5120 SDValue SrcVector = Current->getOperand(0);
5123 CanFold = SrcVector == V1 &&
5124 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5130 assert(V1.getNode() && "Expected at least two non-zero elements!");
5131 if (V1.getSimpleValueType() != MVT::v4f32)
5132 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5133 if (V2.getSimpleValueType() != MVT::v4f32)
5134 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5136 // Ok, we can emit an INSERTPS instruction.
5137 unsigned ZMask = Zeroable.to_ulong();
5139 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5140 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5142 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5143 DAG.getIntPtrConstant(InsertPSMask, DL));
5144 return DAG.getBitcast(VT, Result);
5147 /// Return a vector logical shift node.
5148 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5149 unsigned NumBits, SelectionDAG &DAG,
5150 const TargetLowering &TLI, SDLoc dl) {
5151 assert(VT.is128BitVector() && "Unknown type for VShift");
5152 MVT ShVT = MVT::v2i64;
5153 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5154 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5155 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5156 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5157 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5158 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5162 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5164 // Check if the scalar load can be widened into a vector load. And if
5165 // the address is "base + cst" see if the cst can be "absorbed" into
5166 // the shuffle mask.
5167 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5168 SDValue Ptr = LD->getBasePtr();
5169 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5171 EVT PVT = LD->getValueType(0);
5172 if (PVT != MVT::i32 && PVT != MVT::f32)
5177 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5178 FI = FINode->getIndex();
5180 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5181 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5182 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5183 Offset = Ptr.getConstantOperandVal(1);
5184 Ptr = Ptr.getOperand(0);
5189 // FIXME: 256-bit vector instructions don't require a strict alignment,
5190 // improve this code to support it better.
5191 unsigned RequiredAlign = VT.getSizeInBits()/8;
5192 SDValue Chain = LD->getChain();
5193 // Make sure the stack object alignment is at least 16 or 32.
5194 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5195 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5196 if (MFI->isFixedObjectIndex(FI)) {
5197 // Can't change the alignment. FIXME: It's possible to compute
5198 // the exact stack offset and reference FI + adjust offset instead.
5199 // If someone *really* cares about this. That's the way to implement it.
5202 MFI->setObjectAlignment(FI, RequiredAlign);
5206 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5207 // Ptr + (Offset & ~15).
5210 if ((Offset % RequiredAlign) & 3)
5212 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5215 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5216 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5219 int EltNo = (Offset - StartOffset) >> 2;
5220 unsigned NumElems = VT.getVectorNumElements();
5222 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5223 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5224 LD->getPointerInfo().getWithOffset(StartOffset),
5225 false, false, false, 0);
5227 SmallVector<int, 8> Mask(NumElems, EltNo);
5229 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5235 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5236 /// elements can be replaced by a single large load which has the same value as
5237 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5239 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5241 /// FIXME: we'd also like to handle the case where the last elements are zero
5242 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5243 /// There's even a handy isZeroNode for that purpose.
5244 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5245 SDLoc &DL, SelectionDAG &DAG,
5246 bool isAfterLegalize) {
5247 unsigned NumElems = Elts.size();
5249 LoadSDNode *LDBase = nullptr;
5250 unsigned LastLoadedElt = -1U;
5252 // For each element in the initializer, see if we've found a load or an undef.
5253 // If we don't find an initial load element, or later load elements are
5254 // non-consecutive, bail out.
5255 for (unsigned i = 0; i < NumElems; ++i) {
5256 SDValue Elt = Elts[i];
5257 // Look through a bitcast.
5258 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5259 Elt = Elt.getOperand(0);
5260 if (!Elt.getNode() ||
5261 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5264 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5266 LDBase = cast<LoadSDNode>(Elt.getNode());
5270 if (Elt.getOpcode() == ISD::UNDEF)
5273 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5274 EVT LdVT = Elt.getValueType();
5275 // Each loaded element must be the correct fractional portion of the
5276 // requested vector load.
5277 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5279 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5284 // If we have found an entire vector of loads and undefs, then return a large
5285 // load of the entire vector width starting at the base pointer. If we found
5286 // consecutive loads for the low half, generate a vzext_load node.
5287 if (LastLoadedElt == NumElems - 1) {
5288 assert(LDBase && "Did not find base load for merging consecutive loads");
5289 EVT EltVT = LDBase->getValueType(0);
5290 // Ensure that the input vector size for the merged loads matches the
5291 // cumulative size of the input elements.
5292 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5295 if (isAfterLegalize &&
5296 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5299 SDValue NewLd = SDValue();
5301 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5302 LDBase->getPointerInfo(), LDBase->isVolatile(),
5303 LDBase->isNonTemporal(), LDBase->isInvariant(),
5304 LDBase->getAlignment());
5306 if (LDBase->hasAnyUseOfValue(1)) {
5307 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5309 SDValue(NewLd.getNode(), 1));
5310 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5311 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5312 SDValue(NewLd.getNode(), 1));
5318 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5319 //of a v4i32 / v4f32. It's probably worth generalizing.
5320 EVT EltVT = VT.getVectorElementType();
5321 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5322 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5323 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5324 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5326 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5327 LDBase->getPointerInfo(),
5328 LDBase->getAlignment(),
5329 false/*isVolatile*/, true/*ReadMem*/,
5332 // Make sure the newly-created LOAD is in the same position as LDBase in
5333 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5334 // update uses of LDBase's output chain to use the TokenFactor.
5335 if (LDBase->hasAnyUseOfValue(1)) {
5336 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5337 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5338 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5339 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5340 SDValue(ResNode.getNode(), 1));
5343 return DAG.getBitcast(VT, ResNode);
5348 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5349 /// to generate a splat value for the following cases:
5350 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5351 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5352 /// a scalar load, or a constant.
5353 /// The VBROADCAST node is returned when a pattern is found,
5354 /// or SDValue() otherwise.
5355 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5356 SelectionDAG &DAG) {
5357 // VBROADCAST requires AVX.
5358 // TODO: Splats could be generated for non-AVX CPUs using SSE
5359 // instructions, but there's less potential gain for only 128-bit vectors.
5360 if (!Subtarget->hasAVX())
5363 MVT VT = Op.getSimpleValueType();
5366 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5367 "Unsupported vector type for broadcast.");
5372 switch (Op.getOpcode()) {
5374 // Unknown pattern found.
5377 case ISD::BUILD_VECTOR: {
5378 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5379 BitVector UndefElements;
5380 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5382 // We need a splat of a single value to use broadcast, and it doesn't
5383 // make any sense if the value is only in one element of the vector.
5384 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5388 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5389 Ld.getOpcode() == ISD::ConstantFP);
5391 // Make sure that all of the users of a non-constant load are from the
5392 // BUILD_VECTOR node.
5393 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5398 case ISD::VECTOR_SHUFFLE: {
5399 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5401 // Shuffles must have a splat mask where the first element is
5403 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5406 SDValue Sc = Op.getOperand(0);
5407 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5408 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5410 if (!Subtarget->hasInt256())
5413 // Use the register form of the broadcast instruction available on AVX2.
5414 if (VT.getSizeInBits() >= 256)
5415 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5416 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5419 Ld = Sc.getOperand(0);
5420 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5421 Ld.getOpcode() == ISD::ConstantFP);
5423 // The scalar_to_vector node and the suspected
5424 // load node must have exactly one user.
5425 // Constants may have multiple users.
5427 // AVX-512 has register version of the broadcast
5428 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5429 Ld.getValueType().getSizeInBits() >= 32;
5430 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5437 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5438 bool IsGE256 = (VT.getSizeInBits() >= 256);
5440 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5441 // instruction to save 8 or more bytes of constant pool data.
5442 // TODO: If multiple splats are generated to load the same constant,
5443 // it may be detrimental to overall size. There needs to be a way to detect
5444 // that condition to know if this is truly a size win.
5445 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5447 // Handle broadcasting a single constant scalar from the constant pool
5449 // On Sandybridge (no AVX2), it is still better to load a constant vector
5450 // from the constant pool and not to broadcast it from a scalar.
5451 // But override that restriction when optimizing for size.
5452 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5453 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5454 EVT CVT = Ld.getValueType();
5455 assert(!CVT.isVector() && "Must not broadcast a vector type");
5457 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5458 // For size optimization, also splat v2f64 and v2i64, and for size opt
5459 // with AVX2, also splat i8 and i16.
5460 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5461 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5462 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5463 const Constant *C = nullptr;
5464 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5465 C = CI->getConstantIntValue();
5466 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5467 C = CF->getConstantFPValue();
5469 assert(C && "Invalid constant type");
5471 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5473 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5474 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5476 CVT, dl, DAG.getEntryNode(), CP,
5477 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5478 false, false, Alignment);
5480 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5484 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5486 // Handle AVX2 in-register broadcasts.
5487 if (!IsLoad && Subtarget->hasInt256() &&
5488 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5489 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5491 // The scalar source must be a normal load.
5495 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5496 (Subtarget->hasVLX() && ScalarSize == 64))
5497 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5499 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5500 // double since there is no vbroadcastsd xmm
5501 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5502 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5503 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5506 // Unsupported broadcast.
5510 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5511 /// underlying vector and index.
5513 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5515 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5517 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5518 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5521 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5523 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5525 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5526 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5529 // In this case the vector is the extract_subvector expression and the index
5530 // is 2, as specified by the shuffle.
5531 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5532 SDValue ShuffleVec = SVOp->getOperand(0);
5533 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5534 assert(ShuffleVecVT.getVectorElementType() ==
5535 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5537 int ShuffleIdx = SVOp->getMaskElt(Idx);
5538 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5539 ExtractedFromVec = ShuffleVec;
5545 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5546 MVT VT = Op.getSimpleValueType();
5548 // Skip if insert_vec_elt is not supported.
5549 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5550 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5554 unsigned NumElems = Op.getNumOperands();
5558 SmallVector<unsigned, 4> InsertIndices;
5559 SmallVector<int, 8> Mask(NumElems, -1);
5561 for (unsigned i = 0; i != NumElems; ++i) {
5562 unsigned Opc = Op.getOperand(i).getOpcode();
5564 if (Opc == ISD::UNDEF)
5567 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5568 // Quit if more than 1 elements need inserting.
5569 if (InsertIndices.size() > 1)
5572 InsertIndices.push_back(i);
5576 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5577 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5578 // Quit if non-constant index.
5579 if (!isa<ConstantSDNode>(ExtIdx))
5581 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5583 // Quit if extracted from vector of different type.
5584 if (ExtractedFromVec.getValueType() != VT)
5587 if (!VecIn1.getNode())
5588 VecIn1 = ExtractedFromVec;
5589 else if (VecIn1 != ExtractedFromVec) {
5590 if (!VecIn2.getNode())
5591 VecIn2 = ExtractedFromVec;
5592 else if (VecIn2 != ExtractedFromVec)
5593 // Quit if more than 2 vectors to shuffle
5597 if (ExtractedFromVec == VecIn1)
5599 else if (ExtractedFromVec == VecIn2)
5600 Mask[i] = Idx + NumElems;
5603 if (!VecIn1.getNode())
5606 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5607 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5608 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5609 unsigned Idx = InsertIndices[i];
5610 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5611 DAG.getIntPtrConstant(Idx, DL));
5617 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5618 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5619 Op.getScalarValueSizeInBits() == 1 &&
5620 "Can not convert non-constant vector");
5621 uint64_t Immediate = 0;
5622 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5623 SDValue In = Op.getOperand(idx);
5624 if (In.getOpcode() != ISD::UNDEF)
5625 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5629 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5630 return DAG.getConstant(Immediate, dl, VT);
5632 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5634 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5636 MVT VT = Op.getSimpleValueType();
5637 assert((VT.getVectorElementType() == MVT::i1) &&
5638 "Unexpected type in LowerBUILD_VECTORvXi1!");
5641 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5642 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5643 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5644 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5647 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5648 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5649 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5650 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5653 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5654 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5655 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5656 return DAG.getBitcast(VT, Imm);
5657 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5658 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5659 DAG.getIntPtrConstant(0, dl));
5662 // Vector has one or more non-const elements
5663 uint64_t Immediate = 0;
5664 SmallVector<unsigned, 16> NonConstIdx;
5665 bool IsSplat = true;
5666 bool HasConstElts = false;
5668 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5669 SDValue In = Op.getOperand(idx);
5670 if (In.getOpcode() == ISD::UNDEF)
5672 if (!isa<ConstantSDNode>(In))
5673 NonConstIdx.push_back(idx);
5675 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5676 HasConstElts = true;
5680 else if (In != Op.getOperand(SplatIdx))
5684 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5686 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5687 DAG.getConstant(1, dl, VT),
5688 DAG.getConstant(0, dl, VT));
5690 // insert elements one by one
5694 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5695 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5697 else if (HasConstElts)
5698 Imm = DAG.getConstant(0, dl, VT);
5700 Imm = DAG.getUNDEF(VT);
5701 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5702 DstVec = DAG.getBitcast(VT, Imm);
5704 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5705 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5706 DAG.getIntPtrConstant(0, dl));
5709 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5710 unsigned InsertIdx = NonConstIdx[i];
5711 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5712 Op.getOperand(InsertIdx),
5713 DAG.getIntPtrConstant(InsertIdx, dl));
5718 /// \brief Return true if \p N implements a horizontal binop and return the
5719 /// operands for the horizontal binop into V0 and V1.
5721 /// This is a helper function of LowerToHorizontalOp().
5722 /// This function checks that the build_vector \p N in input implements a
5723 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5724 /// operation to match.
5725 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5726 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5727 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5730 /// This function only analyzes elements of \p N whose indices are
5731 /// in range [BaseIdx, LastIdx).
5732 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5734 unsigned BaseIdx, unsigned LastIdx,
5735 SDValue &V0, SDValue &V1) {
5736 EVT VT = N->getValueType(0);
5738 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5739 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5740 "Invalid Vector in input!");
5742 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5743 bool CanFold = true;
5744 unsigned ExpectedVExtractIdx = BaseIdx;
5745 unsigned NumElts = LastIdx - BaseIdx;
5746 V0 = DAG.getUNDEF(VT);
5747 V1 = DAG.getUNDEF(VT);
5749 // Check if N implements a horizontal binop.
5750 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5751 SDValue Op = N->getOperand(i + BaseIdx);
5754 if (Op->getOpcode() == ISD::UNDEF) {
5755 // Update the expected vector extract index.
5756 if (i * 2 == NumElts)
5757 ExpectedVExtractIdx = BaseIdx;
5758 ExpectedVExtractIdx += 2;
5762 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5767 SDValue Op0 = Op.getOperand(0);
5768 SDValue Op1 = Op.getOperand(1);
5770 // Try to match the following pattern:
5771 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5772 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5773 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5774 Op0.getOperand(0) == Op1.getOperand(0) &&
5775 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5776 isa<ConstantSDNode>(Op1.getOperand(1)));
5780 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5781 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5783 if (i * 2 < NumElts) {
5784 if (V0.getOpcode() == ISD::UNDEF) {
5785 V0 = Op0.getOperand(0);
5786 if (V0.getValueType() != VT)
5790 if (V1.getOpcode() == ISD::UNDEF) {
5791 V1 = Op0.getOperand(0);
5792 if (V1.getValueType() != VT)
5795 if (i * 2 == NumElts)
5796 ExpectedVExtractIdx = BaseIdx;
5799 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5800 if (I0 == ExpectedVExtractIdx)
5801 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5802 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5803 // Try to match the following dag sequence:
5804 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5805 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5809 ExpectedVExtractIdx += 2;
5815 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5816 /// a concat_vector.
5818 /// This is a helper function of LowerToHorizontalOp().
5819 /// This function expects two 256-bit vectors called V0 and V1.
5820 /// At first, each vector is split into two separate 128-bit vectors.
5821 /// Then, the resulting 128-bit vectors are used to implement two
5822 /// horizontal binary operations.
5824 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5826 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5827 /// the two new horizontal binop.
5828 /// When Mode is set, the first horizontal binop dag node would take as input
5829 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5830 /// horizontal binop dag node would take as input the lower 128-bit of V1
5831 /// and the upper 128-bit of V1.
5833 /// HADD V0_LO, V0_HI
5834 /// HADD V1_LO, V1_HI
5836 /// Otherwise, the first horizontal binop dag node takes as input the lower
5837 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5838 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5840 /// HADD V0_LO, V1_LO
5841 /// HADD V0_HI, V1_HI
5843 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5844 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5845 /// the upper 128-bits of the result.
5846 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5847 SDLoc DL, SelectionDAG &DAG,
5848 unsigned X86Opcode, bool Mode,
5849 bool isUndefLO, bool isUndefHI) {
5850 EVT VT = V0.getValueType();
5851 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5852 "Invalid nodes in input!");
5854 unsigned NumElts = VT.getVectorNumElements();
5855 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5856 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5857 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5858 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5859 EVT NewVT = V0_LO.getValueType();
5861 SDValue LO = DAG.getUNDEF(NewVT);
5862 SDValue HI = DAG.getUNDEF(NewVT);
5865 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5866 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5867 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5868 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5869 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5871 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5872 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5873 V1_LO->getOpcode() != ISD::UNDEF))
5874 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5876 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5877 V1_HI->getOpcode() != ISD::UNDEF))
5878 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5881 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5884 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5886 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5887 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5888 EVT VT = BV->getValueType(0);
5889 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5890 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5894 unsigned NumElts = VT.getVectorNumElements();
5895 SDValue InVec0 = DAG.getUNDEF(VT);
5896 SDValue InVec1 = DAG.getUNDEF(VT);
5898 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5899 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5901 // Odd-numbered elements in the input build vector are obtained from
5902 // adding two integer/float elements.
5903 // Even-numbered elements in the input build vector are obtained from
5904 // subtracting two integer/float elements.
5905 unsigned ExpectedOpcode = ISD::FSUB;
5906 unsigned NextExpectedOpcode = ISD::FADD;
5907 bool AddFound = false;
5908 bool SubFound = false;
5910 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5911 SDValue Op = BV->getOperand(i);
5913 // Skip 'undef' values.
5914 unsigned Opcode = Op.getOpcode();
5915 if (Opcode == ISD::UNDEF) {
5916 std::swap(ExpectedOpcode, NextExpectedOpcode);
5920 // Early exit if we found an unexpected opcode.
5921 if (Opcode != ExpectedOpcode)
5924 SDValue Op0 = Op.getOperand(0);
5925 SDValue Op1 = Op.getOperand(1);
5927 // Try to match the following pattern:
5928 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5929 // Early exit if we cannot match that sequence.
5930 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5931 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5932 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5933 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5934 Op0.getOperand(1) != Op1.getOperand(1))
5937 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5941 // We found a valid add/sub node. Update the information accordingly.
5947 // Update InVec0 and InVec1.
5948 if (InVec0.getOpcode() == ISD::UNDEF) {
5949 InVec0 = Op0.getOperand(0);
5950 if (InVec0.getValueType() != VT)
5953 if (InVec1.getOpcode() == ISD::UNDEF) {
5954 InVec1 = Op1.getOperand(0);
5955 if (InVec1.getValueType() != VT)
5959 // Make sure that operands in input to each add/sub node always
5960 // come from a same pair of vectors.
5961 if (InVec0 != Op0.getOperand(0)) {
5962 if (ExpectedOpcode == ISD::FSUB)
5965 // FADD is commutable. Try to commute the operands
5966 // and then test again.
5967 std::swap(Op0, Op1);
5968 if (InVec0 != Op0.getOperand(0))
5972 if (InVec1 != Op1.getOperand(0))
5975 // Update the pair of expected opcodes.
5976 std::swap(ExpectedOpcode, NextExpectedOpcode);
5979 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5980 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5981 InVec1.getOpcode() != ISD::UNDEF)
5982 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5987 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5988 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5989 const X86Subtarget *Subtarget,
5990 SelectionDAG &DAG) {
5991 EVT VT = BV->getValueType(0);
5992 unsigned NumElts = VT.getVectorNumElements();
5993 unsigned NumUndefsLO = 0;
5994 unsigned NumUndefsHI = 0;
5995 unsigned Half = NumElts/2;
5997 // Count the number of UNDEF operands in the build_vector in input.
5998 for (unsigned i = 0, e = Half; i != e; ++i)
5999 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6002 for (unsigned i = Half, e = NumElts; i != e; ++i)
6003 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6006 // Early exit if this is either a build_vector of all UNDEFs or all the
6007 // operands but one are UNDEF.
6008 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6012 SDValue InVec0, InVec1;
6013 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6014 // Try to match an SSE3 float HADD/HSUB.
6015 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6016 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6018 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6019 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6020 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6021 // Try to match an SSSE3 integer HADD/HSUB.
6022 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6023 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6025 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6026 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6029 if (!Subtarget->hasAVX())
6032 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6033 // Try to match an AVX horizontal add/sub of packed single/double
6034 // precision floating point values from 256-bit vectors.
6035 SDValue InVec2, InVec3;
6036 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6037 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6038 ((InVec0.getOpcode() == ISD::UNDEF ||
6039 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6040 ((InVec1.getOpcode() == ISD::UNDEF ||
6041 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6042 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6044 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6045 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6046 ((InVec0.getOpcode() == ISD::UNDEF ||
6047 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6048 ((InVec1.getOpcode() == ISD::UNDEF ||
6049 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6050 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6051 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6052 // Try to match an AVX2 horizontal add/sub of signed integers.
6053 SDValue InVec2, InVec3;
6055 bool CanFold = true;
6057 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6058 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6059 ((InVec0.getOpcode() == ISD::UNDEF ||
6060 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6061 ((InVec1.getOpcode() == ISD::UNDEF ||
6062 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6063 X86Opcode = X86ISD::HADD;
6064 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6065 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6066 ((InVec0.getOpcode() == ISD::UNDEF ||
6067 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6068 ((InVec1.getOpcode() == ISD::UNDEF ||
6069 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6070 X86Opcode = X86ISD::HSUB;
6075 // Fold this build_vector into a single horizontal add/sub.
6076 // Do this only if the target has AVX2.
6077 if (Subtarget->hasAVX2())
6078 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6080 // Do not try to expand this build_vector into a pair of horizontal
6081 // add/sub if we can emit a pair of scalar add/sub.
6082 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6085 // Convert this build_vector into a pair of horizontal binop followed by
6087 bool isUndefLO = NumUndefsLO == Half;
6088 bool isUndefHI = NumUndefsHI == Half;
6089 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6090 isUndefLO, isUndefHI);
6094 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6095 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6097 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6098 X86Opcode = X86ISD::HADD;
6099 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6100 X86Opcode = X86ISD::HSUB;
6101 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6102 X86Opcode = X86ISD::FHADD;
6103 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6104 X86Opcode = X86ISD::FHSUB;
6108 // Don't try to expand this build_vector into a pair of horizontal add/sub
6109 // if we can simply emit a pair of scalar add/sub.
6110 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6113 // Convert this build_vector into two horizontal add/sub followed by
6115 bool isUndefLO = NumUndefsLO == Half;
6116 bool isUndefHI = NumUndefsHI == Half;
6117 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6118 isUndefLO, isUndefHI);
6125 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6128 MVT VT = Op.getSimpleValueType();
6129 MVT ExtVT = VT.getVectorElementType();
6130 unsigned NumElems = Op.getNumOperands();
6132 // Generate vectors for predicate vectors.
6133 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6134 return LowerBUILD_VECTORvXi1(Op, DAG);
6136 // Vectors containing all zeros can be matched by pxor and xorps later
6137 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6138 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6139 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6140 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6143 return getZeroVector(VT, Subtarget, DAG, dl);
6146 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6147 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6148 // vpcmpeqd on 256-bit vectors.
6149 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6150 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6153 if (!VT.is512BitVector())
6154 return getOnesVector(VT, Subtarget, DAG, dl);
6157 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6158 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6160 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6161 return HorizontalOp;
6162 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6165 unsigned EVTBits = ExtVT.getSizeInBits();
6167 unsigned NumZero = 0;
6168 unsigned NumNonZero = 0;
6169 unsigned NonZeros = 0;
6170 bool IsAllConstants = true;
6171 SmallSet<SDValue, 8> Values;
6172 for (unsigned i = 0; i < NumElems; ++i) {
6173 SDValue Elt = Op.getOperand(i);
6174 if (Elt.getOpcode() == ISD::UNDEF)
6177 if (Elt.getOpcode() != ISD::Constant &&
6178 Elt.getOpcode() != ISD::ConstantFP)
6179 IsAllConstants = false;
6180 if (X86::isZeroNode(Elt))
6183 NonZeros |= (1 << i);
6188 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6189 if (NumNonZero == 0)
6190 return DAG.getUNDEF(VT);
6192 // Special case for single non-zero, non-undef, element.
6193 if (NumNonZero == 1) {
6194 unsigned Idx = countTrailingZeros(NonZeros);
6195 SDValue Item = Op.getOperand(Idx);
6197 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6198 // the value are obviously zero, truncate the value to i32 and do the
6199 // insertion that way. Only do this if the value is non-constant or if the
6200 // value is a constant being inserted into element 0. It is cheaper to do
6201 // a constant pool load than it is to do a movd + shuffle.
6202 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6203 (!IsAllConstants || Idx == 0)) {
6204 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6206 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6207 EVT VecVT = MVT::v4i32;
6209 // Truncate the value (which may itself be a constant) to i32, and
6210 // convert it to a vector with movd (S2V+shuffle to zero extend).
6211 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6212 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6213 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6214 Item, Idx * 2, true, Subtarget, DAG));
6218 // If we have a constant or non-constant insertion into the low element of
6219 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6220 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6221 // depending on what the source datatype is.
6224 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6226 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6227 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6228 if (VT.is512BitVector()) {
6229 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6230 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6231 Item, DAG.getIntPtrConstant(0, dl));
6233 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6234 "Expected an SSE value type!");
6235 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6236 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6237 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6240 // We can't directly insert an i8 or i16 into a vector, so zero extend
6242 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6243 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6244 if (VT.is256BitVector()) {
6245 if (Subtarget->hasAVX()) {
6246 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6247 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6249 // Without AVX, we need to extend to a 128-bit vector and then
6250 // insert into the 256-bit vector.
6251 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6252 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6253 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6256 assert(VT.is128BitVector() && "Expected an SSE value type!");
6257 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6258 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6260 return DAG.getBitcast(VT, Item);
6264 // Is it a vector logical left shift?
6265 if (NumElems == 2 && Idx == 1 &&
6266 X86::isZeroNode(Op.getOperand(0)) &&
6267 !X86::isZeroNode(Op.getOperand(1))) {
6268 unsigned NumBits = VT.getSizeInBits();
6269 return getVShift(true, VT,
6270 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6271 VT, Op.getOperand(1)),
6272 NumBits/2, DAG, *this, dl);
6275 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6278 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6279 // is a non-constant being inserted into an element other than the low one,
6280 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6281 // movd/movss) to move this into the low element, then shuffle it into
6283 if (EVTBits == 32) {
6284 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6285 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6289 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6290 if (Values.size() == 1) {
6291 if (EVTBits == 32) {
6292 // Instead of a shuffle like this:
6293 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6294 // Check if it's possible to issue this instead.
6295 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6296 unsigned Idx = countTrailingZeros(NonZeros);
6297 SDValue Item = Op.getOperand(Idx);
6298 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6299 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6304 // A vector full of immediates; various special cases are already
6305 // handled, so this is best done with a single constant-pool load.
6309 // For AVX-length vectors, see if we can use a vector load to get all of the
6310 // elements, otherwise build the individual 128-bit pieces and use
6311 // shuffles to put them in place.
6312 if (VT.is256BitVector() || VT.is512BitVector()) {
6313 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6315 // Check for a build vector of consecutive loads.
6316 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6319 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6321 // Build both the lower and upper subvector.
6322 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6323 makeArrayRef(&V[0], NumElems/2));
6324 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6325 makeArrayRef(&V[NumElems / 2], NumElems/2));
6327 // Recreate the wider vector with the lower and upper part.
6328 if (VT.is256BitVector())
6329 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6330 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6333 // Let legalizer expand 2-wide build_vectors.
6334 if (EVTBits == 64) {
6335 if (NumNonZero == 1) {
6336 // One half is zero or undef.
6337 unsigned Idx = countTrailingZeros(NonZeros);
6338 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6339 Op.getOperand(Idx));
6340 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6345 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6346 if (EVTBits == 8 && NumElems == 16)
6347 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6351 if (EVTBits == 16 && NumElems == 8)
6352 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6356 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6357 if (EVTBits == 32 && NumElems == 4)
6358 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6361 // If element VT is == 32 bits, turn it into a number of shuffles.
6362 SmallVector<SDValue, 8> V(NumElems);
6363 if (NumElems == 4 && NumZero > 0) {
6364 for (unsigned i = 0; i < 4; ++i) {
6365 bool isZero = !(NonZeros & (1 << i));
6367 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6369 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6372 for (unsigned i = 0; i < 2; ++i) {
6373 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6376 V[i] = V[i*2]; // Must be a zero vector.
6379 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6382 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6385 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6390 bool Reverse1 = (NonZeros & 0x3) == 2;
6391 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6395 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6396 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6398 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6401 if (Values.size() > 1 && VT.is128BitVector()) {
6402 // Check for a build vector of consecutive loads.
6403 for (unsigned i = 0; i < NumElems; ++i)
6404 V[i] = Op.getOperand(i);
6406 // Check for elements which are consecutive loads.
6407 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6410 // Check for a build vector from mostly shuffle plus few inserting.
6411 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6414 // For SSE 4.1, use insertps to put the high elements into the low element.
6415 if (Subtarget->hasSSE41()) {
6417 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6418 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6420 Result = DAG.getUNDEF(VT);
6422 for (unsigned i = 1; i < NumElems; ++i) {
6423 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6424 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6425 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6430 // Otherwise, expand into a number of unpckl*, start by extending each of
6431 // our (non-undef) elements to the full vector width with the element in the
6432 // bottom slot of the vector (which generates no code for SSE).
6433 for (unsigned i = 0; i < NumElems; ++i) {
6434 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6435 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6437 V[i] = DAG.getUNDEF(VT);
6440 // Next, we iteratively mix elements, e.g. for v4f32:
6441 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6442 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6443 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6444 unsigned EltStride = NumElems >> 1;
6445 while (EltStride != 0) {
6446 for (unsigned i = 0; i < EltStride; ++i) {
6447 // If V[i+EltStride] is undef and this is the first round of mixing,
6448 // then it is safe to just drop this shuffle: V[i] is already in the
6449 // right place, the one element (since it's the first round) being
6450 // inserted as undef can be dropped. This isn't safe for successive
6451 // rounds because they will permute elements within both vectors.
6452 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6453 EltStride == NumElems/2)
6456 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6465 // 256-bit AVX can use the vinsertf128 instruction
6466 // to create 256-bit vectors from two other 128-bit ones.
6467 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6469 MVT ResVT = Op.getSimpleValueType();
6471 assert((ResVT.is256BitVector() ||
6472 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6474 SDValue V1 = Op.getOperand(0);
6475 SDValue V2 = Op.getOperand(1);
6476 unsigned NumElems = ResVT.getVectorNumElements();
6477 if (ResVT.is256BitVector())
6478 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6480 if (Op.getNumOperands() == 4) {
6481 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6482 ResVT.getVectorNumElements()/2);
6483 SDValue V3 = Op.getOperand(2);
6484 SDValue V4 = Op.getOperand(3);
6485 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6486 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6488 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6491 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6492 const X86Subtarget *Subtarget,
6493 SelectionDAG & DAG) {
6495 MVT ResVT = Op.getSimpleValueType();
6496 unsigned NumOfOperands = Op.getNumOperands();
6498 assert(isPowerOf2_32(NumOfOperands) &&
6499 "Unexpected number of operands in CONCAT_VECTORS");
6501 if (NumOfOperands > 2) {
6502 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6503 ResVT.getVectorNumElements()/2);
6504 SmallVector<SDValue, 2> Ops;
6505 for (unsigned i = 0; i < NumOfOperands/2; i++)
6506 Ops.push_back(Op.getOperand(i));
6507 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6509 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6510 Ops.push_back(Op.getOperand(i));
6511 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6512 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6515 SDValue V1 = Op.getOperand(0);
6516 SDValue V2 = Op.getOperand(1);
6517 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6518 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6520 if (IsZeroV1 && IsZeroV2)
6521 return getZeroVector(ResVT, Subtarget, DAG, dl);
6523 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6524 SDValue Undef = DAG.getUNDEF(ResVT);
6525 unsigned NumElems = ResVT.getVectorNumElements();
6526 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6528 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6529 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6533 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6534 // Zero the upper bits of V1
6535 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6536 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6539 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6542 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6543 const X86Subtarget *Subtarget,
6544 SelectionDAG &DAG) {
6545 MVT VT = Op.getSimpleValueType();
6546 if (VT.getVectorElementType() == MVT::i1)
6547 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6549 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6550 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6551 Op.getNumOperands() == 4)));
6553 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6554 // from two other 128-bit ones.
6556 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6557 return LowerAVXCONCAT_VECTORS(Op, DAG);
6560 //===----------------------------------------------------------------------===//
6561 // Vector shuffle lowering
6563 // This is an experimental code path for lowering vector shuffles on x86. It is
6564 // designed to handle arbitrary vector shuffles and blends, gracefully
6565 // degrading performance as necessary. It works hard to recognize idiomatic
6566 // shuffles and lower them to optimal instruction patterns without leaving
6567 // a framework that allows reasonably efficient handling of all vector shuffle
6569 //===----------------------------------------------------------------------===//
6571 /// \brief Tiny helper function to identify a no-op mask.
6573 /// This is a somewhat boring predicate function. It checks whether the mask
6574 /// array input, which is assumed to be a single-input shuffle mask of the kind
6575 /// used by the X86 shuffle instructions (not a fully general
6576 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6577 /// in-place shuffle are 'no-op's.
6578 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6579 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6580 if (Mask[i] != -1 && Mask[i] != i)
6585 /// \brief Helper function to classify a mask as a single-input mask.
6587 /// This isn't a generic single-input test because in the vector shuffle
6588 /// lowering we canonicalize single inputs to be the first input operand. This
6589 /// means we can more quickly test for a single input by only checking whether
6590 /// an input from the second operand exists. We also assume that the size of
6591 /// mask corresponds to the size of the input vectors which isn't true in the
6592 /// fully general case.
6593 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6595 if (M >= (int)Mask.size())
6600 /// \brief Test whether there are elements crossing 128-bit lanes in this
6603 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6604 /// and we routinely test for these.
6605 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6606 int LaneSize = 128 / VT.getScalarSizeInBits();
6607 int Size = Mask.size();
6608 for (int i = 0; i < Size; ++i)
6609 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6614 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6616 /// This checks a shuffle mask to see if it is performing the same
6617 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6618 /// that it is also not lane-crossing. It may however involve a blend from the
6619 /// same lane of a second vector.
6621 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6622 /// non-trivial to compute in the face of undef lanes. The representation is
6623 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6624 /// entries from both V1 and V2 inputs to the wider mask.
6626 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6627 SmallVectorImpl<int> &RepeatedMask) {
6628 int LaneSize = 128 / VT.getScalarSizeInBits();
6629 RepeatedMask.resize(LaneSize, -1);
6630 int Size = Mask.size();
6631 for (int i = 0; i < Size; ++i) {
6634 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6635 // This entry crosses lanes, so there is no way to model this shuffle.
6638 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6639 if (RepeatedMask[i % LaneSize] == -1)
6640 // This is the first non-undef entry in this slot of a 128-bit lane.
6641 RepeatedMask[i % LaneSize] =
6642 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6643 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6644 // Found a mismatch with the repeated mask.
6650 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6653 /// This is a fast way to test a shuffle mask against a fixed pattern:
6655 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6657 /// It returns true if the mask is exactly as wide as the argument list, and
6658 /// each element of the mask is either -1 (signifying undef) or the value given
6659 /// in the argument.
6660 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6661 ArrayRef<int> ExpectedMask) {
6662 if (Mask.size() != ExpectedMask.size())
6665 int Size = Mask.size();
6667 // If the values are build vectors, we can look through them to find
6668 // equivalent inputs that make the shuffles equivalent.
6669 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6670 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6672 for (int i = 0; i < Size; ++i)
6673 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6674 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6675 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6676 if (!MaskBV || !ExpectedBV ||
6677 MaskBV->getOperand(Mask[i] % Size) !=
6678 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6685 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6687 /// This helper function produces an 8-bit shuffle immediate corresponding to
6688 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6689 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6692 /// NB: We rely heavily on "undef" masks preserving the input lane.
6693 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6694 SelectionDAG &DAG) {
6695 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6696 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6697 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6698 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6699 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6702 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6703 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6704 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6705 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6706 return DAG.getConstant(Imm, DL, MVT::i8);
6709 /// \brief Compute whether each element of a shuffle is zeroable.
6711 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6712 /// Either it is an undef element in the shuffle mask, the element of the input
6713 /// referenced is undef, or the element of the input referenced is known to be
6714 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6715 /// as many lanes with this technique as possible to simplify the remaining
6717 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6718 SDValue V1, SDValue V2) {
6719 SmallBitVector Zeroable(Mask.size(), false);
6721 while (V1.getOpcode() == ISD::BITCAST)
6722 V1 = V1->getOperand(0);
6723 while (V2.getOpcode() == ISD::BITCAST)
6724 V2 = V2->getOperand(0);
6726 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6727 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6729 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6731 // Handle the easy cases.
6732 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6737 // If this is an index into a build_vector node (which has the same number
6738 // of elements), dig out the input value and use it.
6739 SDValue V = M < Size ? V1 : V2;
6740 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6743 SDValue Input = V.getOperand(M % Size);
6744 // The UNDEF opcode check really should be dead code here, but not quite
6745 // worth asserting on (it isn't invalid, just unexpected).
6746 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6753 // X86 has dedicated unpack instructions that can handle specific blend
6754 // operations: UNPCKH and UNPCKL.
6755 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6756 SDValue V1, SDValue V2,
6757 SelectionDAG &DAG) {
6758 int NumElts = VT.getVectorNumElements();
6761 bool UnpcklSwapped = true;
6762 bool UnpckhSwapped = true;
6763 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6765 for (int i = 0; i < NumElts; ++i) {
6766 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6768 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6769 int HiPos = LoPos + NumEltsInLane / 2;
6770 int LoPosSwapped = (LoPos + NumElts) % (NumElts * 2);
6771 int HiPosSwapped = (HiPos + NumElts) % (NumElts * 2);
6775 if (Mask[i] != LoPos)
6777 if (Mask[i] != HiPos)
6779 if (Mask[i] != LoPosSwapped)
6780 UnpcklSwapped = false;
6781 if (Mask[i] != HiPosSwapped)
6782 UnpckhSwapped = false;
6783 if (!Unpckl && !Unpckh && !UnpcklSwapped && !UnpckhSwapped)
6787 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6789 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6791 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6793 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6795 llvm_unreachable("Unexpected result of UNPCK mask analysis");
6799 /// \brief Try to emit a bitmask instruction for a shuffle.
6801 /// This handles cases where we can model a blend exactly as a bitmask due to
6802 /// one of the inputs being zeroable.
6803 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6804 SDValue V2, ArrayRef<int> Mask,
6805 SelectionDAG &DAG) {
6806 MVT EltVT = VT.getScalarType();
6807 int NumEltBits = EltVT.getSizeInBits();
6808 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6809 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6810 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6812 if (EltVT.isFloatingPoint()) {
6813 Zero = DAG.getBitcast(EltVT, Zero);
6814 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6816 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6817 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6819 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6822 if (Mask[i] % Size != i)
6823 return SDValue(); // Not a blend.
6825 V = Mask[i] < Size ? V1 : V2;
6826 else if (V != (Mask[i] < Size ? V1 : V2))
6827 return SDValue(); // Can only let one input through the mask.
6829 VMaskOps[i] = AllOnes;
6832 return SDValue(); // No non-zeroable elements!
6834 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6835 V = DAG.getNode(VT.isFloatingPoint()
6836 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6841 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6843 /// This is used as a fallback approach when first class blend instructions are
6844 /// unavailable. Currently it is only suitable for integer vectors, but could
6845 /// be generalized for floating point vectors if desirable.
6846 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6847 SDValue V2, ArrayRef<int> Mask,
6848 SelectionDAG &DAG) {
6849 assert(VT.isInteger() && "Only supports integer vector types!");
6850 MVT EltVT = VT.getScalarType();
6851 int NumEltBits = EltVT.getSizeInBits();
6852 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6853 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6855 SmallVector<SDValue, 16> MaskOps;
6856 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6857 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6858 return SDValue(); // Shuffled input!
6859 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6862 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6863 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6864 // We have to cast V2 around.
6865 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6866 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6867 DAG.getBitcast(MaskVT, V1Mask),
6868 DAG.getBitcast(MaskVT, V2)));
6869 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6872 /// \brief Try to emit a blend instruction for a shuffle.
6874 /// This doesn't do any checks for the availability of instructions for blending
6875 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6876 /// be matched in the backend with the type given. What it does check for is
6877 /// that the shuffle mask is in fact a blend.
6878 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6879 SDValue V2, ArrayRef<int> Mask,
6880 const X86Subtarget *Subtarget,
6881 SelectionDAG &DAG) {
6882 unsigned BlendMask = 0;
6883 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6884 if (Mask[i] >= Size) {
6885 if (Mask[i] != i + Size)
6886 return SDValue(); // Shuffled V2 input!
6887 BlendMask |= 1u << i;
6890 if (Mask[i] >= 0 && Mask[i] != i)
6891 return SDValue(); // Shuffled V1 input!
6893 switch (VT.SimpleTy) {
6898 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6899 DAG.getConstant(BlendMask, DL, MVT::i8));
6903 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6907 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6908 // that instruction.
6909 if (Subtarget->hasAVX2()) {
6910 // Scale the blend by the number of 32-bit dwords per element.
6911 int Scale = VT.getScalarSizeInBits() / 32;
6913 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6914 if (Mask[i] >= Size)
6915 for (int j = 0; j < Scale; ++j)
6916 BlendMask |= 1u << (i * Scale + j);
6918 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6919 V1 = DAG.getBitcast(BlendVT, V1);
6920 V2 = DAG.getBitcast(BlendVT, V2);
6921 return DAG.getBitcast(
6922 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6923 DAG.getConstant(BlendMask, DL, MVT::i8)));
6927 // For integer shuffles we need to expand the mask and cast the inputs to
6928 // v8i16s prior to blending.
6929 int Scale = 8 / VT.getVectorNumElements();
6931 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6932 if (Mask[i] >= Size)
6933 for (int j = 0; j < Scale; ++j)
6934 BlendMask |= 1u << (i * Scale + j);
6936 V1 = DAG.getBitcast(MVT::v8i16, V1);
6937 V2 = DAG.getBitcast(MVT::v8i16, V2);
6938 return DAG.getBitcast(VT,
6939 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6940 DAG.getConstant(BlendMask, DL, MVT::i8)));
6944 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6945 SmallVector<int, 8> RepeatedMask;
6946 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6947 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6948 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6950 for (int i = 0; i < 8; ++i)
6951 if (RepeatedMask[i] >= 16)
6952 BlendMask |= 1u << i;
6953 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6954 DAG.getConstant(BlendMask, DL, MVT::i8));
6960 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6961 "256-bit byte-blends require AVX2 support!");
6963 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6964 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6967 // Scale the blend by the number of bytes per element.
6968 int Scale = VT.getScalarSizeInBits() / 8;
6970 // This form of blend is always done on bytes. Compute the byte vector
6972 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6974 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6975 // mix of LLVM's code generator and the x86 backend. We tell the code
6976 // generator that boolean values in the elements of an x86 vector register
6977 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6978 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6979 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6980 // of the element (the remaining are ignored) and 0 in that high bit would
6981 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6982 // the LLVM model for boolean values in vector elements gets the relevant
6983 // bit set, it is set backwards and over constrained relative to x86's
6985 SmallVector<SDValue, 32> VSELECTMask;
6986 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6987 for (int j = 0; j < Scale; ++j)
6988 VSELECTMask.push_back(
6989 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6990 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6993 V1 = DAG.getBitcast(BlendVT, V1);
6994 V2 = DAG.getBitcast(BlendVT, V2);
6995 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6996 DAG.getNode(ISD::BUILD_VECTOR, DL,
6997 BlendVT, VSELECTMask),
7002 llvm_unreachable("Not a supported integer vector type!");
7006 /// \brief Try to lower as a blend of elements from two inputs followed by
7007 /// a single-input permutation.
7009 /// This matches the pattern where we can blend elements from two inputs and
7010 /// then reduce the shuffle to a single-input permutation.
7011 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7014 SelectionDAG &DAG) {
7015 // We build up the blend mask while checking whether a blend is a viable way
7016 // to reduce the shuffle.
7017 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7018 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7020 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7024 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7026 if (BlendMask[Mask[i] % Size] == -1)
7027 BlendMask[Mask[i] % Size] = Mask[i];
7028 else if (BlendMask[Mask[i] % Size] != Mask[i])
7029 return SDValue(); // Can't blend in the needed input!
7031 PermuteMask[i] = Mask[i] % Size;
7034 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7035 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7038 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7039 /// blends and permutes.
7041 /// This matches the extremely common pattern for handling combined
7042 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7043 /// operations. It will try to pick the best arrangement of shuffles and
7045 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7049 SelectionDAG &DAG) {
7050 // Shuffle the input elements into the desired positions in V1 and V2 and
7051 // blend them together.
7052 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7053 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7054 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7055 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7056 if (Mask[i] >= 0 && Mask[i] < Size) {
7057 V1Mask[i] = Mask[i];
7059 } else if (Mask[i] >= Size) {
7060 V2Mask[i] = Mask[i] - Size;
7061 BlendMask[i] = i + Size;
7064 // Try to lower with the simpler initial blend strategy unless one of the
7065 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7066 // shuffle may be able to fold with a load or other benefit. However, when
7067 // we'll have to do 2x as many shuffles in order to achieve this, blending
7068 // first is a better strategy.
7069 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7070 if (SDValue BlendPerm =
7071 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7074 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7075 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7076 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7079 /// \brief Try to lower a vector shuffle as a byte rotation.
7081 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7082 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7083 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7084 /// try to generically lower a vector shuffle through such an pattern. It
7085 /// does not check for the profitability of lowering either as PALIGNR or
7086 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7087 /// This matches shuffle vectors that look like:
7089 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7091 /// Essentially it concatenates V1 and V2, shifts right by some number of
7092 /// elements, and takes the low elements as the result. Note that while this is
7093 /// specified as a *right shift* because x86 is little-endian, it is a *left
7094 /// rotate* of the vector lanes.
7095 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7098 const X86Subtarget *Subtarget,
7099 SelectionDAG &DAG) {
7100 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7102 int NumElts = Mask.size();
7103 int NumLanes = VT.getSizeInBits() / 128;
7104 int NumLaneElts = NumElts / NumLanes;
7106 // We need to detect various ways of spelling a rotation:
7107 // [11, 12, 13, 14, 15, 0, 1, 2]
7108 // [-1, 12, 13, 14, -1, -1, 1, -1]
7109 // [-1, -1, -1, -1, -1, -1, 1, 2]
7110 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7111 // [-1, 4, 5, 6, -1, -1, 9, -1]
7112 // [-1, 4, 5, 6, -1, -1, -1, -1]
7115 for (int l = 0; l < NumElts; l += NumLaneElts) {
7116 for (int i = 0; i < NumLaneElts; ++i) {
7117 if (Mask[l + i] == -1)
7119 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7121 // Get the mod-Size index and lane correct it.
7122 int LaneIdx = (Mask[l + i] % NumElts) - l;
7123 // Make sure it was in this lane.
7124 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7127 // Determine where a rotated vector would have started.
7128 int StartIdx = i - LaneIdx;
7130 // The identity rotation isn't interesting, stop.
7133 // If we found the tail of a vector the rotation must be the missing
7134 // front. If we found the head of a vector, it must be how much of the
7136 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7139 Rotation = CandidateRotation;
7140 else if (Rotation != CandidateRotation)
7141 // The rotations don't match, so we can't match this mask.
7144 // Compute which value this mask is pointing at.
7145 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7147 // Compute which of the two target values this index should be assigned
7148 // to. This reflects whether the high elements are remaining or the low
7149 // elements are remaining.
7150 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7152 // Either set up this value if we've not encountered it before, or check
7153 // that it remains consistent.
7156 else if (TargetV != MaskV)
7157 // This may be a rotation, but it pulls from the inputs in some
7158 // unsupported interleaving.
7163 // Check that we successfully analyzed the mask, and normalize the results.
7164 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7165 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7171 // The actual rotate instruction rotates bytes, so we need to scale the
7172 // rotation based on how many bytes are in the vector lane.
7173 int Scale = 16 / NumLaneElts;
7175 // SSSE3 targets can use the palignr instruction.
7176 if (Subtarget->hasSSSE3()) {
7177 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7178 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7179 Lo = DAG.getBitcast(AlignVT, Lo);
7180 Hi = DAG.getBitcast(AlignVT, Hi);
7182 return DAG.getBitcast(
7183 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7184 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7187 assert(VT.getSizeInBits() == 128 &&
7188 "Rotate-based lowering only supports 128-bit lowering!");
7189 assert(Mask.size() <= 16 &&
7190 "Can shuffle at most 16 bytes in a 128-bit vector!");
7192 // Default SSE2 implementation
7193 int LoByteShift = 16 - Rotation * Scale;
7194 int HiByteShift = Rotation * Scale;
7196 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7197 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7198 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7200 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7201 DAG.getConstant(LoByteShift, DL, MVT::i8));
7202 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7203 DAG.getConstant(HiByteShift, DL, MVT::i8));
7204 return DAG.getBitcast(VT,
7205 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7208 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7210 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7211 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7212 /// matches elements from one of the input vectors shuffled to the left or
7213 /// right with zeroable elements 'shifted in'. It handles both the strictly
7214 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7217 /// PSHL : (little-endian) left bit shift.
7218 /// [ zz, 0, zz, 2 ]
7219 /// [ -1, 4, zz, -1 ]
7220 /// PSRL : (little-endian) right bit shift.
7222 /// [ -1, -1, 7, zz]
7223 /// PSLLDQ : (little-endian) left byte shift
7224 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7225 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7226 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7227 /// PSRLDQ : (little-endian) right byte shift
7228 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7229 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7230 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7231 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7232 SDValue V2, ArrayRef<int> Mask,
7233 SelectionDAG &DAG) {
7234 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7236 int Size = Mask.size();
7237 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7239 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7240 for (int i = 0; i < Size; i += Scale)
7241 for (int j = 0; j < Shift; ++j)
7242 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7248 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7249 for (int i = 0; i != Size; i += Scale) {
7250 unsigned Pos = Left ? i + Shift : i;
7251 unsigned Low = Left ? i : i + Shift;
7252 unsigned Len = Scale - Shift;
7253 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7254 Low + (V == V1 ? 0 : Size)))
7258 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7259 bool ByteShift = ShiftEltBits > 64;
7260 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7261 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7262 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7264 // Normalize the scale for byte shifts to still produce an i64 element
7266 Scale = ByteShift ? Scale / 2 : Scale;
7268 // We need to round trip through the appropriate type for the shift.
7269 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7270 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7271 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7272 "Illegal integer vector type");
7273 V = DAG.getBitcast(ShiftVT, V);
7275 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7276 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7277 return DAG.getBitcast(VT, V);
7280 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7281 // keep doubling the size of the integer elements up to that. We can
7282 // then shift the elements of the integer vector by whole multiples of
7283 // their width within the elements of the larger integer vector. Test each
7284 // multiple to see if we can find a match with the moved element indices
7285 // and that the shifted in elements are all zeroable.
7286 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7287 for (int Shift = 1; Shift != Scale; ++Shift)
7288 for (bool Left : {true, false})
7289 if (CheckZeros(Shift, Scale, Left))
7290 for (SDValue V : {V1, V2})
7291 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7298 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7299 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7300 SDValue V2, ArrayRef<int> Mask,
7301 SelectionDAG &DAG) {
7302 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7303 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7305 int Size = Mask.size();
7306 int HalfSize = Size / 2;
7307 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7309 // Upper half must be undefined.
7310 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7313 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7314 // Remainder of lower half result is zero and upper half is all undef.
7315 auto LowerAsEXTRQ = [&]() {
7316 // Determine the extraction length from the part of the
7317 // lower half that isn't zeroable.
7319 for (; Len >= 0; --Len)
7320 if (!Zeroable[Len - 1])
7322 assert(Len > 0 && "Zeroable shuffle mask");
7324 // Attempt to match first Len sequential elements from the lower half.
7327 for (int i = 0; i != Len; ++i) {
7331 SDValue &V = (M < Size ? V1 : V2);
7334 // All mask elements must be in the lower half.
7338 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7349 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7350 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7351 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7352 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7353 DAG.getConstant(BitLen, DL, MVT::i8),
7354 DAG.getConstant(BitIdx, DL, MVT::i8));
7357 if (SDValue ExtrQ = LowerAsEXTRQ())
7360 // INSERTQ: Extract lowest Len elements from lower half of second source and
7361 // insert over first source, starting at Idx.
7362 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7363 auto LowerAsInsertQ = [&]() {
7364 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7367 // Attempt to match first source from mask before insertion point.
7368 if (isUndefInRange(Mask, 0, Idx)) {
7370 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7372 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7378 // Extend the extraction length looking to match both the insertion of
7379 // the second source and the remaining elements of the first.
7380 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7385 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7387 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7393 // Match the remaining elements of the lower half.
7394 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7396 } else if ((!Base || (Base == V1)) &&
7397 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7399 } else if ((!Base || (Base == V2)) &&
7400 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7407 // We may not have a base (first source) - this can safely be undefined.
7409 Base = DAG.getUNDEF(VT);
7411 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7412 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7413 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7414 DAG.getConstant(BitLen, DL, MVT::i8),
7415 DAG.getConstant(BitIdx, DL, MVT::i8));
7422 if (SDValue InsertQ = LowerAsInsertQ())
7428 /// \brief Lower a vector shuffle as a zero or any extension.
7430 /// Given a specific number of elements, element bit width, and extension
7431 /// stride, produce either a zero or any extension based on the available
7432 /// features of the subtarget. The extended elements are consecutive and
7433 /// begin and can start from an offseted element index in the input; to
7434 /// avoid excess shuffling the offset must either being in the bottom lane
7435 /// or at the start of a higher lane. All extended elements must be from
7437 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7438 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7439 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7440 assert(Scale > 1 && "Need a scale to extend.");
7441 int EltBits = VT.getScalarSizeInBits();
7442 int NumElements = VT.getVectorNumElements();
7443 int NumEltsPerLane = 128 / EltBits;
7444 int OffsetLane = Offset / NumEltsPerLane;
7445 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7446 "Only 8, 16, and 32 bit elements can be extended.");
7447 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7448 assert(0 <= Offset && "Extension offset must be positive.");
7449 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7450 "Extension offset must be in the first lane or start an upper lane.");
7452 // Check that an index is in same lane as the base offset.
7453 auto SafeOffset = [&](int Idx) {
7454 return OffsetLane == (Idx / NumEltsPerLane);
7457 // Shift along an input so that the offset base moves to the first element.
7458 auto ShuffleOffset = [&](SDValue V) {
7462 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7463 for (int i = 0; i * Scale < NumElements; ++i) {
7464 int SrcIdx = i + Offset;
7465 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7467 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7470 // Found a valid zext mask! Try various lowering strategies based on the
7471 // input type and available ISA extensions.
7472 if (Subtarget->hasSSE41()) {
7473 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7474 // PUNPCK will catch this in a later shuffle match.
7475 if (Offset && Scale == 2 && VT.getSizeInBits() == 128)
7477 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7478 NumElements / Scale);
7479 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7480 return DAG.getBitcast(VT, InputV);
7483 assert(VT.getSizeInBits() == 128 && "Only 128-bit vectors can be extended.");
7485 // For any extends we can cheat for larger element sizes and use shuffle
7486 // instructions that can fold with a load and/or copy.
7487 if (AnyExt && EltBits == 32) {
7488 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7490 return DAG.getBitcast(
7491 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7492 DAG.getBitcast(MVT::v4i32, InputV),
7493 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7495 if (AnyExt && EltBits == 16 && Scale > 2) {
7496 int PSHUFDMask[4] = {Offset / 2, -1,
7497 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7498 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7499 DAG.getBitcast(MVT::v4i32, InputV),
7500 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7501 int PSHUFWMask[4] = {1, -1, -1, -1};
7502 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7503 return DAG.getBitcast(
7504 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7505 DAG.getBitcast(MVT::v8i16, InputV),
7506 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7509 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7511 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7512 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7513 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7515 int LoIdx = Offset * EltBits;
7516 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7517 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7518 DAG.getConstant(EltBits, DL, MVT::i8),
7519 DAG.getConstant(LoIdx, DL, MVT::i8)));
7521 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7522 !SafeOffset(Offset + 1))
7523 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7525 int HiIdx = (Offset + 1) * EltBits;
7526 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7527 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7528 DAG.getConstant(EltBits, DL, MVT::i8),
7529 DAG.getConstant(HiIdx, DL, MVT::i8)));
7530 return DAG.getNode(ISD::BITCAST, DL, VT,
7531 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7534 // If this would require more than 2 unpack instructions to expand, use
7535 // pshufb when available. We can only use more than 2 unpack instructions
7536 // when zero extending i8 elements which also makes it easier to use pshufb.
7537 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7538 assert(NumElements == 16 && "Unexpected byte vector width!");
7539 SDValue PSHUFBMask[16];
7540 for (int i = 0; i < 16; ++i) {
7541 int Idx = Offset + (i / Scale);
7542 PSHUFBMask[i] = DAG.getConstant(
7543 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7545 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7546 return DAG.getBitcast(VT,
7547 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7548 DAG.getNode(ISD::BUILD_VECTOR, DL,
7549 MVT::v16i8, PSHUFBMask)));
7552 // If we are extending from an offset, ensure we start on a boundary that
7553 // we can unpack from.
7554 int AlignToUnpack = Offset % (NumElements / Scale);
7555 if (AlignToUnpack) {
7556 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7557 for (int i = AlignToUnpack; i < NumElements; ++i)
7558 ShMask[i - AlignToUnpack] = i;
7559 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7560 Offset -= AlignToUnpack;
7563 // Otherwise emit a sequence of unpacks.
7565 unsigned UnpackLoHi = X86ISD::UNPCKL;
7566 if (Offset >= (NumElements / 2)) {
7567 UnpackLoHi = X86ISD::UNPCKH;
7568 Offset -= (NumElements / 2);
7571 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7572 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7573 : getZeroVector(InputVT, Subtarget, DAG, DL);
7574 InputV = DAG.getBitcast(InputVT, InputV);
7575 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7579 } while (Scale > 1);
7580 return DAG.getBitcast(VT, InputV);
7583 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7585 /// This routine will try to do everything in its power to cleverly lower
7586 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7587 /// check for the profitability of this lowering, it tries to aggressively
7588 /// match this pattern. It will use all of the micro-architectural details it
7589 /// can to emit an efficient lowering. It handles both blends with all-zero
7590 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7591 /// masking out later).
7593 /// The reason we have dedicated lowering for zext-style shuffles is that they
7594 /// are both incredibly common and often quite performance sensitive.
7595 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7596 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7597 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7598 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7600 int Bits = VT.getSizeInBits();
7601 int NumLanes = Bits / 128;
7602 int NumElements = VT.getVectorNumElements();
7603 int NumEltsPerLane = NumElements / NumLanes;
7604 assert(VT.getScalarSizeInBits() <= 32 &&
7605 "Exceeds 32-bit integer zero extension limit");
7606 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7608 // Define a helper function to check a particular ext-scale and lower to it if
7610 auto Lower = [&](int Scale) -> SDValue {
7615 for (int i = 0; i < NumElements; ++i) {
7618 continue; // Valid anywhere but doesn't tell us anything.
7619 if (i % Scale != 0) {
7620 // Each of the extended elements need to be zeroable.
7624 // We no longer are in the anyext case.
7629 // Each of the base elements needs to be consecutive indices into the
7630 // same input vector.
7631 SDValue V = M < NumElements ? V1 : V2;
7632 M = M % NumElements;
7635 Offset = M - (i / Scale);
7636 } else if (InputV != V)
7637 return SDValue(); // Flip-flopping inputs.
7639 // Offset must start in the lowest 128-bit lane or at the start of an
7641 // FIXME: Is it ever worth allowing a negative base offset?
7642 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7643 (Offset % NumEltsPerLane) == 0))
7646 // If we are offsetting, all referenced entries must come from the same
7648 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7651 if ((M % NumElements) != (Offset + (i / Scale)))
7652 return SDValue(); // Non-consecutive strided elements.
7656 // If we fail to find an input, we have a zero-shuffle which should always
7657 // have already been handled.
7658 // FIXME: Maybe handle this here in case during blending we end up with one?
7662 // If we are offsetting, don't extend if we only match a single input, we
7663 // can always do better by using a basic PSHUF or PUNPCK.
7664 if (Offset != 0 && Matches < 2)
7667 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7668 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7671 // The widest scale possible for extending is to a 64-bit integer.
7672 assert(Bits % 64 == 0 &&
7673 "The number of bits in a vector must be divisible by 64 on x86!");
7674 int NumExtElements = Bits / 64;
7676 // Each iteration, try extending the elements half as much, but into twice as
7678 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7679 assert(NumElements % NumExtElements == 0 &&
7680 "The input vector size must be divisible by the extended size.");
7681 if (SDValue V = Lower(NumElements / NumExtElements))
7685 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7689 // Returns one of the source operands if the shuffle can be reduced to a
7690 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7691 auto CanZExtLowHalf = [&]() {
7692 for (int i = NumElements / 2; i != NumElements; ++i)
7695 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7697 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7702 if (SDValue V = CanZExtLowHalf()) {
7703 V = DAG.getBitcast(MVT::v2i64, V);
7704 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7705 return DAG.getBitcast(VT, V);
7708 // No viable ext lowering found.
7712 /// \brief Try to get a scalar value for a specific element of a vector.
7714 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7715 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7716 SelectionDAG &DAG) {
7717 MVT VT = V.getSimpleValueType();
7718 MVT EltVT = VT.getVectorElementType();
7719 while (V.getOpcode() == ISD::BITCAST)
7720 V = V.getOperand(0);
7721 // If the bitcasts shift the element size, we can't extract an equivalent
7723 MVT NewVT = V.getSimpleValueType();
7724 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7727 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7728 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7729 // Ensure the scalar operand is the same size as the destination.
7730 // FIXME: Add support for scalar truncation where possible.
7731 SDValue S = V.getOperand(Idx);
7732 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7733 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7739 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7741 /// This is particularly important because the set of instructions varies
7742 /// significantly based on whether the operand is a load or not.
7743 static bool isShuffleFoldableLoad(SDValue V) {
7744 while (V.getOpcode() == ISD::BITCAST)
7745 V = V.getOperand(0);
7747 return ISD::isNON_EXTLoad(V.getNode());
7750 /// \brief Try to lower insertion of a single element into a zero vector.
7752 /// This is a common pattern that we have especially efficient patterns to lower
7753 /// across all subtarget feature sets.
7754 static SDValue lowerVectorShuffleAsElementInsertion(
7755 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7756 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7757 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7759 MVT EltVT = VT.getVectorElementType();
7761 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7762 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7764 bool IsV1Zeroable = true;
7765 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7766 if (i != V2Index && !Zeroable[i]) {
7767 IsV1Zeroable = false;
7771 // Check for a single input from a SCALAR_TO_VECTOR node.
7772 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7773 // all the smarts here sunk into that routine. However, the current
7774 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7775 // vector shuffle lowering is dead.
7776 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7778 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7779 // We need to zext the scalar if it is smaller than an i32.
7780 V2S = DAG.getBitcast(EltVT, V2S);
7781 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7782 // Using zext to expand a narrow element won't work for non-zero
7787 // Zero-extend directly to i32.
7789 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7791 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7792 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7793 EltVT == MVT::i16) {
7794 // Either not inserting from the low element of the input or the input
7795 // element size is too small to use VZEXT_MOVL to clear the high bits.
7799 if (!IsV1Zeroable) {
7800 // If V1 can't be treated as a zero vector we have fewer options to lower
7801 // this. We can't support integer vectors or non-zero targets cheaply, and
7802 // the V1 elements can't be permuted in any way.
7803 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7804 if (!VT.isFloatingPoint() || V2Index != 0)
7806 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7807 V1Mask[V2Index] = -1;
7808 if (!isNoopShuffleMask(V1Mask))
7810 // This is essentially a special case blend operation, but if we have
7811 // general purpose blend operations, they are always faster. Bail and let
7812 // the rest of the lowering handle these as blends.
7813 if (Subtarget->hasSSE41())
7816 // Otherwise, use MOVSD or MOVSS.
7817 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7818 "Only two types of floating point element types to handle!");
7819 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7823 // This lowering only works for the low element with floating point vectors.
7824 if (VT.isFloatingPoint() && V2Index != 0)
7827 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7829 V2 = DAG.getBitcast(VT, V2);
7832 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7833 // the desired position. Otherwise it is more efficient to do a vector
7834 // shift left. We know that we can do a vector shift left because all
7835 // the inputs are zero.
7836 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7837 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7838 V2Shuffle[V2Index] = 0;
7839 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7841 V2 = DAG.getBitcast(MVT::v2i64, V2);
7843 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7844 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7845 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7846 DAG.getDataLayout(), VT)));
7847 V2 = DAG.getBitcast(VT, V2);
7853 /// \brief Try to lower broadcast of a single element.
7855 /// For convenience, this code also bundles all of the subtarget feature set
7856 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7857 /// a convenient way to factor it out.
7858 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7860 const X86Subtarget *Subtarget,
7861 SelectionDAG &DAG) {
7862 if (!Subtarget->hasAVX())
7864 if (VT.isInteger() && !Subtarget->hasAVX2())
7867 // Check that the mask is a broadcast.
7868 int BroadcastIdx = -1;
7870 if (M >= 0 && BroadcastIdx == -1)
7872 else if (M >= 0 && M != BroadcastIdx)
7875 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7876 "a sorted mask where the broadcast "
7879 // Go up the chain of (vector) values to find a scalar load that we can
7880 // combine with the broadcast.
7882 switch (V.getOpcode()) {
7883 case ISD::CONCAT_VECTORS: {
7884 int OperandSize = Mask.size() / V.getNumOperands();
7885 V = V.getOperand(BroadcastIdx / OperandSize);
7886 BroadcastIdx %= OperandSize;
7890 case ISD::INSERT_SUBVECTOR: {
7891 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7892 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7896 int BeginIdx = (int)ConstantIdx->getZExtValue();
7898 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7899 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7900 BroadcastIdx -= BeginIdx;
7911 // Check if this is a broadcast of a scalar. We special case lowering
7912 // for scalars so that we can more effectively fold with loads.
7913 // First, look through bitcast: if the original value has a larger element
7914 // type than the shuffle, the broadcast element is in essence truncated.
7915 // Make that explicit to ease folding.
7916 if (V.getOpcode() == ISD::BITCAST && VT.isInteger()) {
7917 EVT EltVT = VT.getVectorElementType();
7918 SDValue V0 = V.getOperand(0);
7919 EVT V0VT = V0.getValueType();
7921 if (V0VT.isInteger() && V0VT.getVectorElementType().bitsGT(EltVT) &&
7922 ((V0.getOpcode() == ISD::BUILD_VECTOR ||
7923 (V0.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)))) {
7924 V = DAG.getNode(ISD::TRUNCATE, DL, EltVT, V0.getOperand(BroadcastIdx));
7929 // Also check the simpler case, where we can directly reuse the scalar.
7930 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7931 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7932 V = V.getOperand(BroadcastIdx);
7934 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7935 // Only AVX2 has register broadcasts.
7936 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7938 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7939 // We can't broadcast from a vector register without AVX2, and we can only
7940 // broadcast from the zero-element of a vector register.
7944 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7947 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7948 // INSERTPS when the V1 elements are already in the correct locations
7949 // because otherwise we can just always use two SHUFPS instructions which
7950 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7951 // perform INSERTPS if a single V1 element is out of place and all V2
7952 // elements are zeroable.
7953 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7955 SelectionDAG &DAG) {
7956 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7957 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7958 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7959 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7961 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7964 int V1DstIndex = -1;
7965 int V2DstIndex = -1;
7966 bool V1UsedInPlace = false;
7968 for (int i = 0; i < 4; ++i) {
7969 // Synthesize a zero mask from the zeroable elements (includes undefs).
7975 // Flag if we use any V1 inputs in place.
7977 V1UsedInPlace = true;
7981 // We can only insert a single non-zeroable element.
7982 if (V1DstIndex != -1 || V2DstIndex != -1)
7986 // V1 input out of place for insertion.
7989 // V2 input for insertion.
7994 // Don't bother if we have no (non-zeroable) element for insertion.
7995 if (V1DstIndex == -1 && V2DstIndex == -1)
7998 // Determine element insertion src/dst indices. The src index is from the
7999 // start of the inserted vector, not the start of the concatenated vector.
8000 unsigned V2SrcIndex = 0;
8001 if (V1DstIndex != -1) {
8002 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8003 // and don't use the original V2 at all.
8004 V2SrcIndex = Mask[V1DstIndex];
8005 V2DstIndex = V1DstIndex;
8008 V2SrcIndex = Mask[V2DstIndex] - 4;
8011 // If no V1 inputs are used in place, then the result is created only from
8012 // the zero mask and the V2 insertion - so remove V1 dependency.
8014 V1 = DAG.getUNDEF(MVT::v4f32);
8016 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8017 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8019 // Insert the V2 element into the desired position.
8021 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8022 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8025 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8026 /// UNPCK instruction.
8028 /// This specifically targets cases where we end up with alternating between
8029 /// the two inputs, and so can permute them into something that feeds a single
8030 /// UNPCK instruction. Note that this routine only targets integer vectors
8031 /// because for floating point vectors we have a generalized SHUFPS lowering
8032 /// strategy that handles everything that doesn't *exactly* match an unpack,
8033 /// making this clever lowering unnecessary.
8034 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8035 SDValue V1, SDValue V2,
8037 SelectionDAG &DAG) {
8038 assert(!VT.isFloatingPoint() &&
8039 "This routine only supports integer vectors.");
8040 assert(!isSingleInputShuffleMask(Mask) &&
8041 "This routine should only be used when blending two inputs.");
8042 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8044 int Size = Mask.size();
8046 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8047 return M >= 0 && M % Size < Size / 2;
8049 int NumHiInputs = std::count_if(
8050 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8052 bool UnpackLo = NumLoInputs >= NumHiInputs;
8054 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8055 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8056 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8058 for (int i = 0; i < Size; ++i) {
8062 // Each element of the unpack contains Scale elements from this mask.
8063 int UnpackIdx = i / Scale;
8065 // We only handle the case where V1 feeds the first slots of the unpack.
8066 // We rely on canonicalization to ensure this is the case.
8067 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8070 // Setup the mask for this input. The indexing is tricky as we have to
8071 // handle the unpack stride.
8072 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8073 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8077 // If we will have to shuffle both inputs to use the unpack, check whether
8078 // we can just unpack first and shuffle the result. If so, skip this unpack.
8079 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8080 !isNoopShuffleMask(V2Mask))
8083 // Shuffle the inputs into place.
8084 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8085 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8087 // Cast the inputs to the type we will use to unpack them.
8088 V1 = DAG.getBitcast(UnpackVT, V1);
8089 V2 = DAG.getBitcast(UnpackVT, V2);
8091 // Unpack the inputs and cast the result back to the desired type.
8092 return DAG.getBitcast(
8093 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8097 // We try each unpack from the largest to the smallest to try and find one
8098 // that fits this mask.
8099 int OrigNumElements = VT.getVectorNumElements();
8100 int OrigScalarSize = VT.getScalarSizeInBits();
8101 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8102 int Scale = ScalarSize / OrigScalarSize;
8103 int NumElements = OrigNumElements / Scale;
8104 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8105 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8109 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8111 if (NumLoInputs == 0 || NumHiInputs == 0) {
8112 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8113 "We have to have *some* inputs!");
8114 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8116 // FIXME: We could consider the total complexity of the permute of each
8117 // possible unpacking. Or at the least we should consider how many
8118 // half-crossings are created.
8119 // FIXME: We could consider commuting the unpacks.
8121 SmallVector<int, 32> PermMask;
8122 PermMask.assign(Size, -1);
8123 for (int i = 0; i < Size; ++i) {
8127 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8130 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8132 return DAG.getVectorShuffle(
8133 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8135 DAG.getUNDEF(VT), PermMask);
8141 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8143 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8144 /// support for floating point shuffles but not integer shuffles. These
8145 /// instructions will incur a domain crossing penalty on some chips though so
8146 /// it is better to avoid lowering through this for integer vectors where
8148 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8149 const X86Subtarget *Subtarget,
8150 SelectionDAG &DAG) {
8152 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8153 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8154 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8155 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8156 ArrayRef<int> Mask = SVOp->getMask();
8157 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8159 if (isSingleInputShuffleMask(Mask)) {
8160 // Use low duplicate instructions for masks that match their pattern.
8161 if (Subtarget->hasSSE3())
8162 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8163 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8165 // Straight shuffle of a single input vector. Simulate this by using the
8166 // single input as both of the "inputs" to this instruction..
8167 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8169 if (Subtarget->hasAVX()) {
8170 // If we have AVX, we can use VPERMILPS which will allow folding a load
8171 // into the shuffle.
8172 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8173 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8176 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8177 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8179 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8180 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8182 // If we have a single input, insert that into V1 if we can do so cheaply.
8183 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8184 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8185 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8187 // Try inverting the insertion since for v2 masks it is easy to do and we
8188 // can't reliably sort the mask one way or the other.
8189 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8190 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8191 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8192 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8196 // Try to use one of the special instruction patterns to handle two common
8197 // blend patterns if a zero-blend above didn't work.
8198 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8199 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8200 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8201 // We can either use a special instruction to load over the low double or
8202 // to move just the low double.
8204 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8206 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8208 if (Subtarget->hasSSE41())
8209 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8213 // Use dedicated unpack instructions for masks that match their pattern.
8214 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8215 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8216 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8217 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8219 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8220 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8221 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8224 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8226 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8227 /// the integer unit to minimize domain crossing penalties. However, for blends
8228 /// it falls back to the floating point shuffle operation with appropriate bit
8230 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8231 const X86Subtarget *Subtarget,
8232 SelectionDAG &DAG) {
8234 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8235 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8236 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8237 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8238 ArrayRef<int> Mask = SVOp->getMask();
8239 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8241 if (isSingleInputShuffleMask(Mask)) {
8242 // Check for being able to broadcast a single element.
8243 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8244 Mask, Subtarget, DAG))
8247 // Straight shuffle of a single input vector. For everything from SSE2
8248 // onward this has a single fast instruction with no scary immediates.
8249 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8250 V1 = DAG.getBitcast(MVT::v4i32, V1);
8251 int WidenedMask[4] = {
8252 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8253 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8254 return DAG.getBitcast(
8256 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8257 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8259 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8260 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8261 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8262 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8264 // If we have a blend of two PACKUS operations an the blend aligns with the
8265 // low and half halves, we can just merge the PACKUS operations. This is
8266 // particularly important as it lets us merge shuffles that this routine itself
8268 auto GetPackNode = [](SDValue V) {
8269 while (V.getOpcode() == ISD::BITCAST)
8270 V = V.getOperand(0);
8272 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8274 if (SDValue V1Pack = GetPackNode(V1))
8275 if (SDValue V2Pack = GetPackNode(V2))
8276 return DAG.getBitcast(MVT::v2i64,
8277 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8278 Mask[0] == 0 ? V1Pack.getOperand(0)
8279 : V1Pack.getOperand(1),
8280 Mask[1] == 2 ? V2Pack.getOperand(0)
8281 : V2Pack.getOperand(1)));
8283 // Try to use shift instructions.
8285 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8288 // When loading a scalar and then shuffling it into a vector we can often do
8289 // the insertion cheaply.
8290 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8291 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8293 // Try inverting the insertion since for v2 masks it is easy to do and we
8294 // can't reliably sort the mask one way or the other.
8295 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8296 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8297 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8300 // We have different paths for blend lowering, but they all must use the
8301 // *exact* same predicate.
8302 bool IsBlendSupported = Subtarget->hasSSE41();
8303 if (IsBlendSupported)
8304 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8308 // Use dedicated unpack instructions for masks that match their pattern.
8309 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8310 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8311 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8312 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8314 // Try to use byte rotation instructions.
8315 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8316 if (Subtarget->hasSSSE3())
8317 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8318 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8321 // If we have direct support for blends, we should lower by decomposing into
8322 // a permute. That will be faster than the domain cross.
8323 if (IsBlendSupported)
8324 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8327 // We implement this with SHUFPD which is pretty lame because it will likely
8328 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8329 // However, all the alternatives are still more cycles and newer chips don't
8330 // have this problem. It would be really nice if x86 had better shuffles here.
8331 V1 = DAG.getBitcast(MVT::v2f64, V1);
8332 V2 = DAG.getBitcast(MVT::v2f64, V2);
8333 return DAG.getBitcast(MVT::v2i64,
8334 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8337 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8339 /// This is used to disable more specialized lowerings when the shufps lowering
8340 /// will happen to be efficient.
8341 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8342 // This routine only handles 128-bit shufps.
8343 assert(Mask.size() == 4 && "Unsupported mask size!");
8345 // To lower with a single SHUFPS we need to have the low half and high half
8346 // each requiring a single input.
8347 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8349 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8355 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8357 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8358 /// It makes no assumptions about whether this is the *best* lowering, it simply
8360 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8361 ArrayRef<int> Mask, SDValue V1,
8362 SDValue V2, SelectionDAG &DAG) {
8363 SDValue LowV = V1, HighV = V2;
8364 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8367 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8369 if (NumV2Elements == 1) {
8371 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8374 // Compute the index adjacent to V2Index and in the same half by toggling
8376 int V2AdjIndex = V2Index ^ 1;
8378 if (Mask[V2AdjIndex] == -1) {
8379 // Handles all the cases where we have a single V2 element and an undef.
8380 // This will only ever happen in the high lanes because we commute the
8381 // vector otherwise.
8383 std::swap(LowV, HighV);
8384 NewMask[V2Index] -= 4;
8386 // Handle the case where the V2 element ends up adjacent to a V1 element.
8387 // To make this work, blend them together as the first step.
8388 int V1Index = V2AdjIndex;
8389 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8390 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8391 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8393 // Now proceed to reconstruct the final blend as we have the necessary
8394 // high or low half formed.
8401 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8402 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8404 } else if (NumV2Elements == 2) {
8405 if (Mask[0] < 4 && Mask[1] < 4) {
8406 // Handle the easy case where we have V1 in the low lanes and V2 in the
8410 } else if (Mask[2] < 4 && Mask[3] < 4) {
8411 // We also handle the reversed case because this utility may get called
8412 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8413 // arrange things in the right direction.
8419 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8420 // trying to place elements directly, just blend them and set up the final
8421 // shuffle to place them.
8423 // The first two blend mask elements are for V1, the second two are for
8425 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8426 Mask[2] < 4 ? Mask[2] : Mask[3],
8427 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8428 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8429 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8430 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8432 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8435 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8436 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8437 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8438 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8441 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8442 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8445 /// \brief Lower 4-lane 32-bit floating point shuffles.
8447 /// Uses instructions exclusively from the floating point unit to minimize
8448 /// domain crossing penalties, as these are sufficient to implement all v4f32
8450 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8451 const X86Subtarget *Subtarget,
8452 SelectionDAG &DAG) {
8454 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8455 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8456 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8457 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8458 ArrayRef<int> Mask = SVOp->getMask();
8459 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8462 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8464 if (NumV2Elements == 0) {
8465 // Check for being able to broadcast a single element.
8466 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8467 Mask, Subtarget, DAG))
8470 // Use even/odd duplicate instructions for masks that match their pattern.
8471 if (Subtarget->hasSSE3()) {
8472 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8473 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8474 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8475 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8478 if (Subtarget->hasAVX()) {
8479 // If we have AVX, we can use VPERMILPS which will allow folding a load
8480 // into the shuffle.
8481 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8482 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8485 // Otherwise, use a straight shuffle of a single input vector. We pass the
8486 // input vector to both operands to simulate this with a SHUFPS.
8487 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8488 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8491 // There are special ways we can lower some single-element blends. However, we
8492 // have custom ways we can lower more complex single-element blends below that
8493 // we defer to if both this and BLENDPS fail to match, so restrict this to
8494 // when the V2 input is targeting element 0 of the mask -- that is the fast
8496 if (NumV2Elements == 1 && Mask[0] >= 4)
8497 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8498 Mask, Subtarget, DAG))
8501 if (Subtarget->hasSSE41()) {
8502 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8506 // Use INSERTPS if we can complete the shuffle efficiently.
8507 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8510 if (!isSingleSHUFPSMask(Mask))
8511 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8512 DL, MVT::v4f32, V1, V2, Mask, DAG))
8516 // Use dedicated unpack instructions for masks that match their pattern.
8517 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8518 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8519 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8520 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8521 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8522 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8523 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8524 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8526 // Otherwise fall back to a SHUFPS lowering strategy.
8527 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8530 /// \brief Lower 4-lane i32 vector shuffles.
8532 /// We try to handle these with integer-domain shuffles where we can, but for
8533 /// blends we use the floating point domain blend instructions.
8534 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8535 const X86Subtarget *Subtarget,
8536 SelectionDAG &DAG) {
8538 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8539 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8540 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8541 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8542 ArrayRef<int> Mask = SVOp->getMask();
8543 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8545 // Whenever we can lower this as a zext, that instruction is strictly faster
8546 // than any alternative. It also allows us to fold memory operands into the
8547 // shuffle in many cases.
8548 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8549 Mask, Subtarget, DAG))
8553 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8555 if (NumV2Elements == 0) {
8556 // Check for being able to broadcast a single element.
8557 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8558 Mask, Subtarget, DAG))
8561 // Straight shuffle of a single input vector. For everything from SSE2
8562 // onward this has a single fast instruction with no scary immediates.
8563 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8564 // but we aren't actually going to use the UNPCK instruction because doing
8565 // so prevents folding a load into this instruction or making a copy.
8566 const int UnpackLoMask[] = {0, 0, 1, 1};
8567 const int UnpackHiMask[] = {2, 2, 3, 3};
8568 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8569 Mask = UnpackLoMask;
8570 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8571 Mask = UnpackHiMask;
8573 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8574 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8577 // Try to use shift instructions.
8579 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8582 // There are special ways we can lower some single-element blends.
8583 if (NumV2Elements == 1)
8584 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8585 Mask, Subtarget, DAG))
8588 // We have different paths for blend lowering, but they all must use the
8589 // *exact* same predicate.
8590 bool IsBlendSupported = Subtarget->hasSSE41();
8591 if (IsBlendSupported)
8592 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8596 if (SDValue Masked =
8597 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8600 // Use dedicated unpack instructions for masks that match their pattern.
8601 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8602 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8603 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8604 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8605 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8606 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8607 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8608 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8610 // Try to use byte rotation instructions.
8611 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8612 if (Subtarget->hasSSSE3())
8613 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8614 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8617 // If we have direct support for blends, we should lower by decomposing into
8618 // a permute. That will be faster than the domain cross.
8619 if (IsBlendSupported)
8620 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8623 // Try to lower by permuting the inputs into an unpack instruction.
8624 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8628 // We implement this with SHUFPS because it can blend from two vectors.
8629 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8630 // up the inputs, bypassing domain shift penalties that we would encur if we
8631 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8633 return DAG.getBitcast(
8635 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8636 DAG.getBitcast(MVT::v4f32, V2), Mask));
8639 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8640 /// shuffle lowering, and the most complex part.
8642 /// The lowering strategy is to try to form pairs of input lanes which are
8643 /// targeted at the same half of the final vector, and then use a dword shuffle
8644 /// to place them onto the right half, and finally unpack the paired lanes into
8645 /// their final position.
8647 /// The exact breakdown of how to form these dword pairs and align them on the
8648 /// correct sides is really tricky. See the comments within the function for
8649 /// more of the details.
8651 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8652 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8653 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8654 /// vector, form the analogous 128-bit 8-element Mask.
8655 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8656 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8657 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8658 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8659 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8661 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8662 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8663 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8665 SmallVector<int, 4> LoInputs;
8666 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8667 [](int M) { return M >= 0; });
8668 std::sort(LoInputs.begin(), LoInputs.end());
8669 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8670 SmallVector<int, 4> HiInputs;
8671 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8672 [](int M) { return M >= 0; });
8673 std::sort(HiInputs.begin(), HiInputs.end());
8674 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8676 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8677 int NumHToL = LoInputs.size() - NumLToL;
8679 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8680 int NumHToH = HiInputs.size() - NumLToH;
8681 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8682 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8683 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8684 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8686 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8687 // such inputs we can swap two of the dwords across the half mark and end up
8688 // with <=2 inputs to each half in each half. Once there, we can fall through
8689 // to the generic code below. For example:
8691 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8692 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8694 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8695 // and an existing 2-into-2 on the other half. In this case we may have to
8696 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8697 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8698 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8699 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8700 // half than the one we target for fixing) will be fixed when we re-enter this
8701 // path. We will also combine away any sequence of PSHUFD instructions that
8702 // result into a single instruction. Here is an example of the tricky case:
8704 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8705 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8707 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8709 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8710 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8712 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8713 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8715 // The result is fine to be handled by the generic logic.
8716 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8717 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8718 int AOffset, int BOffset) {
8719 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8720 "Must call this with A having 3 or 1 inputs from the A half.");
8721 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8722 "Must call this with B having 1 or 3 inputs from the B half.");
8723 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8724 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8726 bool ThreeAInputs = AToAInputs.size() == 3;
8728 // Compute the index of dword with only one word among the three inputs in
8729 // a half by taking the sum of the half with three inputs and subtracting
8730 // the sum of the actual three inputs. The difference is the remaining
8733 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8734 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8735 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8736 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8737 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8738 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8739 int TripleNonInputIdx =
8740 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8741 TripleDWord = TripleNonInputIdx / 2;
8743 // We use xor with one to compute the adjacent DWord to whichever one the
8745 OneInputDWord = (OneInput / 2) ^ 1;
8747 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8748 // and BToA inputs. If there is also such a problem with the BToB and AToB
8749 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8750 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8751 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8752 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8753 // Compute how many inputs will be flipped by swapping these DWords. We
8755 // to balance this to ensure we don't form a 3-1 shuffle in the other
8757 int NumFlippedAToBInputs =
8758 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8759 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8760 int NumFlippedBToBInputs =
8761 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8762 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8763 if ((NumFlippedAToBInputs == 1 &&
8764 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8765 (NumFlippedBToBInputs == 1 &&
8766 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8767 // We choose whether to fix the A half or B half based on whether that
8768 // half has zero flipped inputs. At zero, we may not be able to fix it
8769 // with that half. We also bias towards fixing the B half because that
8770 // will more commonly be the high half, and we have to bias one way.
8771 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8772 ArrayRef<int> Inputs) {
8773 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8774 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8775 PinnedIdx ^ 1) != Inputs.end();
8776 // Determine whether the free index is in the flipped dword or the
8777 // unflipped dword based on where the pinned index is. We use this bit
8778 // in an xor to conditionally select the adjacent dword.
8779 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8780 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8781 FixFreeIdx) != Inputs.end();
8782 if (IsFixIdxInput == IsFixFreeIdxInput)
8784 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8785 FixFreeIdx) != Inputs.end();
8786 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8787 "We need to be changing the number of flipped inputs!");
8788 int PSHUFHalfMask[] = {0, 1, 2, 3};
8789 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8790 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8792 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8795 if (M != -1 && M == FixIdx)
8797 else if (M != -1 && M == FixFreeIdx)
8800 if (NumFlippedBToBInputs != 0) {
8802 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8803 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8805 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8806 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8807 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8812 int PSHUFDMask[] = {0, 1, 2, 3};
8813 PSHUFDMask[ADWord] = BDWord;
8814 PSHUFDMask[BDWord] = ADWord;
8817 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8818 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8820 // Adjust the mask to match the new locations of A and B.
8822 if (M != -1 && M/2 == ADWord)
8823 M = 2 * BDWord + M % 2;
8824 else if (M != -1 && M/2 == BDWord)
8825 M = 2 * ADWord + M % 2;
8827 // Recurse back into this routine to re-compute state now that this isn't
8828 // a 3 and 1 problem.
8829 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8832 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8833 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8834 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8835 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8837 // At this point there are at most two inputs to the low and high halves from
8838 // each half. That means the inputs can always be grouped into dwords and
8839 // those dwords can then be moved to the correct half with a dword shuffle.
8840 // We use at most one low and one high word shuffle to collect these paired
8841 // inputs into dwords, and finally a dword shuffle to place them.
8842 int PSHUFLMask[4] = {-1, -1, -1, -1};
8843 int PSHUFHMask[4] = {-1, -1, -1, -1};
8844 int PSHUFDMask[4] = {-1, -1, -1, -1};
8846 // First fix the masks for all the inputs that are staying in their
8847 // original halves. This will then dictate the targets of the cross-half
8849 auto fixInPlaceInputs =
8850 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8851 MutableArrayRef<int> SourceHalfMask,
8852 MutableArrayRef<int> HalfMask, int HalfOffset) {
8853 if (InPlaceInputs.empty())
8855 if (InPlaceInputs.size() == 1) {
8856 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8857 InPlaceInputs[0] - HalfOffset;
8858 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8861 if (IncomingInputs.empty()) {
8862 // Just fix all of the in place inputs.
8863 for (int Input : InPlaceInputs) {
8864 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8865 PSHUFDMask[Input / 2] = Input / 2;
8870 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8871 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8872 InPlaceInputs[0] - HalfOffset;
8873 // Put the second input next to the first so that they are packed into
8874 // a dword. We find the adjacent index by toggling the low bit.
8875 int AdjIndex = InPlaceInputs[0] ^ 1;
8876 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8877 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8878 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8880 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8881 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8883 // Now gather the cross-half inputs and place them into a free dword of
8884 // their target half.
8885 // FIXME: This operation could almost certainly be simplified dramatically to
8886 // look more like the 3-1 fixing operation.
8887 auto moveInputsToRightHalf = [&PSHUFDMask](
8888 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8889 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8890 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8892 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8893 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8895 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8897 int LowWord = Word & ~1;
8898 int HighWord = Word | 1;
8899 return isWordClobbered(SourceHalfMask, LowWord) ||
8900 isWordClobbered(SourceHalfMask, HighWord);
8903 if (IncomingInputs.empty())
8906 if (ExistingInputs.empty()) {
8907 // Map any dwords with inputs from them into the right half.
8908 for (int Input : IncomingInputs) {
8909 // If the source half mask maps over the inputs, turn those into
8910 // swaps and use the swapped lane.
8911 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8912 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8913 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8914 Input - SourceOffset;
8915 // We have to swap the uses in our half mask in one sweep.
8916 for (int &M : HalfMask)
8917 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8919 else if (M == Input)
8920 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8922 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8923 Input - SourceOffset &&
8924 "Previous placement doesn't match!");
8926 // Note that this correctly re-maps both when we do a swap and when
8927 // we observe the other side of the swap above. We rely on that to
8928 // avoid swapping the members of the input list directly.
8929 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8932 // Map the input's dword into the correct half.
8933 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8934 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8936 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8938 "Previous placement doesn't match!");
8941 // And just directly shift any other-half mask elements to be same-half
8942 // as we will have mirrored the dword containing the element into the
8943 // same position within that half.
8944 for (int &M : HalfMask)
8945 if (M >= SourceOffset && M < SourceOffset + 4) {
8946 M = M - SourceOffset + DestOffset;
8947 assert(M >= 0 && "This should never wrap below zero!");
8952 // Ensure we have the input in a viable dword of its current half. This
8953 // is particularly tricky because the original position may be clobbered
8954 // by inputs being moved and *staying* in that half.
8955 if (IncomingInputs.size() == 1) {
8956 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8957 int InputFixed = std::find(std::begin(SourceHalfMask),
8958 std::end(SourceHalfMask), -1) -
8959 std::begin(SourceHalfMask) + SourceOffset;
8960 SourceHalfMask[InputFixed - SourceOffset] =
8961 IncomingInputs[0] - SourceOffset;
8962 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8964 IncomingInputs[0] = InputFixed;
8966 } else if (IncomingInputs.size() == 2) {
8967 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8968 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8969 // We have two non-adjacent or clobbered inputs we need to extract from
8970 // the source half. To do this, we need to map them into some adjacent
8971 // dword slot in the source mask.
8972 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8973 IncomingInputs[1] - SourceOffset};
8975 // If there is a free slot in the source half mask adjacent to one of
8976 // the inputs, place the other input in it. We use (Index XOR 1) to
8977 // compute an adjacent index.
8978 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8979 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8980 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8981 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8982 InputsFixed[1] = InputsFixed[0] ^ 1;
8983 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8984 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8985 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8986 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8987 InputsFixed[0] = InputsFixed[1] ^ 1;
8988 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8989 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8990 // The two inputs are in the same DWord but it is clobbered and the
8991 // adjacent DWord isn't used at all. Move both inputs to the free
8993 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8994 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8995 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8996 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8998 // The only way we hit this point is if there is no clobbering
8999 // (because there are no off-half inputs to this half) and there is no
9000 // free slot adjacent to one of the inputs. In this case, we have to
9001 // swap an input with a non-input.
9002 for (int i = 0; i < 4; ++i)
9003 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9004 "We can't handle any clobbers here!");
9005 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9006 "Cannot have adjacent inputs here!");
9008 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9009 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9011 // We also have to update the final source mask in this case because
9012 // it may need to undo the above swap.
9013 for (int &M : FinalSourceHalfMask)
9014 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9015 M = InputsFixed[1] + SourceOffset;
9016 else if (M == InputsFixed[1] + SourceOffset)
9017 M = (InputsFixed[0] ^ 1) + SourceOffset;
9019 InputsFixed[1] = InputsFixed[0] ^ 1;
9022 // Point everything at the fixed inputs.
9023 for (int &M : HalfMask)
9024 if (M == IncomingInputs[0])
9025 M = InputsFixed[0] + SourceOffset;
9026 else if (M == IncomingInputs[1])
9027 M = InputsFixed[1] + SourceOffset;
9029 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9030 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9033 llvm_unreachable("Unhandled input size!");
9036 // Now hoist the DWord down to the right half.
9037 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9038 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9039 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9040 for (int &M : HalfMask)
9041 for (int Input : IncomingInputs)
9043 M = FreeDWord * 2 + Input % 2;
9045 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9046 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9047 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9048 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9050 // Now enact all the shuffles we've computed to move the inputs into their
9052 if (!isNoopShuffleMask(PSHUFLMask))
9053 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9054 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9055 if (!isNoopShuffleMask(PSHUFHMask))
9056 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9057 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9058 if (!isNoopShuffleMask(PSHUFDMask))
9061 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9062 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9064 // At this point, each half should contain all its inputs, and we can then
9065 // just shuffle them into their final position.
9066 assert(std::count_if(LoMask.begin(), LoMask.end(),
9067 [](int M) { return M >= 4; }) == 0 &&
9068 "Failed to lift all the high half inputs to the low mask!");
9069 assert(std::count_if(HiMask.begin(), HiMask.end(),
9070 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9071 "Failed to lift all the low half inputs to the high mask!");
9073 // Do a half shuffle for the low mask.
9074 if (!isNoopShuffleMask(LoMask))
9075 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9076 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9078 // Do a half shuffle with the high mask after shifting its values down.
9079 for (int &M : HiMask)
9082 if (!isNoopShuffleMask(HiMask))
9083 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9084 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9089 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9090 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9091 SDValue V2, ArrayRef<int> Mask,
9092 SelectionDAG &DAG, bool &V1InUse,
9094 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9100 int Size = Mask.size();
9101 int Scale = 16 / Size;
9102 for (int i = 0; i < 16; ++i) {
9103 if (Mask[i / Scale] == -1) {
9104 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9106 const int ZeroMask = 0x80;
9107 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9109 int V2Idx = Mask[i / Scale] < Size
9111 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9112 if (Zeroable[i / Scale])
9113 V1Idx = V2Idx = ZeroMask;
9114 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9115 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9116 V1InUse |= (ZeroMask != V1Idx);
9117 V2InUse |= (ZeroMask != V2Idx);
9122 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9123 DAG.getBitcast(MVT::v16i8, V1),
9124 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9126 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9127 DAG.getBitcast(MVT::v16i8, V2),
9128 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9130 // If we need shuffled inputs from both, blend the two.
9132 if (V1InUse && V2InUse)
9133 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9135 V = V1InUse ? V1 : V2;
9137 // Cast the result back to the correct type.
9138 return DAG.getBitcast(VT, V);
9141 /// \brief Generic lowering of 8-lane i16 shuffles.
9143 /// This handles both single-input shuffles and combined shuffle/blends with
9144 /// two inputs. The single input shuffles are immediately delegated to
9145 /// a dedicated lowering routine.
9147 /// The blends are lowered in one of three fundamental ways. If there are few
9148 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9149 /// of the input is significantly cheaper when lowered as an interleaving of
9150 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9151 /// halves of the inputs separately (making them have relatively few inputs)
9152 /// and then concatenate them.
9153 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9154 const X86Subtarget *Subtarget,
9155 SelectionDAG &DAG) {
9157 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9158 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9159 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9160 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9161 ArrayRef<int> OrigMask = SVOp->getMask();
9162 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9163 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9164 MutableArrayRef<int> Mask(MaskStorage);
9166 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9168 // Whenever we can lower this as a zext, that instruction is strictly faster
9169 // than any alternative.
9170 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9171 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9174 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9176 auto isV2 = [](int M) { return M >= 8; };
9178 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9180 if (NumV2Inputs == 0) {
9181 // Check for being able to broadcast a single element.
9182 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9183 Mask, Subtarget, DAG))
9186 // Try to use shift instructions.
9188 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9191 // Use dedicated unpack instructions for masks that match their pattern.
9192 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
9193 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
9194 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
9195 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
9197 // Try to use byte rotation instructions.
9198 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9199 Mask, Subtarget, DAG))
9202 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9206 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9207 "All single-input shuffles should be canonicalized to be V1-input "
9210 // Try to use shift instructions.
9212 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9215 // See if we can use SSE4A Extraction / Insertion.
9216 if (Subtarget->hasSSE4A())
9217 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9220 // There are special ways we can lower some single-element blends.
9221 if (NumV2Inputs == 1)
9222 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9223 Mask, Subtarget, DAG))
9226 // We have different paths for blend lowering, but they all must use the
9227 // *exact* same predicate.
9228 bool IsBlendSupported = Subtarget->hasSSE41();
9229 if (IsBlendSupported)
9230 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9234 if (SDValue Masked =
9235 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9238 // Use dedicated unpack instructions for masks that match their pattern.
9239 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
9240 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9241 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
9242 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9244 // Try to use byte rotation instructions.
9245 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9246 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9249 if (SDValue BitBlend =
9250 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9253 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9257 // If we can't directly blend but can use PSHUFB, that will be better as it
9258 // can both shuffle and set up the inefficient blend.
9259 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9260 bool V1InUse, V2InUse;
9261 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9265 // We can always bit-blend if we have to so the fallback strategy is to
9266 // decompose into single-input permutes and blends.
9267 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9271 /// \brief Check whether a compaction lowering can be done by dropping even
9272 /// elements and compute how many times even elements must be dropped.
9274 /// This handles shuffles which take every Nth element where N is a power of
9275 /// two. Example shuffle masks:
9277 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9278 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9279 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9280 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9281 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9282 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9284 /// Any of these lanes can of course be undef.
9286 /// This routine only supports N <= 3.
9287 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9290 /// \returns N above, or the number of times even elements must be dropped if
9291 /// there is such a number. Otherwise returns zero.
9292 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9293 // Figure out whether we're looping over two inputs or just one.
9294 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9296 // The modulus for the shuffle vector entries is based on whether this is
9297 // a single input or not.
9298 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9299 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9300 "We should only be called with masks with a power-of-2 size!");
9302 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9304 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9305 // and 2^3 simultaneously. This is because we may have ambiguity with
9306 // partially undef inputs.
9307 bool ViableForN[3] = {true, true, true};
9309 for (int i = 0, e = Mask.size(); i < e; ++i) {
9310 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9315 bool IsAnyViable = false;
9316 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9317 if (ViableForN[j]) {
9320 // The shuffle mask must be equal to (i * 2^N) % M.
9321 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9324 ViableForN[j] = false;
9326 // Early exit if we exhaust the possible powers of two.
9331 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9335 // Return 0 as there is no viable power of two.
9339 /// \brief Generic lowering of v16i8 shuffles.
9341 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9342 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9343 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9344 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9346 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9347 const X86Subtarget *Subtarget,
9348 SelectionDAG &DAG) {
9350 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9351 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9352 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9353 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9354 ArrayRef<int> Mask = SVOp->getMask();
9355 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9357 // Try to use shift instructions.
9359 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9362 // Try to use byte rotation instructions.
9363 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9364 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9367 // Try to use a zext lowering.
9368 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9369 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9372 // See if we can use SSE4A Extraction / Insertion.
9373 if (Subtarget->hasSSE4A())
9374 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9378 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9380 // For single-input shuffles, there are some nicer lowering tricks we can use.
9381 if (NumV2Elements == 0) {
9382 // Check for being able to broadcast a single element.
9383 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9384 Mask, Subtarget, DAG))
9387 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9388 // Notably, this handles splat and partial-splat shuffles more efficiently.
9389 // However, it only makes sense if the pre-duplication shuffle simplifies
9390 // things significantly. Currently, this means we need to be able to
9391 // express the pre-duplication shuffle as an i16 shuffle.
9393 // FIXME: We should check for other patterns which can be widened into an
9394 // i16 shuffle as well.
9395 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9396 for (int i = 0; i < 16; i += 2)
9397 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9402 auto tryToWidenViaDuplication = [&]() -> SDValue {
9403 if (!canWidenViaDuplication(Mask))
9405 SmallVector<int, 4> LoInputs;
9406 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9407 [](int M) { return M >= 0 && M < 8; });
9408 std::sort(LoInputs.begin(), LoInputs.end());
9409 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9411 SmallVector<int, 4> HiInputs;
9412 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9413 [](int M) { return M >= 8; });
9414 std::sort(HiInputs.begin(), HiInputs.end());
9415 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9418 bool TargetLo = LoInputs.size() >= HiInputs.size();
9419 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9420 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9422 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9423 SmallDenseMap<int, int, 8> LaneMap;
9424 for (int I : InPlaceInputs) {
9425 PreDupI16Shuffle[I/2] = I/2;
9428 int j = TargetLo ? 0 : 4, je = j + 4;
9429 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9430 // Check if j is already a shuffle of this input. This happens when
9431 // there are two adjacent bytes after we move the low one.
9432 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9433 // If we haven't yet mapped the input, search for a slot into which
9435 while (j < je && PreDupI16Shuffle[j] != -1)
9439 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9442 // Map this input with the i16 shuffle.
9443 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9446 // Update the lane map based on the mapping we ended up with.
9447 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9449 V1 = DAG.getBitcast(
9451 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9452 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9454 // Unpack the bytes to form the i16s that will be shuffled into place.
9455 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9456 MVT::v16i8, V1, V1);
9458 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9459 for (int i = 0; i < 16; ++i)
9460 if (Mask[i] != -1) {
9461 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9462 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9463 if (PostDupI16Shuffle[i / 2] == -1)
9464 PostDupI16Shuffle[i / 2] = MappedMask;
9466 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9467 "Conflicting entrties in the original shuffle!");
9469 return DAG.getBitcast(
9471 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9472 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9474 if (SDValue V = tryToWidenViaDuplication())
9478 if (SDValue Masked =
9479 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9482 // Use dedicated unpack instructions for masks that match their pattern.
9483 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9484 0, 16, 1, 17, 2, 18, 3, 19,
9486 4, 20, 5, 21, 6, 22, 7, 23}))
9487 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9488 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9489 8, 24, 9, 25, 10, 26, 11, 27,
9491 12, 28, 13, 29, 14, 30, 15, 31}))
9492 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9494 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9495 // with PSHUFB. It is important to do this before we attempt to generate any
9496 // blends but after all of the single-input lowerings. If the single input
9497 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9498 // want to preserve that and we can DAG combine any longer sequences into
9499 // a PSHUFB in the end. But once we start blending from multiple inputs,
9500 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9501 // and there are *very* few patterns that would actually be faster than the
9502 // PSHUFB approach because of its ability to zero lanes.
9504 // FIXME: The only exceptions to the above are blends which are exact
9505 // interleavings with direct instructions supporting them. We currently don't
9506 // handle those well here.
9507 if (Subtarget->hasSSSE3()) {
9508 bool V1InUse = false;
9509 bool V2InUse = false;
9511 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9512 DAG, V1InUse, V2InUse);
9514 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9515 // do so. This avoids using them to handle blends-with-zero which is
9516 // important as a single pshufb is significantly faster for that.
9517 if (V1InUse && V2InUse) {
9518 if (Subtarget->hasSSE41())
9519 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9520 Mask, Subtarget, DAG))
9523 // We can use an unpack to do the blending rather than an or in some
9524 // cases. Even though the or may be (very minorly) more efficient, we
9525 // preference this lowering because there are common cases where part of
9526 // the complexity of the shuffles goes away when we do the final blend as
9528 // FIXME: It might be worth trying to detect if the unpack-feeding
9529 // shuffles will both be pshufb, in which case we shouldn't bother with
9531 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9532 DL, MVT::v16i8, V1, V2, Mask, DAG))
9539 // There are special ways we can lower some single-element blends.
9540 if (NumV2Elements == 1)
9541 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9542 Mask, Subtarget, DAG))
9545 if (SDValue BitBlend =
9546 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9549 // Check whether a compaction lowering can be done. This handles shuffles
9550 // which take every Nth element for some even N. See the helper function for
9553 // We special case these as they can be particularly efficiently handled with
9554 // the PACKUSB instruction on x86 and they show up in common patterns of
9555 // rearranging bytes to truncate wide elements.
9556 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9557 // NumEvenDrops is the power of two stride of the elements. Another way of
9558 // thinking about it is that we need to drop the even elements this many
9559 // times to get the original input.
9560 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9562 // First we need to zero all the dropped bytes.
9563 assert(NumEvenDrops <= 3 &&
9564 "No support for dropping even elements more than 3 times.");
9565 // We use the mask type to pick which bytes are preserved based on how many
9566 // elements are dropped.
9567 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9568 SDValue ByteClearMask = DAG.getBitcast(
9569 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9570 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9572 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9574 // Now pack things back together.
9575 V1 = DAG.getBitcast(MVT::v8i16, V1);
9576 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9577 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9578 for (int i = 1; i < NumEvenDrops; ++i) {
9579 Result = DAG.getBitcast(MVT::v8i16, Result);
9580 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9586 // Handle multi-input cases by blending single-input shuffles.
9587 if (NumV2Elements > 0)
9588 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9591 // The fallback path for single-input shuffles widens this into two v8i16
9592 // vectors with unpacks, shuffles those, and then pulls them back together
9596 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9597 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9598 for (int i = 0; i < 16; ++i)
9600 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9602 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9604 SDValue VLoHalf, VHiHalf;
9605 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9606 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9608 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9609 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9610 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9611 [](int M) { return M >= 0 && M % 2 == 1; })) {
9612 // Use a mask to drop the high bytes.
9613 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9614 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9615 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9617 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9618 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9620 // Squash the masks to point directly into VLoHalf.
9621 for (int &M : LoBlendMask)
9624 for (int &M : HiBlendMask)
9628 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9629 // VHiHalf so that we can blend them as i16s.
9630 VLoHalf = DAG.getBitcast(
9631 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9632 VHiHalf = DAG.getBitcast(
9633 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9636 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9637 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9639 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9642 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9644 /// This routine breaks down the specific type of 128-bit shuffle and
9645 /// dispatches to the lowering routines accordingly.
9646 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9647 MVT VT, const X86Subtarget *Subtarget,
9648 SelectionDAG &DAG) {
9649 switch (VT.SimpleTy) {
9651 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9653 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9655 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9657 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9659 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9661 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9664 llvm_unreachable("Unimplemented!");
9668 /// \brief Helper function to test whether a shuffle mask could be
9669 /// simplified by widening the elements being shuffled.
9671 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9672 /// leaves it in an unspecified state.
9674 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9675 /// shuffle masks. The latter have the special property of a '-2' representing
9676 /// a zero-ed lane of a vector.
9677 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9678 SmallVectorImpl<int> &WidenedMask) {
9679 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9680 // If both elements are undef, its trivial.
9681 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9682 WidenedMask.push_back(SM_SentinelUndef);
9686 // Check for an undef mask and a mask value properly aligned to fit with
9687 // a pair of values. If we find such a case, use the non-undef mask's value.
9688 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9689 WidenedMask.push_back(Mask[i + 1] / 2);
9692 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9693 WidenedMask.push_back(Mask[i] / 2);
9697 // When zeroing, we need to spread the zeroing across both lanes to widen.
9698 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9699 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9700 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9701 WidenedMask.push_back(SM_SentinelZero);
9707 // Finally check if the two mask values are adjacent and aligned with
9709 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9710 WidenedMask.push_back(Mask[i] / 2);
9714 // Otherwise we can't safely widen the elements used in this shuffle.
9717 assert(WidenedMask.size() == Mask.size() / 2 &&
9718 "Incorrect size of mask after widening the elements!");
9723 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9725 /// This routine just extracts two subvectors, shuffles them independently, and
9726 /// then concatenates them back together. This should work effectively with all
9727 /// AVX vector shuffle types.
9728 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9729 SDValue V2, ArrayRef<int> Mask,
9730 SelectionDAG &DAG) {
9731 assert(VT.getSizeInBits() >= 256 &&
9732 "Only for 256-bit or wider vector shuffles!");
9733 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9734 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9736 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9737 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9739 int NumElements = VT.getVectorNumElements();
9740 int SplitNumElements = NumElements / 2;
9741 MVT ScalarVT = VT.getScalarType();
9742 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9744 // Rather than splitting build-vectors, just build two narrower build
9745 // vectors. This helps shuffling with splats and zeros.
9746 auto SplitVector = [&](SDValue V) {
9747 while (V.getOpcode() == ISD::BITCAST)
9748 V = V->getOperand(0);
9750 MVT OrigVT = V.getSimpleValueType();
9751 int OrigNumElements = OrigVT.getVectorNumElements();
9752 int OrigSplitNumElements = OrigNumElements / 2;
9753 MVT OrigScalarVT = OrigVT.getScalarType();
9754 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9758 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9760 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9761 DAG.getIntPtrConstant(0, DL));
9762 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9763 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9766 SmallVector<SDValue, 16> LoOps, HiOps;
9767 for (int i = 0; i < OrigSplitNumElements; ++i) {
9768 LoOps.push_back(BV->getOperand(i));
9769 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9771 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9772 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9774 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9775 DAG.getBitcast(SplitVT, HiV));
9778 SDValue LoV1, HiV1, LoV2, HiV2;
9779 std::tie(LoV1, HiV1) = SplitVector(V1);
9780 std::tie(LoV2, HiV2) = SplitVector(V2);
9782 // Now create two 4-way blends of these half-width vectors.
9783 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9784 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9785 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9786 for (int i = 0; i < SplitNumElements; ++i) {
9787 int M = HalfMask[i];
9788 if (M >= NumElements) {
9789 if (M >= NumElements + SplitNumElements)
9793 V2BlendMask.push_back(M - NumElements);
9794 V1BlendMask.push_back(-1);
9795 BlendMask.push_back(SplitNumElements + i);
9796 } else if (M >= 0) {
9797 if (M >= SplitNumElements)
9801 V2BlendMask.push_back(-1);
9802 V1BlendMask.push_back(M);
9803 BlendMask.push_back(i);
9805 V2BlendMask.push_back(-1);
9806 V1BlendMask.push_back(-1);
9807 BlendMask.push_back(-1);
9811 // Because the lowering happens after all combining takes place, we need to
9812 // manually combine these blend masks as much as possible so that we create
9813 // a minimal number of high-level vector shuffle nodes.
9815 // First try just blending the halves of V1 or V2.
9816 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9817 return DAG.getUNDEF(SplitVT);
9818 if (!UseLoV2 && !UseHiV2)
9819 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9820 if (!UseLoV1 && !UseHiV1)
9821 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9823 SDValue V1Blend, V2Blend;
9824 if (UseLoV1 && UseHiV1) {
9826 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9828 // We only use half of V1 so map the usage down into the final blend mask.
9829 V1Blend = UseLoV1 ? LoV1 : HiV1;
9830 for (int i = 0; i < SplitNumElements; ++i)
9831 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9832 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9834 if (UseLoV2 && UseHiV2) {
9836 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9838 // We only use half of V2 so map the usage down into the final blend mask.
9839 V2Blend = UseLoV2 ? LoV2 : HiV2;
9840 for (int i = 0; i < SplitNumElements; ++i)
9841 if (BlendMask[i] >= SplitNumElements)
9842 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9844 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9846 SDValue Lo = HalfBlend(LoMask);
9847 SDValue Hi = HalfBlend(HiMask);
9848 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9851 /// \brief Either split a vector in halves or decompose the shuffles and the
9854 /// This is provided as a good fallback for many lowerings of non-single-input
9855 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9856 /// between splitting the shuffle into 128-bit components and stitching those
9857 /// back together vs. extracting the single-input shuffles and blending those
9859 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9860 SDValue V2, ArrayRef<int> Mask,
9861 SelectionDAG &DAG) {
9862 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9863 "lower single-input shuffles as it "
9864 "could then recurse on itself.");
9865 int Size = Mask.size();
9867 // If this can be modeled as a broadcast of two elements followed by a blend,
9868 // prefer that lowering. This is especially important because broadcasts can
9869 // often fold with memory operands.
9870 auto DoBothBroadcast = [&] {
9871 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9874 if (V2BroadcastIdx == -1)
9875 V2BroadcastIdx = M - Size;
9876 else if (M - Size != V2BroadcastIdx)
9878 } else if (M >= 0) {
9879 if (V1BroadcastIdx == -1)
9881 else if (M != V1BroadcastIdx)
9886 if (DoBothBroadcast())
9887 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9890 // If the inputs all stem from a single 128-bit lane of each input, then we
9891 // split them rather than blending because the split will decompose to
9892 // unusually few instructions.
9893 int LaneCount = VT.getSizeInBits() / 128;
9894 int LaneSize = Size / LaneCount;
9895 SmallBitVector LaneInputs[2];
9896 LaneInputs[0].resize(LaneCount, false);
9897 LaneInputs[1].resize(LaneCount, false);
9898 for (int i = 0; i < Size; ++i)
9900 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9901 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9902 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9904 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9905 // that the decomposed single-input shuffles don't end up here.
9906 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9909 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9910 /// a permutation and blend of those lanes.
9912 /// This essentially blends the out-of-lane inputs to each lane into the lane
9913 /// from a permuted copy of the vector. This lowering strategy results in four
9914 /// instructions in the worst case for a single-input cross lane shuffle which
9915 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9916 /// of. Special cases for each particular shuffle pattern should be handled
9917 /// prior to trying this lowering.
9918 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9919 SDValue V1, SDValue V2,
9921 SelectionDAG &DAG) {
9922 // FIXME: This should probably be generalized for 512-bit vectors as well.
9923 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9924 int LaneSize = Mask.size() / 2;
9926 // If there are only inputs from one 128-bit lane, splitting will in fact be
9927 // less expensive. The flags track whether the given lane contains an element
9928 // that crosses to another lane.
9929 bool LaneCrossing[2] = {false, false};
9930 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9931 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9932 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9933 if (!LaneCrossing[0] || !LaneCrossing[1])
9934 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9936 if (isSingleInputShuffleMask(Mask)) {
9937 SmallVector<int, 32> FlippedBlendMask;
9938 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9939 FlippedBlendMask.push_back(
9940 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9942 : Mask[i] % LaneSize +
9943 (i / LaneSize) * LaneSize + Size));
9945 // Flip the vector, and blend the results which should now be in-lane. The
9946 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9947 // 5 for the high source. The value 3 selects the high half of source 2 and
9948 // the value 2 selects the low half of source 2. We only use source 2 to
9949 // allow folding it into a memory operand.
9950 unsigned PERMMask = 3 | 2 << 4;
9951 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9952 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9953 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9956 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9957 // will be handled by the above logic and a blend of the results, much like
9958 // other patterns in AVX.
9959 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9962 /// \brief Handle lowering 2-lane 128-bit shuffles.
9963 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9964 SDValue V2, ArrayRef<int> Mask,
9965 const X86Subtarget *Subtarget,
9966 SelectionDAG &DAG) {
9967 // TODO: If minimizing size and one of the inputs is a zero vector and the
9968 // the zero vector has only one use, we could use a VPERM2X128 to save the
9969 // instruction bytes needed to explicitly generate the zero vector.
9971 // Blends are faster and handle all the non-lane-crossing cases.
9972 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9976 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9977 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9979 // If either input operand is a zero vector, use VPERM2X128 because its mask
9980 // allows us to replace the zero input with an implicit zero.
9981 if (!IsV1Zero && !IsV2Zero) {
9982 // Check for patterns which can be matched with a single insert of a 128-bit
9984 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9985 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9986 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9987 VT.getVectorNumElements() / 2);
9988 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9989 DAG.getIntPtrConstant(0, DL));
9990 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9991 OnlyUsesV1 ? V1 : V2,
9992 DAG.getIntPtrConstant(0, DL));
9993 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9997 // Otherwise form a 128-bit permutation. After accounting for undefs,
9998 // convert the 64-bit shuffle mask selection values into 128-bit
9999 // selection bits by dividing the indexes by 2 and shifting into positions
10000 // defined by a vperm2*128 instruction's immediate control byte.
10002 // The immediate permute control byte looks like this:
10003 // [1:0] - select 128 bits from sources for low half of destination
10005 // [3] - zero low half of destination
10006 // [5:4] - select 128 bits from sources for high half of destination
10008 // [7] - zero high half of destination
10010 int MaskLO = Mask[0];
10011 if (MaskLO == SM_SentinelUndef)
10012 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10014 int MaskHI = Mask[2];
10015 if (MaskHI == SM_SentinelUndef)
10016 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10018 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10020 // If either input is a zero vector, replace it with an undef input.
10021 // Shuffle mask values < 4 are selecting elements of V1.
10022 // Shuffle mask values >= 4 are selecting elements of V2.
10023 // Adjust each half of the permute mask by clearing the half that was
10024 // selecting the zero vector and setting the zero mask bit.
10026 V1 = DAG.getUNDEF(VT);
10028 PermMask = (PermMask & 0xf0) | 0x08;
10030 PermMask = (PermMask & 0x0f) | 0x80;
10033 V2 = DAG.getUNDEF(VT);
10035 PermMask = (PermMask & 0xf0) | 0x08;
10037 PermMask = (PermMask & 0x0f) | 0x80;
10040 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10041 DAG.getConstant(PermMask, DL, MVT::i8));
10044 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10045 /// shuffling each lane.
10047 /// This will only succeed when the result of fixing the 128-bit lanes results
10048 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10049 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10050 /// the lane crosses early and then use simpler shuffles within each lane.
10052 /// FIXME: It might be worthwhile at some point to support this without
10053 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10054 /// in x86 only floating point has interesting non-repeating shuffles, and even
10055 /// those are still *marginally* more expensive.
10056 static SDValue lowerVectorShuffleByMerging128BitLanes(
10057 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10058 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10059 assert(!isSingleInputShuffleMask(Mask) &&
10060 "This is only useful with multiple inputs.");
10062 int Size = Mask.size();
10063 int LaneSize = 128 / VT.getScalarSizeInBits();
10064 int NumLanes = Size / LaneSize;
10065 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10067 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10068 // check whether the in-128-bit lane shuffles share a repeating pattern.
10069 SmallVector<int, 4> Lanes;
10070 Lanes.resize(NumLanes, -1);
10071 SmallVector<int, 4> InLaneMask;
10072 InLaneMask.resize(LaneSize, -1);
10073 for (int i = 0; i < Size; ++i) {
10077 int j = i / LaneSize;
10079 if (Lanes[j] < 0) {
10080 // First entry we've seen for this lane.
10081 Lanes[j] = Mask[i] / LaneSize;
10082 } else if (Lanes[j] != Mask[i] / LaneSize) {
10083 // This doesn't match the lane selected previously!
10087 // Check that within each lane we have a consistent shuffle mask.
10088 int k = i % LaneSize;
10089 if (InLaneMask[k] < 0) {
10090 InLaneMask[k] = Mask[i] % LaneSize;
10091 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10092 // This doesn't fit a repeating in-lane mask.
10097 // First shuffle the lanes into place.
10098 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10099 VT.getSizeInBits() / 64);
10100 SmallVector<int, 8> LaneMask;
10101 LaneMask.resize(NumLanes * 2, -1);
10102 for (int i = 0; i < NumLanes; ++i)
10103 if (Lanes[i] >= 0) {
10104 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10105 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10108 V1 = DAG.getBitcast(LaneVT, V1);
10109 V2 = DAG.getBitcast(LaneVT, V2);
10110 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10112 // Cast it back to the type we actually want.
10113 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10115 // Now do a simple shuffle that isn't lane crossing.
10116 SmallVector<int, 8> NewMask;
10117 NewMask.resize(Size, -1);
10118 for (int i = 0; i < Size; ++i)
10120 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10121 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10122 "Must not introduce lane crosses at this point!");
10124 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10127 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10130 /// This returns true if the elements from a particular input are already in the
10131 /// slot required by the given mask and require no permutation.
10132 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10133 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10134 int Size = Mask.size();
10135 for (int i = 0; i < Size; ++i)
10136 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10142 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10143 ArrayRef<int> Mask, SDValue V1,
10144 SDValue V2, SelectionDAG &DAG) {
10146 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10147 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10148 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10149 int NumElts = VT.getVectorNumElements();
10150 bool ShufpdMask = true;
10151 bool CommutableMask = true;
10152 unsigned Immediate = 0;
10153 for (int i = 0; i < NumElts; ++i) {
10156 int Val = (i & 6) + NumElts * (i & 1);
10157 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10158 if (Mask[i] < Val || Mask[i] > Val + 1)
10159 ShufpdMask = false;
10160 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10161 CommutableMask = false;
10162 Immediate |= (Mask[i] % 2) << i;
10165 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10166 DAG.getConstant(Immediate, DL, MVT::i8));
10167 if (CommutableMask)
10168 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10169 DAG.getConstant(Immediate, DL, MVT::i8));
10173 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10175 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10176 /// isn't available.
10177 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10178 const X86Subtarget *Subtarget,
10179 SelectionDAG &DAG) {
10181 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10182 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10183 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10184 ArrayRef<int> Mask = SVOp->getMask();
10185 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10187 SmallVector<int, 4> WidenedMask;
10188 if (canWidenShuffleElements(Mask, WidenedMask))
10189 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10192 if (isSingleInputShuffleMask(Mask)) {
10193 // Check for being able to broadcast a single element.
10194 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10195 Mask, Subtarget, DAG))
10198 // Use low duplicate instructions for masks that match their pattern.
10199 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10200 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10202 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10203 // Non-half-crossing single input shuffles can be lowerid with an
10204 // interleaved permutation.
10205 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10206 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10207 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10208 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10211 // With AVX2 we have direct support for this permutation.
10212 if (Subtarget->hasAVX2())
10213 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10214 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10216 // Otherwise, fall back.
10217 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10221 // X86 has dedicated unpack instructions that can handle specific blend
10222 // operations: UNPCKH and UNPCKL.
10223 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10224 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10225 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10226 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10227 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10228 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
10229 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10230 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
10232 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10236 // Check if the blend happens to exactly fit that of SHUFPD.
10238 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10241 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10242 // shuffle. However, if we have AVX2 and either inputs are already in place,
10243 // we will be able to shuffle even across lanes the other input in a single
10244 // instruction so skip this pattern.
10245 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10246 isShuffleMaskInputInPlace(1, Mask))))
10247 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10248 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10251 // If we have AVX2 then we always want to lower with a blend because an v4 we
10252 // can fully permute the elements.
10253 if (Subtarget->hasAVX2())
10254 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10257 // Otherwise fall back on generic lowering.
10258 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10261 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10263 /// This routine is only called when we have AVX2 and thus a reasonable
10264 /// instruction set for v4i64 shuffling..
10265 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10266 const X86Subtarget *Subtarget,
10267 SelectionDAG &DAG) {
10269 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10270 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10271 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10272 ArrayRef<int> Mask = SVOp->getMask();
10273 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10274 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10276 SmallVector<int, 4> WidenedMask;
10277 if (canWidenShuffleElements(Mask, WidenedMask))
10278 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10281 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10285 // Check for being able to broadcast a single element.
10286 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10287 Mask, Subtarget, DAG))
10290 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10291 // use lower latency instructions that will operate on both 128-bit lanes.
10292 SmallVector<int, 2> RepeatedMask;
10293 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10294 if (isSingleInputShuffleMask(Mask)) {
10295 int PSHUFDMask[] = {-1, -1, -1, -1};
10296 for (int i = 0; i < 2; ++i)
10297 if (RepeatedMask[i] >= 0) {
10298 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10299 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10301 return DAG.getBitcast(
10303 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10304 DAG.getBitcast(MVT::v8i32, V1),
10305 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10309 // AVX2 provides a direct instruction for permuting a single input across
10311 if (isSingleInputShuffleMask(Mask))
10312 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10313 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10315 // Try to use shift instructions.
10316 if (SDValue Shift =
10317 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10320 // Use dedicated unpack instructions for masks that match their pattern.
10321 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10322 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10323 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10324 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10325 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10326 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
10327 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10328 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
10330 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10331 // shuffle. However, if we have AVX2 and either inputs are already in place,
10332 // we will be able to shuffle even across lanes the other input in a single
10333 // instruction so skip this pattern.
10334 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10335 isShuffleMaskInputInPlace(1, Mask))))
10336 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10337 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10340 // Otherwise fall back on generic blend lowering.
10341 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10345 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10347 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10348 /// isn't available.
10349 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10350 const X86Subtarget *Subtarget,
10351 SelectionDAG &DAG) {
10353 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10354 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10355 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10356 ArrayRef<int> Mask = SVOp->getMask();
10357 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10359 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10363 // Check for being able to broadcast a single element.
10364 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10365 Mask, Subtarget, DAG))
10368 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10369 // options to efficiently lower the shuffle.
10370 SmallVector<int, 4> RepeatedMask;
10371 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10372 assert(RepeatedMask.size() == 4 &&
10373 "Repeated masks must be half the mask width!");
10375 // Use even/odd duplicate instructions for masks that match their pattern.
10376 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10377 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10378 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10379 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10381 if (isSingleInputShuffleMask(Mask))
10382 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10383 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10385 // Use dedicated unpack instructions for masks that match their pattern.
10386 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10387 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10388 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10389 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10390 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10391 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
10392 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10393 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
10395 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10396 // have already handled any direct blends. We also need to squash the
10397 // repeated mask into a simulated v4f32 mask.
10398 for (int i = 0; i < 4; ++i)
10399 if (RepeatedMask[i] >= 8)
10400 RepeatedMask[i] -= 4;
10401 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10404 // If we have a single input shuffle with different shuffle patterns in the
10405 // two 128-bit lanes use the variable mask to VPERMILPS.
10406 if (isSingleInputShuffleMask(Mask)) {
10407 SDValue VPermMask[8];
10408 for (int i = 0; i < 8; ++i)
10409 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10410 : DAG.getConstant(Mask[i], DL, MVT::i32);
10411 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10412 return DAG.getNode(
10413 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10414 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10416 if (Subtarget->hasAVX2())
10417 return DAG.getNode(
10418 X86ISD::VPERMV, DL, MVT::v8f32,
10419 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10420 MVT::v8i32, VPermMask)),
10423 // Otherwise, fall back.
10424 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10428 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10430 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10431 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10434 // If we have AVX2 then we always want to lower with a blend because at v8 we
10435 // can fully permute the elements.
10436 if (Subtarget->hasAVX2())
10437 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10440 // Otherwise fall back on generic lowering.
10441 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10444 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10446 /// This routine is only called when we have AVX2 and thus a reasonable
10447 /// instruction set for v8i32 shuffling..
10448 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10449 const X86Subtarget *Subtarget,
10450 SelectionDAG &DAG) {
10452 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10453 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10454 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10455 ArrayRef<int> Mask = SVOp->getMask();
10456 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10457 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10459 // Whenever we can lower this as a zext, that instruction is strictly faster
10460 // than any alternative. It also allows us to fold memory operands into the
10461 // shuffle in many cases.
10462 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10463 Mask, Subtarget, DAG))
10466 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10470 // Check for being able to broadcast a single element.
10471 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10472 Mask, Subtarget, DAG))
10475 // If the shuffle mask is repeated in each 128-bit lane we can use more
10476 // efficient instructions that mirror the shuffles across the two 128-bit
10478 SmallVector<int, 4> RepeatedMask;
10479 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10480 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10481 if (isSingleInputShuffleMask(Mask))
10482 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10483 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10485 // Use dedicated unpack instructions for masks that match their pattern.
10486 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10487 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10488 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10489 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10490 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10491 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10492 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10493 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10496 // Try to use shift instructions.
10497 if (SDValue Shift =
10498 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10501 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10502 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10505 // If the shuffle patterns aren't repeated but it is a single input, directly
10506 // generate a cross-lane VPERMD instruction.
10507 if (isSingleInputShuffleMask(Mask)) {
10508 SDValue VPermMask[8];
10509 for (int i = 0; i < 8; ++i)
10510 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10511 : DAG.getConstant(Mask[i], DL, MVT::i32);
10512 return DAG.getNode(
10513 X86ISD::VPERMV, DL, MVT::v8i32,
10514 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10517 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10519 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10520 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10523 // Otherwise fall back on generic blend lowering.
10524 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10528 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10530 /// This routine is only called when we have AVX2 and thus a reasonable
10531 /// instruction set for v16i16 shuffling..
10532 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10533 const X86Subtarget *Subtarget,
10534 SelectionDAG &DAG) {
10536 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10537 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10538 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10539 ArrayRef<int> Mask = SVOp->getMask();
10540 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10541 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10543 // Whenever we can lower this as a zext, that instruction is strictly faster
10544 // than any alternative. It also allows us to fold memory operands into the
10545 // shuffle in many cases.
10546 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10547 Mask, Subtarget, DAG))
10550 // Check for being able to broadcast a single element.
10551 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10552 Mask, Subtarget, DAG))
10555 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10559 // Use dedicated unpack instructions for masks that match their pattern.
10560 if (isShuffleEquivalent(V1, V2, Mask,
10561 {// First 128-bit lane:
10562 0, 16, 1, 17, 2, 18, 3, 19,
10563 // Second 128-bit lane:
10564 8, 24, 9, 25, 10, 26, 11, 27}))
10565 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10566 if (isShuffleEquivalent(V1, V2, Mask,
10567 {// First 128-bit lane:
10568 4, 20, 5, 21, 6, 22, 7, 23,
10569 // Second 128-bit lane:
10570 12, 28, 13, 29, 14, 30, 15, 31}))
10571 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10573 // Try to use shift instructions.
10574 if (SDValue Shift =
10575 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10578 // Try to use byte rotation instructions.
10579 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10580 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10583 if (isSingleInputShuffleMask(Mask)) {
10584 // There are no generalized cross-lane shuffle operations available on i16
10586 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10587 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10590 SmallVector<int, 8> RepeatedMask;
10591 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10592 // As this is a single-input shuffle, the repeated mask should be
10593 // a strictly valid v8i16 mask that we can pass through to the v8i16
10594 // lowering to handle even the v16 case.
10595 return lowerV8I16GeneralSingleInputVectorShuffle(
10596 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10599 SDValue PSHUFBMask[32];
10600 for (int i = 0; i < 16; ++i) {
10601 if (Mask[i] == -1) {
10602 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10606 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10607 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10608 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10609 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10611 return DAG.getBitcast(MVT::v16i16,
10612 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10613 DAG.getBitcast(MVT::v32i8, V1),
10614 DAG.getNode(ISD::BUILD_VECTOR, DL,
10615 MVT::v32i8, PSHUFBMask)));
10618 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10620 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10621 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10624 // Otherwise fall back on generic lowering.
10625 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10628 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10630 /// This routine is only called when we have AVX2 and thus a reasonable
10631 /// instruction set for v32i8 shuffling..
10632 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10633 const X86Subtarget *Subtarget,
10634 SelectionDAG &DAG) {
10636 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10637 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10638 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10639 ArrayRef<int> Mask = SVOp->getMask();
10640 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10641 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10643 // Whenever we can lower this as a zext, that instruction is strictly faster
10644 // than any alternative. It also allows us to fold memory operands into the
10645 // shuffle in many cases.
10646 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10647 Mask, Subtarget, DAG))
10650 // Check for being able to broadcast a single element.
10651 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10652 Mask, Subtarget, DAG))
10655 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10659 // Use dedicated unpack instructions for masks that match their pattern.
10660 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10662 if (isShuffleEquivalent(
10664 {// First 128-bit lane:
10665 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10666 // Second 128-bit lane:
10667 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10668 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10669 if (isShuffleEquivalent(
10671 {// First 128-bit lane:
10672 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10673 // Second 128-bit lane:
10674 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10675 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10677 // Try to use shift instructions.
10678 if (SDValue Shift =
10679 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10682 // Try to use byte rotation instructions.
10683 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10684 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10687 if (isSingleInputShuffleMask(Mask)) {
10688 // There are no generalized cross-lane shuffle operations available on i8
10690 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10691 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10694 SDValue PSHUFBMask[32];
10695 for (int i = 0; i < 32; ++i)
10698 ? DAG.getUNDEF(MVT::i8)
10699 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10702 return DAG.getNode(
10703 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10704 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10707 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10709 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10710 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10713 // Otherwise fall back on generic lowering.
10714 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10717 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10719 /// This routine either breaks down the specific type of a 256-bit x86 vector
10720 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10721 /// together based on the available instructions.
10722 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10723 MVT VT, const X86Subtarget *Subtarget,
10724 SelectionDAG &DAG) {
10726 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10727 ArrayRef<int> Mask = SVOp->getMask();
10729 // If we have a single input to the zero element, insert that into V1 if we
10730 // can do so cheaply.
10731 int NumElts = VT.getVectorNumElements();
10732 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10733 return M >= NumElts;
10736 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10737 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10738 DL, VT, V1, V2, Mask, Subtarget, DAG))
10741 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10742 // can check for those subtargets here and avoid much of the subtarget
10743 // querying in the per-vector-type lowering routines. With AVX1 we have
10744 // essentially *zero* ability to manipulate a 256-bit vector with integer
10745 // types. Since we'll use floating point types there eventually, just
10746 // immediately cast everything to a float and operate entirely in that domain.
10747 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10748 int ElementBits = VT.getScalarSizeInBits();
10749 if (ElementBits < 32)
10750 // No floating point type available, decompose into 128-bit vectors.
10751 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10753 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10754 VT.getVectorNumElements());
10755 V1 = DAG.getBitcast(FpVT, V1);
10756 V2 = DAG.getBitcast(FpVT, V2);
10757 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10760 switch (VT.SimpleTy) {
10762 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10764 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10766 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10768 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10770 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10772 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10775 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10779 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
10780 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
10781 ArrayRef<int> Mask,
10782 SDValue V1, SDValue V2,
10783 SelectionDAG &DAG) {
10784 assert(VT.getScalarSizeInBits() == 64 &&
10785 "Unexpected element type size for 128bit shuffle.");
10787 // To handle 256 bit vector requires VLX and most probably
10788 // function lowerV2X128VectorShuffle() is better solution.
10789 assert(VT.getSizeInBits() == 512 &&
10790 "Unexpected vector size for 128bit shuffle.");
10792 SmallVector<int, 4> WidenedMask;
10793 if (!canWidenShuffleElements(Mask, WidenedMask))
10796 // Form a 128-bit permutation.
10797 // Convert the 64-bit shuffle mask selection values into 128-bit selection
10798 // bits defined by a vshuf64x2 instruction's immediate control byte.
10799 unsigned PermMask = 0, Imm = 0;
10800 unsigned ControlBitsNum = WidenedMask.size() / 2;
10802 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
10803 if (WidenedMask[i] == SM_SentinelZero)
10806 // Use first element in place of undef mask.
10807 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
10808 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
10811 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
10812 DAG.getConstant(PermMask, DL, MVT::i8));
10815 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10816 ArrayRef<int> Mask, SDValue V1,
10817 SDValue V2, SelectionDAG &DAG) {
10819 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10821 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10822 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10824 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
10825 if (isSingleInputShuffleMask(Mask))
10826 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10828 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10831 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10832 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10833 const X86Subtarget *Subtarget,
10834 SelectionDAG &DAG) {
10836 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10837 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10838 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10839 ArrayRef<int> Mask = SVOp->getMask();
10840 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10842 if (SDValue Shuf128 =
10843 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
10846 if (SDValue Unpck =
10847 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10850 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10853 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10854 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10855 const X86Subtarget *Subtarget,
10856 SelectionDAG &DAG) {
10858 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10859 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10860 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10861 ArrayRef<int> Mask = SVOp->getMask();
10862 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10864 if (SDValue Unpck =
10865 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10868 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10871 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10872 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10873 const X86Subtarget *Subtarget,
10874 SelectionDAG &DAG) {
10876 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10877 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10878 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10879 ArrayRef<int> Mask = SVOp->getMask();
10880 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10882 if (SDValue Shuf128 =
10883 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
10886 if (SDValue Unpck =
10887 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10890 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10893 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10894 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10895 const X86Subtarget *Subtarget,
10896 SelectionDAG &DAG) {
10898 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10899 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10900 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10901 ArrayRef<int> Mask = SVOp->getMask();
10902 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10904 if (SDValue Unpck =
10905 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
10908 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
10911 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10912 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10913 const X86Subtarget *Subtarget,
10914 SelectionDAG &DAG) {
10916 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10917 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10918 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10919 ArrayRef<int> Mask = SVOp->getMask();
10920 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10921 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10923 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
10926 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10927 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10928 const X86Subtarget *Subtarget,
10929 SelectionDAG &DAG) {
10931 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10932 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10933 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10934 ArrayRef<int> Mask = SVOp->getMask();
10935 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10936 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10938 // FIXME: Implement direct support for this type!
10939 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10942 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10944 /// This routine either breaks down the specific type of a 512-bit x86 vector
10945 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10946 /// together based on the available instructions.
10947 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10948 MVT VT, const X86Subtarget *Subtarget,
10949 SelectionDAG &DAG) {
10951 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10952 ArrayRef<int> Mask = SVOp->getMask();
10953 assert(Subtarget->hasAVX512() &&
10954 "Cannot lower 512-bit vectors w/ basic ISA!");
10956 // Check for being able to broadcast a single element.
10957 if (SDValue Broadcast =
10958 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10961 // Dispatch to each element type for lowering. If we don't have supprot for
10962 // specific element type shuffles at 512 bits, immediately split them and
10963 // lower them. Each lowering routine of a given type is allowed to assume that
10964 // the requisite ISA extensions for that element type are available.
10965 switch (VT.SimpleTy) {
10967 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10969 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10971 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10973 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10975 if (Subtarget->hasBWI())
10976 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10979 if (Subtarget->hasBWI())
10980 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10984 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10987 // Otherwise fall back on splitting.
10988 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10991 // Lower vXi1 vector shuffles.
10992 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
10993 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
10994 // vector, shuffle and then truncate it back.
10995 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10996 MVT VT, const X86Subtarget *Subtarget,
10997 SelectionDAG &DAG) {
10999 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11000 ArrayRef<int> Mask = SVOp->getMask();
11001 assert(Subtarget->hasAVX512() &&
11002 "Cannot lower 512-bit vectors w/o basic ISA!");
11004 switch (VT.SimpleTy) {
11006 assert(false && "Expected a vector of i1 elements");
11009 ExtVT = MVT::v2i64;
11012 ExtVT = MVT::v4i32;
11015 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
11018 ExtVT = MVT::v16i32;
11021 ExtVT = MVT::v32i16;
11024 ExtVT = MVT::v64i8;
11028 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11029 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11030 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
11031 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11033 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
11036 V2 = DAG.getUNDEF(ExtVT);
11037 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11038 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11039 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11040 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11042 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11043 return DAG.getNode(ISD::TRUNCATE, DL, VT,
11044 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11046 /// \brief Top-level lowering for x86 vector shuffles.
11048 /// This handles decomposition, canonicalization, and lowering of all x86
11049 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11050 /// above in helper routines. The canonicalization attempts to widen shuffles
11051 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11052 /// s.t. only one of the two inputs needs to be tested, etc.
11053 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11054 SelectionDAG &DAG) {
11055 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11056 ArrayRef<int> Mask = SVOp->getMask();
11057 SDValue V1 = Op.getOperand(0);
11058 SDValue V2 = Op.getOperand(1);
11059 MVT VT = Op.getSimpleValueType();
11060 int NumElements = VT.getVectorNumElements();
11062 bool Is1BitVector = (VT.getScalarType() == MVT::i1);
11064 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11065 "Can't lower MMX shuffles");
11067 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11068 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11069 if (V1IsUndef && V2IsUndef)
11070 return DAG.getUNDEF(VT);
11072 // When we create a shuffle node we put the UNDEF node to second operand,
11073 // but in some cases the first operand may be transformed to UNDEF.
11074 // In this case we should just commute the node.
11076 return DAG.getCommutedVectorShuffle(*SVOp);
11078 // Check for non-undef masks pointing at an undef vector and make the masks
11079 // undef as well. This makes it easier to match the shuffle based solely on
11083 if (M >= NumElements) {
11084 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11085 for (int &M : NewMask)
11086 if (M >= NumElements)
11088 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11091 // We actually see shuffles that are entirely re-arrangements of a set of
11092 // zero inputs. This mostly happens while decomposing complex shuffles into
11093 // simple ones. Directly lower these as a buildvector of zeros.
11094 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11095 if (Zeroable.all())
11096 return getZeroVector(VT, Subtarget, DAG, dl);
11098 // Try to collapse shuffles into using a vector type with fewer elements but
11099 // wider element types. We cap this to not form integers or floating point
11100 // elements wider than 64 bits, but it might be interesting to form i128
11101 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11102 SmallVector<int, 16> WidenedMask;
11103 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11104 canWidenShuffleElements(Mask, WidenedMask)) {
11105 MVT NewEltVT = VT.isFloatingPoint()
11106 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11107 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11108 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11109 // Make sure that the new vector type is legal. For example, v2f64 isn't
11111 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11112 V1 = DAG.getBitcast(NewVT, V1);
11113 V2 = DAG.getBitcast(NewVT, V2);
11114 return DAG.getBitcast(
11115 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11119 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11120 for (int M : SVOp->getMask())
11122 ++NumUndefElements;
11123 else if (M < NumElements)
11128 // Commute the shuffle as needed such that more elements come from V1 than
11129 // V2. This allows us to match the shuffle pattern strictly on how many
11130 // elements come from V1 without handling the symmetric cases.
11131 if (NumV2Elements > NumV1Elements)
11132 return DAG.getCommutedVectorShuffle(*SVOp);
11134 // When the number of V1 and V2 elements are the same, try to minimize the
11135 // number of uses of V2 in the low half of the vector. When that is tied,
11136 // ensure that the sum of indices for V1 is equal to or lower than the sum
11137 // indices for V2. When those are equal, try to ensure that the number of odd
11138 // indices for V1 is lower than the number of odd indices for V2.
11139 if (NumV1Elements == NumV2Elements) {
11140 int LowV1Elements = 0, LowV2Elements = 0;
11141 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11142 if (M >= NumElements)
11146 if (LowV2Elements > LowV1Elements) {
11147 return DAG.getCommutedVectorShuffle(*SVOp);
11148 } else if (LowV2Elements == LowV1Elements) {
11149 int SumV1Indices = 0, SumV2Indices = 0;
11150 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11151 if (SVOp->getMask()[i] >= NumElements)
11153 else if (SVOp->getMask()[i] >= 0)
11155 if (SumV2Indices < SumV1Indices) {
11156 return DAG.getCommutedVectorShuffle(*SVOp);
11157 } else if (SumV2Indices == SumV1Indices) {
11158 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11159 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11160 if (SVOp->getMask()[i] >= NumElements)
11161 NumV2OddIndices += i % 2;
11162 else if (SVOp->getMask()[i] >= 0)
11163 NumV1OddIndices += i % 2;
11164 if (NumV2OddIndices < NumV1OddIndices)
11165 return DAG.getCommutedVectorShuffle(*SVOp);
11170 // For each vector width, delegate to a specialized lowering routine.
11171 if (VT.getSizeInBits() == 128)
11172 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11174 if (VT.getSizeInBits() == 256)
11175 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11177 if (VT.getSizeInBits() == 512)
11178 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11181 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11182 llvm_unreachable("Unimplemented!");
11185 // This function assumes its argument is a BUILD_VECTOR of constants or
11186 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11188 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11189 unsigned &MaskValue) {
11191 unsigned NumElems = BuildVector->getNumOperands();
11193 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11194 // We don't handle the >2 lanes case right now.
11195 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11199 unsigned NumElemsInLane = NumElems / NumLanes;
11201 // Blend for v16i16 should be symmetric for the both lanes.
11202 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11203 SDValue EltCond = BuildVector->getOperand(i);
11204 SDValue SndLaneEltCond =
11205 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11207 int Lane1Cond = -1, Lane2Cond = -1;
11208 if (isa<ConstantSDNode>(EltCond))
11209 Lane1Cond = !isZero(EltCond);
11210 if (isa<ConstantSDNode>(SndLaneEltCond))
11211 Lane2Cond = !isZero(SndLaneEltCond);
11213 unsigned LaneMask = 0;
11214 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11215 // Lane1Cond != 0, means we want the first argument.
11216 // Lane1Cond == 0, means we want the second argument.
11217 // The encoding of this argument is 0 for the first argument, 1
11218 // for the second. Therefore, invert the condition.
11219 LaneMask = !Lane1Cond << i;
11220 else if (Lane1Cond < 0)
11221 LaneMask = !Lane2Cond << i;
11225 MaskValue |= LaneMask;
11227 MaskValue |= LaneMask << NumElemsInLane;
11232 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11233 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11234 const X86Subtarget *Subtarget,
11235 SelectionDAG &DAG) {
11236 SDValue Cond = Op.getOperand(0);
11237 SDValue LHS = Op.getOperand(1);
11238 SDValue RHS = Op.getOperand(2);
11240 MVT VT = Op.getSimpleValueType();
11242 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11244 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11246 // Only non-legal VSELECTs reach this lowering, convert those into generic
11247 // shuffles and re-use the shuffle lowering path for blends.
11248 SmallVector<int, 32> Mask;
11249 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11250 SDValue CondElt = CondBV->getOperand(i);
11252 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11254 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11257 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11258 // A vselect where all conditions and data are constants can be optimized into
11259 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11260 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11261 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11262 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11265 // Try to lower this to a blend-style vector shuffle. This can handle all
11266 // constant condition cases.
11267 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11270 // Variable blends are only legal from SSE4.1 onward.
11271 if (!Subtarget->hasSSE41())
11274 // Only some types will be legal on some subtargets. If we can emit a legal
11275 // VSELECT-matching blend, return Op, and but if we need to expand, return
11277 switch (Op.getSimpleValueType().SimpleTy) {
11279 // Most of the vector types have blends past SSE4.1.
11283 // The byte blends for AVX vectors were introduced only in AVX2.
11284 if (Subtarget->hasAVX2())
11291 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11292 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11295 // FIXME: We should custom lower this by fixing the condition and using i8
11301 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11302 MVT VT = Op.getSimpleValueType();
11305 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11308 if (VT.getSizeInBits() == 8) {
11309 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11310 Op.getOperand(0), Op.getOperand(1));
11311 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11312 DAG.getValueType(VT));
11313 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11316 if (VT.getSizeInBits() == 16) {
11317 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11318 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11320 return DAG.getNode(
11321 ISD::TRUNCATE, dl, MVT::i16,
11322 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11323 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11324 Op.getOperand(1)));
11325 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11326 Op.getOperand(0), Op.getOperand(1));
11327 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11328 DAG.getValueType(VT));
11329 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11332 if (VT == MVT::f32) {
11333 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11334 // the result back to FR32 register. It's only worth matching if the
11335 // result has a single use which is a store or a bitcast to i32. And in
11336 // the case of a store, it's not worth it if the index is a constant 0,
11337 // because a MOVSSmr can be used instead, which is smaller and faster.
11338 if (!Op.hasOneUse())
11340 SDNode *User = *Op.getNode()->use_begin();
11341 if ((User->getOpcode() != ISD::STORE ||
11342 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11343 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11344 (User->getOpcode() != ISD::BITCAST ||
11345 User->getValueType(0) != MVT::i32))
11347 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11348 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11350 return DAG.getBitcast(MVT::f32, Extract);
11353 if (VT == MVT::i32 || VT == MVT::i64) {
11354 // ExtractPS/pextrq works with constant index.
11355 if (isa<ConstantSDNode>(Op.getOperand(1)))
11361 /// Extract one bit from mask vector, like v16i1 or v8i1.
11362 /// AVX-512 feature.
11364 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11365 SDValue Vec = Op.getOperand(0);
11367 MVT VecVT = Vec.getSimpleValueType();
11368 SDValue Idx = Op.getOperand(1);
11369 MVT EltVT = Op.getSimpleValueType();
11371 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11372 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11373 "Unexpected vector type in ExtractBitFromMaskVector");
11375 // variable index can't be handled in mask registers,
11376 // extend vector to VR512
11377 if (!isa<ConstantSDNode>(Idx)) {
11378 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11379 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11380 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11381 ExtVT.getVectorElementType(), Ext, Idx);
11382 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11385 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11386 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11387 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11388 rc = getRegClassFor(MVT::v16i1);
11389 unsigned MaxSift = rc->getSize()*8 - 1;
11390 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11391 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11392 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11393 DAG.getConstant(MaxSift, dl, MVT::i8));
11394 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11395 DAG.getIntPtrConstant(0, dl));
11399 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11400 SelectionDAG &DAG) const {
11402 SDValue Vec = Op.getOperand(0);
11403 MVT VecVT = Vec.getSimpleValueType();
11404 SDValue Idx = Op.getOperand(1);
11406 if (Op.getSimpleValueType() == MVT::i1)
11407 return ExtractBitFromMaskVector(Op, DAG);
11409 if (!isa<ConstantSDNode>(Idx)) {
11410 if (VecVT.is512BitVector() ||
11411 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11412 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11415 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11416 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11417 MaskEltVT.getSizeInBits());
11419 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11420 auto PtrVT = getPointerTy(DAG.getDataLayout());
11421 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11422 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11423 DAG.getConstant(0, dl, PtrVT));
11424 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11425 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11426 DAG.getConstant(0, dl, PtrVT));
11431 // If this is a 256-bit vector result, first extract the 128-bit vector and
11432 // then extract the element from the 128-bit vector.
11433 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11435 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11436 // Get the 128-bit vector.
11437 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11438 MVT EltVT = VecVT.getVectorElementType();
11440 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11442 //if (IdxVal >= NumElems/2)
11443 // IdxVal -= NumElems/2;
11444 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11445 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11446 DAG.getConstant(IdxVal, dl, MVT::i32));
11449 assert(VecVT.is128BitVector() && "Unexpected vector length");
11451 if (Subtarget->hasSSE41())
11452 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11455 MVT VT = Op.getSimpleValueType();
11456 // TODO: handle v16i8.
11457 if (VT.getSizeInBits() == 16) {
11458 SDValue Vec = Op.getOperand(0);
11459 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11461 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11462 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11463 DAG.getBitcast(MVT::v4i32, Vec),
11464 Op.getOperand(1)));
11465 // Transform it so it match pextrw which produces a 32-bit result.
11466 MVT EltVT = MVT::i32;
11467 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11468 Op.getOperand(0), Op.getOperand(1));
11469 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11470 DAG.getValueType(VT));
11471 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11474 if (VT.getSizeInBits() == 32) {
11475 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11479 // SHUFPS the element to the lowest double word, then movss.
11480 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11481 MVT VVT = Op.getOperand(0).getSimpleValueType();
11482 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11483 DAG.getUNDEF(VVT), Mask);
11484 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11485 DAG.getIntPtrConstant(0, dl));
11488 if (VT.getSizeInBits() == 64) {
11489 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11490 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11491 // to match extract_elt for f64.
11492 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11496 // UNPCKHPD the element to the lowest double word, then movsd.
11497 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11498 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11499 int Mask[2] = { 1, -1 };
11500 MVT VVT = Op.getOperand(0).getSimpleValueType();
11501 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11502 DAG.getUNDEF(VVT), Mask);
11503 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11504 DAG.getIntPtrConstant(0, dl));
11510 /// Insert one bit to mask vector, like v16i1 or v8i1.
11511 /// AVX-512 feature.
11513 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11515 SDValue Vec = Op.getOperand(0);
11516 SDValue Elt = Op.getOperand(1);
11517 SDValue Idx = Op.getOperand(2);
11518 MVT VecVT = Vec.getSimpleValueType();
11520 if (!isa<ConstantSDNode>(Idx)) {
11521 // Non constant index. Extend source and destination,
11522 // insert element and then truncate the result.
11523 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11524 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11525 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11526 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11527 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11528 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11531 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11532 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11534 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11535 DAG.getConstant(IdxVal, dl, MVT::i8));
11536 if (Vec.getOpcode() == ISD::UNDEF)
11538 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11541 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11542 SelectionDAG &DAG) const {
11543 MVT VT = Op.getSimpleValueType();
11544 MVT EltVT = VT.getVectorElementType();
11546 if (EltVT == MVT::i1)
11547 return InsertBitToMaskVector(Op, DAG);
11550 SDValue N0 = Op.getOperand(0);
11551 SDValue N1 = Op.getOperand(1);
11552 SDValue N2 = Op.getOperand(2);
11553 if (!isa<ConstantSDNode>(N2))
11555 auto *N2C = cast<ConstantSDNode>(N2);
11556 unsigned IdxVal = N2C->getZExtValue();
11558 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11559 // into that, and then insert the subvector back into the result.
11560 if (VT.is256BitVector() || VT.is512BitVector()) {
11561 // With a 256-bit vector, we can insert into the zero element efficiently
11562 // using a blend if we have AVX or AVX2 and the right data type.
11563 if (VT.is256BitVector() && IdxVal == 0) {
11564 // TODO: It is worthwhile to cast integer to floating point and back
11565 // and incur a domain crossing penalty if that's what we'll end up
11566 // doing anyway after extracting to a 128-bit vector.
11567 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11568 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11569 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11570 N2 = DAG.getIntPtrConstant(1, dl);
11571 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11575 // Get the desired 128-bit vector chunk.
11576 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11578 // Insert the element into the desired chunk.
11579 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11580 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11582 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11583 DAG.getConstant(IdxIn128, dl, MVT::i32));
11585 // Insert the changed part back into the bigger vector
11586 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11588 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11590 if (Subtarget->hasSSE41()) {
11591 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11593 if (VT == MVT::v8i16) {
11594 Opc = X86ISD::PINSRW;
11596 assert(VT == MVT::v16i8);
11597 Opc = X86ISD::PINSRB;
11600 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11602 if (N1.getValueType() != MVT::i32)
11603 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11604 if (N2.getValueType() != MVT::i32)
11605 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11606 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11609 if (EltVT == MVT::f32) {
11610 // Bits [7:6] of the constant are the source select. This will always be
11611 // zero here. The DAG Combiner may combine an extract_elt index into
11612 // these bits. For example (insert (extract, 3), 2) could be matched by
11613 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11614 // Bits [5:4] of the constant are the destination select. This is the
11615 // value of the incoming immediate.
11616 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11617 // combine either bitwise AND or insert of float 0.0 to set these bits.
11619 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11620 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11621 // If this is an insertion of 32-bits into the low 32-bits of
11622 // a vector, we prefer to generate a blend with immediate rather
11623 // than an insertps. Blends are simpler operations in hardware and so
11624 // will always have equal or better performance than insertps.
11625 // But if optimizing for size and there's a load folding opportunity,
11626 // generate insertps because blendps does not have a 32-bit memory
11628 N2 = DAG.getIntPtrConstant(1, dl);
11629 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11630 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11632 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11633 // Create this as a scalar to vector..
11634 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11635 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11638 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11639 // PINSR* works with constant index.
11644 if (EltVT == MVT::i8)
11647 if (EltVT.getSizeInBits() == 16) {
11648 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11649 // as its second argument.
11650 if (N1.getValueType() != MVT::i32)
11651 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11652 if (N2.getValueType() != MVT::i32)
11653 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11654 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11659 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11661 MVT OpVT = Op.getSimpleValueType();
11663 // If this is a 256-bit vector result, first insert into a 128-bit
11664 // vector and then insert into the 256-bit vector.
11665 if (!OpVT.is128BitVector()) {
11666 // Insert into a 128-bit vector.
11667 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11668 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11669 OpVT.getVectorNumElements() / SizeFactor);
11671 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11673 // Insert the 128-bit vector.
11674 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11677 if (OpVT == MVT::v1i64 &&
11678 Op.getOperand(0).getValueType() == MVT::i64)
11679 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11681 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11682 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11683 return DAG.getBitcast(
11684 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11687 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11688 // a simple subregister reference or explicit instructions to grab
11689 // upper bits of a vector.
11690 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11691 SelectionDAG &DAG) {
11693 SDValue In = Op.getOperand(0);
11694 SDValue Idx = Op.getOperand(1);
11695 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11696 MVT ResVT = Op.getSimpleValueType();
11697 MVT InVT = In.getSimpleValueType();
11699 if (Subtarget->hasFp256()) {
11700 if (ResVT.is128BitVector() &&
11701 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11702 isa<ConstantSDNode>(Idx)) {
11703 return Extract128BitVector(In, IdxVal, DAG, dl);
11705 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11706 isa<ConstantSDNode>(Idx)) {
11707 return Extract256BitVector(In, IdxVal, DAG, dl);
11713 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11714 // simple superregister reference or explicit instructions to insert
11715 // the upper bits of a vector.
11716 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11717 SelectionDAG &DAG) {
11718 if (!Subtarget->hasAVX())
11722 SDValue Vec = Op.getOperand(0);
11723 SDValue SubVec = Op.getOperand(1);
11724 SDValue Idx = Op.getOperand(2);
11726 if (!isa<ConstantSDNode>(Idx))
11729 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11730 MVT OpVT = Op.getSimpleValueType();
11731 MVT SubVecVT = SubVec.getSimpleValueType();
11733 // Fold two 16-byte subvector loads into one 32-byte load:
11734 // (insert_subvector (insert_subvector undef, (load addr), 0),
11735 // (load addr + 16), Elts/2)
11737 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11738 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11739 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11740 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11741 if (Idx2 && Idx2->getZExtValue() == 0) {
11742 SDValue SubVec2 = Vec.getOperand(1);
11743 // If needed, look through a bitcast to get to the load.
11744 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11745 SubVec2 = SubVec2.getOperand(0);
11747 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11749 unsigned Alignment = FirstLd->getAlignment();
11750 unsigned AS = FirstLd->getAddressSpace();
11751 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11752 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11753 OpVT, AS, Alignment, &Fast) && Fast) {
11754 SDValue Ops[] = { SubVec2, SubVec };
11755 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11762 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11763 SubVecVT.is128BitVector())
11764 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11766 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11767 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11769 if (OpVT.getVectorElementType() == MVT::i1) {
11770 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11772 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11773 SDValue Undef = DAG.getUNDEF(OpVT);
11774 unsigned NumElems = OpVT.getVectorNumElements();
11775 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11777 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11778 // Zero upper bits of the Vec
11779 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11780 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11782 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11784 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11785 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11788 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11790 // Zero upper bits of the Vec2
11791 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11792 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11793 // Zero lower bits of the Vec
11794 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11795 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11796 // Merge them together
11797 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11803 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11804 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11805 // one of the above mentioned nodes. It has to be wrapped because otherwise
11806 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11807 // be used to form addressing mode. These wrapped nodes will be selected
11810 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11811 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11813 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11814 // global base reg.
11815 unsigned char OpFlag = 0;
11816 unsigned WrapperKind = X86ISD::Wrapper;
11817 CodeModel::Model M = DAG.getTarget().getCodeModel();
11819 if (Subtarget->isPICStyleRIPRel() &&
11820 (M == CodeModel::Small || M == CodeModel::Kernel))
11821 WrapperKind = X86ISD::WrapperRIP;
11822 else if (Subtarget->isPICStyleGOT())
11823 OpFlag = X86II::MO_GOTOFF;
11824 else if (Subtarget->isPICStyleStubPIC())
11825 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11827 auto PtrVT = getPointerTy(DAG.getDataLayout());
11828 SDValue Result = DAG.getTargetConstantPool(
11829 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11831 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11832 // With PIC, the address is actually $g + Offset.
11835 DAG.getNode(ISD::ADD, DL, PtrVT,
11836 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11842 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11843 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11845 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11846 // global base reg.
11847 unsigned char OpFlag = 0;
11848 unsigned WrapperKind = X86ISD::Wrapper;
11849 CodeModel::Model M = DAG.getTarget().getCodeModel();
11851 if (Subtarget->isPICStyleRIPRel() &&
11852 (M == CodeModel::Small || M == CodeModel::Kernel))
11853 WrapperKind = X86ISD::WrapperRIP;
11854 else if (Subtarget->isPICStyleGOT())
11855 OpFlag = X86II::MO_GOTOFF;
11856 else if (Subtarget->isPICStyleStubPIC())
11857 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11859 auto PtrVT = getPointerTy(DAG.getDataLayout());
11860 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11862 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11864 // With PIC, the address is actually $g + Offset.
11867 DAG.getNode(ISD::ADD, DL, PtrVT,
11868 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11874 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11875 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11877 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11878 // global base reg.
11879 unsigned char OpFlag = 0;
11880 unsigned WrapperKind = X86ISD::Wrapper;
11881 CodeModel::Model M = DAG.getTarget().getCodeModel();
11883 if (Subtarget->isPICStyleRIPRel() &&
11884 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11885 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11886 OpFlag = X86II::MO_GOTPCREL;
11887 WrapperKind = X86ISD::WrapperRIP;
11888 } else if (Subtarget->isPICStyleGOT()) {
11889 OpFlag = X86II::MO_GOT;
11890 } else if (Subtarget->isPICStyleStubPIC()) {
11891 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11892 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11893 OpFlag = X86II::MO_DARWIN_NONLAZY;
11896 auto PtrVT = getPointerTy(DAG.getDataLayout());
11897 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11900 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11902 // With PIC, the address is actually $g + Offset.
11903 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11904 !Subtarget->is64Bit()) {
11906 DAG.getNode(ISD::ADD, DL, PtrVT,
11907 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11910 // For symbols that require a load from a stub to get the address, emit the
11912 if (isGlobalStubReference(OpFlag))
11913 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11914 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11915 false, false, false, 0);
11921 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11922 // Create the TargetBlockAddressAddress node.
11923 unsigned char OpFlags =
11924 Subtarget->ClassifyBlockAddressReference();
11925 CodeModel::Model M = DAG.getTarget().getCodeModel();
11926 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11927 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11929 auto PtrVT = getPointerTy(DAG.getDataLayout());
11930 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11932 if (Subtarget->isPICStyleRIPRel() &&
11933 (M == CodeModel::Small || M == CodeModel::Kernel))
11934 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11936 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11938 // With PIC, the address is actually $g + Offset.
11939 if (isGlobalRelativeToPICBase(OpFlags)) {
11940 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11941 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11948 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11949 int64_t Offset, SelectionDAG &DAG) const {
11950 // Create the TargetGlobalAddress node, folding in the constant
11951 // offset if it is legal.
11952 unsigned char OpFlags =
11953 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11954 CodeModel::Model M = DAG.getTarget().getCodeModel();
11955 auto PtrVT = getPointerTy(DAG.getDataLayout());
11957 if (OpFlags == X86II::MO_NO_FLAG &&
11958 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11959 // A direct static reference to a global.
11960 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11963 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11966 if (Subtarget->isPICStyleRIPRel() &&
11967 (M == CodeModel::Small || M == CodeModel::Kernel))
11968 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11970 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11972 // With PIC, the address is actually $g + Offset.
11973 if (isGlobalRelativeToPICBase(OpFlags)) {
11974 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11975 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11978 // For globals that require a load from a stub to get the address, emit the
11980 if (isGlobalStubReference(OpFlags))
11981 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11982 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11983 false, false, false, 0);
11985 // If there was a non-zero offset that we didn't fold, create an explicit
11986 // addition for it.
11988 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11989 DAG.getConstant(Offset, dl, PtrVT));
11995 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11996 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11997 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11998 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12002 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12003 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12004 unsigned char OperandFlags, bool LocalDynamic = false) {
12005 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12006 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12008 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12009 GA->getValueType(0),
12013 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12017 SDValue Ops[] = { Chain, TGA, *InFlag };
12018 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12020 SDValue Ops[] = { Chain, TGA };
12021 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12024 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12025 MFI->setAdjustsStack(true);
12026 MFI->setHasCalls(true);
12028 SDValue Flag = Chain.getValue(1);
12029 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12032 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12034 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12037 SDLoc dl(GA); // ? function entry point might be better
12038 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12039 DAG.getNode(X86ISD::GlobalBaseReg,
12040 SDLoc(), PtrVT), InFlag);
12041 InFlag = Chain.getValue(1);
12043 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12046 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12048 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12050 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12051 X86::RAX, X86II::MO_TLSGD);
12054 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12060 // Get the start address of the TLS block for this module.
12061 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12062 .getInfo<X86MachineFunctionInfo>();
12063 MFI->incNumLocalDynamicTLSAccesses();
12067 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12068 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12071 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12072 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12073 InFlag = Chain.getValue(1);
12074 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12075 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12078 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12082 unsigned char OperandFlags = X86II::MO_DTPOFF;
12083 unsigned WrapperKind = X86ISD::Wrapper;
12084 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12085 GA->getValueType(0),
12086 GA->getOffset(), OperandFlags);
12087 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12089 // Add x@dtpoff with the base.
12090 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12093 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12094 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12095 const EVT PtrVT, TLSModel::Model model,
12096 bool is64Bit, bool isPIC) {
12099 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12100 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12101 is64Bit ? 257 : 256));
12103 SDValue ThreadPointer =
12104 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12105 MachinePointerInfo(Ptr), false, false, false, 0);
12107 unsigned char OperandFlags = 0;
12108 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12110 unsigned WrapperKind = X86ISD::Wrapper;
12111 if (model == TLSModel::LocalExec) {
12112 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12113 } else if (model == TLSModel::InitialExec) {
12115 OperandFlags = X86II::MO_GOTTPOFF;
12116 WrapperKind = X86ISD::WrapperRIP;
12118 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12121 llvm_unreachable("Unexpected model");
12124 // emit "addl x@ntpoff,%eax" (local exec)
12125 // or "addl x@indntpoff,%eax" (initial exec)
12126 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12128 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12129 GA->getOffset(), OperandFlags);
12130 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12132 if (model == TLSModel::InitialExec) {
12133 if (isPIC && !is64Bit) {
12134 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12135 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12139 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12140 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12141 false, false, false, 0);
12144 // The address of the thread local variable is the add of the thread
12145 // pointer with the offset of the variable.
12146 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12150 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12152 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12153 const GlobalValue *GV = GA->getGlobal();
12154 auto PtrVT = getPointerTy(DAG.getDataLayout());
12156 if (Subtarget->isTargetELF()) {
12157 if (DAG.getTarget().Options.EmulatedTLS)
12158 return LowerToTLSEmulatedModel(GA, DAG);
12159 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12161 case TLSModel::GeneralDynamic:
12162 if (Subtarget->is64Bit())
12163 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12164 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12165 case TLSModel::LocalDynamic:
12166 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12167 Subtarget->is64Bit());
12168 case TLSModel::InitialExec:
12169 case TLSModel::LocalExec:
12170 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12171 DAG.getTarget().getRelocationModel() ==
12174 llvm_unreachable("Unknown TLS model.");
12177 if (Subtarget->isTargetDarwin()) {
12178 // Darwin only has one model of TLS. Lower to that.
12179 unsigned char OpFlag = 0;
12180 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12181 X86ISD::WrapperRIP : X86ISD::Wrapper;
12183 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12184 // global base reg.
12185 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12186 !Subtarget->is64Bit();
12188 OpFlag = X86II::MO_TLVP_PIC_BASE;
12190 OpFlag = X86II::MO_TLVP;
12192 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12193 GA->getValueType(0),
12194 GA->getOffset(), OpFlag);
12195 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12197 // With PIC32, the address is actually $g + Offset.
12199 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12200 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12203 // Lowering the machine isd will make sure everything is in the right
12205 SDValue Chain = DAG.getEntryNode();
12206 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12207 SDValue Args[] = { Chain, Offset };
12208 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12210 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12211 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12212 MFI->setAdjustsStack(true);
12214 // And our return value (tls address) is in the standard call return value
12216 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12217 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12220 if (Subtarget->isTargetKnownWindowsMSVC() ||
12221 Subtarget->isTargetWindowsGNU()) {
12222 // Just use the implicit TLS architecture
12223 // Need to generate someting similar to:
12224 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12226 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12227 // mov rcx, qword [rdx+rcx*8]
12228 // mov eax, .tls$:tlsvar
12229 // [rax+rcx] contains the address
12230 // Windows 64bit: gs:0x58
12231 // Windows 32bit: fs:__tls_array
12234 SDValue Chain = DAG.getEntryNode();
12236 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12237 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12238 // use its literal value of 0x2C.
12239 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12240 ? Type::getInt8PtrTy(*DAG.getContext(),
12242 : Type::getInt32PtrTy(*DAG.getContext(),
12245 SDValue TlsArray = Subtarget->is64Bit()
12246 ? DAG.getIntPtrConstant(0x58, dl)
12247 : (Subtarget->isTargetWindowsGNU()
12248 ? DAG.getIntPtrConstant(0x2C, dl)
12249 : DAG.getExternalSymbol("_tls_array", PtrVT));
12251 SDValue ThreadPointer =
12252 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12256 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12257 res = ThreadPointer;
12259 // Load the _tls_index variable
12260 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12261 if (Subtarget->is64Bit())
12262 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12263 MachinePointerInfo(), MVT::i32, false, false,
12266 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12269 auto &DL = DAG.getDataLayout();
12271 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12272 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12274 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12277 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12280 // Get the offset of start of .tls section
12281 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12282 GA->getValueType(0),
12283 GA->getOffset(), X86II::MO_SECREL);
12284 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12286 // The address of the thread local variable is the add of the thread
12287 // pointer with the offset of the variable.
12288 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12291 llvm_unreachable("TLS not implemented for this target.");
12294 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12295 /// and take a 2 x i32 value to shift plus a shift amount.
12296 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12297 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12298 MVT VT = Op.getSimpleValueType();
12299 unsigned VTBits = VT.getSizeInBits();
12301 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12302 SDValue ShOpLo = Op.getOperand(0);
12303 SDValue ShOpHi = Op.getOperand(1);
12304 SDValue ShAmt = Op.getOperand(2);
12305 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12306 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12308 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12309 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12310 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12311 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12312 : DAG.getConstant(0, dl, VT);
12314 SDValue Tmp2, Tmp3;
12315 if (Op.getOpcode() == ISD::SHL_PARTS) {
12316 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12317 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12319 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12320 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12323 // If the shift amount is larger or equal than the width of a part we can't
12324 // rely on the results of shld/shrd. Insert a test and select the appropriate
12325 // values for large shift amounts.
12326 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12327 DAG.getConstant(VTBits, dl, MVT::i8));
12328 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12329 AndNode, DAG.getConstant(0, dl, MVT::i8));
12332 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12333 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12334 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12336 if (Op.getOpcode() == ISD::SHL_PARTS) {
12337 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12338 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12340 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12341 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12344 SDValue Ops[2] = { Lo, Hi };
12345 return DAG.getMergeValues(Ops, dl);
12348 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12349 SelectionDAG &DAG) const {
12350 SDValue Src = Op.getOperand(0);
12351 MVT SrcVT = Src.getSimpleValueType();
12352 MVT VT = Op.getSimpleValueType();
12355 if (SrcVT.isVector()) {
12356 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12357 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12358 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12359 DAG.getUNDEF(SrcVT)));
12361 if (SrcVT.getVectorElementType() == MVT::i1) {
12362 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12363 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12364 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12369 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12370 "Unknown SINT_TO_FP to lower!");
12372 // These are really Legal; return the operand so the caller accepts it as
12374 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12376 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12377 Subtarget->is64Bit()) {
12381 unsigned Size = SrcVT.getSizeInBits()/8;
12382 MachineFunction &MF = DAG.getMachineFunction();
12383 auto PtrVT = getPointerTy(MF.getDataLayout());
12384 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12385 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12386 SDValue Chain = DAG.getStore(
12387 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12388 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12390 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12393 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12395 SelectionDAG &DAG) const {
12399 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12401 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12403 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12405 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12407 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12408 MachineMemOperand *MMO;
12410 int SSFI = FI->getIndex();
12411 MMO = DAG.getMachineFunction().getMachineMemOperand(
12412 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12413 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12415 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12416 StackSlot = StackSlot.getOperand(1);
12418 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12419 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12421 Tys, Ops, SrcVT, MMO);
12424 Chain = Result.getValue(1);
12425 SDValue InFlag = Result.getValue(2);
12427 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12428 // shouldn't be necessary except that RFP cannot be live across
12429 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12430 MachineFunction &MF = DAG.getMachineFunction();
12431 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12432 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12433 auto PtrVT = getPointerTy(MF.getDataLayout());
12434 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12435 Tys = DAG.getVTList(MVT::Other);
12437 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12439 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12440 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12441 MachineMemOperand::MOStore, SSFISize, SSFISize);
12443 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12444 Ops, Op.getValueType(), MMO);
12445 Result = DAG.getLoad(
12446 Op.getValueType(), DL, Chain, StackSlot,
12447 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12448 false, false, false, 0);
12454 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12455 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12456 SelectionDAG &DAG) const {
12457 // This algorithm is not obvious. Here it is what we're trying to output:
12460 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12461 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12463 haddpd %xmm0, %xmm0
12465 pshufd $0x4e, %xmm0, %xmm1
12471 LLVMContext *Context = DAG.getContext();
12473 // Build some magic constants.
12474 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12475 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12476 auto PtrVT = getPointerTy(DAG.getDataLayout());
12477 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12479 SmallVector<Constant*,2> CV1;
12481 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12482 APInt(64, 0x4330000000000000ULL))));
12484 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12485 APInt(64, 0x4530000000000000ULL))));
12486 Constant *C1 = ConstantVector::get(CV1);
12487 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12489 // Load the 64-bit value into an XMM register.
12490 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12493 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12494 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12495 false, false, false, 16);
12497 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12500 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12501 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12502 false, false, false, 16);
12503 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12504 // TODO: Are there any fast-math-flags to propagate here?
12505 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12508 if (Subtarget->hasSSE3()) {
12509 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12510 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12512 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12513 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12515 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12516 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12519 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12520 DAG.getIntPtrConstant(0, dl));
12523 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12524 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12525 SelectionDAG &DAG) const {
12527 // FP constant to bias correct the final result.
12528 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12531 // Load the 32-bit value into an XMM register.
12532 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12535 // Zero out the upper parts of the register.
12536 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12538 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12539 DAG.getBitcast(MVT::v2f64, Load),
12540 DAG.getIntPtrConstant(0, dl));
12542 // Or the load with the bias.
12543 SDValue Or = DAG.getNode(
12544 ISD::OR, dl, MVT::v2i64,
12545 DAG.getBitcast(MVT::v2i64,
12546 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12547 DAG.getBitcast(MVT::v2i64,
12548 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12550 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12551 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12553 // Subtract the bias.
12554 // TODO: Are there any fast-math-flags to propagate here?
12555 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12557 // Handle final rounding.
12558 EVT DestVT = Op.getValueType();
12560 if (DestVT.bitsLT(MVT::f64))
12561 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12562 DAG.getIntPtrConstant(0, dl));
12563 if (DestVT.bitsGT(MVT::f64))
12564 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12566 // Handle final rounding.
12570 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12571 const X86Subtarget &Subtarget) {
12572 // The algorithm is the following:
12573 // #ifdef __SSE4_1__
12574 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12575 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12576 // (uint4) 0x53000000, 0xaa);
12578 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12579 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12581 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12582 // return (float4) lo + fhi;
12584 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12585 // reassociate the two FADDs, and if we do that, the algorithm fails
12586 // spectacularly (PR24512).
12587 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12588 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12589 // there's also the MachineCombiner reassociations happening on Machine IR.
12590 if (DAG.getTarget().Options.UnsafeFPMath)
12594 SDValue V = Op->getOperand(0);
12595 EVT VecIntVT = V.getValueType();
12596 bool Is128 = VecIntVT == MVT::v4i32;
12597 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12598 // If we convert to something else than the supported type, e.g., to v4f64,
12600 if (VecFloatVT != Op->getValueType(0))
12603 unsigned NumElts = VecIntVT.getVectorNumElements();
12604 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12605 "Unsupported custom type");
12606 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12608 // In the #idef/#else code, we have in common:
12609 // - The vector of constants:
12615 // Create the splat vector for 0x4b000000.
12616 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12617 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12618 CstLow, CstLow, CstLow, CstLow};
12619 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12620 makeArrayRef(&CstLowArray[0], NumElts));
12621 // Create the splat vector for 0x53000000.
12622 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12623 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12624 CstHigh, CstHigh, CstHigh, CstHigh};
12625 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12626 makeArrayRef(&CstHighArray[0], NumElts));
12628 // Create the right shift.
12629 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12630 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12631 CstShift, CstShift, CstShift, CstShift};
12632 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12633 makeArrayRef(&CstShiftArray[0], NumElts));
12634 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12637 if (Subtarget.hasSSE41()) {
12638 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12639 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12640 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12641 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12642 // Low will be bitcasted right away, so do not bother bitcasting back to its
12644 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12645 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12646 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12647 // (uint4) 0x53000000, 0xaa);
12648 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12649 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12650 // High will be bitcasted right away, so do not bother bitcasting back to
12651 // its original type.
12652 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12653 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12655 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12656 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12657 CstMask, CstMask, CstMask);
12658 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12659 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12660 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12662 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12663 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12666 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12667 SDValue CstFAdd = DAG.getConstantFP(
12668 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12669 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12670 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12671 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12672 makeArrayRef(&CstFAddArray[0], NumElts));
12674 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12675 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12676 // TODO: Are there any fast-math-flags to propagate here?
12678 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12679 // return (float4) lo + fhi;
12680 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12681 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12684 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12685 SelectionDAG &DAG) const {
12686 SDValue N0 = Op.getOperand(0);
12687 MVT SVT = N0.getSimpleValueType();
12690 switch (SVT.SimpleTy) {
12692 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12697 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12698 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12699 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12703 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12706 if (Subtarget->hasAVX512())
12707 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12708 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12710 llvm_unreachable(nullptr);
12713 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12714 SelectionDAG &DAG) const {
12715 SDValue N0 = Op.getOperand(0);
12717 auto PtrVT = getPointerTy(DAG.getDataLayout());
12719 if (Op.getValueType().isVector())
12720 return lowerUINT_TO_FP_vec(Op, DAG);
12722 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12723 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12724 // the optimization here.
12725 if (DAG.SignBitIsZero(N0))
12726 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12728 MVT SrcVT = N0.getSimpleValueType();
12729 MVT DstVT = Op.getSimpleValueType();
12731 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12732 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12733 // Conversions from unsigned i32 to f32/f64 are legal,
12734 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12738 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12739 return LowerUINT_TO_FP_i64(Op, DAG);
12740 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12741 return LowerUINT_TO_FP_i32(Op, DAG);
12742 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12745 // Make a 64-bit buffer, and use it to build an FILD.
12746 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12747 if (SrcVT == MVT::i32) {
12748 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12749 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12750 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12751 StackSlot, MachinePointerInfo(),
12753 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12754 OffsetSlot, MachinePointerInfo(),
12756 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12760 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12761 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12762 StackSlot, MachinePointerInfo(),
12764 // For i64 source, we need to add the appropriate power of 2 if the input
12765 // was negative. This is the same as the optimization in
12766 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12767 // we must be careful to do the computation in x87 extended precision, not
12768 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12769 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12770 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12771 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12772 MachineMemOperand::MOLoad, 8, 8);
12774 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12775 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12776 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12779 APInt FF(32, 0x5F800000ULL);
12781 // Check whether the sign bit is set.
12782 SDValue SignSet = DAG.getSetCC(
12783 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12784 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12786 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12787 SDValue FudgePtr = DAG.getConstantPool(
12788 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12790 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12791 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12792 SDValue Four = DAG.getIntPtrConstant(4, dl);
12793 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12795 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12797 // Load the value out, extending it from f32 to f80.
12798 // FIXME: Avoid the extend by constructing the right constant pool?
12799 SDValue Fudge = DAG.getExtLoad(
12800 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12801 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12802 false, false, false, 4);
12803 // Extend everything to 80 bits to force it to be done on x87.
12804 // TODO: Are there any fast-math-flags to propagate here?
12805 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12806 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12807 DAG.getIntPtrConstant(0, dl));
12810 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12811 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
12812 // just return an <SDValue(), SDValue()> pair.
12813 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12814 // to i16, i32 or i64, and we lower it to a legal sequence.
12815 // If lowered to the final integer result we return a <result, SDValue()> pair.
12816 // Otherwise we lower it to a sequence ending with a FIST, return a
12817 // <FIST, StackSlot> pair, and the caller is responsible for loading
12818 // the final integer result from StackSlot.
12819 std::pair<SDValue,SDValue>
12820 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12821 bool IsSigned, bool IsReplace) const {
12824 EVT DstTy = Op.getValueType();
12825 EVT TheVT = Op.getOperand(0).getValueType();
12826 auto PtrVT = getPointerTy(DAG.getDataLayout());
12828 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
12829 // f16 must be promoted before using the lowering in this routine.
12830 // fp128 does not use this lowering.
12831 return std::make_pair(SDValue(), SDValue());
12834 // If using FIST to compute an unsigned i64, we'll need some fixup
12835 // to handle values above the maximum signed i64. A FIST is always
12836 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12837 bool UnsignedFixup = !IsSigned &&
12838 DstTy == MVT::i64 &&
12839 (!Subtarget->is64Bit() ||
12840 !isScalarFPTypeInSSEReg(TheVT));
12842 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12843 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12844 // The low 32 bits of the fist result will have the correct uint32 result.
12845 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12849 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12850 DstTy.getSimpleVT() >= MVT::i16 &&
12851 "Unknown FP_TO_INT to lower!");
12853 // These are really Legal.
12854 if (DstTy == MVT::i32 &&
12855 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12856 return std::make_pair(SDValue(), SDValue());
12857 if (Subtarget->is64Bit() &&
12858 DstTy == MVT::i64 &&
12859 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12860 return std::make_pair(SDValue(), SDValue());
12862 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12864 MachineFunction &MF = DAG.getMachineFunction();
12865 unsigned MemSize = DstTy.getSizeInBits()/8;
12866 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12867 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12870 switch (DstTy.getSimpleVT().SimpleTy) {
12871 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12872 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12873 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12874 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12877 SDValue Chain = DAG.getEntryNode();
12878 SDValue Value = Op.getOperand(0);
12879 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12881 if (UnsignedFixup) {
12883 // Conversion to unsigned i64 is implemented with a select,
12884 // depending on whether the source value fits in the range
12885 // of a signed i64. Let Thresh be the FP equivalent of
12886 // 0x8000000000000000ULL.
12888 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12889 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12890 // Fist-to-mem64 FistSrc
12891 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12892 // to XOR'ing the high 32 bits with Adjust.
12894 // Being a power of 2, Thresh is exactly representable in all FP formats.
12895 // For X87 we'd like to use the smallest FP type for this constant, but
12896 // for DAG type consistency we have to match the FP operand type.
12898 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12899 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12900 bool LosesInfo = false;
12901 if (TheVT == MVT::f64)
12902 // The rounding mode is irrelevant as the conversion should be exact.
12903 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12905 else if (TheVT == MVT::f80)
12906 Status = Thresh.convert(APFloat::x87DoubleExtended,
12907 APFloat::rmNearestTiesToEven, &LosesInfo);
12909 assert(Status == APFloat::opOK && !LosesInfo &&
12910 "FP conversion should have been exact");
12912 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12914 SDValue Cmp = DAG.getSetCC(DL,
12915 getSetCCResultType(DAG.getDataLayout(),
12916 *DAG.getContext(), TheVT),
12917 Value, ThreshVal, ISD::SETLT);
12918 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12919 DAG.getConstant(0, DL, MVT::i32),
12920 DAG.getConstant(0x80000000, DL, MVT::i32));
12921 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12922 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12923 *DAG.getContext(), TheVT),
12924 Value, ThreshVal, ISD::SETLT);
12925 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12928 // FIXME This causes a redundant load/store if the SSE-class value is already
12929 // in memory, such as if it is on the callstack.
12930 if (isScalarFPTypeInSSEReg(TheVT)) {
12931 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12932 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12933 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12935 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12937 Chain, StackSlot, DAG.getValueType(TheVT)
12940 MachineMemOperand *MMO =
12941 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12942 MachineMemOperand::MOLoad, MemSize, MemSize);
12943 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12944 Chain = Value.getValue(1);
12945 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12946 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12949 MachineMemOperand *MMO =
12950 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12951 MachineMemOperand::MOStore, MemSize, MemSize);
12953 if (UnsignedFixup) {
12955 // Insert the FIST, load its result as two i32's,
12956 // and XOR the high i32 with Adjust.
12958 SDValue FistOps[] = { Chain, Value, StackSlot };
12959 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12960 FistOps, DstTy, MMO);
12962 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
12963 MachinePointerInfo(),
12964 false, false, false, 0);
12965 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
12966 DAG.getConstant(4, DL, PtrVT));
12968 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
12969 MachinePointerInfo(),
12970 false, false, false, 0);
12971 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
12973 if (Subtarget->is64Bit()) {
12974 // Join High32 and Low32 into a 64-bit result.
12975 // (High32 << 32) | Low32
12976 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
12977 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
12978 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
12979 DAG.getConstant(32, DL, MVT::i8));
12980 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
12981 return std::make_pair(Result, SDValue());
12984 SDValue ResultOps[] = { Low32, High32 };
12986 SDValue pair = IsReplace
12987 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
12988 : DAG.getMergeValues(ResultOps, DL);
12989 return std::make_pair(pair, SDValue());
12991 // Build the FP_TO_INT*_IN_MEM
12992 SDValue Ops[] = { Chain, Value, StackSlot };
12993 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12995 return std::make_pair(FIST, StackSlot);
12999 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13000 const X86Subtarget *Subtarget) {
13001 MVT VT = Op->getSimpleValueType(0);
13002 SDValue In = Op->getOperand(0);
13003 MVT InVT = In.getSimpleValueType();
13006 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
13007 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
13009 // Optimize vectors in AVX mode:
13012 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13013 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13014 // Concat upper and lower parts.
13017 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13018 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13019 // Concat upper and lower parts.
13022 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13023 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13024 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13027 if (Subtarget->hasInt256())
13028 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13030 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13031 SDValue Undef = DAG.getUNDEF(InVT);
13032 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13033 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13034 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13036 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13037 VT.getVectorNumElements()/2);
13039 OpLo = DAG.getBitcast(HVT, OpLo);
13040 OpHi = DAG.getBitcast(HVT, OpHi);
13042 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13045 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13046 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13047 MVT VT = Op->getSimpleValueType(0);
13048 SDValue In = Op->getOperand(0);
13049 MVT InVT = In.getSimpleValueType();
13051 unsigned int NumElts = VT.getVectorNumElements();
13052 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13055 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13056 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13058 assert(InVT.getVectorElementType() == MVT::i1);
13059 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13061 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13063 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13065 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13066 if (VT.is512BitVector())
13068 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13071 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13072 SelectionDAG &DAG) {
13073 if (Subtarget->hasFp256())
13074 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13080 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13081 SelectionDAG &DAG) {
13083 MVT VT = Op.getSimpleValueType();
13084 SDValue In = Op.getOperand(0);
13085 MVT SVT = In.getSimpleValueType();
13087 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13088 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13090 if (Subtarget->hasFp256())
13091 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13094 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13095 VT.getVectorNumElements() != SVT.getVectorNumElements());
13099 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13101 MVT VT = Op.getSimpleValueType();
13102 SDValue In = Op.getOperand(0);
13103 MVT InVT = In.getSimpleValueType();
13105 if (VT == MVT::i1) {
13106 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13107 "Invalid scalar TRUNCATE operation");
13108 if (InVT.getSizeInBits() >= 32)
13110 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13111 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13113 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13114 "Invalid TRUNCATE operation");
13116 // move vector to mask - truncate solution for SKX
13117 if (VT.getVectorElementType() == MVT::i1) {
13118 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13119 Subtarget->hasBWI())
13120 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13121 if ((InVT.is256BitVector() || InVT.is128BitVector())
13122 && InVT.getScalarSizeInBits() <= 16 &&
13123 Subtarget->hasBWI() && Subtarget->hasVLX())
13124 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13125 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13126 Subtarget->hasDQI())
13127 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13128 if ((InVT.is256BitVector() || InVT.is128BitVector())
13129 && InVT.getScalarSizeInBits() >= 32 &&
13130 Subtarget->hasDQI() && Subtarget->hasVLX())
13131 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13134 if (VT.getVectorElementType() == MVT::i1) {
13135 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13136 unsigned NumElts = InVT.getVectorNumElements();
13137 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13138 if (InVT.getSizeInBits() < 512) {
13139 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13140 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13145 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13146 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13147 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13150 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13151 if (((!InVT.is512BitVector() && Subtarget->hasVLX()) || InVT.is512BitVector()) &&
13152 (InVT.getVectorElementType() != MVT::i16 || Subtarget->hasBWI()))
13153 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13155 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13156 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13157 if (Subtarget->hasInt256()) {
13158 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13159 In = DAG.getBitcast(MVT::v8i32, In);
13160 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13162 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13163 DAG.getIntPtrConstant(0, DL));
13166 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13167 DAG.getIntPtrConstant(0, DL));
13168 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13169 DAG.getIntPtrConstant(2, DL));
13170 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13171 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13172 static const int ShufMask[] = {0, 2, 4, 6};
13173 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13176 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13177 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13178 if (Subtarget->hasInt256()) {
13179 In = DAG.getBitcast(MVT::v32i8, In);
13181 SmallVector<SDValue,32> pshufbMask;
13182 for (unsigned i = 0; i < 2; ++i) {
13183 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13184 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13185 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13186 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13187 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13188 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13189 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13190 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13191 for (unsigned j = 0; j < 8; ++j)
13192 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13194 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13195 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13196 In = DAG.getBitcast(MVT::v4i64, In);
13198 static const int ShufMask[] = {0, 2, -1, -1};
13199 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13201 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13202 DAG.getIntPtrConstant(0, DL));
13203 return DAG.getBitcast(VT, In);
13206 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13207 DAG.getIntPtrConstant(0, DL));
13209 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13210 DAG.getIntPtrConstant(4, DL));
13212 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13213 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13215 // The PSHUFB mask:
13216 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13217 -1, -1, -1, -1, -1, -1, -1, -1};
13219 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13220 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13221 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13223 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13224 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13226 // The MOVLHPS Mask:
13227 static const int ShufMask2[] = {0, 1, 4, 5};
13228 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13229 return DAG.getBitcast(MVT::v8i16, res);
13232 // Handle truncation of V256 to V128 using shuffles.
13233 if (!VT.is128BitVector() || !InVT.is256BitVector())
13236 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13238 unsigned NumElems = VT.getVectorNumElements();
13239 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13241 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13242 // Prepare truncation shuffle mask
13243 for (unsigned i = 0; i != NumElems; ++i)
13244 MaskVec[i] = i * 2;
13245 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13246 DAG.getUNDEF(NVT), &MaskVec[0]);
13247 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13248 DAG.getIntPtrConstant(0, DL));
13251 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13252 SelectionDAG &DAG) const {
13253 assert(!Op.getSimpleValueType().isVector());
13255 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13256 /*IsSigned=*/ true, /*IsReplace=*/ false);
13257 SDValue FIST = Vals.first, StackSlot = Vals.second;
13258 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13259 if (!FIST.getNode())
13262 if (StackSlot.getNode())
13263 // Load the result.
13264 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13265 FIST, StackSlot, MachinePointerInfo(),
13266 false, false, false, 0);
13268 // The node is the result.
13272 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13273 SelectionDAG &DAG) const {
13274 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13275 /*IsSigned=*/ false, /*IsReplace=*/ false);
13276 SDValue FIST = Vals.first, StackSlot = Vals.second;
13277 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13278 if (!FIST.getNode())
13281 if (StackSlot.getNode())
13282 // Load the result.
13283 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13284 FIST, StackSlot, MachinePointerInfo(),
13285 false, false, false, 0);
13287 // The node is the result.
13291 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13293 MVT VT = Op.getSimpleValueType();
13294 SDValue In = Op.getOperand(0);
13295 MVT SVT = In.getSimpleValueType();
13297 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13299 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13300 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13301 In, DAG.getUNDEF(SVT)));
13304 /// The only differences between FABS and FNEG are the mask and the logic op.
13305 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13306 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13307 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13308 "Wrong opcode for lowering FABS or FNEG.");
13310 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13312 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13313 // into an FNABS. We'll lower the FABS after that if it is still in use.
13315 for (SDNode *User : Op->uses())
13316 if (User->getOpcode() == ISD::FNEG)
13320 MVT VT = Op.getSimpleValueType();
13322 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13323 // decide if we should generate a 16-byte constant mask when we only need 4 or
13324 // 8 bytes for the scalar case.
13330 if (VT.isVector()) {
13332 EltVT = VT.getVectorElementType();
13333 NumElts = VT.getVectorNumElements();
13335 // There are no scalar bitwise logical SSE/AVX instructions, so we
13336 // generate a 16-byte vector constant and logic op even for the scalar case.
13337 // Using a 16-byte mask allows folding the load of the mask with
13338 // the logic op, so it can save (~4 bytes) on code size.
13339 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13341 NumElts = (VT == MVT::f64) ? 2 : 4;
13344 unsigned EltBits = EltVT.getSizeInBits();
13345 LLVMContext *Context = DAG.getContext();
13346 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13348 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13349 Constant *C = ConstantInt::get(*Context, MaskElt);
13350 C = ConstantVector::getSplat(NumElts, C);
13351 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13352 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13353 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13355 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13356 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13357 false, false, false, Alignment);
13359 SDValue Op0 = Op.getOperand(0);
13360 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13362 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13363 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13366 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13368 // For the scalar case extend to a 128-bit vector, perform the logic op,
13369 // and extract the scalar result back out.
13370 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13371 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13372 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13373 DAG.getIntPtrConstant(0, dl));
13376 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13377 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13378 LLVMContext *Context = DAG.getContext();
13379 SDValue Op0 = Op.getOperand(0);
13380 SDValue Op1 = Op.getOperand(1);
13382 MVT VT = Op.getSimpleValueType();
13383 MVT SrcVT = Op1.getSimpleValueType();
13385 // If second operand is smaller, extend it first.
13386 if (SrcVT.bitsLT(VT)) {
13387 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13390 // And if it is bigger, shrink it first.
13391 if (SrcVT.bitsGT(VT)) {
13392 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13396 // At this point the operands and the result should have the same
13397 // type, and that won't be f80 since that is not custom lowered.
13399 const fltSemantics &Sem =
13400 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13401 const unsigned SizeInBits = VT.getSizeInBits();
13403 SmallVector<Constant *, 4> CV(
13404 VT == MVT::f64 ? 2 : 4,
13405 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13407 // First, clear all bits but the sign bit from the second operand (sign).
13408 CV[0] = ConstantFP::get(*Context,
13409 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13410 Constant *C = ConstantVector::get(CV);
13411 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13412 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13414 // Perform all logic operations as 16-byte vectors because there are no
13415 // scalar FP logic instructions in SSE. This allows load folding of the
13416 // constants into the logic instructions.
13417 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13419 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13420 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13421 false, false, false, 16);
13422 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13423 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13425 // Next, clear the sign bit from the first operand (magnitude).
13426 // If it's a constant, we can clear it here.
13427 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13428 APFloat APF = Op0CN->getValueAPF();
13429 // If the magnitude is a positive zero, the sign bit alone is enough.
13430 if (APF.isPosZero())
13431 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13432 DAG.getIntPtrConstant(0, dl));
13434 CV[0] = ConstantFP::get(*Context, APF);
13436 CV[0] = ConstantFP::get(
13438 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13440 C = ConstantVector::get(CV);
13441 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13443 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13444 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13445 false, false, false, 16);
13446 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13447 if (!isa<ConstantFPSDNode>(Op0)) {
13448 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13449 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13451 // OR the magnitude value with the sign bit.
13452 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13453 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13454 DAG.getIntPtrConstant(0, dl));
13457 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13458 SDValue N0 = Op.getOperand(0);
13460 MVT VT = Op.getSimpleValueType();
13462 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13463 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13464 DAG.getConstant(1, dl, VT));
13465 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13468 // Check whether an OR'd tree is PTEST-able.
13469 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13470 SelectionDAG &DAG) {
13471 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13473 if (!Subtarget->hasSSE41())
13476 if (!Op->hasOneUse())
13479 SDNode *N = Op.getNode();
13482 SmallVector<SDValue, 8> Opnds;
13483 DenseMap<SDValue, unsigned> VecInMap;
13484 SmallVector<SDValue, 8> VecIns;
13485 EVT VT = MVT::Other;
13487 // Recognize a special case where a vector is casted into wide integer to
13489 Opnds.push_back(N->getOperand(0));
13490 Opnds.push_back(N->getOperand(1));
13492 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13493 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13494 // BFS traverse all OR'd operands.
13495 if (I->getOpcode() == ISD::OR) {
13496 Opnds.push_back(I->getOperand(0));
13497 Opnds.push_back(I->getOperand(1));
13498 // Re-evaluate the number of nodes to be traversed.
13499 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13503 // Quit if a non-EXTRACT_VECTOR_ELT
13504 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13507 // Quit if without a constant index.
13508 SDValue Idx = I->getOperand(1);
13509 if (!isa<ConstantSDNode>(Idx))
13512 SDValue ExtractedFromVec = I->getOperand(0);
13513 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13514 if (M == VecInMap.end()) {
13515 VT = ExtractedFromVec.getValueType();
13516 // Quit if not 128/256-bit vector.
13517 if (!VT.is128BitVector() && !VT.is256BitVector())
13519 // Quit if not the same type.
13520 if (VecInMap.begin() != VecInMap.end() &&
13521 VT != VecInMap.begin()->first.getValueType())
13523 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13524 VecIns.push_back(ExtractedFromVec);
13526 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13529 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13530 "Not extracted from 128-/256-bit vector.");
13532 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13534 for (DenseMap<SDValue, unsigned>::const_iterator
13535 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13536 // Quit if not all elements are used.
13537 if (I->second != FullMask)
13541 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13543 // Cast all vectors into TestVT for PTEST.
13544 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13545 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13547 // If more than one full vectors are evaluated, OR them first before PTEST.
13548 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13549 // Each iteration will OR 2 nodes and append the result until there is only
13550 // 1 node left, i.e. the final OR'd value of all vectors.
13551 SDValue LHS = VecIns[Slot];
13552 SDValue RHS = VecIns[Slot + 1];
13553 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13556 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13557 VecIns.back(), VecIns.back());
13560 /// \brief return true if \c Op has a use that doesn't just read flags.
13561 static bool hasNonFlagsUse(SDValue Op) {
13562 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13564 SDNode *User = *UI;
13565 unsigned UOpNo = UI.getOperandNo();
13566 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13567 // Look pass truncate.
13568 UOpNo = User->use_begin().getOperandNo();
13569 User = *User->use_begin();
13572 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13573 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13579 /// Emit nodes that will be selected as "test Op0,Op0", or something
13581 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13582 SelectionDAG &DAG) const {
13583 if (Op.getValueType() == MVT::i1) {
13584 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13585 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13586 DAG.getConstant(0, dl, MVT::i8));
13588 // CF and OF aren't always set the way we want. Determine which
13589 // of these we need.
13590 bool NeedCF = false;
13591 bool NeedOF = false;
13594 case X86::COND_A: case X86::COND_AE:
13595 case X86::COND_B: case X86::COND_BE:
13598 case X86::COND_G: case X86::COND_GE:
13599 case X86::COND_L: case X86::COND_LE:
13600 case X86::COND_O: case X86::COND_NO: {
13601 // Check if we really need to set the
13602 // Overflow flag. If NoSignedWrap is present
13603 // that is not actually needed.
13604 switch (Op->getOpcode()) {
13609 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13610 if (BinNode->Flags.hasNoSignedWrap())
13620 // See if we can use the EFLAGS value from the operand instead of
13621 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13622 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13623 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13624 // Emit a CMP with 0, which is the TEST pattern.
13625 //if (Op.getValueType() == MVT::i1)
13626 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13627 // DAG.getConstant(0, MVT::i1));
13628 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13629 DAG.getConstant(0, dl, Op.getValueType()));
13631 unsigned Opcode = 0;
13632 unsigned NumOperands = 0;
13634 // Truncate operations may prevent the merge of the SETCC instruction
13635 // and the arithmetic instruction before it. Attempt to truncate the operands
13636 // of the arithmetic instruction and use a reduced bit-width instruction.
13637 bool NeedTruncation = false;
13638 SDValue ArithOp = Op;
13639 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13640 SDValue Arith = Op->getOperand(0);
13641 // Both the trunc and the arithmetic op need to have one user each.
13642 if (Arith->hasOneUse())
13643 switch (Arith.getOpcode()) {
13650 NeedTruncation = true;
13656 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13657 // which may be the result of a CAST. We use the variable 'Op', which is the
13658 // non-casted variable when we check for possible users.
13659 switch (ArithOp.getOpcode()) {
13661 // Due to an isel shortcoming, be conservative if this add is likely to be
13662 // selected as part of a load-modify-store instruction. When the root node
13663 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13664 // uses of other nodes in the match, such as the ADD in this case. This
13665 // leads to the ADD being left around and reselected, with the result being
13666 // two adds in the output. Alas, even if none our users are stores, that
13667 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13668 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13669 // climbing the DAG back to the root, and it doesn't seem to be worth the
13671 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13672 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13673 if (UI->getOpcode() != ISD::CopyToReg &&
13674 UI->getOpcode() != ISD::SETCC &&
13675 UI->getOpcode() != ISD::STORE)
13678 if (ConstantSDNode *C =
13679 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13680 // An add of one will be selected as an INC.
13681 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13682 Opcode = X86ISD::INC;
13687 // An add of negative one (subtract of one) will be selected as a DEC.
13688 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13689 Opcode = X86ISD::DEC;
13695 // Otherwise use a regular EFLAGS-setting add.
13696 Opcode = X86ISD::ADD;
13701 // If we have a constant logical shift that's only used in a comparison
13702 // against zero turn it into an equivalent AND. This allows turning it into
13703 // a TEST instruction later.
13704 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13705 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13706 EVT VT = Op.getValueType();
13707 unsigned BitWidth = VT.getSizeInBits();
13708 unsigned ShAmt = Op->getConstantOperandVal(1);
13709 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13711 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13712 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13713 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13714 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13716 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13717 DAG.getConstant(Mask, dl, VT));
13718 DAG.ReplaceAllUsesWith(Op, New);
13724 // If the primary and result isn't used, don't bother using X86ISD::AND,
13725 // because a TEST instruction will be better.
13726 if (!hasNonFlagsUse(Op))
13732 // Due to the ISEL shortcoming noted above, be conservative if this op is
13733 // likely to be selected as part of a load-modify-store instruction.
13734 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13735 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13736 if (UI->getOpcode() == ISD::STORE)
13739 // Otherwise use a regular EFLAGS-setting instruction.
13740 switch (ArithOp.getOpcode()) {
13741 default: llvm_unreachable("unexpected operator!");
13742 case ISD::SUB: Opcode = X86ISD::SUB; break;
13743 case ISD::XOR: Opcode = X86ISD::XOR; break;
13744 case ISD::AND: Opcode = X86ISD::AND; break;
13746 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13747 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13748 if (EFLAGS.getNode())
13751 Opcode = X86ISD::OR;
13765 return SDValue(Op.getNode(), 1);
13771 // If we found that truncation is beneficial, perform the truncation and
13773 if (NeedTruncation) {
13774 EVT VT = Op.getValueType();
13775 SDValue WideVal = Op->getOperand(0);
13776 EVT WideVT = WideVal.getValueType();
13777 unsigned ConvertedOp = 0;
13778 // Use a target machine opcode to prevent further DAGCombine
13779 // optimizations that may separate the arithmetic operations
13780 // from the setcc node.
13781 switch (WideVal.getOpcode()) {
13783 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13784 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13785 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13786 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13787 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13791 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13792 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13793 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13794 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13795 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13801 // Emit a CMP with 0, which is the TEST pattern.
13802 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13803 DAG.getConstant(0, dl, Op.getValueType()));
13805 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13806 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13808 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13809 DAG.ReplaceAllUsesWith(Op, New);
13810 return SDValue(New.getNode(), 1);
13813 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13815 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13816 SDLoc dl, SelectionDAG &DAG) const {
13817 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13818 if (C->getAPIntValue() == 0)
13819 return EmitTest(Op0, X86CC, dl, DAG);
13821 if (Op0.getValueType() == MVT::i1)
13822 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13825 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13826 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13827 // Do the comparison at i32 if it's smaller, besides the Atom case.
13828 // This avoids subregister aliasing issues. Keep the smaller reference
13829 // if we're optimizing for size, however, as that'll allow better folding
13830 // of memory operations.
13831 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13832 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13833 !Subtarget->isAtom()) {
13834 unsigned ExtendOp =
13835 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13836 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13837 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13839 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13840 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13841 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13843 return SDValue(Sub.getNode(), 1);
13845 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13848 /// Convert a comparison if required by the subtarget.
13849 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13850 SelectionDAG &DAG) const {
13851 // If the subtarget does not support the FUCOMI instruction, floating-point
13852 // comparisons have to be converted.
13853 if (Subtarget->hasCMov() ||
13854 Cmp.getOpcode() != X86ISD::CMP ||
13855 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13856 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13859 // The instruction selector will select an FUCOM instruction instead of
13860 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13861 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13862 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13864 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13865 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13866 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13867 DAG.getConstant(8, dl, MVT::i8));
13868 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13869 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13872 /// The minimum architected relative accuracy is 2^-12. We need one
13873 /// Newton-Raphson step to have a good float result (24 bits of precision).
13874 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13875 DAGCombinerInfo &DCI,
13876 unsigned &RefinementSteps,
13877 bool &UseOneConstNR) const {
13878 EVT VT = Op.getValueType();
13879 const char *RecipOp;
13881 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13882 // TODO: Add support for AVX512 (v16f32).
13883 // It is likely not profitable to do this for f64 because a double-precision
13884 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13885 // instructions: convert to single, rsqrtss, convert back to double, refine
13886 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13887 // along with FMA, this could be a throughput win.
13888 if (VT == MVT::f32 && Subtarget->hasSSE1())
13890 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13891 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13892 RecipOp = "vec-sqrtf";
13896 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13897 if (!Recips.isEnabled(RecipOp))
13900 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13901 UseOneConstNR = false;
13902 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13905 /// The minimum architected relative accuracy is 2^-12. We need one
13906 /// Newton-Raphson step to have a good float result (24 bits of precision).
13907 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13908 DAGCombinerInfo &DCI,
13909 unsigned &RefinementSteps) const {
13910 EVT VT = Op.getValueType();
13911 const char *RecipOp;
13913 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13914 // TODO: Add support for AVX512 (v16f32).
13915 // It is likely not profitable to do this for f64 because a double-precision
13916 // reciprocal estimate with refinement on x86 prior to FMA requires
13917 // 15 instructions: convert to single, rcpss, convert back to double, refine
13918 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13919 // along with FMA, this could be a throughput win.
13920 if (VT == MVT::f32 && Subtarget->hasSSE1())
13922 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13923 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13924 RecipOp = "vec-divf";
13928 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13929 if (!Recips.isEnabled(RecipOp))
13932 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13933 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13936 /// If we have at least two divisions that use the same divisor, convert to
13937 /// multplication by a reciprocal. This may need to be adjusted for a given
13938 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13939 /// This is because we still need one division to calculate the reciprocal and
13940 /// then we need two multiplies by that reciprocal as replacements for the
13941 /// original divisions.
13942 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13946 static bool isAllOnes(SDValue V) {
13947 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13948 return C && C->isAllOnesValue();
13951 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13952 /// if it's possible.
13953 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13954 SDLoc dl, SelectionDAG &DAG) const {
13955 SDValue Op0 = And.getOperand(0);
13956 SDValue Op1 = And.getOperand(1);
13957 if (Op0.getOpcode() == ISD::TRUNCATE)
13958 Op0 = Op0.getOperand(0);
13959 if (Op1.getOpcode() == ISD::TRUNCATE)
13960 Op1 = Op1.getOperand(0);
13963 if (Op1.getOpcode() == ISD::SHL)
13964 std::swap(Op0, Op1);
13965 if (Op0.getOpcode() == ISD::SHL) {
13966 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13967 if (And00C->getZExtValue() == 1) {
13968 // If we looked past a truncate, check that it's only truncating away
13970 unsigned BitWidth = Op0.getValueSizeInBits();
13971 unsigned AndBitWidth = And.getValueSizeInBits();
13972 if (BitWidth > AndBitWidth) {
13974 DAG.computeKnownBits(Op0, Zeros, Ones);
13975 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13979 RHS = Op0.getOperand(1);
13981 } else if (Op1.getOpcode() == ISD::Constant) {
13982 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13983 uint64_t AndRHSVal = AndRHS->getZExtValue();
13984 SDValue AndLHS = Op0;
13986 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13987 LHS = AndLHS.getOperand(0);
13988 RHS = AndLHS.getOperand(1);
13991 // Use BT if the immediate can't be encoded in a TEST instruction.
13992 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13994 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13998 if (LHS.getNode()) {
13999 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14000 // instruction. Since the shift amount is in-range-or-undefined, we know
14001 // that doing a bittest on the i32 value is ok. We extend to i32 because
14002 // the encoding for the i16 version is larger than the i32 version.
14003 // Also promote i16 to i32 for performance / code size reason.
14004 if (LHS.getValueType() == MVT::i8 ||
14005 LHS.getValueType() == MVT::i16)
14006 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14008 // If the operand types disagree, extend the shift amount to match. Since
14009 // BT ignores high bits (like shifts) we can use anyextend.
14010 if (LHS.getValueType() != RHS.getValueType())
14011 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14013 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14014 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14015 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14016 DAG.getConstant(Cond, dl, MVT::i8), BT);
14022 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14024 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14029 // SSE Condition code mapping:
14038 switch (SetCCOpcode) {
14039 default: llvm_unreachable("Unexpected SETCC condition");
14041 case ISD::SETEQ: SSECC = 0; break;
14043 case ISD::SETGT: Swap = true; // Fallthrough
14045 case ISD::SETOLT: SSECC = 1; break;
14047 case ISD::SETGE: Swap = true; // Fallthrough
14049 case ISD::SETOLE: SSECC = 2; break;
14050 case ISD::SETUO: SSECC = 3; break;
14052 case ISD::SETNE: SSECC = 4; break;
14053 case ISD::SETULE: Swap = true; // Fallthrough
14054 case ISD::SETUGE: SSECC = 5; break;
14055 case ISD::SETULT: Swap = true; // Fallthrough
14056 case ISD::SETUGT: SSECC = 6; break;
14057 case ISD::SETO: SSECC = 7; break;
14059 case ISD::SETONE: SSECC = 8; break;
14062 std::swap(Op0, Op1);
14067 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14068 // ones, and then concatenate the result back.
14069 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14070 MVT VT = Op.getSimpleValueType();
14072 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14073 "Unsupported value type for operation");
14075 unsigned NumElems = VT.getVectorNumElements();
14077 SDValue CC = Op.getOperand(2);
14079 // Extract the LHS vectors
14080 SDValue LHS = Op.getOperand(0);
14081 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14082 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14084 // Extract the RHS vectors
14085 SDValue RHS = Op.getOperand(1);
14086 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14087 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14089 // Issue the operation on the smaller types and concatenate the result back
14090 MVT EltVT = VT.getVectorElementType();
14091 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14092 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14093 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14094 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14097 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14098 SDValue Op0 = Op.getOperand(0);
14099 SDValue Op1 = Op.getOperand(1);
14100 SDValue CC = Op.getOperand(2);
14101 MVT VT = Op.getSimpleValueType();
14104 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
14105 "Unexpected type for boolean compare operation");
14106 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14107 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14108 DAG.getConstant(-1, dl, VT));
14109 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14110 DAG.getConstant(-1, dl, VT));
14111 switch (SetCCOpcode) {
14112 default: llvm_unreachable("Unexpected SETCC condition");
14114 // (x == y) -> ~(x ^ y)
14115 return DAG.getNode(ISD::XOR, dl, VT,
14116 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14117 DAG.getConstant(-1, dl, VT));
14119 // (x != y) -> (x ^ y)
14120 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14123 // (x > y) -> (x & ~y)
14124 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14127 // (x < y) -> (~x & y)
14128 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14131 // (x <= y) -> (~x | y)
14132 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14135 // (x >=y) -> (x | ~y)
14136 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14140 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14141 const X86Subtarget *Subtarget) {
14142 SDValue Op0 = Op.getOperand(0);
14143 SDValue Op1 = Op.getOperand(1);
14144 SDValue CC = Op.getOperand(2);
14145 MVT VT = Op.getSimpleValueType();
14148 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14149 Op.getValueType().getScalarType() == MVT::i1 &&
14150 "Cannot set masked compare for this operation");
14152 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14154 bool Unsigned = false;
14157 switch (SetCCOpcode) {
14158 default: llvm_unreachable("Unexpected SETCC condition");
14159 case ISD::SETNE: SSECC = 4; break;
14160 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14161 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14162 case ISD::SETLT: Swap = true; //fall-through
14163 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14164 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14165 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14166 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14167 case ISD::SETULE: Unsigned = true; //fall-through
14168 case ISD::SETLE: SSECC = 2; break;
14172 std::swap(Op0, Op1);
14174 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14175 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14176 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14177 DAG.getConstant(SSECC, dl, MVT::i8));
14180 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14181 /// operand \p Op1. If non-trivial (for example because it's not constant)
14182 /// return an empty value.
14183 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14185 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14189 MVT VT = Op1.getSimpleValueType();
14190 MVT EVT = VT.getVectorElementType();
14191 unsigned n = VT.getVectorNumElements();
14192 SmallVector<SDValue, 8> ULTOp1;
14194 for (unsigned i = 0; i < n; ++i) {
14195 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14196 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14199 // Avoid underflow.
14200 APInt Val = Elt->getAPIntValue();
14204 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14207 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14210 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14211 SelectionDAG &DAG) {
14212 SDValue Op0 = Op.getOperand(0);
14213 SDValue Op1 = Op.getOperand(1);
14214 SDValue CC = Op.getOperand(2);
14215 MVT VT = Op.getSimpleValueType();
14216 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14217 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14222 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14223 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14226 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14227 unsigned Opc = X86ISD::CMPP;
14228 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14229 assert(VT.getVectorNumElements() <= 16);
14230 Opc = X86ISD::CMPM;
14232 // In the two special cases we can't handle, emit two comparisons.
14235 unsigned CombineOpc;
14236 if (SetCCOpcode == ISD::SETUEQ) {
14237 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14239 assert(SetCCOpcode == ISD::SETONE);
14240 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14243 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14244 DAG.getConstant(CC0, dl, MVT::i8));
14245 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14246 DAG.getConstant(CC1, dl, MVT::i8));
14247 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14249 // Handle all other FP comparisons here.
14250 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14251 DAG.getConstant(SSECC, dl, MVT::i8));
14254 MVT VTOp0 = Op0.getSimpleValueType();
14255 assert(VTOp0 == Op1.getSimpleValueType() &&
14256 "Expected operands with same type!");
14257 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14258 "Invalid number of packed elements for source and destination!");
14260 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14261 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14262 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14263 // legalizer firstly checks if the first operand in input to the setcc has
14264 // a legal type. If so, then it promotes the return type to that same type.
14265 // Otherwise, the return type is promoted to the 'next legal type' which,
14266 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14268 // We reach this code only if the following two conditions are met:
14269 // 1. Both return type and operand type have been promoted to wider types
14270 // by the type legalizer.
14271 // 2. The original operand type has been promoted to a 256-bit vector.
14273 // Note that condition 2. only applies for AVX targets.
14274 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14275 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14278 // The non-AVX512 code below works under the assumption that source and
14279 // destination types are the same.
14280 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14281 "Value types for source and destination must be the same!");
14283 // Break 256-bit integer vector compare into smaller ones.
14284 if (VT.is256BitVector() && !Subtarget->hasInt256())
14285 return Lower256IntVSETCC(Op, DAG);
14287 EVT OpVT = Op1.getValueType();
14288 if (OpVT.getVectorElementType() == MVT::i1)
14289 return LowerBoolVSETCC_AVX512(Op, DAG);
14291 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14292 if (Subtarget->hasAVX512()) {
14293 if (Op1.getValueType().is512BitVector() ||
14294 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14295 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14296 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14298 // In AVX-512 architecture setcc returns mask with i1 elements,
14299 // But there is no compare instruction for i8 and i16 elements in KNL.
14300 // We are not talking about 512-bit operands in this case, these
14301 // types are illegal.
14303 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14304 OpVT.getVectorElementType().getSizeInBits() >= 8))
14305 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14306 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14309 // Lower using XOP integer comparisons.
14310 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14311 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14312 // Translate compare code to XOP PCOM compare mode.
14313 unsigned CmpMode = 0;
14314 switch (SetCCOpcode) {
14315 default: llvm_unreachable("Unexpected SETCC condition");
14317 case ISD::SETLT: CmpMode = 0x00; break;
14319 case ISD::SETLE: CmpMode = 0x01; break;
14321 case ISD::SETGT: CmpMode = 0x02; break;
14323 case ISD::SETGE: CmpMode = 0x03; break;
14324 case ISD::SETEQ: CmpMode = 0x04; break;
14325 case ISD::SETNE: CmpMode = 0x05; break;
14328 // Are we comparing unsigned or signed integers?
14329 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14330 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14332 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14333 DAG.getConstant(CmpMode, dl, MVT::i8));
14336 // We are handling one of the integer comparisons here. Since SSE only has
14337 // GT and EQ comparisons for integer, swapping operands and multiple
14338 // operations may be required for some comparisons.
14340 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14341 bool Subus = false;
14343 switch (SetCCOpcode) {
14344 default: llvm_unreachable("Unexpected SETCC condition");
14345 case ISD::SETNE: Invert = true;
14346 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14347 case ISD::SETLT: Swap = true;
14348 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14349 case ISD::SETGE: Swap = true;
14350 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14351 Invert = true; break;
14352 case ISD::SETULT: Swap = true;
14353 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14354 FlipSigns = true; break;
14355 case ISD::SETUGE: Swap = true;
14356 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14357 FlipSigns = true; Invert = true; break;
14360 // Special case: Use min/max operations for SETULE/SETUGE
14361 MVT VET = VT.getVectorElementType();
14363 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14364 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14367 switch (SetCCOpcode) {
14369 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14370 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14373 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14376 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14377 if (!MinMax && hasSubus) {
14378 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14380 // t = psubus Op0, Op1
14381 // pcmpeq t, <0..0>
14382 switch (SetCCOpcode) {
14384 case ISD::SETULT: {
14385 // If the comparison is against a constant we can turn this into a
14386 // setule. With psubus, setule does not require a swap. This is
14387 // beneficial because the constant in the register is no longer
14388 // destructed as the destination so it can be hoisted out of a loop.
14389 // Only do this pre-AVX since vpcmp* is no longer destructive.
14390 if (Subtarget->hasAVX())
14392 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14393 if (ULEOp1.getNode()) {
14395 Subus = true; Invert = false; Swap = false;
14399 // Psubus is better than flip-sign because it requires no inversion.
14400 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14401 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14405 Opc = X86ISD::SUBUS;
14411 std::swap(Op0, Op1);
14413 // Check that the operation in question is available (most are plain SSE2,
14414 // but PCMPGTQ and PCMPEQQ have different requirements).
14415 if (VT == MVT::v2i64) {
14416 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14417 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14419 // First cast everything to the right type.
14420 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14421 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14423 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14424 // bits of the inputs before performing those operations. The lower
14425 // compare is always unsigned.
14428 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14430 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14431 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14432 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14433 Sign, Zero, Sign, Zero);
14435 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14436 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14438 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14439 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14440 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14442 // Create masks for only the low parts/high parts of the 64 bit integers.
14443 static const int MaskHi[] = { 1, 1, 3, 3 };
14444 static const int MaskLo[] = { 0, 0, 2, 2 };
14445 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14446 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14447 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14449 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14450 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14453 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14455 return DAG.getBitcast(VT, Result);
14458 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14459 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14460 // pcmpeqd + pshufd + pand.
14461 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14463 // First cast everything to the right type.
14464 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14465 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14468 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14470 // Make sure the lower and upper halves are both all-ones.
14471 static const int Mask[] = { 1, 0, 3, 2 };
14472 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14473 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14476 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14478 return DAG.getBitcast(VT, Result);
14482 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14483 // bits of the inputs before performing those operations.
14485 EVT EltVT = VT.getVectorElementType();
14486 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14488 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14489 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14492 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14494 // If the logical-not of the result is required, perform that now.
14496 Result = DAG.getNOT(dl, Result, VT);
14499 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14502 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14503 getZeroVector(VT, Subtarget, DAG, dl));
14508 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14510 MVT VT = Op.getSimpleValueType();
14512 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14514 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14515 && "SetCC type must be 8-bit or 1-bit integer");
14516 SDValue Op0 = Op.getOperand(0);
14517 SDValue Op1 = Op.getOperand(1);
14519 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14521 // Optimize to BT if possible.
14522 // Lower (X & (1 << N)) == 0 to BT(X, N).
14523 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14524 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14525 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14526 Op1.getOpcode() == ISD::Constant &&
14527 cast<ConstantSDNode>(Op1)->isNullValue() &&
14528 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14529 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14530 if (NewSetCC.getNode()) {
14532 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14537 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14539 if (Op1.getOpcode() == ISD::Constant &&
14540 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14541 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14542 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14544 // If the input is a setcc, then reuse the input setcc or use a new one with
14545 // the inverted condition.
14546 if (Op0.getOpcode() == X86ISD::SETCC) {
14547 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14548 bool Invert = (CC == ISD::SETNE) ^
14549 cast<ConstantSDNode>(Op1)->isNullValue();
14553 CCode = X86::GetOppositeBranchCondition(CCode);
14554 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14555 DAG.getConstant(CCode, dl, MVT::i8),
14556 Op0.getOperand(1));
14558 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14562 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14563 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14564 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14566 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14567 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14570 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14571 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14572 if (X86CC == X86::COND_INVALID)
14575 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14576 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14577 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14578 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14580 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14584 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14585 static bool isX86LogicalCmp(SDValue Op) {
14586 unsigned Opc = Op.getNode()->getOpcode();
14587 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14588 Opc == X86ISD::SAHF)
14590 if (Op.getResNo() == 1 &&
14591 (Opc == X86ISD::ADD ||
14592 Opc == X86ISD::SUB ||
14593 Opc == X86ISD::ADC ||
14594 Opc == X86ISD::SBB ||
14595 Opc == X86ISD::SMUL ||
14596 Opc == X86ISD::UMUL ||
14597 Opc == X86ISD::INC ||
14598 Opc == X86ISD::DEC ||
14599 Opc == X86ISD::OR ||
14600 Opc == X86ISD::XOR ||
14601 Opc == X86ISD::AND))
14604 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14610 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14611 if (V.getOpcode() != ISD::TRUNCATE)
14614 SDValue VOp0 = V.getOperand(0);
14615 unsigned InBits = VOp0.getValueSizeInBits();
14616 unsigned Bits = V.getValueSizeInBits();
14617 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14620 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14621 bool addTest = true;
14622 SDValue Cond = Op.getOperand(0);
14623 SDValue Op1 = Op.getOperand(1);
14624 SDValue Op2 = Op.getOperand(2);
14626 EVT VT = Op1.getValueType();
14629 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14630 // are available or VBLENDV if AVX is available.
14631 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14632 if (Cond.getOpcode() == ISD::SETCC &&
14633 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14634 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14635 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14636 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14637 int SSECC = translateX86FSETCC(
14638 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14641 if (Subtarget->hasAVX512()) {
14642 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14643 DAG.getConstant(SSECC, DL, MVT::i8));
14644 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14647 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14648 DAG.getConstant(SSECC, DL, MVT::i8));
14650 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14651 // of 3 logic instructions for size savings and potentially speed.
14652 // Unfortunately, there is no scalar form of VBLENDV.
14654 // If either operand is a constant, don't try this. We can expect to
14655 // optimize away at least one of the logic instructions later in that
14656 // case, so that sequence would be faster than a variable blend.
14658 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14659 // uses XMM0 as the selection register. That may need just as many
14660 // instructions as the AND/ANDN/OR sequence due to register moves, so
14663 if (Subtarget->hasAVX() &&
14664 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14666 // Convert to vectors, do a VSELECT, and convert back to scalar.
14667 // All of the conversions should be optimized away.
14669 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14670 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14671 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14672 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14674 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14675 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14677 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14679 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14680 VSel, DAG.getIntPtrConstant(0, DL));
14682 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14683 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14684 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14688 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
14690 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14691 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14692 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14693 Op1Scalar = Op1.getOperand(0);
14695 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14696 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14697 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14698 Op2Scalar = Op2.getOperand(0);
14699 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14700 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14701 Op1Scalar.getValueType(),
14702 Cond, Op1Scalar, Op2Scalar);
14703 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14704 return DAG.getBitcast(VT, newSelect);
14705 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14706 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14707 DAG.getIntPtrConstant(0, DL));
14711 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14712 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14713 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14714 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14715 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14716 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14717 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14719 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14722 if (Cond.getOpcode() == ISD::SETCC) {
14723 SDValue NewCond = LowerSETCC(Cond, DAG);
14724 if (NewCond.getNode())
14728 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14729 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14730 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14731 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14732 if (Cond.getOpcode() == X86ISD::SETCC &&
14733 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14734 isZero(Cond.getOperand(1).getOperand(1))) {
14735 SDValue Cmp = Cond.getOperand(1);
14737 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14739 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14740 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14741 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14743 SDValue CmpOp0 = Cmp.getOperand(0);
14744 // Apply further optimizations for special cases
14745 // (select (x != 0), -1, 0) -> neg & sbb
14746 // (select (x == 0), 0, -1) -> neg & sbb
14747 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14748 if (YC->isNullValue() &&
14749 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14750 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14751 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14752 DAG.getConstant(0, DL,
14753 CmpOp0.getValueType()),
14755 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14756 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14757 SDValue(Neg.getNode(), 1));
14761 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14762 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14763 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14765 SDValue Res = // Res = 0 or -1.
14766 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14767 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14769 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14770 Res = DAG.getNOT(DL, Res, Res.getValueType());
14772 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14773 if (!N2C || !N2C->isNullValue())
14774 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14779 // Look past (and (setcc_carry (cmp ...)), 1).
14780 if (Cond.getOpcode() == ISD::AND &&
14781 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14782 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14783 if (C && C->getAPIntValue() == 1)
14784 Cond = Cond.getOperand(0);
14787 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14788 // setting operand in place of the X86ISD::SETCC.
14789 unsigned CondOpcode = Cond.getOpcode();
14790 if (CondOpcode == X86ISD::SETCC ||
14791 CondOpcode == X86ISD::SETCC_CARRY) {
14792 CC = Cond.getOperand(0);
14794 SDValue Cmp = Cond.getOperand(1);
14795 unsigned Opc = Cmp.getOpcode();
14796 MVT VT = Op.getSimpleValueType();
14798 bool IllegalFPCMov = false;
14799 if (VT.isFloatingPoint() && !VT.isVector() &&
14800 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14801 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14803 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14804 Opc == X86ISD::BT) { // FIXME
14808 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14809 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14810 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14811 Cond.getOperand(0).getValueType() != MVT::i8)) {
14812 SDValue LHS = Cond.getOperand(0);
14813 SDValue RHS = Cond.getOperand(1);
14814 unsigned X86Opcode;
14817 switch (CondOpcode) {
14818 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14819 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14820 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14821 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14822 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14823 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14824 default: llvm_unreachable("unexpected overflowing operator");
14826 if (CondOpcode == ISD::UMULO)
14827 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14830 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14832 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14834 if (CondOpcode == ISD::UMULO)
14835 Cond = X86Op.getValue(2);
14837 Cond = X86Op.getValue(1);
14839 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14844 // Look past the truncate if the high bits are known zero.
14845 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14846 Cond = Cond.getOperand(0);
14848 // We know the result of AND is compared against zero. Try to match
14850 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14851 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14852 if (NewSetCC.getNode()) {
14853 CC = NewSetCC.getOperand(0);
14854 Cond = NewSetCC.getOperand(1);
14861 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14862 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14865 // a < b ? -1 : 0 -> RES = ~setcc_carry
14866 // a < b ? 0 : -1 -> RES = setcc_carry
14867 // a >= b ? -1 : 0 -> RES = setcc_carry
14868 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14869 if (Cond.getOpcode() == X86ISD::SUB) {
14870 Cond = ConvertCmpIfNecessary(Cond, DAG);
14871 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14873 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14874 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14875 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14876 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14878 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14879 return DAG.getNOT(DL, Res, Res.getValueType());
14884 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14885 // widen the cmov and push the truncate through. This avoids introducing a new
14886 // branch during isel and doesn't add any extensions.
14887 if (Op.getValueType() == MVT::i8 &&
14888 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14889 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14890 if (T1.getValueType() == T2.getValueType() &&
14891 // Blacklist CopyFromReg to avoid partial register stalls.
14892 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14893 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14894 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14895 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14899 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14900 // condition is true.
14901 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14902 SDValue Ops[] = { Op2, Op1, CC, Cond };
14903 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14906 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14907 const X86Subtarget *Subtarget,
14908 SelectionDAG &DAG) {
14909 MVT VT = Op->getSimpleValueType(0);
14910 SDValue In = Op->getOperand(0);
14911 MVT InVT = In.getSimpleValueType();
14912 MVT VTElt = VT.getVectorElementType();
14913 MVT InVTElt = InVT.getVectorElementType();
14917 if ((InVTElt == MVT::i1) &&
14918 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14919 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14921 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14922 VTElt.getSizeInBits() <= 16)) ||
14924 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14925 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14927 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14928 VTElt.getSizeInBits() >= 32))))
14929 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14931 unsigned int NumElts = VT.getVectorNumElements();
14933 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14936 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14937 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14938 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14939 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14942 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14943 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14945 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14948 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14950 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14951 if (VT.is512BitVector())
14953 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14956 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14957 const X86Subtarget *Subtarget,
14958 SelectionDAG &DAG) {
14959 SDValue In = Op->getOperand(0);
14960 MVT VT = Op->getSimpleValueType(0);
14961 MVT InVT = In.getSimpleValueType();
14962 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14964 MVT InSVT = InVT.getScalarType();
14965 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14967 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14969 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14974 // SSE41 targets can use the pmovsx* instructions directly.
14975 if (Subtarget->hasSSE41())
14976 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14978 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14982 // As SRAI is only available on i16/i32 types, we expand only up to i32
14983 // and handle i64 separately.
14984 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14985 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14986 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14987 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14988 Curr = DAG.getBitcast(CurrVT, Curr);
14991 SDValue SignExt = Curr;
14992 if (CurrVT != InVT) {
14993 unsigned SignExtShift =
14994 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14995 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14996 DAG.getConstant(SignExtShift, dl, MVT::i8));
15002 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
15003 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15004 DAG.getConstant(31, dl, MVT::i8));
15005 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
15006 return DAG.getBitcast(VT, Ext);
15012 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15013 SelectionDAG &DAG) {
15014 MVT VT = Op->getSimpleValueType(0);
15015 SDValue In = Op->getOperand(0);
15016 MVT InVT = In.getSimpleValueType();
15019 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15020 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15022 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15023 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15024 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15027 if (Subtarget->hasInt256())
15028 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15030 // Optimize vectors in AVX mode
15031 // Sign extend v8i16 to v8i32 and
15034 // Divide input vector into two parts
15035 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15036 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15037 // concat the vectors to original VT
15039 unsigned NumElems = InVT.getVectorNumElements();
15040 SDValue Undef = DAG.getUNDEF(InVT);
15042 SmallVector<int,8> ShufMask1(NumElems, -1);
15043 for (unsigned i = 0; i != NumElems/2; ++i)
15046 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15048 SmallVector<int,8> ShufMask2(NumElems, -1);
15049 for (unsigned i = 0; i != NumElems/2; ++i)
15050 ShufMask2[i] = i + NumElems/2;
15052 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15054 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15055 VT.getVectorNumElements()/2);
15057 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15058 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15060 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15063 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15064 // may emit an illegal shuffle but the expansion is still better than scalar
15065 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15066 // we'll emit a shuffle and a arithmetic shift.
15067 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15068 // TODO: It is possible to support ZExt by zeroing the undef values during
15069 // the shuffle phase or after the shuffle.
15070 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15071 SelectionDAG &DAG) {
15072 MVT RegVT = Op.getSimpleValueType();
15073 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15074 assert(RegVT.isInteger() &&
15075 "We only custom lower integer vector sext loads.");
15077 // Nothing useful we can do without SSE2 shuffles.
15078 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15080 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15082 EVT MemVT = Ld->getMemoryVT();
15083 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15084 unsigned RegSz = RegVT.getSizeInBits();
15086 ISD::LoadExtType Ext = Ld->getExtensionType();
15088 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15089 && "Only anyext and sext are currently implemented.");
15090 assert(MemVT != RegVT && "Cannot extend to the same type");
15091 assert(MemVT.isVector() && "Must load a vector from memory");
15093 unsigned NumElems = RegVT.getVectorNumElements();
15094 unsigned MemSz = MemVT.getSizeInBits();
15095 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15097 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15098 // The only way in which we have a legal 256-bit vector result but not the
15099 // integer 256-bit operations needed to directly lower a sextload is if we
15100 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15101 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15102 // correctly legalized. We do this late to allow the canonical form of
15103 // sextload to persist throughout the rest of the DAG combiner -- it wants
15104 // to fold together any extensions it can, and so will fuse a sign_extend
15105 // of an sextload into a sextload targeting a wider value.
15107 if (MemSz == 128) {
15108 // Just switch this to a normal load.
15109 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15110 "it must be a legal 128-bit vector "
15112 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15113 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15114 Ld->isInvariant(), Ld->getAlignment());
15116 assert(MemSz < 128 &&
15117 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15118 // Do an sext load to a 128-bit vector type. We want to use the same
15119 // number of elements, but elements half as wide. This will end up being
15120 // recursively lowered by this routine, but will succeed as we definitely
15121 // have all the necessary features if we're using AVX1.
15123 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15124 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15126 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15127 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15128 Ld->isNonTemporal(), Ld->isInvariant(),
15129 Ld->getAlignment());
15132 // Replace chain users with the new chain.
15133 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15134 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15136 // Finally, do a normal sign-extend to the desired register.
15137 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15140 // All sizes must be a power of two.
15141 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15142 "Non-power-of-two elements are not custom lowered!");
15144 // Attempt to load the original value using scalar loads.
15145 // Find the largest scalar type that divides the total loaded size.
15146 MVT SclrLoadTy = MVT::i8;
15147 for (MVT Tp : MVT::integer_valuetypes()) {
15148 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15153 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15154 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15156 SclrLoadTy = MVT::f64;
15158 // Calculate the number of scalar loads that we need to perform
15159 // in order to load our vector from memory.
15160 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15162 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15163 "Can only lower sext loads with a single scalar load!");
15165 unsigned loadRegZize = RegSz;
15166 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15169 // Represent our vector as a sequence of elements which are the
15170 // largest scalar that we can load.
15171 EVT LoadUnitVecVT = EVT::getVectorVT(
15172 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15174 // Represent the data using the same element type that is stored in
15175 // memory. In practice, we ''widen'' MemVT.
15177 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15178 loadRegZize / MemVT.getScalarType().getSizeInBits());
15180 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15181 "Invalid vector type");
15183 // We can't shuffle using an illegal type.
15184 assert(TLI.isTypeLegal(WideVecVT) &&
15185 "We only lower types that form legal widened vector types");
15187 SmallVector<SDValue, 8> Chains;
15188 SDValue Ptr = Ld->getBasePtr();
15189 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15190 TLI.getPointerTy(DAG.getDataLayout()));
15191 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15193 for (unsigned i = 0; i < NumLoads; ++i) {
15194 // Perform a single load.
15195 SDValue ScalarLoad =
15196 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15197 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15198 Ld->getAlignment());
15199 Chains.push_back(ScalarLoad.getValue(1));
15200 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15201 // another round of DAGCombining.
15203 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15205 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15206 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15208 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15211 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15213 // Bitcast the loaded value to a vector of the original element type, in
15214 // the size of the target vector type.
15215 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15216 unsigned SizeRatio = RegSz / MemSz;
15218 if (Ext == ISD::SEXTLOAD) {
15219 // If we have SSE4.1, we can directly emit a VSEXT node.
15220 if (Subtarget->hasSSE41()) {
15221 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15222 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15226 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15228 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15229 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15231 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15232 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15236 // Redistribute the loaded elements into the different locations.
15237 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15238 for (unsigned i = 0; i != NumElems; ++i)
15239 ShuffleVec[i * SizeRatio] = i;
15241 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15242 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15244 // Bitcast to the requested type.
15245 Shuff = DAG.getBitcast(RegVT, Shuff);
15246 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15250 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15251 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15252 // from the AND / OR.
15253 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15254 Opc = Op.getOpcode();
15255 if (Opc != ISD::OR && Opc != ISD::AND)
15257 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15258 Op.getOperand(0).hasOneUse() &&
15259 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15260 Op.getOperand(1).hasOneUse());
15263 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15264 // 1 and that the SETCC node has a single use.
15265 static bool isXor1OfSetCC(SDValue Op) {
15266 if (Op.getOpcode() != ISD::XOR)
15268 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15269 if (N1C && N1C->getAPIntValue() == 1) {
15270 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15271 Op.getOperand(0).hasOneUse();
15276 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15277 bool addTest = true;
15278 SDValue Chain = Op.getOperand(0);
15279 SDValue Cond = Op.getOperand(1);
15280 SDValue Dest = Op.getOperand(2);
15283 bool Inverted = false;
15285 if (Cond.getOpcode() == ISD::SETCC) {
15286 // Check for setcc([su]{add,sub,mul}o == 0).
15287 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15288 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15289 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15290 Cond.getOperand(0).getResNo() == 1 &&
15291 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15292 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15293 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15294 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15295 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15296 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15298 Cond = Cond.getOperand(0);
15300 SDValue NewCond = LowerSETCC(Cond, DAG);
15301 if (NewCond.getNode())
15306 // FIXME: LowerXALUO doesn't handle these!!
15307 else if (Cond.getOpcode() == X86ISD::ADD ||
15308 Cond.getOpcode() == X86ISD::SUB ||
15309 Cond.getOpcode() == X86ISD::SMUL ||
15310 Cond.getOpcode() == X86ISD::UMUL)
15311 Cond = LowerXALUO(Cond, DAG);
15314 // Look pass (and (setcc_carry (cmp ...)), 1).
15315 if (Cond.getOpcode() == ISD::AND &&
15316 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15317 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15318 if (C && C->getAPIntValue() == 1)
15319 Cond = Cond.getOperand(0);
15322 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15323 // setting operand in place of the X86ISD::SETCC.
15324 unsigned CondOpcode = Cond.getOpcode();
15325 if (CondOpcode == X86ISD::SETCC ||
15326 CondOpcode == X86ISD::SETCC_CARRY) {
15327 CC = Cond.getOperand(0);
15329 SDValue Cmp = Cond.getOperand(1);
15330 unsigned Opc = Cmp.getOpcode();
15331 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15332 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15336 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15340 // These can only come from an arithmetic instruction with overflow,
15341 // e.g. SADDO, UADDO.
15342 Cond = Cond.getNode()->getOperand(1);
15348 CondOpcode = Cond.getOpcode();
15349 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15350 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15351 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15352 Cond.getOperand(0).getValueType() != MVT::i8)) {
15353 SDValue LHS = Cond.getOperand(0);
15354 SDValue RHS = Cond.getOperand(1);
15355 unsigned X86Opcode;
15358 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15359 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15361 switch (CondOpcode) {
15362 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15364 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15366 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15369 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15370 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15372 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15374 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15377 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15378 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15379 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15380 default: llvm_unreachable("unexpected overflowing operator");
15383 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15384 if (CondOpcode == ISD::UMULO)
15385 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15388 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15390 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15392 if (CondOpcode == ISD::UMULO)
15393 Cond = X86Op.getValue(2);
15395 Cond = X86Op.getValue(1);
15397 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15401 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15402 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15403 if (CondOpc == ISD::OR) {
15404 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15405 // two branches instead of an explicit OR instruction with a
15407 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15408 isX86LogicalCmp(Cmp)) {
15409 CC = Cond.getOperand(0).getOperand(0);
15410 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15411 Chain, Dest, CC, Cmp);
15412 CC = Cond.getOperand(1).getOperand(0);
15416 } else { // ISD::AND
15417 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15418 // two branches instead of an explicit AND instruction with a
15419 // separate test. However, we only do this if this block doesn't
15420 // have a fall-through edge, because this requires an explicit
15421 // jmp when the condition is false.
15422 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15423 isX86LogicalCmp(Cmp) &&
15424 Op.getNode()->hasOneUse()) {
15425 X86::CondCode CCode =
15426 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15427 CCode = X86::GetOppositeBranchCondition(CCode);
15428 CC = DAG.getConstant(CCode, dl, MVT::i8);
15429 SDNode *User = *Op.getNode()->use_begin();
15430 // Look for an unconditional branch following this conditional branch.
15431 // We need this because we need to reverse the successors in order
15432 // to implement FCMP_OEQ.
15433 if (User->getOpcode() == ISD::BR) {
15434 SDValue FalseBB = User->getOperand(1);
15436 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15437 assert(NewBR == User);
15441 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15442 Chain, Dest, CC, Cmp);
15443 X86::CondCode CCode =
15444 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15445 CCode = X86::GetOppositeBranchCondition(CCode);
15446 CC = DAG.getConstant(CCode, dl, MVT::i8);
15452 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15453 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15454 // It should be transformed during dag combiner except when the condition
15455 // is set by a arithmetics with overflow node.
15456 X86::CondCode CCode =
15457 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15458 CCode = X86::GetOppositeBranchCondition(CCode);
15459 CC = DAG.getConstant(CCode, dl, MVT::i8);
15460 Cond = Cond.getOperand(0).getOperand(1);
15462 } else if (Cond.getOpcode() == ISD::SETCC &&
15463 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15464 // For FCMP_OEQ, we can emit
15465 // two branches instead of an explicit AND instruction with a
15466 // separate test. However, we only do this if this block doesn't
15467 // have a fall-through edge, because this requires an explicit
15468 // jmp when the condition is false.
15469 if (Op.getNode()->hasOneUse()) {
15470 SDNode *User = *Op.getNode()->use_begin();
15471 // Look for an unconditional branch following this conditional branch.
15472 // We need this because we need to reverse the successors in order
15473 // to implement FCMP_OEQ.
15474 if (User->getOpcode() == ISD::BR) {
15475 SDValue FalseBB = User->getOperand(1);
15477 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15478 assert(NewBR == User);
15482 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15483 Cond.getOperand(0), Cond.getOperand(1));
15484 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15485 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15486 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15487 Chain, Dest, CC, Cmp);
15488 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15493 } else if (Cond.getOpcode() == ISD::SETCC &&
15494 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15495 // For FCMP_UNE, we can emit
15496 // two branches instead of an explicit AND instruction with a
15497 // separate test. However, we only do this if this block doesn't
15498 // have a fall-through edge, because this requires an explicit
15499 // jmp when the condition is false.
15500 if (Op.getNode()->hasOneUse()) {
15501 SDNode *User = *Op.getNode()->use_begin();
15502 // Look for an unconditional branch following this conditional branch.
15503 // We need this because we need to reverse the successors in order
15504 // to implement FCMP_UNE.
15505 if (User->getOpcode() == ISD::BR) {
15506 SDValue FalseBB = User->getOperand(1);
15508 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15509 assert(NewBR == User);
15512 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15513 Cond.getOperand(0), Cond.getOperand(1));
15514 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15515 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15516 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15517 Chain, Dest, CC, Cmp);
15518 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15528 // Look pass the truncate if the high bits are known zero.
15529 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15530 Cond = Cond.getOperand(0);
15532 // We know the result of AND is compared against zero. Try to match
15534 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15535 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15536 if (NewSetCC.getNode()) {
15537 CC = NewSetCC.getOperand(0);
15538 Cond = NewSetCC.getOperand(1);
15545 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15546 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15547 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15549 Cond = ConvertCmpIfNecessary(Cond, DAG);
15550 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15551 Chain, Dest, CC, Cond);
15554 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15555 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15556 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15557 // that the guard pages used by the OS virtual memory manager are allocated in
15558 // correct sequence.
15560 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15561 SelectionDAG &DAG) const {
15562 MachineFunction &MF = DAG.getMachineFunction();
15563 bool SplitStack = MF.shouldSplitStack();
15564 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15569 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15570 SDNode* Node = Op.getNode();
15572 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15573 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15574 " not tell us which reg is the stack pointer!");
15575 EVT VT = Node->getValueType(0);
15576 SDValue Tmp1 = SDValue(Node, 0);
15577 SDValue Tmp2 = SDValue(Node, 1);
15578 SDValue Tmp3 = Node->getOperand(2);
15579 SDValue Chain = Tmp1.getOperand(0);
15581 // Chain the dynamic stack allocation so that it doesn't modify the stack
15582 // pointer when other instructions are using the stack.
15583 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15586 SDValue Size = Tmp2.getOperand(1);
15587 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15588 Chain = SP.getValue(1);
15589 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15590 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15591 unsigned StackAlign = TFI.getStackAlignment();
15592 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15593 if (Align > StackAlign)
15594 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15595 DAG.getConstant(-(uint64_t)Align, dl, VT));
15596 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15598 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15599 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15602 SDValue Ops[2] = { Tmp1, Tmp2 };
15603 return DAG.getMergeValues(Ops, dl);
15607 SDValue Chain = Op.getOperand(0);
15608 SDValue Size = Op.getOperand(1);
15609 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15610 EVT VT = Op.getNode()->getValueType(0);
15612 bool Is64Bit = Subtarget->is64Bit();
15613 MVT SPTy = getPointerTy(DAG.getDataLayout());
15616 MachineRegisterInfo &MRI = MF.getRegInfo();
15619 // The 64 bit implementation of segmented stacks needs to clobber both r10
15620 // r11. This makes it impossible to use it along with nested parameters.
15621 const Function *F = MF.getFunction();
15623 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15625 if (I->hasNestAttr())
15626 report_fatal_error("Cannot use segmented stacks with functions that "
15627 "have nested arguments.");
15630 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15631 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15632 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15633 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15634 DAG.getRegister(Vreg, SPTy));
15635 SDValue Ops1[2] = { Value, Chain };
15636 return DAG.getMergeValues(Ops1, dl);
15639 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15641 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15642 Flag = Chain.getValue(1);
15643 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15645 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15647 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15648 unsigned SPReg = RegInfo->getStackRegister();
15649 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15650 Chain = SP.getValue(1);
15653 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15654 DAG.getConstant(-(uint64_t)Align, dl, VT));
15655 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15658 SDValue Ops1[2] = { SP, Chain };
15659 return DAG.getMergeValues(Ops1, dl);
15663 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15664 MachineFunction &MF = DAG.getMachineFunction();
15665 auto PtrVT = getPointerTy(MF.getDataLayout());
15666 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15668 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15671 if (!Subtarget->is64Bit() ||
15672 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15673 // vastart just stores the address of the VarArgsFrameIndex slot into the
15674 // memory location argument.
15675 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15676 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15677 MachinePointerInfo(SV), false, false, 0);
15681 // gp_offset (0 - 6 * 8)
15682 // fp_offset (48 - 48 + 8 * 16)
15683 // overflow_arg_area (point to parameters coming in memory).
15685 SmallVector<SDValue, 8> MemOps;
15686 SDValue FIN = Op.getOperand(1);
15688 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15689 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15691 FIN, MachinePointerInfo(SV), false, false, 0);
15692 MemOps.push_back(Store);
15695 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15696 Store = DAG.getStore(Op.getOperand(0), DL,
15697 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15699 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15700 MemOps.push_back(Store);
15702 // Store ptr to overflow_arg_area
15703 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15704 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15705 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15706 MachinePointerInfo(SV, 8),
15708 MemOps.push_back(Store);
15710 // Store ptr to reg_save_area.
15711 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15712 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15713 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15714 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15715 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15716 MemOps.push_back(Store);
15717 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15720 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15721 assert(Subtarget->is64Bit() &&
15722 "LowerVAARG only handles 64-bit va_arg!");
15723 assert(Op.getNode()->getNumOperands() == 4);
15725 MachineFunction &MF = DAG.getMachineFunction();
15726 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15727 // The Win64 ABI uses char* instead of a structure.
15728 return DAG.expandVAArg(Op.getNode());
15730 SDValue Chain = Op.getOperand(0);
15731 SDValue SrcPtr = Op.getOperand(1);
15732 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15733 unsigned Align = Op.getConstantOperandVal(3);
15736 EVT ArgVT = Op.getNode()->getValueType(0);
15737 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15738 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15741 // Decide which area this value should be read from.
15742 // TODO: Implement the AMD64 ABI in its entirety. This simple
15743 // selection mechanism works only for the basic types.
15744 if (ArgVT == MVT::f80) {
15745 llvm_unreachable("va_arg for f80 not yet implemented");
15746 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15747 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15748 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15749 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15751 llvm_unreachable("Unhandled argument type in LowerVAARG");
15754 if (ArgMode == 2) {
15755 // Sanity Check: Make sure using fp_offset makes sense.
15756 assert(!Subtarget->useSoftFloat() &&
15757 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15758 Subtarget->hasSSE1());
15761 // Insert VAARG_64 node into the DAG
15762 // VAARG_64 returns two values: Variable Argument Address, Chain
15763 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15764 DAG.getConstant(ArgMode, dl, MVT::i8),
15765 DAG.getConstant(Align, dl, MVT::i32)};
15766 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15767 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15768 VTs, InstOps, MVT::i64,
15769 MachinePointerInfo(SV),
15771 /*Volatile=*/false,
15773 /*WriteMem=*/true);
15774 Chain = VAARG.getValue(1);
15776 // Load the next argument and return it
15777 return DAG.getLoad(ArgVT, dl,
15780 MachinePointerInfo(),
15781 false, false, false, 0);
15784 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15785 SelectionDAG &DAG) {
15786 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15787 // where a va_list is still an i8*.
15788 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15789 if (Subtarget->isCallingConvWin64(
15790 DAG.getMachineFunction().getFunction()->getCallingConv()))
15791 // Probably a Win64 va_copy.
15792 return DAG.expandVACopy(Op.getNode());
15794 SDValue Chain = Op.getOperand(0);
15795 SDValue DstPtr = Op.getOperand(1);
15796 SDValue SrcPtr = Op.getOperand(2);
15797 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15798 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15801 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15802 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15804 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15807 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15808 // amount is a constant. Takes immediate version of shift as input.
15809 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15810 SDValue SrcOp, uint64_t ShiftAmt,
15811 SelectionDAG &DAG) {
15812 MVT ElementType = VT.getVectorElementType();
15814 // Fold this packed shift into its first operand if ShiftAmt is 0.
15818 // Check for ShiftAmt >= element width
15819 if (ShiftAmt >= ElementType.getSizeInBits()) {
15820 if (Opc == X86ISD::VSRAI)
15821 ShiftAmt = ElementType.getSizeInBits() - 1;
15823 return DAG.getConstant(0, dl, VT);
15826 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15827 && "Unknown target vector shift-by-constant node");
15829 // Fold this packed vector shift into a build vector if SrcOp is a
15830 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15831 if (VT == SrcOp.getSimpleValueType() &&
15832 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15833 SmallVector<SDValue, 8> Elts;
15834 unsigned NumElts = SrcOp->getNumOperands();
15835 ConstantSDNode *ND;
15838 default: llvm_unreachable(nullptr);
15839 case X86ISD::VSHLI:
15840 for (unsigned i=0; i!=NumElts; ++i) {
15841 SDValue CurrentOp = SrcOp->getOperand(i);
15842 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15843 Elts.push_back(CurrentOp);
15846 ND = cast<ConstantSDNode>(CurrentOp);
15847 const APInt &C = ND->getAPIntValue();
15848 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15851 case X86ISD::VSRLI:
15852 for (unsigned i=0; i!=NumElts; ++i) {
15853 SDValue CurrentOp = SrcOp->getOperand(i);
15854 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15855 Elts.push_back(CurrentOp);
15858 ND = cast<ConstantSDNode>(CurrentOp);
15859 const APInt &C = ND->getAPIntValue();
15860 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15863 case X86ISD::VSRAI:
15864 for (unsigned i=0; i!=NumElts; ++i) {
15865 SDValue CurrentOp = SrcOp->getOperand(i);
15866 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15867 Elts.push_back(CurrentOp);
15870 ND = cast<ConstantSDNode>(CurrentOp);
15871 const APInt &C = ND->getAPIntValue();
15872 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15877 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15880 return DAG.getNode(Opc, dl, VT, SrcOp,
15881 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15884 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15885 // may or may not be a constant. Takes immediate version of shift as input.
15886 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15887 SDValue SrcOp, SDValue ShAmt,
15888 SelectionDAG &DAG) {
15889 MVT SVT = ShAmt.getSimpleValueType();
15890 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15892 // Catch shift-by-constant.
15893 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15894 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15895 CShAmt->getZExtValue(), DAG);
15897 // Change opcode to non-immediate version
15899 default: llvm_unreachable("Unknown target vector shift node");
15900 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15901 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15902 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15905 const X86Subtarget &Subtarget =
15906 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15907 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15908 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15909 // Let the shuffle legalizer expand this shift amount node.
15910 SDValue Op0 = ShAmt.getOperand(0);
15911 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15912 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15914 // Need to build a vector containing shift amount.
15915 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15916 SmallVector<SDValue, 4> ShOps;
15917 ShOps.push_back(ShAmt);
15918 if (SVT == MVT::i32) {
15919 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15920 ShOps.push_back(DAG.getUNDEF(SVT));
15922 ShOps.push_back(DAG.getUNDEF(SVT));
15924 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15925 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15928 // The return type has to be a 128-bit type with the same element
15929 // type as the input type.
15930 MVT EltVT = VT.getVectorElementType();
15931 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15933 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15934 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15937 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15938 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15939 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15940 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15941 SDValue PreservedSrc,
15942 const X86Subtarget *Subtarget,
15943 SelectionDAG &DAG) {
15944 EVT VT = Op.getValueType();
15945 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15946 MVT::i1, VT.getVectorNumElements());
15947 SDValue VMask = SDValue();
15948 unsigned OpcodeSelect = ISD::VSELECT;
15951 assert(MaskVT.isSimple() && "invalid mask type");
15953 if (isAllOnes(Mask))
15956 if (MaskVT.bitsGT(Mask.getValueType())) {
15957 EVT newMaskVT = EVT::getIntegerVT(*DAG.getContext(),
15958 MaskVT.getSizeInBits());
15959 VMask = DAG.getBitcast(MaskVT,
15960 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15962 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15963 Mask.getValueType().getSizeInBits());
15964 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15965 // are extracted by EXTRACT_SUBVECTOR.
15966 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15967 DAG.getBitcast(BitcastVT, Mask),
15968 DAG.getIntPtrConstant(0, dl));
15971 switch (Op.getOpcode()) {
15973 case X86ISD::PCMPEQM:
15974 case X86ISD::PCMPGTM:
15976 case X86ISD::CMPMU:
15977 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15978 case X86ISD::VFPCLASS:
15979 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
15980 case X86ISD::VTRUNC:
15981 case X86ISD::VTRUNCS:
15982 case X86ISD::VTRUNCUS:
15983 // We can't use ISD::VSELECT here because it is not always "Legal"
15984 // for the destination type. For example vpmovqb require only AVX512
15985 // and vselect that can operate on byte element type require BWI
15986 OpcodeSelect = X86ISD::SELECT;
15989 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15990 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15991 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
15994 /// \brief Creates an SDNode for a predicated scalar operation.
15995 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15996 /// The mask is coming as MVT::i8 and it should be truncated
15997 /// to MVT::i1 while lowering masking intrinsics.
15998 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15999 /// "X86select" instead of "vselect". We just can't create the "vselect" node
16000 /// for a scalar instruction.
16001 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16002 SDValue PreservedSrc,
16003 const X86Subtarget *Subtarget,
16004 SelectionDAG &DAG) {
16005 if (isAllOnes(Mask))
16008 EVT VT = Op.getValueType();
16010 // The mask should be of type MVT::i1
16011 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16013 if (Op.getOpcode() == X86ISD::FSETCC)
16014 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
16015 if (Op.getOpcode() == X86ISD::VFPCLASS)
16016 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
16018 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16019 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16020 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16023 static int getSEHRegistrationNodeSize(const Function *Fn) {
16024 if (!Fn->hasPersonalityFn())
16025 report_fatal_error(
16026 "querying registration node size for function without personality");
16027 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
16028 // WinEHStatePass for the full struct definition.
16029 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
16030 case EHPersonality::MSVC_X86SEH: return 24;
16031 case EHPersonality::MSVC_CXX: return 16;
16034 report_fatal_error("can only recover FP for MSVC EH personality functions");
16037 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
16038 /// function or when returning to a parent frame after catching an exception, we
16039 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
16040 /// Here's the math:
16041 /// RegNodeBase = EntryEBP - RegNodeSize
16042 /// ParentFP = RegNodeBase - RegNodeFrameOffset
16043 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
16044 /// subtracting the offset (negative on x86) takes us back to the parent FP.
16045 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16046 SDValue EntryEBP) {
16047 MachineFunction &MF = DAG.getMachineFunction();
16050 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16051 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16053 // It's possible that the parent function no longer has a personality function
16054 // if the exceptional code was optimized away, in which case we just return
16055 // the incoming EBP.
16056 if (!Fn->hasPersonalityFn())
16059 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16061 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16063 MCSymbol *OffsetSym =
16064 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16065 GlobalValue::getRealLinkageName(Fn->getName()));
16066 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16067 SDValue RegNodeFrameOffset =
16068 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16070 // RegNodeBase = EntryEBP - RegNodeSize
16071 // ParentFP = RegNodeBase - RegNodeFrameOffset
16072 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16073 DAG.getConstant(RegNodeSize, dl, PtrVT));
16074 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
16077 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16078 SelectionDAG &DAG) {
16080 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16081 EVT VT = Op.getValueType();
16082 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16084 switch(IntrData->Type) {
16085 case INTR_TYPE_1OP:
16086 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16087 case INTR_TYPE_2OP:
16088 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16090 case INTR_TYPE_2OP_IMM8:
16091 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16092 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16093 case INTR_TYPE_3OP:
16094 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16095 Op.getOperand(2), Op.getOperand(3));
16096 case INTR_TYPE_4OP:
16097 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16098 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16099 case INTR_TYPE_1OP_MASK_RM: {
16100 SDValue Src = Op.getOperand(1);
16101 SDValue PassThru = Op.getOperand(2);
16102 SDValue Mask = Op.getOperand(3);
16103 SDValue RoundingMode;
16104 // We allways add rounding mode to the Node.
16105 // If the rounding mode is not specified, we add the
16106 // "current direction" mode.
16107 if (Op.getNumOperands() == 4)
16109 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16111 RoundingMode = Op.getOperand(4);
16112 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16113 if (IntrWithRoundingModeOpcode != 0)
16114 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16115 X86::STATIC_ROUNDING::CUR_DIRECTION)
16116 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16117 dl, Op.getValueType(), Src, RoundingMode),
16118 Mask, PassThru, Subtarget, DAG);
16119 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16121 Mask, PassThru, Subtarget, DAG);
16123 case INTR_TYPE_1OP_MASK: {
16124 SDValue Src = Op.getOperand(1);
16125 SDValue PassThru = Op.getOperand(2);
16126 SDValue Mask = Op.getOperand(3);
16127 // We add rounding mode to the Node when
16128 // - RM Opcode is specified and
16129 // - RM is not "current direction".
16130 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16131 if (IntrWithRoundingModeOpcode != 0) {
16132 SDValue Rnd = Op.getOperand(4);
16133 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16134 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16135 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16136 dl, Op.getValueType(),
16138 Mask, PassThru, Subtarget, DAG);
16141 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16142 Mask, PassThru, Subtarget, DAG);
16144 case INTR_TYPE_SCALAR_MASK: {
16145 SDValue Src1 = Op.getOperand(1);
16146 SDValue Src2 = Op.getOperand(2);
16147 SDValue passThru = Op.getOperand(3);
16148 SDValue Mask = Op.getOperand(4);
16149 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16150 Mask, passThru, Subtarget, DAG);
16152 case INTR_TYPE_SCALAR_MASK_RM: {
16153 SDValue Src1 = Op.getOperand(1);
16154 SDValue Src2 = Op.getOperand(2);
16155 SDValue Src0 = Op.getOperand(3);
16156 SDValue Mask = Op.getOperand(4);
16157 // There are 2 kinds of intrinsics in this group:
16158 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16159 // (2) With rounding mode and sae - 7 operands.
16160 if (Op.getNumOperands() == 6) {
16161 SDValue Sae = Op.getOperand(5);
16162 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16163 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16165 Mask, Src0, Subtarget, DAG);
16167 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16168 SDValue RoundingMode = Op.getOperand(5);
16169 SDValue Sae = Op.getOperand(6);
16170 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16171 RoundingMode, Sae),
16172 Mask, Src0, Subtarget, DAG);
16174 case INTR_TYPE_2OP_MASK:
16175 case INTR_TYPE_2OP_IMM8_MASK: {
16176 SDValue Src1 = Op.getOperand(1);
16177 SDValue Src2 = Op.getOperand(2);
16178 SDValue PassThru = Op.getOperand(3);
16179 SDValue Mask = Op.getOperand(4);
16181 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16182 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16184 // We specify 2 possible opcodes for intrinsics with rounding modes.
16185 // First, we check if the intrinsic may have non-default rounding mode,
16186 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16187 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16188 if (IntrWithRoundingModeOpcode != 0) {
16189 SDValue Rnd = Op.getOperand(5);
16190 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16191 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16192 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16193 dl, Op.getValueType(),
16195 Mask, PassThru, Subtarget, DAG);
16198 // TODO: Intrinsics should have fast-math-flags to propagate.
16199 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16200 Mask, PassThru, Subtarget, DAG);
16202 case INTR_TYPE_2OP_MASK_RM: {
16203 SDValue Src1 = Op.getOperand(1);
16204 SDValue Src2 = Op.getOperand(2);
16205 SDValue PassThru = Op.getOperand(3);
16206 SDValue Mask = Op.getOperand(4);
16207 // We specify 2 possible modes for intrinsics, with/without rounding
16209 // First, we check if the intrinsic have rounding mode (6 operands),
16210 // if not, we set rounding mode to "current".
16212 if (Op.getNumOperands() == 6)
16213 Rnd = Op.getOperand(5);
16215 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16216 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16218 Mask, PassThru, Subtarget, DAG);
16220 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16221 SDValue Src1 = Op.getOperand(1);
16222 SDValue Src2 = Op.getOperand(2);
16223 SDValue Src3 = Op.getOperand(3);
16224 SDValue PassThru = Op.getOperand(4);
16225 SDValue Mask = Op.getOperand(5);
16226 SDValue Sae = Op.getOperand(6);
16228 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16230 Mask, PassThru, Subtarget, DAG);
16232 case INTR_TYPE_3OP_MASK_RM: {
16233 SDValue Src1 = Op.getOperand(1);
16234 SDValue Src2 = Op.getOperand(2);
16235 SDValue Imm = Op.getOperand(3);
16236 SDValue PassThru = Op.getOperand(4);
16237 SDValue Mask = Op.getOperand(5);
16238 // We specify 2 possible modes for intrinsics, with/without rounding
16240 // First, we check if the intrinsic have rounding mode (7 operands),
16241 // if not, we set rounding mode to "current".
16243 if (Op.getNumOperands() == 7)
16244 Rnd = Op.getOperand(6);
16246 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16247 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16248 Src1, Src2, Imm, Rnd),
16249 Mask, PassThru, Subtarget, DAG);
16251 case INTR_TYPE_3OP_IMM8_MASK:
16252 case INTR_TYPE_3OP_MASK:
16253 case INSERT_SUBVEC: {
16254 SDValue Src1 = Op.getOperand(1);
16255 SDValue Src2 = Op.getOperand(2);
16256 SDValue Src3 = Op.getOperand(3);
16257 SDValue PassThru = Op.getOperand(4);
16258 SDValue Mask = Op.getOperand(5);
16260 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16261 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16262 else if (IntrData->Type == INSERT_SUBVEC) {
16263 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16264 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16265 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16266 Imm *= Src2.getValueType().getVectorNumElements();
16267 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16270 // We specify 2 possible opcodes for intrinsics with rounding modes.
16271 // First, we check if the intrinsic may have non-default rounding mode,
16272 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16273 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16274 if (IntrWithRoundingModeOpcode != 0) {
16275 SDValue Rnd = Op.getOperand(6);
16276 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16277 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16278 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16279 dl, Op.getValueType(),
16280 Src1, Src2, Src3, Rnd),
16281 Mask, PassThru, Subtarget, DAG);
16284 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16286 Mask, PassThru, Subtarget, DAG);
16288 case VPERM_3OP_MASKZ:
16289 case VPERM_3OP_MASK:
16292 case FMA_OP_MASK: {
16293 SDValue Src1 = Op.getOperand(1);
16294 SDValue Src2 = Op.getOperand(2);
16295 SDValue Src3 = Op.getOperand(3);
16296 SDValue Mask = Op.getOperand(4);
16297 EVT VT = Op.getValueType();
16298 SDValue PassThru = SDValue();
16300 // set PassThru element
16301 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
16302 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16303 else if (IntrData->Type == FMA_OP_MASK3)
16308 // We specify 2 possible opcodes for intrinsics with rounding modes.
16309 // First, we check if the intrinsic may have non-default rounding mode,
16310 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16311 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16312 if (IntrWithRoundingModeOpcode != 0) {
16313 SDValue Rnd = Op.getOperand(5);
16314 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16315 X86::STATIC_ROUNDING::CUR_DIRECTION)
16316 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16317 dl, Op.getValueType(),
16318 Src1, Src2, Src3, Rnd),
16319 Mask, PassThru, Subtarget, DAG);
16321 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16322 dl, Op.getValueType(),
16324 Mask, PassThru, Subtarget, DAG);
16326 case TERLOG_OP_MASK:
16327 case TERLOG_OP_MASKZ: {
16328 SDValue Src1 = Op.getOperand(1);
16329 SDValue Src2 = Op.getOperand(2);
16330 SDValue Src3 = Op.getOperand(3);
16331 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16332 SDValue Mask = Op.getOperand(5);
16333 EVT VT = Op.getValueType();
16334 SDValue PassThru = Src1;
16335 // Set PassThru element.
16336 if (IntrData->Type == TERLOG_OP_MASKZ)
16337 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16339 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16340 Src1, Src2, Src3, Src4),
16341 Mask, PassThru, Subtarget, DAG);
16344 // FPclass intrinsics with mask
16345 SDValue Src1 = Op.getOperand(1);
16346 EVT VT = Src1.getValueType();
16347 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16348 VT.getVectorNumElements());
16349 SDValue Imm = Op.getOperand(2);
16350 SDValue Mask = Op.getOperand(3);
16351 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16352 Mask.getValueType().getSizeInBits());
16353 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16354 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16355 DAG.getTargetConstant(0, dl, MaskVT),
16357 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16358 DAG.getUNDEF(BitcastVT), FPclassMask,
16359 DAG.getIntPtrConstant(0, dl));
16360 return DAG.getBitcast(Op.getValueType(), Res);
16363 SDValue Src1 = Op.getOperand(1);
16364 SDValue Imm = Op.getOperand(2);
16365 SDValue Mask = Op.getOperand(3);
16366 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16367 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16368 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16369 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16372 case CMP_MASK_CC: {
16373 // Comparison intrinsics with masks.
16374 // Example of transformation:
16375 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16376 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16378 // (v8i1 (insert_subvector undef,
16379 // (v2i1 (and (PCMPEQM %a, %b),
16380 // (extract_subvector
16381 // (v8i1 (bitcast %mask)), 0))), 0))))
16382 EVT VT = Op.getOperand(1).getValueType();
16383 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16384 VT.getVectorNumElements());
16385 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16386 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16387 Mask.getValueType().getSizeInBits());
16389 if (IntrData->Type == CMP_MASK_CC) {
16390 SDValue CC = Op.getOperand(3);
16391 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16392 // We specify 2 possible opcodes for intrinsics with rounding modes.
16393 // First, we check if the intrinsic may have non-default rounding mode,
16394 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16395 if (IntrData->Opc1 != 0) {
16396 SDValue Rnd = Op.getOperand(5);
16397 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16398 X86::STATIC_ROUNDING::CUR_DIRECTION)
16399 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16400 Op.getOperand(2), CC, Rnd);
16402 //default rounding mode
16404 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16405 Op.getOperand(2), CC);
16408 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16409 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16412 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16413 DAG.getTargetConstant(0, dl,
16416 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16417 DAG.getUNDEF(BitcastVT), CmpMask,
16418 DAG.getIntPtrConstant(0, dl));
16419 return DAG.getBitcast(Op.getValueType(), Res);
16421 case CMP_MASK_SCALAR_CC: {
16422 SDValue Src1 = Op.getOperand(1);
16423 SDValue Src2 = Op.getOperand(2);
16424 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16425 SDValue Mask = Op.getOperand(4);
16428 if (IntrData->Opc1 != 0) {
16429 SDValue Rnd = Op.getOperand(5);
16430 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16431 X86::STATIC_ROUNDING::CUR_DIRECTION)
16432 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16434 //default rounding mode
16436 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16438 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16439 DAG.getTargetConstant(0, dl,
16443 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16444 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16445 DAG.getValueType(MVT::i1));
16447 case COMI: { // Comparison intrinsics
16448 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16449 SDValue LHS = Op.getOperand(1);
16450 SDValue RHS = Op.getOperand(2);
16451 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16452 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16453 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16454 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16455 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16456 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16459 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16460 Op.getOperand(1), Op.getOperand(2), DAG);
16462 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16463 Op.getSimpleValueType(),
16465 Op.getOperand(2), DAG),
16466 Op.getOperand(4), Op.getOperand(3), Subtarget,
16468 case COMPRESS_EXPAND_IN_REG: {
16469 SDValue Mask = Op.getOperand(3);
16470 SDValue DataToCompress = Op.getOperand(1);
16471 SDValue PassThru = Op.getOperand(2);
16472 if (isAllOnes(Mask)) // return data as is
16473 return Op.getOperand(1);
16475 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16477 Mask, PassThru, Subtarget, DAG);
16480 SDValue Mask = Op.getOperand(3);
16481 EVT VT = Op.getValueType();
16482 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16483 VT.getVectorNumElements());
16484 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16485 Mask.getValueType().getSizeInBits());
16487 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16488 DAG.getBitcast(BitcastVT, Mask),
16489 DAG.getIntPtrConstant(0, dl));
16490 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16499 default: return SDValue(); // Don't custom lower most intrinsics.
16501 case Intrinsic::x86_avx2_permd:
16502 case Intrinsic::x86_avx2_permps:
16503 // Operands intentionally swapped. Mask is last operand to intrinsic,
16504 // but second operand for node/instruction.
16505 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16506 Op.getOperand(2), Op.getOperand(1));
16508 // ptest and testp intrinsics. The intrinsic these come from are designed to
16509 // return an integer value, not just an instruction so lower it to the ptest
16510 // or testp pattern and a setcc for the result.
16511 case Intrinsic::x86_sse41_ptestz:
16512 case Intrinsic::x86_sse41_ptestc:
16513 case Intrinsic::x86_sse41_ptestnzc:
16514 case Intrinsic::x86_avx_ptestz_256:
16515 case Intrinsic::x86_avx_ptestc_256:
16516 case Intrinsic::x86_avx_ptestnzc_256:
16517 case Intrinsic::x86_avx_vtestz_ps:
16518 case Intrinsic::x86_avx_vtestc_ps:
16519 case Intrinsic::x86_avx_vtestnzc_ps:
16520 case Intrinsic::x86_avx_vtestz_pd:
16521 case Intrinsic::x86_avx_vtestc_pd:
16522 case Intrinsic::x86_avx_vtestnzc_pd:
16523 case Intrinsic::x86_avx_vtestz_ps_256:
16524 case Intrinsic::x86_avx_vtestc_ps_256:
16525 case Intrinsic::x86_avx_vtestnzc_ps_256:
16526 case Intrinsic::x86_avx_vtestz_pd_256:
16527 case Intrinsic::x86_avx_vtestc_pd_256:
16528 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16529 bool IsTestPacked = false;
16532 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16533 case Intrinsic::x86_avx_vtestz_ps:
16534 case Intrinsic::x86_avx_vtestz_pd:
16535 case Intrinsic::x86_avx_vtestz_ps_256:
16536 case Intrinsic::x86_avx_vtestz_pd_256:
16537 IsTestPacked = true; // Fallthrough
16538 case Intrinsic::x86_sse41_ptestz:
16539 case Intrinsic::x86_avx_ptestz_256:
16541 X86CC = X86::COND_E;
16543 case Intrinsic::x86_avx_vtestc_ps:
16544 case Intrinsic::x86_avx_vtestc_pd:
16545 case Intrinsic::x86_avx_vtestc_ps_256:
16546 case Intrinsic::x86_avx_vtestc_pd_256:
16547 IsTestPacked = true; // Fallthrough
16548 case Intrinsic::x86_sse41_ptestc:
16549 case Intrinsic::x86_avx_ptestc_256:
16551 X86CC = X86::COND_B;
16553 case Intrinsic::x86_avx_vtestnzc_ps:
16554 case Intrinsic::x86_avx_vtestnzc_pd:
16555 case Intrinsic::x86_avx_vtestnzc_ps_256:
16556 case Intrinsic::x86_avx_vtestnzc_pd_256:
16557 IsTestPacked = true; // Fallthrough
16558 case Intrinsic::x86_sse41_ptestnzc:
16559 case Intrinsic::x86_avx_ptestnzc_256:
16561 X86CC = X86::COND_A;
16565 SDValue LHS = Op.getOperand(1);
16566 SDValue RHS = Op.getOperand(2);
16567 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16568 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16569 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16570 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16571 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16573 case Intrinsic::x86_avx512_kortestz_w:
16574 case Intrinsic::x86_avx512_kortestc_w: {
16575 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16576 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16577 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16578 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16579 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16580 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16581 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16584 case Intrinsic::x86_sse42_pcmpistria128:
16585 case Intrinsic::x86_sse42_pcmpestria128:
16586 case Intrinsic::x86_sse42_pcmpistric128:
16587 case Intrinsic::x86_sse42_pcmpestric128:
16588 case Intrinsic::x86_sse42_pcmpistrio128:
16589 case Intrinsic::x86_sse42_pcmpestrio128:
16590 case Intrinsic::x86_sse42_pcmpistris128:
16591 case Intrinsic::x86_sse42_pcmpestris128:
16592 case Intrinsic::x86_sse42_pcmpistriz128:
16593 case Intrinsic::x86_sse42_pcmpestriz128: {
16597 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16598 case Intrinsic::x86_sse42_pcmpistria128:
16599 Opcode = X86ISD::PCMPISTRI;
16600 X86CC = X86::COND_A;
16602 case Intrinsic::x86_sse42_pcmpestria128:
16603 Opcode = X86ISD::PCMPESTRI;
16604 X86CC = X86::COND_A;
16606 case Intrinsic::x86_sse42_pcmpistric128:
16607 Opcode = X86ISD::PCMPISTRI;
16608 X86CC = X86::COND_B;
16610 case Intrinsic::x86_sse42_pcmpestric128:
16611 Opcode = X86ISD::PCMPESTRI;
16612 X86CC = X86::COND_B;
16614 case Intrinsic::x86_sse42_pcmpistrio128:
16615 Opcode = X86ISD::PCMPISTRI;
16616 X86CC = X86::COND_O;
16618 case Intrinsic::x86_sse42_pcmpestrio128:
16619 Opcode = X86ISD::PCMPESTRI;
16620 X86CC = X86::COND_O;
16622 case Intrinsic::x86_sse42_pcmpistris128:
16623 Opcode = X86ISD::PCMPISTRI;
16624 X86CC = X86::COND_S;
16626 case Intrinsic::x86_sse42_pcmpestris128:
16627 Opcode = X86ISD::PCMPESTRI;
16628 X86CC = X86::COND_S;
16630 case Intrinsic::x86_sse42_pcmpistriz128:
16631 Opcode = X86ISD::PCMPISTRI;
16632 X86CC = X86::COND_E;
16634 case Intrinsic::x86_sse42_pcmpestriz128:
16635 Opcode = X86ISD::PCMPESTRI;
16636 X86CC = X86::COND_E;
16639 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16640 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16641 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16642 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16643 DAG.getConstant(X86CC, dl, MVT::i8),
16644 SDValue(PCMP.getNode(), 1));
16645 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16648 case Intrinsic::x86_sse42_pcmpistri128:
16649 case Intrinsic::x86_sse42_pcmpestri128: {
16651 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16652 Opcode = X86ISD::PCMPISTRI;
16654 Opcode = X86ISD::PCMPESTRI;
16656 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16657 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16658 return DAG.getNode(Opcode, dl, VTs, NewOps);
16661 case Intrinsic::x86_seh_lsda: {
16662 // Compute the symbol for the LSDA. We know it'll get emitted later.
16663 MachineFunction &MF = DAG.getMachineFunction();
16664 SDValue Op1 = Op.getOperand(1);
16665 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16666 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16667 GlobalValue::getRealLinkageName(Fn->getName()));
16669 // Generate a simple absolute symbol reference. This intrinsic is only
16670 // supported on 32-bit Windows, which isn't PIC.
16671 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16672 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16675 case Intrinsic::x86_seh_recoverfp: {
16676 SDValue FnOp = Op.getOperand(1);
16677 SDValue IncomingFPOp = Op.getOperand(2);
16678 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16679 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16681 report_fatal_error(
16682 "llvm.x86.seh.recoverfp must take a function as the first argument");
16683 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16686 case Intrinsic::localaddress: {
16687 // Returns one of the stack, base, or frame pointer registers, depending on
16688 // which is used to reference local variables.
16689 MachineFunction &MF = DAG.getMachineFunction();
16690 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16692 if (RegInfo->hasBasePointer(MF))
16693 Reg = RegInfo->getBaseRegister();
16694 else // This function handles the SP or FP case.
16695 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16696 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16701 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16702 SDValue Src, SDValue Mask, SDValue Base,
16703 SDValue Index, SDValue ScaleOp, SDValue Chain,
16704 const X86Subtarget * Subtarget) {
16706 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16708 llvm_unreachable("Invalid scale type");
16709 unsigned ScaleVal = C->getZExtValue();
16710 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16711 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16713 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16714 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16715 Index.getSimpleValueType().getVectorNumElements());
16717 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16719 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16721 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16722 Mask.getValueType().getSizeInBits());
16724 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16725 // are extracted by EXTRACT_SUBVECTOR.
16726 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16727 DAG.getBitcast(BitcastVT, Mask),
16728 DAG.getIntPtrConstant(0, dl));
16730 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16731 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16732 SDValue Segment = DAG.getRegister(0, MVT::i32);
16733 if (Src.getOpcode() == ISD::UNDEF)
16734 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16735 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16736 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16737 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16738 return DAG.getMergeValues(RetOps, dl);
16741 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16742 SDValue Src, SDValue Mask, SDValue Base,
16743 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16745 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16747 llvm_unreachable("Invalid scale type");
16748 unsigned ScaleVal = C->getZExtValue();
16749 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16750 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16752 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16753 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16754 SDValue Segment = DAG.getRegister(0, MVT::i32);
16755 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16756 Index.getSimpleValueType().getVectorNumElements());
16758 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16760 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16762 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16763 Mask.getValueType().getSizeInBits());
16765 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16766 // are extracted by EXTRACT_SUBVECTOR.
16767 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16768 DAG.getBitcast(BitcastVT, Mask),
16769 DAG.getIntPtrConstant(0, dl));
16771 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16772 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16773 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16774 return SDValue(Res, 1);
16777 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16778 SDValue Mask, SDValue Base, SDValue Index,
16779 SDValue ScaleOp, SDValue Chain) {
16781 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16782 assert(C && "Invalid scale type");
16783 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16784 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16785 SDValue Segment = DAG.getRegister(0, MVT::i32);
16787 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16789 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16791 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16793 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16794 //SDVTList VTs = DAG.getVTList(MVT::Other);
16795 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16796 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16797 return SDValue(Res, 0);
16800 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16801 // read performance monitor counters (x86_rdpmc).
16802 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16803 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16804 SmallVectorImpl<SDValue> &Results) {
16805 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16806 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16809 // The ECX register is used to select the index of the performance counter
16811 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16813 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16815 // Reads the content of a 64-bit performance counter and returns it in the
16816 // registers EDX:EAX.
16817 if (Subtarget->is64Bit()) {
16818 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16819 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16822 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16823 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16826 Chain = HI.getValue(1);
16828 if (Subtarget->is64Bit()) {
16829 // The EAX register is loaded with the low-order 32 bits. The EDX register
16830 // is loaded with the supported high-order bits of the counter.
16831 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16832 DAG.getConstant(32, DL, MVT::i8));
16833 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16834 Results.push_back(Chain);
16838 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16839 SDValue Ops[] = { LO, HI };
16840 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16841 Results.push_back(Pair);
16842 Results.push_back(Chain);
16845 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16846 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16847 // also used to custom lower READCYCLECOUNTER nodes.
16848 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16849 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16850 SmallVectorImpl<SDValue> &Results) {
16851 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16852 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16855 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16856 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16857 // and the EAX register is loaded with the low-order 32 bits.
16858 if (Subtarget->is64Bit()) {
16859 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16860 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16863 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16864 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16867 SDValue Chain = HI.getValue(1);
16869 if (Opcode == X86ISD::RDTSCP_DAG) {
16870 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16872 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16873 // the ECX register. Add 'ecx' explicitly to the chain.
16874 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16876 // Explicitly store the content of ECX at the location passed in input
16877 // to the 'rdtscp' intrinsic.
16878 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16879 MachinePointerInfo(), false, false, 0);
16882 if (Subtarget->is64Bit()) {
16883 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16884 // the EAX register is loaded with the low-order 32 bits.
16885 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16886 DAG.getConstant(32, DL, MVT::i8));
16887 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16888 Results.push_back(Chain);
16892 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16893 SDValue Ops[] = { LO, HI };
16894 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16895 Results.push_back(Pair);
16896 Results.push_back(Chain);
16899 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16900 SelectionDAG &DAG) {
16901 SmallVector<SDValue, 2> Results;
16903 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16905 return DAG.getMergeValues(Results, DL);
16908 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16909 SelectionDAG &DAG) {
16910 MachineFunction &MF = DAG.getMachineFunction();
16911 const Function *Fn = MF.getFunction();
16913 SDValue Chain = Op.getOperand(0);
16915 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16916 "using llvm.x86.seh.restoreframe requires a frame pointer");
16918 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16919 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16921 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16922 unsigned FrameReg =
16923 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16924 unsigned SPReg = RegInfo->getStackRegister();
16925 unsigned SlotSize = RegInfo->getSlotSize();
16927 // Get incoming EBP.
16928 SDValue IncomingEBP =
16929 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16931 // SP is saved in the first field of every registration node, so load
16932 // [EBP-RegNodeSize] into SP.
16933 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16934 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16935 DAG.getConstant(-RegNodeSize, dl, VT));
16937 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16938 false, VT.getScalarSizeInBits() / 8);
16939 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16941 if (!RegInfo->needsStackRealignment(MF)) {
16942 // Adjust EBP to point back to the original frame position.
16943 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16944 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16946 assert(RegInfo->hasBasePointer(MF) &&
16947 "functions with Win32 EH must use frame or base pointer register");
16949 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16950 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16951 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16953 // Reload the spilled EBP value, now that the stack and base pointers are
16955 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16956 X86FI->setHasSEHFramePtrSave(true);
16957 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16958 X86FI->setSEHFramePtrSaveIndex(FI);
16959 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16960 MachinePointerInfo(), false, false, false,
16961 VT.getScalarSizeInBits() / 8);
16962 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16968 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16969 /// return truncate Store/MaskedStore Node
16970 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16974 SDValue Mask = Op.getOperand(4);
16975 SDValue DataToTruncate = Op.getOperand(3);
16976 SDValue Addr = Op.getOperand(2);
16977 SDValue Chain = Op.getOperand(0);
16979 EVT VT = DataToTruncate.getValueType();
16980 EVT SVT = EVT::getVectorVT(*DAG.getContext(),
16981 ElementType, VT.getVectorNumElements());
16983 if (isAllOnes(Mask)) // return just a truncate store
16984 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
16985 MachinePointerInfo(), SVT, false, false,
16986 SVT.getScalarSizeInBits()/8);
16988 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16989 MVT::i1, VT.getVectorNumElements());
16990 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16991 Mask.getValueType().getSizeInBits());
16992 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16993 // are extracted by EXTRACT_SUBVECTOR.
16994 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16995 DAG.getBitcast(BitcastVT, Mask),
16996 DAG.getIntPtrConstant(0, dl));
16998 MachineMemOperand *MMO = DAG.getMachineFunction().
16999 getMachineMemOperand(MachinePointerInfo(),
17000 MachineMemOperand::MOStore, SVT.getStoreSize(),
17001 SVT.getScalarSizeInBits()/8);
17003 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
17004 VMask, SVT, MMO, true);
17007 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17008 SelectionDAG &DAG) {
17009 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17011 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17013 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
17014 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
17019 switch(IntrData->Type) {
17021 llvm_unreachable("Unknown Intrinsic Type");
17025 // Emit the node with the right value type.
17026 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17027 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17029 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17030 // Otherwise return the value from Rand, which is always 0, casted to i32.
17031 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17032 DAG.getConstant(1, dl, Op->getValueType(1)),
17033 DAG.getConstant(X86::COND_B, dl, MVT::i32),
17034 SDValue(Result.getNode(), 1) };
17035 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17036 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17039 // Return { result, isValid, chain }.
17040 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17041 SDValue(Result.getNode(), 2));
17044 //gather(v1, mask, index, base, scale);
17045 SDValue Chain = Op.getOperand(0);
17046 SDValue Src = Op.getOperand(2);
17047 SDValue Base = Op.getOperand(3);
17048 SDValue Index = Op.getOperand(4);
17049 SDValue Mask = Op.getOperand(5);
17050 SDValue Scale = Op.getOperand(6);
17051 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17055 //scatter(base, mask, index, v1, scale);
17056 SDValue Chain = Op.getOperand(0);
17057 SDValue Base = Op.getOperand(2);
17058 SDValue Mask = Op.getOperand(3);
17059 SDValue Index = Op.getOperand(4);
17060 SDValue Src = Op.getOperand(5);
17061 SDValue Scale = Op.getOperand(6);
17062 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17066 SDValue Hint = Op.getOperand(6);
17067 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17068 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17069 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17070 SDValue Chain = Op.getOperand(0);
17071 SDValue Mask = Op.getOperand(2);
17072 SDValue Index = Op.getOperand(3);
17073 SDValue Base = Op.getOperand(4);
17074 SDValue Scale = Op.getOperand(5);
17075 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17077 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17079 SmallVector<SDValue, 2> Results;
17080 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17082 return DAG.getMergeValues(Results, dl);
17084 // Read Performance Monitoring Counters.
17086 SmallVector<SDValue, 2> Results;
17087 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17088 return DAG.getMergeValues(Results, dl);
17090 // XTEST intrinsics.
17092 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17093 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17094 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17095 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17097 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17098 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17099 Ret, SDValue(InTrans.getNode(), 1));
17103 SmallVector<SDValue, 2> Results;
17104 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17105 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17106 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17107 DAG.getConstant(-1, dl, MVT::i8));
17108 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17109 Op.getOperand(4), GenCF.getValue(1));
17110 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17111 Op.getOperand(5), MachinePointerInfo(),
17113 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17114 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17116 Results.push_back(SetCC);
17117 Results.push_back(Store);
17118 return DAG.getMergeValues(Results, dl);
17120 case COMPRESS_TO_MEM: {
17122 SDValue Mask = Op.getOperand(4);
17123 SDValue DataToCompress = Op.getOperand(3);
17124 SDValue Addr = Op.getOperand(2);
17125 SDValue Chain = Op.getOperand(0);
17127 EVT VT = DataToCompress.getValueType();
17128 if (isAllOnes(Mask)) // return just a store
17129 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17130 MachinePointerInfo(), false, false,
17131 VT.getScalarSizeInBits()/8);
17133 SDValue Compressed =
17134 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17135 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17136 return DAG.getStore(Chain, dl, Compressed, Addr,
17137 MachinePointerInfo(), false, false,
17138 VT.getScalarSizeInBits()/8);
17140 case TRUNCATE_TO_MEM_VI8:
17141 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17142 case TRUNCATE_TO_MEM_VI16:
17143 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17144 case TRUNCATE_TO_MEM_VI32:
17145 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17146 case EXPAND_FROM_MEM: {
17148 SDValue Mask = Op.getOperand(4);
17149 SDValue PassThru = Op.getOperand(3);
17150 SDValue Addr = Op.getOperand(2);
17151 SDValue Chain = Op.getOperand(0);
17152 EVT VT = Op.getValueType();
17154 if (isAllOnes(Mask)) // return just a load
17155 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17156 false, VT.getScalarSizeInBits()/8);
17158 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17159 false, false, false,
17160 VT.getScalarSizeInBits()/8);
17162 SDValue Results[] = {
17163 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17164 Mask, PassThru, Subtarget, DAG), Chain};
17165 return DAG.getMergeValues(Results, dl);
17170 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17171 SelectionDAG &DAG) const {
17172 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17173 MFI->setReturnAddressIsTaken(true);
17175 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17178 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17180 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17183 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17184 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17185 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17186 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17187 DAG.getNode(ISD::ADD, dl, PtrVT,
17188 FrameAddr, Offset),
17189 MachinePointerInfo(), false, false, false, 0);
17192 // Just load the return address.
17193 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17194 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17195 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17198 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17199 MachineFunction &MF = DAG.getMachineFunction();
17200 MachineFrameInfo *MFI = MF.getFrameInfo();
17201 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17202 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17203 EVT VT = Op.getValueType();
17205 MFI->setFrameAddressIsTaken(true);
17207 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17208 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17209 // is not possible to crawl up the stack without looking at the unwind codes
17211 int FrameAddrIndex = FuncInfo->getFAIndex();
17212 if (!FrameAddrIndex) {
17213 // Set up a frame object for the return address.
17214 unsigned SlotSize = RegInfo->getSlotSize();
17215 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17216 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17217 FuncInfo->setFAIndex(FrameAddrIndex);
17219 return DAG.getFrameIndex(FrameAddrIndex, VT);
17222 unsigned FrameReg =
17223 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17224 SDLoc dl(Op); // FIXME probably not meaningful
17225 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17226 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17227 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17228 "Invalid Frame Register!");
17229 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17231 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17232 MachinePointerInfo(),
17233 false, false, false, 0);
17237 // FIXME? Maybe this could be a TableGen attribute on some registers and
17238 // this table could be generated automatically from RegInfo.
17239 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17240 SelectionDAG &DAG) const {
17241 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17242 const MachineFunction &MF = DAG.getMachineFunction();
17244 unsigned Reg = StringSwitch<unsigned>(RegName)
17245 .Case("esp", X86::ESP)
17246 .Case("rsp", X86::RSP)
17247 .Case("ebp", X86::EBP)
17248 .Case("rbp", X86::RBP)
17251 if (Reg == X86::EBP || Reg == X86::RBP) {
17252 if (!TFI.hasFP(MF))
17253 report_fatal_error("register " + StringRef(RegName) +
17254 " is allocatable: function has no frame pointer");
17257 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17258 unsigned FrameReg =
17259 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17260 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17261 "Invalid Frame Register!");
17269 report_fatal_error("Invalid register name global variable");
17272 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17273 SelectionDAG &DAG) const {
17274 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17275 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17278 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17279 SDValue Chain = Op.getOperand(0);
17280 SDValue Offset = Op.getOperand(1);
17281 SDValue Handler = Op.getOperand(2);
17284 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17285 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17286 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17287 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17288 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17289 "Invalid Frame Register!");
17290 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17291 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17293 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17294 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17296 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17297 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17299 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17301 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17302 DAG.getRegister(StoreAddrReg, PtrVT));
17305 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17306 SelectionDAG &DAG) const {
17308 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17309 DAG.getVTList(MVT::i32, MVT::Other),
17310 Op.getOperand(0), Op.getOperand(1));
17313 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17314 SelectionDAG &DAG) const {
17316 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17317 Op.getOperand(0), Op.getOperand(1));
17320 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17321 return Op.getOperand(0);
17324 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17325 SelectionDAG &DAG) const {
17326 SDValue Root = Op.getOperand(0);
17327 SDValue Trmp = Op.getOperand(1); // trampoline
17328 SDValue FPtr = Op.getOperand(2); // nested function
17329 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17332 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17333 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17335 if (Subtarget->is64Bit()) {
17336 SDValue OutChains[6];
17338 // Large code-model.
17339 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17340 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17342 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17343 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17345 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17347 // Load the pointer to the nested function into R11.
17348 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17349 SDValue Addr = Trmp;
17350 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17351 Addr, MachinePointerInfo(TrmpAddr),
17354 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17355 DAG.getConstant(2, dl, MVT::i64));
17356 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17357 MachinePointerInfo(TrmpAddr, 2),
17360 // Load the 'nest' parameter value into R10.
17361 // R10 is specified in X86CallingConv.td
17362 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17363 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17364 DAG.getConstant(10, dl, MVT::i64));
17365 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17366 Addr, MachinePointerInfo(TrmpAddr, 10),
17369 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17370 DAG.getConstant(12, dl, MVT::i64));
17371 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17372 MachinePointerInfo(TrmpAddr, 12),
17375 // Jump to the nested function.
17376 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17377 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17378 DAG.getConstant(20, dl, MVT::i64));
17379 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17380 Addr, MachinePointerInfo(TrmpAddr, 20),
17383 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17384 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17385 DAG.getConstant(22, dl, MVT::i64));
17386 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17387 Addr, MachinePointerInfo(TrmpAddr, 22),
17390 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17392 const Function *Func =
17393 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17394 CallingConv::ID CC = Func->getCallingConv();
17399 llvm_unreachable("Unsupported calling convention");
17400 case CallingConv::C:
17401 case CallingConv::X86_StdCall: {
17402 // Pass 'nest' parameter in ECX.
17403 // Must be kept in sync with X86CallingConv.td
17404 NestReg = X86::ECX;
17406 // Check that ECX wasn't needed by an 'inreg' parameter.
17407 FunctionType *FTy = Func->getFunctionType();
17408 const AttributeSet &Attrs = Func->getAttributes();
17410 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17411 unsigned InRegCount = 0;
17414 for (FunctionType::param_iterator I = FTy->param_begin(),
17415 E = FTy->param_end(); I != E; ++I, ++Idx)
17416 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17417 auto &DL = DAG.getDataLayout();
17418 // FIXME: should only count parameters that are lowered to integers.
17419 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17422 if (InRegCount > 2) {
17423 report_fatal_error("Nest register in use - reduce number of inreg"
17429 case CallingConv::X86_FastCall:
17430 case CallingConv::X86_ThisCall:
17431 case CallingConv::Fast:
17432 // Pass 'nest' parameter in EAX.
17433 // Must be kept in sync with X86CallingConv.td
17434 NestReg = X86::EAX;
17438 SDValue OutChains[4];
17439 SDValue Addr, Disp;
17441 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17442 DAG.getConstant(10, dl, MVT::i32));
17443 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17445 // This is storing the opcode for MOV32ri.
17446 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17447 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17448 OutChains[0] = DAG.getStore(Root, dl,
17449 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17450 Trmp, MachinePointerInfo(TrmpAddr),
17453 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17454 DAG.getConstant(1, dl, MVT::i32));
17455 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17456 MachinePointerInfo(TrmpAddr, 1),
17459 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17460 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17461 DAG.getConstant(5, dl, MVT::i32));
17462 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17463 Addr, MachinePointerInfo(TrmpAddr, 5),
17466 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17467 DAG.getConstant(6, dl, MVT::i32));
17468 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17469 MachinePointerInfo(TrmpAddr, 6),
17472 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17476 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17477 SelectionDAG &DAG) const {
17479 The rounding mode is in bits 11:10 of FPSR, and has the following
17481 00 Round to nearest
17486 FLT_ROUNDS, on the other hand, expects the following:
17493 To perform the conversion, we do:
17494 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17497 MachineFunction &MF = DAG.getMachineFunction();
17498 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17499 unsigned StackAlignment = TFI.getStackAlignment();
17500 MVT VT = Op.getSimpleValueType();
17503 // Save FP Control Word to stack slot
17504 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17505 SDValue StackSlot =
17506 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17508 MachineMemOperand *MMO =
17509 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17510 MachineMemOperand::MOStore, 2, 2);
17512 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17513 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17514 DAG.getVTList(MVT::Other),
17515 Ops, MVT::i16, MMO);
17517 // Load FP Control Word from stack slot
17518 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17519 MachinePointerInfo(), false, false, false, 0);
17521 // Transform as necessary
17523 DAG.getNode(ISD::SRL, DL, MVT::i16,
17524 DAG.getNode(ISD::AND, DL, MVT::i16,
17525 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17526 DAG.getConstant(11, DL, MVT::i8));
17528 DAG.getNode(ISD::SRL, DL, MVT::i16,
17529 DAG.getNode(ISD::AND, DL, MVT::i16,
17530 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17531 DAG.getConstant(9, DL, MVT::i8));
17534 DAG.getNode(ISD::AND, DL, MVT::i16,
17535 DAG.getNode(ISD::ADD, DL, MVT::i16,
17536 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17537 DAG.getConstant(1, DL, MVT::i16)),
17538 DAG.getConstant(3, DL, MVT::i16));
17540 return DAG.getNode((VT.getSizeInBits() < 16 ?
17541 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17544 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17546 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17547 // to 512-bit vector.
17548 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17549 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17550 // split the vector, perform operation on it's Lo a Hi part and
17551 // concatenate the results.
17552 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17554 MVT VT = Op.getSimpleValueType();
17555 MVT EltVT = VT.getVectorElementType();
17556 unsigned NumElems = VT.getVectorNumElements();
17558 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17559 // Extend to 512 bit vector.
17560 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17561 "Unsupported value type for operation");
17563 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17564 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17565 DAG.getUNDEF(NewVT),
17567 DAG.getIntPtrConstant(0, dl));
17568 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17570 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17571 DAG.getIntPtrConstant(0, dl));
17574 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17575 "Unsupported element type");
17577 if (16 < NumElems) {
17578 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17580 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17581 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17583 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17584 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17586 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17589 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17591 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17592 "Unsupported value type for operation");
17594 // Use native supported vector instruction vplzcntd.
17595 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17596 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17597 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17598 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
17600 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
17603 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17604 SelectionDAG &DAG) {
17605 MVT VT = Op.getSimpleValueType();
17607 unsigned NumBits = VT.getSizeInBits();
17610 if (VT.isVector() && Subtarget->hasAVX512())
17611 return LowerVectorCTLZ_AVX512(Op, DAG);
17613 Op = Op.getOperand(0);
17614 if (VT == MVT::i8) {
17615 // Zero extend to i32 since there is not an i8 bsr.
17617 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17620 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17621 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17622 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17624 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17627 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17628 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17631 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17633 // Finally xor with NumBits-1.
17634 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17635 DAG.getConstant(NumBits - 1, dl, OpVT));
17638 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17642 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
17643 SelectionDAG &DAG) {
17644 MVT VT = Op.getSimpleValueType();
17646 unsigned NumBits = VT.getSizeInBits();
17649 if (VT.isVector() && Subtarget->hasAVX512())
17650 return LowerVectorCTLZ_AVX512(Op, DAG);
17652 Op = Op.getOperand(0);
17653 if (VT == MVT::i8) {
17654 // Zero extend to i32 since there is not an i8 bsr.
17656 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17659 // Issue a bsr (scan bits in reverse).
17660 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17661 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17663 // And xor with NumBits-1.
17664 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17665 DAG.getConstant(NumBits - 1, dl, OpVT));
17668 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17672 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17673 MVT VT = Op.getSimpleValueType();
17674 unsigned NumBits = VT.getScalarSizeInBits();
17677 if (VT.isVector()) {
17678 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17680 SDValue N0 = Op.getOperand(0);
17681 SDValue Zero = DAG.getConstant(0, dl, VT);
17683 // lsb(x) = (x & -x)
17684 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17685 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17687 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17688 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17689 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17690 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17691 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17692 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17695 // cttz(x) = ctpop(lsb - 1)
17696 SDValue One = DAG.getConstant(1, dl, VT);
17697 return DAG.getNode(ISD::CTPOP, dl, VT,
17698 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17701 assert(Op.getOpcode() == ISD::CTTZ &&
17702 "Only scalar CTTZ requires custom lowering");
17704 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17705 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17706 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17708 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17711 DAG.getConstant(NumBits, dl, VT),
17712 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17715 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17718 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17719 // ones, and then concatenate the result back.
17720 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17721 MVT VT = Op.getSimpleValueType();
17723 assert(VT.is256BitVector() && VT.isInteger() &&
17724 "Unsupported value type for operation");
17726 unsigned NumElems = VT.getVectorNumElements();
17729 // Extract the LHS vectors
17730 SDValue LHS = Op.getOperand(0);
17731 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17732 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17734 // Extract the RHS vectors
17735 SDValue RHS = Op.getOperand(1);
17736 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17737 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17739 MVT EltVT = VT.getVectorElementType();
17740 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17742 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17743 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17744 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17747 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17748 if (Op.getValueType() == MVT::i1)
17749 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17750 Op.getOperand(0), Op.getOperand(1));
17751 assert(Op.getSimpleValueType().is256BitVector() &&
17752 Op.getSimpleValueType().isInteger() &&
17753 "Only handle AVX 256-bit vector integer operation");
17754 return Lower256IntArith(Op, DAG);
17757 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17758 if (Op.getValueType() == MVT::i1)
17759 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17760 Op.getOperand(0), Op.getOperand(1));
17761 assert(Op.getSimpleValueType().is256BitVector() &&
17762 Op.getSimpleValueType().isInteger() &&
17763 "Only handle AVX 256-bit vector integer operation");
17764 return Lower256IntArith(Op, DAG);
17767 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17768 assert(Op.getSimpleValueType().is256BitVector() &&
17769 Op.getSimpleValueType().isInteger() &&
17770 "Only handle AVX 256-bit vector integer operation");
17771 return Lower256IntArith(Op, DAG);
17774 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17775 SelectionDAG &DAG) {
17777 MVT VT = Op.getSimpleValueType();
17780 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17782 // Decompose 256-bit ops into smaller 128-bit ops.
17783 if (VT.is256BitVector() && !Subtarget->hasInt256())
17784 return Lower256IntArith(Op, DAG);
17786 SDValue A = Op.getOperand(0);
17787 SDValue B = Op.getOperand(1);
17789 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17790 // pairs, multiply and truncate.
17791 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17792 if (Subtarget->hasInt256()) {
17793 if (VT == MVT::v32i8) {
17794 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17795 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17796 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17797 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17798 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17799 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17800 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17801 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17802 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17803 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17806 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17807 return DAG.getNode(
17808 ISD::TRUNCATE, dl, VT,
17809 DAG.getNode(ISD::MUL, dl, ExVT,
17810 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17811 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17814 assert(VT == MVT::v16i8 &&
17815 "Pre-AVX2 support only supports v16i8 multiplication");
17816 MVT ExVT = MVT::v8i16;
17818 // Extract the lo parts and sign extend to i16
17820 if (Subtarget->hasSSE41()) {
17821 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17822 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17824 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17825 -1, 4, -1, 5, -1, 6, -1, 7};
17826 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17827 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17828 ALo = DAG.getBitcast(ExVT, ALo);
17829 BLo = DAG.getBitcast(ExVT, BLo);
17830 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17831 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17834 // Extract the hi parts and sign extend to i16
17836 if (Subtarget->hasSSE41()) {
17837 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17838 -1, -1, -1, -1, -1, -1, -1, -1};
17839 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17840 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17841 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17842 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17844 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17845 -1, 12, -1, 13, -1, 14, -1, 15};
17846 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17847 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17848 AHi = DAG.getBitcast(ExVT, AHi);
17849 BHi = DAG.getBitcast(ExVT, BHi);
17850 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17851 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17854 // Multiply, mask the lower 8bits of the lo/hi results and pack
17855 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17856 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17857 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17858 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17859 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17862 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17863 if (VT == MVT::v4i32) {
17864 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17865 "Should not custom lower when pmuldq is available!");
17867 // Extract the odd parts.
17868 static const int UnpackMask[] = { 1, -1, 3, -1 };
17869 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17870 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17872 // Multiply the even parts.
17873 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17874 // Now multiply odd parts.
17875 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17877 Evens = DAG.getBitcast(VT, Evens);
17878 Odds = DAG.getBitcast(VT, Odds);
17880 // Merge the two vectors back together with a shuffle. This expands into 2
17882 static const int ShufMask[] = { 0, 4, 2, 6 };
17883 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17886 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17887 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17889 // Ahi = psrlqi(a, 32);
17890 // Bhi = psrlqi(b, 32);
17892 // AloBlo = pmuludq(a, b);
17893 // AloBhi = pmuludq(a, Bhi);
17894 // AhiBlo = pmuludq(Ahi, b);
17896 // AloBhi = psllqi(AloBhi, 32);
17897 // AhiBlo = psllqi(AhiBlo, 32);
17898 // return AloBlo + AloBhi + AhiBlo;
17900 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17901 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17903 SDValue AhiBlo = Ahi;
17904 SDValue AloBhi = Bhi;
17905 // Bit cast to 32-bit vectors for MULUDQ
17906 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17907 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17908 A = DAG.getBitcast(MulVT, A);
17909 B = DAG.getBitcast(MulVT, B);
17910 Ahi = DAG.getBitcast(MulVT, Ahi);
17911 Bhi = DAG.getBitcast(MulVT, Bhi);
17913 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17914 // After shifting right const values the result may be all-zero.
17915 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17916 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17917 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17919 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17920 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17921 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17924 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17925 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17928 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17929 assert(Subtarget->isTargetWin64() && "Unexpected target");
17930 EVT VT = Op.getValueType();
17931 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17932 "Unexpected return type for lowering");
17936 switch (Op->getOpcode()) {
17937 default: llvm_unreachable("Unexpected request for libcall!");
17938 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17939 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17940 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17941 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17942 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17943 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17947 SDValue InChain = DAG.getEntryNode();
17949 TargetLowering::ArgListTy Args;
17950 TargetLowering::ArgListEntry Entry;
17951 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17952 EVT ArgVT = Op->getOperand(i).getValueType();
17953 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17954 "Unexpected argument type for lowering");
17955 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17956 Entry.Node = StackPtr;
17957 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17959 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17960 Entry.Ty = PointerType::get(ArgTy,0);
17961 Entry.isSExt = false;
17962 Entry.isZExt = false;
17963 Args.push_back(Entry);
17966 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17967 getPointerTy(DAG.getDataLayout()));
17969 TargetLowering::CallLoweringInfo CLI(DAG);
17970 CLI.setDebugLoc(dl).setChain(InChain)
17971 .setCallee(getLibcallCallingConv(LC),
17972 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17973 Callee, std::move(Args), 0)
17974 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17976 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17977 return DAG.getBitcast(VT, CallInfo.first);
17980 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17981 SelectionDAG &DAG) {
17982 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17983 EVT VT = Op0.getValueType();
17986 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17987 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17989 // PMULxD operations multiply each even value (starting at 0) of LHS with
17990 // the related value of RHS and produce a widen result.
17991 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17992 // => <2 x i64> <ae|cg>
17994 // In other word, to have all the results, we need to perform two PMULxD:
17995 // 1. one with the even values.
17996 // 2. one with the odd values.
17997 // To achieve #2, with need to place the odd values at an even position.
17999 // Place the odd value at an even position (basically, shift all values 1
18000 // step to the left):
18001 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18002 // <a|b|c|d> => <b|undef|d|undef>
18003 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18004 // <e|f|g|h> => <f|undef|h|undef>
18005 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18007 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18009 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18010 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18012 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18013 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18014 // => <2 x i64> <ae|cg>
18015 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18016 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18017 // => <2 x i64> <bf|dh>
18018 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18020 // Shuffle it back into the right order.
18021 SDValue Highs, Lows;
18022 if (VT == MVT::v8i32) {
18023 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18024 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18025 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18026 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18028 const int HighMask[] = {1, 5, 3, 7};
18029 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18030 const int LowMask[] = {0, 4, 2, 6};
18031 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18034 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18035 // unsigned multiply.
18036 if (IsSigned && !Subtarget->hasSSE41()) {
18037 SDValue ShAmt = DAG.getConstant(
18039 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
18040 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18041 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18042 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18043 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18045 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18046 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18049 // The first result of MUL_LOHI is actually the low value, followed by the
18051 SDValue Ops[] = {Lows, Highs};
18052 return DAG.getMergeValues(Ops, dl);
18055 // Return true if the required (according to Opcode) shift-imm form is natively
18056 // supported by the Subtarget
18057 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18059 if (VT.getScalarSizeInBits() < 16)
18062 if (VT.is512BitVector() &&
18063 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
18066 bool LShift = VT.is128BitVector() ||
18067 (VT.is256BitVector() && Subtarget->hasInt256());
18069 bool AShift = LShift && (Subtarget->hasVLX() ||
18070 (VT != MVT::v2i64 && VT != MVT::v4i64));
18071 return (Opcode == ISD::SRA) ? AShift : LShift;
18074 // The shift amount is a variable, but it is the same for all vector lanes.
18075 // These instructions are defined together with shift-immediate.
18077 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18079 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18082 // Return true if the required (according to Opcode) variable-shift form is
18083 // natively supported by the Subtarget
18084 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18087 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18090 // vXi16 supported only on AVX-512, BWI
18091 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18094 if (VT.is512BitVector() || Subtarget->hasVLX())
18097 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18098 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18099 return (Opcode == ISD::SRA) ? AShift : LShift;
18102 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18103 const X86Subtarget *Subtarget) {
18104 MVT VT = Op.getSimpleValueType();
18106 SDValue R = Op.getOperand(0);
18107 SDValue Amt = Op.getOperand(1);
18109 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18110 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18112 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18113 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18114 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18115 SDValue Ex = DAG.getBitcast(ExVT, R);
18117 if (ShiftAmt >= 32) {
18118 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18120 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18121 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18122 ShiftAmt - 32, DAG);
18123 if (VT == MVT::v2i64)
18124 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18125 if (VT == MVT::v4i64)
18126 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18127 {9, 1, 11, 3, 13, 5, 15, 7});
18129 // SRA upper i32, SHL whole i64 and select lower i32.
18130 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18133 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18134 Lower = DAG.getBitcast(ExVT, Lower);
18135 if (VT == MVT::v2i64)
18136 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18137 if (VT == MVT::v4i64)
18138 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18139 {8, 1, 10, 3, 12, 5, 14, 7});
18141 return DAG.getBitcast(VT, Ex);
18144 // Optimize shl/srl/sra with constant shift amount.
18145 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18146 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18147 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18149 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18150 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18152 // i64 SRA needs to be performed as partial shifts.
18153 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18154 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18155 return ArithmeticShiftRight64(ShiftAmt);
18157 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
18158 unsigned NumElts = VT.getVectorNumElements();
18159 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18161 // Simple i8 add case
18162 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18163 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18165 // ashr(R, 7) === cmp_slt(R, 0)
18166 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18167 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18168 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18171 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18172 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18175 if (Op.getOpcode() == ISD::SHL) {
18176 // Make a large shift.
18177 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18179 SHL = DAG.getBitcast(VT, SHL);
18180 // Zero out the rightmost bits.
18181 SmallVector<SDValue, 32> V(
18182 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
18183 return DAG.getNode(ISD::AND, dl, VT, SHL,
18184 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18186 if (Op.getOpcode() == ISD::SRL) {
18187 // Make a large shift.
18188 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18190 SRL = DAG.getBitcast(VT, SRL);
18191 // Zero out the leftmost bits.
18192 SmallVector<SDValue, 32> V(
18193 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18194 return DAG.getNode(ISD::AND, dl, VT, SRL,
18195 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18197 if (Op.getOpcode() == ISD::SRA) {
18198 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18199 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18200 SmallVector<SDValue, 32> V(NumElts,
18201 DAG.getConstant(128 >> ShiftAmt, dl,
18203 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18204 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18205 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18208 llvm_unreachable("Unknown shift opcode.");
18213 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18214 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18215 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18217 // Peek through any splat that was introduced for i64 shift vectorization.
18218 int SplatIndex = -1;
18219 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18220 if (SVN->isSplat()) {
18221 SplatIndex = SVN->getSplatIndex();
18222 Amt = Amt.getOperand(0);
18223 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18224 "Splat shuffle referencing second operand");
18227 if (Amt.getOpcode() != ISD::BITCAST ||
18228 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18231 Amt = Amt.getOperand(0);
18232 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18233 VT.getVectorNumElements();
18234 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18235 uint64_t ShiftAmt = 0;
18236 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18237 for (unsigned i = 0; i != Ratio; ++i) {
18238 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18242 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18245 // Check remaining shift amounts (if not a splat).
18246 if (SplatIndex < 0) {
18247 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18248 uint64_t ShAmt = 0;
18249 for (unsigned j = 0; j != Ratio; ++j) {
18250 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18254 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18256 if (ShAmt != ShiftAmt)
18261 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18262 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18264 if (Op.getOpcode() == ISD::SRA)
18265 return ArithmeticShiftRight64(ShiftAmt);
18271 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18272 const X86Subtarget* Subtarget) {
18273 MVT VT = Op.getSimpleValueType();
18275 SDValue R = Op.getOperand(0);
18276 SDValue Amt = Op.getOperand(1);
18278 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18279 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18281 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18282 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18284 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18286 EVT EltVT = VT.getVectorElementType();
18288 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18289 // Check if this build_vector node is doing a splat.
18290 // If so, then set BaseShAmt equal to the splat value.
18291 BaseShAmt = BV->getSplatValue();
18292 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18293 BaseShAmt = SDValue();
18295 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18296 Amt = Amt.getOperand(0);
18298 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18299 if (SVN && SVN->isSplat()) {
18300 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18301 SDValue InVec = Amt.getOperand(0);
18302 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18303 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18304 "Unexpected shuffle index found!");
18305 BaseShAmt = InVec.getOperand(SplatIdx);
18306 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18307 if (ConstantSDNode *C =
18308 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18309 if (C->getZExtValue() == SplatIdx)
18310 BaseShAmt = InVec.getOperand(1);
18315 // Avoid introducing an extract element from a shuffle.
18316 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18317 DAG.getIntPtrConstant(SplatIdx, dl));
18321 if (BaseShAmt.getNode()) {
18322 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18323 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18324 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18325 else if (EltVT.bitsLT(MVT::i32))
18326 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18328 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18332 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18333 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18334 Amt.getOpcode() == ISD::BITCAST &&
18335 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18336 Amt = Amt.getOperand(0);
18337 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18338 VT.getVectorNumElements();
18339 std::vector<SDValue> Vals(Ratio);
18340 for (unsigned i = 0; i != Ratio; ++i)
18341 Vals[i] = Amt.getOperand(i);
18342 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18343 for (unsigned j = 0; j != Ratio; ++j)
18344 if (Vals[j] != Amt.getOperand(i + j))
18348 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18349 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18354 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18355 SelectionDAG &DAG) {
18356 MVT VT = Op.getSimpleValueType();
18358 SDValue R = Op.getOperand(0);
18359 SDValue Amt = Op.getOperand(1);
18361 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18362 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18364 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18367 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18370 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18373 // XOP has 128-bit variable logical/arithmetic shifts.
18374 // +ve/-ve Amt = shift left/right.
18375 if (Subtarget->hasXOP() &&
18376 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18377 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18378 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18379 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18380 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18382 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18383 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18384 if (Op.getOpcode() == ISD::SRA)
18385 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18388 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18389 // shifts per-lane and then shuffle the partial results back together.
18390 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18391 // Splat the shift amounts so the scalar shifts above will catch it.
18392 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18393 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18394 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18395 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18396 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18399 // i64 vector arithmetic shift can be emulated with the transform:
18400 // M = lshr(SIGN_BIT, Amt)
18401 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18402 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18403 Op.getOpcode() == ISD::SRA) {
18404 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18405 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18406 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18407 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18408 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18412 // If possible, lower this packed shift into a vector multiply instead of
18413 // expanding it into a sequence of scalar shifts.
18414 // Do this only if the vector shift count is a constant build_vector.
18415 if (Op.getOpcode() == ISD::SHL &&
18416 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18417 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18418 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18419 SmallVector<SDValue, 8> Elts;
18420 EVT SVT = VT.getScalarType();
18421 unsigned SVTBits = SVT.getSizeInBits();
18422 const APInt &One = APInt(SVTBits, 1);
18423 unsigned NumElems = VT.getVectorNumElements();
18425 for (unsigned i=0; i !=NumElems; ++i) {
18426 SDValue Op = Amt->getOperand(i);
18427 if (Op->getOpcode() == ISD::UNDEF) {
18428 Elts.push_back(Op);
18432 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18433 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18434 uint64_t ShAmt = C.getZExtValue();
18435 if (ShAmt >= SVTBits) {
18436 Elts.push_back(DAG.getUNDEF(SVT));
18439 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18441 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18442 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18445 // Lower SHL with variable shift amount.
18446 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18447 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18449 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18450 DAG.getConstant(0x3f800000U, dl, VT));
18451 Op = DAG.getBitcast(MVT::v4f32, Op);
18452 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18453 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18456 // If possible, lower this shift as a sequence of two shifts by
18457 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18459 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18461 // Could be rewritten as:
18462 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18464 // The advantage is that the two shifts from the example would be
18465 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18466 // the vector shift into four scalar shifts plus four pairs of vector
18468 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18469 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18470 unsigned TargetOpcode = X86ISD::MOVSS;
18471 bool CanBeSimplified;
18472 // The splat value for the first packed shift (the 'X' from the example).
18473 SDValue Amt1 = Amt->getOperand(0);
18474 // The splat value for the second packed shift (the 'Y' from the example).
18475 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18476 Amt->getOperand(2);
18478 // See if it is possible to replace this node with a sequence of
18479 // two shifts followed by a MOVSS/MOVSD
18480 if (VT == MVT::v4i32) {
18481 // Check if it is legal to use a MOVSS.
18482 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18483 Amt2 == Amt->getOperand(3);
18484 if (!CanBeSimplified) {
18485 // Otherwise, check if we can still simplify this node using a MOVSD.
18486 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18487 Amt->getOperand(2) == Amt->getOperand(3);
18488 TargetOpcode = X86ISD::MOVSD;
18489 Amt2 = Amt->getOperand(2);
18492 // Do similar checks for the case where the machine value type
18494 CanBeSimplified = Amt1 == Amt->getOperand(1);
18495 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18496 CanBeSimplified = Amt2 == Amt->getOperand(i);
18498 if (!CanBeSimplified) {
18499 TargetOpcode = X86ISD::MOVSD;
18500 CanBeSimplified = true;
18501 Amt2 = Amt->getOperand(4);
18502 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18503 CanBeSimplified = Amt1 == Amt->getOperand(i);
18504 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18505 CanBeSimplified = Amt2 == Amt->getOperand(j);
18509 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18510 isa<ConstantSDNode>(Amt2)) {
18511 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18512 EVT CastVT = MVT::v4i32;
18514 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18515 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18517 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18518 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18519 if (TargetOpcode == X86ISD::MOVSD)
18520 CastVT = MVT::v2i64;
18521 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18522 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18523 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18525 return DAG.getBitcast(VT, Result);
18529 // v4i32 Non Uniform Shifts.
18530 // If the shift amount is constant we can shift each lane using the SSE2
18531 // immediate shifts, else we need to zero-extend each lane to the lower i64
18532 // and shift using the SSE2 variable shifts.
18533 // The separate results can then be blended together.
18534 if (VT == MVT::v4i32) {
18535 unsigned Opc = Op.getOpcode();
18536 SDValue Amt0, Amt1, Amt2, Amt3;
18537 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18538 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18539 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18540 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18541 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18543 // ISD::SHL is handled above but we include it here for completeness.
18546 llvm_unreachable("Unknown target vector shift node");
18548 Opc = X86ISD::VSHL;
18551 Opc = X86ISD::VSRL;
18554 Opc = X86ISD::VSRA;
18557 // The SSE2 shifts use the lower i64 as the same shift amount for
18558 // all lanes and the upper i64 is ignored. These shuffle masks
18559 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18560 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18561 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18562 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18563 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18564 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18567 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18568 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18569 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18570 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18571 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18572 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18573 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18576 if (VT == MVT::v16i8 ||
18577 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18578 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18579 unsigned ShiftOpcode = Op->getOpcode();
18581 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18582 // On SSE41 targets we make use of the fact that VSELECT lowers
18583 // to PBLENDVB which selects bytes based just on the sign bit.
18584 if (Subtarget->hasSSE41()) {
18585 V0 = DAG.getBitcast(VT, V0);
18586 V1 = DAG.getBitcast(VT, V1);
18587 Sel = DAG.getBitcast(VT, Sel);
18588 return DAG.getBitcast(SelVT,
18589 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18591 // On pre-SSE41 targets we test for the sign bit by comparing to
18592 // zero - a negative value will set all bits of the lanes to true
18593 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18594 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18595 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18596 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18599 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18600 // We can safely do this using i16 shifts as we're only interested in
18601 // the 3 lower bits of each byte.
18602 Amt = DAG.getBitcast(ExtVT, Amt);
18603 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18604 Amt = DAG.getBitcast(VT, Amt);
18606 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18607 // r = VSELECT(r, shift(r, 4), a);
18609 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18610 R = SignBitSelect(VT, Amt, M, R);
18613 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18615 // r = VSELECT(r, shift(r, 2), a);
18616 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18617 R = SignBitSelect(VT, Amt, M, R);
18620 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18622 // return VSELECT(r, shift(r, 1), a);
18623 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18624 R = SignBitSelect(VT, Amt, M, R);
18628 if (Op->getOpcode() == ISD::SRA) {
18629 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18630 // so we can correctly sign extend. We don't care what happens to the
18632 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18633 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18634 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18635 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18636 ALo = DAG.getBitcast(ExtVT, ALo);
18637 AHi = DAG.getBitcast(ExtVT, AHi);
18638 RLo = DAG.getBitcast(ExtVT, RLo);
18639 RHi = DAG.getBitcast(ExtVT, RHi);
18641 // r = VSELECT(r, shift(r, 4), a);
18642 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18643 DAG.getConstant(4, dl, ExtVT));
18644 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18645 DAG.getConstant(4, dl, ExtVT));
18646 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18647 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18650 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18651 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18653 // r = VSELECT(r, shift(r, 2), a);
18654 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18655 DAG.getConstant(2, dl, ExtVT));
18656 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18657 DAG.getConstant(2, dl, ExtVT));
18658 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18659 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18662 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18663 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18665 // r = VSELECT(r, shift(r, 1), a);
18666 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18667 DAG.getConstant(1, dl, ExtVT));
18668 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18669 DAG.getConstant(1, dl, ExtVT));
18670 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18671 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18673 // Logical shift the result back to the lower byte, leaving a zero upper
18675 // meaning that we can safely pack with PACKUSWB.
18677 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18679 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18680 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18684 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18685 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18686 // solution better.
18687 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18688 MVT ExtVT = MVT::v8i32;
18690 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18691 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18692 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18693 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18694 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18697 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18698 MVT ExtVT = MVT::v8i32;
18699 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18700 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18701 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18702 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18703 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18704 ALo = DAG.getBitcast(ExtVT, ALo);
18705 AHi = DAG.getBitcast(ExtVT, AHi);
18706 RLo = DAG.getBitcast(ExtVT, RLo);
18707 RHi = DAG.getBitcast(ExtVT, RHi);
18708 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18709 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18710 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18711 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18712 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18715 if (VT == MVT::v8i16) {
18716 unsigned ShiftOpcode = Op->getOpcode();
18718 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18719 // On SSE41 targets we make use of the fact that VSELECT lowers
18720 // to PBLENDVB which selects bytes based just on the sign bit.
18721 if (Subtarget->hasSSE41()) {
18722 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18723 V0 = DAG.getBitcast(ExtVT, V0);
18724 V1 = DAG.getBitcast(ExtVT, V1);
18725 Sel = DAG.getBitcast(ExtVT, Sel);
18726 return DAG.getBitcast(
18727 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18729 // On pre-SSE41 targets we splat the sign bit - a negative value will
18730 // set all bits of the lanes to true and VSELECT uses that in
18731 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18733 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18734 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18737 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18738 if (Subtarget->hasSSE41()) {
18739 // On SSE41 targets we need to replicate the shift mask in both
18740 // bytes for PBLENDVB.
18743 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18744 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18746 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18749 // r = VSELECT(r, shift(r, 8), a);
18750 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18751 R = SignBitSelect(Amt, M, R);
18754 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18756 // r = VSELECT(r, shift(r, 4), a);
18757 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18758 R = SignBitSelect(Amt, M, R);
18761 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18763 // r = VSELECT(r, shift(r, 2), a);
18764 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18765 R = SignBitSelect(Amt, M, R);
18768 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18770 // return VSELECT(r, shift(r, 1), a);
18771 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18772 R = SignBitSelect(Amt, M, R);
18776 // Decompose 256-bit shifts into smaller 128-bit shifts.
18777 if (VT.is256BitVector()) {
18778 unsigned NumElems = VT.getVectorNumElements();
18779 MVT EltVT = VT.getVectorElementType();
18780 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18782 // Extract the two vectors
18783 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18784 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18786 // Recreate the shift amount vectors
18787 SDValue Amt1, Amt2;
18788 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18789 // Constant shift amount
18790 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18791 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18792 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18794 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18795 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18797 // Variable shift amount
18798 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18799 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18802 // Issue new vector shifts for the smaller types
18803 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18804 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18806 // Concatenate the result back
18807 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18813 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18814 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18815 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18816 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18817 // has only one use.
18818 SDNode *N = Op.getNode();
18819 SDValue LHS = N->getOperand(0);
18820 SDValue RHS = N->getOperand(1);
18821 unsigned BaseOp = 0;
18824 switch (Op.getOpcode()) {
18825 default: llvm_unreachable("Unknown ovf instruction!");
18827 // A subtract of one will be selected as a INC. Note that INC doesn't
18828 // set CF, so we can't do this for UADDO.
18829 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18831 BaseOp = X86ISD::INC;
18832 Cond = X86::COND_O;
18835 BaseOp = X86ISD::ADD;
18836 Cond = X86::COND_O;
18839 BaseOp = X86ISD::ADD;
18840 Cond = X86::COND_B;
18843 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18844 // set CF, so we can't do this for USUBO.
18845 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18847 BaseOp = X86ISD::DEC;
18848 Cond = X86::COND_O;
18851 BaseOp = X86ISD::SUB;
18852 Cond = X86::COND_O;
18855 BaseOp = X86ISD::SUB;
18856 Cond = X86::COND_B;
18859 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18860 Cond = X86::COND_O;
18862 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18863 if (N->getValueType(0) == MVT::i8) {
18864 BaseOp = X86ISD::UMUL8;
18865 Cond = X86::COND_O;
18868 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18870 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18873 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18874 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18875 SDValue(Sum.getNode(), 2));
18877 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18881 // Also sets EFLAGS.
18882 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18883 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18886 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18887 DAG.getConstant(Cond, DL, MVT::i32),
18888 SDValue(Sum.getNode(), 1));
18890 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18893 /// Returns true if the operand type is exactly twice the native width, and
18894 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18895 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18896 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18897 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18898 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18901 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18902 else if (OpWidth == 128)
18903 return Subtarget->hasCmpxchg16b();
18908 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18909 return needsCmpXchgNb(SI->getValueOperand()->getType());
18912 // Note: this turns large loads into lock cmpxchg8b/16b.
18913 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18914 TargetLowering::AtomicExpansionKind
18915 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18916 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18917 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
18918 : AtomicExpansionKind::None;
18921 TargetLowering::AtomicExpansionKind
18922 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18923 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18924 Type *MemType = AI->getType();
18926 // If the operand is too big, we must see if cmpxchg8/16b is available
18927 // and default to library calls otherwise.
18928 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18929 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
18930 : AtomicExpansionKind::None;
18933 AtomicRMWInst::BinOp Op = AI->getOperation();
18936 llvm_unreachable("Unknown atomic operation");
18937 case AtomicRMWInst::Xchg:
18938 case AtomicRMWInst::Add:
18939 case AtomicRMWInst::Sub:
18940 // It's better to use xadd, xsub or xchg for these in all cases.
18941 return AtomicExpansionKind::None;
18942 case AtomicRMWInst::Or:
18943 case AtomicRMWInst::And:
18944 case AtomicRMWInst::Xor:
18945 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18946 // prefix to a normal instruction for these operations.
18947 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
18948 : AtomicExpansionKind::None;
18949 case AtomicRMWInst::Nand:
18950 case AtomicRMWInst::Max:
18951 case AtomicRMWInst::Min:
18952 case AtomicRMWInst::UMax:
18953 case AtomicRMWInst::UMin:
18954 // These always require a non-trivial set of data operations on x86. We must
18955 // use a cmpxchg loop.
18956 return AtomicExpansionKind::CmpXChg;
18960 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18961 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18962 // no-sse2). There isn't any reason to disable it if the target processor
18964 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18968 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18969 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18970 Type *MemType = AI->getType();
18971 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18972 // there is no benefit in turning such RMWs into loads, and it is actually
18973 // harmful as it introduces a mfence.
18974 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18977 auto Builder = IRBuilder<>(AI);
18978 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18979 auto SynchScope = AI->getSynchScope();
18980 // We must restrict the ordering to avoid generating loads with Release or
18981 // ReleaseAcquire orderings.
18982 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18983 auto Ptr = AI->getPointerOperand();
18985 // Before the load we need a fence. Here is an example lifted from
18986 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18989 // x.store(1, relaxed);
18990 // r1 = y.fetch_add(0, release);
18992 // y.fetch_add(42, acquire);
18993 // r2 = x.load(relaxed);
18994 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18995 // lowered to just a load without a fence. A mfence flushes the store buffer,
18996 // making the optimization clearly correct.
18997 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18998 // otherwise, we might be able to be more aggressive on relaxed idempotent
18999 // rmw. In practice, they do not look useful, so we don't try to be
19000 // especially clever.
19001 if (SynchScope == SingleThread)
19002 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19003 // the IR level, so we must wrap it in an intrinsic.
19006 if (!hasMFENCE(*Subtarget))
19007 // FIXME: it might make sense to use a locked operation here but on a
19008 // different cache-line to prevent cache-line bouncing. In practice it
19009 // is probably a small win, and x86 processors without mfence are rare
19010 // enough that we do not bother.
19014 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
19015 Builder.CreateCall(MFence, {});
19017 // Finally we can emit the atomic load.
19018 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19019 AI->getType()->getPrimitiveSizeInBits());
19020 Loaded->setAtomic(Order, SynchScope);
19021 AI->replaceAllUsesWith(Loaded);
19022 AI->eraseFromParent();
19026 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19027 SelectionDAG &DAG) {
19029 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19030 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19031 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19032 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19034 // The only fence that needs an instruction is a sequentially-consistent
19035 // cross-thread fence.
19036 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19037 if (hasMFENCE(*Subtarget))
19038 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19040 SDValue Chain = Op.getOperand(0);
19041 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19043 DAG.getRegister(X86::ESP, MVT::i32), // Base
19044 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19045 DAG.getRegister(0, MVT::i32), // Index
19046 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19047 DAG.getRegister(0, MVT::i32), // Segment.
19051 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19052 return SDValue(Res, 0);
19055 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19056 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19059 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19060 SelectionDAG &DAG) {
19061 MVT T = Op.getSimpleValueType();
19065 switch(T.SimpleTy) {
19066 default: llvm_unreachable("Invalid value type!");
19067 case MVT::i8: Reg = X86::AL; size = 1; break;
19068 case MVT::i16: Reg = X86::AX; size = 2; break;
19069 case MVT::i32: Reg = X86::EAX; size = 4; break;
19071 assert(Subtarget->is64Bit() && "Node not type legal!");
19072 Reg = X86::RAX; size = 8;
19075 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19076 Op.getOperand(2), SDValue());
19077 SDValue Ops[] = { cpIn.getValue(0),
19080 DAG.getTargetConstant(size, DL, MVT::i8),
19081 cpIn.getValue(1) };
19082 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19083 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19084 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19088 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19089 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19090 MVT::i32, cpOut.getValue(2));
19091 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19092 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19095 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19096 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19097 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19101 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19102 SelectionDAG &DAG) {
19103 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19104 MVT DstVT = Op.getSimpleValueType();
19106 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19107 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19108 if (DstVT != MVT::f64)
19109 // This conversion needs to be expanded.
19112 SDValue InVec = Op->getOperand(0);
19114 unsigned NumElts = SrcVT.getVectorNumElements();
19115 EVT SVT = SrcVT.getVectorElementType();
19117 // Widen the vector in input in the case of MVT::v2i32.
19118 // Example: from MVT::v2i32 to MVT::v4i32.
19119 SmallVector<SDValue, 16> Elts;
19120 for (unsigned i = 0, e = NumElts; i != e; ++i)
19121 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19122 DAG.getIntPtrConstant(i, dl)));
19124 // Explicitly mark the extra elements as Undef.
19125 Elts.append(NumElts, DAG.getUNDEF(SVT));
19127 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19128 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19129 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19130 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19131 DAG.getIntPtrConstant(0, dl));
19134 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19135 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19136 assert((DstVT == MVT::i64 ||
19137 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19138 "Unexpected custom BITCAST");
19139 // i64 <=> MMX conversions are Legal.
19140 if (SrcVT==MVT::i64 && DstVT.isVector())
19142 if (DstVT==MVT::i64 && SrcVT.isVector())
19144 // MMX <=> MMX conversions are Legal.
19145 if (SrcVT.isVector() && DstVT.isVector())
19147 // All other conversions need to be expanded.
19151 /// Compute the horizontal sum of bytes in V for the elements of VT.
19153 /// Requires V to be a byte vector and VT to be an integer vector type with
19154 /// wider elements than V's type. The width of the elements of VT determines
19155 /// how many bytes of V are summed horizontally to produce each element of the
19157 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19158 const X86Subtarget *Subtarget,
19159 SelectionDAG &DAG) {
19161 MVT ByteVecVT = V.getSimpleValueType();
19162 MVT EltVT = VT.getVectorElementType();
19163 int NumElts = VT.getVectorNumElements();
19164 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19165 "Expected value to have byte element type.");
19166 assert(EltVT != MVT::i8 &&
19167 "Horizontal byte sum only makes sense for wider elements!");
19168 unsigned VecSize = VT.getSizeInBits();
19169 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19171 // PSADBW instruction horizontally add all bytes and leave the result in i64
19172 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19173 if (EltVT == MVT::i64) {
19174 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19175 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
19176 return DAG.getBitcast(VT, V);
19179 if (EltVT == MVT::i32) {
19180 // We unpack the low half and high half into i32s interleaved with zeros so
19181 // that we can use PSADBW to horizontally sum them. The most useful part of
19182 // this is that it lines up the results of two PSADBW instructions to be
19183 // two v2i64 vectors which concatenated are the 4 population counts. We can
19184 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19185 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19186 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19187 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19189 // Do the horizontal sums into two v2i64s.
19190 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19191 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19192 DAG.getBitcast(ByteVecVT, Low), Zeros);
19193 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19194 DAG.getBitcast(ByteVecVT, High), Zeros);
19196 // Merge them together.
19197 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19198 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19199 DAG.getBitcast(ShortVecVT, Low),
19200 DAG.getBitcast(ShortVecVT, High));
19202 return DAG.getBitcast(VT, V);
19205 // The only element type left is i16.
19206 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19208 // To obtain pop count for each i16 element starting from the pop count for
19209 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19210 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19211 // directly supported.
19212 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19213 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19214 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19215 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19216 DAG.getBitcast(ByteVecVT, V));
19217 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19220 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19221 const X86Subtarget *Subtarget,
19222 SelectionDAG &DAG) {
19223 MVT VT = Op.getSimpleValueType();
19224 MVT EltVT = VT.getVectorElementType();
19225 unsigned VecSize = VT.getSizeInBits();
19227 // Implement a lookup table in register by using an algorithm based on:
19228 // http://wm.ite.pl/articles/sse-popcount.html
19230 // The general idea is that every lower byte nibble in the input vector is an
19231 // index into a in-register pre-computed pop count table. We then split up the
19232 // input vector in two new ones: (1) a vector with only the shifted-right
19233 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19234 // masked out higher ones) for each byte. PSHUB is used separately with both
19235 // to index the in-register table. Next, both are added and the result is a
19236 // i8 vector where each element contains the pop count for input byte.
19238 // To obtain the pop count for elements != i8, we follow up with the same
19239 // approach and use additional tricks as described below.
19241 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19242 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19243 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19244 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19246 int NumByteElts = VecSize / 8;
19247 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19248 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19249 SmallVector<SDValue, 16> LUTVec;
19250 for (int i = 0; i < NumByteElts; ++i)
19251 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19252 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19253 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19254 DAG.getConstant(0x0F, DL, MVT::i8));
19255 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19258 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19259 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19260 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19263 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19265 // The input vector is used as the shuffle mask that index elements into the
19266 // LUT. After counting low and high nibbles, add the vector to obtain the
19267 // final pop count per i8 element.
19268 SDValue HighPopCnt =
19269 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19270 SDValue LowPopCnt =
19271 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19272 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19274 if (EltVT == MVT::i8)
19277 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19280 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19281 const X86Subtarget *Subtarget,
19282 SelectionDAG &DAG) {
19283 MVT VT = Op.getSimpleValueType();
19284 assert(VT.is128BitVector() &&
19285 "Only 128-bit vector bitmath lowering supported.");
19287 int VecSize = VT.getSizeInBits();
19288 MVT EltVT = VT.getVectorElementType();
19289 int Len = EltVT.getSizeInBits();
19291 // This is the vectorized version of the "best" algorithm from
19292 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19293 // with a minor tweak to use a series of adds + shifts instead of vector
19294 // multiplications. Implemented for all integer vector types. We only use
19295 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19296 // much faster, even faster than using native popcnt instructions.
19298 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19299 MVT VT = V.getSimpleValueType();
19300 SmallVector<SDValue, 32> Shifters(
19301 VT.getVectorNumElements(),
19302 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19303 return DAG.getNode(OpCode, DL, VT, V,
19304 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19306 auto GetMask = [&](SDValue V, APInt Mask) {
19307 MVT VT = V.getSimpleValueType();
19308 SmallVector<SDValue, 32> Masks(
19309 VT.getVectorNumElements(),
19310 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19311 return DAG.getNode(ISD::AND, DL, VT, V,
19312 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19315 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19316 // x86, so set the SRL type to have elements at least i16 wide. This is
19317 // correct because all of our SRLs are followed immediately by a mask anyways
19318 // that handles any bits that sneak into the high bits of the byte elements.
19319 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19323 // v = v - ((v >> 1) & 0x55555555...)
19325 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19326 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19327 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19329 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19330 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19331 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19332 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19333 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19335 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19336 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19337 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19338 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19340 // At this point, V contains the byte-wise population count, and we are
19341 // merely doing a horizontal sum if necessary to get the wider element
19343 if (EltVT == MVT::i8)
19346 return LowerHorizontalByteSum(
19347 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19351 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19352 SelectionDAG &DAG) {
19353 MVT VT = Op.getSimpleValueType();
19354 // FIXME: Need to add AVX-512 support here!
19355 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19356 "Unknown CTPOP type to handle");
19357 SDLoc DL(Op.getNode());
19358 SDValue Op0 = Op.getOperand(0);
19360 if (!Subtarget->hasSSSE3()) {
19361 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19362 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19363 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19366 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19367 unsigned NumElems = VT.getVectorNumElements();
19369 // Extract each 128-bit vector, compute pop count and concat the result.
19370 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19371 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19373 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19374 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19375 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19378 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19381 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19382 SelectionDAG &DAG) {
19383 assert(Op.getValueType().isVector() &&
19384 "We only do custom lowering for vector population count.");
19385 return LowerVectorCTPOP(Op, Subtarget, DAG);
19388 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19389 SDNode *Node = Op.getNode();
19391 EVT T = Node->getValueType(0);
19392 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19393 DAG.getConstant(0, dl, T), Node->getOperand(2));
19394 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19395 cast<AtomicSDNode>(Node)->getMemoryVT(),
19396 Node->getOperand(0),
19397 Node->getOperand(1), negOp,
19398 cast<AtomicSDNode>(Node)->getMemOperand(),
19399 cast<AtomicSDNode>(Node)->getOrdering(),
19400 cast<AtomicSDNode>(Node)->getSynchScope());
19403 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19404 SDNode *Node = Op.getNode();
19406 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19408 // Convert seq_cst store -> xchg
19409 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19410 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19411 // (The only way to get a 16-byte store is cmpxchg16b)
19412 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19413 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19414 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19415 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19416 cast<AtomicSDNode>(Node)->getMemoryVT(),
19417 Node->getOperand(0),
19418 Node->getOperand(1), Node->getOperand(2),
19419 cast<AtomicSDNode>(Node)->getMemOperand(),
19420 cast<AtomicSDNode>(Node)->getOrdering(),
19421 cast<AtomicSDNode>(Node)->getSynchScope());
19422 return Swap.getValue(1);
19424 // Other atomic stores have a simple pattern.
19428 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19429 EVT VT = Op.getNode()->getSimpleValueType(0);
19431 // Let legalize expand this if it isn't a legal type yet.
19432 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19435 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19438 bool ExtraOp = false;
19439 switch (Op.getOpcode()) {
19440 default: llvm_unreachable("Invalid code");
19441 case ISD::ADDC: Opc = X86ISD::ADD; break;
19442 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19443 case ISD::SUBC: Opc = X86ISD::SUB; break;
19444 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19448 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19450 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19451 Op.getOperand(1), Op.getOperand(2));
19454 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19455 SelectionDAG &DAG) {
19456 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19458 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19459 // which returns the values as { float, float } (in XMM0) or
19460 // { double, double } (which is returned in XMM0, XMM1).
19462 SDValue Arg = Op.getOperand(0);
19463 EVT ArgVT = Arg.getValueType();
19464 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19466 TargetLowering::ArgListTy Args;
19467 TargetLowering::ArgListEntry Entry;
19471 Entry.isSExt = false;
19472 Entry.isZExt = false;
19473 Args.push_back(Entry);
19475 bool isF64 = ArgVT == MVT::f64;
19476 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19477 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19478 // the results are returned via SRet in memory.
19479 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19480 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19482 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19484 Type *RetTy = isF64
19485 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19486 : (Type*)VectorType::get(ArgTy, 4);
19488 TargetLowering::CallLoweringInfo CLI(DAG);
19489 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19490 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19492 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19495 // Returned in xmm0 and xmm1.
19496 return CallResult.first;
19498 // Returned in bits 0:31 and 32:64 xmm0.
19499 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19500 CallResult.first, DAG.getIntPtrConstant(0, dl));
19501 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19502 CallResult.first, DAG.getIntPtrConstant(1, dl));
19503 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19504 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19507 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19508 SelectionDAG &DAG) {
19509 assert(Subtarget->hasAVX512() &&
19510 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19512 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19513 EVT VT = N->getValue().getValueType();
19514 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19517 // X86 scatter kills mask register, so its type should be added to
19518 // the list of return values
19519 if (N->getNumValues() == 1) {
19520 SDValue Index = N->getIndex();
19521 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19522 !Index.getValueType().is512BitVector())
19523 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19525 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19526 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19527 N->getOperand(3), Index };
19529 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19530 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19531 return SDValue(NewScatter.getNode(), 0);
19536 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19537 SelectionDAG &DAG) {
19538 assert(Subtarget->hasAVX512() &&
19539 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19541 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19542 EVT VT = Op.getValueType();
19543 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19546 SDValue Index = N->getIndex();
19547 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19548 !Index.getValueType().is512BitVector()) {
19549 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19550 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19551 N->getOperand(3), Index };
19552 DAG.UpdateNodeOperands(N, Ops);
19557 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19558 SelectionDAG &DAG) const {
19559 // TODO: Eventually, the lowering of these nodes should be informed by or
19560 // deferred to the GC strategy for the function in which they appear. For
19561 // now, however, they must be lowered to something. Since they are logically
19562 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19563 // require special handling for these nodes), lower them as literal NOOPs for
19565 SmallVector<SDValue, 2> Ops;
19567 Ops.push_back(Op.getOperand(0));
19568 if (Op->getGluedNode())
19569 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19572 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19573 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19578 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19579 SelectionDAG &DAG) const {
19580 // TODO: Eventually, the lowering of these nodes should be informed by or
19581 // deferred to the GC strategy for the function in which they appear. For
19582 // now, however, they must be lowered to something. Since they are logically
19583 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19584 // require special handling for these nodes), lower them as literal NOOPs for
19586 SmallVector<SDValue, 2> Ops;
19588 Ops.push_back(Op.getOperand(0));
19589 if (Op->getGluedNode())
19590 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19593 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19594 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19599 /// LowerOperation - Provide custom lowering hooks for some operations.
19601 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19602 switch (Op.getOpcode()) {
19603 default: llvm_unreachable("Should not custom lower this!");
19604 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19605 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19606 return LowerCMP_SWAP(Op, Subtarget, DAG);
19607 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19608 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19609 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19610 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19611 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19612 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19613 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19614 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19615 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19616 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19617 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19618 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19619 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19620 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19621 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19622 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19623 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19624 case ISD::SHL_PARTS:
19625 case ISD::SRA_PARTS:
19626 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19627 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19628 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19629 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19630 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19631 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19632 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19633 case ISD::SIGN_EXTEND_VECTOR_INREG:
19634 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19635 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19636 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19637 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19638 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19640 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19641 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19642 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19643 case ISD::SETCC: return LowerSETCC(Op, DAG);
19644 case ISD::SELECT: return LowerSELECT(Op, DAG);
19645 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19646 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19647 case ISD::VASTART: return LowerVASTART(Op, DAG);
19648 case ISD::VAARG: return LowerVAARG(Op, DAG);
19649 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19650 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19651 case ISD::INTRINSIC_VOID:
19652 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19653 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19654 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19655 case ISD::FRAME_TO_ARGS_OFFSET:
19656 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19657 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19658 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19659 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19660 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19661 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19662 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19663 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19664 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
19665 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
19667 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19668 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19669 case ISD::UMUL_LOHI:
19670 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19673 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19679 case ISD::UMULO: return LowerXALUO(Op, DAG);
19680 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19681 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19685 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19686 case ISD::ADD: return LowerADD(Op, DAG);
19687 case ISD::SUB: return LowerSUB(Op, DAG);
19691 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19692 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19693 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19694 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19695 case ISD::GC_TRANSITION_START:
19696 return LowerGC_TRANSITION_START(Op, DAG);
19697 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19701 /// ReplaceNodeResults - Replace a node with an illegal result type
19702 /// with a new node built out of custom code.
19703 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19704 SmallVectorImpl<SDValue>&Results,
19705 SelectionDAG &DAG) const {
19707 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19708 switch (N->getOpcode()) {
19710 llvm_unreachable("Do not know how to custom type legalize this operation!");
19711 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19712 case X86ISD::FMINC:
19714 case X86ISD::FMAXC:
19715 case X86ISD::FMAX: {
19716 EVT VT = N->getValueType(0);
19717 if (VT != MVT::v2f32)
19718 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
19719 SDValue UNDEF = DAG.getUNDEF(VT);
19720 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19721 N->getOperand(0), UNDEF);
19722 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19723 N->getOperand(1), UNDEF);
19724 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19727 case ISD::SIGN_EXTEND_INREG:
19732 // We don't want to expand or promote these.
19739 case ISD::UDIVREM: {
19740 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19741 Results.push_back(V);
19744 case ISD::FP_TO_SINT:
19745 case ISD::FP_TO_UINT: {
19746 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19748 std::pair<SDValue,SDValue> Vals =
19749 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19750 SDValue FIST = Vals.first, StackSlot = Vals.second;
19751 if (FIST.getNode()) {
19752 EVT VT = N->getValueType(0);
19753 // Return a load from the stack slot.
19754 if (StackSlot.getNode())
19755 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19756 MachinePointerInfo(),
19757 false, false, false, 0));
19759 Results.push_back(FIST);
19763 case ISD::UINT_TO_FP: {
19764 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19765 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19766 N->getValueType(0) != MVT::v2f32)
19768 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19770 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19772 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19773 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19774 DAG.getBitcast(MVT::v2i64, VBias));
19775 Or = DAG.getBitcast(MVT::v2f64, Or);
19776 // TODO: Are there any fast-math-flags to propagate here?
19777 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19778 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19781 case ISD::FP_ROUND: {
19782 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19784 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19785 Results.push_back(V);
19788 case ISD::FP_EXTEND: {
19789 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19790 // No other ValueType for FP_EXTEND should reach this point.
19791 assert(N->getValueType(0) == MVT::v2f32 &&
19792 "Do not know how to legalize this Node");
19795 case ISD::INTRINSIC_W_CHAIN: {
19796 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19798 default : llvm_unreachable("Do not know how to custom type "
19799 "legalize this intrinsic operation!");
19800 case Intrinsic::x86_rdtsc:
19801 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19803 case Intrinsic::x86_rdtscp:
19804 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19806 case Intrinsic::x86_rdpmc:
19807 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19810 case ISD::READCYCLECOUNTER: {
19811 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19814 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19815 EVT T = N->getValueType(0);
19816 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19817 bool Regs64bit = T == MVT::i128;
19818 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19819 SDValue cpInL, cpInH;
19820 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19821 DAG.getConstant(0, dl, HalfT));
19822 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19823 DAG.getConstant(1, dl, HalfT));
19824 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19825 Regs64bit ? X86::RAX : X86::EAX,
19827 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19828 Regs64bit ? X86::RDX : X86::EDX,
19829 cpInH, cpInL.getValue(1));
19830 SDValue swapInL, swapInH;
19831 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19832 DAG.getConstant(0, dl, HalfT));
19833 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19834 DAG.getConstant(1, dl, HalfT));
19835 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19836 Regs64bit ? X86::RBX : X86::EBX,
19837 swapInL, cpInH.getValue(1));
19838 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19839 Regs64bit ? X86::RCX : X86::ECX,
19840 swapInH, swapInL.getValue(1));
19841 SDValue Ops[] = { swapInH.getValue(0),
19843 swapInH.getValue(1) };
19844 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19845 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19846 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19847 X86ISD::LCMPXCHG8_DAG;
19848 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19849 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19850 Regs64bit ? X86::RAX : X86::EAX,
19851 HalfT, Result.getValue(1));
19852 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19853 Regs64bit ? X86::RDX : X86::EDX,
19854 HalfT, cpOutL.getValue(2));
19855 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19857 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19858 MVT::i32, cpOutH.getValue(2));
19860 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19861 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19862 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19864 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19865 Results.push_back(Success);
19866 Results.push_back(EFLAGS.getValue(1));
19869 case ISD::ATOMIC_SWAP:
19870 case ISD::ATOMIC_LOAD_ADD:
19871 case ISD::ATOMIC_LOAD_SUB:
19872 case ISD::ATOMIC_LOAD_AND:
19873 case ISD::ATOMIC_LOAD_OR:
19874 case ISD::ATOMIC_LOAD_XOR:
19875 case ISD::ATOMIC_LOAD_NAND:
19876 case ISD::ATOMIC_LOAD_MIN:
19877 case ISD::ATOMIC_LOAD_MAX:
19878 case ISD::ATOMIC_LOAD_UMIN:
19879 case ISD::ATOMIC_LOAD_UMAX:
19880 case ISD::ATOMIC_LOAD: {
19881 // Delegate to generic TypeLegalization. Situations we can really handle
19882 // should have already been dealt with by AtomicExpandPass.cpp.
19885 case ISD::BITCAST: {
19886 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19887 EVT DstVT = N->getValueType(0);
19888 EVT SrcVT = N->getOperand(0)->getValueType(0);
19890 if (SrcVT != MVT::f64 ||
19891 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19894 unsigned NumElts = DstVT.getVectorNumElements();
19895 EVT SVT = DstVT.getVectorElementType();
19896 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19897 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19898 MVT::v2f64, N->getOperand(0));
19899 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19901 if (ExperimentalVectorWideningLegalization) {
19902 // If we are legalizing vectors by widening, we already have the desired
19903 // legal vector type, just return it.
19904 Results.push_back(ToVecInt);
19908 SmallVector<SDValue, 8> Elts;
19909 for (unsigned i = 0, e = NumElts; i != e; ++i)
19910 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19911 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19913 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19918 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19919 switch ((X86ISD::NodeType)Opcode) {
19920 case X86ISD::FIRST_NUMBER: break;
19921 case X86ISD::BSF: return "X86ISD::BSF";
19922 case X86ISD::BSR: return "X86ISD::BSR";
19923 case X86ISD::SHLD: return "X86ISD::SHLD";
19924 case X86ISD::SHRD: return "X86ISD::SHRD";
19925 case X86ISD::FAND: return "X86ISD::FAND";
19926 case X86ISD::FANDN: return "X86ISD::FANDN";
19927 case X86ISD::FOR: return "X86ISD::FOR";
19928 case X86ISD::FXOR: return "X86ISD::FXOR";
19929 case X86ISD::FILD: return "X86ISD::FILD";
19930 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19931 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19932 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19933 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19934 case X86ISD::FLD: return "X86ISD::FLD";
19935 case X86ISD::FST: return "X86ISD::FST";
19936 case X86ISD::CALL: return "X86ISD::CALL";
19937 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19938 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19939 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19940 case X86ISD::BT: return "X86ISD::BT";
19941 case X86ISD::CMP: return "X86ISD::CMP";
19942 case X86ISD::COMI: return "X86ISD::COMI";
19943 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19944 case X86ISD::CMPM: return "X86ISD::CMPM";
19945 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19946 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
19947 case X86ISD::SETCC: return "X86ISD::SETCC";
19948 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19949 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19950 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
19951 case X86ISD::CMOV: return "X86ISD::CMOV";
19952 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19953 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19954 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19955 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19956 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19957 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19958 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19959 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
19960 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
19961 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
19962 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19963 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19964 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19965 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19966 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19967 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
19968 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19969 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19970 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19971 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19972 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19973 case X86ISD::ADDUS: return "X86ISD::ADDUS";
19974 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19975 case X86ISD::HADD: return "X86ISD::HADD";
19976 case X86ISD::HSUB: return "X86ISD::HSUB";
19977 case X86ISD::FHADD: return "X86ISD::FHADD";
19978 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19979 case X86ISD::ABS: return "X86ISD::ABS";
19980 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
19981 case X86ISD::FMAX: return "X86ISD::FMAX";
19982 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
19983 case X86ISD::FMIN: return "X86ISD::FMIN";
19984 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
19985 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19986 case X86ISD::FMINC: return "X86ISD::FMINC";
19987 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19988 case X86ISD::FRCP: return "X86ISD::FRCP";
19989 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
19990 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
19991 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19992 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19993 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19994 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19995 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19996 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19997 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19998 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19999 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
20000 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
20001 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
20002 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
20003 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
20004 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
20005 case X86ISD::VZEXT: return "X86ISD::VZEXT";
20006 case X86ISD::VSEXT: return "X86ISD::VSEXT";
20007 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
20008 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
20009 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
20010 case X86ISD::VINSERT: return "X86ISD::VINSERT";
20011 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
20012 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
20013 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
20014 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
20015 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
20016 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
20017 case X86ISD::VSHL: return "X86ISD::VSHL";
20018 case X86ISD::VSRL: return "X86ISD::VSRL";
20019 case X86ISD::VSRA: return "X86ISD::VSRA";
20020 case X86ISD::VSHLI: return "X86ISD::VSHLI";
20021 case X86ISD::VSRLI: return "X86ISD::VSRLI";
20022 case X86ISD::VSRAI: return "X86ISD::VSRAI";
20023 case X86ISD::CMPP: return "X86ISD::CMPP";
20024 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
20025 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
20026 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
20027 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
20028 case X86ISD::ADD: return "X86ISD::ADD";
20029 case X86ISD::SUB: return "X86ISD::SUB";
20030 case X86ISD::ADC: return "X86ISD::ADC";
20031 case X86ISD::SBB: return "X86ISD::SBB";
20032 case X86ISD::SMUL: return "X86ISD::SMUL";
20033 case X86ISD::UMUL: return "X86ISD::UMUL";
20034 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20035 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20036 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20037 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20038 case X86ISD::INC: return "X86ISD::INC";
20039 case X86ISD::DEC: return "X86ISD::DEC";
20040 case X86ISD::OR: return "X86ISD::OR";
20041 case X86ISD::XOR: return "X86ISD::XOR";
20042 case X86ISD::AND: return "X86ISD::AND";
20043 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20044 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20045 case X86ISD::PTEST: return "X86ISD::PTEST";
20046 case X86ISD::TESTP: return "X86ISD::TESTP";
20047 case X86ISD::TESTM: return "X86ISD::TESTM";
20048 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20049 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20050 case X86ISD::KTEST: return "X86ISD::KTEST";
20051 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20052 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20053 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20054 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20055 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20056 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20057 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20058 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20059 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20060 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20061 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20062 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20063 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20064 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20065 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20066 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20067 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20068 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20069 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20070 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20071 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20072 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20073 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20074 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20075 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20076 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20077 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20078 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20079 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20080 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20081 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20082 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20083 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20084 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20085 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20086 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20087 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20088 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20089 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20090 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20091 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20092 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20093 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20094 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20095 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20096 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20097 case X86ISD::SAHF: return "X86ISD::SAHF";
20098 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20099 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20100 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20101 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20102 case X86ISD::VPROT: return "X86ISD::VPROT";
20103 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20104 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20105 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20106 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20107 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20108 case X86ISD::FMADD: return "X86ISD::FMADD";
20109 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20110 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20111 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20112 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20113 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20114 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20115 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20116 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20117 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20118 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20119 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20120 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20121 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20122 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20123 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20124 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20125 case X86ISD::XTEST: return "X86ISD::XTEST";
20126 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20127 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20128 case X86ISD::SELECT: return "X86ISD::SELECT";
20129 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20130 case X86ISD::RCP28: return "X86ISD::RCP28";
20131 case X86ISD::EXP2: return "X86ISD::EXP2";
20132 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20133 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20134 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20135 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20136 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20137 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20138 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20139 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20140 case X86ISD::ADDS: return "X86ISD::ADDS";
20141 case X86ISD::SUBS: return "X86ISD::SUBS";
20142 case X86ISD::AVG: return "X86ISD::AVG";
20143 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20144 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20145 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20146 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20147 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20148 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20153 // isLegalAddressingMode - Return true if the addressing mode represented
20154 // by AM is legal for this target, for a load/store of the specified type.
20155 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20156 const AddrMode &AM, Type *Ty,
20157 unsigned AS) const {
20158 // X86 supports extremely general addressing modes.
20159 CodeModel::Model M = getTargetMachine().getCodeModel();
20160 Reloc::Model R = getTargetMachine().getRelocationModel();
20162 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20163 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20168 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20170 // If a reference to this global requires an extra load, we can't fold it.
20171 if (isGlobalStubReference(GVFlags))
20174 // If BaseGV requires a register for the PIC base, we cannot also have a
20175 // BaseReg specified.
20176 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20179 // If lower 4G is not available, then we must use rip-relative addressing.
20180 if ((M != CodeModel::Small || R != Reloc::Static) &&
20181 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20185 switch (AM.Scale) {
20191 // These scales always work.
20196 // These scales are formed with basereg+scalereg. Only accept if there is
20201 default: // Other stuff never works.
20208 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20209 unsigned Bits = Ty->getScalarSizeInBits();
20211 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20212 // particularly cheaper than those without.
20216 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20217 // variable shifts just as cheap as scalar ones.
20218 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20221 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20222 // fully general vector.
20226 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20227 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20229 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20230 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20231 return NumBits1 > NumBits2;
20234 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20235 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20238 if (!isTypeLegal(EVT::getEVT(Ty1)))
20241 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20243 // Assuming the caller doesn't have a zeroext or signext return parameter,
20244 // truncation all the way down to i1 is valid.
20248 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20249 return isInt<32>(Imm);
20252 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20253 // Can also use sub to handle negated immediates.
20254 return isInt<32>(Imm);
20257 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20258 if (!VT1.isInteger() || !VT2.isInteger())
20260 unsigned NumBits1 = VT1.getSizeInBits();
20261 unsigned NumBits2 = VT2.getSizeInBits();
20262 return NumBits1 > NumBits2;
20265 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20266 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20267 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20270 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20271 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20272 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20275 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20276 EVT VT1 = Val.getValueType();
20277 if (isZExtFree(VT1, VT2))
20280 if (Val.getOpcode() != ISD::LOAD)
20283 if (!VT1.isSimple() || !VT1.isInteger() ||
20284 !VT2.isSimple() || !VT2.isInteger())
20287 switch (VT1.getSimpleVT().SimpleTy) {
20292 // X86 has 8, 16, and 32-bit zero-extending loads.
20299 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20302 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20303 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20306 VT = VT.getScalarType();
20308 if (!VT.isSimple())
20311 switch (VT.getSimpleVT().SimpleTy) {
20322 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20323 // i16 instructions are longer (0x66 prefix) and potentially slower.
20324 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20327 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20328 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20329 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20330 /// are assumed to be legal.
20332 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20334 if (!VT.isSimple())
20337 // Not for i1 vectors
20338 if (VT.getScalarType() == MVT::i1)
20341 // Very little shuffling can be done for 64-bit vectors right now.
20342 if (VT.getSizeInBits() == 64)
20345 // We only care that the types being shuffled are legal. The lowering can
20346 // handle any possible shuffle mask that results.
20347 return isTypeLegal(VT.getSimpleVT());
20351 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20353 // Just delegate to the generic legality, clear masks aren't special.
20354 return isShuffleMaskLegal(Mask, VT);
20357 //===----------------------------------------------------------------------===//
20358 // X86 Scheduler Hooks
20359 //===----------------------------------------------------------------------===//
20361 /// Utility function to emit xbegin specifying the start of an RTM region.
20362 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20363 const TargetInstrInfo *TII) {
20364 DebugLoc DL = MI->getDebugLoc();
20366 const BasicBlock *BB = MBB->getBasicBlock();
20367 MachineFunction::iterator I = ++MBB->getIterator();
20369 // For the v = xbegin(), we generate
20380 MachineBasicBlock *thisMBB = MBB;
20381 MachineFunction *MF = MBB->getParent();
20382 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20383 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20384 MF->insert(I, mainMBB);
20385 MF->insert(I, sinkMBB);
20387 // Transfer the remainder of BB and its successor edges to sinkMBB.
20388 sinkMBB->splice(sinkMBB->begin(), MBB,
20389 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20390 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20394 // # fallthrough to mainMBB
20395 // # abortion to sinkMBB
20396 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20397 thisMBB->addSuccessor(mainMBB);
20398 thisMBB->addSuccessor(sinkMBB);
20402 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20403 mainMBB->addSuccessor(sinkMBB);
20406 // EAX is live into the sinkMBB
20407 sinkMBB->addLiveIn(X86::EAX);
20408 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20409 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20412 MI->eraseFromParent();
20416 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20417 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20418 // in the .td file.
20419 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20420 const TargetInstrInfo *TII) {
20422 switch (MI->getOpcode()) {
20423 default: llvm_unreachable("illegal opcode!");
20424 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20425 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20426 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20427 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20428 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20429 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20430 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20431 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20434 DebugLoc dl = MI->getDebugLoc();
20435 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20437 unsigned NumArgs = MI->getNumOperands();
20438 for (unsigned i = 1; i < NumArgs; ++i) {
20439 MachineOperand &Op = MI->getOperand(i);
20440 if (!(Op.isReg() && Op.isImplicit()))
20441 MIB.addOperand(Op);
20443 if (MI->hasOneMemOperand())
20444 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20446 BuildMI(*BB, MI, dl,
20447 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20448 .addReg(X86::XMM0);
20450 MI->eraseFromParent();
20454 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20455 // defs in an instruction pattern
20456 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20457 const TargetInstrInfo *TII) {
20459 switch (MI->getOpcode()) {
20460 default: llvm_unreachable("illegal opcode!");
20461 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20462 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20463 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20464 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20465 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20466 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20467 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20468 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20471 DebugLoc dl = MI->getDebugLoc();
20472 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20474 unsigned NumArgs = MI->getNumOperands(); // remove the results
20475 for (unsigned i = 1; i < NumArgs; ++i) {
20476 MachineOperand &Op = MI->getOperand(i);
20477 if (!(Op.isReg() && Op.isImplicit()))
20478 MIB.addOperand(Op);
20480 if (MI->hasOneMemOperand())
20481 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20483 BuildMI(*BB, MI, dl,
20484 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20487 MI->eraseFromParent();
20491 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20492 const X86Subtarget *Subtarget) {
20493 DebugLoc dl = MI->getDebugLoc();
20494 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20495 // Address into RAX/EAX, other two args into ECX, EDX.
20496 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20497 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20498 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20499 for (int i = 0; i < X86::AddrNumOperands; ++i)
20500 MIB.addOperand(MI->getOperand(i));
20502 unsigned ValOps = X86::AddrNumOperands;
20503 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20504 .addReg(MI->getOperand(ValOps).getReg());
20505 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20506 .addReg(MI->getOperand(ValOps+1).getReg());
20508 // The instruction doesn't actually take any operands though.
20509 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20511 MI->eraseFromParent(); // The pseudo is gone now.
20515 MachineBasicBlock *
20516 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20517 MachineBasicBlock *MBB) const {
20518 // Emit va_arg instruction on X86-64.
20520 // Operands to this pseudo-instruction:
20521 // 0 ) Output : destination address (reg)
20522 // 1-5) Input : va_list address (addr, i64mem)
20523 // 6 ) ArgSize : Size (in bytes) of vararg type
20524 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20525 // 8 ) Align : Alignment of type
20526 // 9 ) EFLAGS (implicit-def)
20528 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20529 static_assert(X86::AddrNumOperands == 5,
20530 "VAARG_64 assumes 5 address operands");
20532 unsigned DestReg = MI->getOperand(0).getReg();
20533 MachineOperand &Base = MI->getOperand(1);
20534 MachineOperand &Scale = MI->getOperand(2);
20535 MachineOperand &Index = MI->getOperand(3);
20536 MachineOperand &Disp = MI->getOperand(4);
20537 MachineOperand &Segment = MI->getOperand(5);
20538 unsigned ArgSize = MI->getOperand(6).getImm();
20539 unsigned ArgMode = MI->getOperand(7).getImm();
20540 unsigned Align = MI->getOperand(8).getImm();
20542 // Memory Reference
20543 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20544 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20545 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20547 // Machine Information
20548 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20549 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20550 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20551 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20552 DebugLoc DL = MI->getDebugLoc();
20554 // struct va_list {
20557 // i64 overflow_area (address)
20558 // i64 reg_save_area (address)
20560 // sizeof(va_list) = 24
20561 // alignment(va_list) = 8
20563 unsigned TotalNumIntRegs = 6;
20564 unsigned TotalNumXMMRegs = 8;
20565 bool UseGPOffset = (ArgMode == 1);
20566 bool UseFPOffset = (ArgMode == 2);
20567 unsigned MaxOffset = TotalNumIntRegs * 8 +
20568 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20570 /* Align ArgSize to a multiple of 8 */
20571 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20572 bool NeedsAlign = (Align > 8);
20574 MachineBasicBlock *thisMBB = MBB;
20575 MachineBasicBlock *overflowMBB;
20576 MachineBasicBlock *offsetMBB;
20577 MachineBasicBlock *endMBB;
20579 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20580 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20581 unsigned OffsetReg = 0;
20583 if (!UseGPOffset && !UseFPOffset) {
20584 // If we only pull from the overflow region, we don't create a branch.
20585 // We don't need to alter control flow.
20586 OffsetDestReg = 0; // unused
20587 OverflowDestReg = DestReg;
20589 offsetMBB = nullptr;
20590 overflowMBB = thisMBB;
20593 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20594 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20595 // If not, pull from overflow_area. (branch to overflowMBB)
20600 // offsetMBB overflowMBB
20605 // Registers for the PHI in endMBB
20606 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20607 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20609 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20610 MachineFunction *MF = MBB->getParent();
20611 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20612 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20613 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20615 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20617 // Insert the new basic blocks
20618 MF->insert(MBBIter, offsetMBB);
20619 MF->insert(MBBIter, overflowMBB);
20620 MF->insert(MBBIter, endMBB);
20622 // Transfer the remainder of MBB and its successor edges to endMBB.
20623 endMBB->splice(endMBB->begin(), thisMBB,
20624 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20625 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20627 // Make offsetMBB and overflowMBB successors of thisMBB
20628 thisMBB->addSuccessor(offsetMBB);
20629 thisMBB->addSuccessor(overflowMBB);
20631 // endMBB is a successor of both offsetMBB and overflowMBB
20632 offsetMBB->addSuccessor(endMBB);
20633 overflowMBB->addSuccessor(endMBB);
20635 // Load the offset value into a register
20636 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20637 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20641 .addDisp(Disp, UseFPOffset ? 4 : 0)
20642 .addOperand(Segment)
20643 .setMemRefs(MMOBegin, MMOEnd);
20645 // Check if there is enough room left to pull this argument.
20646 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20648 .addImm(MaxOffset + 8 - ArgSizeA8);
20650 // Branch to "overflowMBB" if offset >= max
20651 // Fall through to "offsetMBB" otherwise
20652 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20653 .addMBB(overflowMBB);
20656 // In offsetMBB, emit code to use the reg_save_area.
20658 assert(OffsetReg != 0);
20660 // Read the reg_save_area address.
20661 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20662 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20667 .addOperand(Segment)
20668 .setMemRefs(MMOBegin, MMOEnd);
20670 // Zero-extend the offset
20671 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20672 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20675 .addImm(X86::sub_32bit);
20677 // Add the offset to the reg_save_area to get the final address.
20678 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20679 .addReg(OffsetReg64)
20680 .addReg(RegSaveReg);
20682 // Compute the offset for the next argument
20683 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20684 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20686 .addImm(UseFPOffset ? 16 : 8);
20688 // Store it back into the va_list.
20689 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20693 .addDisp(Disp, UseFPOffset ? 4 : 0)
20694 .addOperand(Segment)
20695 .addReg(NextOffsetReg)
20696 .setMemRefs(MMOBegin, MMOEnd);
20699 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20704 // Emit code to use overflow area
20707 // Load the overflow_area address into a register.
20708 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20709 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20714 .addOperand(Segment)
20715 .setMemRefs(MMOBegin, MMOEnd);
20717 // If we need to align it, do so. Otherwise, just copy the address
20718 // to OverflowDestReg.
20720 // Align the overflow address
20721 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20722 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20724 // aligned_addr = (addr + (align-1)) & ~(align-1)
20725 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20726 .addReg(OverflowAddrReg)
20729 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20731 .addImm(~(uint64_t)(Align-1));
20733 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20734 .addReg(OverflowAddrReg);
20737 // Compute the next overflow address after this argument.
20738 // (the overflow address should be kept 8-byte aligned)
20739 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20740 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20741 .addReg(OverflowDestReg)
20742 .addImm(ArgSizeA8);
20744 // Store the new overflow address.
20745 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20750 .addOperand(Segment)
20751 .addReg(NextAddrReg)
20752 .setMemRefs(MMOBegin, MMOEnd);
20754 // If we branched, emit the PHI to the front of endMBB.
20756 BuildMI(*endMBB, endMBB->begin(), DL,
20757 TII->get(X86::PHI), DestReg)
20758 .addReg(OffsetDestReg).addMBB(offsetMBB)
20759 .addReg(OverflowDestReg).addMBB(overflowMBB);
20762 // Erase the pseudo instruction
20763 MI->eraseFromParent();
20768 MachineBasicBlock *
20769 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20771 MachineBasicBlock *MBB) const {
20772 // Emit code to save XMM registers to the stack. The ABI says that the
20773 // number of registers to save is given in %al, so it's theoretically
20774 // possible to do an indirect jump trick to avoid saving all of them,
20775 // however this code takes a simpler approach and just executes all
20776 // of the stores if %al is non-zero. It's less code, and it's probably
20777 // easier on the hardware branch predictor, and stores aren't all that
20778 // expensive anyway.
20780 // Create the new basic blocks. One block contains all the XMM stores,
20781 // and one block is the final destination regardless of whether any
20782 // stores were performed.
20783 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20784 MachineFunction *F = MBB->getParent();
20785 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20786 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20787 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20788 F->insert(MBBIter, XMMSaveMBB);
20789 F->insert(MBBIter, EndMBB);
20791 // Transfer the remainder of MBB and its successor edges to EndMBB.
20792 EndMBB->splice(EndMBB->begin(), MBB,
20793 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20794 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20796 // The original block will now fall through to the XMM save block.
20797 MBB->addSuccessor(XMMSaveMBB);
20798 // The XMMSaveMBB will fall through to the end block.
20799 XMMSaveMBB->addSuccessor(EndMBB);
20801 // Now add the instructions.
20802 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20803 DebugLoc DL = MI->getDebugLoc();
20805 unsigned CountReg = MI->getOperand(0).getReg();
20806 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20807 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20809 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20810 // If %al is 0, branch around the XMM save block.
20811 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20812 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20813 MBB->addSuccessor(EndMBB);
20816 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20817 // that was just emitted, but clearly shouldn't be "saved".
20818 assert((MI->getNumOperands() <= 3 ||
20819 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20820 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20821 && "Expected last argument to be EFLAGS");
20822 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20823 // In the XMM save block, save all the XMM argument registers.
20824 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20825 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20826 MachineMemOperand *MMO = F->getMachineMemOperand(
20827 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20828 MachineMemOperand::MOStore,
20829 /*Size=*/16, /*Align=*/16);
20830 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20831 .addFrameIndex(RegSaveFrameIndex)
20832 .addImm(/*Scale=*/1)
20833 .addReg(/*IndexReg=*/0)
20834 .addImm(/*Disp=*/Offset)
20835 .addReg(/*Segment=*/0)
20836 .addReg(MI->getOperand(i).getReg())
20837 .addMemOperand(MMO);
20840 MI->eraseFromParent(); // The pseudo instruction is gone now.
20845 // The EFLAGS operand of SelectItr might be missing a kill marker
20846 // because there were multiple uses of EFLAGS, and ISel didn't know
20847 // which to mark. Figure out whether SelectItr should have had a
20848 // kill marker, and set it if it should. Returns the correct kill
20850 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20851 MachineBasicBlock* BB,
20852 const TargetRegisterInfo* TRI) {
20853 // Scan forward through BB for a use/def of EFLAGS.
20854 MachineBasicBlock::iterator miI(std::next(SelectItr));
20855 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20856 const MachineInstr& mi = *miI;
20857 if (mi.readsRegister(X86::EFLAGS))
20859 if (mi.definesRegister(X86::EFLAGS))
20860 break; // Should have kill-flag - update below.
20863 // If we hit the end of the block, check whether EFLAGS is live into a
20865 if (miI == BB->end()) {
20866 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20867 sEnd = BB->succ_end();
20868 sItr != sEnd; ++sItr) {
20869 MachineBasicBlock* succ = *sItr;
20870 if (succ->isLiveIn(X86::EFLAGS))
20875 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20876 // out. SelectMI should have a kill flag on EFLAGS.
20877 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20881 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20882 // together with other CMOV pseudo-opcodes into a single basic-block with
20883 // conditional jump around it.
20884 static bool isCMOVPseudo(MachineInstr *MI) {
20885 switch (MI->getOpcode()) {
20886 case X86::CMOV_FR32:
20887 case X86::CMOV_FR64:
20888 case X86::CMOV_GR8:
20889 case X86::CMOV_GR16:
20890 case X86::CMOV_GR32:
20891 case X86::CMOV_RFP32:
20892 case X86::CMOV_RFP64:
20893 case X86::CMOV_RFP80:
20894 case X86::CMOV_V2F64:
20895 case X86::CMOV_V2I64:
20896 case X86::CMOV_V4F32:
20897 case X86::CMOV_V4F64:
20898 case X86::CMOV_V4I64:
20899 case X86::CMOV_V16F32:
20900 case X86::CMOV_V8F32:
20901 case X86::CMOV_V8F64:
20902 case X86::CMOV_V8I64:
20903 case X86::CMOV_V8I1:
20904 case X86::CMOV_V16I1:
20905 case X86::CMOV_V32I1:
20906 case X86::CMOV_V64I1:
20914 MachineBasicBlock *
20915 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20916 MachineBasicBlock *BB) const {
20917 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20918 DebugLoc DL = MI->getDebugLoc();
20920 // To "insert" a SELECT_CC instruction, we actually have to insert the
20921 // diamond control-flow pattern. The incoming instruction knows the
20922 // destination vreg to set, the condition code register to branch on, the
20923 // true/false values to select between, and a branch opcode to use.
20924 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20925 MachineFunction::iterator It = ++BB->getIterator();
20930 // cmpTY ccX, r1, r2
20932 // fallthrough --> copy0MBB
20933 MachineBasicBlock *thisMBB = BB;
20934 MachineFunction *F = BB->getParent();
20936 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20937 // as described above, by inserting a BB, and then making a PHI at the join
20938 // point to select the true and false operands of the CMOV in the PHI.
20940 // The code also handles two different cases of multiple CMOV opcodes
20944 // In this case, there are multiple CMOVs in a row, all which are based on
20945 // the same condition setting (or the exact opposite condition setting).
20946 // In this case we can lower all the CMOVs using a single inserted BB, and
20947 // then make a number of PHIs at the join point to model the CMOVs. The only
20948 // trickiness here, is that in a case like:
20950 // t2 = CMOV cond1 t1, f1
20951 // t3 = CMOV cond1 t2, f2
20953 // when rewriting this into PHIs, we have to perform some renaming on the
20954 // temps since you cannot have a PHI operand refer to a PHI result earlier
20955 // in the same block. The "simple" but wrong lowering would be:
20957 // t2 = PHI t1(BB1), f1(BB2)
20958 // t3 = PHI t2(BB1), f2(BB2)
20960 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
20961 // renaming is to note that on the path through BB1, t2 is really just a
20962 // copy of t1, and do that renaming, properly generating:
20964 // t2 = PHI t1(BB1), f1(BB2)
20965 // t3 = PHI t1(BB1), f2(BB2)
20967 // Case 2, we lower cascaded CMOVs such as
20969 // (CMOV (CMOV F, T, cc1), T, cc2)
20971 // to two successives branches. For that, we look for another CMOV as the
20972 // following instruction.
20974 // Without this, we would add a PHI between the two jumps, which ends up
20975 // creating a few copies all around. For instance, for
20977 // (sitofp (zext (fcmp une)))
20979 // we would generate:
20981 // ucomiss %xmm1, %xmm0
20982 // movss <1.0f>, %xmm0
20983 // movaps %xmm0, %xmm1
20985 // xorps %xmm1, %xmm1
20988 // movaps %xmm1, %xmm0
20992 // because this custom-inserter would have generated:
21004 // A: X = ...; Y = ...
21006 // C: Z = PHI [X, A], [Y, B]
21008 // E: PHI [X, C], [Z, D]
21010 // If we lower both CMOVs in a single step, we can instead generate:
21022 // A: X = ...; Y = ...
21024 // E: PHI [X, A], [X, C], [Y, D]
21026 // Which, in our sitofp/fcmp example, gives us something like:
21028 // ucomiss %xmm1, %xmm0
21029 // movss <1.0f>, %xmm0
21032 // xorps %xmm0, %xmm0
21036 MachineInstr *CascadedCMOV = nullptr;
21037 MachineInstr *LastCMOV = MI;
21038 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21039 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21040 MachineBasicBlock::iterator NextMIIt =
21041 std::next(MachineBasicBlock::iterator(MI));
21043 // Check for case 1, where there are multiple CMOVs with the same condition
21044 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21045 // number of jumps the most.
21047 if (isCMOVPseudo(MI)) {
21048 // See if we have a string of CMOVS with the same condition.
21049 while (NextMIIt != BB->end() &&
21050 isCMOVPseudo(NextMIIt) &&
21051 (NextMIIt->getOperand(3).getImm() == CC ||
21052 NextMIIt->getOperand(3).getImm() == OppCC)) {
21053 LastCMOV = &*NextMIIt;
21058 // This checks for case 2, but only do this if we didn't already find
21059 // case 1, as indicated by LastCMOV == MI.
21060 if (LastCMOV == MI &&
21061 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21062 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21063 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21064 CascadedCMOV = &*NextMIIt;
21067 MachineBasicBlock *jcc1MBB = nullptr;
21069 // If we have a cascaded CMOV, we lower it to two successive branches to
21070 // the same block. EFLAGS is used by both, so mark it as live in the second.
21071 if (CascadedCMOV) {
21072 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21073 F->insert(It, jcc1MBB);
21074 jcc1MBB->addLiveIn(X86::EFLAGS);
21077 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21078 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21079 F->insert(It, copy0MBB);
21080 F->insert(It, sinkMBB);
21082 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21083 // live into the sink and copy blocks.
21084 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21086 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21087 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21088 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21089 copy0MBB->addLiveIn(X86::EFLAGS);
21090 sinkMBB->addLiveIn(X86::EFLAGS);
21093 // Transfer the remainder of BB and its successor edges to sinkMBB.
21094 sinkMBB->splice(sinkMBB->begin(), BB,
21095 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21096 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21098 // Add the true and fallthrough blocks as its successors.
21099 if (CascadedCMOV) {
21100 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21101 BB->addSuccessor(jcc1MBB);
21103 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21104 // jump to the sinkMBB.
21105 jcc1MBB->addSuccessor(copy0MBB);
21106 jcc1MBB->addSuccessor(sinkMBB);
21108 BB->addSuccessor(copy0MBB);
21111 // The true block target of the first (or only) branch is always sinkMBB.
21112 BB->addSuccessor(sinkMBB);
21114 // Create the conditional branch instruction.
21115 unsigned Opc = X86::GetCondBranchFromCond(CC);
21116 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21118 if (CascadedCMOV) {
21119 unsigned Opc2 = X86::GetCondBranchFromCond(
21120 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21121 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21125 // %FalseValue = ...
21126 // # fallthrough to sinkMBB
21127 copy0MBB->addSuccessor(sinkMBB);
21130 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21132 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21133 MachineBasicBlock::iterator MIItEnd =
21134 std::next(MachineBasicBlock::iterator(LastCMOV));
21135 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21136 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21137 MachineInstrBuilder MIB;
21139 // As we are creating the PHIs, we have to be careful if there is more than
21140 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21141 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21142 // That also means that PHI construction must work forward from earlier to
21143 // later, and that the code must maintain a mapping from earlier PHI's
21144 // destination registers, and the registers that went into the PHI.
21146 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21147 unsigned DestReg = MIIt->getOperand(0).getReg();
21148 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21149 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21151 // If this CMOV we are generating is the opposite condition from
21152 // the jump we generated, then we have to swap the operands for the
21153 // PHI that is going to be generated.
21154 if (MIIt->getOperand(3).getImm() == OppCC)
21155 std::swap(Op1Reg, Op2Reg);
21157 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21158 Op1Reg = RegRewriteTable[Op1Reg].first;
21160 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21161 Op2Reg = RegRewriteTable[Op2Reg].second;
21163 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21164 TII->get(X86::PHI), DestReg)
21165 .addReg(Op1Reg).addMBB(copy0MBB)
21166 .addReg(Op2Reg).addMBB(thisMBB);
21168 // Add this PHI to the rewrite table.
21169 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21172 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21173 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21174 if (CascadedCMOV) {
21175 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21176 // Copy the PHI result to the register defined by the second CMOV.
21177 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21178 DL, TII->get(TargetOpcode::COPY),
21179 CascadedCMOV->getOperand(0).getReg())
21180 .addReg(MI->getOperand(0).getReg());
21181 CascadedCMOV->eraseFromParent();
21184 // Now remove the CMOV(s).
21185 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21186 (MIIt++)->eraseFromParent();
21191 MachineBasicBlock *
21192 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21193 MachineBasicBlock *BB) const {
21194 // Combine the following atomic floating-point modification pattern:
21195 // a.store(reg OP a.load(acquire), release)
21196 // Transform them into:
21197 // OPss (%gpr), %xmm
21198 // movss %xmm, (%gpr)
21199 // Or sd equivalent for 64-bit operations.
21201 switch (MI->getOpcode()) {
21202 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21203 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21204 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21206 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21207 DebugLoc DL = MI->getDebugLoc();
21208 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21209 MachineOperand MSrc = MI->getOperand(0);
21210 unsigned VSrc = MI->getOperand(5).getReg();
21211 const MachineOperand &Disp = MI->getOperand(3);
21212 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21213 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21214 if (hasDisp && MSrc.isReg())
21215 MSrc.setIsKill(false);
21216 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21217 .addOperand(/*Base=*/MSrc)
21218 .addImm(/*Scale=*/1)
21219 .addReg(/*Index=*/0)
21220 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21222 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21223 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21225 .addOperand(/*Base=*/MSrc)
21226 .addImm(/*Scale=*/1)
21227 .addReg(/*Index=*/0)
21228 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21229 .addReg(/*Segment=*/0);
21230 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21231 MI->eraseFromParent(); // The pseudo instruction is gone now.
21235 MachineBasicBlock *
21236 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21237 MachineBasicBlock *BB) const {
21238 MachineFunction *MF = BB->getParent();
21239 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21240 DebugLoc DL = MI->getDebugLoc();
21241 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21243 assert(MF->shouldSplitStack());
21245 const bool Is64Bit = Subtarget->is64Bit();
21246 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21248 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21249 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21252 // ... [Till the alloca]
21253 // If stacklet is not large enough, jump to mallocMBB
21256 // Allocate by subtracting from RSP
21257 // Jump to continueMBB
21260 // Allocate by call to runtime
21264 // [rest of original BB]
21267 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21268 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21269 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21271 MachineRegisterInfo &MRI = MF->getRegInfo();
21272 const TargetRegisterClass *AddrRegClass =
21273 getRegClassFor(getPointerTy(MF->getDataLayout()));
21275 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21276 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21277 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21278 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21279 sizeVReg = MI->getOperand(1).getReg(),
21280 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21282 MachineFunction::iterator MBBIter = ++BB->getIterator();
21284 MF->insert(MBBIter, bumpMBB);
21285 MF->insert(MBBIter, mallocMBB);
21286 MF->insert(MBBIter, continueMBB);
21288 continueMBB->splice(continueMBB->begin(), BB,
21289 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21290 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21292 // Add code to the main basic block to check if the stack limit has been hit,
21293 // and if so, jump to mallocMBB otherwise to bumpMBB.
21294 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21295 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21296 .addReg(tmpSPVReg).addReg(sizeVReg);
21297 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21298 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21299 .addReg(SPLimitVReg);
21300 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21302 // bumpMBB simply decreases the stack pointer, since we know the current
21303 // stacklet has enough space.
21304 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21305 .addReg(SPLimitVReg);
21306 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21307 .addReg(SPLimitVReg);
21308 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21310 // Calls into a routine in libgcc to allocate more space from the heap.
21311 const uint32_t *RegMask =
21312 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21314 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21316 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21317 .addExternalSymbol("__morestack_allocate_stack_space")
21318 .addRegMask(RegMask)
21319 .addReg(X86::RDI, RegState::Implicit)
21320 .addReg(X86::RAX, RegState::ImplicitDefine);
21321 } else if (Is64Bit) {
21322 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21324 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21325 .addExternalSymbol("__morestack_allocate_stack_space")
21326 .addRegMask(RegMask)
21327 .addReg(X86::EDI, RegState::Implicit)
21328 .addReg(X86::EAX, RegState::ImplicitDefine);
21330 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21332 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21333 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21334 .addExternalSymbol("__morestack_allocate_stack_space")
21335 .addRegMask(RegMask)
21336 .addReg(X86::EAX, RegState::ImplicitDefine);
21340 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21343 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21344 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21345 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21347 // Set up the CFG correctly.
21348 BB->addSuccessor(bumpMBB);
21349 BB->addSuccessor(mallocMBB);
21350 mallocMBB->addSuccessor(continueMBB);
21351 bumpMBB->addSuccessor(continueMBB);
21353 // Take care of the PHI nodes.
21354 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21355 MI->getOperand(0).getReg())
21356 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21357 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21359 // Delete the original pseudo instruction.
21360 MI->eraseFromParent();
21363 return continueMBB;
21366 MachineBasicBlock *
21367 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21368 MachineBasicBlock *BB) const {
21369 DebugLoc DL = MI->getDebugLoc();
21371 assert(!Subtarget->isTargetMachO());
21373 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
21376 MI->eraseFromParent(); // The pseudo instruction is gone now.
21380 MachineBasicBlock *
21381 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21382 MachineBasicBlock *BB) const {
21383 // This is pretty easy. We're taking the value that we received from
21384 // our load from the relocation, sticking it in either RDI (x86-64)
21385 // or EAX and doing an indirect call. The return value will then
21386 // be in the normal return register.
21387 MachineFunction *F = BB->getParent();
21388 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21389 DebugLoc DL = MI->getDebugLoc();
21391 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21392 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21394 // Get a register mask for the lowered call.
21395 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21396 // proper register mask.
21397 const uint32_t *RegMask =
21398 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21399 if (Subtarget->is64Bit()) {
21400 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21401 TII->get(X86::MOV64rm), X86::RDI)
21403 .addImm(0).addReg(0)
21404 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21405 MI->getOperand(3).getTargetFlags())
21407 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21408 addDirectMem(MIB, X86::RDI);
21409 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21410 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21411 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21412 TII->get(X86::MOV32rm), X86::EAX)
21414 .addImm(0).addReg(0)
21415 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21416 MI->getOperand(3).getTargetFlags())
21418 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21419 addDirectMem(MIB, X86::EAX);
21420 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21422 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21423 TII->get(X86::MOV32rm), X86::EAX)
21424 .addReg(TII->getGlobalBaseReg(F))
21425 .addImm(0).addReg(0)
21426 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21427 MI->getOperand(3).getTargetFlags())
21429 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21430 addDirectMem(MIB, X86::EAX);
21431 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21434 MI->eraseFromParent(); // The pseudo instruction is gone now.
21438 MachineBasicBlock *
21439 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21440 MachineBasicBlock *MBB) const {
21441 DebugLoc DL = MI->getDebugLoc();
21442 MachineFunction *MF = MBB->getParent();
21443 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21444 MachineRegisterInfo &MRI = MF->getRegInfo();
21446 const BasicBlock *BB = MBB->getBasicBlock();
21447 MachineFunction::iterator I = ++MBB->getIterator();
21449 // Memory Reference
21450 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21451 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21454 unsigned MemOpndSlot = 0;
21456 unsigned CurOp = 0;
21458 DstReg = MI->getOperand(CurOp++).getReg();
21459 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21460 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21461 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21462 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21464 MemOpndSlot = CurOp;
21466 MVT PVT = getPointerTy(MF->getDataLayout());
21467 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21468 "Invalid Pointer Size!");
21470 // For v = setjmp(buf), we generate
21473 // buf[LabelOffset] = restoreMBB
21474 // SjLjSetup restoreMBB
21480 // v = phi(main, restore)
21483 // if base pointer being used, load it from frame
21486 MachineBasicBlock *thisMBB = MBB;
21487 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21488 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21489 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21490 MF->insert(I, mainMBB);
21491 MF->insert(I, sinkMBB);
21492 MF->push_back(restoreMBB);
21494 MachineInstrBuilder MIB;
21496 // Transfer the remainder of BB and its successor edges to sinkMBB.
21497 sinkMBB->splice(sinkMBB->begin(), MBB,
21498 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21499 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21502 unsigned PtrStoreOpc = 0;
21503 unsigned LabelReg = 0;
21504 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21505 Reloc::Model RM = MF->getTarget().getRelocationModel();
21506 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21507 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21509 // Prepare IP either in reg or imm.
21510 if (!UseImmLabel) {
21511 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21512 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21513 LabelReg = MRI.createVirtualRegister(PtrRC);
21514 if (Subtarget->is64Bit()) {
21515 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21519 .addMBB(restoreMBB)
21522 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21523 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21524 .addReg(XII->getGlobalBaseReg(MF))
21527 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21531 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21533 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21534 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21535 if (i == X86::AddrDisp)
21536 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21538 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21541 MIB.addReg(LabelReg);
21543 MIB.addMBB(restoreMBB);
21544 MIB.setMemRefs(MMOBegin, MMOEnd);
21546 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21547 .addMBB(restoreMBB);
21549 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21550 MIB.addRegMask(RegInfo->getNoPreservedMask());
21551 thisMBB->addSuccessor(mainMBB);
21552 thisMBB->addSuccessor(restoreMBB);
21556 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21557 mainMBB->addSuccessor(sinkMBB);
21560 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21561 TII->get(X86::PHI), DstReg)
21562 .addReg(mainDstReg).addMBB(mainMBB)
21563 .addReg(restoreDstReg).addMBB(restoreMBB);
21566 if (RegInfo->hasBasePointer(*MF)) {
21567 const bool Uses64BitFramePtr =
21568 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21569 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21570 X86FI->setRestoreBasePointer(MF);
21571 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21572 unsigned BasePtr = RegInfo->getBaseRegister();
21573 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21574 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21575 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21576 .setMIFlag(MachineInstr::FrameSetup);
21578 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21579 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21580 restoreMBB->addSuccessor(sinkMBB);
21582 MI->eraseFromParent();
21586 MachineBasicBlock *
21587 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21588 MachineBasicBlock *MBB) const {
21589 DebugLoc DL = MI->getDebugLoc();
21590 MachineFunction *MF = MBB->getParent();
21591 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21592 MachineRegisterInfo &MRI = MF->getRegInfo();
21594 // Memory Reference
21595 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21596 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21598 MVT PVT = getPointerTy(MF->getDataLayout());
21599 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21600 "Invalid Pointer Size!");
21602 const TargetRegisterClass *RC =
21603 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21604 unsigned Tmp = MRI.createVirtualRegister(RC);
21605 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21606 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21607 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21608 unsigned SP = RegInfo->getStackRegister();
21610 MachineInstrBuilder MIB;
21612 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21613 const int64_t SPOffset = 2 * PVT.getStoreSize();
21615 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21616 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21619 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21620 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21621 MIB.addOperand(MI->getOperand(i));
21622 MIB.setMemRefs(MMOBegin, MMOEnd);
21624 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21625 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21626 if (i == X86::AddrDisp)
21627 MIB.addDisp(MI->getOperand(i), LabelOffset);
21629 MIB.addOperand(MI->getOperand(i));
21631 MIB.setMemRefs(MMOBegin, MMOEnd);
21633 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21634 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21635 if (i == X86::AddrDisp)
21636 MIB.addDisp(MI->getOperand(i), SPOffset);
21638 MIB.addOperand(MI->getOperand(i));
21640 MIB.setMemRefs(MMOBegin, MMOEnd);
21642 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21644 MI->eraseFromParent();
21648 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21649 // accumulator loops. Writing back to the accumulator allows the coalescer
21650 // to remove extra copies in the loop.
21651 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21652 MachineBasicBlock *
21653 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21654 MachineBasicBlock *MBB) const {
21655 MachineOperand &AddendOp = MI->getOperand(3);
21657 // Bail out early if the addend isn't a register - we can't switch these.
21658 if (!AddendOp.isReg())
21661 MachineFunction &MF = *MBB->getParent();
21662 MachineRegisterInfo &MRI = MF.getRegInfo();
21664 // Check whether the addend is defined by a PHI:
21665 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21666 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21667 if (!AddendDef.isPHI())
21670 // Look for the following pattern:
21672 // %addend = phi [%entry, 0], [%loop, %result]
21674 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21678 // %addend = phi [%entry, 0], [%loop, %result]
21680 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21682 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21683 assert(AddendDef.getOperand(i).isReg());
21684 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21685 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21686 if (&PHISrcInst == MI) {
21687 // Found a matching instruction.
21688 unsigned NewFMAOpc = 0;
21689 switch (MI->getOpcode()) {
21690 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21691 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21692 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21693 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21694 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21695 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21696 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21697 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21698 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21699 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21700 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21701 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21702 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21703 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21704 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21705 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21706 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21707 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21708 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21709 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21711 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21712 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21713 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21714 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21715 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21716 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21717 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21718 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21719 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21720 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21721 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21722 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21723 default: llvm_unreachable("Unrecognized FMA variant.");
21726 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21727 MachineInstrBuilder MIB =
21728 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21729 .addOperand(MI->getOperand(0))
21730 .addOperand(MI->getOperand(3))
21731 .addOperand(MI->getOperand(2))
21732 .addOperand(MI->getOperand(1));
21733 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21734 MI->eraseFromParent();
21741 MachineBasicBlock *
21742 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21743 MachineBasicBlock *BB) const {
21744 switch (MI->getOpcode()) {
21745 default: llvm_unreachable("Unexpected instr type to insert");
21746 case X86::TAILJMPd64:
21747 case X86::TAILJMPr64:
21748 case X86::TAILJMPm64:
21749 case X86::TAILJMPd64_REX:
21750 case X86::TAILJMPr64_REX:
21751 case X86::TAILJMPm64_REX:
21752 llvm_unreachable("TAILJMP64 would not be touched here.");
21753 case X86::TCRETURNdi64:
21754 case X86::TCRETURNri64:
21755 case X86::TCRETURNmi64:
21757 case X86::WIN_ALLOCA:
21758 return EmitLoweredWinAlloca(MI, BB);
21759 case X86::SEG_ALLOCA_32:
21760 case X86::SEG_ALLOCA_64:
21761 return EmitLoweredSegAlloca(MI, BB);
21762 case X86::TLSCall_32:
21763 case X86::TLSCall_64:
21764 return EmitLoweredTLSCall(MI, BB);
21765 case X86::CMOV_FR32:
21766 case X86::CMOV_FR64:
21767 case X86::CMOV_GR8:
21768 case X86::CMOV_GR16:
21769 case X86::CMOV_GR32:
21770 case X86::CMOV_RFP32:
21771 case X86::CMOV_RFP64:
21772 case X86::CMOV_RFP80:
21773 case X86::CMOV_V2F64:
21774 case X86::CMOV_V2I64:
21775 case X86::CMOV_V4F32:
21776 case X86::CMOV_V4F64:
21777 case X86::CMOV_V4I64:
21778 case X86::CMOV_V16F32:
21779 case X86::CMOV_V8F32:
21780 case X86::CMOV_V8F64:
21781 case X86::CMOV_V8I64:
21782 case X86::CMOV_V8I1:
21783 case X86::CMOV_V16I1:
21784 case X86::CMOV_V32I1:
21785 case X86::CMOV_V64I1:
21786 return EmitLoweredSelect(MI, BB);
21788 case X86::RELEASE_FADD32mr:
21789 case X86::RELEASE_FADD64mr:
21790 return EmitLoweredAtomicFP(MI, BB);
21792 case X86::FP32_TO_INT16_IN_MEM:
21793 case X86::FP32_TO_INT32_IN_MEM:
21794 case X86::FP32_TO_INT64_IN_MEM:
21795 case X86::FP64_TO_INT16_IN_MEM:
21796 case X86::FP64_TO_INT32_IN_MEM:
21797 case X86::FP64_TO_INT64_IN_MEM:
21798 case X86::FP80_TO_INT16_IN_MEM:
21799 case X86::FP80_TO_INT32_IN_MEM:
21800 case X86::FP80_TO_INT64_IN_MEM: {
21801 MachineFunction *F = BB->getParent();
21802 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21803 DebugLoc DL = MI->getDebugLoc();
21805 // Change the floating point control register to use "round towards zero"
21806 // mode when truncating to an integer value.
21807 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21808 addFrameReference(BuildMI(*BB, MI, DL,
21809 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21811 // Load the old value of the high byte of the control word...
21813 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21814 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21817 // Set the high part to be round to zero...
21818 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21821 // Reload the modified control word now...
21822 addFrameReference(BuildMI(*BB, MI, DL,
21823 TII->get(X86::FLDCW16m)), CWFrameIdx);
21825 // Restore the memory image of control word to original value
21826 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21829 // Get the X86 opcode to use.
21831 switch (MI->getOpcode()) {
21832 default: llvm_unreachable("illegal opcode!");
21833 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21834 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21835 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21836 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21837 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21838 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21839 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21840 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21841 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21845 MachineOperand &Op = MI->getOperand(0);
21847 AM.BaseType = X86AddressMode::RegBase;
21848 AM.Base.Reg = Op.getReg();
21850 AM.BaseType = X86AddressMode::FrameIndexBase;
21851 AM.Base.FrameIndex = Op.getIndex();
21853 Op = MI->getOperand(1);
21855 AM.Scale = Op.getImm();
21856 Op = MI->getOperand(2);
21858 AM.IndexReg = Op.getImm();
21859 Op = MI->getOperand(3);
21860 if (Op.isGlobal()) {
21861 AM.GV = Op.getGlobal();
21863 AM.Disp = Op.getImm();
21865 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21866 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21868 // Reload the original control word now.
21869 addFrameReference(BuildMI(*BB, MI, DL,
21870 TII->get(X86::FLDCW16m)), CWFrameIdx);
21872 MI->eraseFromParent(); // The pseudo instruction is gone now.
21875 // String/text processing lowering.
21876 case X86::PCMPISTRM128REG:
21877 case X86::VPCMPISTRM128REG:
21878 case X86::PCMPISTRM128MEM:
21879 case X86::VPCMPISTRM128MEM:
21880 case X86::PCMPESTRM128REG:
21881 case X86::VPCMPESTRM128REG:
21882 case X86::PCMPESTRM128MEM:
21883 case X86::VPCMPESTRM128MEM:
21884 assert(Subtarget->hasSSE42() &&
21885 "Target must have SSE4.2 or AVX features enabled");
21886 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21888 // String/text processing lowering.
21889 case X86::PCMPISTRIREG:
21890 case X86::VPCMPISTRIREG:
21891 case X86::PCMPISTRIMEM:
21892 case X86::VPCMPISTRIMEM:
21893 case X86::PCMPESTRIREG:
21894 case X86::VPCMPESTRIREG:
21895 case X86::PCMPESTRIMEM:
21896 case X86::VPCMPESTRIMEM:
21897 assert(Subtarget->hasSSE42() &&
21898 "Target must have SSE4.2 or AVX features enabled");
21899 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21901 // Thread synchronization.
21903 return EmitMonitor(MI, BB, Subtarget);
21907 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21909 case X86::VASTART_SAVE_XMM_REGS:
21910 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21912 case X86::VAARG_64:
21913 return EmitVAARG64WithCustomInserter(MI, BB);
21915 case X86::EH_SjLj_SetJmp32:
21916 case X86::EH_SjLj_SetJmp64:
21917 return emitEHSjLjSetJmp(MI, BB);
21919 case X86::EH_SjLj_LongJmp32:
21920 case X86::EH_SjLj_LongJmp64:
21921 return emitEHSjLjLongJmp(MI, BB);
21923 case TargetOpcode::STATEPOINT:
21924 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21925 // this point in the process. We diverge later.
21926 return emitPatchPoint(MI, BB);
21928 case TargetOpcode::STACKMAP:
21929 case TargetOpcode::PATCHPOINT:
21930 return emitPatchPoint(MI, BB);
21932 case X86::VFMADDPDr213r:
21933 case X86::VFMADDPSr213r:
21934 case X86::VFMADDSDr213r:
21935 case X86::VFMADDSSr213r:
21936 case X86::VFMSUBPDr213r:
21937 case X86::VFMSUBPSr213r:
21938 case X86::VFMSUBSDr213r:
21939 case X86::VFMSUBSSr213r:
21940 case X86::VFNMADDPDr213r:
21941 case X86::VFNMADDPSr213r:
21942 case X86::VFNMADDSDr213r:
21943 case X86::VFNMADDSSr213r:
21944 case X86::VFNMSUBPDr213r:
21945 case X86::VFNMSUBPSr213r:
21946 case X86::VFNMSUBSDr213r:
21947 case X86::VFNMSUBSSr213r:
21948 case X86::VFMADDSUBPDr213r:
21949 case X86::VFMADDSUBPSr213r:
21950 case X86::VFMSUBADDPDr213r:
21951 case X86::VFMSUBADDPSr213r:
21952 case X86::VFMADDPDr213rY:
21953 case X86::VFMADDPSr213rY:
21954 case X86::VFMSUBPDr213rY:
21955 case X86::VFMSUBPSr213rY:
21956 case X86::VFNMADDPDr213rY:
21957 case X86::VFNMADDPSr213rY:
21958 case X86::VFNMSUBPDr213rY:
21959 case X86::VFNMSUBPSr213rY:
21960 case X86::VFMADDSUBPDr213rY:
21961 case X86::VFMADDSUBPSr213rY:
21962 case X86::VFMSUBADDPDr213rY:
21963 case X86::VFMSUBADDPSr213rY:
21964 return emitFMA3Instr(MI, BB);
21968 //===----------------------------------------------------------------------===//
21969 // X86 Optimization Hooks
21970 //===----------------------------------------------------------------------===//
21972 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21975 const SelectionDAG &DAG,
21976 unsigned Depth) const {
21977 unsigned BitWidth = KnownZero.getBitWidth();
21978 unsigned Opc = Op.getOpcode();
21979 assert((Opc >= ISD::BUILTIN_OP_END ||
21980 Opc == ISD::INTRINSIC_WO_CHAIN ||
21981 Opc == ISD::INTRINSIC_W_CHAIN ||
21982 Opc == ISD::INTRINSIC_VOID) &&
21983 "Should use MaskedValueIsZero if you don't know whether Op"
21984 " is a target node!");
21986 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
22000 // These nodes' second result is a boolean.
22001 if (Op.getResNo() == 0)
22004 case X86ISD::SETCC:
22005 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
22007 case ISD::INTRINSIC_WO_CHAIN: {
22008 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
22009 unsigned NumLoBits = 0;
22012 case Intrinsic::x86_sse_movmsk_ps:
22013 case Intrinsic::x86_avx_movmsk_ps_256:
22014 case Intrinsic::x86_sse2_movmsk_pd:
22015 case Intrinsic::x86_avx_movmsk_pd_256:
22016 case Intrinsic::x86_mmx_pmovmskb:
22017 case Intrinsic::x86_sse2_pmovmskb_128:
22018 case Intrinsic::x86_avx2_pmovmskb: {
22019 // High bits of movmskp{s|d}, pmovmskb are known zero.
22021 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
22022 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
22023 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
22024 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
22025 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
22026 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
22027 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
22028 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
22030 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22039 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22041 const SelectionDAG &,
22042 unsigned Depth) const {
22043 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22044 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22045 return Op.getValueType().getScalarType().getSizeInBits();
22051 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22052 /// node is a GlobalAddress + offset.
22053 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22054 const GlobalValue* &GA,
22055 int64_t &Offset) const {
22056 if (N->getOpcode() == X86ISD::Wrapper) {
22057 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22058 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22059 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22063 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22066 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
22067 /// same as extracting the high 128-bit part of 256-bit vector and then
22068 /// inserting the result into the low part of a new 256-bit vector
22069 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
22070 EVT VT = SVOp->getValueType(0);
22071 unsigned NumElems = VT.getVectorNumElements();
22073 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22074 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
22075 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22076 SVOp->getMaskElt(j) >= 0)
22082 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
22083 /// same as extracting the low 128-bit part of 256-bit vector and then
22084 /// inserting the result into the high part of a new 256-bit vector
22085 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
22086 EVT VT = SVOp->getValueType(0);
22087 unsigned NumElems = VT.getVectorNumElements();
22089 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22090 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
22091 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22092 SVOp->getMaskElt(j) >= 0)
22098 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22099 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22100 TargetLowering::DAGCombinerInfo &DCI,
22101 const X86Subtarget* Subtarget) {
22103 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22104 SDValue V1 = SVOp->getOperand(0);
22105 SDValue V2 = SVOp->getOperand(1);
22106 EVT VT = SVOp->getValueType(0);
22107 unsigned NumElems = VT.getVectorNumElements();
22109 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22110 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22114 // V UNDEF BUILD_VECTOR UNDEF
22116 // CONCAT_VECTOR CONCAT_VECTOR
22119 // RESULT: V + zero extended
22121 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22122 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22123 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22126 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22129 // To match the shuffle mask, the first half of the mask should
22130 // be exactly the first vector, and all the rest a splat with the
22131 // first element of the second one.
22132 for (unsigned i = 0; i != NumElems/2; ++i)
22133 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22134 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22137 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22138 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22139 if (Ld->hasNUsesOfValue(1, 0)) {
22140 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22141 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22143 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22145 Ld->getPointerInfo(),
22146 Ld->getAlignment(),
22147 false/*isVolatile*/, true/*ReadMem*/,
22148 false/*WriteMem*/);
22150 // Make sure the newly-created LOAD is in the same position as Ld in
22151 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22152 // and update uses of Ld's output chain to use the TokenFactor.
22153 if (Ld->hasAnyUseOfValue(1)) {
22154 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22155 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22156 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22157 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22158 SDValue(ResNode.getNode(), 1));
22161 return DAG.getBitcast(VT, ResNode);
22165 // Emit a zeroed vector and insert the desired subvector on its
22167 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22168 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22169 return DCI.CombineTo(N, InsV);
22172 //===--------------------------------------------------------------------===//
22173 // Combine some shuffles into subvector extracts and inserts:
22176 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22177 if (isShuffleHigh128VectorInsertLow(SVOp)) {
22178 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
22179 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
22180 return DCI.CombineTo(N, InsV);
22183 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22184 if (isShuffleLow128VectorInsertHigh(SVOp)) {
22185 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
22186 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
22187 return DCI.CombineTo(N, InsV);
22193 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22196 /// This is the leaf of the recursive combinine below. When we have found some
22197 /// chain of single-use x86 shuffle instructions and accumulated the combined
22198 /// shuffle mask represented by them, this will try to pattern match that mask
22199 /// into either a single instruction if there is a special purpose instruction
22200 /// for this operation, or into a PSHUFB instruction which is a fully general
22201 /// instruction but should only be used to replace chains over a certain depth.
22202 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22203 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22204 TargetLowering::DAGCombinerInfo &DCI,
22205 const X86Subtarget *Subtarget) {
22206 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22208 // Find the operand that enters the chain. Note that multiple uses are OK
22209 // here, we're not going to remove the operand we find.
22210 SDValue Input = Op.getOperand(0);
22211 while (Input.getOpcode() == ISD::BITCAST)
22212 Input = Input.getOperand(0);
22214 MVT VT = Input.getSimpleValueType();
22215 MVT RootVT = Root.getSimpleValueType();
22218 if (Mask.size() == 1) {
22219 int Index = Mask[0];
22220 assert((Index >= 0 || Index == SM_SentinelUndef ||
22221 Index == SM_SentinelZero) &&
22222 "Invalid shuffle index found!");
22224 // We may end up with an accumulated mask of size 1 as a result of
22225 // widening of shuffle operands (see function canWidenShuffleElements).
22226 // If the only shuffle index is equal to SM_SentinelZero then propagate
22227 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22228 // mask, and therefore the entire chain of shuffles can be folded away.
22229 if (Index == SM_SentinelZero)
22230 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22232 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22237 // Use the float domain if the operand type is a floating point type.
22238 bool FloatDomain = VT.isFloatingPoint();
22240 // For floating point shuffles, we don't have free copies in the shuffle
22241 // instructions or the ability to load as part of the instruction, so
22242 // canonicalize their shuffles to UNPCK or MOV variants.
22244 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22245 // vectors because it can have a load folded into it that UNPCK cannot. This
22246 // doesn't preclude something switching to the shorter encoding post-RA.
22248 // FIXME: Should teach these routines about AVX vector widths.
22249 if (FloatDomain && VT.getSizeInBits() == 128) {
22250 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22251 bool Lo = Mask.equals({0, 0});
22254 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22255 // is no slower than UNPCKLPD but has the option to fold the input operand
22256 // into even an unaligned memory load.
22257 if (Lo && Subtarget->hasSSE3()) {
22258 Shuffle = X86ISD::MOVDDUP;
22259 ShuffleVT = MVT::v2f64;
22261 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22262 // than the UNPCK variants.
22263 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22264 ShuffleVT = MVT::v4f32;
22266 if (Depth == 1 && Root->getOpcode() == Shuffle)
22267 return false; // Nothing to do!
22268 Op = DAG.getBitcast(ShuffleVT, Input);
22269 DCI.AddToWorklist(Op.getNode());
22270 if (Shuffle == X86ISD::MOVDDUP)
22271 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22273 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22274 DCI.AddToWorklist(Op.getNode());
22275 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22279 if (Subtarget->hasSSE3() &&
22280 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22281 bool Lo = Mask.equals({0, 0, 2, 2});
22282 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22283 MVT ShuffleVT = MVT::v4f32;
22284 if (Depth == 1 && Root->getOpcode() == Shuffle)
22285 return false; // Nothing to do!
22286 Op = DAG.getBitcast(ShuffleVT, Input);
22287 DCI.AddToWorklist(Op.getNode());
22288 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22289 DCI.AddToWorklist(Op.getNode());
22290 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22294 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22295 bool Lo = Mask.equals({0, 0, 1, 1});
22296 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22297 MVT ShuffleVT = MVT::v4f32;
22298 if (Depth == 1 && Root->getOpcode() == Shuffle)
22299 return false; // Nothing to do!
22300 Op = DAG.getBitcast(ShuffleVT, Input);
22301 DCI.AddToWorklist(Op.getNode());
22302 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22303 DCI.AddToWorklist(Op.getNode());
22304 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22310 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22311 // variants as none of these have single-instruction variants that are
22312 // superior to the UNPCK formulation.
22313 if (!FloatDomain && VT.getSizeInBits() == 128 &&
22314 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22315 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22316 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22318 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22319 bool Lo = Mask[0] == 0;
22320 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22321 if (Depth == 1 && Root->getOpcode() == Shuffle)
22322 return false; // Nothing to do!
22324 switch (Mask.size()) {
22326 ShuffleVT = MVT::v8i16;
22329 ShuffleVT = MVT::v16i8;
22332 llvm_unreachable("Impossible mask size!");
22334 Op = DAG.getBitcast(ShuffleVT, Input);
22335 DCI.AddToWorklist(Op.getNode());
22336 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22337 DCI.AddToWorklist(Op.getNode());
22338 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22343 // Don't try to re-form single instruction chains under any circumstances now
22344 // that we've done encoding canonicalization for them.
22348 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22349 // can replace them with a single PSHUFB instruction profitably. Intel's
22350 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22351 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22352 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22353 SmallVector<SDValue, 16> PSHUFBMask;
22354 int NumBytes = VT.getSizeInBits() / 8;
22355 int Ratio = NumBytes / Mask.size();
22356 for (int i = 0; i < NumBytes; ++i) {
22357 if (Mask[i / Ratio] == SM_SentinelUndef) {
22358 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22361 int M = Mask[i / Ratio] != SM_SentinelZero
22362 ? Ratio * Mask[i / Ratio] + i % Ratio
22364 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22366 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22367 Op = DAG.getBitcast(ByteVT, Input);
22368 DCI.AddToWorklist(Op.getNode());
22369 SDValue PSHUFBMaskOp =
22370 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22371 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22372 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22373 DCI.AddToWorklist(Op.getNode());
22374 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22379 // Failed to find any combines.
22383 /// \brief Fully generic combining of x86 shuffle instructions.
22385 /// This should be the last combine run over the x86 shuffle instructions. Once
22386 /// they have been fully optimized, this will recursively consider all chains
22387 /// of single-use shuffle instructions, build a generic model of the cumulative
22388 /// shuffle operation, and check for simpler instructions which implement this
22389 /// operation. We use this primarily for two purposes:
22391 /// 1) Collapse generic shuffles to specialized single instructions when
22392 /// equivalent. In most cases, this is just an encoding size win, but
22393 /// sometimes we will collapse multiple generic shuffles into a single
22394 /// special-purpose shuffle.
22395 /// 2) Look for sequences of shuffle instructions with 3 or more total
22396 /// instructions, and replace them with the slightly more expensive SSSE3
22397 /// PSHUFB instruction if available. We do this as the last combining step
22398 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22399 /// a suitable short sequence of other instructions. The PHUFB will either
22400 /// use a register or have to read from memory and so is slightly (but only
22401 /// slightly) more expensive than the other shuffle instructions.
22403 /// Because this is inherently a quadratic operation (for each shuffle in
22404 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22405 /// This should never be an issue in practice as the shuffle lowering doesn't
22406 /// produce sequences of more than 8 instructions.
22408 /// FIXME: We will currently miss some cases where the redundant shuffling
22409 /// would simplify under the threshold for PSHUFB formation because of
22410 /// combine-ordering. To fix this, we should do the redundant instruction
22411 /// combining in this recursive walk.
22412 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22413 ArrayRef<int> RootMask,
22414 int Depth, bool HasPSHUFB,
22416 TargetLowering::DAGCombinerInfo &DCI,
22417 const X86Subtarget *Subtarget) {
22418 // Bound the depth of our recursive combine because this is ultimately
22419 // quadratic in nature.
22423 // Directly rip through bitcasts to find the underlying operand.
22424 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22425 Op = Op.getOperand(0);
22427 MVT VT = Op.getSimpleValueType();
22428 if (!VT.isVector())
22429 return false; // Bail if we hit a non-vector.
22431 assert(Root.getSimpleValueType().isVector() &&
22432 "Shuffles operate on vector types!");
22433 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22434 "Can only combine shuffles of the same vector register size.");
22436 if (!isTargetShuffle(Op.getOpcode()))
22438 SmallVector<int, 16> OpMask;
22440 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22441 // We only can combine unary shuffles which we can decode the mask for.
22442 if (!HaveMask || !IsUnary)
22445 assert(VT.getVectorNumElements() == OpMask.size() &&
22446 "Different mask size from vector size!");
22447 assert(((RootMask.size() > OpMask.size() &&
22448 RootMask.size() % OpMask.size() == 0) ||
22449 (OpMask.size() > RootMask.size() &&
22450 OpMask.size() % RootMask.size() == 0) ||
22451 OpMask.size() == RootMask.size()) &&
22452 "The smaller number of elements must divide the larger.");
22453 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22454 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22455 assert(((RootRatio == 1 && OpRatio == 1) ||
22456 (RootRatio == 1) != (OpRatio == 1)) &&
22457 "Must not have a ratio for both incoming and op masks!");
22459 SmallVector<int, 16> Mask;
22460 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22462 // Merge this shuffle operation's mask into our accumulated mask. Note that
22463 // this shuffle's mask will be the first applied to the input, followed by the
22464 // root mask to get us all the way to the root value arrangement. The reason
22465 // for this order is that we are recursing up the operation chain.
22466 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22467 int RootIdx = i / RootRatio;
22468 if (RootMask[RootIdx] < 0) {
22469 // This is a zero or undef lane, we're done.
22470 Mask.push_back(RootMask[RootIdx]);
22474 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22475 int OpIdx = RootMaskedIdx / OpRatio;
22476 if (OpMask[OpIdx] < 0) {
22477 // The incoming lanes are zero or undef, it doesn't matter which ones we
22479 Mask.push_back(OpMask[OpIdx]);
22483 // Ok, we have non-zero lanes, map them through.
22484 Mask.push_back(OpMask[OpIdx] * OpRatio +
22485 RootMaskedIdx % OpRatio);
22488 // See if we can recurse into the operand to combine more things.
22489 switch (Op.getOpcode()) {
22490 case X86ISD::PSHUFB:
22492 case X86ISD::PSHUFD:
22493 case X86ISD::PSHUFHW:
22494 case X86ISD::PSHUFLW:
22495 if (Op.getOperand(0).hasOneUse() &&
22496 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22497 HasPSHUFB, DAG, DCI, Subtarget))
22501 case X86ISD::UNPCKL:
22502 case X86ISD::UNPCKH:
22503 assert(Op.getOperand(0) == Op.getOperand(1) &&
22504 "We only combine unary shuffles!");
22505 // We can't check for single use, we have to check that this shuffle is the
22507 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22508 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22509 HasPSHUFB, DAG, DCI, Subtarget))
22514 // Minor canonicalization of the accumulated shuffle mask to make it easier
22515 // to match below. All this does is detect masks with squential pairs of
22516 // elements, and shrink them to the half-width mask. It does this in a loop
22517 // so it will reduce the size of the mask to the minimal width mask which
22518 // performs an equivalent shuffle.
22519 SmallVector<int, 16> WidenedMask;
22520 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22521 Mask = std::move(WidenedMask);
22522 WidenedMask.clear();
22525 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22529 /// \brief Get the PSHUF-style mask from PSHUF node.
22531 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22532 /// PSHUF-style masks that can be reused with such instructions.
22533 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22534 MVT VT = N.getSimpleValueType();
22535 SmallVector<int, 4> Mask;
22537 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22541 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22542 // matter. Check that the upper masks are repeats and remove them.
22543 if (VT.getSizeInBits() > 128) {
22544 int LaneElts = 128 / VT.getScalarSizeInBits();
22546 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22547 for (int j = 0; j < LaneElts; ++j)
22548 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22549 "Mask doesn't repeat in high 128-bit lanes!");
22551 Mask.resize(LaneElts);
22554 switch (N.getOpcode()) {
22555 case X86ISD::PSHUFD:
22557 case X86ISD::PSHUFLW:
22560 case X86ISD::PSHUFHW:
22561 Mask.erase(Mask.begin(), Mask.begin() + 4);
22562 for (int &M : Mask)
22566 llvm_unreachable("No valid shuffle instruction found!");
22570 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22572 /// We walk up the chain and look for a combinable shuffle, skipping over
22573 /// shuffles that we could hoist this shuffle's transformation past without
22574 /// altering anything.
22576 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22578 TargetLowering::DAGCombinerInfo &DCI) {
22579 assert(N.getOpcode() == X86ISD::PSHUFD &&
22580 "Called with something other than an x86 128-bit half shuffle!");
22583 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22584 // of the shuffles in the chain so that we can form a fresh chain to replace
22586 SmallVector<SDValue, 8> Chain;
22587 SDValue V = N.getOperand(0);
22588 for (; V.hasOneUse(); V = V.getOperand(0)) {
22589 switch (V.getOpcode()) {
22591 return SDValue(); // Nothing combined!
22594 // Skip bitcasts as we always know the type for the target specific
22598 case X86ISD::PSHUFD:
22599 // Found another dword shuffle.
22602 case X86ISD::PSHUFLW:
22603 // Check that the low words (being shuffled) are the identity in the
22604 // dword shuffle, and the high words are self-contained.
22605 if (Mask[0] != 0 || Mask[1] != 1 ||
22606 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22609 Chain.push_back(V);
22612 case X86ISD::PSHUFHW:
22613 // Check that the high words (being shuffled) are the identity in the
22614 // dword shuffle, and the low words are self-contained.
22615 if (Mask[2] != 2 || Mask[3] != 3 ||
22616 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22619 Chain.push_back(V);
22622 case X86ISD::UNPCKL:
22623 case X86ISD::UNPCKH:
22624 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22625 // shuffle into a preceding word shuffle.
22626 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
22627 V.getSimpleValueType().getScalarType() != MVT::i16)
22630 // Search for a half-shuffle which we can combine with.
22631 unsigned CombineOp =
22632 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22633 if (V.getOperand(0) != V.getOperand(1) ||
22634 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22636 Chain.push_back(V);
22637 V = V.getOperand(0);
22639 switch (V.getOpcode()) {
22641 return SDValue(); // Nothing to combine.
22643 case X86ISD::PSHUFLW:
22644 case X86ISD::PSHUFHW:
22645 if (V.getOpcode() == CombineOp)
22648 Chain.push_back(V);
22652 V = V.getOperand(0);
22656 } while (V.hasOneUse());
22659 // Break out of the loop if we break out of the switch.
22663 if (!V.hasOneUse())
22664 // We fell out of the loop without finding a viable combining instruction.
22667 // Merge this node's mask and our incoming mask.
22668 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22669 for (int &M : Mask)
22671 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22672 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22674 // Rebuild the chain around this new shuffle.
22675 while (!Chain.empty()) {
22676 SDValue W = Chain.pop_back_val();
22678 if (V.getValueType() != W.getOperand(0).getValueType())
22679 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22681 switch (W.getOpcode()) {
22683 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22685 case X86ISD::UNPCKL:
22686 case X86ISD::UNPCKH:
22687 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22690 case X86ISD::PSHUFD:
22691 case X86ISD::PSHUFLW:
22692 case X86ISD::PSHUFHW:
22693 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22697 if (V.getValueType() != N.getValueType())
22698 V = DAG.getBitcast(N.getValueType(), V);
22700 // Return the new chain to replace N.
22704 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22707 /// We walk up the chain, skipping shuffles of the other half and looking
22708 /// through shuffles which switch halves trying to find a shuffle of the same
22709 /// pair of dwords.
22710 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22712 TargetLowering::DAGCombinerInfo &DCI) {
22714 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22715 "Called with something other than an x86 128-bit half shuffle!");
22717 unsigned CombineOpcode = N.getOpcode();
22719 // Walk up a single-use chain looking for a combinable shuffle.
22720 SDValue V = N.getOperand(0);
22721 for (; V.hasOneUse(); V = V.getOperand(0)) {
22722 switch (V.getOpcode()) {
22724 return false; // Nothing combined!
22727 // Skip bitcasts as we always know the type for the target specific
22731 case X86ISD::PSHUFLW:
22732 case X86ISD::PSHUFHW:
22733 if (V.getOpcode() == CombineOpcode)
22736 // Other-half shuffles are no-ops.
22739 // Break out of the loop if we break out of the switch.
22743 if (!V.hasOneUse())
22744 // We fell out of the loop without finding a viable combining instruction.
22747 // Combine away the bottom node as its shuffle will be accumulated into
22748 // a preceding shuffle.
22749 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22751 // Record the old value.
22754 // Merge this node's mask and our incoming mask (adjusted to account for all
22755 // the pshufd instructions encountered).
22756 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22757 for (int &M : Mask)
22759 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22760 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22762 // Check that the shuffles didn't cancel each other out. If not, we need to
22763 // combine to the new one.
22765 // Replace the combinable shuffle with the combined one, updating all users
22766 // so that we re-evaluate the chain here.
22767 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22772 /// \brief Try to combine x86 target specific shuffles.
22773 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22774 TargetLowering::DAGCombinerInfo &DCI,
22775 const X86Subtarget *Subtarget) {
22777 MVT VT = N.getSimpleValueType();
22778 SmallVector<int, 4> Mask;
22780 switch (N.getOpcode()) {
22781 case X86ISD::PSHUFD:
22782 case X86ISD::PSHUFLW:
22783 case X86ISD::PSHUFHW:
22784 Mask = getPSHUFShuffleMask(N);
22785 assert(Mask.size() == 4);
22791 // Nuke no-op shuffles that show up after combining.
22792 if (isNoopShuffleMask(Mask))
22793 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22795 // Look for simplifications involving one or two shuffle instructions.
22796 SDValue V = N.getOperand(0);
22797 switch (N.getOpcode()) {
22800 case X86ISD::PSHUFLW:
22801 case X86ISD::PSHUFHW:
22802 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
22804 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22805 return SDValue(); // We combined away this shuffle, so we're done.
22807 // See if this reduces to a PSHUFD which is no more expensive and can
22808 // combine with more operations. Note that it has to at least flip the
22809 // dwords as otherwise it would have been removed as a no-op.
22810 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
22811 int DMask[] = {0, 1, 2, 3};
22812 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22813 DMask[DOffset + 0] = DOffset + 1;
22814 DMask[DOffset + 1] = DOffset + 0;
22815 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
22816 V = DAG.getBitcast(DVT, V);
22817 DCI.AddToWorklist(V.getNode());
22818 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
22819 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
22820 DCI.AddToWorklist(V.getNode());
22821 return DAG.getBitcast(VT, V);
22824 // Look for shuffle patterns which can be implemented as a single unpack.
22825 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22826 // only works when we have a PSHUFD followed by two half-shuffles.
22827 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22828 (V.getOpcode() == X86ISD::PSHUFLW ||
22829 V.getOpcode() == X86ISD::PSHUFHW) &&
22830 V.getOpcode() != N.getOpcode() &&
22832 SDValue D = V.getOperand(0);
22833 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22834 D = D.getOperand(0);
22835 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22836 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22837 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22838 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22839 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22841 for (int i = 0; i < 4; ++i) {
22842 WordMask[i + NOffset] = Mask[i] + NOffset;
22843 WordMask[i + VOffset] = VMask[i] + VOffset;
22845 // Map the word mask through the DWord mask.
22847 for (int i = 0; i < 8; ++i)
22848 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22849 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22850 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
22851 // We can replace all three shuffles with an unpack.
22852 V = DAG.getBitcast(VT, D.getOperand(0));
22853 DCI.AddToWorklist(V.getNode());
22854 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22863 case X86ISD::PSHUFD:
22864 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22873 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22875 /// We combine this directly on the abstract vector shuffle nodes so it is
22876 /// easier to generically match. We also insert dummy vector shuffle nodes for
22877 /// the operands which explicitly discard the lanes which are unused by this
22878 /// operation to try to flow through the rest of the combiner the fact that
22879 /// they're unused.
22880 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22882 EVT VT = N->getValueType(0);
22884 // We only handle target-independent shuffles.
22885 // FIXME: It would be easy and harmless to use the target shuffle mask
22886 // extraction tool to support more.
22887 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22890 auto *SVN = cast<ShuffleVectorSDNode>(N);
22891 ArrayRef<int> Mask = SVN->getMask();
22892 SDValue V1 = N->getOperand(0);
22893 SDValue V2 = N->getOperand(1);
22895 // We require the first shuffle operand to be the SUB node, and the second to
22896 // be the ADD node.
22897 // FIXME: We should support the commuted patterns.
22898 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22901 // If there are other uses of these operations we can't fold them.
22902 if (!V1->hasOneUse() || !V2->hasOneUse())
22905 // Ensure that both operations have the same operands. Note that we can
22906 // commute the FADD operands.
22907 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22908 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22909 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22912 // We're looking for blends between FADD and FSUB nodes. We insist on these
22913 // nodes being lined up in a specific expected pattern.
22914 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22915 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22916 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22919 // Only specific types are legal at this point, assert so we notice if and
22920 // when these change.
22921 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22922 VT == MVT::v4f64) &&
22923 "Unknown vector type encountered!");
22925 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22928 /// PerformShuffleCombine - Performs several different shuffle combines.
22929 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22930 TargetLowering::DAGCombinerInfo &DCI,
22931 const X86Subtarget *Subtarget) {
22933 SDValue N0 = N->getOperand(0);
22934 SDValue N1 = N->getOperand(1);
22935 EVT VT = N->getValueType(0);
22937 // Don't create instructions with illegal types after legalize types has run.
22938 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22939 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22942 // If we have legalized the vector types, look for blends of FADD and FSUB
22943 // nodes that we can fuse into an ADDSUB node.
22944 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22945 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22948 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22949 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22950 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22951 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22953 // During Type Legalization, when promoting illegal vector types,
22954 // the backend might introduce new shuffle dag nodes and bitcasts.
22956 // This code performs the following transformation:
22957 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22958 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22960 // We do this only if both the bitcast and the BINOP dag nodes have
22961 // one use. Also, perform this transformation only if the new binary
22962 // operation is legal. This is to avoid introducing dag nodes that
22963 // potentially need to be further expanded (or custom lowered) into a
22964 // less optimal sequence of dag nodes.
22965 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22966 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22967 N0.getOpcode() == ISD::BITCAST) {
22968 SDValue BC0 = N0.getOperand(0);
22969 EVT SVT = BC0.getValueType();
22970 unsigned Opcode = BC0.getOpcode();
22971 unsigned NumElts = VT.getVectorNumElements();
22973 if (BC0.hasOneUse() && SVT.isVector() &&
22974 SVT.getVectorNumElements() * 2 == NumElts &&
22975 TLI.isOperationLegal(Opcode, VT)) {
22976 bool CanFold = false;
22988 unsigned SVTNumElts = SVT.getVectorNumElements();
22989 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22990 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22991 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22992 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22993 CanFold = SVOp->getMaskElt(i) < 0;
22996 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
22997 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
22998 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22999 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
23004 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
23005 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
23006 // consecutive, non-overlapping, and in the right order.
23007 SmallVector<SDValue, 16> Elts;
23008 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
23009 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
23011 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
23014 if (isTargetShuffle(N->getOpcode())) {
23016 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
23017 if (Shuffle.getNode())
23020 // Try recursively combining arbitrary sequences of x86 shuffle
23021 // instructions into higher-order shuffles. We do this after combining
23022 // specific PSHUF instruction sequences into their minimal form so that we
23023 // can evaluate how many specialized shuffle instructions are involved in
23024 // a particular chain.
23025 SmallVector<int, 1> NonceMask; // Just a placeholder.
23026 NonceMask.push_back(0);
23027 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
23028 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
23030 return SDValue(); // This routine will use CombineTo to replace N.
23036 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23037 /// specific shuffle of a load can be folded into a single element load.
23038 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23039 /// shuffles have been custom lowered so we need to handle those here.
23040 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23041 TargetLowering::DAGCombinerInfo &DCI) {
23042 if (DCI.isBeforeLegalizeOps())
23045 SDValue InVec = N->getOperand(0);
23046 SDValue EltNo = N->getOperand(1);
23048 if (!isa<ConstantSDNode>(EltNo))
23051 EVT OriginalVT = InVec.getValueType();
23053 if (InVec.getOpcode() == ISD::BITCAST) {
23054 // Don't duplicate a load with other uses.
23055 if (!InVec.hasOneUse())
23057 EVT BCVT = InVec.getOperand(0).getValueType();
23058 if (!BCVT.isVector() ||
23059 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23061 InVec = InVec.getOperand(0);
23064 EVT CurrentVT = InVec.getValueType();
23066 if (!isTargetShuffle(InVec.getOpcode()))
23069 // Don't duplicate a load with other uses.
23070 if (!InVec.hasOneUse())
23073 SmallVector<int, 16> ShuffleMask;
23075 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
23076 ShuffleMask, UnaryShuffle))
23079 // Select the input vector, guarding against out of range extract vector.
23080 unsigned NumElems = CurrentVT.getVectorNumElements();
23081 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23082 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
23083 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23084 : InVec.getOperand(1);
23086 // If inputs to shuffle are the same for both ops, then allow 2 uses
23087 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23088 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23090 if (LdNode.getOpcode() == ISD::BITCAST) {
23091 // Don't duplicate a load with other uses.
23092 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23095 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23096 LdNode = LdNode.getOperand(0);
23099 if (!ISD::isNormalLoad(LdNode.getNode()))
23102 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23104 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23107 EVT EltVT = N->getValueType(0);
23108 // If there's a bitcast before the shuffle, check if the load type and
23109 // alignment is valid.
23110 unsigned Align = LN0->getAlignment();
23111 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23112 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23113 EltVT.getTypeForEVT(*DAG.getContext()));
23115 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23118 // All checks match so transform back to vector_shuffle so that DAG combiner
23119 // can finish the job
23122 // Create shuffle node taking into account the case that its a unary shuffle
23123 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23124 : InVec.getOperand(1);
23125 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23126 InVec.getOperand(0), Shuffle,
23128 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23129 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23133 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23134 /// special and don't usually play with other vector types, it's better to
23135 /// handle them early to be sure we emit efficient code by avoiding
23136 /// store-load conversions.
23137 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
23138 if (N->getValueType(0) != MVT::x86mmx ||
23139 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
23140 N->getOperand(0)->getValueType(0) != MVT::v2i32)
23143 SDValue V = N->getOperand(0);
23144 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
23145 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
23146 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
23147 N->getValueType(0), V.getOperand(0));
23152 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23153 /// generation and convert it from being a bunch of shuffles and extracts
23154 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23155 /// storing the value and loading scalars back, while for x64 we should
23156 /// use 64-bit extracts and shifts.
23157 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23158 TargetLowering::DAGCombinerInfo &DCI) {
23159 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23162 SDValue InputVector = N->getOperand(0);
23163 SDLoc dl(InputVector);
23164 // Detect mmx to i32 conversion through a v2i32 elt extract.
23165 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23166 N->getValueType(0) == MVT::i32 &&
23167 InputVector.getValueType() == MVT::v2i32) {
23169 // The bitcast source is a direct mmx result.
23170 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23171 if (MMXSrc.getValueType() == MVT::x86mmx)
23172 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23173 N->getValueType(0),
23174 InputVector.getNode()->getOperand(0));
23176 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23177 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23178 MMXSrc.getValueType() == MVT::i64) {
23179 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23180 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23181 MMXSrcOp.getValueType() == MVT::v1i64 &&
23182 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23183 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23184 N->getValueType(0), MMXSrcOp.getOperand(0));
23188 EVT VT = N->getValueType(0);
23190 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
23191 InputVector.getOpcode() == ISD::BITCAST &&
23192 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
23193 uint64_t ExtractedElt =
23194 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23195 uint64_t InputValue =
23196 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23197 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23198 return DAG.getConstant(Res, dl, MVT::i1);
23200 // Only operate on vectors of 4 elements, where the alternative shuffling
23201 // gets to be more expensive.
23202 if (InputVector.getValueType() != MVT::v4i32)
23205 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23206 // single use which is a sign-extend or zero-extend, and all elements are
23208 SmallVector<SDNode *, 4> Uses;
23209 unsigned ExtractedElements = 0;
23210 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23211 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23212 if (UI.getUse().getResNo() != InputVector.getResNo())
23215 SDNode *Extract = *UI;
23216 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23219 if (Extract->getValueType(0) != MVT::i32)
23221 if (!Extract->hasOneUse())
23223 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23224 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23226 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23229 // Record which element was extracted.
23230 ExtractedElements |=
23231 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23233 Uses.push_back(Extract);
23236 // If not all the elements were used, this may not be worthwhile.
23237 if (ExtractedElements != 15)
23240 // Ok, we've now decided to do the transformation.
23241 // If 64-bit shifts are legal, use the extract-shift sequence,
23242 // otherwise bounce the vector off the cache.
23243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23246 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23247 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23248 auto &DL = DAG.getDataLayout();
23249 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23250 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23251 DAG.getConstant(0, dl, VecIdxTy));
23252 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23253 DAG.getConstant(1, dl, VecIdxTy));
23255 SDValue ShAmt = DAG.getConstant(
23256 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23257 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23258 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23259 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23260 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23261 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23262 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23264 // Store the value to a temporary stack slot.
23265 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23266 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23267 MachinePointerInfo(), false, false, 0);
23269 EVT ElementType = InputVector.getValueType().getVectorElementType();
23270 unsigned EltSize = ElementType.getSizeInBits() / 8;
23272 // Replace each use (extract) with a load of the appropriate element.
23273 for (unsigned i = 0; i < 4; ++i) {
23274 uint64_t Offset = EltSize * i;
23275 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23276 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23278 SDValue ScalarAddr =
23279 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23281 // Load the scalar.
23282 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23283 ScalarAddr, MachinePointerInfo(),
23284 false, false, false, 0);
23289 // Replace the extracts
23290 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23291 UE = Uses.end(); UI != UE; ++UI) {
23292 SDNode *Extract = *UI;
23294 SDValue Idx = Extract->getOperand(1);
23295 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23296 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23299 // The replacement was made in place; don't return anything.
23304 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23305 const X86Subtarget *Subtarget) {
23307 SDValue Cond = N->getOperand(0);
23308 SDValue LHS = N->getOperand(1);
23309 SDValue RHS = N->getOperand(2);
23311 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23312 SDValue CondSrc = Cond->getOperand(0);
23313 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23314 Cond = CondSrc->getOperand(0);
23317 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23320 // A vselect where all conditions and data are constants can be optimized into
23321 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23322 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23323 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23326 unsigned MaskValue = 0;
23327 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23330 MVT VT = N->getSimpleValueType(0);
23331 unsigned NumElems = VT.getVectorNumElements();
23332 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23333 for (unsigned i = 0; i < NumElems; ++i) {
23334 // Be sure we emit undef where we can.
23335 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23336 ShuffleMask[i] = -1;
23338 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23341 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23342 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23344 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23347 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23349 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23350 TargetLowering::DAGCombinerInfo &DCI,
23351 const X86Subtarget *Subtarget) {
23353 SDValue Cond = N->getOperand(0);
23354 // Get the LHS/RHS of the select.
23355 SDValue LHS = N->getOperand(1);
23356 SDValue RHS = N->getOperand(2);
23357 EVT VT = LHS.getValueType();
23358 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23360 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23361 // instructions match the semantics of the common C idiom x<y?x:y but not
23362 // x<=y?x:y, because of how they handle negative zero (which can be
23363 // ignored in unsafe-math mode).
23364 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23365 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23366 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23367 (Subtarget->hasSSE2() ||
23368 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23369 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23371 unsigned Opcode = 0;
23372 // Check for x CC y ? x : y.
23373 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23374 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23378 // Converting this to a min would handle NaNs incorrectly, and swapping
23379 // the operands would cause it to handle comparisons between positive
23380 // and negative zero incorrectly.
23381 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23382 if (!DAG.getTarget().Options.UnsafeFPMath &&
23383 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23385 std::swap(LHS, RHS);
23387 Opcode = X86ISD::FMIN;
23390 // Converting this to a min would handle comparisons between positive
23391 // and negative zero incorrectly.
23392 if (!DAG.getTarget().Options.UnsafeFPMath &&
23393 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23395 Opcode = X86ISD::FMIN;
23398 // Converting this to a min would handle both negative zeros and NaNs
23399 // incorrectly, but we can swap the operands to fix both.
23400 std::swap(LHS, RHS);
23404 Opcode = X86ISD::FMIN;
23408 // Converting this to a max would handle comparisons between positive
23409 // and negative zero incorrectly.
23410 if (!DAG.getTarget().Options.UnsafeFPMath &&
23411 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23413 Opcode = X86ISD::FMAX;
23416 // Converting this to a max would handle NaNs incorrectly, and swapping
23417 // the operands would cause it to handle comparisons between positive
23418 // and negative zero incorrectly.
23419 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23420 if (!DAG.getTarget().Options.UnsafeFPMath &&
23421 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23423 std::swap(LHS, RHS);
23425 Opcode = X86ISD::FMAX;
23428 // Converting this to a max would handle both negative zeros and NaNs
23429 // incorrectly, but we can swap the operands to fix both.
23430 std::swap(LHS, RHS);
23434 Opcode = X86ISD::FMAX;
23437 // Check for x CC y ? y : x -- a min/max with reversed arms.
23438 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23439 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23443 // Converting this to a min would handle comparisons between positive
23444 // and negative zero incorrectly, and swapping the operands would
23445 // cause it to handle NaNs incorrectly.
23446 if (!DAG.getTarget().Options.UnsafeFPMath &&
23447 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23448 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23450 std::swap(LHS, RHS);
23452 Opcode = X86ISD::FMIN;
23455 // Converting this to a min would handle NaNs incorrectly.
23456 if (!DAG.getTarget().Options.UnsafeFPMath &&
23457 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23459 Opcode = X86ISD::FMIN;
23462 // Converting this to a min would handle both negative zeros and NaNs
23463 // incorrectly, but we can swap the operands to fix both.
23464 std::swap(LHS, RHS);
23468 Opcode = X86ISD::FMIN;
23472 // Converting this to a max would handle NaNs incorrectly.
23473 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23475 Opcode = X86ISD::FMAX;
23478 // Converting this to a max would handle comparisons between positive
23479 // and negative zero incorrectly, and swapping the operands would
23480 // cause it to handle NaNs incorrectly.
23481 if (!DAG.getTarget().Options.UnsafeFPMath &&
23482 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23483 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23485 std::swap(LHS, RHS);
23487 Opcode = X86ISD::FMAX;
23490 // Converting this to a max would handle both negative zeros and NaNs
23491 // incorrectly, but we can swap the operands to fix both.
23492 std::swap(LHS, RHS);
23496 Opcode = X86ISD::FMAX;
23502 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23505 EVT CondVT = Cond.getValueType();
23506 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23507 CondVT.getVectorElementType() == MVT::i1) {
23508 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23509 // lowering on KNL. In this case we convert it to
23510 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23511 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23512 // Since SKX these selects have a proper lowering.
23513 EVT OpVT = LHS.getValueType();
23514 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23515 (OpVT.getVectorElementType() == MVT::i8 ||
23516 OpVT.getVectorElementType() == MVT::i16) &&
23517 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23518 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23519 DCI.AddToWorklist(Cond.getNode());
23520 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23523 // If this is a select between two integer constants, try to do some
23525 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23526 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23527 // Don't do this for crazy integer types.
23528 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23529 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23530 // so that TrueC (the true value) is larger than FalseC.
23531 bool NeedsCondInvert = false;
23533 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23534 // Efficiently invertible.
23535 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23536 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23537 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23538 NeedsCondInvert = true;
23539 std::swap(TrueC, FalseC);
23542 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23543 if (FalseC->getAPIntValue() == 0 &&
23544 TrueC->getAPIntValue().isPowerOf2()) {
23545 if (NeedsCondInvert) // Invert the condition if needed.
23546 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23547 DAG.getConstant(1, DL, Cond.getValueType()));
23549 // Zero extend the condition if needed.
23550 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23552 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23553 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23554 DAG.getConstant(ShAmt, DL, MVT::i8));
23557 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23558 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23559 if (NeedsCondInvert) // Invert the condition if needed.
23560 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23561 DAG.getConstant(1, DL, Cond.getValueType()));
23563 // Zero extend the condition if needed.
23564 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23565 FalseC->getValueType(0), Cond);
23566 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23567 SDValue(FalseC, 0));
23570 // Optimize cases that will turn into an LEA instruction. This requires
23571 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23572 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23573 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23574 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23576 bool isFastMultiplier = false;
23578 switch ((unsigned char)Diff) {
23580 case 1: // result = add base, cond
23581 case 2: // result = lea base( , cond*2)
23582 case 3: // result = lea base(cond, cond*2)
23583 case 4: // result = lea base( , cond*4)
23584 case 5: // result = lea base(cond, cond*4)
23585 case 8: // result = lea base( , cond*8)
23586 case 9: // result = lea base(cond, cond*8)
23587 isFastMultiplier = true;
23592 if (isFastMultiplier) {
23593 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23594 if (NeedsCondInvert) // Invert the condition if needed.
23595 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23596 DAG.getConstant(1, DL, Cond.getValueType()));
23598 // Zero extend the condition if needed.
23599 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23601 // Scale the condition by the difference.
23603 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23604 DAG.getConstant(Diff, DL,
23605 Cond.getValueType()));
23607 // Add the base if non-zero.
23608 if (FalseC->getAPIntValue() != 0)
23609 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23610 SDValue(FalseC, 0));
23617 // Canonicalize max and min:
23618 // (x > y) ? x : y -> (x >= y) ? x : y
23619 // (x < y) ? x : y -> (x <= y) ? x : y
23620 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23621 // the need for an extra compare
23622 // against zero. e.g.
23623 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23625 // testl %edi, %edi
23627 // cmovgl %edi, %eax
23631 // cmovsl %eax, %edi
23632 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23633 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23634 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23635 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23640 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23641 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23642 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23643 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23648 // Early exit check
23649 if (!TLI.isTypeLegal(VT))
23652 // Match VSELECTs into subs with unsigned saturation.
23653 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23654 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23655 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23656 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23657 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23659 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23660 // left side invert the predicate to simplify logic below.
23662 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23664 CC = ISD::getSetCCInverse(CC, true);
23665 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23669 if (Other.getNode() && Other->getNumOperands() == 2 &&
23670 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23671 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23672 SDValue CondRHS = Cond->getOperand(1);
23674 // Look for a general sub with unsigned saturation first.
23675 // x >= y ? x-y : 0 --> subus x, y
23676 // x > y ? x-y : 0 --> subus x, y
23677 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23678 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23679 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23681 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23682 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23683 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23684 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23685 // If the RHS is a constant we have to reverse the const
23686 // canonicalization.
23687 // x > C-1 ? x+-C : 0 --> subus x, C
23688 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23689 CondRHSConst->getAPIntValue() ==
23690 (-OpRHSConst->getAPIntValue() - 1))
23691 return DAG.getNode(
23692 X86ISD::SUBUS, DL, VT, OpLHS,
23693 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23695 // Another special case: If C was a sign bit, the sub has been
23696 // canonicalized into a xor.
23697 // FIXME: Would it be better to use computeKnownBits to determine
23698 // whether it's safe to decanonicalize the xor?
23699 // x s< 0 ? x^C : 0 --> subus x, C
23700 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23701 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23702 OpRHSConst->getAPIntValue().isSignBit())
23703 // Note that we have to rebuild the RHS constant here to ensure we
23704 // don't rely on particular values of undef lanes.
23705 return DAG.getNode(
23706 X86ISD::SUBUS, DL, VT, OpLHS,
23707 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23712 // Simplify vector selection if condition value type matches vselect
23714 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23715 assert(Cond.getValueType().isVector() &&
23716 "vector select expects a vector selector!");
23718 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23719 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23721 // Try invert the condition if true value is not all 1s and false value
23723 if (!TValIsAllOnes && !FValIsAllZeros &&
23724 // Check if the selector will be produced by CMPP*/PCMP*
23725 Cond.getOpcode() == ISD::SETCC &&
23726 // Check if SETCC has already been promoted
23727 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23729 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23730 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23732 if (TValIsAllZeros || FValIsAllOnes) {
23733 SDValue CC = Cond.getOperand(2);
23734 ISD::CondCode NewCC =
23735 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23736 Cond.getOperand(0).getValueType().isInteger());
23737 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23738 std::swap(LHS, RHS);
23739 TValIsAllOnes = FValIsAllOnes;
23740 FValIsAllZeros = TValIsAllZeros;
23744 if (TValIsAllOnes || FValIsAllZeros) {
23747 if (TValIsAllOnes && FValIsAllZeros)
23749 else if (TValIsAllOnes)
23751 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
23752 else if (FValIsAllZeros)
23753 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23754 DAG.getBitcast(CondVT, LHS));
23756 return DAG.getBitcast(VT, Ret);
23760 // We should generate an X86ISD::BLENDI from a vselect if its argument
23761 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23762 // constants. This specific pattern gets generated when we split a
23763 // selector for a 512 bit vector in a machine without AVX512 (but with
23764 // 256-bit vectors), during legalization:
23766 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23768 // Iff we find this pattern and the build_vectors are built from
23769 // constants, we translate the vselect into a shuffle_vector that we
23770 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23771 if ((N->getOpcode() == ISD::VSELECT ||
23772 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23773 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
23774 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23775 if (Shuffle.getNode())
23779 // If this is a *dynamic* select (non-constant condition) and we can match
23780 // this node with one of the variable blend instructions, restructure the
23781 // condition so that the blends can use the high bit of each element and use
23782 // SimplifyDemandedBits to simplify the condition operand.
23783 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23784 !DCI.isBeforeLegalize() &&
23785 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23786 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23788 // Don't optimize vector selects that map to mask-registers.
23792 // We can only handle the cases where VSELECT is directly legal on the
23793 // subtarget. We custom lower VSELECT nodes with constant conditions and
23794 // this makes it hard to see whether a dynamic VSELECT will correctly
23795 // lower, so we both check the operation's status and explicitly handle the
23796 // cases where a *dynamic* blend will fail even though a constant-condition
23797 // blend could be custom lowered.
23798 // FIXME: We should find a better way to handle this class of problems.
23799 // Potentially, we should combine constant-condition vselect nodes
23800 // pre-legalization into shuffles and not mark as many types as custom
23802 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
23804 // FIXME: We don't support i16-element blends currently. We could and
23805 // should support them by making *all* the bits in the condition be set
23806 // rather than just the high bit and using an i8-element blend.
23807 if (VT.getScalarType() == MVT::i16)
23809 // Dynamic blending was only available from SSE4.1 onward.
23810 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
23812 // Byte blends are only available in AVX2
23813 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
23814 !Subtarget->hasAVX2())
23817 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23818 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23820 APInt KnownZero, KnownOne;
23821 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23822 DCI.isBeforeLegalizeOps());
23823 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23824 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23826 // If we changed the computation somewhere in the DAG, this change
23827 // will affect all users of Cond.
23828 // Make sure it is fine and update all the nodes so that we do not
23829 // use the generic VSELECT anymore. Otherwise, we may perform
23830 // wrong optimizations as we messed up with the actual expectation
23831 // for the vector boolean values.
23832 if (Cond != TLO.Old) {
23833 // Check all uses of that condition operand to check whether it will be
23834 // consumed by non-BLEND instructions, which may depend on all bits are
23836 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23838 if (I->getOpcode() != ISD::VSELECT)
23839 // TODO: Add other opcodes eventually lowered into BLEND.
23842 // Update all the users of the condition, before committing the change,
23843 // so that the VSELECT optimizations that expect the correct vector
23844 // boolean value will not be triggered.
23845 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23847 DAG.ReplaceAllUsesOfValueWith(
23849 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23850 Cond, I->getOperand(1), I->getOperand(2)));
23851 DCI.CommitTargetLoweringOpt(TLO);
23854 // At this point, only Cond is changed. Change the condition
23855 // just for N to keep the opportunity to optimize all other
23856 // users their own way.
23857 DAG.ReplaceAllUsesOfValueWith(
23859 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23860 TLO.New, N->getOperand(1), N->getOperand(2)));
23868 // Check whether a boolean test is testing a boolean value generated by
23869 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23872 // Simplify the following patterns:
23873 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23874 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23875 // to (Op EFLAGS Cond)
23877 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23878 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23879 // to (Op EFLAGS !Cond)
23881 // where Op could be BRCOND or CMOV.
23883 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23884 // Quit if not CMP and SUB with its value result used.
23885 if (Cmp.getOpcode() != X86ISD::CMP &&
23886 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23889 // Quit if not used as a boolean value.
23890 if (CC != X86::COND_E && CC != X86::COND_NE)
23893 // Check CMP operands. One of them should be 0 or 1 and the other should be
23894 // an SetCC or extended from it.
23895 SDValue Op1 = Cmp.getOperand(0);
23896 SDValue Op2 = Cmp.getOperand(1);
23899 const ConstantSDNode* C = nullptr;
23900 bool needOppositeCond = (CC == X86::COND_E);
23901 bool checkAgainstTrue = false; // Is it a comparison against 1?
23903 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23905 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23907 else // Quit if all operands are not constants.
23910 if (C->getZExtValue() == 1) {
23911 needOppositeCond = !needOppositeCond;
23912 checkAgainstTrue = true;
23913 } else if (C->getZExtValue() != 0)
23914 // Quit if the constant is neither 0 or 1.
23917 bool truncatedToBoolWithAnd = false;
23918 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23919 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23920 SetCC.getOpcode() == ISD::TRUNCATE ||
23921 SetCC.getOpcode() == ISD::AND) {
23922 if (SetCC.getOpcode() == ISD::AND) {
23924 ConstantSDNode *CS;
23925 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23926 CS->getZExtValue() == 1)
23928 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23929 CS->getZExtValue() == 1)
23933 SetCC = SetCC.getOperand(OpIdx);
23934 truncatedToBoolWithAnd = true;
23936 SetCC = SetCC.getOperand(0);
23939 switch (SetCC.getOpcode()) {
23940 case X86ISD::SETCC_CARRY:
23941 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23942 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23943 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23944 // truncated to i1 using 'and'.
23945 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23947 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23948 "Invalid use of SETCC_CARRY!");
23950 case X86ISD::SETCC:
23951 // Set the condition code or opposite one if necessary.
23952 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23953 if (needOppositeCond)
23954 CC = X86::GetOppositeBranchCondition(CC);
23955 return SetCC.getOperand(1);
23956 case X86ISD::CMOV: {
23957 // Check whether false/true value has canonical one, i.e. 0 or 1.
23958 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23959 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23960 // Quit if true value is not a constant.
23963 // Quit if false value is not a constant.
23965 SDValue Op = SetCC.getOperand(0);
23966 // Skip 'zext' or 'trunc' node.
23967 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23968 Op.getOpcode() == ISD::TRUNCATE)
23969 Op = Op.getOperand(0);
23970 // A special case for rdrand/rdseed, where 0 is set if false cond is
23972 if ((Op.getOpcode() != X86ISD::RDRAND &&
23973 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23976 // Quit if false value is not the constant 0 or 1.
23977 bool FValIsFalse = true;
23978 if (FVal && FVal->getZExtValue() != 0) {
23979 if (FVal->getZExtValue() != 1)
23981 // If FVal is 1, opposite cond is needed.
23982 needOppositeCond = !needOppositeCond;
23983 FValIsFalse = false;
23985 // Quit if TVal is not the constant opposite of FVal.
23986 if (FValIsFalse && TVal->getZExtValue() != 1)
23988 if (!FValIsFalse && TVal->getZExtValue() != 0)
23990 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23991 if (needOppositeCond)
23992 CC = X86::GetOppositeBranchCondition(CC);
23993 return SetCC.getOperand(3);
24000 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
24002 /// (X86or (X86setcc) (X86setcc))
24003 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
24004 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24005 X86::CondCode &CC1, SDValue &Flags,
24007 if (Cond->getOpcode() == X86ISD::CMP) {
24008 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
24009 if (!CondOp1C || !CondOp1C->isNullValue())
24012 Cond = Cond->getOperand(0);
24017 SDValue SetCC0, SetCC1;
24018 switch (Cond->getOpcode()) {
24019 default: return false;
24026 SetCC0 = Cond->getOperand(0);
24027 SetCC1 = Cond->getOperand(1);
24031 // Make sure we have SETCC nodes, using the same flags value.
24032 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24033 SetCC1.getOpcode() != X86ISD::SETCC ||
24034 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24037 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24038 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24039 Flags = SetCC0->getOperand(1);
24043 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24044 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24045 TargetLowering::DAGCombinerInfo &DCI,
24046 const X86Subtarget *Subtarget) {
24049 // If the flag operand isn't dead, don't touch this CMOV.
24050 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24053 SDValue FalseOp = N->getOperand(0);
24054 SDValue TrueOp = N->getOperand(1);
24055 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24056 SDValue Cond = N->getOperand(3);
24058 if (CC == X86::COND_E || CC == X86::COND_NE) {
24059 switch (Cond.getOpcode()) {
24063 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24064 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24065 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24071 Flags = checkBoolTestSetCCCombine(Cond, CC);
24072 if (Flags.getNode() &&
24073 // Extra check as FCMOV only supports a subset of X86 cond.
24074 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24075 SDValue Ops[] = { FalseOp, TrueOp,
24076 DAG.getConstant(CC, DL, MVT::i8), Flags };
24077 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24080 // If this is a select between two integer constants, try to do some
24081 // optimizations. Note that the operands are ordered the opposite of SELECT
24083 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24084 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24085 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24086 // larger than FalseC (the false value).
24087 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24088 CC = X86::GetOppositeBranchCondition(CC);
24089 std::swap(TrueC, FalseC);
24090 std::swap(TrueOp, FalseOp);
24093 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24094 // This is efficient for any integer data type (including i8/i16) and
24096 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24097 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24098 DAG.getConstant(CC, DL, MVT::i8), Cond);
24100 // Zero extend the condition if needed.
24101 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24103 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24104 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24105 DAG.getConstant(ShAmt, DL, MVT::i8));
24106 if (N->getNumValues() == 2) // Dead flag value?
24107 return DCI.CombineTo(N, Cond, SDValue());
24111 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24112 // for any integer data type, including i8/i16.
24113 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24114 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24115 DAG.getConstant(CC, DL, MVT::i8), Cond);
24117 // Zero extend the condition if needed.
24118 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24119 FalseC->getValueType(0), Cond);
24120 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24121 SDValue(FalseC, 0));
24123 if (N->getNumValues() == 2) // Dead flag value?
24124 return DCI.CombineTo(N, Cond, SDValue());
24128 // Optimize cases that will turn into an LEA instruction. This requires
24129 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24130 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24131 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24132 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24134 bool isFastMultiplier = false;
24136 switch ((unsigned char)Diff) {
24138 case 1: // result = add base, cond
24139 case 2: // result = lea base( , cond*2)
24140 case 3: // result = lea base(cond, cond*2)
24141 case 4: // result = lea base( , cond*4)
24142 case 5: // result = lea base(cond, cond*4)
24143 case 8: // result = lea base( , cond*8)
24144 case 9: // result = lea base(cond, cond*8)
24145 isFastMultiplier = true;
24150 if (isFastMultiplier) {
24151 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24152 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24153 DAG.getConstant(CC, DL, MVT::i8), Cond);
24154 // Zero extend the condition if needed.
24155 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24157 // Scale the condition by the difference.
24159 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24160 DAG.getConstant(Diff, DL, Cond.getValueType()));
24162 // Add the base if non-zero.
24163 if (FalseC->getAPIntValue() != 0)
24164 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24165 SDValue(FalseC, 0));
24166 if (N->getNumValues() == 2) // Dead flag value?
24167 return DCI.CombineTo(N, Cond, SDValue());
24174 // Handle these cases:
24175 // (select (x != c), e, c) -> select (x != c), e, x),
24176 // (select (x == c), c, e) -> select (x == c), x, e)
24177 // where the c is an integer constant, and the "select" is the combination
24178 // of CMOV and CMP.
24180 // The rationale for this change is that the conditional-move from a constant
24181 // needs two instructions, however, conditional-move from a register needs
24182 // only one instruction.
24184 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24185 // some instruction-combining opportunities. This opt needs to be
24186 // postponed as late as possible.
24188 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24189 // the DCI.xxxx conditions are provided to postpone the optimization as
24190 // late as possible.
24192 ConstantSDNode *CmpAgainst = nullptr;
24193 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24194 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24195 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24197 if (CC == X86::COND_NE &&
24198 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24199 CC = X86::GetOppositeBranchCondition(CC);
24200 std::swap(TrueOp, FalseOp);
24203 if (CC == X86::COND_E &&
24204 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24205 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24206 DAG.getConstant(CC, DL, MVT::i8), Cond };
24207 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24212 // Fold and/or of setcc's to double CMOV:
24213 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24214 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24216 // This combine lets us generate:
24217 // cmovcc1 (jcc1 if we don't have CMOV)
24223 // cmovne (jne if we don't have CMOV)
24224 // When we can't use the CMOV instruction, it might increase branch
24226 // When we can use CMOV, or when there is no mispredict, this improves
24227 // throughput and reduces register pressure.
24229 if (CC == X86::COND_NE) {
24231 X86::CondCode CC0, CC1;
24233 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24235 std::swap(FalseOp, TrueOp);
24236 CC0 = X86::GetOppositeBranchCondition(CC0);
24237 CC1 = X86::GetOppositeBranchCondition(CC1);
24240 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24242 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24243 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24244 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24245 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24253 /// PerformMulCombine - Optimize a single multiply with constant into two
24254 /// in order to implement it with two cheaper instructions, e.g.
24255 /// LEA + SHL, LEA + LEA.
24256 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24257 TargetLowering::DAGCombinerInfo &DCI) {
24258 // An imul is usually smaller than the alternative sequence.
24259 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24262 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24265 EVT VT = N->getValueType(0);
24266 if (VT != MVT::i64 && VT != MVT::i32)
24269 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24272 uint64_t MulAmt = C->getZExtValue();
24273 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24276 uint64_t MulAmt1 = 0;
24277 uint64_t MulAmt2 = 0;
24278 if ((MulAmt % 9) == 0) {
24280 MulAmt2 = MulAmt / 9;
24281 } else if ((MulAmt % 5) == 0) {
24283 MulAmt2 = MulAmt / 5;
24284 } else if ((MulAmt % 3) == 0) {
24286 MulAmt2 = MulAmt / 3;
24289 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24292 if (isPowerOf2_64(MulAmt2) &&
24293 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24294 // If second multiplifer is pow2, issue it first. We want the multiply by
24295 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24297 std::swap(MulAmt1, MulAmt2);
24300 if (isPowerOf2_64(MulAmt1))
24301 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24302 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24304 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24305 DAG.getConstant(MulAmt1, DL, VT));
24307 if (isPowerOf2_64(MulAmt2))
24308 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24309 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24311 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24312 DAG.getConstant(MulAmt2, DL, VT));
24314 // Do not add new nodes to DAG combiner worklist.
24315 DCI.CombineTo(N, NewMul, false);
24320 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24321 SDValue N0 = N->getOperand(0);
24322 SDValue N1 = N->getOperand(1);
24323 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24324 EVT VT = N0.getValueType();
24326 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24327 // since the result of setcc_c is all zero's or all ones.
24328 if (VT.isInteger() && !VT.isVector() &&
24329 N1C && N0.getOpcode() == ISD::AND &&
24330 N0.getOperand(1).getOpcode() == ISD::Constant) {
24331 SDValue N00 = N0.getOperand(0);
24332 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24333 APInt ShAmt = N1C->getAPIntValue();
24334 Mask = Mask.shl(ShAmt);
24335 bool MaskOK = false;
24336 // We can handle cases concerning bit-widening nodes containing setcc_c if
24337 // we carefully interrogate the mask to make sure we are semantics
24339 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24340 // of the underlying setcc_c operation if the setcc_c was zero extended.
24341 // Consider the following example:
24342 // zext(setcc_c) -> i32 0x0000FFFF
24343 // c1 -> i32 0x0000FFFF
24344 // c2 -> i32 0x00000001
24345 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24346 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24347 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24349 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24350 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24352 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24353 N00.getOpcode() == ISD::ANY_EXTEND) &&
24354 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24355 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24357 if (MaskOK && Mask != 0) {
24359 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24363 // Hardware support for vector shifts is sparse which makes us scalarize the
24364 // vector operations in many cases. Also, on sandybridge ADD is faster than
24366 // (shl V, 1) -> add V,V
24367 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24368 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24369 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24370 // We shift all of the values by one. In many cases we do not have
24371 // hardware support for this operation. This is better expressed as an ADD
24373 if (N1SplatC->getAPIntValue() == 1)
24374 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24380 /// \brief Returns a vector of 0s if the node in input is a vector logical
24381 /// shift by a constant amount which is known to be bigger than or equal
24382 /// to the vector element size in bits.
24383 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24384 const X86Subtarget *Subtarget) {
24385 EVT VT = N->getValueType(0);
24387 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24388 (!Subtarget->hasInt256() ||
24389 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24392 SDValue Amt = N->getOperand(1);
24394 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24395 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24396 APInt ShiftAmt = AmtSplat->getAPIntValue();
24397 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24399 // SSE2/AVX2 logical shifts always return a vector of 0s
24400 // if the shift amount is bigger than or equal to
24401 // the element size. The constant shift amount will be
24402 // encoded as a 8-bit immediate.
24403 if (ShiftAmt.trunc(8).uge(MaxAmount))
24404 return getZeroVector(VT, Subtarget, DAG, DL);
24410 /// PerformShiftCombine - Combine shifts.
24411 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24412 TargetLowering::DAGCombinerInfo &DCI,
24413 const X86Subtarget *Subtarget) {
24414 if (N->getOpcode() == ISD::SHL)
24415 if (SDValue V = PerformSHLCombine(N, DAG))
24418 // Try to fold this logical shift into a zero vector.
24419 if (N->getOpcode() != ISD::SRA)
24420 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24426 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24427 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24428 // and friends. Likewise for OR -> CMPNEQSS.
24429 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24430 TargetLowering::DAGCombinerInfo &DCI,
24431 const X86Subtarget *Subtarget) {
24434 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24435 // we're requiring SSE2 for both.
24436 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24437 SDValue N0 = N->getOperand(0);
24438 SDValue N1 = N->getOperand(1);
24439 SDValue CMP0 = N0->getOperand(1);
24440 SDValue CMP1 = N1->getOperand(1);
24443 // The SETCCs should both refer to the same CMP.
24444 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24447 SDValue CMP00 = CMP0->getOperand(0);
24448 SDValue CMP01 = CMP0->getOperand(1);
24449 EVT VT = CMP00.getValueType();
24451 if (VT == MVT::f32 || VT == MVT::f64) {
24452 bool ExpectingFlags = false;
24453 // Check for any users that want flags:
24454 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24455 !ExpectingFlags && UI != UE; ++UI)
24456 switch (UI->getOpcode()) {
24461 ExpectingFlags = true;
24463 case ISD::CopyToReg:
24464 case ISD::SIGN_EXTEND:
24465 case ISD::ZERO_EXTEND:
24466 case ISD::ANY_EXTEND:
24470 if (!ExpectingFlags) {
24471 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24472 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24474 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24475 X86::CondCode tmp = cc0;
24480 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24481 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24482 // FIXME: need symbolic constants for these magic numbers.
24483 // See X86ATTInstPrinter.cpp:printSSECC().
24484 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24485 if (Subtarget->hasAVX512()) {
24486 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24488 DAG.getConstant(x86cc, DL, MVT::i8));
24489 if (N->getValueType(0) != MVT::i1)
24490 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24494 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24495 CMP00.getValueType(), CMP00, CMP01,
24496 DAG.getConstant(x86cc, DL,
24499 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24500 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24502 if (is64BitFP && !Subtarget->is64Bit()) {
24503 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24504 // 64-bit integer, since that's not a legal type. Since
24505 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24506 // bits, but can do this little dance to extract the lowest 32 bits
24507 // and work with those going forward.
24508 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24510 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24511 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24512 Vector32, DAG.getIntPtrConstant(0, DL));
24516 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24517 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24518 DAG.getConstant(1, DL, IntVT));
24519 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24521 return OneBitOfTruth;
24529 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24530 /// so it can be folded inside ANDNP.
24531 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24532 EVT VT = N->getValueType(0);
24534 // Match direct AllOnes for 128 and 256-bit vectors
24535 if (ISD::isBuildVectorAllOnes(N))
24538 // Look through a bit convert.
24539 if (N->getOpcode() == ISD::BITCAST)
24540 N = N->getOperand(0).getNode();
24542 // Sometimes the operand may come from a insert_subvector building a 256-bit
24544 if (VT.is256BitVector() &&
24545 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24546 SDValue V1 = N->getOperand(0);
24547 SDValue V2 = N->getOperand(1);
24549 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24550 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24551 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24552 ISD::isBuildVectorAllOnes(V2.getNode()))
24559 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24560 // register. In most cases we actually compare or select YMM-sized registers
24561 // and mixing the two types creates horrible code. This method optimizes
24562 // some of the transition sequences.
24563 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24564 TargetLowering::DAGCombinerInfo &DCI,
24565 const X86Subtarget *Subtarget) {
24566 EVT VT = N->getValueType(0);
24567 if (!VT.is256BitVector())
24570 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24571 N->getOpcode() == ISD::ZERO_EXTEND ||
24572 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24574 SDValue Narrow = N->getOperand(0);
24575 EVT NarrowVT = Narrow->getValueType(0);
24576 if (!NarrowVT.is128BitVector())
24579 if (Narrow->getOpcode() != ISD::XOR &&
24580 Narrow->getOpcode() != ISD::AND &&
24581 Narrow->getOpcode() != ISD::OR)
24584 SDValue N0 = Narrow->getOperand(0);
24585 SDValue N1 = Narrow->getOperand(1);
24588 // The Left side has to be a trunc.
24589 if (N0.getOpcode() != ISD::TRUNCATE)
24592 // The type of the truncated inputs.
24593 EVT WideVT = N0->getOperand(0)->getValueType(0);
24597 // The right side has to be a 'trunc' or a constant vector.
24598 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24599 ConstantSDNode *RHSConstSplat = nullptr;
24600 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24601 RHSConstSplat = RHSBV->getConstantSplatNode();
24602 if (!RHSTrunc && !RHSConstSplat)
24605 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24607 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24610 // Set N0 and N1 to hold the inputs to the new wide operation.
24611 N0 = N0->getOperand(0);
24612 if (RHSConstSplat) {
24613 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24614 SDValue(RHSConstSplat, 0));
24615 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24616 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24617 } else if (RHSTrunc) {
24618 N1 = N1->getOperand(0);
24621 // Generate the wide operation.
24622 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24623 unsigned Opcode = N->getOpcode();
24625 case ISD::ANY_EXTEND:
24627 case ISD::ZERO_EXTEND: {
24628 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24629 APInt Mask = APInt::getAllOnesValue(InBits);
24630 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24631 return DAG.getNode(ISD::AND, DL, VT,
24632 Op, DAG.getConstant(Mask, DL, VT));
24634 case ISD::SIGN_EXTEND:
24635 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24636 Op, DAG.getValueType(NarrowVT));
24638 llvm_unreachable("Unexpected opcode");
24642 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24643 TargetLowering::DAGCombinerInfo &DCI,
24644 const X86Subtarget *Subtarget) {
24645 SDValue N0 = N->getOperand(0);
24646 SDValue N1 = N->getOperand(1);
24649 // A vector zext_in_reg may be represented as a shuffle,
24650 // feeding into a bitcast (this represents anyext) feeding into
24651 // an and with a mask.
24652 // We'd like to try to combine that into a shuffle with zero
24653 // plus a bitcast, removing the and.
24654 if (N0.getOpcode() != ISD::BITCAST ||
24655 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24658 // The other side of the AND should be a splat of 2^C, where C
24659 // is the number of bits in the source type.
24660 if (N1.getOpcode() == ISD::BITCAST)
24661 N1 = N1.getOperand(0);
24662 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24664 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24666 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24667 EVT SrcType = Shuffle->getValueType(0);
24669 // We expect a single-source shuffle
24670 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24673 unsigned SrcSize = SrcType.getScalarSizeInBits();
24675 APInt SplatValue, SplatUndef;
24676 unsigned SplatBitSize;
24678 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24679 SplatBitSize, HasAnyUndefs))
24682 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24683 // Make sure the splat matches the mask we expect
24684 if (SplatBitSize > ResSize ||
24685 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24688 // Make sure the input and output size make sense
24689 if (SrcSize >= ResSize || ResSize % SrcSize)
24692 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24693 // The number of u's between each two values depends on the ratio between
24694 // the source and dest type.
24695 unsigned ZextRatio = ResSize / SrcSize;
24696 bool IsZext = true;
24697 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24698 if (i % ZextRatio) {
24699 if (Shuffle->getMaskElt(i) > 0) {
24705 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24706 // Expected element number
24716 // Ok, perform the transformation - replace the shuffle with
24717 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24718 // (instead of undef) where the k elements come from the zero vector.
24719 SmallVector<int, 8> Mask;
24720 unsigned NumElems = SrcType.getVectorNumElements();
24721 for (unsigned i = 0; i < NumElems; ++i)
24723 Mask.push_back(NumElems);
24725 Mask.push_back(i / ZextRatio);
24727 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24728 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24729 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24732 /// If both input operands of a logic op are being cast from floating point
24733 /// types, try to convert this into a floating point logic node to avoid
24734 /// unnecessary moves from SSE to integer registers.
24735 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
24736 const X86Subtarget *Subtarget) {
24737 unsigned FPOpcode = ISD::DELETED_NODE;
24738 if (N->getOpcode() == ISD::AND)
24739 FPOpcode = X86ISD::FAND;
24740 else if (N->getOpcode() == ISD::OR)
24741 FPOpcode = X86ISD::FOR;
24742 else if (N->getOpcode() == ISD::XOR)
24743 FPOpcode = X86ISD::FXOR;
24745 assert(FPOpcode != ISD::DELETED_NODE &&
24746 "Unexpected input node for FP logic conversion");
24748 EVT VT = N->getValueType(0);
24749 SDValue N0 = N->getOperand(0);
24750 SDValue N1 = N->getOperand(1);
24752 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
24753 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
24754 (Subtarget->hasSSE2() && VT == MVT::i64))) {
24755 SDValue N00 = N0.getOperand(0);
24756 SDValue N10 = N1.getOperand(0);
24757 EVT N00Type = N00.getValueType();
24758 EVT N10Type = N10.getValueType();
24759 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
24760 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
24761 return DAG.getBitcast(VT, FPLogic);
24767 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24768 TargetLowering::DAGCombinerInfo &DCI,
24769 const X86Subtarget *Subtarget) {
24770 if (DCI.isBeforeLegalizeOps())
24773 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
24776 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24779 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24782 EVT VT = N->getValueType(0);
24783 SDValue N0 = N->getOperand(0);
24784 SDValue N1 = N->getOperand(1);
24787 // Create BEXTR instructions
24788 // BEXTR is ((X >> imm) & (2**size-1))
24789 if (VT == MVT::i32 || VT == MVT::i64) {
24790 // Check for BEXTR.
24791 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24792 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24793 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24794 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24795 if (MaskNode && ShiftNode) {
24796 uint64_t Mask = MaskNode->getZExtValue();
24797 uint64_t Shift = ShiftNode->getZExtValue();
24798 if (isMask_64(Mask)) {
24799 uint64_t MaskSize = countPopulation(Mask);
24800 if (Shift + MaskSize <= VT.getSizeInBits())
24801 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24802 DAG.getConstant(Shift | (MaskSize << 8), DL,
24811 // Want to form ANDNP nodes:
24812 // 1) In the hopes of then easily combining them with OR and AND nodes
24813 // to form PBLEND/PSIGN.
24814 // 2) To match ANDN packed intrinsics
24815 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24818 // Check LHS for vnot
24819 if (N0.getOpcode() == ISD::XOR &&
24820 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24821 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24822 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24824 // Check RHS for vnot
24825 if (N1.getOpcode() == ISD::XOR &&
24826 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24827 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24828 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24833 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24834 TargetLowering::DAGCombinerInfo &DCI,
24835 const X86Subtarget *Subtarget) {
24836 if (DCI.isBeforeLegalizeOps())
24839 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24842 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24845 SDValue N0 = N->getOperand(0);
24846 SDValue N1 = N->getOperand(1);
24847 EVT VT = N->getValueType(0);
24849 // look for psign/blend
24850 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24851 if (!Subtarget->hasSSSE3() ||
24852 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24855 // Canonicalize pandn to RHS
24856 if (N0.getOpcode() == X86ISD::ANDNP)
24858 // or (and (m, y), (pandn m, x))
24859 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24860 SDValue Mask = N1.getOperand(0);
24861 SDValue X = N1.getOperand(1);
24863 if (N0.getOperand(0) == Mask)
24864 Y = N0.getOperand(1);
24865 if (N0.getOperand(1) == Mask)
24866 Y = N0.getOperand(0);
24868 // Check to see if the mask appeared in both the AND and ANDNP and
24872 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24873 // Look through mask bitcast.
24874 if (Mask.getOpcode() == ISD::BITCAST)
24875 Mask = Mask.getOperand(0);
24876 if (X.getOpcode() == ISD::BITCAST)
24877 X = X.getOperand(0);
24878 if (Y.getOpcode() == ISD::BITCAST)
24879 Y = Y.getOperand(0);
24881 EVT MaskVT = Mask.getValueType();
24883 // Validate that the Mask operand is a vector sra node.
24884 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24885 // there is no psrai.b
24886 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24887 unsigned SraAmt = ~0;
24888 if (Mask.getOpcode() == ISD::SRA) {
24889 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24890 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24891 SraAmt = AmtConst->getZExtValue();
24892 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24893 SDValue SraC = Mask.getOperand(1);
24894 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24896 if ((SraAmt + 1) != EltBits)
24901 // Now we know we at least have a plendvb with the mask val. See if
24902 // we can form a psignb/w/d.
24903 // psign = x.type == y.type == mask.type && y = sub(0, x);
24904 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24905 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24906 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24907 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24908 "Unsupported VT for PSIGN");
24909 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24910 return DAG.getBitcast(VT, Mask);
24912 // PBLENDVB only available on SSE 4.1
24913 if (!Subtarget->hasSSE41())
24916 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24918 X = DAG.getBitcast(BlendVT, X);
24919 Y = DAG.getBitcast(BlendVT, Y);
24920 Mask = DAG.getBitcast(BlendVT, Mask);
24921 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24922 return DAG.getBitcast(VT, Mask);
24926 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24929 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24930 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
24932 // SHLD/SHRD instructions have lower register pressure, but on some
24933 // platforms they have higher latency than the equivalent
24934 // series of shifts/or that would otherwise be generated.
24935 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24936 // have higher latencies and we are not optimizing for size.
24937 if (!OptForSize && Subtarget->isSHLDSlow())
24940 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24942 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24944 if (!N0.hasOneUse() || !N1.hasOneUse())
24947 SDValue ShAmt0 = N0.getOperand(1);
24948 if (ShAmt0.getValueType() != MVT::i8)
24950 SDValue ShAmt1 = N1.getOperand(1);
24951 if (ShAmt1.getValueType() != MVT::i8)
24953 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24954 ShAmt0 = ShAmt0.getOperand(0);
24955 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24956 ShAmt1 = ShAmt1.getOperand(0);
24959 unsigned Opc = X86ISD::SHLD;
24960 SDValue Op0 = N0.getOperand(0);
24961 SDValue Op1 = N1.getOperand(0);
24962 if (ShAmt0.getOpcode() == ISD::SUB) {
24963 Opc = X86ISD::SHRD;
24964 std::swap(Op0, Op1);
24965 std::swap(ShAmt0, ShAmt1);
24968 unsigned Bits = VT.getSizeInBits();
24969 if (ShAmt1.getOpcode() == ISD::SUB) {
24970 SDValue Sum = ShAmt1.getOperand(0);
24971 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24972 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24973 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24974 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24975 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24976 return DAG.getNode(Opc, DL, VT,
24978 DAG.getNode(ISD::TRUNCATE, DL,
24981 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24982 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24984 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24985 return DAG.getNode(Opc, DL, VT,
24986 N0.getOperand(0), N1.getOperand(0),
24987 DAG.getNode(ISD::TRUNCATE, DL,
24994 // Generate NEG and CMOV for integer abs.
24995 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24996 EVT VT = N->getValueType(0);
24998 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24999 // 8-bit integer abs to NEG and CMOV.
25000 if (VT.isInteger() && VT.getSizeInBits() == 8)
25003 SDValue N0 = N->getOperand(0);
25004 SDValue N1 = N->getOperand(1);
25007 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
25008 // and change it to SUB and CMOV.
25009 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25010 N0.getOpcode() == ISD::ADD &&
25011 N0.getOperand(1) == N1 &&
25012 N1.getOpcode() == ISD::SRA &&
25013 N1.getOperand(0) == N0.getOperand(0))
25014 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25015 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25016 // Generate SUB & CMOV.
25017 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25018 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25020 SDValue Ops[] = { N0.getOperand(0), Neg,
25021 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25022 SDValue(Neg.getNode(), 1) };
25023 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25028 // Try to turn tests against the signbit in the form of:
25029 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25032 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25033 // This is only worth doing if the output type is i8.
25034 if (N->getValueType(0) != MVT::i8)
25037 SDValue N0 = N->getOperand(0);
25038 SDValue N1 = N->getOperand(1);
25040 // We should be performing an xor against a truncated shift.
25041 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25044 // Make sure we are performing an xor against one.
25045 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
25048 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25049 SDValue Shift = N0.getOperand(0);
25050 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25053 // Make sure we are truncating from one of i16, i32 or i64.
25054 EVT ShiftTy = Shift.getValueType();
25055 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25058 // Make sure the shift amount extracts the sign bit.
25059 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25060 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25063 // Create a greater-than comparison against -1.
25064 // N.B. Using SETGE against 0 works but we want a canonical looking
25065 // comparison, using SETGT matches up with what TranslateX86CC.
25067 SDValue ShiftOp = Shift.getOperand(0);
25068 EVT ShiftOpTy = ShiftOp.getValueType();
25069 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
25070 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
25074 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25075 TargetLowering::DAGCombinerInfo &DCI,
25076 const X86Subtarget *Subtarget) {
25077 if (DCI.isBeforeLegalizeOps())
25080 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
25083 if (Subtarget->hasCMov())
25084 if (SDValue RV = performIntegerAbsCombine(N, DAG))
25087 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25093 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
25094 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
25095 TargetLowering::DAGCombinerInfo &DCI,
25096 const X86Subtarget *Subtarget) {
25097 LoadSDNode *Ld = cast<LoadSDNode>(N);
25098 EVT RegVT = Ld->getValueType(0);
25099 EVT MemVT = Ld->getMemoryVT();
25101 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25103 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
25104 // into two 16-byte operations.
25105 ISD::LoadExtType Ext = Ld->getExtensionType();
25107 unsigned AddressSpace = Ld->getAddressSpace();
25108 unsigned Alignment = Ld->getAlignment();
25109 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
25110 Ext == ISD::NON_EXTLOAD &&
25111 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25112 AddressSpace, Alignment, &Fast) && !Fast) {
25113 unsigned NumElems = RegVT.getVectorNumElements();
25117 SDValue Ptr = Ld->getBasePtr();
25118 SDValue Increment =
25119 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25121 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
25123 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25124 Ld->getPointerInfo(), Ld->isVolatile(),
25125 Ld->isNonTemporal(), Ld->isInvariant(),
25127 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25128 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25129 Ld->getPointerInfo(), Ld->isVolatile(),
25130 Ld->isNonTemporal(), Ld->isInvariant(),
25131 std::min(16U, Alignment));
25132 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
25134 Load2.getValue(1));
25136 SDValue NewVec = DAG.getUNDEF(RegVT);
25137 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
25138 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
25139 return DCI.CombineTo(N, NewVec, TF, true);
25145 /// PerformMLOADCombine - Resolve extending loads
25146 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
25147 TargetLowering::DAGCombinerInfo &DCI,
25148 const X86Subtarget *Subtarget) {
25149 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
25150 if (Mld->getExtensionType() != ISD::SEXTLOAD)
25153 EVT VT = Mld->getValueType(0);
25154 unsigned NumElems = VT.getVectorNumElements();
25155 EVT LdVT = Mld->getMemoryVT();
25158 assert(LdVT != VT && "Cannot extend to the same type");
25159 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
25160 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
25161 // From, To sizes and ElemCount must be pow of two
25162 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25163 "Unexpected size for extending masked load");
25165 unsigned SizeRatio = ToSz / FromSz;
25166 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
25168 // Create a type on which we perform the shuffle
25169 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25170 LdVT.getScalarType(), NumElems*SizeRatio);
25171 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25173 // Convert Src0 value
25174 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
25175 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
25176 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25177 for (unsigned i = 0; i != NumElems; ++i)
25178 ShuffleVec[i] = i * SizeRatio;
25180 // Can't shuffle using an illegal type.
25181 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25182 "WideVecVT should be legal");
25183 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
25184 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
25186 // Prepare the new mask
25188 SDValue Mask = Mld->getMask();
25189 if (Mask.getValueType() == VT) {
25190 // Mask and original value have the same type
25191 NewMask = DAG.getBitcast(WideVecVT, Mask);
25192 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25193 for (unsigned i = 0; i != NumElems; ++i)
25194 ShuffleVec[i] = i * SizeRatio;
25195 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25196 ShuffleVec[i] = NumElems*SizeRatio;
25197 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25198 DAG.getConstant(0, dl, WideVecVT),
25202 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25203 unsigned WidenNumElts = NumElems*SizeRatio;
25204 unsigned MaskNumElts = VT.getVectorNumElements();
25205 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25208 unsigned NumConcat = WidenNumElts / MaskNumElts;
25209 SmallVector<SDValue, 16> Ops(NumConcat);
25210 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25212 for (unsigned i = 1; i != NumConcat; ++i)
25215 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25218 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
25219 Mld->getBasePtr(), NewMask, WideSrc0,
25220 Mld->getMemoryVT(), Mld->getMemOperand(),
25222 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
25223 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
25225 /// PerformMSTORECombine - Resolve truncating stores
25226 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
25227 const X86Subtarget *Subtarget) {
25228 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
25229 if (!Mst->isTruncatingStore())
25232 EVT VT = Mst->getValue().getValueType();
25233 unsigned NumElems = VT.getVectorNumElements();
25234 EVT StVT = Mst->getMemoryVT();
25237 assert(StVT != VT && "Cannot truncate to the same type");
25238 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25239 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25241 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25243 // The truncating store is legal in some cases. For example
25244 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25245 // are designated for truncate store.
25246 // In this case we don't need any further transformations.
25247 if (TLI.isTruncStoreLegal(VT, StVT))
25250 // From, To sizes and ElemCount must be pow of two
25251 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25252 "Unexpected size for truncating masked store");
25253 // We are going to use the original vector elt for storing.
25254 // Accumulated smaller vector elements must be a multiple of the store size.
25255 assert (((NumElems * FromSz) % ToSz) == 0 &&
25256 "Unexpected ratio for truncating masked store");
25258 unsigned SizeRatio = FromSz / ToSz;
25259 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25261 // Create a type on which we perform the shuffle
25262 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25263 StVT.getScalarType(), NumElems*SizeRatio);
25265 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25267 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25268 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25269 for (unsigned i = 0; i != NumElems; ++i)
25270 ShuffleVec[i] = i * SizeRatio;
25272 // Can't shuffle using an illegal type.
25273 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25274 "WideVecVT should be legal");
25276 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25277 DAG.getUNDEF(WideVecVT),
25281 SDValue Mask = Mst->getMask();
25282 if (Mask.getValueType() == VT) {
25283 // Mask and original value have the same type
25284 NewMask = DAG.getBitcast(WideVecVT, Mask);
25285 for (unsigned i = 0; i != NumElems; ++i)
25286 ShuffleVec[i] = i * SizeRatio;
25287 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25288 ShuffleVec[i] = NumElems*SizeRatio;
25289 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25290 DAG.getConstant(0, dl, WideVecVT),
25294 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25295 unsigned WidenNumElts = NumElems*SizeRatio;
25296 unsigned MaskNumElts = VT.getVectorNumElements();
25297 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25300 unsigned NumConcat = WidenNumElts / MaskNumElts;
25301 SmallVector<SDValue, 16> Ops(NumConcat);
25302 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25304 for (unsigned i = 1; i != NumConcat; ++i)
25307 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25310 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
25311 NewMask, StVT, Mst->getMemOperand(), false);
25313 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25314 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25315 const X86Subtarget *Subtarget) {
25316 StoreSDNode *St = cast<StoreSDNode>(N);
25317 EVT VT = St->getValue().getValueType();
25318 EVT StVT = St->getMemoryVT();
25320 SDValue StoredVal = St->getOperand(1);
25321 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25323 // If we are saving a concatenation of two XMM registers and 32-byte stores
25324 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25326 unsigned AddressSpace = St->getAddressSpace();
25327 unsigned Alignment = St->getAlignment();
25328 if (VT.is256BitVector() && StVT == VT &&
25329 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25330 AddressSpace, Alignment, &Fast) && !Fast) {
25331 unsigned NumElems = VT.getVectorNumElements();
25335 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25336 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25339 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25340 SDValue Ptr0 = St->getBasePtr();
25341 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25343 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25344 St->getPointerInfo(), St->isVolatile(),
25345 St->isNonTemporal(), Alignment);
25346 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25347 St->getPointerInfo(), St->isVolatile(),
25348 St->isNonTemporal(),
25349 std::min(16U, Alignment));
25350 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25353 // Optimize trunc store (of multiple scalars) to shuffle and store.
25354 // First, pack all of the elements in one place. Next, store to memory
25355 // in fewer chunks.
25356 if (St->isTruncatingStore() && VT.isVector()) {
25357 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25358 unsigned NumElems = VT.getVectorNumElements();
25359 assert(StVT != VT && "Cannot truncate to the same type");
25360 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25361 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25363 // The truncating store is legal in some cases. For example
25364 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25365 // are designated for truncate store.
25366 // In this case we don't need any further transformations.
25367 if (TLI.isTruncStoreLegal(VT, StVT))
25370 // From, To sizes and ElemCount must be pow of two
25371 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25372 // We are going to use the original vector elt for storing.
25373 // Accumulated smaller vector elements must be a multiple of the store size.
25374 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25376 unsigned SizeRatio = FromSz / ToSz;
25378 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25380 // Create a type on which we perform the shuffle
25381 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25382 StVT.getScalarType(), NumElems*SizeRatio);
25384 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25386 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25387 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25388 for (unsigned i = 0; i != NumElems; ++i)
25389 ShuffleVec[i] = i * SizeRatio;
25391 // Can't shuffle using an illegal type.
25392 if (!TLI.isTypeLegal(WideVecVT))
25395 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25396 DAG.getUNDEF(WideVecVT),
25398 // At this point all of the data is stored at the bottom of the
25399 // register. We now need to save it to mem.
25401 // Find the largest store unit
25402 MVT StoreType = MVT::i8;
25403 for (MVT Tp : MVT::integer_valuetypes()) {
25404 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25408 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25409 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25410 (64 <= NumElems * ToSz))
25411 StoreType = MVT::f64;
25413 // Bitcast the original vector into a vector of store-size units
25414 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25415 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25416 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25417 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25418 SmallVector<SDValue, 8> Chains;
25419 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25420 TLI.getPointerTy(DAG.getDataLayout()));
25421 SDValue Ptr = St->getBasePtr();
25423 // Perform one or more big stores into memory.
25424 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25425 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25426 StoreType, ShuffWide,
25427 DAG.getIntPtrConstant(i, dl));
25428 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25429 St->getPointerInfo(), St->isVolatile(),
25430 St->isNonTemporal(), St->getAlignment());
25431 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25432 Chains.push_back(Ch);
25435 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25438 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25439 // the FP state in cases where an emms may be missing.
25440 // A preferable solution to the general problem is to figure out the right
25441 // places to insert EMMS. This qualifies as a quick hack.
25443 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25444 if (VT.getSizeInBits() != 64)
25447 const Function *F = DAG.getMachineFunction().getFunction();
25448 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25450 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25451 if ((VT.isVector() ||
25452 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25453 isa<LoadSDNode>(St->getValue()) &&
25454 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25455 St->getChain().hasOneUse() && !St->isVolatile()) {
25456 SDNode* LdVal = St->getValue().getNode();
25457 LoadSDNode *Ld = nullptr;
25458 int TokenFactorIndex = -1;
25459 SmallVector<SDValue, 8> Ops;
25460 SDNode* ChainVal = St->getChain().getNode();
25461 // Must be a store of a load. We currently handle two cases: the load
25462 // is a direct child, and it's under an intervening TokenFactor. It is
25463 // possible to dig deeper under nested TokenFactors.
25464 if (ChainVal == LdVal)
25465 Ld = cast<LoadSDNode>(St->getChain());
25466 else if (St->getValue().hasOneUse() &&
25467 ChainVal->getOpcode() == ISD::TokenFactor) {
25468 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25469 if (ChainVal->getOperand(i).getNode() == LdVal) {
25470 TokenFactorIndex = i;
25471 Ld = cast<LoadSDNode>(St->getValue());
25473 Ops.push_back(ChainVal->getOperand(i));
25477 if (!Ld || !ISD::isNormalLoad(Ld))
25480 // If this is not the MMX case, i.e. we are just turning i64 load/store
25481 // into f64 load/store, avoid the transformation if there are multiple
25482 // uses of the loaded value.
25483 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25488 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25489 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25491 if (Subtarget->is64Bit() || F64IsLegal) {
25492 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25493 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25494 Ld->getPointerInfo(), Ld->isVolatile(),
25495 Ld->isNonTemporal(), Ld->isInvariant(),
25496 Ld->getAlignment());
25497 SDValue NewChain = NewLd.getValue(1);
25498 if (TokenFactorIndex != -1) {
25499 Ops.push_back(NewChain);
25500 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25502 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25503 St->getPointerInfo(),
25504 St->isVolatile(), St->isNonTemporal(),
25505 St->getAlignment());
25508 // Otherwise, lower to two pairs of 32-bit loads / stores.
25509 SDValue LoAddr = Ld->getBasePtr();
25510 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25511 DAG.getConstant(4, LdDL, MVT::i32));
25513 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25514 Ld->getPointerInfo(),
25515 Ld->isVolatile(), Ld->isNonTemporal(),
25516 Ld->isInvariant(), Ld->getAlignment());
25517 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25518 Ld->getPointerInfo().getWithOffset(4),
25519 Ld->isVolatile(), Ld->isNonTemporal(),
25521 MinAlign(Ld->getAlignment(), 4));
25523 SDValue NewChain = LoLd.getValue(1);
25524 if (TokenFactorIndex != -1) {
25525 Ops.push_back(LoLd);
25526 Ops.push_back(HiLd);
25527 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25530 LoAddr = St->getBasePtr();
25531 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25532 DAG.getConstant(4, StDL, MVT::i32));
25534 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25535 St->getPointerInfo(),
25536 St->isVolatile(), St->isNonTemporal(),
25537 St->getAlignment());
25538 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25539 St->getPointerInfo().getWithOffset(4),
25541 St->isNonTemporal(),
25542 MinAlign(St->getAlignment(), 4));
25543 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25546 // This is similar to the above case, but here we handle a scalar 64-bit
25547 // integer store that is extracted from a vector on a 32-bit target.
25548 // If we have SSE2, then we can treat it like a floating-point double
25549 // to get past legalization. The execution dependencies fixup pass will
25550 // choose the optimal machine instruction for the store if this really is
25551 // an integer or v2f32 rather than an f64.
25552 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25553 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25554 SDValue OldExtract = St->getOperand(1);
25555 SDValue ExtOp0 = OldExtract.getOperand(0);
25556 unsigned VecSize = ExtOp0.getValueSizeInBits();
25557 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25558 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25559 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25560 BitCast, OldExtract.getOperand(1));
25561 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25562 St->getPointerInfo(), St->isVolatile(),
25563 St->isNonTemporal(), St->getAlignment());
25569 /// Return 'true' if this vector operation is "horizontal"
25570 /// and return the operands for the horizontal operation in LHS and RHS. A
25571 /// horizontal operation performs the binary operation on successive elements
25572 /// of its first operand, then on successive elements of its second operand,
25573 /// returning the resulting values in a vector. For example, if
25574 /// A = < float a0, float a1, float a2, float a3 >
25576 /// B = < float b0, float b1, float b2, float b3 >
25577 /// then the result of doing a horizontal operation on A and B is
25578 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25579 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25580 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25581 /// set to A, RHS to B, and the routine returns 'true'.
25582 /// Note that the binary operation should have the property that if one of the
25583 /// operands is UNDEF then the result is UNDEF.
25584 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25585 // Look for the following pattern: if
25586 // A = < float a0, float a1, float a2, float a3 >
25587 // B = < float b0, float b1, float b2, float b3 >
25589 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25590 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25591 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25592 // which is A horizontal-op B.
25594 // At least one of the operands should be a vector shuffle.
25595 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25596 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25599 MVT VT = LHS.getSimpleValueType();
25601 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25602 "Unsupported vector type for horizontal add/sub");
25604 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25605 // operate independently on 128-bit lanes.
25606 unsigned NumElts = VT.getVectorNumElements();
25607 unsigned NumLanes = VT.getSizeInBits()/128;
25608 unsigned NumLaneElts = NumElts / NumLanes;
25609 assert((NumLaneElts % 2 == 0) &&
25610 "Vector type should have an even number of elements in each lane");
25611 unsigned HalfLaneElts = NumLaneElts/2;
25613 // View LHS in the form
25614 // LHS = VECTOR_SHUFFLE A, B, LMask
25615 // If LHS is not a shuffle then pretend it is the shuffle
25616 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25617 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25620 SmallVector<int, 16> LMask(NumElts);
25621 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25622 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25623 A = LHS.getOperand(0);
25624 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25625 B = LHS.getOperand(1);
25626 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25627 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25629 if (LHS.getOpcode() != ISD::UNDEF)
25631 for (unsigned i = 0; i != NumElts; ++i)
25635 // Likewise, view RHS in the form
25636 // RHS = VECTOR_SHUFFLE C, D, RMask
25638 SmallVector<int, 16> RMask(NumElts);
25639 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25640 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25641 C = RHS.getOperand(0);
25642 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25643 D = RHS.getOperand(1);
25644 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25645 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25647 if (RHS.getOpcode() != ISD::UNDEF)
25649 for (unsigned i = 0; i != NumElts; ++i)
25653 // Check that the shuffles are both shuffling the same vectors.
25654 if (!(A == C && B == D) && !(A == D && B == C))
25657 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25658 if (!A.getNode() && !B.getNode())
25661 // If A and B occur in reverse order in RHS, then "swap" them (which means
25662 // rewriting the mask).
25664 ShuffleVectorSDNode::commuteMask(RMask);
25666 // At this point LHS and RHS are equivalent to
25667 // LHS = VECTOR_SHUFFLE A, B, LMask
25668 // RHS = VECTOR_SHUFFLE A, B, RMask
25669 // Check that the masks correspond to performing a horizontal operation.
25670 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25671 for (unsigned i = 0; i != NumLaneElts; ++i) {
25672 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25674 // Ignore any UNDEF components.
25675 if (LIdx < 0 || RIdx < 0 ||
25676 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25677 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25680 // Check that successive elements are being operated on. If not, this is
25681 // not a horizontal operation.
25682 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25683 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25684 if (!(LIdx == Index && RIdx == Index + 1) &&
25685 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25690 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25691 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25695 /// Do target-specific dag combines on floating point adds.
25696 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25697 const X86Subtarget *Subtarget) {
25698 EVT VT = N->getValueType(0);
25699 SDValue LHS = N->getOperand(0);
25700 SDValue RHS = N->getOperand(1);
25702 // Try to synthesize horizontal adds from adds of shuffles.
25703 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25704 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25705 isHorizontalBinOp(LHS, RHS, true))
25706 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25710 /// Do target-specific dag combines on floating point subs.
25711 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25712 const X86Subtarget *Subtarget) {
25713 EVT VT = N->getValueType(0);
25714 SDValue LHS = N->getOperand(0);
25715 SDValue RHS = N->getOperand(1);
25717 // Try to synthesize horizontal subs from subs of shuffles.
25718 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25719 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25720 isHorizontalBinOp(LHS, RHS, false))
25721 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25725 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25726 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
25727 const X86Subtarget *Subtarget) {
25728 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25730 // F[X]OR(0.0, x) -> x
25731 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25732 if (C->getValueAPF().isPosZero())
25733 return N->getOperand(1);
25735 // F[X]OR(x, 0.0) -> x
25736 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25737 if (C->getValueAPF().isPosZero())
25738 return N->getOperand(0);
25740 EVT VT = N->getValueType(0);
25741 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
25743 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
25744 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
25746 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
25747 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
25748 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
25749 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
25750 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
25755 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25756 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25757 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25759 // Only perform optimizations if UnsafeMath is used.
25760 if (!DAG.getTarget().Options.UnsafeFPMath)
25763 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25764 // into FMINC and FMAXC, which are Commutative operations.
25765 unsigned NewOp = 0;
25766 switch (N->getOpcode()) {
25767 default: llvm_unreachable("unknown opcode");
25768 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25769 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25772 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25773 N->getOperand(0), N->getOperand(1));
25776 /// Do target-specific dag combines on X86ISD::FAND nodes.
25777 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25778 // FAND(0.0, x) -> 0.0
25779 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25780 if (C->getValueAPF().isPosZero())
25781 return N->getOperand(0);
25783 // FAND(x, 0.0) -> 0.0
25784 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25785 if (C->getValueAPF().isPosZero())
25786 return N->getOperand(1);
25791 /// Do target-specific dag combines on X86ISD::FANDN nodes
25792 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25793 // FANDN(0.0, x) -> x
25794 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25795 if (C->getValueAPF().isPosZero())
25796 return N->getOperand(1);
25798 // FANDN(x, 0.0) -> 0.0
25799 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25800 if (C->getValueAPF().isPosZero())
25801 return N->getOperand(1);
25806 static SDValue PerformBTCombine(SDNode *N,
25808 TargetLowering::DAGCombinerInfo &DCI) {
25809 // BT ignores high bits in the bit index operand.
25810 SDValue Op1 = N->getOperand(1);
25811 if (Op1.hasOneUse()) {
25812 unsigned BitWidth = Op1.getValueSizeInBits();
25813 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25814 APInt KnownZero, KnownOne;
25815 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25816 !DCI.isBeforeLegalizeOps());
25817 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25818 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25819 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25820 DCI.CommitTargetLoweringOpt(TLO);
25825 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25826 SDValue Op = N->getOperand(0);
25827 if (Op.getOpcode() == ISD::BITCAST)
25828 Op = Op.getOperand(0);
25829 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25830 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25831 VT.getVectorElementType().getSizeInBits() ==
25832 OpVT.getVectorElementType().getSizeInBits()) {
25833 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25838 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25839 const X86Subtarget *Subtarget) {
25840 EVT VT = N->getValueType(0);
25841 if (!VT.isVector())
25844 SDValue N0 = N->getOperand(0);
25845 SDValue N1 = N->getOperand(1);
25846 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25849 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25850 // both SSE and AVX2 since there is no sign-extended shift right
25851 // operation on a vector with 64-bit elements.
25852 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25853 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25854 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25855 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25856 SDValue N00 = N0.getOperand(0);
25858 // EXTLOAD has a better solution on AVX2,
25859 // it may be replaced with X86ISD::VSEXT node.
25860 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25861 if (!ISD::isNormalLoad(N00.getNode()))
25864 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25865 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25867 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25873 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
25874 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
25875 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
25876 /// eliminate extend, add, and shift instructions.
25877 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
25878 const X86Subtarget *Subtarget) {
25879 // TODO: This should be valid for other integer types.
25880 EVT VT = Sext->getValueType(0);
25881 if (VT != MVT::i64)
25884 // We need an 'add nsw' feeding into the 'sext'.
25885 SDValue Add = Sext->getOperand(0);
25886 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
25889 // Having a constant operand to the 'add' ensures that we are not increasing
25890 // the instruction count because the constant is extended for free below.
25891 // A constant operand can also become the displacement field of an LEA.
25892 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
25896 // Don't make the 'add' bigger if there's no hope of combining it with some
25897 // other 'add' or 'shl' instruction.
25898 // TODO: It may be profitable to generate simpler LEA instructions in place
25899 // of single 'add' instructions, but the cost model for selecting an LEA
25900 // currently has a high threshold.
25901 bool HasLEAPotential = false;
25902 for (auto *User : Sext->uses()) {
25903 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
25904 HasLEAPotential = true;
25908 if (!HasLEAPotential)
25911 // Everything looks good, so pull the 'sext' ahead of the 'add'.
25912 int64_t AddConstant = AddOp1->getSExtValue();
25913 SDValue AddOp0 = Add.getOperand(0);
25914 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
25915 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
25917 // The wider add is guaranteed to not wrap because both operands are
25920 Flags.setNoSignedWrap(true);
25921 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
25924 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25925 TargetLowering::DAGCombinerInfo &DCI,
25926 const X86Subtarget *Subtarget) {
25927 SDValue N0 = N->getOperand(0);
25928 EVT VT = N->getValueType(0);
25929 EVT SVT = VT.getScalarType();
25930 EVT InVT = N0.getValueType();
25931 EVT InSVT = InVT.getScalarType();
25934 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25935 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25936 // This exposes the sext to the sdivrem lowering, so that it directly extends
25937 // from AH (which we otherwise need to do contortions to access).
25938 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25939 InVT == MVT::i8 && VT == MVT::i32) {
25940 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25941 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
25942 N0.getOperand(0), N0.getOperand(1));
25943 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25944 return R.getValue(1);
25947 if (!DCI.isBeforeLegalizeOps()) {
25948 if (InVT == MVT::i1) {
25949 SDValue Zero = DAG.getConstant(0, DL, VT);
25951 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
25952 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
25957 if (VT.isVector() && Subtarget->hasSSE2()) {
25958 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
25959 EVT InVT = N.getValueType();
25960 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
25961 Size / InVT.getScalarSizeInBits());
25962 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
25963 DAG.getUNDEF(InVT));
25965 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
25968 // If target-size is less than 128-bits, extend to a type that would extend
25969 // to 128 bits, extend that and extract the original target vector.
25970 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
25971 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25972 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25973 unsigned Scale = 128 / VT.getSizeInBits();
25975 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
25976 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
25977 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
25978 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
25979 DAG.getIntPtrConstant(0, DL));
25982 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
25983 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
25984 if (VT.getSizeInBits() == 128 &&
25985 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25986 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25987 SDValue ExOp = ExtendVecSize(DL, N0, 128);
25988 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
25991 // On pre-AVX2 targets, split into 128-bit nodes of
25992 // ISD::SIGN_EXTEND_VECTOR_INREG.
25993 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
25994 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25995 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25996 unsigned NumVecs = VT.getSizeInBits() / 128;
25997 unsigned NumSubElts = 128 / SVT.getSizeInBits();
25998 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
25999 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
26001 SmallVector<SDValue, 8> Opnds;
26002 for (unsigned i = 0, Offset = 0; i != NumVecs;
26003 ++i, Offset += NumSubElts) {
26004 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
26005 DAG.getIntPtrConstant(Offset, DL));
26006 SrcVec = ExtendVecSize(DL, SrcVec, 128);
26007 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
26008 Opnds.push_back(SrcVec);
26010 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
26014 if (Subtarget->hasAVX() && VT.isVector() && VT.getSizeInBits() == 256)
26015 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26018 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
26024 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
26025 const X86Subtarget* Subtarget) {
26027 EVT VT = N->getValueType(0);
26029 // Let legalize expand this if it isn't a legal type yet.
26030 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26033 EVT ScalarVT = VT.getScalarType();
26034 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
26035 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
26036 !Subtarget->hasAVX512()))
26039 SDValue A = N->getOperand(0);
26040 SDValue B = N->getOperand(1);
26041 SDValue C = N->getOperand(2);
26043 bool NegA = (A.getOpcode() == ISD::FNEG);
26044 bool NegB = (B.getOpcode() == ISD::FNEG);
26045 bool NegC = (C.getOpcode() == ISD::FNEG);
26047 // Negative multiplication when NegA xor NegB
26048 bool NegMul = (NegA != NegB);
26050 A = A.getOperand(0);
26052 B = B.getOperand(0);
26054 C = C.getOperand(0);
26058 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
26060 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
26062 return DAG.getNode(Opcode, dl, VT, A, B, C);
26065 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
26066 TargetLowering::DAGCombinerInfo &DCI,
26067 const X86Subtarget *Subtarget) {
26068 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
26069 // (and (i32 x86isd::setcc_carry), 1)
26070 // This eliminates the zext. This transformation is necessary because
26071 // ISD::SETCC is always legalized to i8.
26073 SDValue N0 = N->getOperand(0);
26074 EVT VT = N->getValueType(0);
26076 if (N0.getOpcode() == ISD::AND &&
26078 N0.getOperand(0).hasOneUse()) {
26079 SDValue N00 = N0.getOperand(0);
26080 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26081 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
26082 if (!C || C->getZExtValue() != 1)
26084 return DAG.getNode(ISD::AND, dl, VT,
26085 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26086 N00.getOperand(0), N00.getOperand(1)),
26087 DAG.getConstant(1, dl, VT));
26091 if (N0.getOpcode() == ISD::TRUNCATE &&
26093 N0.getOperand(0).hasOneUse()) {
26094 SDValue N00 = N0.getOperand(0);
26095 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26096 return DAG.getNode(ISD::AND, dl, VT,
26097 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26098 N00.getOperand(0), N00.getOperand(1)),
26099 DAG.getConstant(1, dl, VT));
26103 if (VT.is256BitVector())
26104 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26107 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
26108 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
26109 // This exposes the zext to the udivrem lowering, so that it directly extends
26110 // from AH (which we otherwise need to do contortions to access).
26111 if (N0.getOpcode() == ISD::UDIVREM &&
26112 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
26113 (VT == MVT::i32 || VT == MVT::i64)) {
26114 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26115 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
26116 N0.getOperand(0), N0.getOperand(1));
26117 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26118 return R.getValue(1);
26124 // Optimize x == -y --> x+y == 0
26125 // x != -y --> x+y != 0
26126 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
26127 const X86Subtarget* Subtarget) {
26128 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
26129 SDValue LHS = N->getOperand(0);
26130 SDValue RHS = N->getOperand(1);
26131 EVT VT = N->getValueType(0);
26134 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
26135 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
26136 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
26137 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
26138 LHS.getOperand(1));
26139 return DAG.getSetCC(DL, N->getValueType(0), addV,
26140 DAG.getConstant(0, DL, addV.getValueType()), CC);
26142 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
26143 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
26144 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
26145 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
26146 RHS.getOperand(1));
26147 return DAG.getSetCC(DL, N->getValueType(0), addV,
26148 DAG.getConstant(0, DL, addV.getValueType()), CC);
26151 if (VT.getScalarType() == MVT::i1 &&
26152 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
26154 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26155 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26156 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26158 if (!IsSEXT0 || !IsVZero1) {
26159 // Swap the operands and update the condition code.
26160 std::swap(LHS, RHS);
26161 CC = ISD::getSetCCSwappedOperands(CC);
26163 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26164 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26165 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26168 if (IsSEXT0 && IsVZero1) {
26169 assert(VT == LHS.getOperand(0).getValueType() &&
26170 "Uexpected operand type");
26171 if (CC == ISD::SETGT)
26172 return DAG.getConstant(0, DL, VT);
26173 if (CC == ISD::SETLE)
26174 return DAG.getConstant(1, DL, VT);
26175 if (CC == ISD::SETEQ || CC == ISD::SETGE)
26176 return DAG.getNOT(DL, LHS.getOperand(0), VT);
26178 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
26179 "Unexpected condition code!");
26180 return LHS.getOperand(0);
26187 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
26188 SelectionDAG &DAG) {
26190 MVT VT = Load->getSimpleValueType(0);
26191 MVT EVT = VT.getVectorElementType();
26192 SDValue Addr = Load->getOperand(1);
26193 SDValue NewAddr = DAG.getNode(
26194 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
26195 DAG.getConstant(Index * EVT.getStoreSize(), dl,
26196 Addr.getSimpleValueType()));
26199 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
26200 DAG.getMachineFunction().getMachineMemOperand(
26201 Load->getMemOperand(), 0, EVT.getStoreSize()));
26205 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
26206 const X86Subtarget *Subtarget) {
26208 MVT VT = N->getOperand(1)->getSimpleValueType(0);
26209 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
26210 "X86insertps is only defined for v4x32");
26212 SDValue Ld = N->getOperand(1);
26213 if (MayFoldLoad(Ld)) {
26214 // Extract the countS bits from the immediate so we can get the proper
26215 // address when narrowing the vector load to a specific element.
26216 // When the second source op is a memory address, insertps doesn't use
26217 // countS and just gets an f32 from that address.
26218 unsigned DestIndex =
26219 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
26221 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
26223 // Create this as a scalar to vector to match the instruction pattern.
26224 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
26225 // countS bits are ignored when loading from memory on insertps, which
26226 // means we don't need to explicitly set them to 0.
26227 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
26228 LoadScalarToVector, N->getOperand(2));
26233 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
26234 SDValue V0 = N->getOperand(0);
26235 SDValue V1 = N->getOperand(1);
26237 EVT VT = N->getValueType(0);
26239 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
26240 // operands and changing the mask to 1. This saves us a bunch of
26241 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
26242 // x86InstrInfo knows how to commute this back after instruction selection
26243 // if it would help register allocation.
26245 // TODO: If optimizing for size or a processor that doesn't suffer from
26246 // partial register update stalls, this should be transformed into a MOVSD
26247 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
26249 if (VT == MVT::v2f64)
26250 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
26251 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
26252 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
26253 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
26259 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
26260 // as "sbb reg,reg", since it can be extended without zext and produces
26261 // an all-ones bit which is more useful than 0/1 in some cases.
26262 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
26265 return DAG.getNode(ISD::AND, DL, VT,
26266 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26267 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26269 DAG.getConstant(1, DL, VT));
26270 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
26271 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
26272 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26273 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26277 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
26278 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
26279 TargetLowering::DAGCombinerInfo &DCI,
26280 const X86Subtarget *Subtarget) {
26282 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
26283 SDValue EFLAGS = N->getOperand(1);
26285 if (CC == X86::COND_A) {
26286 // Try to convert COND_A into COND_B in an attempt to facilitate
26287 // materializing "setb reg".
26289 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
26290 // cannot take an immediate as its first operand.
26292 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
26293 EFLAGS.getValueType().isInteger() &&
26294 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
26295 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
26296 EFLAGS.getNode()->getVTList(),
26297 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
26298 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
26299 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
26303 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
26304 // a zext and produces an all-ones bit which is more useful than 0/1 in some
26306 if (CC == X86::COND_B)
26307 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
26309 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26310 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26311 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26317 // Optimize branch condition evaluation.
26319 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26320 TargetLowering::DAGCombinerInfo &DCI,
26321 const X86Subtarget *Subtarget) {
26323 SDValue Chain = N->getOperand(0);
26324 SDValue Dest = N->getOperand(1);
26325 SDValue EFLAGS = N->getOperand(3);
26326 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26328 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26329 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26330 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26337 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26338 SelectionDAG &DAG) {
26339 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26340 // optimize away operation when it's from a constant.
26342 // The general transformation is:
26343 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26344 // AND(VECTOR_CMP(x,y), constant2)
26345 // constant2 = UNARYOP(constant)
26347 // Early exit if this isn't a vector operation, the operand of the
26348 // unary operation isn't a bitwise AND, or if the sizes of the operations
26349 // aren't the same.
26350 EVT VT = N->getValueType(0);
26351 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26352 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26353 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26356 // Now check that the other operand of the AND is a constant. We could
26357 // make the transformation for non-constant splats as well, but it's unclear
26358 // that would be a benefit as it would not eliminate any operations, just
26359 // perform one more step in scalar code before moving to the vector unit.
26360 if (BuildVectorSDNode *BV =
26361 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26362 // Bail out if the vector isn't a constant.
26363 if (!BV->isConstant())
26366 // Everything checks out. Build up the new and improved node.
26368 EVT IntVT = BV->getValueType(0);
26369 // Create a new constant of the appropriate type for the transformed
26371 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26372 // The AND node needs bitcasts to/from an integer vector type around it.
26373 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26374 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26375 N->getOperand(0)->getOperand(0), MaskConst);
26376 SDValue Res = DAG.getBitcast(VT, NewAnd);
26383 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26384 const X86Subtarget *Subtarget) {
26385 SDValue Op0 = N->getOperand(0);
26386 EVT VT = N->getValueType(0);
26387 EVT InVT = Op0.getValueType();
26388 EVT InSVT = InVT.getScalarType();
26389 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26391 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26392 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26393 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26395 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26396 InVT.getVectorNumElements());
26397 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26399 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26400 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26402 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26408 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26409 const X86Subtarget *Subtarget) {
26410 // First try to optimize away the conversion entirely when it's
26411 // conditionally from a constant. Vectors only.
26412 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26415 // Now move on to more general possibilities.
26416 SDValue Op0 = N->getOperand(0);
26417 EVT VT = N->getValueType(0);
26418 EVT InVT = Op0.getValueType();
26419 EVT InSVT = InVT.getScalarType();
26421 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26422 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26423 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26425 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26426 InVT.getVectorNumElements());
26427 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26428 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26431 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26432 // a 32-bit target where SSE doesn't support i64->FP operations.
26433 if (Op0.getOpcode() == ISD::LOAD) {
26434 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26435 EVT LdVT = Ld->getValueType(0);
26437 // This transformation is not supported if the result type is f16
26438 if (VT == MVT::f16)
26441 if (!Ld->isVolatile() && !VT.isVector() &&
26442 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26443 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26444 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26445 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26446 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26453 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26454 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26455 X86TargetLowering::DAGCombinerInfo &DCI) {
26456 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26457 // the result is either zero or one (depending on the input carry bit).
26458 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26459 if (X86::isZeroNode(N->getOperand(0)) &&
26460 X86::isZeroNode(N->getOperand(1)) &&
26461 // We don't have a good way to replace an EFLAGS use, so only do this when
26463 SDValue(N, 1).use_empty()) {
26465 EVT VT = N->getValueType(0);
26466 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26467 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26468 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26469 DAG.getConstant(X86::COND_B, DL,
26472 DAG.getConstant(1, DL, VT));
26473 return DCI.CombineTo(N, Res1, CarryOut);
26479 // fold (add Y, (sete X, 0)) -> adc 0, Y
26480 // (add Y, (setne X, 0)) -> sbb -1, Y
26481 // (sub (sete X, 0), Y) -> sbb 0, Y
26482 // (sub (setne X, 0), Y) -> adc -1, Y
26483 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26486 // Look through ZExts.
26487 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26488 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26491 SDValue SetCC = Ext.getOperand(0);
26492 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26495 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26496 if (CC != X86::COND_E && CC != X86::COND_NE)
26499 SDValue Cmp = SetCC.getOperand(1);
26500 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26501 !X86::isZeroNode(Cmp.getOperand(1)) ||
26502 !Cmp.getOperand(0).getValueType().isInteger())
26505 SDValue CmpOp0 = Cmp.getOperand(0);
26506 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26507 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26509 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26510 if (CC == X86::COND_NE)
26511 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26512 DL, OtherVal.getValueType(), OtherVal,
26513 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26515 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26516 DL, OtherVal.getValueType(), OtherVal,
26517 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26520 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26521 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26522 const X86Subtarget *Subtarget) {
26523 EVT VT = N->getValueType(0);
26524 SDValue Op0 = N->getOperand(0);
26525 SDValue Op1 = N->getOperand(1);
26527 // Try to synthesize horizontal adds from adds of shuffles.
26528 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26529 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26530 isHorizontalBinOp(Op0, Op1, true))
26531 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26533 return OptimizeConditionalInDecrement(N, DAG);
26536 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26537 const X86Subtarget *Subtarget) {
26538 SDValue Op0 = N->getOperand(0);
26539 SDValue Op1 = N->getOperand(1);
26541 // X86 can't encode an immediate LHS of a sub. See if we can push the
26542 // negation into a preceding instruction.
26543 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26544 // If the RHS of the sub is a XOR with one use and a constant, invert the
26545 // immediate. Then add one to the LHS of the sub so we can turn
26546 // X-Y -> X+~Y+1, saving one register.
26547 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26548 isa<ConstantSDNode>(Op1.getOperand(1))) {
26549 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26550 EVT VT = Op0.getValueType();
26551 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26553 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26554 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26555 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26559 // Try to synthesize horizontal adds from adds of shuffles.
26560 EVT VT = N->getValueType(0);
26561 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26562 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26563 isHorizontalBinOp(Op0, Op1, true))
26564 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26566 return OptimizeConditionalInDecrement(N, DAG);
26569 /// performVZEXTCombine - Performs build vector combines
26570 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26571 TargetLowering::DAGCombinerInfo &DCI,
26572 const X86Subtarget *Subtarget) {
26574 MVT VT = N->getSimpleValueType(0);
26575 SDValue Op = N->getOperand(0);
26576 MVT OpVT = Op.getSimpleValueType();
26577 MVT OpEltVT = OpVT.getVectorElementType();
26578 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26580 // (vzext (bitcast (vzext (x)) -> (vzext x)
26582 while (V.getOpcode() == ISD::BITCAST)
26583 V = V.getOperand(0);
26585 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26586 MVT InnerVT = V.getSimpleValueType();
26587 MVT InnerEltVT = InnerVT.getVectorElementType();
26589 // If the element sizes match exactly, we can just do one larger vzext. This
26590 // is always an exact type match as vzext operates on integer types.
26591 if (OpEltVT == InnerEltVT) {
26592 assert(OpVT == InnerVT && "Types must match for vzext!");
26593 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
26596 // The only other way we can combine them is if only a single element of the
26597 // inner vzext is used in the input to the outer vzext.
26598 if (InnerEltVT.getSizeInBits() < InputBits)
26601 // In this case, the inner vzext is completely dead because we're going to
26602 // only look at bits inside of the low element. Just do the outer vzext on
26603 // a bitcast of the input to the inner.
26604 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
26607 // Check if we can bypass extracting and re-inserting an element of an input
26608 // vector. Essentially:
26609 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
26610 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
26611 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
26612 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
26613 SDValue ExtractedV = V.getOperand(0);
26614 SDValue OrigV = ExtractedV.getOperand(0);
26615 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
26616 if (ExtractIdx->getZExtValue() == 0) {
26617 MVT OrigVT = OrigV.getSimpleValueType();
26618 // Extract a subvector if necessary...
26619 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
26620 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
26621 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
26622 OrigVT.getVectorNumElements() / Ratio);
26623 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
26624 DAG.getIntPtrConstant(0, DL));
26626 Op = DAG.getBitcast(OpVT, OrigV);
26627 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
26634 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
26635 DAGCombinerInfo &DCI) const {
26636 SelectionDAG &DAG = DCI.DAG;
26637 switch (N->getOpcode()) {
26639 case ISD::EXTRACT_VECTOR_ELT:
26640 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
26643 case X86ISD::SHRUNKBLEND:
26644 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
26645 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
26646 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
26647 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
26648 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
26649 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
26650 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26653 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26654 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26655 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26656 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26657 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26658 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26659 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26660 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26661 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26662 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26663 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26664 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26666 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
26668 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26669 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26670 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26671 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26672 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26673 case ISD::ANY_EXTEND:
26674 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26675 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26676 case ISD::SIGN_EXTEND_INREG:
26677 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26678 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26679 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26680 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26681 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26682 case X86ISD::SHUFP: // Handle all target specific shuffles
26683 case X86ISD::PALIGNR:
26684 case X86ISD::UNPCKH:
26685 case X86ISD::UNPCKL:
26686 case X86ISD::MOVHLPS:
26687 case X86ISD::MOVLHPS:
26688 case X86ISD::PSHUFB:
26689 case X86ISD::PSHUFD:
26690 case X86ISD::PSHUFHW:
26691 case X86ISD::PSHUFLW:
26692 case X86ISD::MOVSS:
26693 case X86ISD::MOVSD:
26694 case X86ISD::VPERMILPI:
26695 case X86ISD::VPERM2X128:
26696 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26697 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26698 case X86ISD::INSERTPS: {
26699 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
26700 return PerformINSERTPSCombine(N, DAG, Subtarget);
26703 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26709 /// isTypeDesirableForOp - Return true if the target has native support for
26710 /// the specified value type and it is 'desirable' to use the type for the
26711 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26712 /// instruction encodings are longer and some i16 instructions are slow.
26713 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26714 if (!isTypeLegal(VT))
26716 if (VT != MVT::i16)
26723 case ISD::SIGN_EXTEND:
26724 case ISD::ZERO_EXTEND:
26725 case ISD::ANY_EXTEND:
26738 /// IsDesirableToPromoteOp - This method query the target whether it is
26739 /// beneficial for dag combiner to promote the specified node. If true, it
26740 /// should return the desired promotion type by reference.
26741 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26742 EVT VT = Op.getValueType();
26743 if (VT != MVT::i16)
26746 bool Promote = false;
26747 bool Commute = false;
26748 switch (Op.getOpcode()) {
26751 LoadSDNode *LD = cast<LoadSDNode>(Op);
26752 // If the non-extending load has a single use and it's not live out, then it
26753 // might be folded.
26754 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26755 Op.hasOneUse()*/) {
26756 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26757 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26758 // The only case where we'd want to promote LOAD (rather then it being
26759 // promoted as an operand is when it's only use is liveout.
26760 if (UI->getOpcode() != ISD::CopyToReg)
26767 case ISD::SIGN_EXTEND:
26768 case ISD::ZERO_EXTEND:
26769 case ISD::ANY_EXTEND:
26774 SDValue N0 = Op.getOperand(0);
26775 // Look out for (store (shl (load), x)).
26776 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26789 SDValue N0 = Op.getOperand(0);
26790 SDValue N1 = Op.getOperand(1);
26791 if (!Commute && MayFoldLoad(N1))
26793 // Avoid disabling potential load folding opportunities.
26794 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26796 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26806 //===----------------------------------------------------------------------===//
26807 // X86 Inline Assembly Support
26808 //===----------------------------------------------------------------------===//
26810 // Helper to match a string separated by whitespace.
26811 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
26812 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
26814 for (StringRef Piece : Pieces) {
26815 if (!S.startswith(Piece)) // Check if the piece matches.
26818 S = S.substr(Piece.size());
26819 StringRef::size_type Pos = S.find_first_not_of(" \t");
26820 if (Pos == 0) // We matched a prefix.
26829 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26831 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26832 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26833 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26834 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26836 if (AsmPieces.size() == 3)
26838 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26845 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26846 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26848 std::string AsmStr = IA->getAsmString();
26850 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26851 if (!Ty || Ty->getBitWidth() % 16 != 0)
26854 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26855 SmallVector<StringRef, 4> AsmPieces;
26856 SplitString(AsmStr, AsmPieces, ";\n");
26858 switch (AsmPieces.size()) {
26859 default: return false;
26861 // FIXME: this should verify that we are targeting a 486 or better. If not,
26862 // we will turn this bswap into something that will be lowered to logical
26863 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26864 // lower so don't worry about this.
26866 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
26867 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
26868 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
26869 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
26870 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
26871 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
26872 // No need to check constraints, nothing other than the equivalent of
26873 // "=r,0" would be valid here.
26874 return IntrinsicLowering::LowerToByteSwap(CI);
26877 // rorw $$8, ${0:w} --> llvm.bswap.i16
26878 if (CI->getType()->isIntegerTy(16) &&
26879 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26880 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
26881 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
26883 StringRef ConstraintsStr = IA->getConstraintString();
26884 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26885 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26886 if (clobbersFlagRegisters(AsmPieces))
26887 return IntrinsicLowering::LowerToByteSwap(CI);
26891 if (CI->getType()->isIntegerTy(32) &&
26892 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26893 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
26894 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
26895 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
26897 StringRef ConstraintsStr = IA->getConstraintString();
26898 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26899 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26900 if (clobbersFlagRegisters(AsmPieces))
26901 return IntrinsicLowering::LowerToByteSwap(CI);
26904 if (CI->getType()->isIntegerTy(64)) {
26905 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26906 if (Constraints.size() >= 2 &&
26907 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26908 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26909 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26910 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
26911 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
26912 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
26913 return IntrinsicLowering::LowerToByteSwap(CI);
26921 /// getConstraintType - Given a constraint letter, return the type of
26922 /// constraint it is for this target.
26923 X86TargetLowering::ConstraintType
26924 X86TargetLowering::getConstraintType(StringRef Constraint) const {
26925 if (Constraint.size() == 1) {
26926 switch (Constraint[0]) {
26937 return C_RegisterClass;
26961 return TargetLowering::getConstraintType(Constraint);
26964 /// Examine constraint type and operand type and determine a weight value.
26965 /// This object must already have been set up with the operand type
26966 /// and the current alternative constraint selected.
26967 TargetLowering::ConstraintWeight
26968 X86TargetLowering::getSingleConstraintMatchWeight(
26969 AsmOperandInfo &info, const char *constraint) const {
26970 ConstraintWeight weight = CW_Invalid;
26971 Value *CallOperandVal = info.CallOperandVal;
26972 // If we don't have a value, we can't do a match,
26973 // but allow it at the lowest weight.
26974 if (!CallOperandVal)
26976 Type *type = CallOperandVal->getType();
26977 // Look at the constraint type.
26978 switch (*constraint) {
26980 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26991 if (CallOperandVal->getType()->isIntegerTy())
26992 weight = CW_SpecificReg;
26997 if (type->isFloatingPointTy())
26998 weight = CW_SpecificReg;
27001 if (type->isX86_MMXTy() && Subtarget->hasMMX())
27002 weight = CW_SpecificReg;
27006 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
27007 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
27008 weight = CW_Register;
27011 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
27012 if (C->getZExtValue() <= 31)
27013 weight = CW_Constant;
27017 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27018 if (C->getZExtValue() <= 63)
27019 weight = CW_Constant;
27023 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27024 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
27025 weight = CW_Constant;
27029 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27030 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
27031 weight = CW_Constant;
27035 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27036 if (C->getZExtValue() <= 3)
27037 weight = CW_Constant;
27041 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27042 if (C->getZExtValue() <= 0xff)
27043 weight = CW_Constant;
27048 if (isa<ConstantFP>(CallOperandVal)) {
27049 weight = CW_Constant;
27053 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27054 if ((C->getSExtValue() >= -0x80000000LL) &&
27055 (C->getSExtValue() <= 0x7fffffffLL))
27056 weight = CW_Constant;
27060 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27061 if (C->getZExtValue() <= 0xffffffff)
27062 weight = CW_Constant;
27069 /// LowerXConstraint - try to replace an X constraint, which matches anything,
27070 /// with another that has more specific requirements based on the type of the
27071 /// corresponding operand.
27072 const char *X86TargetLowering::
27073 LowerXConstraint(EVT ConstraintVT) const {
27074 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
27075 // 'f' like normal targets.
27076 if (ConstraintVT.isFloatingPoint()) {
27077 if (Subtarget->hasSSE2())
27079 if (Subtarget->hasSSE1())
27083 return TargetLowering::LowerXConstraint(ConstraintVT);
27086 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
27087 /// vector. If it is invalid, don't add anything to Ops.
27088 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
27089 std::string &Constraint,
27090 std::vector<SDValue>&Ops,
27091 SelectionDAG &DAG) const {
27094 // Only support length 1 constraints for now.
27095 if (Constraint.length() > 1) return;
27097 char ConstraintLetter = Constraint[0];
27098 switch (ConstraintLetter) {
27101 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27102 if (C->getZExtValue() <= 31) {
27103 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27104 Op.getValueType());
27110 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27111 if (C->getZExtValue() <= 63) {
27112 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27113 Op.getValueType());
27119 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27120 if (isInt<8>(C->getSExtValue())) {
27121 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27122 Op.getValueType());
27128 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27129 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
27130 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
27131 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
27132 Op.getValueType());
27138 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27139 if (C->getZExtValue() <= 3) {
27140 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27141 Op.getValueType());
27147 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27148 if (C->getZExtValue() <= 255) {
27149 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27150 Op.getValueType());
27156 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27157 if (C->getZExtValue() <= 127) {
27158 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27159 Op.getValueType());
27165 // 32-bit signed value
27166 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27167 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27168 C->getSExtValue())) {
27169 // Widen to 64 bits here to get it sign extended.
27170 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
27173 // FIXME gcc accepts some relocatable values here too, but only in certain
27174 // memory models; it's complicated.
27179 // 32-bit unsigned value
27180 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27181 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27182 C->getZExtValue())) {
27183 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27184 Op.getValueType());
27188 // FIXME gcc accepts some relocatable values here too, but only in certain
27189 // memory models; it's complicated.
27193 // Literal immediates are always ok.
27194 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
27195 // Widen to 64 bits here to get it sign extended.
27196 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
27200 // In any sort of PIC mode addresses need to be computed at runtime by
27201 // adding in a register or some sort of table lookup. These can't
27202 // be used as immediates.
27203 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
27206 // If we are in non-pic codegen mode, we allow the address of a global (with
27207 // an optional displacement) to be used with 'i'.
27208 GlobalAddressSDNode *GA = nullptr;
27209 int64_t Offset = 0;
27211 // Match either (GA), (GA+C), (GA+C1+C2), etc.
27213 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
27214 Offset += GA->getOffset();
27216 } else if (Op.getOpcode() == ISD::ADD) {
27217 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27218 Offset += C->getZExtValue();
27219 Op = Op.getOperand(0);
27222 } else if (Op.getOpcode() == ISD::SUB) {
27223 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27224 Offset += -C->getZExtValue();
27225 Op = Op.getOperand(0);
27230 // Otherwise, this isn't something we can handle, reject it.
27234 const GlobalValue *GV = GA->getGlobal();
27235 // If we require an extra load to get this address, as in PIC mode, we
27236 // can't accept it.
27237 if (isGlobalStubReference(
27238 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
27241 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
27242 GA->getValueType(0), Offset);
27247 if (Result.getNode()) {
27248 Ops.push_back(Result);
27251 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
27254 std::pair<unsigned, const TargetRegisterClass *>
27255 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
27256 StringRef Constraint,
27258 // First, see if this is a constraint that directly corresponds to an LLVM
27260 if (Constraint.size() == 1) {
27261 // GCC Constraint Letters
27262 switch (Constraint[0]) {
27264 // TODO: Slight differences here in allocation order and leaving
27265 // RIP in the class. Do they matter any more here than they do
27266 // in the normal allocation?
27267 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
27268 if (Subtarget->is64Bit()) {
27269 if (VT == MVT::i32 || VT == MVT::f32)
27270 return std::make_pair(0U, &X86::GR32RegClass);
27271 if (VT == MVT::i16)
27272 return std::make_pair(0U, &X86::GR16RegClass);
27273 if (VT == MVT::i8 || VT == MVT::i1)
27274 return std::make_pair(0U, &X86::GR8RegClass);
27275 if (VT == MVT::i64 || VT == MVT::f64)
27276 return std::make_pair(0U, &X86::GR64RegClass);
27279 // 32-bit fallthrough
27280 case 'Q': // Q_REGS
27281 if (VT == MVT::i32 || VT == MVT::f32)
27282 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
27283 if (VT == MVT::i16)
27284 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
27285 if (VT == MVT::i8 || VT == MVT::i1)
27286 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
27287 if (VT == MVT::i64)
27288 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
27290 case 'r': // GENERAL_REGS
27291 case 'l': // INDEX_REGS
27292 if (VT == MVT::i8 || VT == MVT::i1)
27293 return std::make_pair(0U, &X86::GR8RegClass);
27294 if (VT == MVT::i16)
27295 return std::make_pair(0U, &X86::GR16RegClass);
27296 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
27297 return std::make_pair(0U, &X86::GR32RegClass);
27298 return std::make_pair(0U, &X86::GR64RegClass);
27299 case 'R': // LEGACY_REGS
27300 if (VT == MVT::i8 || VT == MVT::i1)
27301 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
27302 if (VT == MVT::i16)
27303 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
27304 if (VT == MVT::i32 || !Subtarget->is64Bit())
27305 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
27306 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
27307 case 'f': // FP Stack registers.
27308 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
27309 // value to the correct fpstack register class.
27310 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
27311 return std::make_pair(0U, &X86::RFP32RegClass);
27312 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27313 return std::make_pair(0U, &X86::RFP64RegClass);
27314 return std::make_pair(0U, &X86::RFP80RegClass);
27315 case 'y': // MMX_REGS if MMX allowed.
27316 if (!Subtarget->hasMMX()) break;
27317 return std::make_pair(0U, &X86::VR64RegClass);
27318 case 'Y': // SSE_REGS if SSE2 allowed
27319 if (!Subtarget->hasSSE2()) break;
27321 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27322 if (!Subtarget->hasSSE1()) break;
27324 switch (VT.SimpleTy) {
27326 // Scalar SSE types.
27329 return std::make_pair(0U, &X86::FR32RegClass);
27332 return std::make_pair(0U, &X86::FR64RegClass);
27340 return std::make_pair(0U, &X86::VR128RegClass);
27348 return std::make_pair(0U, &X86::VR256RegClass);
27353 return std::make_pair(0U, &X86::VR512RegClass);
27359 // Use the default implementation in TargetLowering to convert the register
27360 // constraint into a member of a register class.
27361 std::pair<unsigned, const TargetRegisterClass*> Res;
27362 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27364 // Not found as a standard register?
27366 // Map st(0) -> st(7) -> ST0
27367 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27368 tolower(Constraint[1]) == 's' &&
27369 tolower(Constraint[2]) == 't' &&
27370 Constraint[3] == '(' &&
27371 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27372 Constraint[5] == ')' &&
27373 Constraint[6] == '}') {
27375 Res.first = X86::FP0+Constraint[4]-'0';
27376 Res.second = &X86::RFP80RegClass;
27380 // GCC allows "st(0)" to be called just plain "st".
27381 if (StringRef("{st}").equals_lower(Constraint)) {
27382 Res.first = X86::FP0;
27383 Res.second = &X86::RFP80RegClass;
27388 if (StringRef("{flags}").equals_lower(Constraint)) {
27389 Res.first = X86::EFLAGS;
27390 Res.second = &X86::CCRRegClass;
27394 // 'A' means EAX + EDX.
27395 if (Constraint == "A") {
27396 Res.first = X86::EAX;
27397 Res.second = &X86::GR32_ADRegClass;
27403 // Otherwise, check to see if this is a register class of the wrong value
27404 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27405 // turn into {ax},{dx}.
27406 // MVT::Other is used to specify clobber names.
27407 if (Res.second->hasType(VT) || VT == MVT::Other)
27408 return Res; // Correct type already, nothing to do.
27410 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27411 // return "eax". This should even work for things like getting 64bit integer
27412 // registers when given an f64 type.
27413 const TargetRegisterClass *Class = Res.second;
27414 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27415 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27416 unsigned Size = VT.getSizeInBits();
27417 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27418 : Size == 16 ? MVT::i16
27419 : Size == 32 ? MVT::i32
27420 : Size == 64 ? MVT::i64
27422 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27424 Res.first = DestReg;
27425 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27426 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27427 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27428 : &X86::GR64RegClass;
27429 assert(Res.second->contains(Res.first) && "Register in register class");
27431 // No register found/type mismatch.
27433 Res.second = nullptr;
27435 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27436 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27437 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27438 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27439 Class == &X86::VR512RegClass) {
27440 // Handle references to XMM physical registers that got mapped into the
27441 // wrong class. This can happen with constraints like {xmm0} where the
27442 // target independent register mapper will just pick the first match it can
27443 // find, ignoring the required type.
27445 if (VT == MVT::f32 || VT == MVT::i32)
27446 Res.second = &X86::FR32RegClass;
27447 else if (VT == MVT::f64 || VT == MVT::i64)
27448 Res.second = &X86::FR64RegClass;
27449 else if (X86::VR128RegClass.hasType(VT))
27450 Res.second = &X86::VR128RegClass;
27451 else if (X86::VR256RegClass.hasType(VT))
27452 Res.second = &X86::VR256RegClass;
27453 else if (X86::VR512RegClass.hasType(VT))
27454 Res.second = &X86::VR512RegClass;
27456 // Type mismatch and not a clobber: Return an error;
27458 Res.second = nullptr;
27465 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27466 const AddrMode &AM, Type *Ty,
27467 unsigned AS) const {
27468 // Scaling factors are not free at all.
27469 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27470 // will take 2 allocations in the out of order engine instead of 1
27471 // for plain addressing mode, i.e. inst (reg1).
27473 // vaddps (%rsi,%drx), %ymm0, %ymm1
27474 // Requires two allocations (one for the load, one for the computation)
27476 // vaddps (%rsi), %ymm0, %ymm1
27477 // Requires just 1 allocation, i.e., freeing allocations for other operations
27478 // and having less micro operations to execute.
27480 // For some X86 architectures, this is even worse because for instance for
27481 // stores, the complex addressing mode forces the instruction to use the
27482 // "load" ports instead of the dedicated "store" port.
27483 // E.g., on Haswell:
27484 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27485 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27486 if (isLegalAddressingMode(DL, AM, Ty, AS))
27487 // Scale represents reg2 * scale, thus account for 1
27488 // as soon as we use a second register.
27489 return AM.Scale != 0;
27493 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27494 // Integer division on x86 is expensive. However, when aggressively optimizing
27495 // for code size, we prefer to use a div instruction, as it is usually smaller
27496 // than the alternative sequence.
27497 // The exception to this is vector division. Since x86 doesn't have vector
27498 // integer division, leaving the division as-is is a loss even in terms of
27499 // size, because it will have to be scalarized, while the alternative code
27500 // sequence can be performed in vector form.
27501 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27502 Attribute::MinSize);
27503 return OptSize && !VT.isVector();