1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86ISelLowering.h"
17 #include "X86TargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Support/CommandLine.h"
29 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
30 cl::desc("Enable fastcc on X86"));
32 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
33 : TargetLowering(TM) {
34 // Set up the TargetLowering object.
36 // X86 is weird, it always uses i8 for shift amounts and setcc results.
37 setShiftAmountType(MVT::i8);
38 setSetCCResultType(MVT::i8);
39 setSetCCResultContents(ZeroOrOneSetCCResult);
40 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
42 // Set up the register classes.
43 addRegisterClass(MVT::i8, X86::R8RegisterClass);
44 addRegisterClass(MVT::i16, X86::R16RegisterClass);
45 addRegisterClass(MVT::i32, X86::R32RegisterClass);
47 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
49 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
50 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
51 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
52 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
54 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
56 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
57 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
60 // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64
62 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
63 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
64 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
65 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
68 // Handle FP_TO_UINT by promoting the destination to a larger signed
70 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
71 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
72 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
75 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
77 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
79 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
80 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
81 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
83 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
84 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
87 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
89 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
90 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
91 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
92 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
93 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
94 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
95 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
96 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
97 setOperationAction(ISD::FREM , MVT::f64 , Expand);
98 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
99 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
100 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
101 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
102 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
103 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
104 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
105 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
106 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
107 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
109 setOperationAction(ISD::READIO , MVT::i1 , Expand);
110 setOperationAction(ISD::READIO , MVT::i8 , Expand);
111 setOperationAction(ISD::READIO , MVT::i16 , Expand);
112 setOperationAction(ISD::READIO , MVT::i32 , Expand);
113 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand);
114 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
115 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
116 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
118 // These should be promoted to a larger select which is supported.
119 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
120 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
121 // X86 wants to expand cmov itself.
123 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
124 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
125 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
126 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
127 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
128 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
131 // We don't have line number support yet.
132 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
133 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
136 // Set up the FP register classes.
137 addRegisterClass(MVT::f32, X86::V4F4RegisterClass);
138 addRegisterClass(MVT::f64, X86::V2F8RegisterClass);
140 // SSE has no load+extend ops
141 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
142 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
144 // SSE has no i16 to fp conversion, only i32
145 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
146 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
148 // Expand FP_TO_UINT into a select.
149 // FIXME: We would like to use a Custom expander here eventually to do
150 // the optimal thing for SSE vs. the default expansion in the legalizer.
151 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
153 // We don't support sin/cos/sqrt/fmod
154 setOperationAction(ISD::FSIN , MVT::f64, Expand);
155 setOperationAction(ISD::FCOS , MVT::f64, Expand);
156 setOperationAction(ISD::FABS , MVT::f64, Expand);
157 setOperationAction(ISD::FNEG , MVT::f64, Expand);
158 setOperationAction(ISD::FREM , MVT::f64, Expand);
159 setOperationAction(ISD::FSIN , MVT::f32, Expand);
160 setOperationAction(ISD::FCOS , MVT::f32, Expand);
161 setOperationAction(ISD::FABS , MVT::f32, Expand);
162 setOperationAction(ISD::FNEG , MVT::f32, Expand);
163 setOperationAction(ISD::FREM , MVT::f32, Expand);
165 addLegalFPImmediate(+0.0); // xorps / xorpd
167 // Set up the FP register classes.
168 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
171 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
172 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
175 addLegalFPImmediate(+0.0); // FLD0
176 addLegalFPImmediate(+1.0); // FLD1
177 addLegalFPImmediate(-0.0); // FLD0/FCHS
178 addLegalFPImmediate(-1.0); // FLD1/FCHS
180 computeRegisterProperties();
182 maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores
183 maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores
184 maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores
185 allowUnalignedMemoryAccesses = true; // x86 supports it!
188 std::vector<SDOperand>
189 X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
190 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
191 return LowerFastCCArguments(F, DAG);
192 return LowerCCCArguments(F, DAG);
195 std::pair<SDOperand, SDOperand>
196 X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
197 bool isVarArg, unsigned CallingConv,
199 SDOperand Callee, ArgListTy &Args,
201 assert((!isVarArg || CallingConv == CallingConv::C) &&
202 "Only C takes varargs!");
203 if (CallingConv == CallingConv::Fast && EnableFastCC)
204 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
205 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
208 SDOperand X86TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
211 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
214 MVT::ValueType OpVT = Op.getValueType();
216 default: assert(0 && "Unknown type to return!");
218 Copy = DAG.getCopyToReg(Chain, X86::EAX, Op, SDOperand());
221 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
222 DAG.getConstant(1, MVT::i32));
223 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
224 DAG.getConstant(0, MVT::i32));
225 Copy = DAG.getCopyToReg(Chain, X86::EAX, Hi, SDOperand());
226 Copy = DAG.getCopyToReg(Copy, X86::EDX, Lo, Copy.getValue(1));
232 std::vector<MVT::ValueType> Tys;
233 Tys.push_back(MVT::Other);
234 Tys.push_back(MVT::Flag);
235 std::vector<SDOperand> Ops;
236 Ops.push_back(Chain);
237 if (OpVT == MVT::f32)
238 Op = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op);
240 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
242 // Spill the value to memory and reload it into top of stack.
243 unsigned Size = MVT::getSizeInBits(OpVT)/8;
244 MachineFunction &MF = DAG.getMachineFunction();
245 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
246 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
247 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Op,
248 StackSlot, DAG.getSrcValue(NULL));
249 std::vector<MVT::ValueType> Tys;
250 Tys.push_back(MVT::f64);
251 Tys.push_back(MVT::Other);
252 std::vector<SDOperand> Ops;
253 Ops.push_back(Chain);
254 Ops.push_back(StackSlot);
255 Ops.push_back(DAG.getValueType(OpVT));
256 Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
258 Tys.push_back(MVT::Other);
259 Tys.push_back(MVT::Flag);
261 Ops.push_back(Copy.getValue(1));
263 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
268 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
269 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
273 //===----------------------------------------------------------------------===//
274 // C Calling Convention implementation
275 //===----------------------------------------------------------------------===//
277 std::vector<SDOperand>
278 X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
279 std::vector<SDOperand> ArgValues;
281 MachineFunction &MF = DAG.getMachineFunction();
282 MachineFrameInfo *MFI = MF.getFrameInfo();
284 // Add DAG nodes to load the arguments... On entry to a function on the X86,
285 // the stack frame looks like this:
287 // [ESP] -- return address
288 // [ESP + 4] -- first argument (leftmost lexically)
289 // [ESP + 8] -- second argument, if first argument is four bytes in size
292 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
293 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
294 MVT::ValueType ObjectVT = getValueType(I->getType());
295 unsigned ArgIncrement = 4;
298 default: assert(0 && "Unhandled argument type!");
300 case MVT::i8: ObjSize = 1; break;
301 case MVT::i16: ObjSize = 2; break;
302 case MVT::i32: ObjSize = 4; break;
303 case MVT::i64: ObjSize = ArgIncrement = 8; break;
304 case MVT::f32: ObjSize = 4; break;
305 case MVT::f64: ObjSize = ArgIncrement = 8; break;
307 // Create the frame index object for this incoming parameter...
308 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
310 // Create the SelectionDAG nodes corresponding to a load from this parameter
311 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
313 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
317 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
318 DAG.getSrcValue(NULL));
320 if (MVT::isInteger(ObjectVT))
321 ArgValue = DAG.getConstant(0, ObjectVT);
323 ArgValue = DAG.getConstantFP(0, ObjectVT);
325 ArgValues.push_back(ArgValue);
327 ArgOffset += ArgIncrement; // Move on to the next argument...
330 // If the function takes variable number of arguments, make a frame index for
331 // the start of the first vararg value... for expansion of llvm.va_start.
333 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
334 ReturnAddrIndex = 0; // No return address slot generated yet.
335 BytesToPopOnReturn = 0; // Callee pops nothing.
336 BytesCallerReserves = ArgOffset;
338 // Finally, inform the code generator which regs we return values in.
339 switch (getValueType(F.getReturnType())) {
340 default: assert(0 && "Unknown type!");
341 case MVT::isVoid: break;
346 MF.addLiveOut(X86::EAX);
349 MF.addLiveOut(X86::EAX);
350 MF.addLiveOut(X86::EDX);
354 MF.addLiveOut(X86::ST0);
360 std::pair<SDOperand, SDOperand>
361 X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
362 bool isVarArg, bool isTailCall,
363 SDOperand Callee, ArgListTy &Args,
365 // Count how many bytes are to be pushed on the stack.
366 unsigned NumBytes = 0;
370 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
371 DAG.getConstant(0, getPointerTy()));
373 for (unsigned i = 0, e = Args.size(); i != e; ++i)
374 switch (getValueType(Args[i].second)) {
375 default: assert(0 && "Unknown value type!");
389 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
390 DAG.getConstant(NumBytes, getPointerTy()));
392 // Arguments go on the stack in reverse order, as specified by the ABI.
393 unsigned ArgOffset = 0;
394 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
396 std::vector<SDOperand> Stores;
398 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
399 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
400 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
402 switch (getValueType(Args[i].second)) {
403 default: assert(0 && "Unexpected ValueType for argument!");
407 // Promote the integer to 32 bits. If the input type is signed use a
408 // sign extend, otherwise use a zero extend.
409 if (Args[i].second->isSigned())
410 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
412 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
417 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
418 Args[i].first, PtrOff,
419 DAG.getSrcValue(NULL)));
424 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
425 Args[i].first, PtrOff,
426 DAG.getSrcValue(NULL)));
431 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
434 std::vector<MVT::ValueType> RetVals;
435 MVT::ValueType RetTyVT = getValueType(RetTy);
436 RetVals.push_back(MVT::Other);
438 // The result values produced have to be legal. Promote the result.
440 case MVT::isVoid: break;
442 RetVals.push_back(RetTyVT);
447 RetVals.push_back(MVT::i32);
451 RetVals.push_back(MVT::f32);
453 RetVals.push_back(MVT::f64);
456 RetVals.push_back(MVT::i32);
457 RetVals.push_back(MVT::i32);
462 std::vector<MVT::ValueType> NodeTys;
463 NodeTys.push_back(MVT::Other); // Returns a chain
464 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
466 std::vector<SDOperand> Ops;
467 Ops.push_back(Chain);
468 Ops.push_back(Callee);
470 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
472 SDOperand InFlag = Chain.getValue(1);
475 if (RetTyVT != MVT::isVoid) {
477 default: assert(0 && "Unknown value type to return!");
480 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
481 Chain = RetVal.getValue(1);
484 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
485 Chain = RetVal.getValue(1);
488 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
489 Chain = RetVal.getValue(1);
492 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
493 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
495 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
496 Chain = Hi.getValue(1);
501 std::vector<MVT::ValueType> Tys;
502 Tys.push_back(MVT::f64);
503 Tys.push_back(MVT::Other);
504 std::vector<SDOperand> Ops;
505 Ops.push_back(Chain);
506 Ops.push_back(InFlag);
507 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
508 Chain = RetVal.getValue(1);
510 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
511 MachineFunction &MF = DAG.getMachineFunction();
512 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
513 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
515 Tys.push_back(MVT::Other);
517 Ops.push_back(Chain);
518 Ops.push_back(RetVal);
519 Ops.push_back(StackSlot);
520 Ops.push_back(DAG.getValueType(RetTyVT));
521 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
522 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
523 DAG.getSrcValue(NULL));
524 Chain = RetVal.getValue(1);
525 } else if (RetTyVT == MVT::f32)
526 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
532 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
533 DAG.getConstant(NumBytes, getPointerTy()),
534 DAG.getConstant(0, getPointerTy()));
535 return std::make_pair(RetVal, Chain);
537 std::vector<SDOperand> Ops;
538 Ops.push_back(Chain);
539 Ops.push_back(Callee);
540 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
541 Ops.push_back(DAG.getConstant(0, getPointerTy()));
543 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
548 case MVT::isVoid: break;
550 ResultVal = TheCall.getValue(1);
555 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
558 // FIXME: we would really like to remember that this FP_ROUND operation is
559 // okay to eliminate if we allow excess FP precision.
560 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
563 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
564 TheCall.getValue(2));
568 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
569 return std::make_pair(ResultVal, Chain);
574 X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
575 Value *VAListV, SelectionDAG &DAG) {
576 // vastart just stores the address of the VarArgsFrameIndex slot.
577 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
578 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
579 DAG.getSrcValue(VAListV));
583 std::pair<SDOperand,SDOperand>
584 X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP,
585 Value *VAListV, const Type *ArgTy,
587 MVT::ValueType ArgVT = getValueType(ArgTy);
588 SDOperand Val = DAG.getLoad(MVT::i32, Chain,
589 VAListP, DAG.getSrcValue(VAListV));
590 SDOperand Result = DAG.getLoad(ArgVT, Chain, Val,
591 DAG.getSrcValue(NULL));
593 if (ArgVT == MVT::i32)
596 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
597 "Other types should have been promoted for varargs!");
600 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
601 DAG.getConstant(Amt, Val.getValueType()));
602 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
603 Val, VAListP, DAG.getSrcValue(VAListV));
604 return std::make_pair(Result, Chain);
607 //===----------------------------------------------------------------------===//
608 // Fast Calling Convention implementation
609 //===----------------------------------------------------------------------===//
611 // The X86 'fast' calling convention passes up to two integer arguments in
612 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
613 // and requires that the callee pop its arguments off the stack (allowing proper
614 // tail calls), and has the same return value conventions as C calling convs.
616 // This calling convention always arranges for the callee pop value to be 8n+4
617 // bytes, which is needed for tail recursion elimination and stack alignment
620 // Note that this can be enhanced in the future to pass fp vals in registers
621 // (when we have a global fp allocator) and do other tricks.
624 /// AddLiveIn - This helper function adds the specified physical register to the
625 /// MachineFunction as a live in value. It also creates a corresponding virtual
627 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
628 TargetRegisterClass *RC) {
629 assert(RC->contains(PReg) && "Not the correct regclass!");
630 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
631 MF.addLiveIn(PReg, VReg);
636 std::vector<SDOperand>
637 X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
638 std::vector<SDOperand> ArgValues;
640 MachineFunction &MF = DAG.getMachineFunction();
641 MachineFrameInfo *MFI = MF.getFrameInfo();
643 // Add DAG nodes to load the arguments... On entry to a function the stack
644 // frame looks like this:
646 // [ESP] -- return address
647 // [ESP + 4] -- first nonreg argument (leftmost lexically)
648 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
650 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
652 // Keep track of the number of integer regs passed so far. This can be either
653 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
655 unsigned NumIntRegs = 0;
657 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
658 MVT::ValueType ObjectVT = getValueType(I->getType());
659 unsigned ArgIncrement = 4;
660 unsigned ObjSize = 0;
664 default: assert(0 && "Unhandled argument type!");
667 if (NumIntRegs < 2) {
668 if (!I->use_empty()) {
669 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
670 X86::R8RegisterClass);
671 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
672 DAG.setRoot(ArgValue.getValue(1));
673 if (ObjectVT == MVT::i1)
674 // FIXME: Should insert a assertzext here.
675 ArgValue = DAG.getNode(ISD::TRUNCATE, MVT::i1, ArgValue);
684 if (NumIntRegs < 2) {
685 if (!I->use_empty()) {
686 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
687 X86::R16RegisterClass);
688 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
689 DAG.setRoot(ArgValue.getValue(1));
697 if (NumIntRegs < 2) {
698 if (!I->use_empty()) {
699 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
700 X86::R32RegisterClass);
701 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
702 DAG.setRoot(ArgValue.getValue(1));
710 if (NumIntRegs == 0) {
711 if (!I->use_empty()) {
712 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
713 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
715 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
716 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
717 DAG.setRoot(Hi.getValue(1));
719 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
723 } else if (NumIntRegs == 1) {
724 if (!I->use_empty()) {
725 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
726 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
727 DAG.setRoot(Low.getValue(1));
729 // Load the high part from memory.
730 // Create the frame index object for this incoming parameter...
731 int FI = MFI->CreateFixedObject(4, ArgOffset);
732 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
733 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
734 DAG.getSrcValue(NULL));
735 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
741 ObjSize = ArgIncrement = 8;
743 case MVT::f32: ObjSize = 4; break;
744 case MVT::f64: ObjSize = ArgIncrement = 8; break;
747 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
749 if (ObjSize && !I->use_empty()) {
750 // Create the frame index object for this incoming parameter...
751 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
753 // Create the SelectionDAG nodes corresponding to a load from this
755 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
757 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
758 DAG.getSrcValue(NULL));
759 } else if (ArgValue.Val == 0) {
760 if (MVT::isInteger(ObjectVT))
761 ArgValue = DAG.getConstant(0, ObjectVT);
763 ArgValue = DAG.getConstantFP(0, ObjectVT);
765 ArgValues.push_back(ArgValue);
768 ArgOffset += ArgIncrement; // Move on to the next argument.
771 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
772 // arguments and the arguments after the retaddr has been pushed are aligned.
773 if ((ArgOffset & 7) == 0)
776 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
777 ReturnAddrIndex = 0; // No return address slot generated yet.
778 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
779 BytesCallerReserves = 0;
781 // Finally, inform the code generator which regs we return values in.
782 switch (getValueType(F.getReturnType())) {
783 default: assert(0 && "Unknown type!");
784 case MVT::isVoid: break;
789 MF.addLiveOut(X86::EAX);
792 MF.addLiveOut(X86::EAX);
793 MF.addLiveOut(X86::EDX);
797 MF.addLiveOut(X86::ST0);
803 std::pair<SDOperand, SDOperand>
804 X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
805 bool isTailCall, SDOperand Callee,
806 ArgListTy &Args, SelectionDAG &DAG) {
807 // Count how many bytes are to be pushed on the stack.
808 unsigned NumBytes = 0;
810 // Keep track of the number of integer regs passed so far. This can be either
811 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
813 unsigned NumIntRegs = 0;
815 for (unsigned i = 0, e = Args.size(); i != e; ++i)
816 switch (getValueType(Args[i].second)) {
817 default: assert(0 && "Unknown value type!");
822 if (NumIntRegs < 2) {
831 if (NumIntRegs == 0) {
834 } else if (NumIntRegs == 1) {
846 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
847 // arguments and the arguments after the retaddr has been pushed are aligned.
848 if ((NumBytes & 7) == 0)
851 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
852 DAG.getConstant(NumBytes, getPointerTy()));
854 // Arguments go on the stack in reverse order, as specified by the ABI.
855 unsigned ArgOffset = 0;
856 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
859 std::vector<SDOperand> Stores;
860 std::vector<SDOperand> RegValuesToPass;
861 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
862 switch (getValueType(Args[i].second)) {
863 default: assert(0 && "Unexpected ValueType for argument!");
865 Args[i].first = DAG.getNode(ISD::ANY_EXTEND, MVT::i8, Args[i].first);
870 if (NumIntRegs < 2) {
871 RegValuesToPass.push_back(Args[i].first);
877 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
878 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
879 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
880 Args[i].first, PtrOff,
881 DAG.getSrcValue(NULL)));
886 if (NumIntRegs < 2) { // Can pass part of it in regs?
887 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
888 Args[i].first, DAG.getConstant(1, MVT::i32));
889 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
890 Args[i].first, DAG.getConstant(0, MVT::i32));
891 RegValuesToPass.push_back(Lo);
893 if (NumIntRegs < 2) { // Pass both parts in regs?
894 RegValuesToPass.push_back(Hi);
897 // Pass the high part in memory.
898 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
899 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
900 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
901 Hi, PtrOff, DAG.getSrcValue(NULL)));
908 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
909 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
910 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
911 Args[i].first, PtrOff,
912 DAG.getSrcValue(NULL)));
918 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
920 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
921 // arguments and the arguments after the retaddr has been pushed are aligned.
922 if ((ArgOffset & 7) == 0)
925 std::vector<MVT::ValueType> RetVals;
926 MVT::ValueType RetTyVT = getValueType(RetTy);
928 RetVals.push_back(MVT::Other);
930 // The result values produced have to be legal. Promote the result.
932 case MVT::isVoid: break;
934 RetVals.push_back(RetTyVT);
939 RetVals.push_back(MVT::i32);
943 RetVals.push_back(MVT::f32);
945 RetVals.push_back(MVT::f64);
948 RetVals.push_back(MVT::i32);
949 RetVals.push_back(MVT::i32);
953 std::vector<SDOperand> Ops;
954 Ops.push_back(Chain);
955 Ops.push_back(Callee);
956 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
957 // Callee pops all arg values on the stack.
958 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
960 // Pass register arguments as needed.
961 Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end());
963 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
965 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
969 case MVT::isVoid: break;
971 ResultVal = TheCall.getValue(1);
976 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
979 // FIXME: we would really like to remember that this FP_ROUND operation is
980 // okay to eliminate if we allow excess FP precision.
981 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
984 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
985 TheCall.getValue(2));
989 return std::make_pair(ResultVal, Chain);
992 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
993 if (ReturnAddrIndex == 0) {
994 // Set up a frame object for the return address.
995 MachineFunction &MF = DAG.getMachineFunction();
996 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
999 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
1004 std::pair<SDOperand, SDOperand> X86TargetLowering::
1005 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
1006 SelectionDAG &DAG) {
1008 if (Depth) // Depths > 0 not supported yet!
1009 Result = DAG.getConstant(0, getPointerTy());
1011 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
1012 if (!isFrameAddress)
1013 // Just load the return address
1014 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
1015 DAG.getSrcValue(NULL));
1017 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
1018 DAG.getConstant(4, MVT::i32));
1020 return std::make_pair(Result, Chain);
1023 //===----------------------------------------------------------------------===//
1024 // X86 Custom Lowering Hooks
1025 //===----------------------------------------------------------------------===//
1027 /// LowerOperation - Provide custom lowering hooks for some operations.
1029 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1030 switch (Op.getOpcode()) {
1031 default: assert(0 && "Should not custom lower this!");
1032 case ISD::SINT_TO_FP: {
1033 assert(Op.getValueType() == MVT::f64 &&
1034 Op.getOperand(0).getValueType() == MVT::i64 &&
1035 "Unknown SINT_TO_FP to lower!");
1036 // We lower sint64->FP into a store to a temporary stack slot, followed by a
1038 MachineFunction &MF = DAG.getMachineFunction();
1039 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
1040 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1041 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
1042 Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL));
1043 std::vector<MVT::ValueType> RTs;
1044 RTs.push_back(MVT::f64);
1045 RTs.push_back(MVT::Other);
1046 std::vector<SDOperand> Ops;
1047 Ops.push_back(Store);
1048 Ops.push_back(StackSlot);
1049 return DAG.getNode(X86ISD::FILD64m, RTs, Ops);
1051 case ISD::FP_TO_SINT: {
1052 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
1053 Op.getOperand(0).getValueType() == MVT::f64 &&
1054 "Unknown FP_TO_SINT to lower!");
1055 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
1057 MachineFunction &MF = DAG.getMachineFunction();
1058 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
1059 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
1060 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1063 switch (Op.getValueType()) {
1064 default: assert(0 && "Invalid FP_TO_SINT to lower!");
1065 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
1066 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
1067 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
1070 // Build the FP_TO_INT*_IN_MEM
1071 std::vector<SDOperand> Ops;
1072 Ops.push_back(DAG.getEntryNode());
1073 Ops.push_back(Op.getOperand(0));
1074 Ops.push_back(StackSlot);
1075 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
1078 return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
1079 DAG.getSrcValue(NULL));
1081 case ISD::READCYCLECOUNTER: {
1082 std::vector<MVT::ValueType> Tys;
1083 Tys.push_back(MVT::Other);
1084 Tys.push_back(MVT::Flag);
1085 std::vector<SDOperand> Ops;
1086 Ops.push_back(Op.getOperand(0));
1087 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops);
1089 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
1090 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
1091 MVT::i32, Ops[0].getValue(2)));
1092 Ops.push_back(Ops[1].getValue(1));
1093 Tys[0] = Tys[1] = MVT::i32;
1094 Tys.push_back(MVT::Other);
1095 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1098 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
1099 SDOperand CC = Op.getOperand(2);
1100 SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1101 Op.getOperand(0), Op.getOperand(1));
1102 return DAG.getNode(X86ISD::SETCC, MVT::i8, CC, Cond);
1105 SDOperand Cond = Op.getOperand(0);
1107 if (Cond.getOpcode() == X86ISD::SETCC) {
1108 CC = Cond.getOperand(0);
1109 Cond = Cond.getOperand(1);
1110 } else if (Cond.getOpcode() == ISD::SETCC) {
1111 CC = Cond.getOperand(2);
1112 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1113 Cond.getOperand(0), Cond.getOperand(1));
1115 CC = DAG.getCondCode(ISD::SETEQ);
1116 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1118 return DAG.getNode(X86ISD::CMOV, Op.getValueType(),
1119 Op.getOperand(1), Op.getOperand(2), CC, Cond);
1122 SDOperand Cond = Op.getOperand(1);
1123 SDOperand Dest = Op.getOperand(2);
1125 // TODO: handle Cond == OR / AND / XOR
1126 if (Cond.getOpcode() == X86ISD::SETCC) {
1127 CC = Cond.getOperand(0);
1128 Cond = Cond.getOperand(1);
1129 } else if (Cond.getOpcode() == ISD::SETCC) {
1130 CC = Cond.getOperand(2);
1131 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1132 Cond.getOperand(0), Cond.getOperand(1));
1134 CC = DAG.getCondCode(ISD::SETNE);
1135 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1137 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
1138 Op.getOperand(0), Op.getOperand(2), CC, Cond);
1140 case ISD::GlobalAddress: {
1141 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1142 SDOperand GVOp = DAG.getTargetGlobalAddress(GV, getPointerTy());
1143 // For Darwin, external and weak symbols are indirect, so we want to load
1144 // the value at address GV, not the value of GV itself. This means that
1145 // the GlobalAddress must be in the base or index register of the address,
1146 // not the GV offset field.
1147 if (getTargetMachine().
1148 getSubtarget<X86Subtarget>().getIndirectExternAndWeakGlobals() &&
1149 (GV->hasWeakLinkage() || GV->isExternal()))
1150 return DAG.getLoad(MVT::i32, DAG.getEntryNode(),
1151 GVOp, DAG.getSrcValue(NULL));
1159 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
1161 default: return NULL;
1162 case X86ISD::FILD64m: return "X86ISD::FILD64m";
1163 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
1164 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
1165 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
1166 case X86ISD::FLD: return "X86ISD::FLD";
1167 case X86ISD::FST: return "X86ISD::FST";
1168 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
1169 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
1170 case X86ISD::CALL: return "X86ISD::CALL";
1171 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
1172 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
1173 case X86ISD::CMP: return "X86ISD::CMP";
1174 case X86ISD::TEST: return "X86ISD::TEST";
1175 case X86ISD::SETCC: return "X86ISD::SETCC";
1176 case X86ISD::CMOV: return "X86ISD::CMOV";
1177 case X86ISD::BRCOND: return "X86ISD::BRCOND";
1178 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
1182 bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
1183 uint64_t Mask) const {
1185 unsigned Opc = Op.getOpcode();
1189 assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node");
1191 case X86ISD::SETCC: return (Mask & 1) == 0;