1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86ISelLowering.h"
17 #include "X86TargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Support/CommandLine.h"
29 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
30 cl::desc("Enable fastcc on X86"));
32 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
33 : TargetLowering(TM) {
34 // Set up the TargetLowering object.
36 // X86 is weird, it always uses i8 for shift amounts and setcc results.
37 setShiftAmountType(MVT::i8);
38 setSetCCResultType(MVT::i8);
39 setSetCCResultContents(ZeroOrOneSetCCResult);
40 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
42 // Set up the register classes.
43 addRegisterClass(MVT::i8, X86::R8RegisterClass);
44 addRegisterClass(MVT::i16, X86::R16RegisterClass);
45 addRegisterClass(MVT::i32, X86::R32RegisterClass);
47 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
49 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
50 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
51 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
52 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
54 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
56 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
57 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
60 // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64
62 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
63 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
64 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
65 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
68 // Handle FP_TO_UINT by promoting the destination to a larger signed
70 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
71 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
72 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
75 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
77 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
79 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
80 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
81 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
83 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
84 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
87 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
89 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
90 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
91 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
92 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
93 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
94 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
95 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
96 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
97 setOperationAction(ISD::FREM , MVT::f64 , Expand);
98 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
99 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
100 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
101 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
102 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
103 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
104 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
105 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
106 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
107 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
109 setOperationAction(ISD::READIO , MVT::i1 , Expand);
110 setOperationAction(ISD::READIO , MVT::i8 , Expand);
111 setOperationAction(ISD::READIO , MVT::i16 , Expand);
112 setOperationAction(ISD::READIO , MVT::i32 , Expand);
113 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand);
114 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
115 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
116 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
118 // These should be promoted to a larger select which is supported.
119 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
120 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
122 // X86 wants to expand cmov itself.
123 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
124 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
125 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
126 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
127 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
128 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
129 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
130 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
131 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
132 // X86 ret instruction may pop stack.
133 setOperationAction(ISD::RET , MVT::Other, Custom);
135 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
138 // We don't have line number support yet.
139 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
140 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
141 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
144 // Set up the FP register classes.
145 addRegisterClass(MVT::f32, X86::V4F4RegisterClass);
146 addRegisterClass(MVT::f64, X86::V2F8RegisterClass);
148 // SSE has no load+extend ops
149 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
150 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
152 // SSE has no i16 to fp conversion, only i32
153 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
154 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
156 // Expand FP_TO_UINT into a select.
157 // FIXME: We would like to use a Custom expander here eventually to do
158 // the optimal thing for SSE vs. the default expansion in the legalizer.
159 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
161 // We don't support sin/cos/sqrt/fmod
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FABS , MVT::f64, Expand);
165 setOperationAction(ISD::FNEG , MVT::f64, Expand);
166 setOperationAction(ISD::FREM , MVT::f64, Expand);
167 setOperationAction(ISD::FSIN , MVT::f32, Expand);
168 setOperationAction(ISD::FCOS , MVT::f32, Expand);
169 setOperationAction(ISD::FABS , MVT::f32, Expand);
170 setOperationAction(ISD::FNEG , MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
173 addLegalFPImmediate(+0.0); // xorps / xorpd
175 // Set up the FP register classes.
176 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
179 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
180 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
183 addLegalFPImmediate(+0.0); // FLD0
184 addLegalFPImmediate(+1.0); // FLD1
185 addLegalFPImmediate(-0.0); // FLD0/FCHS
186 addLegalFPImmediate(-1.0); // FLD1/FCHS
188 computeRegisterProperties();
190 maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores
191 maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores
192 maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores
193 allowUnalignedMemoryAccesses = true; // x86 supports it!
196 std::vector<SDOperand>
197 X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
198 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
199 return LowerFastCCArguments(F, DAG);
200 return LowerCCCArguments(F, DAG);
203 std::pair<SDOperand, SDOperand>
204 X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
205 bool isVarArg, unsigned CallingConv,
207 SDOperand Callee, ArgListTy &Args,
209 assert((!isVarArg || CallingConv == CallingConv::C) &&
210 "Only C takes varargs!");
212 // If the callee is a GlobalAddress node (quite common, every direct call is)
213 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
214 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
215 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
217 if (CallingConv == CallingConv::Fast && EnableFastCC)
218 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
219 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
222 SDOperand X86TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
225 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
228 MVT::ValueType OpVT = Op.getValueType();
230 default: assert(0 && "Unknown type to return!");
232 Copy = DAG.getCopyToReg(Chain, X86::EAX, Op, SDOperand());
235 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
236 DAG.getConstant(1, MVT::i32));
237 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
238 DAG.getConstant(0, MVT::i32));
239 Copy = DAG.getCopyToReg(Chain, X86::EDX, Hi, SDOperand());
240 Copy = DAG.getCopyToReg(Copy, X86::EAX, Lo, Copy.getValue(1));
246 std::vector<MVT::ValueType> Tys;
247 Tys.push_back(MVT::Other);
248 Tys.push_back(MVT::Flag);
249 std::vector<SDOperand> Ops;
250 Ops.push_back(Chain);
251 if (OpVT == MVT::f32)
252 Op = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op);
254 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
256 // Spill the value to memory and reload it into top of stack.
257 unsigned Size = MVT::getSizeInBits(OpVT)/8;
258 MachineFunction &MF = DAG.getMachineFunction();
259 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
260 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
261 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Op,
262 StackSlot, DAG.getSrcValue(NULL));
263 std::vector<MVT::ValueType> Tys;
264 Tys.push_back(MVT::f64);
265 Tys.push_back(MVT::Other);
266 std::vector<SDOperand> Ops;
267 Ops.push_back(Chain);
268 Ops.push_back(StackSlot);
269 Ops.push_back(DAG.getValueType(OpVT));
270 Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
272 Tys.push_back(MVT::Other);
273 Tys.push_back(MVT::Flag);
275 Ops.push_back(Copy.getValue(1));
277 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
282 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
283 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
287 //===----------------------------------------------------------------------===//
288 // C Calling Convention implementation
289 //===----------------------------------------------------------------------===//
291 std::vector<SDOperand>
292 X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
293 std::vector<SDOperand> ArgValues;
295 MachineFunction &MF = DAG.getMachineFunction();
296 MachineFrameInfo *MFI = MF.getFrameInfo();
298 // Add DAG nodes to load the arguments... On entry to a function on the X86,
299 // the stack frame looks like this:
301 // [ESP] -- return address
302 // [ESP + 4] -- first argument (leftmost lexically)
303 // [ESP + 8] -- second argument, if first argument is four bytes in size
306 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
307 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
308 MVT::ValueType ObjectVT = getValueType(I->getType());
309 unsigned ArgIncrement = 4;
312 default: assert(0 && "Unhandled argument type!");
314 case MVT::i8: ObjSize = 1; break;
315 case MVT::i16: ObjSize = 2; break;
316 case MVT::i32: ObjSize = 4; break;
317 case MVT::i64: ObjSize = ArgIncrement = 8; break;
318 case MVT::f32: ObjSize = 4; break;
319 case MVT::f64: ObjSize = ArgIncrement = 8; break;
321 // Create the frame index object for this incoming parameter...
322 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
324 // Create the SelectionDAG nodes corresponding to a load from this parameter
325 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
327 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
331 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
332 DAG.getSrcValue(NULL));
334 if (MVT::isInteger(ObjectVT))
335 ArgValue = DAG.getConstant(0, ObjectVT);
337 ArgValue = DAG.getConstantFP(0, ObjectVT);
339 ArgValues.push_back(ArgValue);
341 ArgOffset += ArgIncrement; // Move on to the next argument...
344 // If the function takes variable number of arguments, make a frame index for
345 // the start of the first vararg value... for expansion of llvm.va_start.
347 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
348 ReturnAddrIndex = 0; // No return address slot generated yet.
349 BytesToPopOnReturn = 0; // Callee pops nothing.
350 BytesCallerReserves = ArgOffset;
352 // Finally, inform the code generator which regs we return values in.
353 switch (getValueType(F.getReturnType())) {
354 default: assert(0 && "Unknown type!");
355 case MVT::isVoid: break;
360 MF.addLiveOut(X86::EAX);
363 MF.addLiveOut(X86::EAX);
364 MF.addLiveOut(X86::EDX);
368 MF.addLiveOut(X86::ST0);
374 std::pair<SDOperand, SDOperand>
375 X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
376 bool isVarArg, bool isTailCall,
377 SDOperand Callee, ArgListTy &Args,
379 // Count how many bytes are to be pushed on the stack.
380 unsigned NumBytes = 0;
384 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
385 DAG.getConstant(0, getPointerTy()));
387 for (unsigned i = 0, e = Args.size(); i != e; ++i)
388 switch (getValueType(Args[i].second)) {
389 default: assert(0 && "Unknown value type!");
403 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
404 DAG.getConstant(NumBytes, getPointerTy()));
406 // Arguments go on the stack in reverse order, as specified by the ABI.
407 unsigned ArgOffset = 0;
408 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
410 std::vector<SDOperand> Stores;
412 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
413 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
414 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
416 switch (getValueType(Args[i].second)) {
417 default: assert(0 && "Unexpected ValueType for argument!");
421 // Promote the integer to 32 bits. If the input type is signed use a
422 // sign extend, otherwise use a zero extend.
423 if (Args[i].second->isSigned())
424 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
426 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
431 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
432 Args[i].first, PtrOff,
433 DAG.getSrcValue(NULL)));
438 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
439 Args[i].first, PtrOff,
440 DAG.getSrcValue(NULL)));
445 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
448 std::vector<MVT::ValueType> RetVals;
449 MVT::ValueType RetTyVT = getValueType(RetTy);
450 RetVals.push_back(MVT::Other);
452 // The result values produced have to be legal. Promote the result.
454 case MVT::isVoid: break;
456 RetVals.push_back(RetTyVT);
461 RetVals.push_back(MVT::i32);
465 RetVals.push_back(MVT::f32);
467 RetVals.push_back(MVT::f64);
470 RetVals.push_back(MVT::i32);
471 RetVals.push_back(MVT::i32);
476 std::vector<MVT::ValueType> NodeTys;
477 NodeTys.push_back(MVT::Other); // Returns a chain
478 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
480 std::vector<SDOperand> Ops;
481 Ops.push_back(Chain);
482 Ops.push_back(Callee);
484 // FIXME: Do not generate X86ISD::TAILCALL for now.
485 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
486 SDOperand InFlag = Chain.getValue(1);
489 if (RetTyVT != MVT::isVoid) {
491 default: assert(0 && "Unknown value type to return!");
494 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
495 Chain = RetVal.getValue(1);
498 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
499 Chain = RetVal.getValue(1);
502 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
503 Chain = RetVal.getValue(1);
506 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
507 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
509 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
510 Chain = Hi.getValue(1);
515 std::vector<MVT::ValueType> Tys;
516 Tys.push_back(MVT::f64);
517 Tys.push_back(MVT::Other);
518 std::vector<SDOperand> Ops;
519 Ops.push_back(Chain);
520 Ops.push_back(InFlag);
521 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
522 Chain = RetVal.getValue(1);
524 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
525 MachineFunction &MF = DAG.getMachineFunction();
526 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
527 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
529 Tys.push_back(MVT::Other);
531 Ops.push_back(Chain);
532 Ops.push_back(RetVal);
533 Ops.push_back(StackSlot);
534 Ops.push_back(DAG.getValueType(RetTyVT));
535 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
536 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
537 DAG.getSrcValue(NULL));
538 Chain = RetVal.getValue(1);
539 } else if (RetTyVT == MVT::f32)
540 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
546 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
547 DAG.getConstant(NumBytes, getPointerTy()),
548 DAG.getConstant(0, getPointerTy()));
549 return std::make_pair(RetVal, Chain);
551 std::vector<SDOperand> Ops;
552 Ops.push_back(Chain);
553 Ops.push_back(Callee);
554 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
555 Ops.push_back(DAG.getConstant(0, getPointerTy()));
557 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
562 case MVT::isVoid: break;
564 ResultVal = TheCall.getValue(1);
569 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
572 // FIXME: we would really like to remember that this FP_ROUND operation is
573 // okay to eliminate if we allow excess FP precision.
574 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
577 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
578 TheCall.getValue(2));
582 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
583 return std::make_pair(ResultVal, Chain);
588 X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
589 Value *VAListV, SelectionDAG &DAG) {
590 // vastart just stores the address of the VarArgsFrameIndex slot.
591 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
592 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
593 DAG.getSrcValue(VAListV));
597 std::pair<SDOperand,SDOperand>
598 X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP,
599 Value *VAListV, const Type *ArgTy,
601 MVT::ValueType ArgVT = getValueType(ArgTy);
602 SDOperand Val = DAG.getLoad(MVT::i32, Chain,
603 VAListP, DAG.getSrcValue(VAListV));
604 SDOperand Result = DAG.getLoad(ArgVT, Chain, Val,
605 DAG.getSrcValue(NULL));
607 if (ArgVT == MVT::i32)
610 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
611 "Other types should have been promoted for varargs!");
614 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
615 DAG.getConstant(Amt, Val.getValueType()));
616 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
617 Val, VAListP, DAG.getSrcValue(VAListV));
618 return std::make_pair(Result, Chain);
621 //===----------------------------------------------------------------------===//
622 // Fast Calling Convention implementation
623 //===----------------------------------------------------------------------===//
625 // The X86 'fast' calling convention passes up to two integer arguments in
626 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
627 // and requires that the callee pop its arguments off the stack (allowing proper
628 // tail calls), and has the same return value conventions as C calling convs.
630 // This calling convention always arranges for the callee pop value to be 8n+4
631 // bytes, which is needed for tail recursion elimination and stack alignment
634 // Note that this can be enhanced in the future to pass fp vals in registers
635 // (when we have a global fp allocator) and do other tricks.
638 /// AddLiveIn - This helper function adds the specified physical register to the
639 /// MachineFunction as a live in value. It also creates a corresponding virtual
641 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
642 TargetRegisterClass *RC) {
643 assert(RC->contains(PReg) && "Not the correct regclass!");
644 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
645 MF.addLiveIn(PReg, VReg);
650 std::vector<SDOperand>
651 X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
652 std::vector<SDOperand> ArgValues;
654 MachineFunction &MF = DAG.getMachineFunction();
655 MachineFrameInfo *MFI = MF.getFrameInfo();
657 // Add DAG nodes to load the arguments... On entry to a function the stack
658 // frame looks like this:
660 // [ESP] -- return address
661 // [ESP + 4] -- first nonreg argument (leftmost lexically)
662 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
664 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
666 // Keep track of the number of integer regs passed so far. This can be either
667 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
669 unsigned NumIntRegs = 0;
671 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
672 MVT::ValueType ObjectVT = getValueType(I->getType());
673 unsigned ArgIncrement = 4;
674 unsigned ObjSize = 0;
678 default: assert(0 && "Unhandled argument type!");
681 if (NumIntRegs < 2) {
682 if (!I->use_empty()) {
683 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
684 X86::R8RegisterClass);
685 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
686 DAG.setRoot(ArgValue.getValue(1));
687 if (ObjectVT == MVT::i1)
688 // FIXME: Should insert a assertzext here.
689 ArgValue = DAG.getNode(ISD::TRUNCATE, MVT::i1, ArgValue);
698 if (NumIntRegs < 2) {
699 if (!I->use_empty()) {
700 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
701 X86::R16RegisterClass);
702 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
703 DAG.setRoot(ArgValue.getValue(1));
711 if (NumIntRegs < 2) {
712 if (!I->use_empty()) {
713 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
714 X86::R32RegisterClass);
715 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
716 DAG.setRoot(ArgValue.getValue(1));
724 if (NumIntRegs == 0) {
725 if (!I->use_empty()) {
726 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
727 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
729 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
730 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
731 DAG.setRoot(Hi.getValue(1));
733 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
737 } else if (NumIntRegs == 1) {
738 if (!I->use_empty()) {
739 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
740 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
741 DAG.setRoot(Low.getValue(1));
743 // Load the high part from memory.
744 // Create the frame index object for this incoming parameter...
745 int FI = MFI->CreateFixedObject(4, ArgOffset);
746 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
747 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
748 DAG.getSrcValue(NULL));
749 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
755 ObjSize = ArgIncrement = 8;
757 case MVT::f32: ObjSize = 4; break;
758 case MVT::f64: ObjSize = ArgIncrement = 8; break;
761 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
763 if (ObjSize && !I->use_empty()) {
764 // Create the frame index object for this incoming parameter...
765 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
767 // Create the SelectionDAG nodes corresponding to a load from this
769 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
771 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
772 DAG.getSrcValue(NULL));
773 } else if (ArgValue.Val == 0) {
774 if (MVT::isInteger(ObjectVT))
775 ArgValue = DAG.getConstant(0, ObjectVT);
777 ArgValue = DAG.getConstantFP(0, ObjectVT);
779 ArgValues.push_back(ArgValue);
782 ArgOffset += ArgIncrement; // Move on to the next argument.
785 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
786 // arguments and the arguments after the retaddr has been pushed are aligned.
787 if ((ArgOffset & 7) == 0)
790 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
791 ReturnAddrIndex = 0; // No return address slot generated yet.
792 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
793 BytesCallerReserves = 0;
795 // Finally, inform the code generator which regs we return values in.
796 switch (getValueType(F.getReturnType())) {
797 default: assert(0 && "Unknown type!");
798 case MVT::isVoid: break;
803 MF.addLiveOut(X86::EAX);
806 MF.addLiveOut(X86::EAX);
807 MF.addLiveOut(X86::EDX);
811 MF.addLiveOut(X86::ST0);
817 std::pair<SDOperand, SDOperand>
818 X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
819 bool isTailCall, SDOperand Callee,
820 ArgListTy &Args, SelectionDAG &DAG) {
821 // Count how many bytes are to be pushed on the stack.
822 unsigned NumBytes = 0;
824 // Keep track of the number of integer regs passed so far. This can be either
825 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
827 unsigned NumIntRegs = 0;
829 for (unsigned i = 0, e = Args.size(); i != e; ++i)
830 switch (getValueType(Args[i].second)) {
831 default: assert(0 && "Unknown value type!");
836 if (NumIntRegs < 2) {
845 if (NumIntRegs == 0) {
848 } else if (NumIntRegs == 1) {
860 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
861 // arguments and the arguments after the retaddr has been pushed are aligned.
862 if ((NumBytes & 7) == 0)
865 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
866 DAG.getConstant(NumBytes, getPointerTy()));
868 // Arguments go on the stack in reverse order, as specified by the ABI.
869 unsigned ArgOffset = 0;
870 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
873 std::vector<SDOperand> Stores;
874 std::vector<SDOperand> RegValuesToPass;
875 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
876 switch (getValueType(Args[i].second)) {
877 default: assert(0 && "Unexpected ValueType for argument!");
879 Args[i].first = DAG.getNode(ISD::ANY_EXTEND, MVT::i8, Args[i].first);
884 if (NumIntRegs < 2) {
885 RegValuesToPass.push_back(Args[i].first);
891 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
892 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
893 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
894 Args[i].first, PtrOff,
895 DAG.getSrcValue(NULL)));
900 if (NumIntRegs < 2) { // Can pass part of it in regs?
901 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
902 Args[i].first, DAG.getConstant(1, MVT::i32));
903 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
904 Args[i].first, DAG.getConstant(0, MVT::i32));
905 RegValuesToPass.push_back(Lo);
907 if (NumIntRegs < 2) { // Pass both parts in regs?
908 RegValuesToPass.push_back(Hi);
911 // Pass the high part in memory.
912 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
913 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
914 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
915 Hi, PtrOff, DAG.getSrcValue(NULL)));
922 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
923 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
924 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
925 Args[i].first, PtrOff,
926 DAG.getSrcValue(NULL)));
932 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
934 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
935 // arguments and the arguments after the retaddr has been pushed are aligned.
936 if ((ArgOffset & 7) == 0)
939 std::vector<MVT::ValueType> RetVals;
940 MVT::ValueType RetTyVT = getValueType(RetTy);
942 RetVals.push_back(MVT::Other);
944 // The result values produced have to be legal. Promote the result.
946 case MVT::isVoid: break;
948 RetVals.push_back(RetTyVT);
953 RetVals.push_back(MVT::i32);
957 RetVals.push_back(MVT::f32);
959 RetVals.push_back(MVT::f64);
962 RetVals.push_back(MVT::i32);
963 RetVals.push_back(MVT::i32);
968 // Build a sequence of copy-to-reg nodes chained together with token chain
969 // and flag operands which copy the outgoing args into registers.
971 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
973 SDOperand RegToPass = RegValuesToPass[i];
974 switch (RegToPass.getValueType()) {
975 default: assert(0 && "Bad thing to pass in regs");
977 CCReg = (i == 0) ? X86::AL : X86::DL;
980 CCReg = (i == 0) ? X86::AX : X86::DX;
983 CCReg = (i == 0) ? X86::EAX : X86::EDX;
987 Chain = DAG.getCopyToReg(Chain, CCReg, RegToPass, InFlag);
988 InFlag = Chain.getValue(1);
991 std::vector<MVT::ValueType> NodeTys;
992 NodeTys.push_back(MVT::Other); // Returns a chain
993 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
995 std::vector<SDOperand> Ops;
996 Ops.push_back(Chain);
997 Ops.push_back(Callee);
999 Ops.push_back(InFlag);
1001 // FIXME: Do not generate X86ISD::TAILCALL for now.
1002 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
1003 InFlag = Chain.getValue(1);
1006 if (RetTyVT != MVT::isVoid) {
1008 default: assert(0 && "Unknown value type to return!");
1011 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
1012 Chain = RetVal.getValue(1);
1015 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
1016 Chain = RetVal.getValue(1);
1019 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
1020 Chain = RetVal.getValue(1);
1023 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
1024 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
1026 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
1027 Chain = Hi.getValue(1);
1032 std::vector<MVT::ValueType> Tys;
1033 Tys.push_back(MVT::f64);
1034 Tys.push_back(MVT::Other);
1035 std::vector<SDOperand> Ops;
1036 Ops.push_back(Chain);
1037 Ops.push_back(InFlag);
1038 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
1039 Chain = RetVal.getValue(1);
1041 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
1042 MachineFunction &MF = DAG.getMachineFunction();
1043 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
1044 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1046 Tys.push_back(MVT::Other);
1048 Ops.push_back(Chain);
1049 Ops.push_back(RetVal);
1050 Ops.push_back(StackSlot);
1051 Ops.push_back(DAG.getValueType(RetTyVT));
1052 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
1053 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
1054 DAG.getSrcValue(NULL));
1055 Chain = RetVal.getValue(1);
1056 } else if (RetTyVT == MVT::f32)
1057 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
1063 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1064 DAG.getConstant(ArgOffset, getPointerTy()),
1065 DAG.getConstant(ArgOffset, getPointerTy()));
1066 return std::make_pair(RetVal, Chain);
1068 std::vector<SDOperand> Ops;
1069 Ops.push_back(Chain);
1070 Ops.push_back(Callee);
1071 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
1072 // Callee pops all arg values on the stack.
1073 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
1075 // Pass register arguments as needed.
1076 Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end());
1078 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1080 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
1082 SDOperand ResultVal;
1084 case MVT::isVoid: break;
1086 ResultVal = TheCall.getValue(1);
1091 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
1094 // FIXME: we would really like to remember that this FP_ROUND operation is
1095 // okay to eliminate if we allow excess FP precision.
1096 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
1099 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
1100 TheCall.getValue(2));
1104 return std::make_pair(ResultVal, Chain);
1108 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1109 if (ReturnAddrIndex == 0) {
1110 // Set up a frame object for the return address.
1111 MachineFunction &MF = DAG.getMachineFunction();
1112 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1115 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
1120 std::pair<SDOperand, SDOperand> X86TargetLowering::
1121 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
1122 SelectionDAG &DAG) {
1124 if (Depth) // Depths > 0 not supported yet!
1125 Result = DAG.getConstant(0, getPointerTy());
1127 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
1128 if (!isFrameAddress)
1129 // Just load the return address
1130 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
1131 DAG.getSrcValue(NULL));
1133 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
1134 DAG.getConstant(4, MVT::i32));
1136 return std::make_pair(Result, Chain);
1139 //===----------------------------------------------------------------------===//
1140 // X86 Custom Lowering Hooks
1141 //===----------------------------------------------------------------------===//
1143 /// SetCCToX86CondCode - do a one to one translation of a ISD::CondCode to
1144 /// X86 specific CondCode. It returns a X86ISD::COND_INVALID if it cannot
1145 /// do a direct translation.
1146 static unsigned CCToX86CondCode(SDOperand CC, bool isFP) {
1147 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
1148 unsigned X86CC = X86ISD::COND_INVALID;
1150 switch (SetCCOpcode) {
1152 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1153 case ISD::SETGT: X86CC = X86ISD::COND_G; break;
1154 case ISD::SETGE: X86CC = X86ISD::COND_GE; break;
1155 case ISD::SETLT: X86CC = X86ISD::COND_L; break;
1156 case ISD::SETLE: X86CC = X86ISD::COND_LE; break;
1157 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1158 case ISD::SETULT: X86CC = X86ISD::COND_B; break;
1159 case ISD::SETUGT: X86CC = X86ISD::COND_A; break;
1160 case ISD::SETULE: X86CC = X86ISD::COND_BE; break;
1161 case ISD::SETUGE: X86CC = X86ISD::COND_AE; break;
1164 // On a floating point condition, the flags are set as follows:
1166 // 0 | 0 | 0 | X > Y
1167 // 0 | 0 | 1 | X < Y
1168 // 1 | 0 | 0 | X == Y
1169 // 1 | 1 | 1 | unordered
1170 switch (SetCCOpcode) {
1173 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1175 case ISD::SETGT: X86CC = X86ISD::COND_A; break;
1177 case ISD::SETGE: X86CC = X86ISD::COND_AE; break;
1179 case ISD::SETLT: X86CC = X86ISD::COND_B; break;
1181 case ISD::SETLE: X86CC = X86ISD::COND_BE; break;
1183 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1184 case ISD::SETUO: X86CC = X86ISD::COND_P; break;
1185 case ISD::SETO: X86CC = X86ISD::COND_NP; break;
1191 /// LowerOperation - Provide custom lowering hooks for some operations.
1193 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1194 switch (Op.getOpcode()) {
1195 default: assert(0 && "Should not custom lower this!");
1196 case ISD::SINT_TO_FP: {
1197 assert(Op.getValueType() == MVT::f64 &&
1198 Op.getOperand(0).getValueType() == MVT::i64 &&
1199 "Unknown SINT_TO_FP to lower!");
1200 // We lower sint64->FP into a store to a temporary stack slot, followed by a
1202 MachineFunction &MF = DAG.getMachineFunction();
1203 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
1204 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1205 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
1206 Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL));
1207 std::vector<MVT::ValueType> RTs;
1208 RTs.push_back(MVT::f64);
1209 RTs.push_back(MVT::Other);
1210 std::vector<SDOperand> Ops;
1211 Ops.push_back(Store);
1212 Ops.push_back(StackSlot);
1213 return DAG.getNode(X86ISD::FILD64m, RTs, Ops);
1215 case ISD::FP_TO_SINT: {
1216 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
1217 Op.getOperand(0).getValueType() == MVT::f64 &&
1218 "Unknown FP_TO_SINT to lower!");
1219 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
1221 MachineFunction &MF = DAG.getMachineFunction();
1222 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
1223 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
1224 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1227 switch (Op.getValueType()) {
1228 default: assert(0 && "Invalid FP_TO_SINT to lower!");
1229 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
1230 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
1231 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
1234 // Build the FP_TO_INT*_IN_MEM
1235 std::vector<SDOperand> Ops;
1236 Ops.push_back(DAG.getEntryNode());
1237 Ops.push_back(Op.getOperand(0));
1238 Ops.push_back(StackSlot);
1239 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
1242 return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
1243 DAG.getSrcValue(NULL));
1245 case ISD::READCYCLECOUNTER: {
1246 std::vector<MVT::ValueType> Tys;
1247 Tys.push_back(MVT::Other);
1248 Tys.push_back(MVT::Flag);
1249 std::vector<SDOperand> Ops;
1250 Ops.push_back(Op.getOperand(0));
1251 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops);
1253 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
1254 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
1255 MVT::i32, Ops[0].getValue(2)));
1256 Ops.push_back(Ops[1].getValue(1));
1257 Tys[0] = Tys[1] = MVT::i32;
1258 Tys.push_back(MVT::Other);
1259 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1262 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
1263 SDOperand CC = Op.getOperand(2);
1264 SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1265 Op.getOperand(0), Op.getOperand(1));
1266 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
1267 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
1268 unsigned X86CC = CCToX86CondCode(CC, isFP);
1269 if (X86CC != X86ISD::COND_INVALID) {
1270 return DAG.getNode(X86ISD::SETCC, MVT::i8,
1271 DAG.getConstant(X86CC, MVT::i8), Cond);
1273 assert(isFP && "Illegal integer SetCC!");
1275 std::vector<MVT::ValueType> Tys;
1276 std::vector<SDOperand> Ops;
1277 switch (SetCCOpcode) {
1278 default: assert(false && "Illegal floating point SetCC!");
1279 case ISD::SETOEQ: { // !PF & ZF
1280 Tys.push_back(MVT::i8);
1281 Tys.push_back(MVT::Flag);
1282 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1283 Ops.push_back(Cond);
1284 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1285 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1286 DAG.getConstant(X86ISD::COND_E, MVT::i8),
1288 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1290 case ISD::SETOLT: { // !PF & CF
1291 Tys.push_back(MVT::i8);
1292 Tys.push_back(MVT::Flag);
1293 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1294 Ops.push_back(Cond);
1295 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1296 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1297 DAG.getConstant(X86ISD::COND_B, MVT::i8),
1299 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1301 case ISD::SETOLE: { // !PF & (CF || ZF)
1302 Tys.push_back(MVT::i8);
1303 Tys.push_back(MVT::Flag);
1304 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1305 Ops.push_back(Cond);
1306 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1307 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1308 DAG.getConstant(X86ISD::COND_BE, MVT::i8),
1310 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1312 case ISD::SETUGT: { // PF | (!ZF & !CF)
1313 Tys.push_back(MVT::i8);
1314 Tys.push_back(MVT::Flag);
1315 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1316 Ops.push_back(Cond);
1317 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1318 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1319 DAG.getConstant(X86ISD::COND_A, MVT::i8),
1321 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1323 case ISD::SETUGE: { // PF | !CF
1324 Tys.push_back(MVT::i8);
1325 Tys.push_back(MVT::Flag);
1326 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1327 Ops.push_back(Cond);
1328 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1329 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1330 DAG.getConstant(X86ISD::COND_AE, MVT::i8),
1332 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1334 case ISD::SETUNE: { // PF | !ZF
1335 Tys.push_back(MVT::i8);
1336 Tys.push_back(MVT::Flag);
1337 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1338 Ops.push_back(Cond);
1339 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1340 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1341 DAG.getConstant(X86ISD::COND_NE, MVT::i8),
1343 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1349 SDOperand Cond = Op.getOperand(0);
1351 if (Cond.getOpcode() == X86ISD::SETCC) {
1352 CC = Cond.getOperand(0);
1353 Cond = Cond.getOperand(1);
1354 } else if (Cond.getOpcode() == ISD::SETCC) {
1355 CC = Cond.getOperand(2);
1356 bool isFP = MVT::isFloatingPoint(Cond.getOperand(1).getValueType());
1357 unsigned X86CC = CCToX86CondCode(CC, isFP);
1358 CC = DAG.getConstant(X86CC, MVT::i8);
1359 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1360 Cond.getOperand(0), Cond.getOperand(1));
1362 CC = DAG.getConstant(X86ISD::COND_E, MVT::i8);
1363 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1365 return DAG.getNode(X86ISD::CMOV, Op.getValueType(),
1366 Op.getOperand(1), Op.getOperand(2), CC, Cond);
1369 SDOperand Cond = Op.getOperand(1);
1370 SDOperand Dest = Op.getOperand(2);
1372 // TODO: handle Cond == OR / AND / XOR
1373 if (Cond.getOpcode() == X86ISD::SETCC) {
1374 CC = Cond.getOperand(0);
1375 Cond = Cond.getOperand(1);
1376 } else if (Cond.getOpcode() == ISD::SETCC) {
1377 CC = Cond.getOperand(2);
1378 bool isFP = MVT::isFloatingPoint(Cond.getOperand(1).getValueType());
1379 unsigned X86CC = CCToX86CondCode(CC, isFP);
1380 CC = DAG.getConstant(X86CC, MVT::i8);
1381 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1382 Cond.getOperand(0), Cond.getOperand(1));
1384 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1385 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1387 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
1388 Op.getOperand(0), Op.getOperand(2), CC, Cond);
1391 // Can only be return void.
1392 return DAG.getNode(X86ISD::RET, MVT::Other, Op.getOperand(0),
1393 DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
1395 case ISD::GlobalAddress: {
1396 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1397 SDOperand GVOp = DAG.getTargetGlobalAddress(GV, getPointerTy());
1398 // For Darwin, external and weak symbols are indirect, so we want to load
1399 // the value at address GV, not the value of GV itself. This means that
1400 // the GlobalAddress must be in the base or index register of the address,
1401 // not the GV offset field.
1402 if (getTargetMachine().
1403 getSubtarget<X86Subtarget>().getIndirectExternAndWeakGlobals() &&
1404 (GV->hasWeakLinkage() || GV->isExternal()))
1405 return DAG.getLoad(MVT::i32, DAG.getEntryNode(),
1406 GVOp, DAG.getSrcValue(NULL));
1414 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
1416 default: return NULL;
1417 case X86ISD::FILD64m: return "X86ISD::FILD64m";
1418 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
1419 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
1420 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
1421 case X86ISD::FLD: return "X86ISD::FLD";
1422 case X86ISD::FST: return "X86ISD::FST";
1423 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
1424 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
1425 case X86ISD::CALL: return "X86ISD::CALL";
1426 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
1427 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
1428 case X86ISD::CMP: return "X86ISD::CMP";
1429 case X86ISD::TEST: return "X86ISD::TEST";
1430 case X86ISD::SETCC: return "X86ISD::SETCC";
1431 case X86ISD::CMOV: return "X86ISD::CMOV";
1432 case X86ISD::BRCOND: return "X86ISD::BRCOND";
1433 case X86ISD::RET: return "X86ISD::RET";
1434 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
1438 bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
1439 uint64_t Mask) const {
1441 unsigned Opc = Op.getOpcode();
1445 assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node");
1447 case X86ISD::SETCC: return (Mask & 1) == 0;