1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/ADT/VectorExtras.h"
26 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/SSARegMap.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/ADT/StringExtras.h"
39 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
40 cl::desc("Enable fastcc on X86"));
41 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
42 : TargetLowering(TM) {
43 Subtarget = &TM.getSubtarget<X86Subtarget>();
44 X86ScalarSSE = Subtarget->hasSSE2();
45 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
47 // Set up the TargetLowering object.
49 // X86 is weird, it always uses i8 for shift amounts and setcc results.
50 setShiftAmountType(MVT::i8);
51 setSetCCResultType(MVT::i8);
52 setSetCCResultContents(ZeroOrOneSetCCResult);
53 setSchedulingPreference(SchedulingForRegPressure);
54 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
55 setStackPointerRegisterToSaveRestore(X86StackPtr);
57 if (Subtarget->isTargetDarwin()) {
58 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
59 setUseUnderscoreSetJmp(false);
60 setUseUnderscoreLongJmp(false);
61 } else if (Subtarget->isTargetMingw()) {
62 // MS runtime is weird: it exports _setjmp, but longjmp!
63 setUseUnderscoreSetJmp(true);
64 setUseUnderscoreLongJmp(false);
66 setUseUnderscoreSetJmp(true);
67 setUseUnderscoreLongJmp(true);
70 // Add legal addressing mode scale values.
71 addLegalAddressScale(8);
72 addLegalAddressScale(4);
73 addLegalAddressScale(2);
74 // Enter the ones which require both scale + index last. These are more
76 addLegalAddressScale(9);
77 addLegalAddressScale(5);
78 addLegalAddressScale(3);
80 // Set up the register classes.
81 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
82 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
83 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
84 if (Subtarget->is64Bit())
85 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
87 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
89 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
91 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
92 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
93 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
95 if (Subtarget->is64Bit()) {
96 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
97 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
100 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
101 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
103 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
106 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
108 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
109 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
110 // SSE has no i16 to fp conversion, only i32
112 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
114 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
115 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
118 if (!Subtarget->is64Bit()) {
119 // Custom lower SINT_TO_FP and FP_TO_SINT from/to i64 in 32-bit mode.
120 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
121 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
124 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
126 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
127 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
130 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
132 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
133 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
136 // Handle FP_TO_UINT by promoting the destination to a larger signed
138 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
139 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
140 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
142 if (Subtarget->is64Bit()) {
143 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
144 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
146 if (X86ScalarSSE && !Subtarget->hasSSE3())
147 // Expand FP_TO_UINT into a select.
148 // FIXME: We would like to use a Custom expander here eventually to do
149 // the optimal thing for SSE vs. the default expansion in the legalizer.
150 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
152 // With SSE3 we can use fisttpll to convert to a signed i64.
153 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
156 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
158 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
159 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
162 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
163 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
164 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
165 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
166 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
167 if (Subtarget->is64Bit())
168 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
169 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
170 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
171 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
172 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
173 setOperationAction(ISD::FREM , MVT::f64 , Expand);
175 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
176 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
177 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
178 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
179 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
180 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
181 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
182 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
183 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
184 if (Subtarget->is64Bit()) {
185 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
186 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
187 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
190 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
191 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
193 // These should be promoted to a larger select which is supported.
194 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
195 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
196 // X86 wants to expand cmov itself.
197 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
198 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
199 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
200 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
201 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
202 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
203 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
204 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
205 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
206 if (Subtarget->is64Bit()) {
207 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
208 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
210 // X86 ret instruction may pop stack.
211 setOperationAction(ISD::RET , MVT::Other, Custom);
213 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
214 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
215 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
216 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
217 if (Subtarget->is64Bit()) {
218 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
219 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
220 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
221 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
223 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
224 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
225 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
226 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
227 // X86 wants to expand memset / memcpy itself.
228 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
229 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
231 // We don't have line number support yet.
232 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
233 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
234 // FIXME - use subtarget debug flags
235 if (!Subtarget->isTargetDarwin() &&
236 !Subtarget->isTargetELF() &&
237 !Subtarget->isTargetCygMing())
238 setOperationAction(ISD::LABEL, MVT::Other, Expand);
240 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
241 setOperationAction(ISD::VASTART , MVT::Other, Custom);
243 // Use the default implementation.
244 setOperationAction(ISD::VAARG , MVT::Other, Expand);
245 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
246 setOperationAction(ISD::VAEND , MVT::Other, Expand);
247 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
248 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
249 if (Subtarget->is64Bit())
250 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
251 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
254 // Set up the FP register classes.
255 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
256 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
258 // Use ANDPD to simulate FABS.
259 setOperationAction(ISD::FABS , MVT::f64, Custom);
260 setOperationAction(ISD::FABS , MVT::f32, Custom);
262 // Use XORP to simulate FNEG.
263 setOperationAction(ISD::FNEG , MVT::f64, Custom);
264 setOperationAction(ISD::FNEG , MVT::f32, Custom);
266 // Use ANDPD and ORPD to simulate FCOPYSIGN.
267 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
268 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
270 // We don't support sin/cos/fmod
271 setOperationAction(ISD::FSIN , MVT::f64, Expand);
272 setOperationAction(ISD::FCOS , MVT::f64, Expand);
273 setOperationAction(ISD::FREM , MVT::f64, Expand);
274 setOperationAction(ISD::FSIN , MVT::f32, Expand);
275 setOperationAction(ISD::FCOS , MVT::f32, Expand);
276 setOperationAction(ISD::FREM , MVT::f32, Expand);
278 // Expand FP immediates into loads from the stack, except for the special
280 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
281 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
282 addLegalFPImmediate(+0.0); // xorps / xorpd
284 // Set up the FP register classes.
285 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
287 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
288 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
289 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
292 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
293 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
296 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
297 addLegalFPImmediate(+0.0); // FLD0
298 addLegalFPImmediate(+1.0); // FLD1
299 addLegalFPImmediate(-0.0); // FLD0/FCHS
300 addLegalFPImmediate(-1.0); // FLD1/FCHS
303 // First set operation action for all vector types to expand. Then we
304 // will selectively turn on ones that can be effectively codegen'd.
305 for (unsigned VT = (unsigned)MVT::Vector + 1;
306 VT != (unsigned)MVT::LAST_VALUETYPE; VT++) {
307 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
308 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
309 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
310 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
311 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
312 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
313 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
314 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
315 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
316 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
317 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
318 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
319 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
320 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
321 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
324 if (Subtarget->hasMMX()) {
325 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
326 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
327 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
329 // FIXME: add MMX packed arithmetics
330 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
331 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
332 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
335 if (Subtarget->hasSSE1()) {
336 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
338 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
339 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
340 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
341 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
342 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
343 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
344 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
345 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
346 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
349 if (Subtarget->hasSSE2()) {
350 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
351 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
352 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
353 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
354 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
356 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
357 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
358 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
359 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
360 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
361 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
362 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
363 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
364 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
365 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
366 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
368 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
369 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
370 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
371 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
372 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
373 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
375 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
376 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
377 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
378 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
379 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
381 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
382 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
383 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
384 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
385 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
386 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
388 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
389 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
390 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
391 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
392 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
393 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
394 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
395 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
396 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
397 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
398 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
399 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
402 // Custom lower v2i64 and v2f64 selects.
403 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
404 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
405 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
406 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
409 // We want to custom lower some of our intrinsics.
410 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
412 // We have target-specific dag combine patterns for the following nodes:
413 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
414 setTargetDAGCombine(ISD::SELECT);
416 computeRegisterProperties();
418 // FIXME: These should be based on subtarget info. Plus, the values should
419 // be smaller when we are in optimizing for size mode.
420 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
421 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
422 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
423 allowUnalignedMemoryAccesses = true; // x86 supports it!
427 //===----------------------------------------------------------------------===//
428 // Return Value Calling Convention Implementation
429 //===----------------------------------------------------------------------===//
431 /// GetRetValueLocs - If we are returning a set of values with the specified
432 /// value types, determine the set of registers each one will land in. This
433 /// sets one element of the ResultRegs array for each element in the VTs array.
434 static void GetRetValueLocs(const MVT::ValueType *VTs, unsigned NumVTs,
435 unsigned *ResultRegs,
436 const X86Subtarget *Subtarget,
438 if (NumVTs == 0) return;
441 ResultRegs[0] = VTs[0] == MVT::i64 ? X86::RAX : X86::EAX;
442 ResultRegs[1] = VTs[1] == MVT::i64 ? X86::RDX : X86::EDX;
446 // Otherwise, NumVTs is 1.
447 MVT::ValueType ArgVT = VTs[0];
451 case MVT::i8: Reg = X86::AL; break;
452 case MVT::i16: Reg = X86::AX; break;
453 case MVT::i32: Reg = X86::EAX; break;
454 case MVT::i64: Reg = X86::RAX; break;
457 if (Subtarget->is64Bit())
458 Reg = X86::XMM0; // FP values in X86-64 go in XMM0.
459 else if (CC == CallingConv::Fast && Subtarget->hasSSE2())
460 Reg = X86::XMM0; // FP values in X86-32 with fastcc go in XMM0.
462 Reg = X86::ST0; // FP values in X86-32 go in ST0.
465 assert(MVT::isVector(ArgVT) && "Unknown return value type!");
466 Reg = X86::XMM0; // Int/FP vector result -> XMM0.
472 /// LowerRET - Lower an ISD::RET node.
473 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
474 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
476 // Support up returning up to two registers.
477 MVT::ValueType VTs[2];
478 unsigned DestRegs[2];
479 unsigned NumRegs = Op.getNumOperands() / 2;
480 assert(NumRegs <= 2 && "Can only return up to two regs!");
482 for (unsigned i = 0; i != NumRegs; ++i)
483 VTs[i] = Op.getOperand(i*2+1).getValueType();
485 // Determine which register each value should be copied into.
486 GetRetValueLocs(VTs, NumRegs, DestRegs, Subtarget,
487 DAG.getMachineFunction().getFunction()->getCallingConv());
489 // If this is the first return lowered for this function, add the regs to the
490 // liveout set for the function.
491 if (DAG.getMachineFunction().liveout_empty()) {
492 for (unsigned i = 0; i != NumRegs; ++i)
493 DAG.getMachineFunction().addLiveOut(DestRegs[i]);
496 SDOperand Chain = Op.getOperand(0);
499 // Copy the result values into the output registers.
500 if (NumRegs != 1 || DestRegs[0] != X86::ST0) {
501 for (unsigned i = 0; i != NumRegs; ++i) {
502 Chain = DAG.getCopyToReg(Chain, DestRegs[i], Op.getOperand(i*2+1), Flag);
503 Flag = Chain.getValue(1);
506 // We need to handle a destination of ST0 specially, because it isn't really
508 SDOperand Value = Op.getOperand(1);
510 // If this is an FP return with ScalarSSE, we need to move the value from
511 // an XMM register onto the fp-stack.
515 // If this is a load into a scalarsse value, don't store the loaded value
516 // back to the stack, only to reload it: just replace the scalar-sse load.
517 if (ISD::isNON_EXTLoad(Value.Val) &&
518 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
519 Chain = Value.getOperand(0);
520 MemLoc = Value.getOperand(1);
522 // Spill the value to memory and reload it into top of stack.
523 unsigned Size = MVT::getSizeInBits(VTs[0])/8;
524 MachineFunction &MF = DAG.getMachineFunction();
525 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
526 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
527 Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0);
529 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other);
530 SDOperand Ops[] = { Chain, MemLoc, DAG.getValueType(VTs[0]) };
531 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
532 Chain = Value.getValue(1);
535 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
536 SDOperand Ops[] = { Chain, Value };
537 Chain = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
538 Flag = Chain.getValue(1);
541 SDOperand BytesToPop = DAG.getConstant(getBytesToPopOnReturn(), MVT::i16);
543 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop, Flag);
545 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop);
549 /// LowerCallResult - Lower the result values of an ISD::CALL into the
550 /// appropriate copies out of appropriate physical registers. This assumes that
551 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
552 /// being lowered. The returns a SDNode with the same number of values as the
554 SDNode *X86TargetLowering::
555 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
556 unsigned CallingConv, SelectionDAG &DAG) {
557 SmallVector<SDOperand, 8> ResultVals;
559 // We support returning up to two registers.
560 MVT::ValueType VTs[2];
561 unsigned DestRegs[2];
562 unsigned NumRegs = TheCall->getNumValues() - 1;
563 assert(NumRegs <= 2 && "Can only return up to two regs!");
565 for (unsigned i = 0; i != NumRegs; ++i)
566 VTs[i] = TheCall->getValueType(i);
568 // Determine which register each value should be copied into.
569 GetRetValueLocs(VTs, NumRegs, DestRegs, Subtarget, CallingConv);
571 // Copy all of the result registers out of their specified physreg.
572 if (NumRegs != 1 || DestRegs[0] != X86::ST0) {
573 for (unsigned i = 0; i != NumRegs; ++i) {
574 Chain = DAG.getCopyFromReg(Chain, DestRegs[i], VTs[i],
576 InFlag = Chain.getValue(2);
577 ResultVals.push_back(Chain.getValue(0));
580 // Copies from the FP stack are special, as ST0 isn't a valid register
581 // before the fp stackifier runs.
583 // Copy ST0 into an RFP register with FP_GET_RESULT.
584 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
585 SDOperand GROps[] = { Chain, InFlag };
586 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2);
587 Chain = RetVal.getValue(1);
588 InFlag = RetVal.getValue(2);
590 // If we are using ScalarSSE, store ST(0) to the stack and reload it into
593 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
594 // shouldn't be necessary except that RFP cannot be live across
595 // multiple blocks. When stackifier is fixed, they can be uncoupled.
596 MachineFunction &MF = DAG.getMachineFunction();
597 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
598 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
600 Chain, RetVal, StackSlot, DAG.getValueType(VTs[0]), InFlag
602 Chain = DAG.getNode(X86ISD::FST, MVT::Other, Ops, 5);
603 RetVal = DAG.getLoad(VTs[0], Chain, StackSlot, NULL, 0);
604 Chain = RetVal.getValue(1);
607 if (VTs[0] == MVT::f32 && !X86ScalarSSE)
608 // FIXME: we would really like to remember that this FP_ROUND
609 // operation is okay to eliminate if we allow excess FP precision.
610 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
611 ResultVals.push_back(RetVal);
614 // Merge everything together with a MERGE_VALUES node.
615 ResultVals.push_back(Chain);
616 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
617 &ResultVals[0], ResultVals.size()).Val;
621 //===----------------------------------------------------------------------===//
622 // C & StdCall Calling Convention implementation
623 //===----------------------------------------------------------------------===//
624 // StdCall calling convention seems to be standard for many Windows' API
625 // routines and around. It differs from C calling convention just a little:
626 // callee should clean up the stack, not caller. Symbols should be also
627 // decorated in some fancy way :) It doesn't support any vector arguments.
629 /// AddLiveIn - This helper function adds the specified physical register to the
630 /// MachineFunction as a live in value. It also creates a corresponding virtual
632 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
633 const TargetRegisterClass *RC) {
634 assert(RC->contains(PReg) && "Not the correct regclass!");
635 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
636 MF.addLiveIn(PReg, VReg);
640 /// HowToPassArgument - Returns how an formal argument of the specified type
641 /// should be passed. If it is through stack, returns the size of the stack
642 /// slot; if it is through integer or XMM register, returns the number of
643 /// integer or XMM registers are needed.
645 HowToPassCallArgument(MVT::ValueType ObjectVT,
647 unsigned NumIntRegs, unsigned NumXMMRegs,
648 unsigned MaxNumIntRegs,
649 unsigned &ObjSize, unsigned &ObjIntRegs,
650 unsigned &ObjXMMRegs) {
655 if (MaxNumIntRegs>3) {
656 // We don't have too much registers on ia32! :)
661 default: assert(0 && "Unhandled argument type!");
663 if (ArgInReg && (NumIntRegs < MaxNumIntRegs))
669 if (ArgInReg && (NumIntRegs < MaxNumIntRegs))
675 if (ArgInReg && (NumIntRegs < MaxNumIntRegs))
681 if (ArgInReg && (NumIntRegs+2 <= MaxNumIntRegs)) {
683 } else if (ArgInReg && (NumIntRegs+1 <= MaxNumIntRegs)) {
708 SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
710 unsigned NumArgs = Op.Val->getNumValues() - 1;
711 MachineFunction &MF = DAG.getMachineFunction();
712 MachineFrameInfo *MFI = MF.getFrameInfo();
713 SDOperand Root = Op.getOperand(0);
714 SmallVector<SDOperand, 8> ArgValues;
715 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
717 // Add DAG nodes to load the arguments... On entry to a function on the X86,
718 // the stack frame looks like this:
720 // [ESP] -- return address
721 // [ESP + 4] -- first argument (leftmost lexically)
722 // [ESP + 8] -- second argument, if first argument is <= 4 bytes in size
725 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
726 unsigned NumSRetBytes= 0; // How much bytes on stack used for struct return
727 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
728 unsigned NumIntRegs = 0; // Integer regs used for parameter passing
730 static const unsigned XMMArgRegs[] = {
731 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
733 static const unsigned GPRArgRegs[][3] = {
734 { X86::AL, X86::DL, X86::CL },
735 { X86::AX, X86::DX, X86::CX },
736 { X86::EAX, X86::EDX, X86::ECX }
738 static const TargetRegisterClass* GPRClasses[3] = {
739 X86::GR8RegisterClass, X86::GR16RegisterClass, X86::GR32RegisterClass
742 // Handle regparm attribute
743 SmallVector<bool, 8> ArgInRegs(NumArgs, false);
744 SmallVector<bool, 8> SRetArgs(NumArgs, false);
746 for (unsigned i = 0; i<NumArgs; ++i) {
747 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(3+i))->getValue();
748 ArgInRegs[i] = (Flags >> 1) & 1;
749 SRetArgs[i] = (Flags >> 2) & 1;
753 for (unsigned i = 0; i < NumArgs; ++i) {
754 MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
755 unsigned ArgIncrement = 4;
756 unsigned ObjSize = 0;
757 unsigned ObjXMMRegs = 0;
758 unsigned ObjIntRegs = 0;
762 HowToPassCallArgument(ObjectVT,
764 NumIntRegs, NumXMMRegs, 3,
765 ObjSize, ObjIntRegs, ObjXMMRegs);
768 ArgIncrement = ObjSize;
770 if (ObjIntRegs || ObjXMMRegs) {
772 default: assert(0 && "Unhandled argument type!");
776 unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][NumIntRegs];
777 Reg = AddLiveIn(MF, RegToUse, GPRClasses[ObjectVT-MVT::i8]);
778 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
787 assert(!isStdCall && "Unhandled argument type!");
788 Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass);
789 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
792 NumIntRegs += ObjIntRegs;
793 NumXMMRegs += ObjXMMRegs;
796 // XMM arguments have to be aligned on 16-byte boundary.
798 ArgOffset = ((ArgOffset + 15) / 16) * 16;
799 // Create the SelectionDAG nodes corresponding to a load from this
801 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
802 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
803 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
805 ArgOffset += ArgIncrement; // Move on to the next argument.
807 NumSRetBytes += ArgIncrement;
810 ArgValues.push_back(ArgValue);
813 ArgValues.push_back(Root);
815 // If the function takes variable number of arguments, make a frame index for
816 // the start of the first vararg value... for expansion of llvm.va_start.
818 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
820 if (isStdCall && !isVarArg) {
821 BytesToPopOnReturn = ArgOffset; // Callee pops everything..
822 BytesCallerReserves = 0;
824 BytesToPopOnReturn = NumSRetBytes; // Callee pops hidden struct pointer.
825 BytesCallerReserves = ArgOffset;
828 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
829 ReturnAddrIndex = 0; // No return address slot generated yet.
832 MF.getInfo<X86FunctionInfo>()->setBytesToPopOnReturn(BytesToPopOnReturn);
834 // Return the new list of results.
835 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
836 &ArgValues[0], ArgValues.size());
839 SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG,
841 SDOperand Chain = Op.getOperand(0);
842 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
843 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
844 SDOperand Callee = Op.getOperand(4);
845 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
847 static const unsigned XMMArgRegs[] = {
848 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
850 static const unsigned GPR32ArgRegs[] = {
851 X86::EAX, X86::EDX, X86::ECX
854 // Count how many bytes are to be pushed on the stack.
855 unsigned NumBytes = 0;
856 // Keep track of the number of integer regs passed so far.
857 unsigned NumIntRegs = 0;
858 // Keep track of the number of XMM regs passed so far.
859 unsigned NumXMMRegs = 0;
860 // How much bytes on stack used for struct return
861 unsigned NumSRetBytes= 0;
863 // Handle regparm attribute
864 SmallVector<bool, 8> ArgInRegs(NumOps, false);
865 SmallVector<bool, 8> SRetArgs(NumOps, false);
866 for (unsigned i = 0; i<NumOps; ++i) {
868 dyn_cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
869 ArgInRegs[i] = (Flags >> 1) & 1;
870 SRetArgs[i] = (Flags >> 2) & 1;
873 // Calculate stack frame size
874 for (unsigned i = 0; i != NumOps; ++i) {
875 SDOperand Arg = Op.getOperand(5+2*i);
876 unsigned ArgIncrement = 4;
877 unsigned ObjSize = 0;
878 unsigned ObjIntRegs = 0;
879 unsigned ObjXMMRegs = 0;
881 HowToPassCallArgument(Arg.getValueType(),
883 NumIntRegs, NumXMMRegs, 3,
884 ObjSize, ObjIntRegs, ObjXMMRegs);
886 ArgIncrement = ObjSize;
888 NumIntRegs += ObjIntRegs;
889 NumXMMRegs += ObjXMMRegs;
891 // XMM arguments have to be aligned on 16-byte boundary.
893 NumBytes = ((NumBytes + 15) / 16) * 16;
894 NumBytes += ArgIncrement;
898 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
900 // Arguments go on the stack in reverse order, as specified by the ABI.
901 unsigned ArgOffset = 0;
904 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
905 SmallVector<SDOperand, 8> MemOpChains;
906 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
907 for (unsigned i = 0; i != NumOps; ++i) {
908 SDOperand Arg = Op.getOperand(5+2*i);
909 unsigned ArgIncrement = 4;
910 unsigned ObjSize = 0;
911 unsigned ObjIntRegs = 0;
912 unsigned ObjXMMRegs = 0;
914 HowToPassCallArgument(Arg.getValueType(),
916 NumIntRegs, NumXMMRegs, 3,
917 ObjSize, ObjIntRegs, ObjXMMRegs);
920 ArgIncrement = ObjSize;
922 if (Arg.getValueType() == MVT::i8 || Arg.getValueType() == MVT::i16) {
923 // Promote the integer to 32 bits. If the input type is signed use a
924 // sign extend, otherwise use a zero extend.
925 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
927 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
928 Arg = DAG.getNode(ExtOp, MVT::i32, Arg);
931 if (ObjIntRegs || ObjXMMRegs) {
932 switch (Arg.getValueType()) {
933 default: assert(0 && "Unhandled argument type!");
935 RegsToPass.push_back(std::make_pair(GPR32ArgRegs[NumIntRegs], Arg));
943 RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg));
947 NumIntRegs += ObjIntRegs;
948 NumXMMRegs += ObjXMMRegs;
951 // XMM arguments have to be aligned on 16-byte boundary.
953 ArgOffset = ((ArgOffset + 15) / 16) * 16;
955 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
956 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
957 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
959 ArgOffset += ArgIncrement; // Move on to the next argument.
961 NumSRetBytes += ArgIncrement;
965 // Sanity check: we haven't seen NumSRetBytes > 4
966 assert((NumSRetBytes<=4) &&
967 "Too much space for struct-return pointer requested");
969 if (!MemOpChains.empty())
970 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
971 &MemOpChains[0], MemOpChains.size());
973 // Build a sequence of copy-to-reg nodes chained together with token chain
974 // and flag operands which copy the outgoing args into registers.
976 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
977 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
979 InFlag = Chain.getValue(1);
982 // ELF / PIC requires GOT in the EBX register before function calls via PLT
984 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
985 Subtarget->isPICStyleGOT()) {
986 Chain = DAG.getCopyToReg(Chain, X86::EBX,
987 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
989 InFlag = Chain.getValue(1);
992 // If the callee is a GlobalAddress node (quite common, every direct call is)
993 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
994 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
995 // We should use extra load for direct calls to dllimported functions in
997 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
998 getTargetMachine(), true))
999 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1000 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1001 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1003 // Returns a chain & a flag for retval copy to use.
1004 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1005 SmallVector<SDOperand, 8> Ops;
1006 Ops.push_back(Chain);
1007 Ops.push_back(Callee);
1009 // Add argument registers to the end of the list so that they are known live
1011 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1012 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1013 RegsToPass[i].second.getValueType()));
1015 // Add an implicit use GOT pointer in EBX.
1016 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1017 Subtarget->isPICStyleGOT())
1018 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1021 Ops.push_back(InFlag);
1023 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1024 NodeTys, &Ops[0], Ops.size());
1025 InFlag = Chain.getValue(1);
1027 // Create the CALLSEQ_END node.
1028 unsigned NumBytesForCalleeToPush = 0;
1030 if (CC == CallingConv::X86_StdCall) {
1032 NumBytesForCalleeToPush = NumSRetBytes;
1034 NumBytesForCalleeToPush = NumBytes;
1036 // If this is is a call to a struct-return function, the callee
1037 // pops the hidden struct pointer, so we have to push it back.
1038 // This is common for Darwin/X86, Linux & Mingw32 targets.
1039 NumBytesForCalleeToPush = NumSRetBytes;
1042 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1044 Ops.push_back(Chain);
1045 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1046 Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy()));
1047 Ops.push_back(InFlag);
1048 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1049 InFlag = Chain.getValue(1);
1051 // Handle result values, copying them out of physregs into vregs that we
1053 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1057 //===----------------------------------------------------------------------===//
1058 // X86-64 C Calling Convention implementation
1059 //===----------------------------------------------------------------------===//
1061 /// HowToPassX86_64CCCArgument - Returns how an formal argument of the specified
1062 /// type should be passed. If it is through stack, returns the size of the stack
1063 /// slot; if it is through integer or XMM register, returns the number of
1064 /// integer or XMM registers are needed.
1066 HowToPassX86_64CCCArgument(MVT::ValueType ObjectVT,
1067 unsigned NumIntRegs, unsigned NumXMMRegs,
1068 unsigned &ObjSize, unsigned &ObjIntRegs,
1069 unsigned &ObjXMMRegs) {
1075 default: assert(0 && "Unhandled argument type!");
1085 case MVT::i8: ObjSize = 1; break;
1086 case MVT::i16: ObjSize = 2; break;
1087 case MVT::i32: ObjSize = 4; break;
1088 case MVT::i64: ObjSize = 8; break;
1105 case MVT::f32: ObjSize = 4; break;
1106 case MVT::f64: ObjSize = 8; break;
1112 case MVT::v2f64: ObjSize = 16; break;
1120 X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
1121 unsigned NumArgs = Op.Val->getNumValues() - 1;
1122 MachineFunction &MF = DAG.getMachineFunction();
1123 MachineFrameInfo *MFI = MF.getFrameInfo();
1124 SDOperand Root = Op.getOperand(0);
1125 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1126 SmallVector<SDOperand, 8> ArgValues;
1128 // Add DAG nodes to load the arguments... On entry to a function on the X86,
1129 // the stack frame looks like this:
1131 // [RSP] -- return address
1132 // [RSP + 8] -- first nonreg argument (leftmost lexically)
1133 // [RSP +16] -- second nonreg argument, if 1st argument is <= 8 bytes in size
1136 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
1137 unsigned NumIntRegs = 0; // Int regs used for parameter passing.
1138 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
1140 static const unsigned GPR32ArgRegs[] = {
1141 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1143 static const unsigned GPR64ArgRegs[] = {
1144 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1146 static const unsigned XMMArgRegs[] = {
1147 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1148 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1151 for (unsigned i = 0; i < NumArgs; ++i) {
1152 MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
1153 unsigned ArgFlags = cast<ConstantSDNode>(Op.getOperand(3+i))->getValue();
1154 unsigned ArgIncrement = 8;
1155 unsigned ObjSize = 0;
1156 unsigned ObjIntRegs = 0;
1157 unsigned ObjXMMRegs = 0;
1159 // FIXME: __int128 and long double support?
1160 HowToPassX86_64CCCArgument(ObjectVT, NumIntRegs, NumXMMRegs,
1161 ObjSize, ObjIntRegs, ObjXMMRegs);
1163 ArgIncrement = ObjSize;
1167 if (ObjIntRegs || ObjXMMRegs) {
1169 default: assert(0 && "Unhandled argument type!");
1174 TargetRegisterClass *RC = NULL;
1176 default: assert(0 && "Unknown integer VT!");
1180 RC = X86::GR32RegisterClass;
1181 Reg = GPR32ArgRegs[NumIntRegs];
1182 ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i32);
1185 RC = X86::GR64RegisterClass;
1186 Reg = GPR64ArgRegs[NumIntRegs];
1187 ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i64);
1190 Reg = AddLiveIn(MF, Reg, RC);
1192 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1193 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1195 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i16) {
1196 // FIXME: FORMAL_ARGUMENTS can't currently distinguish between an
1197 // argument with undefined high bits, so we can't insert a assertzext
1200 unsigned ExtOpc = (ArgFlags & 1) ? ISD::AssertSext :ISD::AssertZext;
1201 ArgValue = DAG.getNode(ExtOpc, MVT::i32, ArgValue,
1202 DAG.getValueType(ObjectVT));
1203 ArgValue = DAG.getNode(ISD::TRUNCATE, ObjectVT, ArgValue);
1216 TargetRegisterClass *RC= (ObjectVT == MVT::f32) ?
1217 X86::FR32RegisterClass : ((ObjectVT == MVT::f64) ?
1218 X86::FR64RegisterClass : X86::VR128RegisterClass);
1219 Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], RC);
1220 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
1224 NumIntRegs += ObjIntRegs;
1225 NumXMMRegs += ObjXMMRegs;
1226 } else if (ObjSize) {
1227 // XMM arguments have to be aligned on 16-byte boundary.
1229 ArgOffset = ((ArgOffset + 15) / 16) * 16;
1230 // Create the SelectionDAG nodes corresponding to a load from this
1232 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
1233 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1234 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
1235 ArgOffset += ArgIncrement; // Move on to the next argument.
1238 ArgValues.push_back(ArgValue);
1241 // If the function takes variable number of arguments, make a frame index for
1242 // the start of the first vararg value... for expansion of llvm.va_start.
1244 // For X86-64, if there are vararg parameters that are passed via
1245 // registers, then we must store them to their spots on the stack so they
1246 // may be loaded by deferencing the result of va_next.
1247 VarArgsGPOffset = NumIntRegs * 8;
1248 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
1249 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
1250 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
1252 // Store the integer parameter registers.
1253 SmallVector<SDOperand, 8> MemOps;
1254 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1255 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1256 DAG.getConstant(VarArgsGPOffset, getPointerTy()));
1257 for (; NumIntRegs != 6; ++NumIntRegs) {
1258 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1259 X86::GR64RegisterClass);
1260 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1261 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1262 MemOps.push_back(Store);
1263 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1264 DAG.getConstant(8, getPointerTy()));
1267 // Now store the XMM (fp + vector) parameter registers.
1268 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1269 DAG.getConstant(VarArgsFPOffset, getPointerTy()));
1270 for (; NumXMMRegs != 8; ++NumXMMRegs) {
1271 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1272 X86::VR128RegisterClass);
1273 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1274 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1275 MemOps.push_back(Store);
1276 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1277 DAG.getConstant(16, getPointerTy()));
1279 if (!MemOps.empty())
1280 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1281 &MemOps[0], MemOps.size());
1284 ArgValues.push_back(Root);
1286 ReturnAddrIndex = 0; // No return address slot generated yet.
1287 BytesToPopOnReturn = 0; // Callee pops nothing.
1288 BytesCallerReserves = ArgOffset;
1290 // Return the new list of results.
1291 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1292 &ArgValues[0], ArgValues.size());
1296 X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
1298 SDOperand Chain = Op.getOperand(0);
1299 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1300 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1301 SDOperand Callee = Op.getOperand(4);
1302 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1304 // Count how many bytes are to be pushed on the stack.
1305 unsigned NumBytes = 0;
1306 unsigned NumIntRegs = 0; // Int regs used for parameter passing.
1307 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
1309 static const unsigned GPR32ArgRegs[] = {
1310 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1312 static const unsigned GPR64ArgRegs[] = {
1313 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1315 static const unsigned XMMArgRegs[] = {
1316 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1317 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1320 for (unsigned i = 0; i != NumOps; ++i) {
1321 SDOperand Arg = Op.getOperand(5+2*i);
1322 MVT::ValueType ArgVT = Arg.getValueType();
1325 default: assert(0 && "Unknown value type!");
1345 else if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
1348 // XMM arguments have to be aligned on 16-byte boundary.
1349 NumBytes = ((NumBytes + 15) / 16) * 16;
1356 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1358 // Arguments go on the stack in reverse order, as specified by the ABI.
1359 unsigned ArgOffset = 0;
1362 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1363 SmallVector<SDOperand, 8> MemOpChains;
1364 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
1365 for (unsigned i = 0; i != NumOps; ++i) {
1366 SDOperand Arg = Op.getOperand(5+2*i);
1367 MVT::ValueType ArgVT = Arg.getValueType();
1368 unsigned ArgFlags =cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
1370 if (MVT::isInteger(ArgVT) && ArgVT < MVT::i32) {
1371 // Promote the integer to 32 bits. If the input type is signed use a
1372 // sign extend, otherwise use a zero extend.
1373 unsigned ExtOpc = (ArgFlags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1374 Arg = DAG.getNode(ExtOpc, MVT::i32, Arg);
1379 default: assert(0 && "Unexpected ValueType for argument!");
1384 if (NumIntRegs < 6) {
1387 default: assert(0 && "Unknown integer size!");
1389 Reg = GPR32ArgRegs[NumIntRegs];
1391 case MVT::i64: Reg = GPR64ArgRegs[NumIntRegs]; break;
1393 RegsToPass.push_back(std::make_pair(Reg, Arg));
1396 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1397 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1398 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1410 if (NumXMMRegs < 8) {
1411 RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg));
1414 if (ArgVT != MVT::f32 && ArgVT != MVT::f64) {
1415 // XMM arguments have to be aligned on 16-byte boundary.
1416 ArgOffset = ((ArgOffset + 15) / 16) * 16;
1418 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1419 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1420 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1421 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
1429 if (!MemOpChains.empty())
1430 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1431 &MemOpChains[0], MemOpChains.size());
1433 // Build a sequence of copy-to-reg nodes chained together with token chain
1434 // and flag operands which copy the outgoing args into registers.
1436 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1437 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1439 InFlag = Chain.getValue(1);
1443 // From AMD64 ABI document:
1444 // For calls that may call functions that use varargs or stdargs
1445 // (prototype-less calls or calls to functions containing ellipsis (...) in
1446 // the declaration) %al is used as hidden argument to specify the number
1447 // of SSE registers used. The contents of %al do not need to match exactly
1448 // the number of registers, but must be an ubound on the number of SSE
1449 // registers used and is in the range 0 - 8 inclusive.
1450 Chain = DAG.getCopyToReg(Chain, X86::AL,
1451 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1452 InFlag = Chain.getValue(1);
1455 // If the callee is a GlobalAddress node (quite common, every direct call is)
1456 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1457 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1458 // We should use extra load for direct calls to dllimported functions in
1460 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1461 getTargetMachine(), true))
1462 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1463 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1464 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1466 // Returns a chain & a flag for retval copy to use.
1467 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1468 SmallVector<SDOperand, 8> Ops;
1469 Ops.push_back(Chain);
1470 Ops.push_back(Callee);
1472 // Add argument registers to the end of the list so that they are known live
1474 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1475 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1476 RegsToPass[i].second.getValueType()));
1479 Ops.push_back(InFlag);
1481 // FIXME: Do not generate X86ISD::TAILCALL for now.
1482 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1483 NodeTys, &Ops[0], Ops.size());
1484 InFlag = Chain.getValue(1);
1486 // Returns a flag for retval copy to use.
1487 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1489 Ops.push_back(Chain);
1490 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1491 Ops.push_back(DAG.getConstant(0, getPointerTy()));
1492 Ops.push_back(InFlag);
1493 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1494 InFlag = Chain.getValue(1);
1496 // Handle result values, copying them out of physregs into vregs that we
1498 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1501 //===----------------------------------------------------------------------===//
1502 // Fast & FastCall Calling Convention implementation
1503 //===----------------------------------------------------------------------===//
1505 // The X86 'fast' calling convention passes up to two integer arguments in
1506 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
1507 // and requires that the callee pop its arguments off the stack (allowing proper
1508 // tail calls), and has the same return value conventions as C calling convs.
1510 // This calling convention always arranges for the callee pop value to be 8n+4
1511 // bytes, which is needed for tail recursion elimination and stack alignment
1514 // Note that this can be enhanced in the future to pass fp vals in registers
1515 // (when we have a global fp allocator) and do other tricks.
1517 //===----------------------------------------------------------------------===//
1518 // The X86 'fastcall' calling convention passes up to two integer arguments in
1519 // registers (an appropriate portion of ECX/EDX), passes arguments in C order,
1520 // and requires that the callee pop its arguments off the stack (allowing proper
1521 // tail calls), and has the same return value conventions as C calling convs.
1523 // This calling convention always arranges for the callee pop value to be 8n+4
1524 // bytes, which is needed for tail recursion elimination and stack alignment
1529 X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG,
1531 unsigned NumArgs = Op.Val->getNumValues()-1;
1532 MachineFunction &MF = DAG.getMachineFunction();
1533 MachineFrameInfo *MFI = MF.getFrameInfo();
1534 SDOperand Root = Op.getOperand(0);
1535 SmallVector<SDOperand, 8> ArgValues;
1537 // Add DAG nodes to load the arguments... On entry to a function the stack
1538 // frame looks like this:
1540 // [ESP] -- return address
1541 // [ESP + 4] -- first nonreg argument (leftmost lexically)
1542 // [ESP + 8] -- second nonreg argument, if 1st argument is <= 4 bytes in size
1544 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
1546 // Keep track of the number of integer regs passed so far. This can be either
1547 // 0 (neither EAX/ECX or EDX used), 1 (EAX/ECX is used) or 2 (EAX/ECX and EDX
1549 unsigned NumIntRegs = 0;
1550 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
1552 static const unsigned XMMArgRegs[] = {
1553 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1556 static const unsigned GPRArgRegs[][2][2] = {
1557 {{ X86::AL, X86::DL }, { X86::CL, X86::DL }},
1558 {{ X86::AX, X86::DX }, { X86::CX, X86::DX }},
1559 {{ X86::EAX, X86::EDX }, { X86::ECX, X86::EDX }}
1562 static const TargetRegisterClass* GPRClasses[3] = {
1563 X86::GR8RegisterClass, X86::GR16RegisterClass, X86::GR32RegisterClass
1566 unsigned GPRInd = (isFastCall ? 1 : 0);
1567 for (unsigned i = 0; i < NumArgs; ++i) {
1568 MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
1569 unsigned ArgIncrement = 4;
1570 unsigned ObjSize = 0;
1571 unsigned ObjXMMRegs = 0;
1572 unsigned ObjIntRegs = 0;
1576 HowToPassCallArgument(ObjectVT,
1577 true, // Use as much registers as possible
1578 NumIntRegs, NumXMMRegs,
1579 (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS),
1580 ObjSize, ObjIntRegs, ObjXMMRegs);
1583 ArgIncrement = ObjSize;
1585 if (ObjIntRegs || ObjXMMRegs) {
1587 default: assert(0 && "Unhandled argument type!");
1591 unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][GPRInd][NumIntRegs];
1592 Reg = AddLiveIn(MF, RegToUse, GPRClasses[ObjectVT-MVT::i8]);
1593 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
1602 assert(!isFastCall && "Unhandled argument type!");
1603 Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass);
1604 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
1608 NumIntRegs += ObjIntRegs;
1609 NumXMMRegs += ObjXMMRegs;
1612 // XMM arguments have to be aligned on 16-byte boundary.
1614 ArgOffset = ((ArgOffset + 15) / 16) * 16;
1615 // Create the SelectionDAG nodes corresponding to a load from this
1617 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
1618 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1619 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
1621 ArgOffset += ArgIncrement; // Move on to the next argument.
1624 ArgValues.push_back(ArgValue);
1627 ArgValues.push_back(Root);
1629 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1630 // arguments and the arguments after the retaddr has been pushed are aligned.
1631 if ((ArgOffset & 7) == 0)
1634 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1635 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
1636 ReturnAddrIndex = 0; // No return address slot generated yet.
1637 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
1638 BytesCallerReserves = 0;
1640 MF.getInfo<X86FunctionInfo>()->setBytesToPopOnReturn(BytesToPopOnReturn);
1642 // Finally, inform the code generator which regs we return values in.
1643 switch (getValueType(MF.getFunction()->getReturnType())) {
1644 default: assert(0 && "Unknown type!");
1645 case MVT::isVoid: break;
1650 MF.addLiveOut(X86::EAX);
1653 MF.addLiveOut(X86::EAX);
1654 MF.addLiveOut(X86::EDX);
1658 MF.addLiveOut(X86::ST0);
1666 assert(!isFastCall && "Unknown result type");
1667 MF.addLiveOut(X86::XMM0);
1671 // Return the new list of results.
1672 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1673 &ArgValues[0], ArgValues.size());
1676 SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
1678 SDOperand Chain = Op.getOperand(0);
1679 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1680 SDOperand Callee = Op.getOperand(4);
1681 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1683 // Count how many bytes are to be pushed on the stack.
1684 unsigned NumBytes = 0;
1686 // Keep track of the number of integer regs passed so far. This can be either
1687 // 0 (neither EAX/ECX or EDX used), 1 (EAX/ECX is used) or 2 (EAX/ECX and EDX
1689 unsigned NumIntRegs = 0;
1690 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
1692 static const unsigned GPRArgRegs[][2][2] = {
1693 {{ X86::AL, X86::DL }, { X86::CL, X86::DL }},
1694 {{ X86::AX, X86::DX }, { X86::CX, X86::DX }},
1695 {{ X86::EAX, X86::EDX }, { X86::ECX, X86::EDX }}
1697 static const unsigned XMMArgRegs[] = {
1698 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1701 bool isFastCall = CC == CallingConv::X86_FastCall;
1702 unsigned GPRInd = isFastCall ? 1 : 0;
1703 for (unsigned i = 0; i != NumOps; ++i) {
1704 SDOperand Arg = Op.getOperand(5+2*i);
1706 switch (Arg.getValueType()) {
1707 default: assert(0 && "Unknown value type!");
1711 unsigned MaxNumIntRegs = (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS);
1712 if (NumIntRegs < MaxNumIntRegs) {
1729 assert(!isFastCall && "Unknown value type!");
1733 // XMM arguments have to be aligned on 16-byte boundary.
1734 NumBytes = ((NumBytes + 15) / 16) * 16;
1741 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1742 // arguments and the arguments after the retaddr has been pushed are aligned.
1743 if ((NumBytes & 7) == 0)
1746 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1748 // Arguments go on the stack in reverse order, as specified by the ABI.
1749 unsigned ArgOffset = 0;
1751 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1752 SmallVector<SDOperand, 8> MemOpChains;
1753 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
1754 for (unsigned i = 0; i != NumOps; ++i) {
1755 SDOperand Arg = Op.getOperand(5+2*i);
1757 switch (Arg.getValueType()) {
1758 default: assert(0 && "Unexpected ValueType for argument!");
1762 unsigned MaxNumIntRegs = (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS);
1763 if (NumIntRegs < MaxNumIntRegs) {
1765 GPRArgRegs[Arg.getValueType()-MVT::i8][GPRInd][NumIntRegs];
1766 RegsToPass.push_back(std::make_pair(RegToUse, Arg));
1772 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1773 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1774 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1779 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1780 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1781 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1791 assert(!isFastCall && "Unexpected ValueType for argument!");
1792 if (NumXMMRegs < 4) {
1793 RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg));
1796 // XMM arguments have to be aligned on 16-byte boundary.
1797 ArgOffset = ((ArgOffset + 15) / 16) * 16;
1798 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1799 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1800 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1807 if (!MemOpChains.empty())
1808 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1809 &MemOpChains[0], MemOpChains.size());
1811 // Build a sequence of copy-to-reg nodes chained together with token chain
1812 // and flag operands which copy the outgoing args into registers.
1814 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1815 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1817 InFlag = Chain.getValue(1);
1820 // If the callee is a GlobalAddress node (quite common, every direct call is)
1821 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1822 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1823 // We should use extra load for direct calls to dllimported functions in
1825 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1826 getTargetMachine(), true))
1827 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1828 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1829 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1831 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1833 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1834 Subtarget->isPICStyleGOT()) {
1835 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1836 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1838 InFlag = Chain.getValue(1);
1841 // Returns a chain & a flag for retval copy to use.
1842 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1843 SmallVector<SDOperand, 8> Ops;
1844 Ops.push_back(Chain);
1845 Ops.push_back(Callee);
1847 // Add argument registers to the end of the list so that they are known live
1849 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1850 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1851 RegsToPass[i].second.getValueType()));
1853 // Add an implicit use GOT pointer in EBX.
1854 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1855 Subtarget->isPICStyleGOT())
1856 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1859 Ops.push_back(InFlag);
1861 // FIXME: Do not generate X86ISD::TAILCALL for now.
1862 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1863 NodeTys, &Ops[0], Ops.size());
1864 InFlag = Chain.getValue(1);
1866 // Returns a flag for retval copy to use.
1867 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1869 Ops.push_back(Chain);
1870 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1871 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1872 Ops.push_back(InFlag);
1873 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1874 InFlag = Chain.getValue(1);
1876 // Handle result values, copying them out of physregs into vregs that we
1878 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1881 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1882 if (ReturnAddrIndex == 0) {
1883 // Set up a frame object for the return address.
1884 MachineFunction &MF = DAG.getMachineFunction();
1885 if (Subtarget->is64Bit())
1886 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1888 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1891 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1896 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1897 /// specific condition code. It returns a false if it cannot do a direct
1898 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1900 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1901 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1902 SelectionDAG &DAG) {
1903 X86CC = X86::COND_INVALID;
1905 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1906 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1907 // X > -1 -> X == 0, jump !sign.
1908 RHS = DAG.getConstant(0, RHS.getValueType());
1909 X86CC = X86::COND_NS;
1911 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1912 // X < 0 -> X == 0, jump on sign.
1913 X86CC = X86::COND_S;
1918 switch (SetCCOpcode) {
1920 case ISD::SETEQ: X86CC = X86::COND_E; break;
1921 case ISD::SETGT: X86CC = X86::COND_G; break;
1922 case ISD::SETGE: X86CC = X86::COND_GE; break;
1923 case ISD::SETLT: X86CC = X86::COND_L; break;
1924 case ISD::SETLE: X86CC = X86::COND_LE; break;
1925 case ISD::SETNE: X86CC = X86::COND_NE; break;
1926 case ISD::SETULT: X86CC = X86::COND_B; break;
1927 case ISD::SETUGT: X86CC = X86::COND_A; break;
1928 case ISD::SETULE: X86CC = X86::COND_BE; break;
1929 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1932 // On a floating point condition, the flags are set as follows:
1934 // 0 | 0 | 0 | X > Y
1935 // 0 | 0 | 1 | X < Y
1936 // 1 | 0 | 0 | X == Y
1937 // 1 | 1 | 1 | unordered
1939 switch (SetCCOpcode) {
1942 case ISD::SETEQ: X86CC = X86::COND_E; break;
1943 case ISD::SETOLT: Flip = true; // Fallthrough
1945 case ISD::SETGT: X86CC = X86::COND_A; break;
1946 case ISD::SETOLE: Flip = true; // Fallthrough
1948 case ISD::SETGE: X86CC = X86::COND_AE; break;
1949 case ISD::SETUGT: Flip = true; // Fallthrough
1951 case ISD::SETLT: X86CC = X86::COND_B; break;
1952 case ISD::SETUGE: Flip = true; // Fallthrough
1954 case ISD::SETLE: X86CC = X86::COND_BE; break;
1956 case ISD::SETNE: X86CC = X86::COND_NE; break;
1957 case ISD::SETUO: X86CC = X86::COND_P; break;
1958 case ISD::SETO: X86CC = X86::COND_NP; break;
1961 std::swap(LHS, RHS);
1964 return X86CC != X86::COND_INVALID;
1967 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1968 /// code. Current x86 isa includes the following FP cmov instructions:
1969 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1970 static bool hasFPCMov(unsigned X86CC) {
1986 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
1987 /// true if Op is undef or if its value falls within the specified range (L, H].
1988 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1989 if (Op.getOpcode() == ISD::UNDEF)
1992 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
1993 return (Val >= Low && Val < Hi);
1996 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
1997 /// true if Op is undef or if its value equal to the specified value.
1998 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
1999 if (Op.getOpcode() == ISD::UNDEF)
2001 return cast<ConstantSDNode>(Op)->getValue() == Val;
2004 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2005 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
2006 bool X86::isPSHUFDMask(SDNode *N) {
2007 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2009 if (N->getNumOperands() != 4)
2012 // Check if the value doesn't reference the second vector.
2013 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2014 SDOperand Arg = N->getOperand(i);
2015 if (Arg.getOpcode() == ISD::UNDEF) continue;
2016 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2017 if (cast<ConstantSDNode>(Arg)->getValue() >= 4)
2024 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2025 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2026 bool X86::isPSHUFHWMask(SDNode *N) {
2027 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2029 if (N->getNumOperands() != 8)
2032 // Lower quadword copied in order.
2033 for (unsigned i = 0; i != 4; ++i) {
2034 SDOperand Arg = N->getOperand(i);
2035 if (Arg.getOpcode() == ISD::UNDEF) continue;
2036 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2037 if (cast<ConstantSDNode>(Arg)->getValue() != i)
2041 // Upper quadword shuffled.
2042 for (unsigned i = 4; i != 8; ++i) {
2043 SDOperand Arg = N->getOperand(i);
2044 if (Arg.getOpcode() == ISD::UNDEF) continue;
2045 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2046 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2047 if (Val < 4 || Val > 7)
2054 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2055 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2056 bool X86::isPSHUFLWMask(SDNode *N) {
2057 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2059 if (N->getNumOperands() != 8)
2062 // Upper quadword copied in order.
2063 for (unsigned i = 4; i != 8; ++i)
2064 if (!isUndefOrEqual(N->getOperand(i), i))
2067 // Lower quadword shuffled.
2068 for (unsigned i = 0; i != 4; ++i)
2069 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2075 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2076 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2077 static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
2078 if (NumElems != 2 && NumElems != 4) return false;
2080 unsigned Half = NumElems / 2;
2081 for (unsigned i = 0; i < Half; ++i)
2082 if (!isUndefOrInRange(Elems[i], 0, NumElems))
2084 for (unsigned i = Half; i < NumElems; ++i)
2085 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
2091 bool X86::isSHUFPMask(SDNode *N) {
2092 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2093 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
2096 /// isCommutedSHUFP - Returns true if the shuffle mask is except
2097 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2098 /// half elements to come from vector 1 (which would equal the dest.) and
2099 /// the upper half to come from vector 2.
2100 static bool isCommutedSHUFP(const SDOperand *Ops, unsigned NumOps) {
2101 if (NumOps != 2 && NumOps != 4) return false;
2103 unsigned Half = NumOps / 2;
2104 for (unsigned i = 0; i < Half; ++i)
2105 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
2107 for (unsigned i = Half; i < NumOps; ++i)
2108 if (!isUndefOrInRange(Ops[i], 0, NumOps))
2113 static bool isCommutedSHUFP(SDNode *N) {
2114 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2115 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
2118 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2119 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2120 bool X86::isMOVHLPSMask(SDNode *N) {
2121 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2123 if (N->getNumOperands() != 4)
2126 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2127 return isUndefOrEqual(N->getOperand(0), 6) &&
2128 isUndefOrEqual(N->getOperand(1), 7) &&
2129 isUndefOrEqual(N->getOperand(2), 2) &&
2130 isUndefOrEqual(N->getOperand(3), 3);
2133 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2134 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2136 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2137 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2139 if (N->getNumOperands() != 4)
2142 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2143 return isUndefOrEqual(N->getOperand(0), 2) &&
2144 isUndefOrEqual(N->getOperand(1), 3) &&
2145 isUndefOrEqual(N->getOperand(2), 2) &&
2146 isUndefOrEqual(N->getOperand(3), 3);
2149 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2150 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2151 bool X86::isMOVLPMask(SDNode *N) {
2152 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2154 unsigned NumElems = N->getNumOperands();
2155 if (NumElems != 2 && NumElems != 4)
2158 for (unsigned i = 0; i < NumElems/2; ++i)
2159 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2162 for (unsigned i = NumElems/2; i < NumElems; ++i)
2163 if (!isUndefOrEqual(N->getOperand(i), i))
2169 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2170 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2172 bool X86::isMOVHPMask(SDNode *N) {
2173 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2175 unsigned NumElems = N->getNumOperands();
2176 if (NumElems != 2 && NumElems != 4)
2179 for (unsigned i = 0; i < NumElems/2; ++i)
2180 if (!isUndefOrEqual(N->getOperand(i), i))
2183 for (unsigned i = 0; i < NumElems/2; ++i) {
2184 SDOperand Arg = N->getOperand(i + NumElems/2);
2185 if (!isUndefOrEqual(Arg, i + NumElems))
2192 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2193 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2194 bool static isUNPCKLMask(const SDOperand *Elts, unsigned NumElts,
2195 bool V2IsSplat = false) {
2196 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2199 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2200 SDOperand BitI = Elts[i];
2201 SDOperand BitI1 = Elts[i+1];
2202 if (!isUndefOrEqual(BitI, j))
2205 if (isUndefOrEqual(BitI1, NumElts))
2208 if (!isUndefOrEqual(BitI1, j + NumElts))
2216 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2217 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2218 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2221 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2222 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2223 bool static isUNPCKHMask(const SDOperand *Elts, unsigned NumElts,
2224 bool V2IsSplat = false) {
2225 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2228 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2229 SDOperand BitI = Elts[i];
2230 SDOperand BitI1 = Elts[i+1];
2231 if (!isUndefOrEqual(BitI, j + NumElts/2))
2234 if (isUndefOrEqual(BitI1, NumElts))
2237 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2245 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2246 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2247 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2250 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2251 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2253 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2254 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2256 unsigned NumElems = N->getNumOperands();
2257 if (NumElems != 4 && NumElems != 8 && NumElems != 16)
2260 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2261 SDOperand BitI = N->getOperand(i);
2262 SDOperand BitI1 = N->getOperand(i+1);
2264 if (!isUndefOrEqual(BitI, j))
2266 if (!isUndefOrEqual(BitI1, j))
2273 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2274 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2275 /// MOVSD, and MOVD, i.e. setting the lowest element.
2276 static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) {
2277 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2280 if (!isUndefOrEqual(Elts[0], NumElts))
2283 for (unsigned i = 1; i < NumElts; ++i) {
2284 if (!isUndefOrEqual(Elts[i], i))
2291 bool X86::isMOVLMask(SDNode *N) {
2292 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2293 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2296 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2297 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2298 /// element of vector 2 and the other elements to come from vector 1 in order.
2299 static bool isCommutedMOVL(const SDOperand *Ops, unsigned NumOps,
2300 bool V2IsSplat = false,
2301 bool V2IsUndef = false) {
2302 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2305 if (!isUndefOrEqual(Ops[0], 0))
2308 for (unsigned i = 1; i < NumOps; ++i) {
2309 SDOperand Arg = Ops[i];
2310 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2311 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2312 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2319 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2320 bool V2IsUndef = false) {
2321 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2322 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2323 V2IsSplat, V2IsUndef);
2326 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2327 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2328 bool X86::isMOVSHDUPMask(SDNode *N) {
2329 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2331 if (N->getNumOperands() != 4)
2334 // Expect 1, 1, 3, 3
2335 for (unsigned i = 0; i < 2; ++i) {
2336 SDOperand Arg = N->getOperand(i);
2337 if (Arg.getOpcode() == ISD::UNDEF) continue;
2338 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2339 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2340 if (Val != 1) return false;
2344 for (unsigned i = 2; i < 4; ++i) {
2345 SDOperand Arg = N->getOperand(i);
2346 if (Arg.getOpcode() == ISD::UNDEF) continue;
2347 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2348 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2349 if (Val != 3) return false;
2353 // Don't use movshdup if it can be done with a shufps.
2357 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2358 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2359 bool X86::isMOVSLDUPMask(SDNode *N) {
2360 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2362 if (N->getNumOperands() != 4)
2365 // Expect 0, 0, 2, 2
2366 for (unsigned i = 0; i < 2; ++i) {
2367 SDOperand Arg = N->getOperand(i);
2368 if (Arg.getOpcode() == ISD::UNDEF) continue;
2369 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2370 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2371 if (Val != 0) return false;
2375 for (unsigned i = 2; i < 4; ++i) {
2376 SDOperand Arg = N->getOperand(i);
2377 if (Arg.getOpcode() == ISD::UNDEF) continue;
2378 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2379 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2380 if (Val != 2) return false;
2384 // Don't use movshdup if it can be done with a shufps.
2388 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2389 /// a splat of a single element.
2390 static bool isSplatMask(SDNode *N) {
2391 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2393 // This is a splat operation if each element of the permute is the same, and
2394 // if the value doesn't reference the second vector.
2395 unsigned NumElems = N->getNumOperands();
2396 SDOperand ElementBase;
2398 for (; i != NumElems; ++i) {
2399 SDOperand Elt = N->getOperand(i);
2400 if (isa<ConstantSDNode>(Elt)) {
2406 if (!ElementBase.Val)
2409 for (; i != NumElems; ++i) {
2410 SDOperand Arg = N->getOperand(i);
2411 if (Arg.getOpcode() == ISD::UNDEF) continue;
2412 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2413 if (Arg != ElementBase) return false;
2416 // Make sure it is a splat of the first vector operand.
2417 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
2420 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2421 /// a splat of a single element and it's a 2 or 4 element mask.
2422 bool X86::isSplatMask(SDNode *N) {
2423 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2425 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2426 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2428 return ::isSplatMask(N);
2431 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2432 /// specifies a splat of zero element.
2433 bool X86::isSplatLoMask(SDNode *N) {
2434 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2436 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2437 if (!isUndefOrEqual(N->getOperand(i), 0))
2442 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2443 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2445 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2446 unsigned NumOperands = N->getNumOperands();
2447 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2449 for (unsigned i = 0; i < NumOperands; ++i) {
2451 SDOperand Arg = N->getOperand(NumOperands-i-1);
2452 if (Arg.getOpcode() != ISD::UNDEF)
2453 Val = cast<ConstantSDNode>(Arg)->getValue();
2454 if (Val >= NumOperands) Val -= NumOperands;
2456 if (i != NumOperands - 1)
2463 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2464 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2466 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2468 // 8 nodes, but we only care about the last 4.
2469 for (unsigned i = 7; i >= 4; --i) {
2471 SDOperand Arg = N->getOperand(i);
2472 if (Arg.getOpcode() != ISD::UNDEF)
2473 Val = cast<ConstantSDNode>(Arg)->getValue();
2482 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2483 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2485 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2487 // 8 nodes, but we only care about the first 4.
2488 for (int i = 3; i >= 0; --i) {
2490 SDOperand Arg = N->getOperand(i);
2491 if (Arg.getOpcode() != ISD::UNDEF)
2492 Val = cast<ConstantSDNode>(Arg)->getValue();
2501 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2502 /// specifies a 8 element shuffle that can be broken into a pair of
2503 /// PSHUFHW and PSHUFLW.
2504 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2505 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2507 if (N->getNumOperands() != 8)
2510 // Lower quadword shuffled.
2511 for (unsigned i = 0; i != 4; ++i) {
2512 SDOperand Arg = N->getOperand(i);
2513 if (Arg.getOpcode() == ISD::UNDEF) continue;
2514 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2515 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2520 // Upper quadword shuffled.
2521 for (unsigned i = 4; i != 8; ++i) {
2522 SDOperand Arg = N->getOperand(i);
2523 if (Arg.getOpcode() == ISD::UNDEF) continue;
2524 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2525 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2526 if (Val < 4 || Val > 7)
2533 /// CommuteVectorShuffle - Swap vector_shuffle operandsas well as
2534 /// values in ther permute mask.
2535 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2536 SDOperand &V2, SDOperand &Mask,
2537 SelectionDAG &DAG) {
2538 MVT::ValueType VT = Op.getValueType();
2539 MVT::ValueType MaskVT = Mask.getValueType();
2540 MVT::ValueType EltVT = MVT::getVectorBaseType(MaskVT);
2541 unsigned NumElems = Mask.getNumOperands();
2542 SmallVector<SDOperand, 8> MaskVec;
2544 for (unsigned i = 0; i != NumElems; ++i) {
2545 SDOperand Arg = Mask.getOperand(i);
2546 if (Arg.getOpcode() == ISD::UNDEF) {
2547 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2550 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2551 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2553 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2555 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2559 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2560 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2563 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2564 /// match movhlps. The lower half elements should come from upper half of
2565 /// V1 (and in order), and the upper half elements should come from the upper
2566 /// half of V2 (and in order).
2567 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2568 unsigned NumElems = Mask->getNumOperands();
2571 for (unsigned i = 0, e = 2; i != e; ++i)
2572 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2574 for (unsigned i = 2; i != 4; ++i)
2575 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2580 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2581 /// is promoted to a vector.
2582 static inline bool isScalarLoadToVector(SDNode *N) {
2583 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2584 N = N->getOperand(0).Val;
2585 return ISD::isNON_EXTLoad(N);
2590 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2591 /// match movlp{s|d}. The lower half elements should come from lower half of
2592 /// V1 (and in order), and the upper half elements should come from the upper
2593 /// half of V2 (and in order). And since V1 will become the source of the
2594 /// MOVLP, it must be either a vector load or a scalar load to vector.
2595 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2596 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2598 // Is V2 is a vector load, don't do this transformation. We will try to use
2599 // load folding shufps op.
2600 if (ISD::isNON_EXTLoad(V2))
2603 unsigned NumElems = Mask->getNumOperands();
2604 if (NumElems != 2 && NumElems != 4)
2606 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2607 if (!isUndefOrEqual(Mask->getOperand(i), i))
2609 for (unsigned i = NumElems/2; i != NumElems; ++i)
2610 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2615 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2617 static bool isSplatVector(SDNode *N) {
2618 if (N->getOpcode() != ISD::BUILD_VECTOR)
2621 SDOperand SplatValue = N->getOperand(0);
2622 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2623 if (N->getOperand(i) != SplatValue)
2628 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2630 static bool isUndefShuffle(SDNode *N) {
2631 if (N->getOpcode() != ISD::BUILD_VECTOR)
2634 SDOperand V1 = N->getOperand(0);
2635 SDOperand V2 = N->getOperand(1);
2636 SDOperand Mask = N->getOperand(2);
2637 unsigned NumElems = Mask.getNumOperands();
2638 for (unsigned i = 0; i != NumElems; ++i) {
2639 SDOperand Arg = Mask.getOperand(i);
2640 if (Arg.getOpcode() != ISD::UNDEF) {
2641 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2642 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2644 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2651 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2652 /// that point to V2 points to its first element.
2653 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2654 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2656 bool Changed = false;
2657 SmallVector<SDOperand, 8> MaskVec;
2658 unsigned NumElems = Mask.getNumOperands();
2659 for (unsigned i = 0; i != NumElems; ++i) {
2660 SDOperand Arg = Mask.getOperand(i);
2661 if (Arg.getOpcode() != ISD::UNDEF) {
2662 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2663 if (Val > NumElems) {
2664 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2668 MaskVec.push_back(Arg);
2672 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2673 &MaskVec[0], MaskVec.size());
2677 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2678 /// operation of specified width.
2679 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2680 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2681 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2683 SmallVector<SDOperand, 8> MaskVec;
2684 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2685 for (unsigned i = 1; i != NumElems; ++i)
2686 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2687 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2690 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2691 /// of specified width.
2692 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2693 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2694 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2695 SmallVector<SDOperand, 8> MaskVec;
2696 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2697 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2698 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2700 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2703 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2704 /// of specified width.
2705 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2706 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2707 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2708 unsigned Half = NumElems/2;
2709 SmallVector<SDOperand, 8> MaskVec;
2710 for (unsigned i = 0; i != Half; ++i) {
2711 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2712 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2714 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2717 /// getZeroVector - Returns a vector of specified type with all zero elements.
2719 static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
2720 assert(MVT::isVector(VT) && "Expected a vector type");
2721 unsigned NumElems = getVectorNumElements(VT);
2722 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
2723 bool isFP = MVT::isFloatingPoint(EVT);
2724 SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
2725 SmallVector<SDOperand, 8> ZeroVec(NumElems, Zero);
2726 return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size());
2729 /// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
2731 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
2732 SDOperand V1 = Op.getOperand(0);
2733 SDOperand Mask = Op.getOperand(2);
2734 MVT::ValueType VT = Op.getValueType();
2735 unsigned NumElems = Mask.getNumOperands();
2736 Mask = getUnpacklMask(NumElems, DAG);
2737 while (NumElems != 4) {
2738 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2741 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
2743 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2744 Mask = getZeroVector(MaskVT, DAG);
2745 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
2746 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
2747 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2750 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2752 static inline bool isZeroNode(SDOperand Elt) {
2753 return ((isa<ConstantSDNode>(Elt) &&
2754 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2755 (isa<ConstantFPSDNode>(Elt) &&
2756 cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0)));
2759 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2760 /// vector and zero or undef vector.
2761 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
2762 unsigned NumElems, unsigned Idx,
2763 bool isZero, SelectionDAG &DAG) {
2764 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
2765 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2766 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
2767 SDOperand Zero = DAG.getConstant(0, EVT);
2768 SmallVector<SDOperand, 8> MaskVec(NumElems, Zero);
2769 MaskVec[Idx] = DAG.getConstant(NumElems, EVT);
2770 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2771 &MaskVec[0], MaskVec.size());
2772 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2775 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2777 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2778 unsigned NumNonZero, unsigned NumZero,
2779 SelectionDAG &DAG, TargetLowering &TLI) {
2785 for (unsigned i = 0; i < 16; ++i) {
2786 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2787 if (ThisIsNonZero && First) {
2789 V = getZeroVector(MVT::v8i16, DAG);
2791 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2796 SDOperand ThisElt(0, 0), LastElt(0, 0);
2797 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2798 if (LastIsNonZero) {
2799 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2801 if (ThisIsNonZero) {
2802 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2803 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2804 ThisElt, DAG.getConstant(8, MVT::i8));
2806 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2811 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
2812 DAG.getConstant(i/2, TLI.getPointerTy()));
2816 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2819 /// LowerBuildVectorv16i8 - Custom lower build_vector of v8i16.
2821 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2822 unsigned NumNonZero, unsigned NumZero,
2823 SelectionDAG &DAG, TargetLowering &TLI) {
2829 for (unsigned i = 0; i < 8; ++i) {
2830 bool isNonZero = (NonZeros & (1 << i)) != 0;
2834 V = getZeroVector(MVT::v8i16, DAG);
2836 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2839 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
2840 DAG.getConstant(i, TLI.getPointerTy()));
2848 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2849 // All zero's are handled with pxor.
2850 if (ISD::isBuildVectorAllZeros(Op.Val))
2853 // All one's are handled with pcmpeqd.
2854 if (ISD::isBuildVectorAllOnes(Op.Val))
2857 MVT::ValueType VT = Op.getValueType();
2858 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
2859 unsigned EVTBits = MVT::getSizeInBits(EVT);
2861 unsigned NumElems = Op.getNumOperands();
2862 unsigned NumZero = 0;
2863 unsigned NumNonZero = 0;
2864 unsigned NonZeros = 0;
2865 std::set<SDOperand> Values;
2866 for (unsigned i = 0; i < NumElems; ++i) {
2867 SDOperand Elt = Op.getOperand(i);
2868 if (Elt.getOpcode() != ISD::UNDEF) {
2870 if (isZeroNode(Elt))
2873 NonZeros |= (1 << i);
2879 if (NumNonZero == 0)
2880 // Must be a mix of zero and undef. Return a zero vector.
2881 return getZeroVector(VT, DAG);
2883 // Splat is obviously ok. Let legalizer expand it to a shuffle.
2884 if (Values.size() == 1)
2887 // Special case for single non-zero element.
2888 if (NumNonZero == 1) {
2889 unsigned Idx = CountTrailingZeros_32(NonZeros);
2890 SDOperand Item = Op.getOperand(Idx);
2891 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
2893 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
2894 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
2897 if (EVTBits == 32) {
2898 // Turn it into a shuffle of zero and zero-extended scalar to vector.
2899 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
2901 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2902 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
2903 SmallVector<SDOperand, 8> MaskVec;
2904 for (unsigned i = 0; i < NumElems; i++)
2905 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
2906 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2907 &MaskVec[0], MaskVec.size());
2908 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
2909 DAG.getNode(ISD::UNDEF, VT), Mask);
2913 // Let legalizer expand 2-wide build_vector's.
2917 // If element VT is < 32 bits, convert it to inserts into a zero vector.
2919 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
2921 if (V.Val) return V;
2924 if (EVTBits == 16) {
2925 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
2927 if (V.Val) return V;
2930 // If element VT is == 32 bits, turn it into a number of shuffles.
2931 SmallVector<SDOperand, 8> V;
2933 if (NumElems == 4 && NumZero > 0) {
2934 for (unsigned i = 0; i < 4; ++i) {
2935 bool isZero = !(NonZeros & (1 << i));
2937 V[i] = getZeroVector(VT, DAG);
2939 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2942 for (unsigned i = 0; i < 2; ++i) {
2943 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
2946 V[i] = V[i*2]; // Must be a zero vector.
2949 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
2950 getMOVLMask(NumElems, DAG));
2953 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2954 getMOVLMask(NumElems, DAG));
2957 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2958 getUnpacklMask(NumElems, DAG));
2963 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd)
2964 // clears the upper bits.
2965 // FIXME: we can do the same for v4f32 case when we know both parts of
2966 // the lower half come from scalar_to_vector (loadf32). We should do
2967 // that in post legalizer dag combiner with target specific hooks.
2968 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
2970 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2971 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
2972 SmallVector<SDOperand, 8> MaskVec;
2973 bool Reverse = (NonZeros & 0x3) == 2;
2974 for (unsigned i = 0; i < 2; ++i)
2976 MaskVec.push_back(DAG.getConstant(1-i, EVT));
2978 MaskVec.push_back(DAG.getConstant(i, EVT));
2979 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
2980 for (unsigned i = 0; i < 2; ++i)
2982 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
2984 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
2985 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2986 &MaskVec[0], MaskVec.size());
2987 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
2990 if (Values.size() > 2) {
2991 // Expand into a number of unpckl*.
2993 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
2994 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
2995 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
2996 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
2997 for (unsigned i = 0; i < NumElems; ++i)
2998 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3000 while (NumElems != 0) {
3001 for (unsigned i = 0; i < NumElems; ++i)
3002 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3013 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
3014 SDOperand V1 = Op.getOperand(0);
3015 SDOperand V2 = Op.getOperand(1);
3016 SDOperand PermMask = Op.getOperand(2);
3017 MVT::ValueType VT = Op.getValueType();
3018 unsigned NumElems = PermMask.getNumOperands();
3019 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3020 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
3021 bool V1IsSplat = false;
3022 bool V2IsSplat = false;
3024 if (isUndefShuffle(Op.Val))
3025 return DAG.getNode(ISD::UNDEF, VT);
3027 if (isSplatMask(PermMask.Val)) {
3028 if (NumElems <= 4) return Op;
3029 // Promote it to a v4i32 splat.
3030 return PromoteSplat(Op, DAG);
3033 if (X86::isMOVLMask(PermMask.Val))
3034 return (V1IsUndef) ? V2 : Op;
3036 if (X86::isMOVSHDUPMask(PermMask.Val) ||
3037 X86::isMOVSLDUPMask(PermMask.Val) ||
3038 X86::isMOVHLPSMask(PermMask.Val) ||
3039 X86::isMOVHPMask(PermMask.Val) ||
3040 X86::isMOVLPMask(PermMask.Val))
3043 if (ShouldXformToMOVHLPS(PermMask.Val) ||
3044 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
3045 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3047 bool Commuted = false;
3048 V1IsSplat = isSplatVector(V1.Val);
3049 V2IsSplat = isSplatVector(V2.Val);
3050 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
3051 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3052 std::swap(V1IsSplat, V2IsSplat);
3053 std::swap(V1IsUndef, V2IsUndef);
3057 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
3058 if (V2IsUndef) return V1;
3059 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3061 // V2 is a splat, so the mask may be malformed. That is, it may point
3062 // to any V2 element. The instruction selectior won't like this. Get
3063 // a corrected mask and commute to form a proper MOVS{S|D}.
3064 SDOperand NewMask = getMOVLMask(NumElems, DAG);
3065 if (NewMask.Val != PermMask.Val)
3066 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3071 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3072 X86::isUNPCKLMask(PermMask.Val) ||
3073 X86::isUNPCKHMask(PermMask.Val))
3077 // Normalize mask so all entries that point to V2 points to its first
3078 // element then try to match unpck{h|l} again. If match, return a
3079 // new vector_shuffle with the corrected mask.
3080 SDOperand NewMask = NormalizeMask(PermMask, DAG);
3081 if (NewMask.Val != PermMask.Val) {
3082 if (X86::isUNPCKLMask(PermMask.Val, true)) {
3083 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
3084 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3085 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
3086 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
3087 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3092 // Normalize the node to match x86 shuffle ops if needed
3093 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
3094 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3097 // Commute is back and try unpck* again.
3098 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3099 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3100 X86::isUNPCKLMask(PermMask.Val) ||
3101 X86::isUNPCKHMask(PermMask.Val))
3105 // If VT is integer, try PSHUF* first, then SHUFP*.
3106 if (MVT::isInteger(VT)) {
3107 if (X86::isPSHUFDMask(PermMask.Val) ||
3108 X86::isPSHUFHWMask(PermMask.Val) ||
3109 X86::isPSHUFLWMask(PermMask.Val)) {
3110 if (V2.getOpcode() != ISD::UNDEF)
3111 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3112 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3116 if (X86::isSHUFPMask(PermMask.Val))
3119 // Handle v8i16 shuffle high / low shuffle node pair.
3120 if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
3121 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3122 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
3123 SmallVector<SDOperand, 8> MaskVec;
3124 for (unsigned i = 0; i != 4; ++i)
3125 MaskVec.push_back(PermMask.getOperand(i));
3126 for (unsigned i = 4; i != 8; ++i)
3127 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3128 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3129 &MaskVec[0], MaskVec.size());
3130 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
3132 for (unsigned i = 0; i != 4; ++i)
3133 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3134 for (unsigned i = 4; i != 8; ++i)
3135 MaskVec.push_back(PermMask.getOperand(i));
3136 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],MaskVec.size());
3137 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
3140 // Floating point cases in the other order.
3141 if (X86::isSHUFPMask(PermMask.Val))
3143 if (X86::isPSHUFDMask(PermMask.Val) ||
3144 X86::isPSHUFHWMask(PermMask.Val) ||
3145 X86::isPSHUFLWMask(PermMask.Val)) {
3146 if (V2.getOpcode() != ISD::UNDEF)
3147 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3148 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3153 if (NumElems == 4) {
3154 MVT::ValueType MaskVT = PermMask.getValueType();
3155 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
3156 SmallVector<std::pair<int, int>, 8> Locs;
3157 Locs.reserve(NumElems);
3158 SmallVector<SDOperand, 8> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3159 SmallVector<SDOperand, 8> Mask2(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3162 // If no more than two elements come from either vector. This can be
3163 // implemented with two shuffles. First shuffle gather the elements.
3164 // The second shuffle, which takes the first shuffle as both of its
3165 // vector operands, put the elements into the right order.
3166 for (unsigned i = 0; i != NumElems; ++i) {
3167 SDOperand Elt = PermMask.getOperand(i);
3168 if (Elt.getOpcode() == ISD::UNDEF) {
3169 Locs[i] = std::make_pair(-1, -1);
3171 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
3172 if (Val < NumElems) {
3173 Locs[i] = std::make_pair(0, NumLo);
3177 Locs[i] = std::make_pair(1, NumHi);
3178 if (2+NumHi < NumElems)
3179 Mask1[2+NumHi] = Elt;
3184 if (NumLo <= 2 && NumHi <= 2) {
3185 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3186 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3187 &Mask1[0], Mask1.size()));
3188 for (unsigned i = 0; i != NumElems; ++i) {
3189 if (Locs[i].first == -1)
3192 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
3193 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
3194 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3198 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3199 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3200 &Mask2[0], Mask2.size()));
3203 // Break it into (shuffle shuffle_hi, shuffle_lo).
3205 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3206 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3207 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
3208 unsigned MaskIdx = 0;
3210 unsigned HiIdx = NumElems/2;
3211 for (unsigned i = 0; i != NumElems; ++i) {
3212 if (i == NumElems/2) {
3218 SDOperand Elt = PermMask.getOperand(i);
3219 if (Elt.getOpcode() == ISD::UNDEF) {
3220 Locs[i] = std::make_pair(-1, -1);
3221 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
3222 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3223 (*MaskPtr)[LoIdx] = Elt;
3226 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3227 (*MaskPtr)[HiIdx] = Elt;
3232 SDOperand LoShuffle =
3233 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3234 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3235 &LoMask[0], LoMask.size()));
3236 SDOperand HiShuffle =
3237 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3238 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3239 &HiMask[0], HiMask.size()));
3240 SmallVector<SDOperand, 8> MaskOps;
3241 for (unsigned i = 0; i != NumElems; ++i) {
3242 if (Locs[i].first == -1) {
3243 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3245 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
3246 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3249 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3250 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3251 &MaskOps[0], MaskOps.size()));
3258 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3259 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3262 MVT::ValueType VT = Op.getValueType();
3263 // TODO: handle v16i8.
3264 if (MVT::getSizeInBits(VT) == 16) {
3265 // Transform it so it match pextrw which produces a 32-bit result.
3266 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
3267 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
3268 Op.getOperand(0), Op.getOperand(1));
3269 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
3270 DAG.getValueType(VT));
3271 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3272 } else if (MVT::getSizeInBits(VT) == 32) {
3273 SDOperand Vec = Op.getOperand(0);
3274 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3277 // SHUFPS the element to the lowest double word, then movss.
3278 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3279 SmallVector<SDOperand, 8> IdxVec;
3280 IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorBaseType(MaskVT)));
3281 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
3282 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
3283 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
3284 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3285 &IdxVec[0], IdxVec.size());
3286 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3287 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3288 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3289 DAG.getConstant(0, getPointerTy()));
3290 } else if (MVT::getSizeInBits(VT) == 64) {
3291 SDOperand Vec = Op.getOperand(0);
3292 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3296 // UNPCKHPD the element to the lowest double word, then movsd.
3297 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
3298 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
3299 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3300 SmallVector<SDOperand, 8> IdxVec;
3301 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT)));
3302 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
3303 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3304 &IdxVec[0], IdxVec.size());
3305 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3306 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3307 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3308 DAG.getConstant(0, getPointerTy()));
3315 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3316 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
3317 // as its second argument.
3318 MVT::ValueType VT = Op.getValueType();
3319 MVT::ValueType BaseVT = MVT::getVectorBaseType(VT);
3320 SDOperand N0 = Op.getOperand(0);
3321 SDOperand N1 = Op.getOperand(1);
3322 SDOperand N2 = Op.getOperand(2);
3323 if (MVT::getSizeInBits(BaseVT) == 16) {
3324 if (N1.getValueType() != MVT::i32)
3325 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
3326 if (N2.getValueType() != MVT::i32)
3327 N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32);
3328 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
3329 } else if (MVT::getSizeInBits(BaseVT) == 32) {
3330 unsigned Idx = cast<ConstantSDNode>(N2)->getValue();
3333 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1);
3334 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3335 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
3336 SmallVector<SDOperand, 8> MaskVec;
3337 MaskVec.push_back(DAG.getConstant(4, BaseVT));
3338 for (unsigned i = 1; i <= 3; ++i)
3339 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3340 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1,
3341 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3342 &MaskVec[0], MaskVec.size()));
3344 // Use two pinsrw instructions to insert a 32 bit value.
3346 if (MVT::isFloatingPoint(N1.getValueType())) {
3347 if (ISD::isNON_EXTLoad(N1.Val)) {
3348 // Just load directly from f32mem to GR32.
3349 LoadSDNode *LD = cast<LoadSDNode>(N1);
3350 N1 = DAG.getLoad(MVT::i32, LD->getChain(), LD->getBasePtr(),
3351 LD->getSrcValue(), LD->getSrcValueOffset());
3353 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
3354 N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
3355 N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
3356 DAG.getConstant(0, getPointerTy()));
3359 N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
3360 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
3361 DAG.getConstant(Idx, getPointerTy()));
3362 N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
3363 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
3364 DAG.getConstant(Idx+1, getPointerTy()));
3365 return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3373 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3374 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
3375 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt);
3378 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3379 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
3380 // one of the above mentioned nodes. It has to be wrapped because otherwise
3381 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3382 // be used to form addressing mode. These wrapped nodes will be selected
3385 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
3386 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3387 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
3389 CP->getAlignment());
3390 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3391 // With PIC, the address is actually $g + Offset.
3392 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3393 !Subtarget->isPICStyleRIPRel()) {
3394 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3395 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3403 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
3404 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3405 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
3406 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3407 // With PIC, the address is actually $g + Offset.
3408 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3409 !Subtarget->isPICStyleRIPRel()) {
3410 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3411 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3415 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
3416 // load the value at address GV, not the value of GV itself. This means that
3417 // the GlobalAddress must be in the base or index register of the address, not
3418 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
3419 // The same applies for external symbols during PIC codegen
3420 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
3421 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
3427 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
3428 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
3429 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
3430 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3431 // With PIC, the address is actually $g + Offset.
3432 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3433 !Subtarget->isPICStyleRIPRel()) {
3434 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3435 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3442 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
3443 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3444 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
3445 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3446 // With PIC, the address is actually $g + Offset.
3447 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3448 !Subtarget->isPICStyleRIPRel()) {
3449 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3450 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3457 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
3458 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
3459 "Not an i64 shift!");
3460 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
3461 SDOperand ShOpLo = Op.getOperand(0);
3462 SDOperand ShOpHi = Op.getOperand(1);
3463 SDOperand ShAmt = Op.getOperand(2);
3464 SDOperand Tmp1 = isSRA ?
3465 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
3466 DAG.getConstant(0, MVT::i32);
3468 SDOperand Tmp2, Tmp3;
3469 if (Op.getOpcode() == ISD::SHL_PARTS) {
3470 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
3471 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
3473 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
3474 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
3477 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3478 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
3479 DAG.getConstant(32, MVT::i8));
3480 SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)};
3481 SDOperand InFlag = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
3484 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3486 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
3487 SmallVector<SDOperand, 4> Ops;
3488 if (Op.getOpcode() == ISD::SHL_PARTS) {
3489 Ops.push_back(Tmp2);
3490 Ops.push_back(Tmp3);
3492 Ops.push_back(InFlag);
3493 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3494 InFlag = Hi.getValue(1);
3497 Ops.push_back(Tmp3);
3498 Ops.push_back(Tmp1);
3500 Ops.push_back(InFlag);
3501 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3503 Ops.push_back(Tmp2);
3504 Ops.push_back(Tmp3);
3506 Ops.push_back(InFlag);
3507 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3508 InFlag = Lo.getValue(1);
3511 Ops.push_back(Tmp3);
3512 Ops.push_back(Tmp1);
3514 Ops.push_back(InFlag);
3515 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3518 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
3522 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
3525 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3526 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
3527 Op.getOperand(0).getValueType() >= MVT::i16 &&
3528 "Unknown SINT_TO_FP to lower!");
3531 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3532 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
3533 MachineFunction &MF = DAG.getMachineFunction();
3534 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
3535 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3536 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
3537 StackSlot, NULL, 0);
3542 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
3544 Tys = DAG.getVTList(MVT::f64, MVT::Other);
3545 SmallVector<SDOperand, 8> Ops;
3546 Ops.push_back(Chain);
3547 Ops.push_back(StackSlot);
3548 Ops.push_back(DAG.getValueType(SrcVT));
3549 Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
3550 Tys, &Ops[0], Ops.size());
3553 Chain = Result.getValue(1);
3554 SDOperand InFlag = Result.getValue(2);
3556 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
3557 // shouldn't be necessary except that RFP cannot be live across
3558 // multiple blocks. When stackifier is fixed, they can be uncoupled.
3559 MachineFunction &MF = DAG.getMachineFunction();
3560 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3561 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3562 Tys = DAG.getVTList(MVT::Other);
3563 SmallVector<SDOperand, 8> Ops;
3564 Ops.push_back(Chain);
3565 Ops.push_back(Result);
3566 Ops.push_back(StackSlot);
3567 Ops.push_back(DAG.getValueType(Op.getValueType()));
3568 Ops.push_back(InFlag);
3569 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
3570 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0);
3576 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
3577 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
3578 "Unknown FP_TO_SINT to lower!");
3579 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
3581 MachineFunction &MF = DAG.getMachineFunction();
3582 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
3583 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3584 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3587 switch (Op.getValueType()) {
3588 default: assert(0 && "Invalid FP_TO_SINT to lower!");
3589 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
3590 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
3591 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
3594 SDOperand Chain = DAG.getEntryNode();
3595 SDOperand Value = Op.getOperand(0);
3597 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
3598 Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
3599 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other);
3601 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
3603 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
3604 Chain = Value.getValue(1);
3605 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3606 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3609 // Build the FP_TO_INT*_IN_MEM
3610 SDOperand Ops[] = { Chain, Value, StackSlot };
3611 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
3614 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
3617 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
3618 MVT::ValueType VT = Op.getValueType();
3619 const Type *OpNTy = MVT::getTypeForValueType(VT);
3620 std::vector<Constant*> CV;
3621 if (VT == MVT::f64) {
3622 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63))));
3623 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3625 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31))));
3626 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3627 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3628 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3630 Constant *CS = ConstantStruct::get(CV);
3631 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3632 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
3633 SmallVector<SDOperand, 3> Ops;
3634 Ops.push_back(DAG.getEntryNode());
3635 Ops.push_back(CPIdx);
3636 Ops.push_back(DAG.getSrcValue(NULL));
3637 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3638 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
3641 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
3642 MVT::ValueType VT = Op.getValueType();
3643 const Type *OpNTy = MVT::getTypeForValueType(VT);
3644 std::vector<Constant*> CV;
3645 if (VT == MVT::f64) {
3646 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63)));
3647 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3649 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31)));
3650 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3651 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3652 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3654 Constant *CS = ConstantStruct::get(CV);
3655 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3656 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
3657 SmallVector<SDOperand, 3> Ops;
3658 Ops.push_back(DAG.getEntryNode());
3659 Ops.push_back(CPIdx);
3660 Ops.push_back(DAG.getSrcValue(NULL));
3661 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3662 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
3665 SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
3666 SDOperand Op0 = Op.getOperand(0);
3667 SDOperand Op1 = Op.getOperand(1);
3668 MVT::ValueType VT = Op.getValueType();
3669 MVT::ValueType SrcVT = Op1.getValueType();
3670 const Type *SrcTy = MVT::getTypeForValueType(SrcVT);
3672 // If second operand is smaller, extend it first.
3673 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) {
3674 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
3678 // First get the sign bit of second operand.
3679 std::vector<Constant*> CV;
3680 if (SrcVT == MVT::f64) {
3681 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(1ULL << 63)));
3682 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3684 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(1U << 31)));
3685 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3686 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3687 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3689 Constant *CS = ConstantStruct::get(CV);
3690 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3691 SDVTList Tys = DAG.getVTList(SrcVT, MVT::Other);
3692 SmallVector<SDOperand, 3> Ops;
3693 Ops.push_back(DAG.getEntryNode());
3694 Ops.push_back(CPIdx);
3695 Ops.push_back(DAG.getSrcValue(NULL));
3696 SDOperand Mask1 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3697 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
3699 // Shift sign bit right or left if the two operands have different types.
3700 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
3701 // Op0 is MVT::f32, Op1 is MVT::f64.
3702 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
3703 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
3704 DAG.getConstant(32, MVT::i32));
3705 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
3706 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
3707 DAG.getConstant(0, getPointerTy()));
3710 // Clear first operand sign bit.
3712 if (VT == MVT::f64) {
3713 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(~(1ULL << 63))));
3714 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3716 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(~(1U << 31))));
3717 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3718 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3719 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3721 CS = ConstantStruct::get(CV);
3722 CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3723 Tys = DAG.getVTList(VT, MVT::Other);
3725 Ops.push_back(DAG.getEntryNode());
3726 Ops.push_back(CPIdx);
3727 Ops.push_back(DAG.getSrcValue(NULL));
3728 SDOperand Mask2 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3729 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
3731 // Or the value with the sign bit.
3732 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
3735 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG,
3737 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
3739 SDOperand Op0 = Op.getOperand(0);
3740 SDOperand Op1 = Op.getOperand(1);
3741 SDOperand CC = Op.getOperand(2);
3742 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3743 const MVT::ValueType *VTs1 = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3744 const MVT::ValueType *VTs2 = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
3745 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
3748 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
3750 SDOperand Ops1[] = { Chain, Op0, Op1 };
3751 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, Ops1, 3).getValue(1);
3752 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
3753 return DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3756 assert(isFP && "Illegal integer SetCC!");
3758 SDOperand COps[] = { Chain, Op0, Op1 };
3759 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, COps, 3).getValue(1);
3761 switch (SetCCOpcode) {
3762 default: assert(false && "Illegal floating point SetCC!");
3763 case ISD::SETOEQ: { // !PF & ZF
3764 SDOperand Ops1[] = { DAG.getConstant(X86::COND_NP, MVT::i8), Cond };
3765 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3766 SDOperand Ops2[] = { DAG.getConstant(X86::COND_E, MVT::i8),
3768 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3769 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
3771 case ISD::SETUNE: { // PF | !ZF
3772 SDOperand Ops1[] = { DAG.getConstant(X86::COND_P, MVT::i8), Cond };
3773 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3774 SDOperand Ops2[] = { DAG.getConstant(X86::COND_NE, MVT::i8),
3776 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3777 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
3782 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
3783 bool addTest = true;
3784 SDOperand Chain = DAG.getEntryNode();
3785 SDOperand Cond = Op.getOperand(0);
3787 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3789 if (Cond.getOpcode() == ISD::SETCC)
3790 Cond = LowerSETCC(Cond, DAG, Chain);
3792 if (Cond.getOpcode() == X86ISD::SETCC) {
3793 CC = Cond.getOperand(0);
3795 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3796 // (since flag operand cannot be shared). Use it as the condition setting
3797 // operand in place of the X86ISD::SETCC.
3798 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3799 // to use a test instead of duplicating the X86ISD::CMP (for register
3800 // pressure reason)?
3801 SDOperand Cmp = Cond.getOperand(1);
3802 unsigned Opc = Cmp.getOpcode();
3803 bool IllegalFPCMov = !X86ScalarSSE &&
3804 MVT::isFloatingPoint(Op.getValueType()) &&
3805 !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
3806 if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) &&
3808 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3809 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3815 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3816 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3817 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3820 VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag);
3821 SmallVector<SDOperand, 4> Ops;
3822 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
3823 // condition is true.
3824 Ops.push_back(Op.getOperand(2));
3825 Ops.push_back(Op.getOperand(1));
3827 Ops.push_back(Cond.getValue(1));
3828 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3831 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
3832 bool addTest = true;
3833 SDOperand Chain = Op.getOperand(0);
3834 SDOperand Cond = Op.getOperand(1);
3835 SDOperand Dest = Op.getOperand(2);
3837 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3839 if (Cond.getOpcode() == ISD::SETCC)
3840 Cond = LowerSETCC(Cond, DAG, Chain);
3842 if (Cond.getOpcode() == X86ISD::SETCC) {
3843 CC = Cond.getOperand(0);
3845 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3846 // (since flag operand cannot be shared). Use it as the condition setting
3847 // operand in place of the X86ISD::SETCC.
3848 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3849 // to use a test instead of duplicating the X86ISD::CMP (for register
3850 // pressure reason)?
3851 SDOperand Cmp = Cond.getOperand(1);
3852 unsigned Opc = Cmp.getOpcode();
3853 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) {
3854 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3855 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3861 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3862 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3863 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3865 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
3866 Cond, Op.getOperand(2), CC, Cond.getValue(1));
3869 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
3870 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3872 if (Subtarget->is64Bit())
3873 return LowerX86_64CCCCallTo(Op, DAG, CallingConv);
3875 switch (CallingConv) {
3877 assert(0 && "Unsupported calling convention");
3878 case CallingConv::Fast:
3880 return LowerFastCCCallTo(Op, DAG, CallingConv);
3882 case CallingConv::C:
3883 case CallingConv::X86_StdCall:
3884 return LowerCCCCallTo(Op, DAG, CallingConv);
3885 case CallingConv::X86_FastCall:
3886 return LowerFastCCCallTo(Op, DAG, CallingConv);
3891 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
3892 MachineFunction &MF = DAG.getMachineFunction();
3893 const Function* Fn = MF.getFunction();
3894 if (Fn->hasExternalLinkage() &&
3895 Subtarget->isTargetCygMing() &&
3896 Fn->getName() == "main")
3897 MF.getInfo<X86FunctionInfo>()->setForceFramePointer(true);
3899 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3900 if (Subtarget->is64Bit())
3901 return LowerX86_64CCCArguments(Op, DAG);
3905 assert(0 && "Unsupported calling convention");
3906 case CallingConv::Fast:
3908 return LowerFastCCArguments(Op, DAG);
3911 case CallingConv::C:
3912 return LowerCCCArguments(Op, DAG);
3913 case CallingConv::X86_StdCall:
3914 MF.getInfo<X86FunctionInfo>()->setDecorationStyle(StdCall);
3915 return LowerCCCArguments(Op, DAG, true);
3916 case CallingConv::X86_FastCall:
3917 MF.getInfo<X86FunctionInfo>()->setDecorationStyle(FastCall);
3918 return LowerFastCCArguments(Op, DAG, true);
3922 SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
3923 SDOperand InFlag(0, 0);
3924 SDOperand Chain = Op.getOperand(0);
3926 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
3927 if (Align == 0) Align = 1;
3929 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
3930 // If not DWORD aligned, call memset if size is less than the threshold.
3931 // It knows how to align to the right boundary first.
3932 if ((Align & 3) != 0 ||
3933 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
3934 MVT::ValueType IntPtr = getPointerTy();
3935 const Type *IntPtrTy = getTargetData()->getIntPtrType();
3936 TargetLowering::ArgListTy Args;
3937 TargetLowering::ArgListEntry Entry;
3938 Entry.Node = Op.getOperand(1);
3939 Entry.Ty = IntPtrTy;
3940 Entry.isSigned = false;
3941 Entry.isInReg = false;
3942 Entry.isSRet = false;
3943 Args.push_back(Entry);
3944 // Extend the unsigned i8 argument to be an int value for the call.
3945 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
3946 Entry.Ty = IntPtrTy;
3947 Entry.isSigned = false;
3948 Entry.isInReg = false;
3949 Entry.isSRet = false;
3950 Args.push_back(Entry);
3951 Entry.Node = Op.getOperand(3);
3952 Args.push_back(Entry);
3953 std::pair<SDOperand,SDOperand> CallResult =
3954 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
3955 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
3956 return CallResult.second;
3961 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
3962 unsigned BytesLeft = 0;
3963 bool TwoRepStos = false;
3966 uint64_t Val = ValC->getValue() & 255;
3968 // If the value is a constant, then we can potentially use larger sets.
3969 switch (Align & 3) {
3970 case 2: // WORD aligned
3973 Val = (Val << 8) | Val;
3975 case 0: // DWORD aligned
3978 Val = (Val << 8) | Val;
3979 Val = (Val << 16) | Val;
3980 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
3983 Val = (Val << 32) | Val;
3986 default: // Byte aligned
3989 Count = Op.getOperand(3);
3993 if (AVT > MVT::i8) {
3995 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
3996 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
3997 BytesLeft = I->getValue() % UBytes;
3999 assert(AVT >= MVT::i32 &&
4000 "Do not use rep;stos if not at least DWORD aligned");
4001 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
4002 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
4007 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
4009 InFlag = Chain.getValue(1);
4012 Count = Op.getOperand(3);
4013 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
4014 InFlag = Chain.getValue(1);
4017 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4019 InFlag = Chain.getValue(1);
4020 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4021 Op.getOperand(1), InFlag);
4022 InFlag = Chain.getValue(1);
4024 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4025 SmallVector<SDOperand, 8> Ops;
4026 Ops.push_back(Chain);
4027 Ops.push_back(DAG.getValueType(AVT));
4028 Ops.push_back(InFlag);
4029 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4032 InFlag = Chain.getValue(1);
4033 Count = Op.getOperand(3);
4034 MVT::ValueType CVT = Count.getValueType();
4035 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
4036 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4037 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4039 InFlag = Chain.getValue(1);
4040 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4042 Ops.push_back(Chain);
4043 Ops.push_back(DAG.getValueType(MVT::i8));
4044 Ops.push_back(InFlag);
4045 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4046 } else if (BytesLeft) {
4047 // Issue stores for the last 1 - 7 bytes.
4049 unsigned Val = ValC->getValue() & 255;
4050 unsigned Offset = I->getValue() - BytesLeft;
4051 SDOperand DstAddr = Op.getOperand(1);
4052 MVT::ValueType AddrVT = DstAddr.getValueType();
4053 if (BytesLeft >= 4) {
4054 Val = (Val << 8) | Val;
4055 Val = (Val << 16) | Val;
4056 Value = DAG.getConstant(Val, MVT::i32);
4057 Chain = DAG.getStore(Chain, Value,
4058 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4059 DAG.getConstant(Offset, AddrVT)),
4064 if (BytesLeft >= 2) {
4065 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
4066 Chain = DAG.getStore(Chain, Value,
4067 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4068 DAG.getConstant(Offset, AddrVT)),
4073 if (BytesLeft == 1) {
4074 Value = DAG.getConstant(Val, MVT::i8);
4075 Chain = DAG.getStore(Chain, Value,
4076 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4077 DAG.getConstant(Offset, AddrVT)),
4085 SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
4086 SDOperand Chain = Op.getOperand(0);
4088 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
4089 if (Align == 0) Align = 1;
4091 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
4092 // If not DWORD aligned, call memcpy if size is less than the threshold.
4093 // It knows how to align to the right boundary first.
4094 if ((Align & 3) != 0 ||
4095 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
4096 MVT::ValueType IntPtr = getPointerTy();
4097 TargetLowering::ArgListTy Args;
4098 TargetLowering::ArgListEntry Entry;
4099 Entry.Ty = getTargetData()->getIntPtrType();
4100 Entry.isSigned = false;
4101 Entry.isInReg = false;
4102 Entry.isSRet = false;
4103 Entry.Node = Op.getOperand(1); Args.push_back(Entry);
4104 Entry.Node = Op.getOperand(2); Args.push_back(Entry);
4105 Entry.Node = Op.getOperand(3); Args.push_back(Entry);
4106 std::pair<SDOperand,SDOperand> CallResult =
4107 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
4108 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
4109 return CallResult.second;
4114 unsigned BytesLeft = 0;
4115 bool TwoRepMovs = false;
4116 switch (Align & 3) {
4117 case 2: // WORD aligned
4120 case 0: // DWORD aligned
4122 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
4125 default: // Byte aligned
4127 Count = Op.getOperand(3);
4131 if (AVT > MVT::i8) {
4133 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4134 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
4135 BytesLeft = I->getValue() % UBytes;
4137 assert(AVT >= MVT::i32 &&
4138 "Do not use rep;movs if not at least DWORD aligned");
4139 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
4140 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
4145 SDOperand InFlag(0, 0);
4146 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4148 InFlag = Chain.getValue(1);
4149 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4150 Op.getOperand(1), InFlag);
4151 InFlag = Chain.getValue(1);
4152 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
4153 Op.getOperand(2), InFlag);
4154 InFlag = Chain.getValue(1);
4156 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4157 SmallVector<SDOperand, 8> Ops;
4158 Ops.push_back(Chain);
4159 Ops.push_back(DAG.getValueType(AVT));
4160 Ops.push_back(InFlag);
4161 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
4164 InFlag = Chain.getValue(1);
4165 Count = Op.getOperand(3);
4166 MVT::ValueType CVT = Count.getValueType();
4167 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
4168 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4169 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4171 InFlag = Chain.getValue(1);
4172 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4174 Ops.push_back(Chain);
4175 Ops.push_back(DAG.getValueType(MVT::i8));
4176 Ops.push_back(InFlag);
4177 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
4178 } else if (BytesLeft) {
4179 // Issue loads and stores for the last 1 - 7 bytes.
4180 unsigned Offset = I->getValue() - BytesLeft;
4181 SDOperand DstAddr = Op.getOperand(1);
4182 MVT::ValueType DstVT = DstAddr.getValueType();
4183 SDOperand SrcAddr = Op.getOperand(2);
4184 MVT::ValueType SrcVT = SrcAddr.getValueType();
4186 if (BytesLeft >= 4) {
4187 Value = DAG.getLoad(MVT::i32, Chain,
4188 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4189 DAG.getConstant(Offset, SrcVT)),
4191 Chain = Value.getValue(1);
4192 Chain = DAG.getStore(Chain, Value,
4193 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4194 DAG.getConstant(Offset, DstVT)),
4199 if (BytesLeft >= 2) {
4200 Value = DAG.getLoad(MVT::i16, Chain,
4201 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4202 DAG.getConstant(Offset, SrcVT)),
4204 Chain = Value.getValue(1);
4205 Chain = DAG.getStore(Chain, Value,
4206 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4207 DAG.getConstant(Offset, DstVT)),
4213 if (BytesLeft == 1) {
4214 Value = DAG.getLoad(MVT::i8, Chain,
4215 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4216 DAG.getConstant(Offset, SrcVT)),
4218 Chain = Value.getValue(1);
4219 Chain = DAG.getStore(Chain, Value,
4220 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4221 DAG.getConstant(Offset, DstVT)),
4230 X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) {
4231 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4232 SDOperand TheOp = Op.getOperand(0);
4233 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheOp, 1);
4234 if (Subtarget->is64Bit()) {
4235 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
4236 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::RDX,
4237 MVT::i64, Copy1.getValue(2));
4238 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, Copy2,
4239 DAG.getConstant(32, MVT::i8));
4241 DAG.getNode(ISD::OR, MVT::i64, Copy1, Tmp), Copy2.getValue(1)
4244 Tys = DAG.getVTList(MVT::i64, MVT::Other);
4245 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
4248 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
4249 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::EDX,
4250 MVT::i32, Copy1.getValue(2));
4251 SDOperand Ops[] = { Copy1, Copy2, Copy2.getValue(1) };
4252 Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
4253 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 3);
4256 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
4257 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
4259 if (!Subtarget->is64Bit()) {
4260 // vastart just stores the address of the VarArgsFrameIndex slot into the
4261 // memory location argument.
4262 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4263 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(),
4268 // gp_offset (0 - 6 * 8)
4269 // fp_offset (48 - 48 + 8 * 16)
4270 // overflow_arg_area (point to parameters coming in memory).
4272 SmallVector<SDOperand, 8> MemOps;
4273 SDOperand FIN = Op.getOperand(1);
4275 SDOperand Store = DAG.getStore(Op.getOperand(0),
4276 DAG.getConstant(VarArgsGPOffset, MVT::i32),
4277 FIN, SV->getValue(), SV->getOffset());
4278 MemOps.push_back(Store);
4281 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4282 DAG.getConstant(4, getPointerTy()));
4283 Store = DAG.getStore(Op.getOperand(0),
4284 DAG.getConstant(VarArgsFPOffset, MVT::i32),
4285 FIN, SV->getValue(), SV->getOffset());
4286 MemOps.push_back(Store);
4288 // Store ptr to overflow_arg_area
4289 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4290 DAG.getConstant(4, getPointerTy()));
4291 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4292 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
4294 MemOps.push_back(Store);
4296 // Store ptr to reg_save_area.
4297 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4298 DAG.getConstant(8, getPointerTy()));
4299 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
4300 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
4302 MemOps.push_back(Store);
4303 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
4307 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
4308 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
4310 default: return SDOperand(); // Don't custom lower most intrinsics.
4311 // Comparison intrinsics.
4312 case Intrinsic::x86_sse_comieq_ss:
4313 case Intrinsic::x86_sse_comilt_ss:
4314 case Intrinsic::x86_sse_comile_ss:
4315 case Intrinsic::x86_sse_comigt_ss:
4316 case Intrinsic::x86_sse_comige_ss:
4317 case Intrinsic::x86_sse_comineq_ss:
4318 case Intrinsic::x86_sse_ucomieq_ss:
4319 case Intrinsic::x86_sse_ucomilt_ss:
4320 case Intrinsic::x86_sse_ucomile_ss:
4321 case Intrinsic::x86_sse_ucomigt_ss:
4322 case Intrinsic::x86_sse_ucomige_ss:
4323 case Intrinsic::x86_sse_ucomineq_ss:
4324 case Intrinsic::x86_sse2_comieq_sd:
4325 case Intrinsic::x86_sse2_comilt_sd:
4326 case Intrinsic::x86_sse2_comile_sd:
4327 case Intrinsic::x86_sse2_comigt_sd:
4328 case Intrinsic::x86_sse2_comige_sd:
4329 case Intrinsic::x86_sse2_comineq_sd:
4330 case Intrinsic::x86_sse2_ucomieq_sd:
4331 case Intrinsic::x86_sse2_ucomilt_sd:
4332 case Intrinsic::x86_sse2_ucomile_sd:
4333 case Intrinsic::x86_sse2_ucomigt_sd:
4334 case Intrinsic::x86_sse2_ucomige_sd:
4335 case Intrinsic::x86_sse2_ucomineq_sd: {
4337 ISD::CondCode CC = ISD::SETCC_INVALID;
4340 case Intrinsic::x86_sse_comieq_ss:
4341 case Intrinsic::x86_sse2_comieq_sd:
4345 case Intrinsic::x86_sse_comilt_ss:
4346 case Intrinsic::x86_sse2_comilt_sd:
4350 case Intrinsic::x86_sse_comile_ss:
4351 case Intrinsic::x86_sse2_comile_sd:
4355 case Intrinsic::x86_sse_comigt_ss:
4356 case Intrinsic::x86_sse2_comigt_sd:
4360 case Intrinsic::x86_sse_comige_ss:
4361 case Intrinsic::x86_sse2_comige_sd:
4365 case Intrinsic::x86_sse_comineq_ss:
4366 case Intrinsic::x86_sse2_comineq_sd:
4370 case Intrinsic::x86_sse_ucomieq_ss:
4371 case Intrinsic::x86_sse2_ucomieq_sd:
4372 Opc = X86ISD::UCOMI;
4375 case Intrinsic::x86_sse_ucomilt_ss:
4376 case Intrinsic::x86_sse2_ucomilt_sd:
4377 Opc = X86ISD::UCOMI;
4380 case Intrinsic::x86_sse_ucomile_ss:
4381 case Intrinsic::x86_sse2_ucomile_sd:
4382 Opc = X86ISD::UCOMI;
4385 case Intrinsic::x86_sse_ucomigt_ss:
4386 case Intrinsic::x86_sse2_ucomigt_sd:
4387 Opc = X86ISD::UCOMI;
4390 case Intrinsic::x86_sse_ucomige_ss:
4391 case Intrinsic::x86_sse2_ucomige_sd:
4392 Opc = X86ISD::UCOMI;
4395 case Intrinsic::x86_sse_ucomineq_ss:
4396 case Intrinsic::x86_sse2_ucomineq_sd:
4397 Opc = X86ISD::UCOMI;
4403 SDOperand LHS = Op.getOperand(1);
4404 SDOperand RHS = Op.getOperand(2);
4405 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
4407 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
4408 SDOperand Ops1[] = { DAG.getEntryNode(), LHS, RHS };
4409 SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3);
4410 VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
4411 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
4412 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
4413 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
4418 SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
4419 // Depths > 0 not supported yet!
4420 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4423 // Just load the return address
4424 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4425 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
4428 SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
4429 // Depths > 0 not supported yet!
4430 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4433 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4434 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
4435 DAG.getConstant(4, getPointerTy()));
4438 /// LowerOperation - Provide custom lowering hooks for some operations.
4440 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4441 switch (Op.getOpcode()) {
4442 default: assert(0 && "Should not custom lower this!");
4443 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4444 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4445 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4446 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
4447 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4448 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4449 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4450 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
4451 case ISD::SHL_PARTS:
4452 case ISD::SRA_PARTS:
4453 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
4454 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4455 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
4456 case ISD::FABS: return LowerFABS(Op, DAG);
4457 case ISD::FNEG: return LowerFNEG(Op, DAG);
4458 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4459 case ISD::SETCC: return LowerSETCC(Op, DAG, DAG.getEntryNode());
4460 case ISD::SELECT: return LowerSELECT(Op, DAG);
4461 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
4462 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4463 case ISD::CALL: return LowerCALL(Op, DAG);
4464 case ISD::RET: return LowerRET(Op, DAG);
4465 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
4466 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
4467 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
4468 case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG);
4469 case ISD::VASTART: return LowerVASTART(Op, DAG);
4470 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4471 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4472 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4477 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
4479 default: return NULL;
4480 case X86ISD::SHLD: return "X86ISD::SHLD";
4481 case X86ISD::SHRD: return "X86ISD::SHRD";
4482 case X86ISD::FAND: return "X86ISD::FAND";
4483 case X86ISD::FOR: return "X86ISD::FOR";
4484 case X86ISD::FXOR: return "X86ISD::FXOR";
4485 case X86ISD::FSRL: return "X86ISD::FSRL";
4486 case X86ISD::FILD: return "X86ISD::FILD";
4487 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
4488 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
4489 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
4490 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
4491 case X86ISD::FLD: return "X86ISD::FLD";
4492 case X86ISD::FST: return "X86ISD::FST";
4493 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
4494 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
4495 case X86ISD::CALL: return "X86ISD::CALL";
4496 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
4497 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
4498 case X86ISD::CMP: return "X86ISD::CMP";
4499 case X86ISD::COMI: return "X86ISD::COMI";
4500 case X86ISD::UCOMI: return "X86ISD::UCOMI";
4501 case X86ISD::SETCC: return "X86ISD::SETCC";
4502 case X86ISD::CMOV: return "X86ISD::CMOV";
4503 case X86ISD::BRCOND: return "X86ISD::BRCOND";
4504 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
4505 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
4506 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
4507 case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK";
4508 case X86ISD::LOAD_UA: return "X86ISD::LOAD_UA";
4509 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
4510 case X86ISD::Wrapper: return "X86ISD::Wrapper";
4511 case X86ISD::S2VEC: return "X86ISD::S2VEC";
4512 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
4513 case X86ISD::PINSRW: return "X86ISD::PINSRW";
4514 case X86ISD::FMAX: return "X86ISD::FMAX";
4515 case X86ISD::FMIN: return "X86ISD::FMIN";
4519 /// isLegalAddressImmediate - Return true if the integer value or
4520 /// GlobalValue can be used as the offset of the target addressing mode.
4521 bool X86TargetLowering::isLegalAddressImmediate(int64_t V) const {
4522 // X86 allows a sign-extended 32-bit immediate field.
4523 return (V > -(1LL << 32) && V < (1LL << 32)-1);
4526 bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
4527 // In 64-bit mode, GV is 64-bit so it won't fit in the 32-bit displacement
4528 // field unless we are in small code model.
4529 if (Subtarget->is64Bit() &&
4530 getTargetMachine().getCodeModel() != CodeModel::Small)
4533 return (!Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false));
4536 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4537 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4538 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4539 /// are assumed to be legal.
4541 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
4542 // Only do shuffles on 128-bit vector types for now.
4543 if (MVT::getSizeInBits(VT) == 64) return false;
4544 return (Mask.Val->getNumOperands() <= 4 ||
4545 isSplatMask(Mask.Val) ||
4546 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
4547 X86::isUNPCKLMask(Mask.Val) ||
4548 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
4549 X86::isUNPCKHMask(Mask.Val));
4552 bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
4554 SelectionDAG &DAG) const {
4555 unsigned NumElts = BVOps.size();
4556 // Only do shuffles on 128-bit vector types for now.
4557 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
4558 if (NumElts == 2) return true;
4560 return (isMOVLMask(&BVOps[0], 4) ||
4561 isCommutedMOVL(&BVOps[0], 4, true) ||
4562 isSHUFPMask(&BVOps[0], 4) ||
4563 isCommutedSHUFP(&BVOps[0], 4));
4568 //===----------------------------------------------------------------------===//
4569 // X86 Scheduler Hooks
4570 //===----------------------------------------------------------------------===//
4573 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
4574 MachineBasicBlock *BB) {
4575 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4576 switch (MI->getOpcode()) {
4577 default: assert(false && "Unexpected instr type to insert");
4578 case X86::CMOV_FR32:
4579 case X86::CMOV_FR64:
4580 case X86::CMOV_V4F32:
4581 case X86::CMOV_V2F64:
4582 case X86::CMOV_V2I64: {
4583 // To "insert" a SELECT_CC instruction, we actually have to insert the
4584 // diamond control-flow pattern. The incoming instruction knows the
4585 // destination vreg to set, the condition code register to branch on, the
4586 // true/false values to select between, and a branch opcode to use.
4587 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4588 ilist<MachineBasicBlock>::iterator It = BB;
4594 // cmpTY ccX, r1, r2
4596 // fallthrough --> copy0MBB
4597 MachineBasicBlock *thisMBB = BB;
4598 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
4599 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
4601 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
4602 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
4603 MachineFunction *F = BB->getParent();
4604 F->getBasicBlockList().insert(It, copy0MBB);
4605 F->getBasicBlockList().insert(It, sinkMBB);
4606 // Update machine-CFG edges by first adding all successors of the current
4607 // block to the new block which will contain the Phi node for the select.
4608 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
4609 e = BB->succ_end(); i != e; ++i)
4610 sinkMBB->addSuccessor(*i);
4611 // Next, remove all successors of the current block, and add the true
4612 // and fallthrough blocks as its successors.
4613 while(!BB->succ_empty())
4614 BB->removeSuccessor(BB->succ_begin());
4615 BB->addSuccessor(copy0MBB);
4616 BB->addSuccessor(sinkMBB);
4619 // %FalseValue = ...
4620 // # fallthrough to sinkMBB
4623 // Update machine-CFG edges
4624 BB->addSuccessor(sinkMBB);
4627 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4630 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
4631 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4632 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4634 delete MI; // The pseudo instruction is gone now.
4638 case X86::FP_TO_INT16_IN_MEM:
4639 case X86::FP_TO_INT32_IN_MEM:
4640 case X86::FP_TO_INT64_IN_MEM: {
4641 // Change the floating point control register to use "round towards zero"
4642 // mode when truncating to an integer value.
4643 MachineFunction *F = BB->getParent();
4644 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
4645 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
4647 // Load the old value of the high byte of the control word...
4649 F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass);
4650 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
4652 // Set the high part to be round to zero...
4653 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
4656 // Reload the modified control word now...
4657 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4659 // Restore the memory image of control word to original value
4660 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
4663 // Get the X86 opcode to use.
4665 switch (MI->getOpcode()) {
4666 default: assert(0 && "illegal opcode!");
4667 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
4668 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
4669 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
4673 MachineOperand &Op = MI->getOperand(0);
4674 if (Op.isRegister()) {
4675 AM.BaseType = X86AddressMode::RegBase;
4676 AM.Base.Reg = Op.getReg();
4678 AM.BaseType = X86AddressMode::FrameIndexBase;
4679 AM.Base.FrameIndex = Op.getFrameIndex();
4681 Op = MI->getOperand(1);
4682 if (Op.isImmediate())
4683 AM.Scale = Op.getImm();
4684 Op = MI->getOperand(2);
4685 if (Op.isImmediate())
4686 AM.IndexReg = Op.getImm();
4687 Op = MI->getOperand(3);
4688 if (Op.isGlobalAddress()) {
4689 AM.GV = Op.getGlobal();
4691 AM.Disp = Op.getImm();
4693 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
4694 .addReg(MI->getOperand(4).getReg());
4696 // Reload the original control word now.
4697 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4699 delete MI; // The pseudo instruction is gone now.
4705 //===----------------------------------------------------------------------===//
4706 // X86 Optimization Hooks
4707 //===----------------------------------------------------------------------===//
4709 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
4711 uint64_t &KnownZero,
4713 unsigned Depth) const {
4714 unsigned Opc = Op.getOpcode();
4715 assert((Opc >= ISD::BUILTIN_OP_END ||
4716 Opc == ISD::INTRINSIC_WO_CHAIN ||
4717 Opc == ISD::INTRINSIC_W_CHAIN ||
4718 Opc == ISD::INTRINSIC_VOID) &&
4719 "Should use MaskedValueIsZero if you don't know whether Op"
4720 " is a target node!");
4722 KnownZero = KnownOne = 0; // Don't know anything.
4726 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
4731 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4732 /// element of the result of the vector shuffle.
4733 static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
4734 MVT::ValueType VT = N->getValueType(0);
4735 SDOperand PermMask = N->getOperand(2);
4736 unsigned NumElems = PermMask.getNumOperands();
4737 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1);
4739 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4741 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT));
4742 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
4743 SDOperand Idx = PermMask.getOperand(i);
4744 if (Idx.getOpcode() == ISD::UNDEF)
4745 return DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT));
4746 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
4751 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
4752 /// node is a GlobalAddress + an offset.
4753 static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
4754 unsigned Opc = N->getOpcode();
4755 if (Opc == X86ISD::Wrapper) {
4756 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
4757 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
4760 } else if (Opc == ISD::ADD) {
4761 SDOperand N1 = N->getOperand(0);
4762 SDOperand N2 = N->getOperand(1);
4763 if (isGAPlusOffset(N1.Val, GA, Offset)) {
4764 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
4766 Offset += V->getSignExtended();
4769 } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
4770 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
4772 Offset += V->getSignExtended();
4780 /// isConsecutiveLoad - Returns true if N is loading from an address of Base
4782 static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
4783 MachineFrameInfo *MFI) {
4784 if (N->getOperand(0).Val != Base->getOperand(0).Val)
4787 SDOperand Loc = N->getOperand(1);
4788 SDOperand BaseLoc = Base->getOperand(1);
4789 if (Loc.getOpcode() == ISD::FrameIndex) {
4790 if (BaseLoc.getOpcode() != ISD::FrameIndex)
4792 int FI = dyn_cast<FrameIndexSDNode>(Loc)->getIndex();
4793 int BFI = dyn_cast<FrameIndexSDNode>(BaseLoc)->getIndex();
4794 int FS = MFI->getObjectSize(FI);
4795 int BFS = MFI->getObjectSize(BFI);
4796 if (FS != BFS || FS != Size) return false;
4797 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
4799 GlobalValue *GV1 = NULL;
4800 GlobalValue *GV2 = NULL;
4801 int64_t Offset1 = 0;
4802 int64_t Offset2 = 0;
4803 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
4804 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
4805 if (isGA1 && isGA2 && GV1 == GV2)
4806 return Offset1 == (Offset2 + Dist*Size);
4812 static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI,
4813 const X86Subtarget *Subtarget) {
4816 if (isGAPlusOffset(Base, GV, Offset))
4817 return (GV->getAlignment() >= 16 && (Offset % 16) == 0);
4819 assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!");
4820 int BFI = dyn_cast<FrameIndexSDNode>(Base)->getIndex();
4822 // Fixed objects do not specify alignment, however the offsets are known.
4823 return ((Subtarget->getStackAlignment() % 16) == 0 &&
4824 (MFI->getObjectOffset(BFI) % 16) == 0);
4826 return MFI->getObjectAlignment(BFI) >= 16;
4832 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
4833 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
4834 /// if the load addresses are consecutive, non-overlapping, and in the right
4836 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
4837 const X86Subtarget *Subtarget) {
4838 MachineFunction &MF = DAG.getMachineFunction();
4839 MachineFrameInfo *MFI = MF.getFrameInfo();
4840 MVT::ValueType VT = N->getValueType(0);
4841 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
4842 SDOperand PermMask = N->getOperand(2);
4843 int NumElems = (int)PermMask.getNumOperands();
4844 SDNode *Base = NULL;
4845 for (int i = 0; i < NumElems; ++i) {
4846 SDOperand Idx = PermMask.getOperand(i);
4847 if (Idx.getOpcode() == ISD::UNDEF) {
4848 if (!Base) return SDOperand();
4851 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
4852 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
4856 else if (!isConsecutiveLoad(Arg.Val, Base,
4857 i, MVT::getSizeInBits(EVT)/8,MFI))
4862 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
4864 LoadSDNode *LD = cast<LoadSDNode>(Base);
4865 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
4866 LD->getSrcValueOffset());
4868 // Just use movups, it's shorter.
4869 SDVTList Tys = DAG.getVTList(MVT::v4f32, MVT::Other);
4870 SmallVector<SDOperand, 3> Ops;
4871 Ops.push_back(Base->getOperand(0));
4872 Ops.push_back(Base->getOperand(1));
4873 Ops.push_back(Base->getOperand(2));
4874 return DAG.getNode(ISD::BIT_CONVERT, VT,
4875 DAG.getNode(X86ISD::LOAD_UA, Tys, &Ops[0], Ops.size()));
4879 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
4880 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
4881 const X86Subtarget *Subtarget) {
4882 SDOperand Cond = N->getOperand(0);
4884 // If we have SSE[12] support, try to form min/max nodes.
4885 if (Subtarget->hasSSE2() &&
4886 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
4887 if (Cond.getOpcode() == ISD::SETCC) {
4888 // Get the LHS/RHS of the select.
4889 SDOperand LHS = N->getOperand(1);
4890 SDOperand RHS = N->getOperand(2);
4891 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
4893 unsigned Opcode = 0;
4894 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
4897 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
4900 if (!UnsafeFPMath) break;
4902 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
4904 Opcode = X86ISD::FMIN;
4907 case ISD::SETOGT: // (X > Y) ? X : Y -> max
4910 if (!UnsafeFPMath) break;
4912 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
4914 Opcode = X86ISD::FMAX;
4917 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
4920 case ISD::SETOGT: // (X > Y) ? Y : X -> min
4923 if (!UnsafeFPMath) break;
4925 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
4927 Opcode = X86ISD::FMIN;
4930 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
4933 if (!UnsafeFPMath) break;
4935 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
4937 Opcode = X86ISD::FMAX;
4943 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
4952 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
4953 DAGCombinerInfo &DCI) const {
4954 SelectionDAG &DAG = DCI.DAG;
4955 switch (N->getOpcode()) {
4957 case ISD::VECTOR_SHUFFLE:
4958 return PerformShuffleCombine(N, DAG, Subtarget);
4960 return PerformSELECTCombine(N, DAG, Subtarget);
4966 //===----------------------------------------------------------------------===//
4967 // X86 Inline Assembly Support
4968 //===----------------------------------------------------------------------===//
4970 /// getConstraintType - Given a constraint letter, return the type of
4971 /// constraint it is for this target.
4972 X86TargetLowering::ConstraintType
4973 X86TargetLowering::getConstraintType(char ConstraintLetter) const {
4974 switch (ConstraintLetter) {
4983 return C_RegisterClass;
4984 default: return TargetLowering::getConstraintType(ConstraintLetter);
4988 /// isOperandValidForConstraint - Return the specified operand (possibly
4989 /// modified) if the specified SDOperand is valid for the specified target
4990 /// constraint letter, otherwise return null.
4991 SDOperand X86TargetLowering::
4992 isOperandValidForConstraint(SDOperand Op, char Constraint, SelectionDAG &DAG) {
4993 switch (Constraint) {
4996 // Literal immediates are always ok.
4997 if (isa<ConstantSDNode>(Op)) return Op;
4999 // If we are in non-pic codegen mode, we allow the address of a global to
5000 // be used with 'i'.
5001 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
5002 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
5003 return SDOperand(0, 0);
5005 if (GA->getOpcode() != ISD::TargetGlobalAddress)
5006 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5011 // Otherwise, not valid for this mode.
5012 return SDOperand(0, 0);
5014 return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG);
5018 std::vector<unsigned> X86TargetLowering::
5019 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5020 MVT::ValueType VT) const {
5021 if (Constraint.size() == 1) {
5022 // FIXME: not handling fp-stack yet!
5023 // FIXME: not handling MMX registers yet ('y' constraint).
5024 switch (Constraint[0]) { // GCC X86 Constraint Letters
5025 default: break; // Unknown constraint letter
5026 case 'A': // EAX/EDX
5027 if (VT == MVT::i32 || VT == MVT::i64)
5028 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
5030 case 'r': // GENERAL_REGS
5031 case 'R': // LEGACY_REGS
5032 if (VT == MVT::i64 && Subtarget->is64Bit())
5033 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
5034 X86::RSI, X86::RDI, X86::RBP, X86::RSP,
5035 X86::R8, X86::R9, X86::R10, X86::R11,
5036 X86::R12, X86::R13, X86::R14, X86::R15, 0);
5038 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
5039 X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0);
5040 else if (VT == MVT::i16)
5041 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
5042 X86::SI, X86::DI, X86::BP, X86::SP, 0);
5043 else if (VT == MVT::i8)
5044 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
5046 case 'l': // INDEX_REGS
5048 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
5049 X86::ESI, X86::EDI, X86::EBP, 0);
5050 else if (VT == MVT::i16)
5051 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
5052 X86::SI, X86::DI, X86::BP, 0);
5053 else if (VT == MVT::i8)
5054 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
5056 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
5059 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
5060 else if (VT == MVT::i16)
5061 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
5062 else if (VT == MVT::i8)
5063 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
5065 case 'x': // SSE_REGS if SSE1 allowed
5066 if (Subtarget->hasSSE1())
5067 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
5068 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
5070 return std::vector<unsigned>();
5071 case 'Y': // SSE_REGS if SSE2 allowed
5072 if (Subtarget->hasSSE2())
5073 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
5074 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
5076 return std::vector<unsigned>();
5080 return std::vector<unsigned>();
5083 std::pair<unsigned, const TargetRegisterClass*>
5084 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5085 MVT::ValueType VT) const {
5086 // Use the default implementation in TargetLowering to convert the register
5087 // constraint into a member of a register class.
5088 std::pair<unsigned, const TargetRegisterClass*> Res;
5089 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5091 // Not found as a standard register?
5092 if (Res.second == 0) {
5093 // GCC calls "st(0)" just plain "st".
5094 if (StringsEqualNoCase("{st}", Constraint)) {
5095 Res.first = X86::ST0;
5096 Res.second = X86::RSTRegisterClass;
5102 // Otherwise, check to see if this is a register class of the wrong value
5103 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
5104 // turn into {ax},{dx}.
5105 if (Res.second->hasType(VT))
5106 return Res; // Correct type already, nothing to do.
5108 // All of the single-register GCC register classes map their values onto
5109 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
5110 // really want an 8-bit or 32-bit register, map to the appropriate register
5111 // class and return the appropriate register.
5112 if (Res.second != X86::GR16RegisterClass)
5115 if (VT == MVT::i8) {
5116 unsigned DestReg = 0;
5117 switch (Res.first) {
5119 case X86::AX: DestReg = X86::AL; break;
5120 case X86::DX: DestReg = X86::DL; break;
5121 case X86::CX: DestReg = X86::CL; break;
5122 case X86::BX: DestReg = X86::BL; break;
5125 Res.first = DestReg;
5126 Res.second = Res.second = X86::GR8RegisterClass;
5128 } else if (VT == MVT::i32) {
5129 unsigned DestReg = 0;
5130 switch (Res.first) {
5132 case X86::AX: DestReg = X86::EAX; break;
5133 case X86::DX: DestReg = X86::EDX; break;
5134 case X86::CX: DestReg = X86::ECX; break;
5135 case X86::BX: DestReg = X86::EBX; break;
5136 case X86::SI: DestReg = X86::ESI; break;
5137 case X86::DI: DestReg = X86::EDI; break;
5138 case X86::BP: DestReg = X86::EBP; break;
5139 case X86::SP: DestReg = X86::ESP; break;
5142 Res.first = DestReg;
5143 Res.second = Res.second = X86::GR32RegisterClass;
5145 } else if (VT == MVT::i64) {
5146 unsigned DestReg = 0;
5147 switch (Res.first) {
5149 case X86::AX: DestReg = X86::RAX; break;
5150 case X86::DX: DestReg = X86::RDX; break;
5151 case X86::CX: DestReg = X86::RCX; break;
5152 case X86::BX: DestReg = X86::RBX; break;
5153 case X86::SI: DestReg = X86::RSI; break;
5154 case X86::DI: DestReg = X86::RDI; break;
5155 case X86::BP: DestReg = X86::RBP; break;
5156 case X86::SP: DestReg = X86::RSP; break;
5159 Res.first = DestReg;
5160 Res.second = Res.second = X86::GR64RegisterClass;