1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
71 const X86Subtarget &STI)
72 : TargetLowering(TM), Subtarget(&STI) {
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
77 // Set up the TargetLowering object.
79 // X86 is weird. It always uses i8 for shift amounts and setcc results.
80 setBooleanContents(ZeroOrOneBooleanContent);
81 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
82 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
84 // For 64-bit, since we have so many registers, use the ILP scheduler.
85 // For 32-bit, use the register pressure specific scheduling.
86 // For Atom, always use ILP scheduling.
87 if (Subtarget->isAtom())
88 setSchedulingPreference(Sched::ILP);
89 else if (Subtarget->is64Bit())
90 setSchedulingPreference(Sched::ILP);
92 setSchedulingPreference(Sched::RegPressure);
93 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
94 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
96 // Bypass expensive divides on Atom when compiling with O2.
97 if (TM.getOptLevel() >= CodeGenOpt::Default) {
98 if (Subtarget->hasSlowDivide32())
99 addBypassSlowDiv(32, 8);
100 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
101 addBypassSlowDiv(64, 16);
104 if (Subtarget->isTargetKnownWindowsMSVC()) {
105 // Setup Windows compiler runtime calls.
106 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
107 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
108 setLibcallName(RTLIB::SREM_I64, "_allrem");
109 setLibcallName(RTLIB::UREM_I64, "_aullrem");
110 setLibcallName(RTLIB::MUL_I64, "_allmul");
111 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
112 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
118 if (Subtarget->isTargetDarwin()) {
119 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
120 setUseUnderscoreSetJmp(false);
121 setUseUnderscoreLongJmp(false);
122 } else if (Subtarget->isTargetWindowsGNU()) {
123 // MS runtime is weird: it exports _setjmp, but longjmp!
124 setUseUnderscoreSetJmp(true);
125 setUseUnderscoreLongJmp(false);
127 setUseUnderscoreSetJmp(true);
128 setUseUnderscoreLongJmp(true);
131 // Set up the register classes.
132 addRegisterClass(MVT::i8, &X86::GR8RegClass);
133 addRegisterClass(MVT::i16, &X86::GR16RegClass);
134 addRegisterClass(MVT::i32, &X86::GR32RegClass);
135 if (Subtarget->is64Bit())
136 addRegisterClass(MVT::i64, &X86::GR64RegClass);
138 for (MVT VT : MVT::integer_valuetypes())
139 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
141 // We don't accept any truncstore of integer registers.
142 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
143 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
145 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
146 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
147 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
149 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
151 // SETOEQ and SETUNE require checking two conditions.
152 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
153 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
155 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
159 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
161 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
162 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
165 if (Subtarget->is64Bit()) {
166 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
167 // f32/f64 are legal, f80 is custom.
168 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
170 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
172 } else if (!Subtarget->useSoftFloat()) {
173 // We have an algorithm for SSE2->double, and we turn this into a
174 // 64-bit FILD followed by conditional FADD for other targets.
175 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
176 // We have an algorithm for SSE2, and we turn this into a 64-bit
177 // FILD or VCVTUSI2SS/SD for other targets.
178 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
181 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
183 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
184 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
186 if (!Subtarget->useSoftFloat()) {
187 // SSE has no i16 to fp conversion, only i32
188 if (X86ScalarSSEf32) {
189 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
190 // f32 and f64 cases are Legal, f80 case is not
191 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
193 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
197 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
201 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
202 // are Legal, f80 is custom lowered.
203 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
204 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
206 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
208 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
209 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
211 if (X86ScalarSSEf32) {
212 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
213 // f32 and f64 cases are Legal, f80 case is not
214 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
216 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
220 // Handle FP_TO_UINT by promoting the destination to a larger signed
222 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
223 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
224 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
226 if (Subtarget->is64Bit()) {
227 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
228 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
229 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
230 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
232 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
233 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
235 } else if (!Subtarget->useSoftFloat()) {
236 // Since AVX is a superset of SSE3, only check for SSE here.
237 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
238 // Expand FP_TO_UINT into a select.
239 // FIXME: We would like to use a Custom expander here eventually to do
240 // the optimal thing for SSE vs. the default expansion in the legalizer.
241 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
243 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
244 // With SSE3 we can use fisttpll to convert to a signed i64; without
245 // SSE, we're stuck with a fistpll.
246 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
248 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
251 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
252 if (!X86ScalarSSEf64) {
253 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
254 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
255 if (Subtarget->is64Bit()) {
256 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
257 // Without SSE, i64->f64 goes through memory.
258 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
262 // Scalar integer divide and remainder are lowered to use operations that
263 // produce two results, to match the available instructions. This exposes
264 // the two-result form to trivial CSE, which is able to combine x/y and x%y
265 // into a single instruction.
267 // Scalar integer multiply-high is also lowered to use two-result
268 // operations, to match the available instructions. However, plain multiply
269 // (low) operations are left as Legal, as there are single-result
270 // instructions for this in x86. Using the two-result multiply instructions
271 // when both high and low results are needed must be arranged by dagcombine.
272 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
273 setOperationAction(ISD::MULHS, VT, Expand);
274 setOperationAction(ISD::MULHU, VT, Expand);
275 setOperationAction(ISD::SDIV, VT, Expand);
276 setOperationAction(ISD::UDIV, VT, Expand);
277 setOperationAction(ISD::SREM, VT, Expand);
278 setOperationAction(ISD::UREM, VT, Expand);
280 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
281 setOperationAction(ISD::ADDC, VT, Custom);
282 setOperationAction(ISD::ADDE, VT, Custom);
283 setOperationAction(ISD::SUBC, VT, Custom);
284 setOperationAction(ISD::SUBE, VT, Custom);
287 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
288 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
289 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
290 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
291 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
292 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
293 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
294 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
295 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
296 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
297 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
298 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
299 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
300 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
301 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
303 if (Subtarget->is64Bit())
304 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
305 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
307 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
308 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
310 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
311 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
312 // is. We should promote the value to 64-bits to solve this.
313 // This is what the CRT headers do - `fmodf` is an inline header
314 // function casting to f64 and calling `fmod`.
315 setOperationAction(ISD::FREM , MVT::f32 , Promote);
317 setOperationAction(ISD::FREM , MVT::f32 , Expand);
320 setOperationAction(ISD::FREM , MVT::f64 , Expand);
321 setOperationAction(ISD::FREM , MVT::f80 , Expand);
322 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
324 // Promote the i8 variants and force them on up to i32 which has a shorter
326 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
327 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
328 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
330 if (Subtarget->hasBMI()) {
331 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
332 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
333 if (Subtarget->is64Bit())
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
336 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
337 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
338 if (Subtarget->is64Bit())
339 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
342 if (Subtarget->hasLZCNT()) {
343 // When promoting the i8 variants, force them to i32 for a shorter
345 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
346 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
347 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
350 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
351 if (Subtarget->is64Bit())
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
354 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
355 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
356 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
358 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
360 if (Subtarget->is64Bit()) {
361 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
362 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
366 // Special handling for half-precision floating point conversions.
367 // If we don't have F16C support, then lower half float conversions
368 // into library calls.
369 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
370 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
371 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
374 // There's never any support for operations beyond MVT::f32.
375 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
376 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
377 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
378 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
380 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
381 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
383 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
384 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
387 if (Subtarget->hasPOPCNT()) {
388 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
390 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
391 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
392 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
393 if (Subtarget->is64Bit())
394 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
397 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
399 if (!Subtarget->hasMOVBE())
400 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
402 // These should be promoted to a larger select which is supported.
403 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
404 // X86 wants to expand cmov itself.
405 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
406 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
407 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
408 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
409 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
411 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
412 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
414 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
415 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
417 if (Subtarget->is64Bit()) {
418 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
421 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
422 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
423 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
424 // support continuation, user-level threading, and etc.. As a result, no
425 // other SjLj exception interfaces are implemented and please don't build
426 // your own exception handling based on them.
427 // LLVM/Clang supports zero-cost DWARF exception handling.
428 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
429 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
432 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
433 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
434 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
435 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
436 if (Subtarget->is64Bit())
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
438 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
439 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
440 if (Subtarget->is64Bit()) {
441 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
442 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
443 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
444 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
445 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
447 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
448 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
449 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
450 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
451 if (Subtarget->is64Bit()) {
452 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
453 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
454 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
457 if (Subtarget->hasSSE1())
458 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
460 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
462 // Expand certain atomics
463 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
464 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
465 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
466 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
469 if (Subtarget->hasCmpxchg16b()) {
470 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
473 // FIXME - use subtarget debug flags
474 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
475 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
476 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
479 if (Subtarget->isTarget64BitLP64()) {
480 setExceptionPointerRegister(X86::RAX);
481 setExceptionSelectorRegister(X86::RDX);
483 setExceptionPointerRegister(X86::EAX);
484 setExceptionSelectorRegister(X86::EDX);
486 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
487 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
489 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
490 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
492 setOperationAction(ISD::TRAP, MVT::Other, Legal);
493 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
495 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
496 setOperationAction(ISD::VASTART , MVT::Other, Custom);
497 setOperationAction(ISD::VAEND , MVT::Other, Expand);
498 if (Subtarget->is64Bit()) {
499 setOperationAction(ISD::VAARG , MVT::Other, Custom);
500 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
502 // TargetInfo::CharPtrBuiltinVaList
503 setOperationAction(ISD::VAARG , MVT::Other, Expand);
504 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
507 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
508 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
510 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
512 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
513 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
514 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
516 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
517 // f32 and f64 use SSE.
518 // Set up the FP register classes.
519 addRegisterClass(MVT::f32, &X86::FR32RegClass);
520 addRegisterClass(MVT::f64, &X86::FR64RegClass);
522 // Use ANDPD to simulate FABS.
523 setOperationAction(ISD::FABS , MVT::f64, Custom);
524 setOperationAction(ISD::FABS , MVT::f32, Custom);
526 // Use XORP to simulate FNEG.
527 setOperationAction(ISD::FNEG , MVT::f64, Custom);
528 setOperationAction(ISD::FNEG , MVT::f32, Custom);
530 // Use ANDPD and ORPD to simulate FCOPYSIGN.
531 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
532 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
534 // Lower this to FGETSIGNx86 plus an AND.
535 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
536 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
538 // We don't support sin/cos/fmod
539 setOperationAction(ISD::FSIN , MVT::f64, Expand);
540 setOperationAction(ISD::FCOS , MVT::f64, Expand);
541 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
542 setOperationAction(ISD::FSIN , MVT::f32, Expand);
543 setOperationAction(ISD::FCOS , MVT::f32, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
546 // Expand FP immediates into loads from the stack, except for the special
548 addLegalFPImmediate(APFloat(+0.0)); // xorpd
549 addLegalFPImmediate(APFloat(+0.0f)); // xorps
550 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
551 // Use SSE for f32, x87 for f64.
552 // Set up the FP register classes.
553 addRegisterClass(MVT::f32, &X86::FR32RegClass);
554 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
556 // Use ANDPS to simulate FABS.
557 setOperationAction(ISD::FABS , MVT::f32, Custom);
559 // Use XORP to simulate FNEG.
560 setOperationAction(ISD::FNEG , MVT::f32, Custom);
562 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
564 // Use ANDPS and ORPS to simulate FCOPYSIGN.
565 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
566 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
568 // We don't support sin/cos/fmod
569 setOperationAction(ISD::FSIN , MVT::f32, Expand);
570 setOperationAction(ISD::FCOS , MVT::f32, Expand);
571 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
573 // Special cases we handle for FP constants.
574 addLegalFPImmediate(APFloat(+0.0f)); // xorps
575 addLegalFPImmediate(APFloat(+0.0)); // FLD0
576 addLegalFPImmediate(APFloat(+1.0)); // FLD1
577 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
578 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
580 if (!TM.Options.UnsafeFPMath) {
581 setOperationAction(ISD::FSIN , MVT::f64, Expand);
582 setOperationAction(ISD::FCOS , MVT::f64, Expand);
583 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
585 } else if (!Subtarget->useSoftFloat()) {
586 // f32 and f64 in x87.
587 // Set up the FP register classes.
588 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
589 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
591 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
592 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
593 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
594 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
596 if (!TM.Options.UnsafeFPMath) {
597 setOperationAction(ISD::FSIN , MVT::f64, Expand);
598 setOperationAction(ISD::FSIN , MVT::f32, Expand);
599 setOperationAction(ISD::FCOS , MVT::f64, Expand);
600 setOperationAction(ISD::FCOS , MVT::f32, Expand);
601 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
602 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
604 addLegalFPImmediate(APFloat(+0.0)); // FLD0
605 addLegalFPImmediate(APFloat(+1.0)); // FLD1
606 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
607 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
608 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
614 // We don't support FMA.
615 setOperationAction(ISD::FMA, MVT::f64, Expand);
616 setOperationAction(ISD::FMA, MVT::f32, Expand);
618 // Long double always uses X87.
619 if (!Subtarget->useSoftFloat()) {
620 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
621 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
622 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
624 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
625 addLegalFPImmediate(TmpFlt); // FLD0
627 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
630 APFloat TmpFlt2(+1.0);
631 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
633 addLegalFPImmediate(TmpFlt2); // FLD1
634 TmpFlt2.changeSign();
635 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
638 if (!TM.Options.UnsafeFPMath) {
639 setOperationAction(ISD::FSIN , MVT::f80, Expand);
640 setOperationAction(ISD::FCOS , MVT::f80, Expand);
641 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
644 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
645 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
646 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
647 setOperationAction(ISD::FRINT, MVT::f80, Expand);
648 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
649 setOperationAction(ISD::FMA, MVT::f80, Expand);
652 // Always use a library call for pow.
653 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
654 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
655 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
657 setOperationAction(ISD::FLOG, MVT::f80, Expand);
658 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
659 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
660 setOperationAction(ISD::FEXP, MVT::f80, Expand);
661 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
662 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
663 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
665 // First set operation action for all vector types to either promote
666 // (for widening) or expand (for scalarization). Then we will selectively
667 // turn on ones that can be effectively codegen'd.
668 for (MVT VT : MVT::vector_valuetypes()) {
669 setOperationAction(ISD::ADD , VT, Expand);
670 setOperationAction(ISD::SUB , VT, Expand);
671 setOperationAction(ISD::FADD, VT, Expand);
672 setOperationAction(ISD::FNEG, VT, Expand);
673 setOperationAction(ISD::FSUB, VT, Expand);
674 setOperationAction(ISD::MUL , VT, Expand);
675 setOperationAction(ISD::FMUL, VT, Expand);
676 setOperationAction(ISD::SDIV, VT, Expand);
677 setOperationAction(ISD::UDIV, VT, Expand);
678 setOperationAction(ISD::FDIV, VT, Expand);
679 setOperationAction(ISD::SREM, VT, Expand);
680 setOperationAction(ISD::UREM, VT, Expand);
681 setOperationAction(ISD::LOAD, VT, Expand);
682 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
683 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
684 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
685 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
686 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
687 setOperationAction(ISD::FABS, VT, Expand);
688 setOperationAction(ISD::FSIN, VT, Expand);
689 setOperationAction(ISD::FSINCOS, VT, Expand);
690 setOperationAction(ISD::FCOS, VT, Expand);
691 setOperationAction(ISD::FSINCOS, VT, Expand);
692 setOperationAction(ISD::FREM, VT, Expand);
693 setOperationAction(ISD::FMA, VT, Expand);
694 setOperationAction(ISD::FPOWI, VT, Expand);
695 setOperationAction(ISD::FSQRT, VT, Expand);
696 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
697 setOperationAction(ISD::FFLOOR, VT, Expand);
698 setOperationAction(ISD::FCEIL, VT, Expand);
699 setOperationAction(ISD::FTRUNC, VT, Expand);
700 setOperationAction(ISD::FRINT, VT, Expand);
701 setOperationAction(ISD::FNEARBYINT, VT, Expand);
702 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHS, VT, Expand);
704 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
705 setOperationAction(ISD::MULHU, VT, Expand);
706 setOperationAction(ISD::SDIVREM, VT, Expand);
707 setOperationAction(ISD::UDIVREM, VT, Expand);
708 setOperationAction(ISD::FPOW, VT, Expand);
709 setOperationAction(ISD::CTPOP, VT, Expand);
710 setOperationAction(ISD::CTTZ, VT, Expand);
711 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
712 setOperationAction(ISD::CTLZ, VT, Expand);
713 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
714 setOperationAction(ISD::SHL, VT, Expand);
715 setOperationAction(ISD::SRA, VT, Expand);
716 setOperationAction(ISD::SRL, VT, Expand);
717 setOperationAction(ISD::ROTL, VT, Expand);
718 setOperationAction(ISD::ROTR, VT, Expand);
719 setOperationAction(ISD::BSWAP, VT, Expand);
720 setOperationAction(ISD::SETCC, VT, Expand);
721 setOperationAction(ISD::FLOG, VT, Expand);
722 setOperationAction(ISD::FLOG2, VT, Expand);
723 setOperationAction(ISD::FLOG10, VT, Expand);
724 setOperationAction(ISD::FEXP, VT, Expand);
725 setOperationAction(ISD::FEXP2, VT, Expand);
726 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
727 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
728 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
729 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
730 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
731 setOperationAction(ISD::TRUNCATE, VT, Expand);
732 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
733 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
734 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
735 setOperationAction(ISD::VSELECT, VT, Expand);
736 setOperationAction(ISD::SELECT_CC, VT, Expand);
737 for (MVT InnerVT : MVT::vector_valuetypes()) {
738 setTruncStoreAction(InnerVT, VT, Expand);
740 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
741 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
743 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
744 // types, we have to deal with them whether we ask for Expansion or not.
745 // Setting Expand causes its own optimisation problems though, so leave
747 if (VT.getVectorElementType() == MVT::i1)
748 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
750 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
751 // split/scalarized right now.
752 if (VT.getVectorElementType() == MVT::f16)
753 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
757 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
758 // with -msoft-float, disable use of MMX as well.
759 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
760 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
761 // No operations on x86mmx supported, everything uses intrinsics.
764 // MMX-sized vectors (other than x86mmx) are expected to be expanded
765 // into smaller operations.
766 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
767 setOperationAction(ISD::MULHS, MMXTy, Expand);
768 setOperationAction(ISD::AND, MMXTy, Expand);
769 setOperationAction(ISD::OR, MMXTy, Expand);
770 setOperationAction(ISD::XOR, MMXTy, Expand);
771 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
772 setOperationAction(ISD::SELECT, MMXTy, Expand);
773 setOperationAction(ISD::BITCAST, MMXTy, Expand);
775 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
777 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
778 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
780 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
781 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
782 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
783 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
784 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
785 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
786 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
787 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
788 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
789 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
790 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
791 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
792 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
793 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
796 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
797 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
799 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
800 // registers cannot be used even for integer operations.
801 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
802 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
803 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
804 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
806 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
807 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
808 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
809 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
810 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
811 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
812 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
813 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
814 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
815 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
816 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
817 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
818 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
819 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
820 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
821 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
822 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
823 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
824 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
825 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
826 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
827 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
828 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
830 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
831 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
832 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
833 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
835 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
836 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
837 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
838 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
840 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
841 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
843 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
844 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
846 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
847 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
848 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
849 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
851 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
852 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
853 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
854 // ISD::CTTZ v2i64 - scalarization is faster.
855 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
856 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
857 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
858 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
860 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
861 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
862 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
863 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
864 setOperationAction(ISD::VSELECT, VT, Custom);
865 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
868 // We support custom legalizing of sext and anyext loads for specific
869 // memory vector types which we can load as a scalar (or sequence of
870 // scalars) and extend in-register to a legal 128-bit vector type. For sext
871 // loads these must work with a single scalar load.
872 for (MVT VT : MVT::integer_vector_valuetypes()) {
873 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
874 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
875 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
876 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
877 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
878 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
879 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
880 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
884 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
885 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
886 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
887 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
888 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
889 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
893 if (Subtarget->is64Bit()) {
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
898 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
899 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
900 setOperationAction(ISD::AND, VT, Promote);
901 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
902 setOperationAction(ISD::OR, VT, Promote);
903 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
904 setOperationAction(ISD::XOR, VT, Promote);
905 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
906 setOperationAction(ISD::LOAD, VT, Promote);
907 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
908 setOperationAction(ISD::SELECT, VT, Promote);
909 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
912 // Custom lower v2i64 and v2f64 selects.
913 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
914 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
915 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
916 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
918 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
919 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
921 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
923 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
924 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
925 // As there is no 64-bit GPR available, we need build a special custom
926 // sequence to convert from v2i32 to v2f32.
927 if (!Subtarget->is64Bit())
928 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
930 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
931 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
933 for (MVT VT : MVT::fp_vector_valuetypes())
934 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
936 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
937 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
938 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
941 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
942 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
943 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
944 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
945 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
946 setOperationAction(ISD::FRINT, RoundedTy, Legal);
947 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
950 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
951 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
952 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
953 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
954 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
955 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
956 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
957 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
959 // FIXME: Do we need to handle scalar-to-vector here?
960 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
962 // We directly match byte blends in the backend as they match the VSELECT
964 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
966 // SSE41 brings specific instructions for doing vector sign extend even in
967 // cases where we don't have SRA.
968 for (MVT VT : MVT::integer_vector_valuetypes()) {
969 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
970 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
971 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
974 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
975 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
976 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
977 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
978 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
979 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
982 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
983 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
984 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
985 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
989 // i8 and i16 vectors are custom because the source register and source
990 // source memory operand types are not the same width. f32 vectors are
991 // custom since the immediate controlling the insert encodes additional
993 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
994 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
995 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
998 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
999 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // FIXME: these should be Legal, but that's only for the case where
1004 // the index is constant. For now custom expand to deal with that.
1005 if (Subtarget->is64Bit()) {
1006 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1007 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1011 if (Subtarget->hasSSE2()) {
1012 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1013 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1014 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1016 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1017 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1019 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1020 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1022 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1023 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1025 // In the customized shift lowering, the legal cases in AVX2 will be
1027 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1028 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1030 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1031 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1033 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1034 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1037 if (Subtarget->hasXOP()) {
1038 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1039 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1040 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1041 setOperationAction(ISD::ROTL, MVT::v2i64, Custom);
1042 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1043 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1044 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1045 setOperationAction(ISD::ROTL, MVT::v4i64, Custom);
1048 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1049 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1050 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1051 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1052 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1053 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1054 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1056 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1057 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1058 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1060 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1061 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1062 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1063 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1064 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1065 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1071 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1073 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1074 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1075 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1076 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1077 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1078 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1084 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1086 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1087 // even though v8i16 is a legal type.
1088 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1089 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1090 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1092 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1093 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1094 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1096 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1097 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1099 for (MVT VT : MVT::fp_vector_valuetypes())
1100 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1102 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1103 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1105 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1106 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1108 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1109 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1111 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1112 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1113 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1114 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1116 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1117 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1118 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1120 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1121 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1122 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1123 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1124 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1125 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1126 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1127 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1128 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1129 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1130 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1131 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1133 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1134 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1135 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1136 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1138 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1139 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1140 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1141 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1142 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1143 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1144 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1145 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1147 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1148 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1149 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1151 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1152 setOperationAction(ISD::FMA, MVT::f32, Legal);
1153 setOperationAction(ISD::FMA, MVT::f64, Legal);
1156 if (Subtarget->hasInt256()) {
1157 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1158 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1159 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1160 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1162 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1163 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1164 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1165 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1167 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1168 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1169 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1170 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1173 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1174 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1175 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1177 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1178 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1179 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1180 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1181 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1182 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1183 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1184 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1185 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1186 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1187 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1188 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1190 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1191 // when we have a 256bit-wide blend with immediate.
1192 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1194 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1195 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1196 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1197 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1198 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1199 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1202 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1203 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1204 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1205 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1206 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1209 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1210 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1211 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1212 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1214 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1215 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1216 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1217 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1219 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1220 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1221 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1222 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1224 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1225 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1226 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1227 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1228 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1229 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1230 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1231 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1232 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1233 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1234 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1235 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1238 // In the customized shift lowering, the legal cases in AVX2 will be
1240 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1241 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1243 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1244 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1246 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1247 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1249 // Custom lower several nodes for 256-bit types.
1250 for (MVT VT : MVT::vector_valuetypes()) {
1251 if (VT.getScalarSizeInBits() >= 32) {
1252 setOperationAction(ISD::MLOAD, VT, Legal);
1253 setOperationAction(ISD::MSTORE, VT, Legal);
1255 // Extract subvector is special because the value type
1256 // (result) is 128-bit but the source is 256-bit wide.
1257 if (VT.is128BitVector()) {
1258 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1260 // Do not attempt to custom lower other non-256-bit vectors
1261 if (!VT.is256BitVector())
1264 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1265 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1266 setOperationAction(ISD::VSELECT, VT, Custom);
1267 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1268 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1269 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1270 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1271 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1274 if (Subtarget->hasInt256())
1275 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1277 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1278 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1279 setOperationAction(ISD::AND, VT, Promote);
1280 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1281 setOperationAction(ISD::OR, VT, Promote);
1282 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1283 setOperationAction(ISD::XOR, VT, Promote);
1284 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1285 setOperationAction(ISD::LOAD, VT, Promote);
1286 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1287 setOperationAction(ISD::SELECT, VT, Promote);
1288 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1292 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1293 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1294 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1295 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1296 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1298 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1299 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1300 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1302 for (MVT VT : MVT::fp_vector_valuetypes())
1303 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1305 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1306 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1307 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1308 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1309 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1310 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1311 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1312 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1313 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1314 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1315 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1316 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1318 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1319 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1320 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1321 setOperationAction(ISD::XOR, MVT::i1, Legal);
1322 setOperationAction(ISD::OR, MVT::i1, Legal);
1323 setOperationAction(ISD::AND, MVT::i1, Legal);
1324 setOperationAction(ISD::SUB, MVT::i1, Custom);
1325 setOperationAction(ISD::ADD, MVT::i1, Custom);
1326 setOperationAction(ISD::MUL, MVT::i1, Custom);
1327 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1328 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1329 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1330 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1331 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1333 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1334 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1335 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1336 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1337 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1338 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1340 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1341 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1342 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1343 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1344 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1345 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1346 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1349 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1350 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1351 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1352 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1353 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1354 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1355 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1356 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1357 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1358 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1359 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1360 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1361 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1362 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1363 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1364 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1366 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1367 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1368 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1369 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1370 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1371 if (Subtarget->hasVLX()){
1372 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1373 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1374 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1375 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1376 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1378 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1379 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1380 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1381 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1382 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1384 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1385 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1386 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1387 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1388 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1389 if (Subtarget->hasDQI()) {
1390 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1391 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1393 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1394 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1395 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1396 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1397 if (Subtarget->hasVLX()) {
1398 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1399 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1400 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1401 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1402 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1405 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1408 if (Subtarget->hasVLX()) {
1409 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1411 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1412 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1414 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1415 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1418 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1419 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1420 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1421 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1422 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1423 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1424 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1425 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1426 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1427 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1428 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1429 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1430 if (Subtarget->hasDQI()) {
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1434 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1435 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1436 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1437 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1438 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1439 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1440 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1441 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1442 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1443 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1445 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1446 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1447 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1448 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1449 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1451 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1452 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1454 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1456 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1457 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1458 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1459 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1460 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1461 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1463 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1464 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1465 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1466 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1468 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1469 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1470 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1471 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1472 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1473 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1474 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1475 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1477 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1478 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1480 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1481 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1483 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1485 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1486 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1488 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1489 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1491 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1492 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1494 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1495 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1496 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1497 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1498 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1499 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1501 if (Subtarget->hasCDI()) {
1502 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1503 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1507 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1508 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1509 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1510 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Custom);
1512 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Custom);
1513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Custom);
1514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Custom);
1516 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1517 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1519 if (Subtarget->hasVLX()) {
1520 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1521 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1522 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1523 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1524 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1525 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1526 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1527 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1529 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1530 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1531 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1532 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1534 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1535 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1536 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1537 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1538 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Custom);
1539 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Custom);
1540 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Custom);
1541 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Custom);
1543 } // Subtarget->hasCDI()
1545 if (Subtarget->hasDQI()) {
1546 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1547 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1548 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1550 // Custom lower several nodes.
1551 for (MVT VT : MVT::vector_valuetypes()) {
1552 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1554 setOperationAction(ISD::AND, VT, Legal);
1555 setOperationAction(ISD::OR, VT, Legal);
1556 setOperationAction(ISD::XOR, VT, Legal);
1558 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1559 setOperationAction(ISD::MGATHER, VT, Custom);
1560 setOperationAction(ISD::MSCATTER, VT, Custom);
1562 // Extract subvector is special because the value type
1563 // (result) is 256/128-bit but the source is 512-bit wide.
1564 if (VT.is128BitVector() || VT.is256BitVector()) {
1565 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1567 if (VT.getVectorElementType() == MVT::i1)
1568 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1570 // Do not attempt to custom lower other non-512-bit vectors
1571 if (!VT.is512BitVector())
1574 if (EltSize >= 32) {
1575 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1576 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1577 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1578 setOperationAction(ISD::VSELECT, VT, Legal);
1579 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1580 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1581 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1582 setOperationAction(ISD::MLOAD, VT, Legal);
1583 setOperationAction(ISD::MSTORE, VT, Legal);
1586 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1587 setOperationAction(ISD::SELECT, VT, Promote);
1588 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1592 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1593 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1594 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1596 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1597 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1599 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1600 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1601 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1602 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1603 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1604 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1605 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1606 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1607 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1608 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1609 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1610 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Legal);
1611 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Legal);
1612 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1613 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1614 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1615 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1616 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1617 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1618 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1619 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1620 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1621 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1622 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1623 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1624 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1625 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1626 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1627 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1628 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1629 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1630 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1631 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1632 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1633 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1634 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1635 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1636 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1637 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1638 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1639 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1640 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1642 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1643 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1644 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1645 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1646 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1647 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1648 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1649 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1651 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1652 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1653 if (Subtarget->hasVLX())
1654 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1656 if (Subtarget->hasCDI()) {
1657 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1658 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1659 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Custom);
1660 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);
1663 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1664 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1665 setOperationAction(ISD::VSELECT, VT, Legal);
1669 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1670 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1671 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1673 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1674 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1675 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1676 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1677 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1678 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1679 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1680 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1681 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1682 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1683 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1684 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1686 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1687 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1688 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1689 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1690 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1691 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1692 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1693 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1695 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1696 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1697 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1698 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1699 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1700 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1701 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1702 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1705 // We want to custom lower some of our intrinsics.
1706 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1707 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1708 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1709 if (!Subtarget->is64Bit())
1710 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1712 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1713 // handle type legalization for these operations here.
1715 // FIXME: We really should do custom legalization for addition and
1716 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1717 // than generic legalization for 64-bit multiplication-with-overflow, though.
1718 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1719 if (VT == MVT::i64 && !Subtarget->is64Bit())
1721 // Add/Sub/Mul with overflow operations are custom lowered.
1722 setOperationAction(ISD::SADDO, VT, Custom);
1723 setOperationAction(ISD::UADDO, VT, Custom);
1724 setOperationAction(ISD::SSUBO, VT, Custom);
1725 setOperationAction(ISD::USUBO, VT, Custom);
1726 setOperationAction(ISD::SMULO, VT, Custom);
1727 setOperationAction(ISD::UMULO, VT, Custom);
1730 if (!Subtarget->is64Bit()) {
1731 // These libcalls are not available in 32-bit.
1732 setLibcallName(RTLIB::SHL_I128, nullptr);
1733 setLibcallName(RTLIB::SRL_I128, nullptr);
1734 setLibcallName(RTLIB::SRA_I128, nullptr);
1737 // Combine sin / cos into one node or libcall if possible.
1738 if (Subtarget->hasSinCos()) {
1739 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1740 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1741 if (Subtarget->isTargetDarwin()) {
1742 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1743 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1744 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1745 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1749 if (Subtarget->isTargetWin64()) {
1750 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1751 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1752 setOperationAction(ISD::SREM, MVT::i128, Custom);
1753 setOperationAction(ISD::UREM, MVT::i128, Custom);
1754 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1755 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1758 // We have target-specific dag combine patterns for the following nodes:
1759 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1760 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1761 setTargetDAGCombine(ISD::BITCAST);
1762 setTargetDAGCombine(ISD::VSELECT);
1763 setTargetDAGCombine(ISD::SELECT);
1764 setTargetDAGCombine(ISD::SHL);
1765 setTargetDAGCombine(ISD::SRA);
1766 setTargetDAGCombine(ISD::SRL);
1767 setTargetDAGCombine(ISD::OR);
1768 setTargetDAGCombine(ISD::AND);
1769 setTargetDAGCombine(ISD::ADD);
1770 setTargetDAGCombine(ISD::FADD);
1771 setTargetDAGCombine(ISD::FSUB);
1772 setTargetDAGCombine(ISD::FMA);
1773 setTargetDAGCombine(ISD::SUB);
1774 setTargetDAGCombine(ISD::LOAD);
1775 setTargetDAGCombine(ISD::MLOAD);
1776 setTargetDAGCombine(ISD::STORE);
1777 setTargetDAGCombine(ISD::MSTORE);
1778 setTargetDAGCombine(ISD::ZERO_EXTEND);
1779 setTargetDAGCombine(ISD::ANY_EXTEND);
1780 setTargetDAGCombine(ISD::SIGN_EXTEND);
1781 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1782 setTargetDAGCombine(ISD::SINT_TO_FP);
1783 setTargetDAGCombine(ISD::UINT_TO_FP);
1784 setTargetDAGCombine(ISD::SETCC);
1785 setTargetDAGCombine(ISD::BUILD_VECTOR);
1786 setTargetDAGCombine(ISD::MUL);
1787 setTargetDAGCombine(ISD::XOR);
1789 computeRegisterProperties(Subtarget->getRegisterInfo());
1791 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1792 MaxStoresPerMemsetOptSize = 8;
1793 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1794 MaxStoresPerMemcpyOptSize = 4;
1795 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1796 MaxStoresPerMemmoveOptSize = 4;
1797 setPrefLoopAlignment(4); // 2^4 bytes.
1799 // A predictable cmov does not hurt on an in-order CPU.
1800 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1801 PredictableSelectIsExpensive = !Subtarget->isAtom();
1802 EnableExtLdPromotion = true;
1803 setPrefFunctionAlignment(4); // 2^4 bytes.
1805 verifyIntrinsicTables();
1808 // This has so far only been implemented for 64-bit MachO.
1809 bool X86TargetLowering::useLoadStackGuardNode() const {
1810 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1813 TargetLoweringBase::LegalizeTypeAction
1814 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1815 if (ExperimentalVectorWideningLegalization &&
1816 VT.getVectorNumElements() != 1 &&
1817 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1818 return TypeWidenVector;
1820 return TargetLoweringBase::getPreferredVectorAction(VT);
1823 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1826 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1828 if (VT.isSimple()) {
1829 MVT VVT = VT.getSimpleVT();
1830 const unsigned NumElts = VVT.getVectorNumElements();
1831 const MVT EltVT = VVT.getVectorElementType();
1832 if (VVT.is512BitVector()) {
1833 if (Subtarget->hasAVX512())
1834 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1835 EltVT == MVT::f32 || EltVT == MVT::f64)
1837 case 8: return MVT::v8i1;
1838 case 16: return MVT::v16i1;
1840 if (Subtarget->hasBWI())
1841 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1843 case 32: return MVT::v32i1;
1844 case 64: return MVT::v64i1;
1848 if (VVT.is256BitVector() || VVT.is128BitVector()) {
1849 if (Subtarget->hasVLX())
1850 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1851 EltVT == MVT::f32 || EltVT == MVT::f64)
1853 case 2: return MVT::v2i1;
1854 case 4: return MVT::v4i1;
1855 case 8: return MVT::v8i1;
1857 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1858 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1860 case 8: return MVT::v8i1;
1861 case 16: return MVT::v16i1;
1862 case 32: return MVT::v32i1;
1867 return VT.changeVectorElementTypeToInteger();
1870 /// Helper for getByValTypeAlignment to determine
1871 /// the desired ByVal argument alignment.
1872 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1875 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1876 if (VTy->getBitWidth() == 128)
1878 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1879 unsigned EltAlign = 0;
1880 getMaxByValAlign(ATy->getElementType(), EltAlign);
1881 if (EltAlign > MaxAlign)
1882 MaxAlign = EltAlign;
1883 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1884 for (auto *EltTy : STy->elements()) {
1885 unsigned EltAlign = 0;
1886 getMaxByValAlign(EltTy, EltAlign);
1887 if (EltAlign > MaxAlign)
1888 MaxAlign = EltAlign;
1895 /// Return the desired alignment for ByVal aggregate
1896 /// function arguments in the caller parameter area. For X86, aggregates
1897 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1898 /// are at 4-byte boundaries.
1899 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1900 const DataLayout &DL) const {
1901 if (Subtarget->is64Bit()) {
1902 // Max of 8 and alignment of type.
1903 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1910 if (Subtarget->hasSSE1())
1911 getMaxByValAlign(Ty, Align);
1915 /// Returns the target specific optimal type for load
1916 /// and store operations as a result of memset, memcpy, and memmove
1917 /// lowering. If DstAlign is zero that means it's safe to destination
1918 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1919 /// means there isn't a need to check it against alignment requirement,
1920 /// probably because the source does not need to be loaded. If 'IsMemset' is
1921 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1922 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1923 /// source is constant so it does not need to be loaded.
1924 /// It returns EVT::Other if the type should be determined using generic
1925 /// target-independent logic.
1927 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1928 unsigned DstAlign, unsigned SrcAlign,
1929 bool IsMemset, bool ZeroMemset,
1931 MachineFunction &MF) const {
1932 const Function *F = MF.getFunction();
1933 if ((!IsMemset || ZeroMemset) &&
1934 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1936 (!Subtarget->isUnalignedMem16Slow() ||
1937 ((DstAlign == 0 || DstAlign >= 16) &&
1938 (SrcAlign == 0 || SrcAlign >= 16)))) {
1940 // FIXME: Check if unaligned 32-byte accesses are slow.
1941 if (Subtarget->hasInt256())
1943 if (Subtarget->hasFp256())
1946 if (Subtarget->hasSSE2())
1948 if (Subtarget->hasSSE1())
1950 } else if (!MemcpyStrSrc && Size >= 8 &&
1951 !Subtarget->is64Bit() &&
1952 Subtarget->hasSSE2()) {
1953 // Do not use f64 to lower memcpy if source is string constant. It's
1954 // better to use i32 to avoid the loads.
1958 // This is a compromise. If we reach here, unaligned accesses may be slow on
1959 // this target. However, creating smaller, aligned accesses could be even
1960 // slower and would certainly be a lot more code.
1961 if (Subtarget->is64Bit() && Size >= 8)
1966 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1968 return X86ScalarSSEf32;
1969 else if (VT == MVT::f64)
1970 return X86ScalarSSEf64;
1975 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1980 switch (VT.getSizeInBits()) {
1982 // 8-byte and under are always assumed to be fast.
1986 *Fast = !Subtarget->isUnalignedMem16Slow();
1989 *Fast = !Subtarget->isUnalignedMem32Slow();
1991 // TODO: What about AVX-512 (512-bit) accesses?
1994 // Misaligned accesses of any size are always allowed.
1998 /// Return the entry encoding for a jump table in the
1999 /// current function. The returned value is a member of the
2000 /// MachineJumpTableInfo::JTEntryKind enum.
2001 unsigned X86TargetLowering::getJumpTableEncoding() const {
2002 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2004 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2005 Subtarget->isPICStyleGOT())
2006 return MachineJumpTableInfo::EK_Custom32;
2008 // Otherwise, use the normal jump table encoding heuristics.
2009 return TargetLowering::getJumpTableEncoding();
2012 bool X86TargetLowering::useSoftFloat() const {
2013 return Subtarget->useSoftFloat();
2017 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2018 const MachineBasicBlock *MBB,
2019 unsigned uid,MCContext &Ctx) const{
2020 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2021 Subtarget->isPICStyleGOT());
2022 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2024 return MCSymbolRefExpr::create(MBB->getSymbol(),
2025 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2028 /// Returns relocation base for the given PIC jumptable.
2029 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2030 SelectionDAG &DAG) const {
2031 if (!Subtarget->is64Bit())
2032 // This doesn't have SDLoc associated with it, but is not really the
2033 // same as a Register.
2034 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2035 getPointerTy(DAG.getDataLayout()));
2039 /// This returns the relocation base for the given PIC jumptable,
2040 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2041 const MCExpr *X86TargetLowering::
2042 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2043 MCContext &Ctx) const {
2044 // X86-64 uses RIP relative addressing based on the jump table label.
2045 if (Subtarget->isPICStyleRIPRel())
2046 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2048 // Otherwise, the reference is relative to the PIC base.
2049 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2052 std::pair<const TargetRegisterClass *, uint8_t>
2053 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2055 const TargetRegisterClass *RRC = nullptr;
2057 switch (VT.SimpleTy) {
2059 return TargetLowering::findRepresentativeClass(TRI, VT);
2060 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2061 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2064 RRC = &X86::VR64RegClass;
2066 case MVT::f32: case MVT::f64:
2067 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2068 case MVT::v4f32: case MVT::v2f64:
2069 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2071 RRC = &X86::VR128RegClass;
2074 return std::make_pair(RRC, Cost);
2077 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2078 unsigned &Offset) const {
2079 if (!Subtarget->isTargetLinux())
2082 if (Subtarget->is64Bit()) {
2083 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2085 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2097 Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2098 if (!Subtarget->isTargetAndroid())
2099 return TargetLowering::getSafeStackPointerLocation(IRB);
2101 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2102 // definition of TLS_SLOT_SAFESTACK in
2103 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2104 unsigned AddressSpace, Offset;
2105 if (Subtarget->is64Bit()) {
2106 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2108 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2118 return ConstantExpr::getIntToPtr(
2119 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2120 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2123 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2124 unsigned DestAS) const {
2125 assert(SrcAS != DestAS && "Expected different address spaces!");
2127 return SrcAS < 256 && DestAS < 256;
2130 //===----------------------------------------------------------------------===//
2131 // Return Value Calling Convention Implementation
2132 //===----------------------------------------------------------------------===//
2134 #include "X86GenCallingConv.inc"
2136 bool X86TargetLowering::CanLowerReturn(
2137 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2138 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2139 SmallVector<CCValAssign, 16> RVLocs;
2140 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2141 return CCInfo.CheckReturn(Outs, RetCC_X86);
2144 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2145 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2150 X86TargetLowering::LowerReturn(SDValue Chain,
2151 CallingConv::ID CallConv, bool isVarArg,
2152 const SmallVectorImpl<ISD::OutputArg> &Outs,
2153 const SmallVectorImpl<SDValue> &OutVals,
2154 SDLoc dl, SelectionDAG &DAG) const {
2155 MachineFunction &MF = DAG.getMachineFunction();
2156 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2160 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2163 SmallVector<SDValue, 6> RetOps;
2164 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2165 // Operand #1 = Bytes To Pop
2166 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2169 // Copy the result values into the output registers.
2170 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2171 CCValAssign &VA = RVLocs[i];
2172 assert(VA.isRegLoc() && "Can only return in registers!");
2173 SDValue ValToCopy = OutVals[i];
2174 EVT ValVT = ValToCopy.getValueType();
2176 // Promote values to the appropriate types.
2177 if (VA.getLocInfo() == CCValAssign::SExt)
2178 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2179 else if (VA.getLocInfo() == CCValAssign::ZExt)
2180 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2181 else if (VA.getLocInfo() == CCValAssign::AExt) {
2182 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2183 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2185 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2187 else if (VA.getLocInfo() == CCValAssign::BCvt)
2188 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2190 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2191 "Unexpected FP-extend for return value.");
2193 // If this is x86-64, and we disabled SSE, we can't return FP values,
2194 // or SSE or MMX vectors.
2195 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2196 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2197 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2198 report_fatal_error("SSE register return with SSE disabled");
2200 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2201 // llvm-gcc has never done it right and no one has noticed, so this
2202 // should be OK for now.
2203 if (ValVT == MVT::f64 &&
2204 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2205 report_fatal_error("SSE2 register return with SSE2 disabled");
2207 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2208 // the RET instruction and handled by the FP Stackifier.
2209 if (VA.getLocReg() == X86::FP0 ||
2210 VA.getLocReg() == X86::FP1) {
2211 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2212 // change the value to the FP stack register class.
2213 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2214 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2215 RetOps.push_back(ValToCopy);
2216 // Don't emit a copytoreg.
2220 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2221 // which is returned in RAX / RDX.
2222 if (Subtarget->is64Bit()) {
2223 if (ValVT == MVT::x86mmx) {
2224 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2225 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2226 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2228 // If we don't have SSE2 available, convert to v4f32 so the generated
2229 // register is legal.
2230 if (!Subtarget->hasSSE2())
2231 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2236 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2237 Flag = Chain.getValue(1);
2238 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2241 // All x86 ABIs require that for returning structs by value we copy
2242 // the sret argument into %rax/%eax (depending on ABI) for the return.
2243 // We saved the argument into a virtual register in the entry block,
2244 // so now we copy the value out and into %rax/%eax.
2246 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2247 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2248 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2249 // either case FuncInfo->setSRetReturnReg() will have been called.
2250 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2251 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2252 getPointerTy(MF.getDataLayout()));
2255 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2256 X86::RAX : X86::EAX;
2257 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2258 Flag = Chain.getValue(1);
2260 // RAX/EAX now acts like a return value.
2262 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2265 RetOps[0] = Chain; // Update chain.
2267 // Add the flag if we have it.
2269 RetOps.push_back(Flag);
2271 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2274 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2275 if (N->getNumValues() != 1)
2277 if (!N->hasNUsesOfValue(1, 0))
2280 SDValue TCChain = Chain;
2281 SDNode *Copy = *N->use_begin();
2282 if (Copy->getOpcode() == ISD::CopyToReg) {
2283 // If the copy has a glue operand, we conservatively assume it isn't safe to
2284 // perform a tail call.
2285 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2287 TCChain = Copy->getOperand(0);
2288 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2291 bool HasRet = false;
2292 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2294 if (UI->getOpcode() != X86ISD::RET_FLAG)
2296 // If we are returning more than one value, we can definitely
2297 // not make a tail call see PR19530
2298 if (UI->getNumOperands() > 4)
2300 if (UI->getNumOperands() == 4 &&
2301 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2314 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2315 ISD::NodeType ExtendKind) const {
2317 // TODO: Is this also valid on 32-bit?
2318 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2319 ReturnMVT = MVT::i8;
2321 ReturnMVT = MVT::i32;
2323 EVT MinVT = getRegisterType(Context, ReturnMVT);
2324 return VT.bitsLT(MinVT) ? MinVT : VT;
2327 /// Lower the result values of a call into the
2328 /// appropriate copies out of appropriate physical registers.
2331 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2332 CallingConv::ID CallConv, bool isVarArg,
2333 const SmallVectorImpl<ISD::InputArg> &Ins,
2334 SDLoc dl, SelectionDAG &DAG,
2335 SmallVectorImpl<SDValue> &InVals) const {
2337 // Assign locations to each value returned by this call.
2338 SmallVector<CCValAssign, 16> RVLocs;
2339 bool Is64Bit = Subtarget->is64Bit();
2340 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2342 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2344 // Copy all of the result registers out of their specified physreg.
2345 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2346 CCValAssign &VA = RVLocs[i];
2347 EVT CopyVT = VA.getLocVT();
2349 // If this is x86-64, and we disabled SSE, we can't return FP values
2350 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2351 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2352 report_fatal_error("SSE register return with SSE disabled");
2355 // If we prefer to use the value in xmm registers, copy it out as f80 and
2356 // use a truncate to move it from fp stack reg to xmm reg.
2357 bool RoundAfterCopy = false;
2358 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2359 isScalarFPTypeInSSEReg(VA.getValVT())) {
2361 RoundAfterCopy = (CopyVT != VA.getLocVT());
2364 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2365 CopyVT, InFlag).getValue(1);
2366 SDValue Val = Chain.getValue(0);
2369 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2370 // This truncation won't change the value.
2371 DAG.getIntPtrConstant(1, dl));
2373 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2374 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2376 InFlag = Chain.getValue(2);
2377 InVals.push_back(Val);
2383 //===----------------------------------------------------------------------===//
2384 // C & StdCall & Fast Calling Convention implementation
2385 //===----------------------------------------------------------------------===//
2386 // StdCall calling convention seems to be standard for many Windows' API
2387 // routines and around. It differs from C calling convention just a little:
2388 // callee should clean up the stack, not caller. Symbols should be also
2389 // decorated in some fancy way :) It doesn't support any vector arguments.
2390 // For info on fast calling convention see Fast Calling Convention (tail call)
2391 // implementation LowerX86_32FastCCCallTo.
2393 /// CallIsStructReturn - Determines whether a call uses struct return
2395 enum StructReturnType {
2400 static StructReturnType
2401 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2403 return NotStructReturn;
2405 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2406 if (!Flags.isSRet())
2407 return NotStructReturn;
2408 if (Flags.isInReg())
2409 return RegStructReturn;
2410 return StackStructReturn;
2413 /// Determines whether a function uses struct return semantics.
2414 static StructReturnType
2415 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2417 return NotStructReturn;
2419 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2420 if (!Flags.isSRet())
2421 return NotStructReturn;
2422 if (Flags.isInReg())
2423 return RegStructReturn;
2424 return StackStructReturn;
2427 /// Make a copy of an aggregate at address specified by "Src" to address
2428 /// "Dst" with size and alignment information specified by the specific
2429 /// parameter attribute. The copy will be passed as a byval function parameter.
2431 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2432 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2434 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2436 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2437 /*isVolatile*/false, /*AlwaysInline=*/true,
2438 /*isTailCall*/false,
2439 MachinePointerInfo(), MachinePointerInfo());
2442 /// Return true if the calling convention is one that we can guarantee TCO for.
2443 static bool canGuaranteeTCO(CallingConv::ID CC) {
2444 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2445 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2448 /// Return true if we might ever do TCO for calls with this calling convention.
2449 static bool mayTailCallThisCC(CallingConv::ID CC) {
2451 // C calling conventions:
2452 case CallingConv::C:
2453 case CallingConv::X86_64_Win64:
2454 case CallingConv::X86_64_SysV:
2455 // Callee pop conventions:
2456 case CallingConv::X86_ThisCall:
2457 case CallingConv::X86_StdCall:
2458 case CallingConv::X86_VectorCall:
2459 case CallingConv::X86_FastCall:
2462 return canGuaranteeTCO(CC);
2466 /// Return true if the function is being made into a tailcall target by
2467 /// changing its ABI.
2468 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2469 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2472 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2474 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2475 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2479 CallingConv::ID CalleeCC = CS.getCallingConv();
2480 if (!mayTailCallThisCC(CalleeCC))
2487 X86TargetLowering::LowerMemArgument(SDValue Chain,
2488 CallingConv::ID CallConv,
2489 const SmallVectorImpl<ISD::InputArg> &Ins,
2490 SDLoc dl, SelectionDAG &DAG,
2491 const CCValAssign &VA,
2492 MachineFrameInfo *MFI,
2494 // Create the nodes corresponding to a load from this parameter slot.
2495 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2496 bool AlwaysUseMutable = shouldGuaranteeTCO(
2497 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2498 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2501 // If value is passed by pointer we have address passed instead of the value
2503 bool ExtendedInMem = VA.isExtInLoc() &&
2504 VA.getValVT().getScalarType() == MVT::i1;
2506 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2507 ValVT = VA.getLocVT();
2509 ValVT = VA.getValVT();
2511 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2512 // changed with more analysis.
2513 // In case of tail call optimization mark all arguments mutable. Since they
2514 // could be overwritten by lowering of arguments in case of a tail call.
2515 if (Flags.isByVal()) {
2516 unsigned Bytes = Flags.getByValSize();
2517 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2518 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2519 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2521 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2522 VA.getLocMemOffset(), isImmutable);
2523 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2524 SDValue Val = DAG.getLoad(
2525 ValVT, dl, Chain, FIN,
2526 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2528 return ExtendedInMem ?
2529 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2533 // FIXME: Get this from tablegen.
2534 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2535 const X86Subtarget *Subtarget) {
2536 assert(Subtarget->is64Bit());
2538 if (Subtarget->isCallingConvWin64(CallConv)) {
2539 static const MCPhysReg GPR64ArgRegsWin64[] = {
2540 X86::RCX, X86::RDX, X86::R8, X86::R9
2542 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2545 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2546 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2548 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2551 // FIXME: Get this from tablegen.
2552 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2553 CallingConv::ID CallConv,
2554 const X86Subtarget *Subtarget) {
2555 assert(Subtarget->is64Bit());
2556 if (Subtarget->isCallingConvWin64(CallConv)) {
2557 // The XMM registers which might contain var arg parameters are shadowed
2558 // in their paired GPR. So we only need to save the GPR to their home
2560 // TODO: __vectorcall will change this.
2564 const Function *Fn = MF.getFunction();
2565 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2566 bool isSoftFloat = Subtarget->useSoftFloat();
2567 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2568 "SSE register cannot be used when SSE is disabled!");
2569 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2570 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2574 static const MCPhysReg XMMArgRegs64Bit[] = {
2575 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2576 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2578 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2581 SDValue X86TargetLowering::LowerFormalArguments(
2582 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2583 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2584 SmallVectorImpl<SDValue> &InVals) const {
2585 MachineFunction &MF = DAG.getMachineFunction();
2586 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2587 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2589 const Function* Fn = MF.getFunction();
2590 if (Fn->hasExternalLinkage() &&
2591 Subtarget->isTargetCygMing() &&
2592 Fn->getName() == "main")
2593 FuncInfo->setForceFramePointer(true);
2595 MachineFrameInfo *MFI = MF.getFrameInfo();
2596 bool Is64Bit = Subtarget->is64Bit();
2597 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2599 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2600 "Var args not supported with calling convention fastcc, ghc or hipe");
2602 // Assign locations to all of the incoming arguments.
2603 SmallVector<CCValAssign, 16> ArgLocs;
2604 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2606 // Allocate shadow area for Win64
2608 CCInfo.AllocateStack(32, 8);
2610 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2612 unsigned LastVal = ~0U;
2614 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2615 CCValAssign &VA = ArgLocs[i];
2616 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2618 assert(VA.getValNo() != LastVal &&
2619 "Don't support value assigned to multiple locs yet");
2621 LastVal = VA.getValNo();
2623 if (VA.isRegLoc()) {
2624 EVT RegVT = VA.getLocVT();
2625 const TargetRegisterClass *RC;
2626 if (RegVT == MVT::i32)
2627 RC = &X86::GR32RegClass;
2628 else if (Is64Bit && RegVT == MVT::i64)
2629 RC = &X86::GR64RegClass;
2630 else if (RegVT == MVT::f32)
2631 RC = &X86::FR32RegClass;
2632 else if (RegVT == MVT::f64)
2633 RC = &X86::FR64RegClass;
2634 else if (RegVT.is512BitVector())
2635 RC = &X86::VR512RegClass;
2636 else if (RegVT.is256BitVector())
2637 RC = &X86::VR256RegClass;
2638 else if (RegVT.is128BitVector())
2639 RC = &X86::VR128RegClass;
2640 else if (RegVT == MVT::x86mmx)
2641 RC = &X86::VR64RegClass;
2642 else if (RegVT == MVT::i1)
2643 RC = &X86::VK1RegClass;
2644 else if (RegVT == MVT::v8i1)
2645 RC = &X86::VK8RegClass;
2646 else if (RegVT == MVT::v16i1)
2647 RC = &X86::VK16RegClass;
2648 else if (RegVT == MVT::v32i1)
2649 RC = &X86::VK32RegClass;
2650 else if (RegVT == MVT::v64i1)
2651 RC = &X86::VK64RegClass;
2653 llvm_unreachable("Unknown argument type!");
2655 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2656 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2658 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2659 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2661 if (VA.getLocInfo() == CCValAssign::SExt)
2662 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2663 DAG.getValueType(VA.getValVT()));
2664 else if (VA.getLocInfo() == CCValAssign::ZExt)
2665 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2666 DAG.getValueType(VA.getValVT()));
2667 else if (VA.getLocInfo() == CCValAssign::BCvt)
2668 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2670 if (VA.isExtInLoc()) {
2671 // Handle MMX values passed in XMM regs.
2672 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2673 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2675 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2678 assert(VA.isMemLoc());
2679 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2682 // If value is passed via pointer - do a load.
2683 if (VA.getLocInfo() == CCValAssign::Indirect)
2684 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2685 MachinePointerInfo(), false, false, false, 0);
2687 InVals.push_back(ArgValue);
2690 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2691 // All x86 ABIs require that for returning structs by value we copy the
2692 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2693 // the argument into a virtual register so that we can access it from the
2695 if (Ins[i].Flags.isSRet()) {
2696 unsigned Reg = FuncInfo->getSRetReturnReg();
2698 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2699 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2700 FuncInfo->setSRetReturnReg(Reg);
2702 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2703 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2708 unsigned StackSize = CCInfo.getNextStackOffset();
2709 // Align stack specially for tail calls.
2710 if (shouldGuaranteeTCO(CallConv,
2711 MF.getTarget().Options.GuaranteedTailCallOpt))
2712 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2714 // If the function takes variable number of arguments, make a frame index for
2715 // the start of the first vararg value... for expansion of llvm.va_start. We
2716 // can skip this if there are no va_start calls.
2717 if (MFI->hasVAStart() &&
2718 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2719 CallConv != CallingConv::X86_ThisCall))) {
2720 FuncInfo->setVarArgsFrameIndex(
2721 MFI->CreateFixedObject(1, StackSize, true));
2724 MachineModuleInfo &MMI = MF.getMMI();
2726 // Figure out if XMM registers are in use.
2727 assert(!(Subtarget->useSoftFloat() &&
2728 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2729 "SSE register cannot be used when SSE is disabled!");
2731 // 64-bit calling conventions support varargs and register parameters, so we
2732 // have to do extra work to spill them in the prologue.
2733 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2734 // Find the first unallocated argument registers.
2735 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2736 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2737 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2738 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2739 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2740 "SSE register cannot be used when SSE is disabled!");
2742 // Gather all the live in physical registers.
2743 SmallVector<SDValue, 6> LiveGPRs;
2744 SmallVector<SDValue, 8> LiveXMMRegs;
2746 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2747 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2749 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2751 if (!ArgXMMs.empty()) {
2752 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2753 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2754 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2755 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2756 LiveXMMRegs.push_back(
2757 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2762 // Get to the caller-allocated home save location. Add 8 to account
2763 // for the return address.
2764 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2765 FuncInfo->setRegSaveFrameIndex(
2766 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2767 // Fixup to set vararg frame on shadow area (4 x i64).
2769 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2771 // For X86-64, if there are vararg parameters that are passed via
2772 // registers, then we must store them to their spots on the stack so
2773 // they may be loaded by deferencing the result of va_next.
2774 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2775 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2776 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2777 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2780 // Store the integer parameter registers.
2781 SmallVector<SDValue, 8> MemOps;
2782 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2783 getPointerTy(DAG.getDataLayout()));
2784 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2785 for (SDValue Val : LiveGPRs) {
2786 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2787 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2789 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2790 MachinePointerInfo::getFixedStack(
2791 DAG.getMachineFunction(),
2792 FuncInfo->getRegSaveFrameIndex(), Offset),
2794 MemOps.push_back(Store);
2798 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2799 // Now store the XMM (fp + vector) parameter registers.
2800 SmallVector<SDValue, 12> SaveXMMOps;
2801 SaveXMMOps.push_back(Chain);
2802 SaveXMMOps.push_back(ALVal);
2803 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2804 FuncInfo->getRegSaveFrameIndex(), dl));
2805 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2806 FuncInfo->getVarArgsFPOffset(), dl));
2807 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2809 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2810 MVT::Other, SaveXMMOps));
2813 if (!MemOps.empty())
2814 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2817 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2818 // Find the largest legal vector type.
2819 MVT VecVT = MVT::Other;
2820 // FIXME: Only some x86_32 calling conventions support AVX512.
2821 if (Subtarget->hasAVX512() &&
2822 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2823 CallConv == CallingConv::Intel_OCL_BI)))
2824 VecVT = MVT::v16f32;
2825 else if (Subtarget->hasAVX())
2827 else if (Subtarget->hasSSE2())
2830 // We forward some GPRs and some vector types.
2831 SmallVector<MVT, 2> RegParmTypes;
2832 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2833 RegParmTypes.push_back(IntVT);
2834 if (VecVT != MVT::Other)
2835 RegParmTypes.push_back(VecVT);
2837 // Compute the set of forwarded registers. The rest are scratch.
2838 SmallVectorImpl<ForwardedRegister> &Forwards =
2839 FuncInfo->getForwardedMustTailRegParms();
2840 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2842 // Conservatively forward AL on x86_64, since it might be used for varargs.
2843 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2844 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2845 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2848 // Copy all forwards from physical to virtual registers.
2849 for (ForwardedRegister &F : Forwards) {
2850 // FIXME: Can we use a less constrained schedule?
2851 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2852 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2853 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2857 // Some CCs need callee pop.
2858 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2859 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2860 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2862 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2863 // If this is an sret function, the return should pop the hidden pointer.
2864 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
2865 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2866 argsAreStructReturn(Ins) == StackStructReturn)
2867 FuncInfo->setBytesToPopOnReturn(4);
2871 // RegSaveFrameIndex is X86-64 only.
2872 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2873 if (CallConv == CallingConv::X86_FastCall ||
2874 CallConv == CallingConv::X86_ThisCall)
2875 // fastcc functions can't have varargs.
2876 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2879 FuncInfo->setArgumentStackSize(StackSize);
2881 if (MMI.hasWinEHFuncInfo(Fn)) {
2883 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2884 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2885 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2886 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2887 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2888 MachinePointerInfo::getFixedStack(
2889 DAG.getMachineFunction(), UnwindHelpFI),
2890 /*isVolatile=*/true,
2891 /*isNonTemporal=*/false, /*Alignment=*/0);
2893 // Functions using Win32 EH are considered to have opaque SP adjustments
2894 // to force local variables to be addressed from the frame or base
2896 MFI->setHasOpaqueSPAdjustment(true);
2904 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2905 SDValue StackPtr, SDValue Arg,
2906 SDLoc dl, SelectionDAG &DAG,
2907 const CCValAssign &VA,
2908 ISD::ArgFlagsTy Flags) const {
2909 unsigned LocMemOffset = VA.getLocMemOffset();
2910 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2911 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2913 if (Flags.isByVal())
2914 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2916 return DAG.getStore(
2917 Chain, dl, Arg, PtrOff,
2918 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2922 /// Emit a load of return address if tail call
2923 /// optimization is performed and it is required.
2925 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2926 SDValue &OutRetAddr, SDValue Chain,
2927 bool IsTailCall, bool Is64Bit,
2928 int FPDiff, SDLoc dl) const {
2929 // Adjust the Return address stack slot.
2930 EVT VT = getPointerTy(DAG.getDataLayout());
2931 OutRetAddr = getReturnAddressFrameIndex(DAG);
2933 // Load the "old" Return address.
2934 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2935 false, false, false, 0);
2936 return SDValue(OutRetAddr.getNode(), 1);
2939 /// Emit a store of the return address if tail call
2940 /// optimization is performed and it is required (FPDiff!=0).
2941 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2942 SDValue Chain, SDValue RetAddrFrIdx,
2943 EVT PtrVT, unsigned SlotSize,
2944 int FPDiff, SDLoc dl) {
2945 // Store the return address to the appropriate stack slot.
2946 if (!FPDiff) return Chain;
2947 // Calculate the new stack slot for the return address.
2948 int NewReturnAddrFI =
2949 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2951 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2952 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2953 MachinePointerInfo::getFixedStack(
2954 DAG.getMachineFunction(), NewReturnAddrFI),
2959 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2960 /// operation of specified width.
2961 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
2963 unsigned NumElems = VT.getVectorNumElements();
2964 SmallVector<int, 8> Mask;
2965 Mask.push_back(NumElems);
2966 for (unsigned i = 1; i != NumElems; ++i)
2968 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2972 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2973 SmallVectorImpl<SDValue> &InVals) const {
2974 SelectionDAG &DAG = CLI.DAG;
2976 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2977 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2978 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2979 SDValue Chain = CLI.Chain;
2980 SDValue Callee = CLI.Callee;
2981 CallingConv::ID CallConv = CLI.CallConv;
2982 bool &isTailCall = CLI.IsTailCall;
2983 bool isVarArg = CLI.IsVarArg;
2985 MachineFunction &MF = DAG.getMachineFunction();
2986 bool Is64Bit = Subtarget->is64Bit();
2987 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2988 StructReturnType SR = callIsStructReturn(Outs);
2989 bool IsSibcall = false;
2990 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2991 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2993 if (Attr.getValueAsString() == "true")
2996 if (Subtarget->isPICStyleGOT() &&
2997 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2998 // If we are using a GOT, disable tail calls to external symbols with
2999 // default visibility. Tail calling such a symbol requires using a GOT
3000 // relocation, which forces early binding of the symbol. This breaks code
3001 // that require lazy function symbol resolution. Using musttail or
3002 // GuaranteedTailCallOpt will override this.
3003 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3004 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3005 G->getGlobal()->hasDefaultVisibility()))
3009 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3011 // Force this to be a tail call. The verifier rules are enough to ensure
3012 // that we can lower this successfully without moving the return address
3015 } else if (isTailCall) {
3016 // Check if it's really possible to do a tail call.
3017 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3018 isVarArg, SR != NotStructReturn,
3019 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3020 Outs, OutVals, Ins, DAG);
3022 // Sibcalls are automatically detected tailcalls which do not require
3024 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3031 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
3032 "Var args not supported with calling convention fastcc, ghc or hipe");
3034 // Analyze operands of the call, assigning locations to each operand.
3035 SmallVector<CCValAssign, 16> ArgLocs;
3036 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3038 // Allocate shadow area for Win64
3040 CCInfo.AllocateStack(32, 8);
3042 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3044 // Get a count of how many bytes are to be pushed on the stack.
3045 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3047 // This is a sibcall. The memory operands are available in caller's
3048 // own caller's stack.
3050 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3051 canGuaranteeTCO(CallConv))
3052 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3055 if (isTailCall && !IsSibcall && !IsMustTail) {
3056 // Lower arguments at fp - stackoffset + fpdiff.
3057 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3059 FPDiff = NumBytesCallerPushed - NumBytes;
3061 // Set the delta of movement of the returnaddr stackslot.
3062 // But only set if delta is greater than previous delta.
3063 if (FPDiff < X86Info->getTCReturnAddrDelta())
3064 X86Info->setTCReturnAddrDelta(FPDiff);
3067 unsigned NumBytesToPush = NumBytes;
3068 unsigned NumBytesToPop = NumBytes;
3070 // If we have an inalloca argument, all stack space has already been allocated
3071 // for us and be right at the top of the stack. We don't support multiple
3072 // arguments passed in memory when using inalloca.
3073 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3075 if (!ArgLocs.back().isMemLoc())
3076 report_fatal_error("cannot use inalloca attribute on a register "
3078 if (ArgLocs.back().getLocMemOffset() != 0)
3079 report_fatal_error("any parameter with the inalloca attribute must be "
3080 "the only memory argument");
3084 Chain = DAG.getCALLSEQ_START(
3085 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3087 SDValue RetAddrFrIdx;
3088 // Load return address for tail calls.
3089 if (isTailCall && FPDiff)
3090 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3091 Is64Bit, FPDiff, dl);
3093 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3094 SmallVector<SDValue, 8> MemOpChains;
3097 // Walk the register/memloc assignments, inserting copies/loads. In the case
3098 // of tail call optimization arguments are handle later.
3099 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3100 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3101 // Skip inalloca arguments, they have already been written.
3102 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3103 if (Flags.isInAlloca())
3106 CCValAssign &VA = ArgLocs[i];
3107 EVT RegVT = VA.getLocVT();
3108 SDValue Arg = OutVals[i];
3109 bool isByVal = Flags.isByVal();
3111 // Promote the value if needed.
3112 switch (VA.getLocInfo()) {
3113 default: llvm_unreachable("Unknown loc info!");
3114 case CCValAssign::Full: break;
3115 case CCValAssign::SExt:
3116 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3118 case CCValAssign::ZExt:
3119 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3121 case CCValAssign::AExt:
3122 if (Arg.getValueType().isVector() &&
3123 Arg.getValueType().getVectorElementType() == MVT::i1)
3124 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3125 else if (RegVT.is128BitVector()) {
3126 // Special case: passing MMX values in XMM registers.
3127 Arg = DAG.getBitcast(MVT::i64, Arg);
3128 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3129 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3131 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3133 case CCValAssign::BCvt:
3134 Arg = DAG.getBitcast(RegVT, Arg);
3136 case CCValAssign::Indirect: {
3137 // Store the argument.
3138 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3139 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3140 Chain = DAG.getStore(
3141 Chain, dl, Arg, SpillSlot,
3142 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3149 if (VA.isRegLoc()) {
3150 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3151 if (isVarArg && IsWin64) {
3152 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3153 // shadow reg if callee is a varargs function.
3154 unsigned ShadowReg = 0;
3155 switch (VA.getLocReg()) {
3156 case X86::XMM0: ShadowReg = X86::RCX; break;
3157 case X86::XMM1: ShadowReg = X86::RDX; break;
3158 case X86::XMM2: ShadowReg = X86::R8; break;
3159 case X86::XMM3: ShadowReg = X86::R9; break;
3162 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3164 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3165 assert(VA.isMemLoc());
3166 if (!StackPtr.getNode())
3167 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3168 getPointerTy(DAG.getDataLayout()));
3169 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3170 dl, DAG, VA, Flags));
3174 if (!MemOpChains.empty())
3175 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3177 if (Subtarget->isPICStyleGOT()) {
3178 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3181 RegsToPass.push_back(std::make_pair(
3182 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3183 getPointerTy(DAG.getDataLayout()))));
3185 // If we are tail calling and generating PIC/GOT style code load the
3186 // address of the callee into ECX. The value in ecx is used as target of
3187 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3188 // for tail calls on PIC/GOT architectures. Normally we would just put the
3189 // address of GOT into ebx and then call target@PLT. But for tail calls
3190 // ebx would be restored (since ebx is callee saved) before jumping to the
3193 // Note: The actual moving to ECX is done further down.
3194 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3195 if (G && !G->getGlobal()->hasLocalLinkage() &&
3196 G->getGlobal()->hasDefaultVisibility())
3197 Callee = LowerGlobalAddress(Callee, DAG);
3198 else if (isa<ExternalSymbolSDNode>(Callee))
3199 Callee = LowerExternalSymbol(Callee, DAG);
3203 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3204 // From AMD64 ABI document:
3205 // For calls that may call functions that use varargs or stdargs
3206 // (prototype-less calls or calls to functions containing ellipsis (...) in
3207 // the declaration) %al is used as hidden argument to specify the number
3208 // of SSE registers used. The contents of %al do not need to match exactly
3209 // the number of registers, but must be an ubound on the number of SSE
3210 // registers used and is in the range 0 - 8 inclusive.
3212 // Count the number of XMM registers allocated.
3213 static const MCPhysReg XMMArgRegs[] = {
3214 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3215 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3217 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3218 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3219 && "SSE registers cannot be used when SSE is disabled");
3221 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3222 DAG.getConstant(NumXMMRegs, dl,
3226 if (isVarArg && IsMustTail) {
3227 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3228 for (const auto &F : Forwards) {
3229 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3230 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3234 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3235 // don't need this because the eligibility check rejects calls that require
3236 // shuffling arguments passed in memory.
3237 if (!IsSibcall && isTailCall) {
3238 // Force all the incoming stack arguments to be loaded from the stack
3239 // before any new outgoing arguments are stored to the stack, because the
3240 // outgoing stack slots may alias the incoming argument stack slots, and
3241 // the alias isn't otherwise explicit. This is slightly more conservative
3242 // than necessary, because it means that each store effectively depends
3243 // on every argument instead of just those arguments it would clobber.
3244 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3246 SmallVector<SDValue, 8> MemOpChains2;
3249 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3250 CCValAssign &VA = ArgLocs[i];
3253 assert(VA.isMemLoc());
3254 SDValue Arg = OutVals[i];
3255 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3256 // Skip inalloca arguments. They don't require any work.
3257 if (Flags.isInAlloca())
3259 // Create frame index.
3260 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3261 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3262 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3263 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3265 if (Flags.isByVal()) {
3266 // Copy relative to framepointer.
3267 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3268 if (!StackPtr.getNode())
3269 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3270 getPointerTy(DAG.getDataLayout()));
3271 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3274 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3278 // Store relative to framepointer.
3279 MemOpChains2.push_back(DAG.getStore(
3280 ArgChain, dl, Arg, FIN,
3281 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3286 if (!MemOpChains2.empty())
3287 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3289 // Store the return address to the appropriate stack slot.
3290 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3291 getPointerTy(DAG.getDataLayout()),
3292 RegInfo->getSlotSize(), FPDiff, dl);
3295 // Build a sequence of copy-to-reg nodes chained together with token chain
3296 // and flag operands which copy the outgoing args into registers.
3298 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3299 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3300 RegsToPass[i].second, InFlag);
3301 InFlag = Chain.getValue(1);
3304 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3305 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3306 // In the 64-bit large code model, we have to make all calls
3307 // through a register, since the call instruction's 32-bit
3308 // pc-relative offset may not be large enough to hold the whole
3310 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3311 // If the callee is a GlobalAddress node (quite common, every direct call
3312 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3314 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3316 // We should use extra load for direct calls to dllimported functions in
3318 const GlobalValue *GV = G->getGlobal();
3319 if (!GV->hasDLLImportStorageClass()) {
3320 unsigned char OpFlags = 0;
3321 bool ExtraLoad = false;
3322 unsigned WrapperKind = ISD::DELETED_NODE;
3324 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3325 // external symbols most go through the PLT in PIC mode. If the symbol
3326 // has hidden or protected visibility, or if it is static or local, then
3327 // we don't need to use the PLT - we can directly call it.
3328 if (Subtarget->isTargetELF() &&
3329 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3330 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3331 OpFlags = X86II::MO_PLT;
3332 } else if (Subtarget->isPICStyleStubAny() &&
3333 !GV->isStrongDefinitionForLinker() &&
3334 (!Subtarget->getTargetTriple().isMacOSX() ||
3335 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3336 // PC-relative references to external symbols should go through $stub,
3337 // unless we're building with the leopard linker or later, which
3338 // automatically synthesizes these stubs.
3339 OpFlags = X86II::MO_DARWIN_STUB;
3340 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3341 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3342 // If the function is marked as non-lazy, generate an indirect call
3343 // which loads from the GOT directly. This avoids runtime overhead
3344 // at the cost of eager binding (and one extra byte of encoding).
3345 OpFlags = X86II::MO_GOTPCREL;
3346 WrapperKind = X86ISD::WrapperRIP;
3350 Callee = DAG.getTargetGlobalAddress(
3351 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3353 // Add a wrapper if needed.
3354 if (WrapperKind != ISD::DELETED_NODE)
3355 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3356 getPointerTy(DAG.getDataLayout()), Callee);
3357 // Add extra indirection if needed.
3359 Callee = DAG.getLoad(
3360 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3361 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3364 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3365 unsigned char OpFlags = 0;
3367 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3368 // external symbols should go through the PLT.
3369 if (Subtarget->isTargetELF() &&
3370 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3371 OpFlags = X86II::MO_PLT;
3372 } else if (Subtarget->isPICStyleStubAny() &&
3373 (!Subtarget->getTargetTriple().isMacOSX() ||
3374 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3375 // PC-relative references to external symbols should go through $stub,
3376 // unless we're building with the leopard linker or later, which
3377 // automatically synthesizes these stubs.
3378 OpFlags = X86II::MO_DARWIN_STUB;
3381 Callee = DAG.getTargetExternalSymbol(
3382 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3383 } else if (Subtarget->isTarget64BitILP32() &&
3384 Callee->getValueType(0) == MVT::i32) {
3385 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3386 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3389 // Returns a chain & a flag for retval copy to use.
3390 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3391 SmallVector<SDValue, 8> Ops;
3393 if (!IsSibcall && isTailCall) {
3394 Chain = DAG.getCALLSEQ_END(Chain,
3395 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3396 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3397 InFlag = Chain.getValue(1);
3400 Ops.push_back(Chain);
3401 Ops.push_back(Callee);
3404 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3406 // Add argument registers to the end of the list so that they are known live
3408 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3409 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3410 RegsToPass[i].second.getValueType()));
3412 // Add a register mask operand representing the call-preserved registers.
3413 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3414 assert(Mask && "Missing call preserved mask for calling convention");
3416 // If this is an invoke in a 32-bit function using a funclet-based
3417 // personality, assume the function clobbers all registers. If an exception
3418 // is thrown, the runtime will not restore CSRs.
3419 // FIXME: Model this more precisely so that we can register allocate across
3420 // the normal edge and spill and fill across the exceptional edge.
3421 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3422 const Function *CallerFn = MF.getFunction();
3423 EHPersonality Pers =
3424 CallerFn->hasPersonalityFn()
3425 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3426 : EHPersonality::Unknown;
3427 if (isFuncletEHPersonality(Pers))
3428 Mask = RegInfo->getNoPreservedMask();
3431 Ops.push_back(DAG.getRegisterMask(Mask));
3433 if (InFlag.getNode())
3434 Ops.push_back(InFlag);
3438 //// If this is the first return lowered for this function, add the regs
3439 //// to the liveout set for the function.
3440 // This isn't right, although it's probably harmless on x86; liveouts
3441 // should be computed from returns not tail calls. Consider a void
3442 // function making a tail call to a function returning int.
3443 MF.getFrameInfo()->setHasTailCall();
3444 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3447 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3448 InFlag = Chain.getValue(1);
3450 // Create the CALLSEQ_END node.
3451 unsigned NumBytesForCalleeToPop;
3452 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3453 DAG.getTarget().Options.GuaranteedTailCallOpt))
3454 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3455 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3456 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3457 SR == StackStructReturn)
3458 // If this is a call to a struct-return function, the callee
3459 // pops the hidden struct pointer, so we have to push it back.
3460 // This is common for Darwin/X86, Linux & Mingw32 targets.
3461 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3462 NumBytesForCalleeToPop = 4;
3464 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3466 // Returns a flag for retval copy to use.
3468 Chain = DAG.getCALLSEQ_END(Chain,
3469 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3470 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3473 InFlag = Chain.getValue(1);
3476 // Handle result values, copying them out of physregs into vregs that we
3478 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3479 Ins, dl, DAG, InVals);
3482 //===----------------------------------------------------------------------===//
3483 // Fast Calling Convention (tail call) implementation
3484 //===----------------------------------------------------------------------===//
3486 // Like std call, callee cleans arguments, convention except that ECX is
3487 // reserved for storing the tail called function address. Only 2 registers are
3488 // free for argument passing (inreg). Tail call optimization is performed
3490 // * tailcallopt is enabled
3491 // * caller/callee are fastcc
3492 // On X86_64 architecture with GOT-style position independent code only local
3493 // (within module) calls are supported at the moment.
3494 // To keep the stack aligned according to platform abi the function
3495 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3496 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3497 // If a tail called function callee has more arguments than the caller the
3498 // caller needs to make sure that there is room to move the RETADDR to. This is
3499 // achieved by reserving an area the size of the argument delta right after the
3500 // original RETADDR, but before the saved framepointer or the spilled registers
3501 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3513 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3516 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3517 SelectionDAG& DAG) const {
3518 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3519 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3520 unsigned StackAlignment = TFI.getStackAlignment();
3521 uint64_t AlignMask = StackAlignment - 1;
3522 int64_t Offset = StackSize;
3523 unsigned SlotSize = RegInfo->getSlotSize();
3524 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3525 // Number smaller than 12 so just add the difference.
3526 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3528 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3529 Offset = ((~AlignMask) & Offset) + StackAlignment +
3530 (StackAlignment-SlotSize);
3535 /// Return true if the given stack call argument is already available in the
3536 /// same position (relatively) of the caller's incoming argument stack.
3538 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3539 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3540 const X86InstrInfo *TII) {
3541 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3543 if (Arg.getOpcode() == ISD::CopyFromReg) {
3544 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3545 if (!TargetRegisterInfo::isVirtualRegister(VR))
3547 MachineInstr *Def = MRI->getVRegDef(VR);
3550 if (!Flags.isByVal()) {
3551 if (!TII->isLoadFromStackSlot(Def, FI))
3554 unsigned Opcode = Def->getOpcode();
3555 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3556 Opcode == X86::LEA64_32r) &&
3557 Def->getOperand(1).isFI()) {
3558 FI = Def->getOperand(1).getIndex();
3559 Bytes = Flags.getByValSize();
3563 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3564 if (Flags.isByVal())
3565 // ByVal argument is passed in as a pointer but it's now being
3566 // dereferenced. e.g.
3567 // define @foo(%struct.X* %A) {
3568 // tail call @bar(%struct.X* byval %A)
3571 SDValue Ptr = Ld->getBasePtr();
3572 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3575 FI = FINode->getIndex();
3576 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3577 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3578 FI = FINode->getIndex();
3579 Bytes = Flags.getByValSize();
3583 assert(FI != INT_MAX);
3584 if (!MFI->isFixedObjectIndex(FI))
3586 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3589 /// Check whether the call is eligible for tail call optimization. Targets
3590 /// that want to do tail call optimization should implement this function.
3591 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3592 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3593 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3594 const SmallVectorImpl<ISD::OutputArg> &Outs,
3595 const SmallVectorImpl<SDValue> &OutVals,
3596 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3597 if (!mayTailCallThisCC(CalleeCC))
3600 // If -tailcallopt is specified, make fastcc functions tail-callable.
3601 MachineFunction &MF = DAG.getMachineFunction();
3602 const Function *CallerF = MF.getFunction();
3604 // If the function return type is x86_fp80 and the callee return type is not,
3605 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3606 // perform a tailcall optimization here.
3607 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3610 CallingConv::ID CallerCC = CallerF->getCallingConv();
3611 bool CCMatch = CallerCC == CalleeCC;
3612 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3613 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3615 // Win64 functions have extra shadow space for argument homing. Don't do the
3616 // sibcall if the caller and callee have mismatched expectations for this
3618 if (IsCalleeWin64 != IsCallerWin64)
3621 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3622 if (canGuaranteeTCO(CalleeCC) && CCMatch)
3627 // Look for obvious safe cases to perform tail call optimization that do not
3628 // require ABI changes. This is what gcc calls sibcall.
3630 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3631 // emit a special epilogue.
3632 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3633 if (RegInfo->needsStackRealignment(MF))
3636 // Also avoid sibcall optimization if either caller or callee uses struct
3637 // return semantics.
3638 if (isCalleeStructRet || isCallerStructRet)
3641 // Do not sibcall optimize vararg calls unless all arguments are passed via
3643 if (isVarArg && !Outs.empty()) {
3644 // Optimizing for varargs on Win64 is unlikely to be safe without
3645 // additional testing.
3646 if (IsCalleeWin64 || IsCallerWin64)
3649 SmallVector<CCValAssign, 16> ArgLocs;
3650 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3653 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3654 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3655 if (!ArgLocs[i].isRegLoc())
3659 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3660 // stack. Therefore, if it's not used by the call it is not safe to optimize
3661 // this into a sibcall.
3662 bool Unused = false;
3663 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3670 SmallVector<CCValAssign, 16> RVLocs;
3671 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3673 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3674 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3675 CCValAssign &VA = RVLocs[i];
3676 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3681 // If the calling conventions do not match, then we'd better make sure the
3682 // results are returned in the same way as what the caller expects.
3684 SmallVector<CCValAssign, 16> RVLocs1;
3685 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3687 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3689 SmallVector<CCValAssign, 16> RVLocs2;
3690 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3692 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3694 if (RVLocs1.size() != RVLocs2.size())
3696 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3697 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3699 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3701 if (RVLocs1[i].isRegLoc()) {
3702 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3705 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3711 unsigned StackArgsSize = 0;
3713 // If the callee takes no arguments then go on to check the results of the
3715 if (!Outs.empty()) {
3716 // Check if stack adjustment is needed. For now, do not do this if any
3717 // argument is passed on the stack.
3718 SmallVector<CCValAssign, 16> ArgLocs;
3719 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3722 // Allocate shadow area for Win64
3724 CCInfo.AllocateStack(32, 8);
3726 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3727 StackArgsSize = CCInfo.getNextStackOffset();
3729 if (CCInfo.getNextStackOffset()) {
3730 // Check if the arguments are already laid out in the right way as
3731 // the caller's fixed stack objects.
3732 MachineFrameInfo *MFI = MF.getFrameInfo();
3733 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3734 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3735 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3736 CCValAssign &VA = ArgLocs[i];
3737 SDValue Arg = OutVals[i];
3738 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3739 if (VA.getLocInfo() == CCValAssign::Indirect)
3741 if (!VA.isRegLoc()) {
3742 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3749 // If the tailcall address may be in a register, then make sure it's
3750 // possible to register allocate for it. In 32-bit, the call address can
3751 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3752 // callee-saved registers are restored. These happen to be the same
3753 // registers used to pass 'inreg' arguments so watch out for those.
3754 if (!Subtarget->is64Bit() &&
3755 ((!isa<GlobalAddressSDNode>(Callee) &&
3756 !isa<ExternalSymbolSDNode>(Callee)) ||
3757 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3758 unsigned NumInRegs = 0;
3759 // In PIC we need an extra register to formulate the address computation
3761 unsigned MaxInRegs =
3762 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3764 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3765 CCValAssign &VA = ArgLocs[i];
3768 unsigned Reg = VA.getLocReg();
3771 case X86::EAX: case X86::EDX: case X86::ECX:
3772 if (++NumInRegs == MaxInRegs)
3780 bool CalleeWillPop =
3781 X86::isCalleePop(CalleeCC, Subtarget->is64Bit(), isVarArg,
3782 MF.getTarget().Options.GuaranteedTailCallOpt);
3784 if (unsigned BytesToPop =
3785 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
3786 // If we have bytes to pop, the callee must pop them.
3787 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3788 if (!CalleePopMatches)
3790 } else if (CalleeWillPop && StackArgsSize > 0) {
3791 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3799 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3800 const TargetLibraryInfo *libInfo) const {
3801 return X86::createFastISel(funcInfo, libInfo);
3804 //===----------------------------------------------------------------------===//
3805 // Other Lowering Hooks
3806 //===----------------------------------------------------------------------===//
3808 static bool MayFoldLoad(SDValue Op) {
3809 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3812 static bool MayFoldIntoStore(SDValue Op) {
3813 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3816 static bool isTargetShuffle(unsigned Opcode) {
3818 default: return false;
3819 case X86ISD::BLENDI:
3820 case X86ISD::PSHUFB:
3821 case X86ISD::PSHUFD:
3822 case X86ISD::PSHUFHW:
3823 case X86ISD::PSHUFLW:
3825 case X86ISD::PALIGNR:
3826 case X86ISD::MOVLHPS:
3827 case X86ISD::MOVLHPD:
3828 case X86ISD::MOVHLPS:
3829 case X86ISD::MOVLPS:
3830 case X86ISD::MOVLPD:
3831 case X86ISD::MOVSHDUP:
3832 case X86ISD::MOVSLDUP:
3833 case X86ISD::MOVDDUP:
3836 case X86ISD::UNPCKL:
3837 case X86ISD::UNPCKH:
3838 case X86ISD::VPERMILPI:
3839 case X86ISD::VPERM2X128:
3840 case X86ISD::VPERMI:
3841 case X86ISD::VPERMV:
3842 case X86ISD::VPERMV3:
3847 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3848 SDValue V1, unsigned TargetMask,
3849 SelectionDAG &DAG) {
3851 default: llvm_unreachable("Unknown x86 shuffle node");
3852 case X86ISD::PSHUFD:
3853 case X86ISD::PSHUFHW:
3854 case X86ISD::PSHUFLW:
3855 case X86ISD::VPERMILPI:
3856 case X86ISD::VPERMI:
3857 return DAG.getNode(Opc, dl, VT, V1,
3858 DAG.getConstant(TargetMask, dl, MVT::i8));
3862 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3863 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3865 default: llvm_unreachable("Unknown x86 shuffle node");
3866 case X86ISD::MOVLHPS:
3867 case X86ISD::MOVLHPD:
3868 case X86ISD::MOVHLPS:
3869 case X86ISD::MOVLPS:
3870 case X86ISD::MOVLPD:
3873 case X86ISD::UNPCKL:
3874 case X86ISD::UNPCKH:
3875 return DAG.getNode(Opc, dl, VT, V1, V2);
3879 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3880 MachineFunction &MF = DAG.getMachineFunction();
3881 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3882 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3883 int ReturnAddrIndex = FuncInfo->getRAIndex();
3885 if (ReturnAddrIndex == 0) {
3886 // Set up a frame object for the return address.
3887 unsigned SlotSize = RegInfo->getSlotSize();
3888 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3891 FuncInfo->setRAIndex(ReturnAddrIndex);
3894 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3897 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3898 bool hasSymbolicDisplacement) {
3899 // Offset should fit into 32 bit immediate field.
3900 if (!isInt<32>(Offset))
3903 // If we don't have a symbolic displacement - we don't have any extra
3905 if (!hasSymbolicDisplacement)
3908 // FIXME: Some tweaks might be needed for medium code model.
3909 if (M != CodeModel::Small && M != CodeModel::Kernel)
3912 // For small code model we assume that latest object is 16MB before end of 31
3913 // bits boundary. We may also accept pretty large negative constants knowing
3914 // that all objects are in the positive half of address space.
3915 if (M == CodeModel::Small && Offset < 16*1024*1024)
3918 // For kernel code model we know that all object resist in the negative half
3919 // of 32bits address space. We may not accept negative offsets, since they may
3920 // be just off and we may accept pretty large positive ones.
3921 if (M == CodeModel::Kernel && Offset >= 0)
3927 /// Determines whether the callee is required to pop its own arguments.
3928 /// Callee pop is necessary to support tail calls.
3929 bool X86::isCalleePop(CallingConv::ID CallingConv,
3930 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
3931 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
3932 // can guarantee TCO.
3933 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
3936 switch (CallingConv) {
3939 case CallingConv::X86_StdCall:
3940 case CallingConv::X86_FastCall:
3941 case CallingConv::X86_ThisCall:
3942 case CallingConv::X86_VectorCall:
3947 /// \brief Return true if the condition is an unsigned comparison operation.
3948 static bool isX86CCUnsigned(unsigned X86CC) {
3950 default: llvm_unreachable("Invalid integer condition!");
3951 case X86::COND_E: return true;
3952 case X86::COND_G: return false;
3953 case X86::COND_GE: return false;
3954 case X86::COND_L: return false;
3955 case X86::COND_LE: return false;
3956 case X86::COND_NE: return true;
3957 case X86::COND_B: return true;
3958 case X86::COND_A: return true;
3959 case X86::COND_BE: return true;
3960 case X86::COND_AE: return true;
3964 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3965 /// condition code, returning the condition code and the LHS/RHS of the
3966 /// comparison to make.
3967 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3968 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3970 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3971 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3972 // X > -1 -> X == 0, jump !sign.
3973 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3974 return X86::COND_NS;
3976 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3977 // X < 0 -> X == 0, jump on sign.
3980 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3982 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3983 return X86::COND_LE;
3987 switch (SetCCOpcode) {
3988 default: llvm_unreachable("Invalid integer condition!");
3989 case ISD::SETEQ: return X86::COND_E;
3990 case ISD::SETGT: return X86::COND_G;
3991 case ISD::SETGE: return X86::COND_GE;
3992 case ISD::SETLT: return X86::COND_L;
3993 case ISD::SETLE: return X86::COND_LE;
3994 case ISD::SETNE: return X86::COND_NE;
3995 case ISD::SETULT: return X86::COND_B;
3996 case ISD::SETUGT: return X86::COND_A;
3997 case ISD::SETULE: return X86::COND_BE;
3998 case ISD::SETUGE: return X86::COND_AE;
4002 // First determine if it is required or is profitable to flip the operands.
4004 // If LHS is a foldable load, but RHS is not, flip the condition.
4005 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4006 !ISD::isNON_EXTLoad(RHS.getNode())) {
4007 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4008 std::swap(LHS, RHS);
4011 switch (SetCCOpcode) {
4017 std::swap(LHS, RHS);
4021 // On a floating point condition, the flags are set as follows:
4023 // 0 | 0 | 0 | X > Y
4024 // 0 | 0 | 1 | X < Y
4025 // 1 | 0 | 0 | X == Y
4026 // 1 | 1 | 1 | unordered
4027 switch (SetCCOpcode) {
4028 default: llvm_unreachable("Condcode should be pre-legalized away");
4030 case ISD::SETEQ: return X86::COND_E;
4031 case ISD::SETOLT: // flipped
4033 case ISD::SETGT: return X86::COND_A;
4034 case ISD::SETOLE: // flipped
4036 case ISD::SETGE: return X86::COND_AE;
4037 case ISD::SETUGT: // flipped
4039 case ISD::SETLT: return X86::COND_B;
4040 case ISD::SETUGE: // flipped
4042 case ISD::SETLE: return X86::COND_BE;
4044 case ISD::SETNE: return X86::COND_NE;
4045 case ISD::SETUO: return X86::COND_P;
4046 case ISD::SETO: return X86::COND_NP;
4048 case ISD::SETUNE: return X86::COND_INVALID;
4052 /// Is there a floating point cmov for the specific X86 condition code?
4053 /// Current x86 isa includes the following FP cmov instructions:
4054 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4055 static bool hasFPCMov(unsigned X86CC) {
4071 /// Returns true if the target can instruction select the
4072 /// specified FP immediate natively. If false, the legalizer will
4073 /// materialize the FP immediate as a load from a constant pool.
4074 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4075 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4076 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4082 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4083 ISD::LoadExtType ExtTy,
4085 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4086 // relocation target a movq or addq instruction: don't let the load shrink.
4087 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4088 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4089 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4090 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4094 /// \brief Returns true if it is beneficial to convert a load of a constant
4095 /// to just the constant itself.
4096 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4098 assert(Ty->isIntegerTy());
4100 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4101 if (BitSize == 0 || BitSize > 64)
4106 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4107 unsigned Index) const {
4108 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4111 return (Index == 0 || Index == ResVT.getVectorNumElements());
4114 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4115 // Speculate cttz only if we can directly use TZCNT.
4116 return Subtarget->hasBMI();
4119 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4120 // Speculate ctlz only if we can directly use LZCNT.
4121 return Subtarget->hasLZCNT();
4124 /// Return true if every element in Mask, beginning
4125 /// from position Pos and ending in Pos+Size is undef.
4126 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4127 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4133 /// Return true if Val is undef or if its value falls within the
4134 /// specified range (L, H].
4135 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4136 return (Val < 0) || (Val >= Low && Val < Hi);
4139 /// Val is either less than zero (undef) or equal to the specified value.
4140 static bool isUndefOrEqual(int Val, int CmpVal) {
4141 return (Val < 0 || Val == CmpVal);
4144 /// Return true if every element in Mask, beginning
4145 /// from position Pos and ending in Pos+Size, falls within the specified
4146 /// sequential range (Low, Low+Size]. or is undef.
4147 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4148 unsigned Pos, unsigned Size, int Low) {
4149 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4150 if (!isUndefOrEqual(Mask[i], Low))
4155 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4156 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4157 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4158 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4159 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4162 // The index should be aligned on a vecWidth-bit boundary.
4164 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4166 MVT VT = N->getSimpleValueType(0);
4167 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4168 bool Result = (Index * ElSize) % vecWidth == 0;
4173 /// Return true if the specified INSERT_SUBVECTOR
4174 /// operand specifies a subvector insert that is suitable for input to
4175 /// insertion of 128 or 256-bit subvectors
4176 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4177 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4178 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4180 // The index should be aligned on a vecWidth-bit boundary.
4182 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4184 MVT VT = N->getSimpleValueType(0);
4185 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4186 bool Result = (Index * ElSize) % vecWidth == 0;
4191 bool X86::isVINSERT128Index(SDNode *N) {
4192 return isVINSERTIndex(N, 128);
4195 bool X86::isVINSERT256Index(SDNode *N) {
4196 return isVINSERTIndex(N, 256);
4199 bool X86::isVEXTRACT128Index(SDNode *N) {
4200 return isVEXTRACTIndex(N, 128);
4203 bool X86::isVEXTRACT256Index(SDNode *N) {
4204 return isVEXTRACTIndex(N, 256);
4207 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4208 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4209 assert(isa<ConstantSDNode>(N->getOperand(1).getNode()) &&
4210 "Illegal extract subvector for VEXTRACT");
4213 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4215 MVT VecVT = N->getOperand(0).getSimpleValueType();
4216 MVT ElVT = VecVT.getVectorElementType();
4218 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4219 return Index / NumElemsPerChunk;
4222 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4223 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4224 assert(isa<ConstantSDNode>(N->getOperand(2).getNode()) &&
4225 "Illegal insert subvector for VINSERT");
4228 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4230 MVT VecVT = N->getSimpleValueType(0);
4231 MVT ElVT = VecVT.getVectorElementType();
4233 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4234 return Index / NumElemsPerChunk;
4237 /// Return the appropriate immediate to extract the specified
4238 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4239 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4240 return getExtractVEXTRACTImmediate(N, 128);
4243 /// Return the appropriate immediate to extract the specified
4244 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4245 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4246 return getExtractVEXTRACTImmediate(N, 256);
4249 /// Return the appropriate immediate to insert at the specified
4250 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4251 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4252 return getInsertVINSERTImmediate(N, 128);
4255 /// Return the appropriate immediate to insert at the specified
4256 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4257 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4258 return getInsertVINSERTImmediate(N, 256);
4261 /// Returns true if V is a constant integer zero.
4262 static bool isZero(SDValue V) {
4263 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4264 return C && C->isNullValue();
4267 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4268 bool X86::isZeroNode(SDValue Elt) {
4271 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4272 return CFP->getValueAPF().isPosZero();
4276 // Build a vector of constants
4277 // Use an UNDEF node if MaskElt == -1.
4278 // Spilt 64-bit constants in the 32-bit mode.
4279 static SDValue getConstVector(ArrayRef<int> Values, MVT VT,
4281 SDLoc dl, bool IsMask = false) {
4283 SmallVector<SDValue, 32> Ops;
4286 MVT ConstVecVT = VT;
4287 unsigned NumElts = VT.getVectorNumElements();
4288 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4289 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4290 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4294 MVT EltVT = ConstVecVT.getVectorElementType();
4295 for (unsigned i = 0; i < NumElts; ++i) {
4296 bool IsUndef = Values[i] < 0 && IsMask;
4297 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4298 DAG.getConstant(Values[i], dl, EltVT);
4299 Ops.push_back(OpNode);
4301 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4302 DAG.getConstant(0, dl, EltVT));
4304 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4306 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4310 /// Returns a vector of specified type with all zero elements.
4311 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4312 SelectionDAG &DAG, SDLoc dl) {
4313 assert(VT.isVector() && "Expected a vector type");
4315 // Always build SSE zero vectors as <4 x i32> bitcasted
4316 // to their dest type. This ensures they get CSE'd.
4318 if (VT.is128BitVector()) { // SSE
4319 if (Subtarget->hasSSE2()) { // SSE2
4320 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4321 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4323 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4324 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4326 } else if (VT.is256BitVector()) { // AVX
4327 if (Subtarget->hasInt256()) { // AVX2
4328 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4329 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4330 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4332 // 256-bit logic and arithmetic instructions in AVX are all
4333 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4334 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4335 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4336 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4338 } else if (VT.is512BitVector()) { // AVX-512
4339 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4340 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4341 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4342 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4343 } else if (VT.getVectorElementType() == MVT::i1) {
4345 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4346 && "Unexpected vector type");
4347 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4348 && "Unexpected vector type");
4349 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4350 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4351 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4353 llvm_unreachable("Unexpected vector type");
4355 return DAG.getBitcast(VT, Vec);
4358 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4359 SelectionDAG &DAG, SDLoc dl,
4360 unsigned vectorWidth) {
4361 assert((vectorWidth == 128 || vectorWidth == 256) &&
4362 "Unsupported vector width");
4363 EVT VT = Vec.getValueType();
4364 EVT ElVT = VT.getVectorElementType();
4365 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4366 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4367 VT.getVectorNumElements()/Factor);
4369 // Extract from UNDEF is UNDEF.
4370 if (Vec.getOpcode() == ISD::UNDEF)
4371 return DAG.getUNDEF(ResultVT);
4373 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4374 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4375 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4377 // This is the index of the first element of the vectorWidth-bit chunk
4378 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4379 IdxVal &= ~(ElemsPerChunk - 1);
4381 // If the input is a buildvector just emit a smaller one.
4382 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4383 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4384 makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk));
4386 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4387 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4390 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4391 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4392 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4393 /// instructions or a simple subregister reference. Idx is an index in the
4394 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4395 /// lowering EXTRACT_VECTOR_ELT operations easier.
4396 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4397 SelectionDAG &DAG, SDLoc dl) {
4398 assert((Vec.getValueType().is256BitVector() ||
4399 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4400 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4403 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4404 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4405 SelectionDAG &DAG, SDLoc dl) {
4406 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4407 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4410 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4411 unsigned IdxVal, SelectionDAG &DAG,
4412 SDLoc dl, unsigned vectorWidth) {
4413 assert((vectorWidth == 128 || vectorWidth == 256) &&
4414 "Unsupported vector width");
4415 // Inserting UNDEF is Result
4416 if (Vec.getOpcode() == ISD::UNDEF)
4418 EVT VT = Vec.getValueType();
4419 EVT ElVT = VT.getVectorElementType();
4420 EVT ResultVT = Result.getValueType();
4422 // Insert the relevant vectorWidth bits.
4423 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4424 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4426 // This is the index of the first element of the vectorWidth-bit chunk
4427 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4428 IdxVal &= ~(ElemsPerChunk - 1);
4430 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4431 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4434 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4435 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4436 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4437 /// simple superregister reference. Idx is an index in the 128 bits
4438 /// we want. It need not be aligned to a 128-bit boundary. That makes
4439 /// lowering INSERT_VECTOR_ELT operations easier.
4440 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4441 SelectionDAG &DAG, SDLoc dl) {
4442 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4444 // For insertion into the zero index (low half) of a 256-bit vector, it is
4445 // more efficient to generate a blend with immediate instead of an insert*128.
4446 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4447 // extend the subvector to the size of the result vector. Make sure that
4448 // we are not recursing on that node by checking for undef here.
4449 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4450 Result.getOpcode() != ISD::UNDEF) {
4451 EVT ResultVT = Result.getValueType();
4452 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4453 SDValue Undef = DAG.getUNDEF(ResultVT);
4454 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4457 // The blend instruction, and therefore its mask, depend on the data type.
4458 MVT ScalarType = ResultVT.getVectorElementType().getSimpleVT();
4459 if (ScalarType.isFloatingPoint()) {
4460 // Choose either vblendps (float) or vblendpd (double).
4461 unsigned ScalarSize = ScalarType.getSizeInBits();
4462 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4463 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4464 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4465 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4468 const X86Subtarget &Subtarget =
4469 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4471 // AVX2 is needed for 256-bit integer blend support.
4472 // Integers must be cast to 32-bit because there is only vpblendd;
4473 // vpblendw can't be used for this because it has a handicapped mask.
4475 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4476 // is still more efficient than using the wrong domain vinsertf128 that
4477 // will be created by InsertSubVector().
4478 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4480 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4481 Vec256 = DAG.getBitcast(CastVT, Vec256);
4482 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4483 return DAG.getBitcast(ResultVT, Vec256);
4486 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4489 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4490 SelectionDAG &DAG, SDLoc dl) {
4491 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4492 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4495 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4496 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4497 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4498 /// large BUILD_VECTORS.
4499 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4500 unsigned NumElems, SelectionDAG &DAG,
4502 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4503 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4506 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4507 unsigned NumElems, SelectionDAG &DAG,
4509 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4510 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4513 /// Returns a vector of specified type with all bits set.
4514 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4515 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4516 /// Then bitcast to their original type, ensuring they get CSE'd.
4517 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4518 SelectionDAG &DAG, SDLoc dl) {
4519 assert(VT.isVector() && "Expected a vector type");
4521 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4523 if (VT.is512BitVector()) {
4524 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4525 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4526 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4527 } else if (VT.is256BitVector()) {
4528 if (Subtarget->hasInt256()) { // AVX2
4529 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4530 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4532 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4533 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4535 } else if (VT.is128BitVector()) {
4536 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4538 llvm_unreachable("Unexpected vector type");
4540 return DAG.getBitcast(VT, Vec);
4543 /// Returns a vector_shuffle node for an unpackl operation.
4544 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4546 unsigned NumElems = VT.getVectorNumElements();
4547 SmallVector<int, 8> Mask;
4548 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4550 Mask.push_back(i + NumElems);
4552 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4555 /// Returns a vector_shuffle node for an unpackh operation.
4556 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4558 unsigned NumElems = VT.getVectorNumElements();
4559 SmallVector<int, 8> Mask;
4560 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4561 Mask.push_back(i + Half);
4562 Mask.push_back(i + NumElems + Half);
4564 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4567 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4568 /// This produces a shuffle where the low element of V2 is swizzled into the
4569 /// zero/undef vector, landing at element Idx.
4570 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4571 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4573 const X86Subtarget *Subtarget,
4574 SelectionDAG &DAG) {
4575 MVT VT = V2.getSimpleValueType();
4577 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4578 unsigned NumElems = VT.getVectorNumElements();
4579 SmallVector<int, 16> MaskVec;
4580 for (unsigned i = 0; i != NumElems; ++i)
4581 // If this is the insertion idx, put the low elt of V2 here.
4582 MaskVec.push_back(i == Idx ? NumElems : i);
4583 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4586 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4587 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4588 /// uses one source. Note that this will set IsUnary for shuffles which use a
4589 /// single input multiple times, and in those cases it will
4590 /// adjust the mask to only have indices within that single input.
4591 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4592 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4593 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4594 unsigned NumElems = VT.getVectorNumElements();
4598 bool IsFakeUnary = false;
4599 switch(N->getOpcode()) {
4600 case X86ISD::BLENDI:
4601 ImmN = N->getOperand(N->getNumOperands()-1);
4602 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4605 ImmN = N->getOperand(N->getNumOperands()-1);
4606 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4607 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4609 case X86ISD::UNPCKH:
4610 DecodeUNPCKHMask(VT, Mask);
4611 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4613 case X86ISD::UNPCKL:
4614 DecodeUNPCKLMask(VT, Mask);
4615 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4617 case X86ISD::MOVHLPS:
4618 DecodeMOVHLPSMask(NumElems, Mask);
4619 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4621 case X86ISD::MOVLHPS:
4622 DecodeMOVLHPSMask(NumElems, Mask);
4623 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4625 case X86ISD::PALIGNR:
4626 ImmN = N->getOperand(N->getNumOperands()-1);
4627 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4629 case X86ISD::PSHUFD:
4630 case X86ISD::VPERMILPI:
4631 ImmN = N->getOperand(N->getNumOperands()-1);
4632 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4635 case X86ISD::PSHUFHW:
4636 ImmN = N->getOperand(N->getNumOperands()-1);
4637 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4640 case X86ISD::PSHUFLW:
4641 ImmN = N->getOperand(N->getNumOperands()-1);
4642 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4645 case X86ISD::PSHUFB: {
4647 SDValue MaskNode = N->getOperand(1);
4648 while (MaskNode->getOpcode() == ISD::BITCAST)
4649 MaskNode = MaskNode->getOperand(0);
4651 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4652 // If we have a build-vector, then things are easy.
4653 MVT VT = MaskNode.getSimpleValueType();
4654 assert(VT.isVector() &&
4655 "Can't produce a non-vector with a build_vector!");
4656 if (!VT.isInteger())
4659 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4661 SmallVector<uint64_t, 32> RawMask;
4662 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4663 SDValue Op = MaskNode->getOperand(i);
4664 if (Op->getOpcode() == ISD::UNDEF) {
4665 RawMask.push_back((uint64_t)SM_SentinelUndef);
4668 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4671 APInt MaskElement = CN->getAPIntValue();
4673 // We now have to decode the element which could be any integer size and
4674 // extract each byte of it.
4675 for (int j = 0; j < NumBytesPerElement; ++j) {
4676 // Note that this is x86 and so always little endian: the low byte is
4677 // the first byte of the mask.
4678 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4679 MaskElement = MaskElement.lshr(8);
4682 DecodePSHUFBMask(RawMask, Mask);
4686 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4690 SDValue Ptr = MaskLoad->getBasePtr();
4691 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4692 Ptr->getOpcode() == X86ISD::WrapperRIP)
4693 Ptr = Ptr->getOperand(0);
4695 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4696 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4699 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4700 DecodePSHUFBMask(C, Mask);
4708 case X86ISD::VPERMI:
4709 ImmN = N->getOperand(N->getNumOperands()-1);
4710 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4715 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4717 case X86ISD::VPERM2X128:
4718 ImmN = N->getOperand(N->getNumOperands()-1);
4719 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4720 if (Mask.empty()) return false;
4721 // Mask only contains negative index if an element is zero.
4722 if (std::any_of(Mask.begin(), Mask.end(),
4723 [](int M){ return M == SM_SentinelZero; }))
4726 case X86ISD::MOVSLDUP:
4727 DecodeMOVSLDUPMask(VT, Mask);
4730 case X86ISD::MOVSHDUP:
4731 DecodeMOVSHDUPMask(VT, Mask);
4734 case X86ISD::MOVDDUP:
4735 DecodeMOVDDUPMask(VT, Mask);
4738 case X86ISD::MOVLHPD:
4739 case X86ISD::MOVLPD:
4740 case X86ISD::MOVLPS:
4741 // Not yet implemented
4743 case X86ISD::VPERMV: {
4745 SDValue MaskNode = N->getOperand(0);
4746 while (MaskNode->getOpcode() == ISD::BITCAST)
4747 MaskNode = MaskNode->getOperand(0);
4749 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4750 SmallVector<uint64_t, 32> RawMask;
4751 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4752 // If we have a build-vector, then things are easy.
4753 assert(MaskNode.getSimpleValueType().isInteger() &&
4754 MaskNode.getSimpleValueType().getVectorNumElements() ==
4755 VT.getVectorNumElements());
4757 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4758 SDValue Op = MaskNode->getOperand(i);
4759 if (Op->getOpcode() == ISD::UNDEF)
4760 RawMask.push_back((uint64_t)SM_SentinelUndef);
4761 else if (isa<ConstantSDNode>(Op)) {
4762 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4763 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4767 DecodeVPERMVMask(RawMask, Mask);
4770 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4771 unsigned NumEltsInMask = MaskNode->getNumOperands();
4772 MaskNode = MaskNode->getOperand(0);
4773 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4775 APInt MaskEltValue = CN->getAPIntValue();
4776 for (unsigned i = 0; i < NumEltsInMask; ++i)
4777 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4778 DecodeVPERMVMask(RawMask, Mask);
4781 // It may be a scalar load
4784 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4788 SDValue Ptr = MaskLoad->getBasePtr();
4789 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4790 Ptr->getOpcode() == X86ISD::WrapperRIP)
4791 Ptr = Ptr->getOperand(0);
4793 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4794 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4797 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4799 DecodeVPERMVMask(C, VT, Mask);
4806 case X86ISD::VPERMV3: {
4808 SDValue MaskNode = N->getOperand(1);
4809 while (MaskNode->getOpcode() == ISD::BITCAST)
4810 MaskNode = MaskNode->getOperand(1);
4812 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4813 // If we have a build-vector, then things are easy.
4814 assert(MaskNode.getSimpleValueType().isInteger() &&
4815 MaskNode.getSimpleValueType().getVectorNumElements() ==
4816 VT.getVectorNumElements());
4818 SmallVector<uint64_t, 32> RawMask;
4819 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4821 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4822 SDValue Op = MaskNode->getOperand(i);
4823 if (Op->getOpcode() == ISD::UNDEF)
4824 RawMask.push_back((uint64_t)SM_SentinelUndef);
4826 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4829 APInt MaskElement = CN->getAPIntValue();
4830 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4833 DecodeVPERMV3Mask(RawMask, Mask);
4837 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4841 SDValue Ptr = MaskLoad->getBasePtr();
4842 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4843 Ptr->getOpcode() == X86ISD::WrapperRIP)
4844 Ptr = Ptr->getOperand(0);
4846 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4847 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4850 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4852 DecodeVPERMV3Mask(C, VT, Mask);
4859 default: llvm_unreachable("unknown target shuffle node");
4862 // If we have a fake unary shuffle, the shuffle mask is spread across two
4863 // inputs that are actually the same node. Re-map the mask to always point
4864 // into the first input.
4867 if (M >= (int)Mask.size())
4873 /// Returns the scalar element that will make up the ith
4874 /// element of the result of the vector shuffle.
4875 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4878 return SDValue(); // Limit search depth.
4880 SDValue V = SDValue(N, 0);
4881 EVT VT = V.getValueType();
4882 unsigned Opcode = V.getOpcode();
4884 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4885 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4886 int Elt = SV->getMaskElt(Index);
4889 return DAG.getUNDEF(VT.getVectorElementType());
4891 unsigned NumElems = VT.getVectorNumElements();
4892 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4893 : SV->getOperand(1);
4894 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4897 // Recurse into target specific vector shuffles to find scalars.
4898 if (isTargetShuffle(Opcode)) {
4899 MVT ShufVT = V.getSimpleValueType();
4900 unsigned NumElems = ShufVT.getVectorNumElements();
4901 SmallVector<int, 16> ShuffleMask;
4904 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4907 int Elt = ShuffleMask[Index];
4909 return DAG.getUNDEF(ShufVT.getVectorElementType());
4911 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4913 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4917 // Actual nodes that may contain scalar elements
4918 if (Opcode == ISD::BITCAST) {
4919 V = V.getOperand(0);
4920 EVT SrcVT = V.getValueType();
4921 unsigned NumElems = VT.getVectorNumElements();
4923 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4927 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4928 return (Index == 0) ? V.getOperand(0)
4929 : DAG.getUNDEF(VT.getVectorElementType());
4931 if (V.getOpcode() == ISD::BUILD_VECTOR)
4932 return V.getOperand(Index);
4937 /// Custom lower build_vector of v16i8.
4938 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4939 unsigned NumNonZero, unsigned NumZero,
4941 const X86Subtarget* Subtarget,
4942 const TargetLowering &TLI) {
4950 // SSE4.1 - use PINSRB to insert each byte directly.
4951 if (Subtarget->hasSSE41()) {
4952 for (unsigned i = 0; i < 16; ++i) {
4953 bool isNonZero = (NonZeros & (1 << i)) != 0;
4957 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4959 V = DAG.getUNDEF(MVT::v16i8);
4962 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4963 MVT::v16i8, V, Op.getOperand(i),
4964 DAG.getIntPtrConstant(i, dl));
4971 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4972 for (unsigned i = 0; i < 16; ++i) {
4973 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4974 if (ThisIsNonZero && First) {
4976 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4978 V = DAG.getUNDEF(MVT::v8i16);
4983 SDValue ThisElt, LastElt;
4984 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4985 if (LastIsNonZero) {
4986 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4987 MVT::i16, Op.getOperand(i-1));
4989 if (ThisIsNonZero) {
4990 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4991 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4992 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4994 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4998 if (ThisElt.getNode())
4999 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5000 DAG.getIntPtrConstant(i/2, dl));
5004 return DAG.getBitcast(MVT::v16i8, V);
5007 /// Custom lower build_vector of v8i16.
5008 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5009 unsigned NumNonZero, unsigned NumZero,
5011 const X86Subtarget* Subtarget,
5012 const TargetLowering &TLI) {
5019 for (unsigned i = 0; i < 8; ++i) {
5020 bool isNonZero = (NonZeros & (1 << i)) != 0;
5024 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5026 V = DAG.getUNDEF(MVT::v8i16);
5029 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5030 MVT::v8i16, V, Op.getOperand(i),
5031 DAG.getIntPtrConstant(i, dl));
5038 /// Custom lower build_vector of v4i32 or v4f32.
5039 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5040 const X86Subtarget *Subtarget,
5041 const TargetLowering &TLI) {
5042 // Find all zeroable elements.
5043 std::bitset<4> Zeroable;
5044 for (int i=0; i < 4; ++i) {
5045 SDValue Elt = Op->getOperand(i);
5046 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5048 assert(Zeroable.size() - Zeroable.count() > 1 &&
5049 "We expect at least two non-zero elements!");
5051 // We only know how to deal with build_vector nodes where elements are either
5052 // zeroable or extract_vector_elt with constant index.
5053 SDValue FirstNonZero;
5054 unsigned FirstNonZeroIdx;
5055 for (unsigned i=0; i < 4; ++i) {
5058 SDValue Elt = Op->getOperand(i);
5059 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5060 !isa<ConstantSDNode>(Elt.getOperand(1)))
5062 // Make sure that this node is extracting from a 128-bit vector.
5063 MVT VT = Elt.getOperand(0).getSimpleValueType();
5064 if (!VT.is128BitVector())
5066 if (!FirstNonZero.getNode()) {
5068 FirstNonZeroIdx = i;
5072 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5073 SDValue V1 = FirstNonZero.getOperand(0);
5074 MVT VT = V1.getSimpleValueType();
5076 // See if this build_vector can be lowered as a blend with zero.
5078 unsigned EltMaskIdx, EltIdx;
5080 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5081 if (Zeroable[EltIdx]) {
5082 // The zero vector will be on the right hand side.
5083 Mask[EltIdx] = EltIdx+4;
5087 Elt = Op->getOperand(EltIdx);
5088 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5089 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5090 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5092 Mask[EltIdx] = EltIdx;
5096 // Let the shuffle legalizer deal with blend operations.
5097 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5098 if (V1.getSimpleValueType() != VT)
5099 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5100 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5103 // See if we can lower this build_vector to a INSERTPS.
5104 if (!Subtarget->hasSSE41())
5107 SDValue V2 = Elt.getOperand(0);
5108 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5111 bool CanFold = true;
5112 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5116 SDValue Current = Op->getOperand(i);
5117 SDValue SrcVector = Current->getOperand(0);
5120 CanFold = SrcVector == V1 &&
5121 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5127 assert(V1.getNode() && "Expected at least two non-zero elements!");
5128 if (V1.getSimpleValueType() != MVT::v4f32)
5129 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5130 if (V2.getSimpleValueType() != MVT::v4f32)
5131 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5133 // Ok, we can emit an INSERTPS instruction.
5134 unsigned ZMask = Zeroable.to_ulong();
5136 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5137 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5139 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5140 DAG.getIntPtrConstant(InsertPSMask, DL));
5141 return DAG.getBitcast(VT, Result);
5144 /// Return a vector logical shift node.
5145 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5146 unsigned NumBits, SelectionDAG &DAG,
5147 const TargetLowering &TLI, SDLoc dl) {
5148 assert(VT.is128BitVector() && "Unknown type for VShift");
5149 MVT ShVT = MVT::v2i64;
5150 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5151 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5152 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5153 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5154 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5155 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5159 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5161 // Check if the scalar load can be widened into a vector load. And if
5162 // the address is "base + cst" see if the cst can be "absorbed" into
5163 // the shuffle mask.
5164 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5165 SDValue Ptr = LD->getBasePtr();
5166 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5168 EVT PVT = LD->getValueType(0);
5169 if (PVT != MVT::i32 && PVT != MVT::f32)
5174 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5175 FI = FINode->getIndex();
5177 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5178 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5179 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5180 Offset = Ptr.getConstantOperandVal(1);
5181 Ptr = Ptr.getOperand(0);
5186 // FIXME: 256-bit vector instructions don't require a strict alignment,
5187 // improve this code to support it better.
5188 unsigned RequiredAlign = VT.getSizeInBits()/8;
5189 SDValue Chain = LD->getChain();
5190 // Make sure the stack object alignment is at least 16 or 32.
5191 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5192 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5193 if (MFI->isFixedObjectIndex(FI)) {
5194 // Can't change the alignment. FIXME: It's possible to compute
5195 // the exact stack offset and reference FI + adjust offset instead.
5196 // If someone *really* cares about this. That's the way to implement it.
5199 MFI->setObjectAlignment(FI, RequiredAlign);
5203 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5204 // Ptr + (Offset & ~15).
5207 if ((Offset % RequiredAlign) & 3)
5209 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5212 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5213 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5216 int EltNo = (Offset - StartOffset) >> 2;
5217 unsigned NumElems = VT.getVectorNumElements();
5219 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5220 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5221 LD->getPointerInfo().getWithOffset(StartOffset),
5222 false, false, false, 0);
5224 SmallVector<int, 8> Mask(NumElems, EltNo);
5226 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5232 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5233 /// elements can be replaced by a single large load which has the same value as
5234 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5236 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5238 /// FIXME: we'd also like to handle the case where the last elements are zero
5239 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5240 /// There's even a handy isZeroNode for that purpose.
5241 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5242 SDLoc &DL, SelectionDAG &DAG,
5243 bool isAfterLegalize) {
5244 unsigned NumElems = Elts.size();
5246 LoadSDNode *LDBase = nullptr;
5247 unsigned LastLoadedElt = -1U;
5249 // For each element in the initializer, see if we've found a load or an undef.
5250 // If we don't find an initial load element, or later load elements are
5251 // non-consecutive, bail out.
5252 for (unsigned i = 0; i < NumElems; ++i) {
5253 SDValue Elt = Elts[i];
5254 // Look through a bitcast.
5255 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5256 Elt = Elt.getOperand(0);
5257 if (!Elt.getNode() ||
5258 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5261 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5263 LDBase = cast<LoadSDNode>(Elt.getNode());
5267 if (Elt.getOpcode() == ISD::UNDEF)
5270 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5271 EVT LdVT = Elt.getValueType();
5272 // Each loaded element must be the correct fractional portion of the
5273 // requested vector load.
5274 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5276 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5281 // If we have found an entire vector of loads and undefs, then return a large
5282 // load of the entire vector width starting at the base pointer. If we found
5283 // consecutive loads for the low half, generate a vzext_load node.
5284 if (LastLoadedElt == NumElems - 1) {
5285 assert(LDBase && "Did not find base load for merging consecutive loads");
5286 EVT EltVT = LDBase->getValueType(0);
5287 // Ensure that the input vector size for the merged loads matches the
5288 // cumulative size of the input elements.
5289 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5292 if (isAfterLegalize &&
5293 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5296 SDValue NewLd = SDValue();
5298 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5299 LDBase->getPointerInfo(), LDBase->isVolatile(),
5300 LDBase->isNonTemporal(), LDBase->isInvariant(),
5301 LDBase->getAlignment());
5303 if (LDBase->hasAnyUseOfValue(1)) {
5304 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5306 SDValue(NewLd.getNode(), 1));
5307 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5308 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5309 SDValue(NewLd.getNode(), 1));
5315 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5316 //of a v4i32 / v4f32. It's probably worth generalizing.
5317 EVT EltVT = VT.getVectorElementType();
5318 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5319 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5320 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5321 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5323 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5324 LDBase->getPointerInfo(),
5325 LDBase->getAlignment(),
5326 false/*isVolatile*/, true/*ReadMem*/,
5329 // Make sure the newly-created LOAD is in the same position as LDBase in
5330 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5331 // update uses of LDBase's output chain to use the TokenFactor.
5332 if (LDBase->hasAnyUseOfValue(1)) {
5333 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5334 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5335 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5336 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5337 SDValue(ResNode.getNode(), 1));
5340 return DAG.getBitcast(VT, ResNode);
5345 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5346 /// to generate a splat value for the following cases:
5347 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5348 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5349 /// a scalar load, or a constant.
5350 /// The VBROADCAST node is returned when a pattern is found,
5351 /// or SDValue() otherwise.
5352 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5353 SelectionDAG &DAG) {
5354 // VBROADCAST requires AVX.
5355 // TODO: Splats could be generated for non-AVX CPUs using SSE
5356 // instructions, but there's less potential gain for only 128-bit vectors.
5357 if (!Subtarget->hasAVX())
5360 MVT VT = Op.getSimpleValueType();
5363 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5364 "Unsupported vector type for broadcast.");
5369 switch (Op.getOpcode()) {
5371 // Unknown pattern found.
5374 case ISD::BUILD_VECTOR: {
5375 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5376 BitVector UndefElements;
5377 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5379 // We need a splat of a single value to use broadcast, and it doesn't
5380 // make any sense if the value is only in one element of the vector.
5381 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5385 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5386 Ld.getOpcode() == ISD::ConstantFP);
5388 // Make sure that all of the users of a non-constant load are from the
5389 // BUILD_VECTOR node.
5390 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5395 case ISD::VECTOR_SHUFFLE: {
5396 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5398 // Shuffles must have a splat mask where the first element is
5400 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5403 SDValue Sc = Op.getOperand(0);
5404 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5405 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5407 if (!Subtarget->hasInt256())
5410 // Use the register form of the broadcast instruction available on AVX2.
5411 if (VT.getSizeInBits() >= 256)
5412 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5413 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5416 Ld = Sc.getOperand(0);
5417 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5418 Ld.getOpcode() == ISD::ConstantFP);
5420 // The scalar_to_vector node and the suspected
5421 // load node must have exactly one user.
5422 // Constants may have multiple users.
5424 // AVX-512 has register version of the broadcast
5425 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5426 Ld.getValueType().getSizeInBits() >= 32;
5427 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5434 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5435 bool IsGE256 = (VT.getSizeInBits() >= 256);
5437 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5438 // instruction to save 8 or more bytes of constant pool data.
5439 // TODO: If multiple splats are generated to load the same constant,
5440 // it may be detrimental to overall size. There needs to be a way to detect
5441 // that condition to know if this is truly a size win.
5442 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5444 // Handle broadcasting a single constant scalar from the constant pool
5446 // On Sandybridge (no AVX2), it is still better to load a constant vector
5447 // from the constant pool and not to broadcast it from a scalar.
5448 // But override that restriction when optimizing for size.
5449 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5450 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5451 EVT CVT = Ld.getValueType();
5452 assert(!CVT.isVector() && "Must not broadcast a vector type");
5454 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5455 // For size optimization, also splat v2f64 and v2i64, and for size opt
5456 // with AVX2, also splat i8 and i16.
5457 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5458 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5459 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5460 const Constant *C = nullptr;
5461 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5462 C = CI->getConstantIntValue();
5463 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5464 C = CF->getConstantFPValue();
5466 assert(C && "Invalid constant type");
5468 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5470 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5471 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5473 CVT, dl, DAG.getEntryNode(), CP,
5474 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5475 false, false, Alignment);
5477 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5481 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5483 // Handle AVX2 in-register broadcasts.
5484 if (!IsLoad && Subtarget->hasInt256() &&
5485 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5486 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5488 // The scalar source must be a normal load.
5492 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5493 (Subtarget->hasVLX() && ScalarSize == 64))
5494 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5496 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5497 // double since there is no vbroadcastsd xmm
5498 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5499 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5500 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5503 // Unsupported broadcast.
5507 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5508 /// underlying vector and index.
5510 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5512 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5514 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5515 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5518 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5520 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5522 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5523 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5526 // In this case the vector is the extract_subvector expression and the index
5527 // is 2, as specified by the shuffle.
5528 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5529 SDValue ShuffleVec = SVOp->getOperand(0);
5530 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5531 assert(ShuffleVecVT.getVectorElementType() ==
5532 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5534 int ShuffleIdx = SVOp->getMaskElt(Idx);
5535 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5536 ExtractedFromVec = ShuffleVec;
5542 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5543 MVT VT = Op.getSimpleValueType();
5545 // Skip if insert_vec_elt is not supported.
5546 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5547 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5551 unsigned NumElems = Op.getNumOperands();
5555 SmallVector<unsigned, 4> InsertIndices;
5556 SmallVector<int, 8> Mask(NumElems, -1);
5558 for (unsigned i = 0; i != NumElems; ++i) {
5559 unsigned Opc = Op.getOperand(i).getOpcode();
5561 if (Opc == ISD::UNDEF)
5564 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5565 // Quit if more than 1 elements need inserting.
5566 if (InsertIndices.size() > 1)
5569 InsertIndices.push_back(i);
5573 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5574 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5575 // Quit if non-constant index.
5576 if (!isa<ConstantSDNode>(ExtIdx))
5578 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5580 // Quit if extracted from vector of different type.
5581 if (ExtractedFromVec.getValueType() != VT)
5584 if (!VecIn1.getNode())
5585 VecIn1 = ExtractedFromVec;
5586 else if (VecIn1 != ExtractedFromVec) {
5587 if (!VecIn2.getNode())
5588 VecIn2 = ExtractedFromVec;
5589 else if (VecIn2 != ExtractedFromVec)
5590 // Quit if more than 2 vectors to shuffle
5594 if (ExtractedFromVec == VecIn1)
5596 else if (ExtractedFromVec == VecIn2)
5597 Mask[i] = Idx + NumElems;
5600 if (!VecIn1.getNode())
5603 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5604 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5605 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5606 unsigned Idx = InsertIndices[i];
5607 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5608 DAG.getIntPtrConstant(Idx, DL));
5614 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5615 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5616 Op.getScalarValueSizeInBits() == 1 &&
5617 "Can not convert non-constant vector");
5618 uint64_t Immediate = 0;
5619 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5620 SDValue In = Op.getOperand(idx);
5621 if (In.getOpcode() != ISD::UNDEF)
5622 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5626 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5627 return DAG.getConstant(Immediate, dl, VT);
5629 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5631 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5633 MVT VT = Op.getSimpleValueType();
5634 assert((VT.getVectorElementType() == MVT::i1) &&
5635 "Unexpected type in LowerBUILD_VECTORvXi1!");
5638 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5639 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5640 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5641 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5644 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5645 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5646 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5647 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5650 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5651 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5652 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5653 return DAG.getBitcast(VT, Imm);
5654 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5655 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5656 DAG.getIntPtrConstant(0, dl));
5659 // Vector has one or more non-const elements
5660 uint64_t Immediate = 0;
5661 SmallVector<unsigned, 16> NonConstIdx;
5662 bool IsSplat = true;
5663 bool HasConstElts = false;
5665 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5666 SDValue In = Op.getOperand(idx);
5667 if (In.getOpcode() == ISD::UNDEF)
5669 if (!isa<ConstantSDNode>(In))
5670 NonConstIdx.push_back(idx);
5672 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5673 HasConstElts = true;
5677 else if (In != Op.getOperand(SplatIdx))
5681 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5683 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5684 DAG.getConstant(1, dl, VT),
5685 DAG.getConstant(0, dl, VT));
5687 // insert elements one by one
5691 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5692 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5694 else if (HasConstElts)
5695 Imm = DAG.getConstant(0, dl, VT);
5697 Imm = DAG.getUNDEF(VT);
5698 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5699 DstVec = DAG.getBitcast(VT, Imm);
5701 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5702 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5703 DAG.getIntPtrConstant(0, dl));
5706 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5707 unsigned InsertIdx = NonConstIdx[i];
5708 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5709 Op.getOperand(InsertIdx),
5710 DAG.getIntPtrConstant(InsertIdx, dl));
5715 /// \brief Return true if \p N implements a horizontal binop and return the
5716 /// operands for the horizontal binop into V0 and V1.
5718 /// This is a helper function of LowerToHorizontalOp().
5719 /// This function checks that the build_vector \p N in input implements a
5720 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5721 /// operation to match.
5722 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5723 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5724 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5727 /// This function only analyzes elements of \p N whose indices are
5728 /// in range [BaseIdx, LastIdx).
5729 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5731 unsigned BaseIdx, unsigned LastIdx,
5732 SDValue &V0, SDValue &V1) {
5733 EVT VT = N->getValueType(0);
5735 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5736 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5737 "Invalid Vector in input!");
5739 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5740 bool CanFold = true;
5741 unsigned ExpectedVExtractIdx = BaseIdx;
5742 unsigned NumElts = LastIdx - BaseIdx;
5743 V0 = DAG.getUNDEF(VT);
5744 V1 = DAG.getUNDEF(VT);
5746 // Check if N implements a horizontal binop.
5747 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5748 SDValue Op = N->getOperand(i + BaseIdx);
5751 if (Op->getOpcode() == ISD::UNDEF) {
5752 // Update the expected vector extract index.
5753 if (i * 2 == NumElts)
5754 ExpectedVExtractIdx = BaseIdx;
5755 ExpectedVExtractIdx += 2;
5759 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5764 SDValue Op0 = Op.getOperand(0);
5765 SDValue Op1 = Op.getOperand(1);
5767 // Try to match the following pattern:
5768 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5769 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5770 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5771 Op0.getOperand(0) == Op1.getOperand(0) &&
5772 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5773 isa<ConstantSDNode>(Op1.getOperand(1)));
5777 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5778 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5780 if (i * 2 < NumElts) {
5781 if (V0.getOpcode() == ISD::UNDEF) {
5782 V0 = Op0.getOperand(0);
5783 if (V0.getValueType() != VT)
5787 if (V1.getOpcode() == ISD::UNDEF) {
5788 V1 = Op0.getOperand(0);
5789 if (V1.getValueType() != VT)
5792 if (i * 2 == NumElts)
5793 ExpectedVExtractIdx = BaseIdx;
5796 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5797 if (I0 == ExpectedVExtractIdx)
5798 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5799 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5800 // Try to match the following dag sequence:
5801 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5802 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5806 ExpectedVExtractIdx += 2;
5812 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5813 /// a concat_vector.
5815 /// This is a helper function of LowerToHorizontalOp().
5816 /// This function expects two 256-bit vectors called V0 and V1.
5817 /// At first, each vector is split into two separate 128-bit vectors.
5818 /// Then, the resulting 128-bit vectors are used to implement two
5819 /// horizontal binary operations.
5821 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5823 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5824 /// the two new horizontal binop.
5825 /// When Mode is set, the first horizontal binop dag node would take as input
5826 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5827 /// horizontal binop dag node would take as input the lower 128-bit of V1
5828 /// and the upper 128-bit of V1.
5830 /// HADD V0_LO, V0_HI
5831 /// HADD V1_LO, V1_HI
5833 /// Otherwise, the first horizontal binop dag node takes as input the lower
5834 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5835 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5837 /// HADD V0_LO, V1_LO
5838 /// HADD V0_HI, V1_HI
5840 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5841 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5842 /// the upper 128-bits of the result.
5843 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5844 SDLoc DL, SelectionDAG &DAG,
5845 unsigned X86Opcode, bool Mode,
5846 bool isUndefLO, bool isUndefHI) {
5847 EVT VT = V0.getValueType();
5848 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5849 "Invalid nodes in input!");
5851 unsigned NumElts = VT.getVectorNumElements();
5852 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5853 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5854 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5855 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5856 EVT NewVT = V0_LO.getValueType();
5858 SDValue LO = DAG.getUNDEF(NewVT);
5859 SDValue HI = DAG.getUNDEF(NewVT);
5862 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5863 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5864 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5865 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5866 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5868 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5869 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5870 V1_LO->getOpcode() != ISD::UNDEF))
5871 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5873 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5874 V1_HI->getOpcode() != ISD::UNDEF))
5875 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5878 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5881 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5883 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5884 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5885 MVT VT = BV->getSimpleValueType(0);
5886 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5887 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5891 unsigned NumElts = VT.getVectorNumElements();
5892 SDValue InVec0 = DAG.getUNDEF(VT);
5893 SDValue InVec1 = DAG.getUNDEF(VT);
5895 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5896 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5898 // Odd-numbered elements in the input build vector are obtained from
5899 // adding two integer/float elements.
5900 // Even-numbered elements in the input build vector are obtained from
5901 // subtracting two integer/float elements.
5902 unsigned ExpectedOpcode = ISD::FSUB;
5903 unsigned NextExpectedOpcode = ISD::FADD;
5904 bool AddFound = false;
5905 bool SubFound = false;
5907 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5908 SDValue Op = BV->getOperand(i);
5910 // Skip 'undef' values.
5911 unsigned Opcode = Op.getOpcode();
5912 if (Opcode == ISD::UNDEF) {
5913 std::swap(ExpectedOpcode, NextExpectedOpcode);
5917 // Early exit if we found an unexpected opcode.
5918 if (Opcode != ExpectedOpcode)
5921 SDValue Op0 = Op.getOperand(0);
5922 SDValue Op1 = Op.getOperand(1);
5924 // Try to match the following pattern:
5925 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5926 // Early exit if we cannot match that sequence.
5927 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5928 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5929 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5930 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5931 Op0.getOperand(1) != Op1.getOperand(1))
5934 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5938 // We found a valid add/sub node. Update the information accordingly.
5944 // Update InVec0 and InVec1.
5945 if (InVec0.getOpcode() == ISD::UNDEF) {
5946 InVec0 = Op0.getOperand(0);
5947 if (InVec0.getSimpleValueType() != VT)
5950 if (InVec1.getOpcode() == ISD::UNDEF) {
5951 InVec1 = Op1.getOperand(0);
5952 if (InVec1.getSimpleValueType() != VT)
5956 // Make sure that operands in input to each add/sub node always
5957 // come from a same pair of vectors.
5958 if (InVec0 != Op0.getOperand(0)) {
5959 if (ExpectedOpcode == ISD::FSUB)
5962 // FADD is commutable. Try to commute the operands
5963 // and then test again.
5964 std::swap(Op0, Op1);
5965 if (InVec0 != Op0.getOperand(0))
5969 if (InVec1 != Op1.getOperand(0))
5972 // Update the pair of expected opcodes.
5973 std::swap(ExpectedOpcode, NextExpectedOpcode);
5976 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5977 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5978 InVec1.getOpcode() != ISD::UNDEF)
5979 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5984 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5985 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5986 const X86Subtarget *Subtarget,
5987 SelectionDAG &DAG) {
5988 MVT VT = BV->getSimpleValueType(0);
5989 unsigned NumElts = VT.getVectorNumElements();
5990 unsigned NumUndefsLO = 0;
5991 unsigned NumUndefsHI = 0;
5992 unsigned Half = NumElts/2;
5994 // Count the number of UNDEF operands in the build_vector in input.
5995 for (unsigned i = 0, e = Half; i != e; ++i)
5996 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5999 for (unsigned i = Half, e = NumElts; i != e; ++i)
6000 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6003 // Early exit if this is either a build_vector of all UNDEFs or all the
6004 // operands but one are UNDEF.
6005 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6009 SDValue InVec0, InVec1;
6010 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6011 // Try to match an SSE3 float HADD/HSUB.
6012 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6013 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6015 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6016 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6017 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6018 // Try to match an SSSE3 integer HADD/HSUB.
6019 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6020 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6022 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6023 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6026 if (!Subtarget->hasAVX())
6029 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6030 // Try to match an AVX horizontal add/sub of packed single/double
6031 // precision floating point values from 256-bit vectors.
6032 SDValue InVec2, InVec3;
6033 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6034 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6035 ((InVec0.getOpcode() == ISD::UNDEF ||
6036 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6037 ((InVec1.getOpcode() == ISD::UNDEF ||
6038 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6039 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6041 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6042 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6043 ((InVec0.getOpcode() == ISD::UNDEF ||
6044 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6045 ((InVec1.getOpcode() == ISD::UNDEF ||
6046 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6047 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6048 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6049 // Try to match an AVX2 horizontal add/sub of signed integers.
6050 SDValue InVec2, InVec3;
6052 bool CanFold = true;
6054 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6055 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6056 ((InVec0.getOpcode() == ISD::UNDEF ||
6057 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6058 ((InVec1.getOpcode() == ISD::UNDEF ||
6059 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6060 X86Opcode = X86ISD::HADD;
6061 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6062 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6063 ((InVec0.getOpcode() == ISD::UNDEF ||
6064 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6065 ((InVec1.getOpcode() == ISD::UNDEF ||
6066 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6067 X86Opcode = X86ISD::HSUB;
6072 // Fold this build_vector into a single horizontal add/sub.
6073 // Do this only if the target has AVX2.
6074 if (Subtarget->hasAVX2())
6075 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6077 // Do not try to expand this build_vector into a pair of horizontal
6078 // add/sub if we can emit a pair of scalar add/sub.
6079 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6082 // Convert this build_vector into a pair of horizontal binop followed by
6084 bool isUndefLO = NumUndefsLO == Half;
6085 bool isUndefHI = NumUndefsHI == Half;
6086 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6087 isUndefLO, isUndefHI);
6091 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6092 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6094 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6095 X86Opcode = X86ISD::HADD;
6096 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6097 X86Opcode = X86ISD::HSUB;
6098 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6099 X86Opcode = X86ISD::FHADD;
6100 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6101 X86Opcode = X86ISD::FHSUB;
6105 // Don't try to expand this build_vector into a pair of horizontal add/sub
6106 // if we can simply emit a pair of scalar add/sub.
6107 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6110 // Convert this build_vector into two horizontal add/sub followed by
6112 bool isUndefLO = NumUndefsLO == Half;
6113 bool isUndefHI = NumUndefsHI == Half;
6114 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6115 isUndefLO, isUndefHI);
6122 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6125 MVT VT = Op.getSimpleValueType();
6126 MVT ExtVT = VT.getVectorElementType();
6127 unsigned NumElems = Op.getNumOperands();
6129 // Generate vectors for predicate vectors.
6130 if (VT.getVectorElementType() == MVT::i1 && Subtarget->hasAVX512())
6131 return LowerBUILD_VECTORvXi1(Op, DAG);
6133 // Vectors containing all zeros can be matched by pxor and xorps later
6134 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6135 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6136 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6137 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6140 return getZeroVector(VT, Subtarget, DAG, dl);
6143 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6144 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6145 // vpcmpeqd on 256-bit vectors.
6146 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6147 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6150 if (!VT.is512BitVector())
6151 return getOnesVector(VT, Subtarget, DAG, dl);
6154 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6155 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6157 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6158 return HorizontalOp;
6159 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6162 unsigned EVTBits = ExtVT.getSizeInBits();
6164 unsigned NumZero = 0;
6165 unsigned NumNonZero = 0;
6166 unsigned NonZeros = 0;
6167 bool IsAllConstants = true;
6168 SmallSet<SDValue, 8> Values;
6169 for (unsigned i = 0; i < NumElems; ++i) {
6170 SDValue Elt = Op.getOperand(i);
6171 if (Elt.getOpcode() == ISD::UNDEF)
6174 if (Elt.getOpcode() != ISD::Constant &&
6175 Elt.getOpcode() != ISD::ConstantFP)
6176 IsAllConstants = false;
6177 if (X86::isZeroNode(Elt))
6180 NonZeros |= (1 << i);
6185 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6186 if (NumNonZero == 0)
6187 return DAG.getUNDEF(VT);
6189 // Special case for single non-zero, non-undef, element.
6190 if (NumNonZero == 1) {
6191 unsigned Idx = countTrailingZeros(NonZeros);
6192 SDValue Item = Op.getOperand(Idx);
6194 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6195 // the value are obviously zero, truncate the value to i32 and do the
6196 // insertion that way. Only do this if the value is non-constant or if the
6197 // value is a constant being inserted into element 0. It is cheaper to do
6198 // a constant pool load than it is to do a movd + shuffle.
6199 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6200 (!IsAllConstants || Idx == 0)) {
6201 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6203 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6204 MVT VecVT = MVT::v4i32;
6206 // Truncate the value (which may itself be a constant) to i32, and
6207 // convert it to a vector with movd (S2V+shuffle to zero extend).
6208 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6209 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6210 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6211 Item, Idx * 2, true, Subtarget, DAG));
6215 // If we have a constant or non-constant insertion into the low element of
6216 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6217 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6218 // depending on what the source datatype is.
6221 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6223 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6224 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6225 if (VT.is512BitVector()) {
6226 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6227 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6228 Item, DAG.getIntPtrConstant(0, dl));
6230 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6231 "Expected an SSE value type!");
6232 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6233 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6234 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6237 // We can't directly insert an i8 or i16 into a vector, so zero extend
6239 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6240 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6241 if (VT.is256BitVector()) {
6242 if (Subtarget->hasAVX()) {
6243 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6244 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6246 // Without AVX, we need to extend to a 128-bit vector and then
6247 // insert into the 256-bit vector.
6248 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6249 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6250 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6253 assert(VT.is128BitVector() && "Expected an SSE value type!");
6254 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6255 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6257 return DAG.getBitcast(VT, Item);
6261 // Is it a vector logical left shift?
6262 if (NumElems == 2 && Idx == 1 &&
6263 X86::isZeroNode(Op.getOperand(0)) &&
6264 !X86::isZeroNode(Op.getOperand(1))) {
6265 unsigned NumBits = VT.getSizeInBits();
6266 return getVShift(true, VT,
6267 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6268 VT, Op.getOperand(1)),
6269 NumBits/2, DAG, *this, dl);
6272 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6275 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6276 // is a non-constant being inserted into an element other than the low one,
6277 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6278 // movd/movss) to move this into the low element, then shuffle it into
6280 if (EVTBits == 32) {
6281 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6282 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6286 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6287 if (Values.size() == 1) {
6288 if (EVTBits == 32) {
6289 // Instead of a shuffle like this:
6290 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6291 // Check if it's possible to issue this instead.
6292 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6293 unsigned Idx = countTrailingZeros(NonZeros);
6294 SDValue Item = Op.getOperand(Idx);
6295 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6296 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6301 // A vector full of immediates; various special cases are already
6302 // handled, so this is best done with a single constant-pool load.
6306 // For AVX-length vectors, see if we can use a vector load to get all of the
6307 // elements, otherwise build the individual 128-bit pieces and use
6308 // shuffles to put them in place.
6309 if (VT.is256BitVector() || VT.is512BitVector()) {
6310 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6312 // Check for a build vector of consecutive loads.
6313 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6316 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6318 // Build both the lower and upper subvector.
6319 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6320 makeArrayRef(&V[0], NumElems/2));
6321 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6322 makeArrayRef(&V[NumElems / 2], NumElems/2));
6324 // Recreate the wider vector with the lower and upper part.
6325 if (VT.is256BitVector())
6326 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6327 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6330 // Let legalizer expand 2-wide build_vectors.
6331 if (EVTBits == 64) {
6332 if (NumNonZero == 1) {
6333 // One half is zero or undef.
6334 unsigned Idx = countTrailingZeros(NonZeros);
6335 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6336 Op.getOperand(Idx));
6337 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6342 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6343 if (EVTBits == 8 && NumElems == 16)
6344 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6348 if (EVTBits == 16 && NumElems == 8)
6349 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6353 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6354 if (EVTBits == 32 && NumElems == 4)
6355 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6358 // If element VT is == 32 bits, turn it into a number of shuffles.
6359 SmallVector<SDValue, 8> V(NumElems);
6360 if (NumElems == 4 && NumZero > 0) {
6361 for (unsigned i = 0; i < 4; ++i) {
6362 bool isZero = !(NonZeros & (1 << i));
6364 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6366 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6369 for (unsigned i = 0; i < 2; ++i) {
6370 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6373 V[i] = V[i*2]; // Must be a zero vector.
6376 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6379 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6382 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6387 bool Reverse1 = (NonZeros & 0x3) == 2;
6388 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6392 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6393 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6395 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6398 if (Values.size() > 1 && VT.is128BitVector()) {
6399 // Check for a build vector of consecutive loads.
6400 for (unsigned i = 0; i < NumElems; ++i)
6401 V[i] = Op.getOperand(i);
6403 // Check for elements which are consecutive loads.
6404 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6407 // Check for a build vector from mostly shuffle plus few inserting.
6408 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6411 // For SSE 4.1, use insertps to put the high elements into the low element.
6412 if (Subtarget->hasSSE41()) {
6414 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6415 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6417 Result = DAG.getUNDEF(VT);
6419 for (unsigned i = 1; i < NumElems; ++i) {
6420 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6421 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6422 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6427 // Otherwise, expand into a number of unpckl*, start by extending each of
6428 // our (non-undef) elements to the full vector width with the element in the
6429 // bottom slot of the vector (which generates no code for SSE).
6430 for (unsigned i = 0; i < NumElems; ++i) {
6431 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6432 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6434 V[i] = DAG.getUNDEF(VT);
6437 // Next, we iteratively mix elements, e.g. for v4f32:
6438 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6439 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6440 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6441 unsigned EltStride = NumElems >> 1;
6442 while (EltStride != 0) {
6443 for (unsigned i = 0; i < EltStride; ++i) {
6444 // If V[i+EltStride] is undef and this is the first round of mixing,
6445 // then it is safe to just drop this shuffle: V[i] is already in the
6446 // right place, the one element (since it's the first round) being
6447 // inserted as undef can be dropped. This isn't safe for successive
6448 // rounds because they will permute elements within both vectors.
6449 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6450 EltStride == NumElems/2)
6453 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6462 // 256-bit AVX can use the vinsertf128 instruction
6463 // to create 256-bit vectors from two other 128-bit ones.
6464 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6466 MVT ResVT = Op.getSimpleValueType();
6468 assert((ResVT.is256BitVector() ||
6469 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6471 SDValue V1 = Op.getOperand(0);
6472 SDValue V2 = Op.getOperand(1);
6473 unsigned NumElems = ResVT.getVectorNumElements();
6474 if (ResVT.is256BitVector())
6475 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6477 if (Op.getNumOperands() == 4) {
6478 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6479 ResVT.getVectorNumElements()/2);
6480 SDValue V3 = Op.getOperand(2);
6481 SDValue V4 = Op.getOperand(3);
6482 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6483 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6485 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6488 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6489 const X86Subtarget *Subtarget,
6490 SelectionDAG & DAG) {
6492 MVT ResVT = Op.getSimpleValueType();
6493 unsigned NumOfOperands = Op.getNumOperands();
6495 assert(isPowerOf2_32(NumOfOperands) &&
6496 "Unexpected number of operands in CONCAT_VECTORS");
6498 if (NumOfOperands > 2) {
6499 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6500 ResVT.getVectorNumElements()/2);
6501 SmallVector<SDValue, 2> Ops;
6502 for (unsigned i = 0; i < NumOfOperands/2; i++)
6503 Ops.push_back(Op.getOperand(i));
6504 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6506 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6507 Ops.push_back(Op.getOperand(i));
6508 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6509 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6512 SDValue V1 = Op.getOperand(0);
6513 SDValue V2 = Op.getOperand(1);
6514 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6515 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6517 if (IsZeroV1 && IsZeroV2)
6518 return getZeroVector(ResVT, Subtarget, DAG, dl);
6520 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6521 SDValue Undef = DAG.getUNDEF(ResVT);
6522 unsigned NumElems = ResVT.getVectorNumElements();
6523 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6525 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6526 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6530 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6531 // Zero the upper bits of V1
6532 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6533 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6536 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6539 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6540 const X86Subtarget *Subtarget,
6541 SelectionDAG &DAG) {
6542 MVT VT = Op.getSimpleValueType();
6543 if (VT.getVectorElementType() == MVT::i1)
6544 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6546 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6547 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6548 Op.getNumOperands() == 4)));
6550 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6551 // from two other 128-bit ones.
6553 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6554 return LowerAVXCONCAT_VECTORS(Op, DAG);
6557 //===----------------------------------------------------------------------===//
6558 // Vector shuffle lowering
6560 // This is an experimental code path for lowering vector shuffles on x86. It is
6561 // designed to handle arbitrary vector shuffles and blends, gracefully
6562 // degrading performance as necessary. It works hard to recognize idiomatic
6563 // shuffles and lower them to optimal instruction patterns without leaving
6564 // a framework that allows reasonably efficient handling of all vector shuffle
6566 //===----------------------------------------------------------------------===//
6568 /// \brief Tiny helper function to identify a no-op mask.
6570 /// This is a somewhat boring predicate function. It checks whether the mask
6571 /// array input, which is assumed to be a single-input shuffle mask of the kind
6572 /// used by the X86 shuffle instructions (not a fully general
6573 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6574 /// in-place shuffle are 'no-op's.
6575 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6576 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6577 if (Mask[i] != -1 && Mask[i] != i)
6582 /// \brief Helper function to classify a mask as a single-input mask.
6584 /// This isn't a generic single-input test because in the vector shuffle
6585 /// lowering we canonicalize single inputs to be the first input operand. This
6586 /// means we can more quickly test for a single input by only checking whether
6587 /// an input from the second operand exists. We also assume that the size of
6588 /// mask corresponds to the size of the input vectors which isn't true in the
6589 /// fully general case.
6590 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6592 if (M >= (int)Mask.size())
6597 /// \brief Test whether there are elements crossing 128-bit lanes in this
6600 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6601 /// and we routinely test for these.
6602 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6603 int LaneSize = 128 / VT.getScalarSizeInBits();
6604 int Size = Mask.size();
6605 for (int i = 0; i < Size; ++i)
6606 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6611 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6613 /// This checks a shuffle mask to see if it is performing the same
6614 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6615 /// that it is also not lane-crossing. It may however involve a blend from the
6616 /// same lane of a second vector.
6618 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6619 /// non-trivial to compute in the face of undef lanes. The representation is
6620 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6621 /// entries from both V1 and V2 inputs to the wider mask.
6623 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6624 SmallVectorImpl<int> &RepeatedMask) {
6625 int LaneSize = 128 / VT.getScalarSizeInBits();
6626 RepeatedMask.resize(LaneSize, -1);
6627 int Size = Mask.size();
6628 for (int i = 0; i < Size; ++i) {
6631 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6632 // This entry crosses lanes, so there is no way to model this shuffle.
6635 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6636 if (RepeatedMask[i % LaneSize] == -1)
6637 // This is the first non-undef entry in this slot of a 128-bit lane.
6638 RepeatedMask[i % LaneSize] =
6639 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6640 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6641 // Found a mismatch with the repeated mask.
6647 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6650 /// This is a fast way to test a shuffle mask against a fixed pattern:
6652 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6654 /// It returns true if the mask is exactly as wide as the argument list, and
6655 /// each element of the mask is either -1 (signifying undef) or the value given
6656 /// in the argument.
6657 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6658 ArrayRef<int> ExpectedMask) {
6659 if (Mask.size() != ExpectedMask.size())
6662 int Size = Mask.size();
6664 // If the values are build vectors, we can look through them to find
6665 // equivalent inputs that make the shuffles equivalent.
6666 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6667 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6669 for (int i = 0; i < Size; ++i)
6670 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6671 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6672 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6673 if (!MaskBV || !ExpectedBV ||
6674 MaskBV->getOperand(Mask[i] % Size) !=
6675 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6682 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6684 /// This helper function produces an 8-bit shuffle immediate corresponding to
6685 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6686 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6689 /// NB: We rely heavily on "undef" masks preserving the input lane.
6690 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6691 SelectionDAG &DAG) {
6692 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6693 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6694 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6695 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6696 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6699 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6700 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6701 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6702 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6703 return DAG.getConstant(Imm, DL, MVT::i8);
6706 /// \brief Compute whether each element of a shuffle is zeroable.
6708 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6709 /// Either it is an undef element in the shuffle mask, the element of the input
6710 /// referenced is undef, or the element of the input referenced is known to be
6711 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6712 /// as many lanes with this technique as possible to simplify the remaining
6714 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6715 SDValue V1, SDValue V2) {
6716 SmallBitVector Zeroable(Mask.size(), false);
6718 while (V1.getOpcode() == ISD::BITCAST)
6719 V1 = V1->getOperand(0);
6720 while (V2.getOpcode() == ISD::BITCAST)
6721 V2 = V2->getOperand(0);
6723 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6724 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6726 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6728 // Handle the easy cases.
6729 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6734 // If this is an index into a build_vector node (which has the same number
6735 // of elements), dig out the input value and use it.
6736 SDValue V = M < Size ? V1 : V2;
6737 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6740 SDValue Input = V.getOperand(M % Size);
6741 // The UNDEF opcode check really should be dead code here, but not quite
6742 // worth asserting on (it isn't invalid, just unexpected).
6743 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6750 // X86 has dedicated unpack instructions that can handle specific blend
6751 // operations: UNPCKH and UNPCKL.
6752 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6753 SDValue V1, SDValue V2,
6754 SelectionDAG &DAG) {
6755 int NumElts = VT.getVectorNumElements();
6756 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6757 SmallVector<int, 8> Unpckl;
6758 SmallVector<int, 8> Unpckh;
6760 for (int i = 0; i < NumElts; ++i) {
6761 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6762 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6763 int HiPos = LoPos + NumEltsInLane / 2;
6764 Unpckl.push_back(LoPos);
6765 Unpckh.push_back(HiPos);
6768 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6769 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6770 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6771 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6773 // Commute and try again.
6774 ShuffleVectorSDNode::commuteMask(Unpckl);
6775 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6776 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6778 ShuffleVectorSDNode::commuteMask(Unpckh);
6779 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6780 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6785 /// \brief Try to emit a bitmask instruction for a shuffle.
6787 /// This handles cases where we can model a blend exactly as a bitmask due to
6788 /// one of the inputs being zeroable.
6789 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6790 SDValue V2, ArrayRef<int> Mask,
6791 SelectionDAG &DAG) {
6792 MVT EltVT = VT.getVectorElementType();
6793 int NumEltBits = EltVT.getSizeInBits();
6794 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6795 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6796 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6798 if (EltVT.isFloatingPoint()) {
6799 Zero = DAG.getBitcast(EltVT, Zero);
6800 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6802 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6803 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6805 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6808 if (Mask[i] % Size != i)
6809 return SDValue(); // Not a blend.
6811 V = Mask[i] < Size ? V1 : V2;
6812 else if (V != (Mask[i] < Size ? V1 : V2))
6813 return SDValue(); // Can only let one input through the mask.
6815 VMaskOps[i] = AllOnes;
6818 return SDValue(); // No non-zeroable elements!
6820 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6821 V = DAG.getNode(VT.isFloatingPoint()
6822 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6827 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6829 /// This is used as a fallback approach when first class blend instructions are
6830 /// unavailable. Currently it is only suitable for integer vectors, but could
6831 /// be generalized for floating point vectors if desirable.
6832 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6833 SDValue V2, ArrayRef<int> Mask,
6834 SelectionDAG &DAG) {
6835 assert(VT.isInteger() && "Only supports integer vector types!");
6836 MVT EltVT = VT.getVectorElementType();
6837 int NumEltBits = EltVT.getSizeInBits();
6838 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6839 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6841 SmallVector<SDValue, 16> MaskOps;
6842 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6843 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6844 return SDValue(); // Shuffled input!
6845 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6848 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6849 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6850 // We have to cast V2 around.
6851 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6852 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6853 DAG.getBitcast(MaskVT, V1Mask),
6854 DAG.getBitcast(MaskVT, V2)));
6855 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6858 /// \brief Try to emit a blend instruction for a shuffle.
6860 /// This doesn't do any checks for the availability of instructions for blending
6861 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6862 /// be matched in the backend with the type given. What it does check for is
6863 /// that the shuffle mask is a blend, or convertible into a blend with zero.
6864 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6865 SDValue V2, ArrayRef<int> Original,
6866 const X86Subtarget *Subtarget,
6867 SelectionDAG &DAG) {
6868 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6869 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6870 SmallVector<int, 8> Mask(Original.begin(), Original.end());
6871 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6872 bool ForceV1Zero = false, ForceV2Zero = false;
6874 // Attempt to generate the binary blend mask. If an input is zero then
6875 // we can use any lane.
6876 // TODO: generalize the zero matching to any scalar like isShuffleEquivalent.
6877 unsigned BlendMask = 0;
6878 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6884 if (M == i + Size) {
6885 BlendMask |= 1u << i;
6896 BlendMask |= 1u << i;
6901 return SDValue(); // Shuffled input!
6904 // Create a REAL zero vector - ISD::isBuildVectorAllZeros allows UNDEFs.
6906 V1 = getZeroVector(VT, Subtarget, DAG, DL);
6908 V2 = getZeroVector(VT, Subtarget, DAG, DL);
6910 auto ScaleBlendMask = [](unsigned BlendMask, int Size, int Scale) {
6911 unsigned ScaledMask = 0;
6912 for (int i = 0; i != Size; ++i)
6913 if (BlendMask & (1u << i))
6914 for (int j = 0; j != Scale; ++j)
6915 ScaledMask |= 1u << (i * Scale + j);
6919 switch (VT.SimpleTy) {
6924 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6925 DAG.getConstant(BlendMask, DL, MVT::i8));
6929 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6933 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6934 // that instruction.
6935 if (Subtarget->hasAVX2()) {
6936 // Scale the blend by the number of 32-bit dwords per element.
6937 int Scale = VT.getScalarSizeInBits() / 32;
6938 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
6939 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6940 V1 = DAG.getBitcast(BlendVT, V1);
6941 V2 = DAG.getBitcast(BlendVT, V2);
6942 return DAG.getBitcast(
6943 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6944 DAG.getConstant(BlendMask, DL, MVT::i8)));
6948 // For integer shuffles we need to expand the mask and cast the inputs to
6949 // v8i16s prior to blending.
6950 int Scale = 8 / VT.getVectorNumElements();
6951 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
6952 V1 = DAG.getBitcast(MVT::v8i16, V1);
6953 V2 = DAG.getBitcast(MVT::v8i16, V2);
6954 return DAG.getBitcast(VT,
6955 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6956 DAG.getConstant(BlendMask, DL, MVT::i8)));
6960 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6961 SmallVector<int, 8> RepeatedMask;
6962 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6963 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6964 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6966 for (int i = 0; i < 8; ++i)
6967 if (RepeatedMask[i] >= 16)
6968 BlendMask |= 1u << i;
6969 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6970 DAG.getConstant(BlendMask, DL, MVT::i8));
6976 assert((VT.is128BitVector() || Subtarget->hasAVX2()) &&
6977 "256-bit byte-blends require AVX2 support!");
6979 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6980 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6983 // Scale the blend by the number of bytes per element.
6984 int Scale = VT.getScalarSizeInBits() / 8;
6986 // This form of blend is always done on bytes. Compute the byte vector
6988 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6990 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6991 // mix of LLVM's code generator and the x86 backend. We tell the code
6992 // generator that boolean values in the elements of an x86 vector register
6993 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6994 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6995 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6996 // of the element (the remaining are ignored) and 0 in that high bit would
6997 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6998 // the LLVM model for boolean values in vector elements gets the relevant
6999 // bit set, it is set backwards and over constrained relative to x86's
7001 SmallVector<SDValue, 32> VSELECTMask;
7002 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7003 for (int j = 0; j < Scale; ++j)
7004 VSELECTMask.push_back(
7005 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7006 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
7009 V1 = DAG.getBitcast(BlendVT, V1);
7010 V2 = DAG.getBitcast(BlendVT, V2);
7011 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
7012 DAG.getNode(ISD::BUILD_VECTOR, DL,
7013 BlendVT, VSELECTMask),
7018 llvm_unreachable("Not a supported integer vector type!");
7022 /// \brief Try to lower as a blend of elements from two inputs followed by
7023 /// a single-input permutation.
7025 /// This matches the pattern where we can blend elements from two inputs and
7026 /// then reduce the shuffle to a single-input permutation.
7027 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7030 SelectionDAG &DAG) {
7031 // We build up the blend mask while checking whether a blend is a viable way
7032 // to reduce the shuffle.
7033 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7034 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7036 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7040 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7042 if (BlendMask[Mask[i] % Size] == -1)
7043 BlendMask[Mask[i] % Size] = Mask[i];
7044 else if (BlendMask[Mask[i] % Size] != Mask[i])
7045 return SDValue(); // Can't blend in the needed input!
7047 PermuteMask[i] = Mask[i] % Size;
7050 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7051 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7054 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7055 /// blends and permutes.
7057 /// This matches the extremely common pattern for handling combined
7058 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7059 /// operations. It will try to pick the best arrangement of shuffles and
7061 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7065 SelectionDAG &DAG) {
7066 // Shuffle the input elements into the desired positions in V1 and V2 and
7067 // blend them together.
7068 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7069 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7070 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7071 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7072 if (Mask[i] >= 0 && Mask[i] < Size) {
7073 V1Mask[i] = Mask[i];
7075 } else if (Mask[i] >= Size) {
7076 V2Mask[i] = Mask[i] - Size;
7077 BlendMask[i] = i + Size;
7080 // Try to lower with the simpler initial blend strategy unless one of the
7081 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7082 // shuffle may be able to fold with a load or other benefit. However, when
7083 // we'll have to do 2x as many shuffles in order to achieve this, blending
7084 // first is a better strategy.
7085 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7086 if (SDValue BlendPerm =
7087 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7090 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7091 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7092 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7095 /// \brief Try to lower a vector shuffle as a byte rotation.
7097 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7098 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7099 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7100 /// try to generically lower a vector shuffle through such an pattern. It
7101 /// does not check for the profitability of lowering either as PALIGNR or
7102 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7103 /// This matches shuffle vectors that look like:
7105 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7107 /// Essentially it concatenates V1 and V2, shifts right by some number of
7108 /// elements, and takes the low elements as the result. Note that while this is
7109 /// specified as a *right shift* because x86 is little-endian, it is a *left
7110 /// rotate* of the vector lanes.
7111 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7114 const X86Subtarget *Subtarget,
7115 SelectionDAG &DAG) {
7116 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7118 int NumElts = Mask.size();
7119 int NumLanes = VT.getSizeInBits() / 128;
7120 int NumLaneElts = NumElts / NumLanes;
7122 // We need to detect various ways of spelling a rotation:
7123 // [11, 12, 13, 14, 15, 0, 1, 2]
7124 // [-1, 12, 13, 14, -1, -1, 1, -1]
7125 // [-1, -1, -1, -1, -1, -1, 1, 2]
7126 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7127 // [-1, 4, 5, 6, -1, -1, 9, -1]
7128 // [-1, 4, 5, 6, -1, -1, -1, -1]
7131 for (int l = 0; l < NumElts; l += NumLaneElts) {
7132 for (int i = 0; i < NumLaneElts; ++i) {
7133 if (Mask[l + i] == -1)
7135 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7137 // Get the mod-Size index and lane correct it.
7138 int LaneIdx = (Mask[l + i] % NumElts) - l;
7139 // Make sure it was in this lane.
7140 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7143 // Determine where a rotated vector would have started.
7144 int StartIdx = i - LaneIdx;
7146 // The identity rotation isn't interesting, stop.
7149 // If we found the tail of a vector the rotation must be the missing
7150 // front. If we found the head of a vector, it must be how much of the
7152 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7155 Rotation = CandidateRotation;
7156 else if (Rotation != CandidateRotation)
7157 // The rotations don't match, so we can't match this mask.
7160 // Compute which value this mask is pointing at.
7161 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7163 // Compute which of the two target values this index should be assigned
7164 // to. This reflects whether the high elements are remaining or the low
7165 // elements are remaining.
7166 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7168 // Either set up this value if we've not encountered it before, or check
7169 // that it remains consistent.
7172 else if (TargetV != MaskV)
7173 // This may be a rotation, but it pulls from the inputs in some
7174 // unsupported interleaving.
7179 // Check that we successfully analyzed the mask, and normalize the results.
7180 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7181 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7187 // The actual rotate instruction rotates bytes, so we need to scale the
7188 // rotation based on how many bytes are in the vector lane.
7189 int Scale = 16 / NumLaneElts;
7191 // SSSE3 targets can use the palignr instruction.
7192 if (Subtarget->hasSSSE3()) {
7193 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7194 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7195 Lo = DAG.getBitcast(AlignVT, Lo);
7196 Hi = DAG.getBitcast(AlignVT, Hi);
7198 return DAG.getBitcast(
7199 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7200 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7203 assert(VT.is128BitVector() &&
7204 "Rotate-based lowering only supports 128-bit lowering!");
7205 assert(Mask.size() <= 16 &&
7206 "Can shuffle at most 16 bytes in a 128-bit vector!");
7208 // Default SSE2 implementation
7209 int LoByteShift = 16 - Rotation * Scale;
7210 int HiByteShift = Rotation * Scale;
7212 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7213 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7214 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7216 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7217 DAG.getConstant(LoByteShift, DL, MVT::i8));
7218 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7219 DAG.getConstant(HiByteShift, DL, MVT::i8));
7220 return DAG.getBitcast(VT,
7221 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7224 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7226 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7227 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7228 /// matches elements from one of the input vectors shuffled to the left or
7229 /// right with zeroable elements 'shifted in'. It handles both the strictly
7230 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7233 /// PSHL : (little-endian) left bit shift.
7234 /// [ zz, 0, zz, 2 ]
7235 /// [ -1, 4, zz, -1 ]
7236 /// PSRL : (little-endian) right bit shift.
7238 /// [ -1, -1, 7, zz]
7239 /// PSLLDQ : (little-endian) left byte shift
7240 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7241 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7242 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7243 /// PSRLDQ : (little-endian) right byte shift
7244 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7245 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7246 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7247 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7248 SDValue V2, ArrayRef<int> Mask,
7249 SelectionDAG &DAG) {
7250 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7252 int Size = Mask.size();
7253 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7255 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7256 for (int i = 0; i < Size; i += Scale)
7257 for (int j = 0; j < Shift; ++j)
7258 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7264 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7265 for (int i = 0; i != Size; i += Scale) {
7266 unsigned Pos = Left ? i + Shift : i;
7267 unsigned Low = Left ? i : i + Shift;
7268 unsigned Len = Scale - Shift;
7269 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7270 Low + (V == V1 ? 0 : Size)))
7274 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7275 bool ByteShift = ShiftEltBits > 64;
7276 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7277 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7278 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7280 // Normalize the scale for byte shifts to still produce an i64 element
7282 Scale = ByteShift ? Scale / 2 : Scale;
7284 // We need to round trip through the appropriate type for the shift.
7285 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7286 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7287 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7288 "Illegal integer vector type");
7289 V = DAG.getBitcast(ShiftVT, V);
7291 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7292 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7293 return DAG.getBitcast(VT, V);
7296 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7297 // keep doubling the size of the integer elements up to that. We can
7298 // then shift the elements of the integer vector by whole multiples of
7299 // their width within the elements of the larger integer vector. Test each
7300 // multiple to see if we can find a match with the moved element indices
7301 // and that the shifted in elements are all zeroable.
7302 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7303 for (int Shift = 1; Shift != Scale; ++Shift)
7304 for (bool Left : {true, false})
7305 if (CheckZeros(Shift, Scale, Left))
7306 for (SDValue V : {V1, V2})
7307 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7314 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7315 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7316 SDValue V2, ArrayRef<int> Mask,
7317 SelectionDAG &DAG) {
7318 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7319 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7321 int Size = Mask.size();
7322 int HalfSize = Size / 2;
7323 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7325 // Upper half must be undefined.
7326 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7329 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7330 // Remainder of lower half result is zero and upper half is all undef.
7331 auto LowerAsEXTRQ = [&]() {
7332 // Determine the extraction length from the part of the
7333 // lower half that isn't zeroable.
7335 for (; Len > 0; --Len)
7336 if (!Zeroable[Len - 1])
7338 assert(Len > 0 && "Zeroable shuffle mask");
7340 // Attempt to match first Len sequential elements from the lower half.
7343 for (int i = 0; i != Len; ++i) {
7347 SDValue &V = (M < Size ? V1 : V2);
7350 // All mask elements must be in the lower half.
7354 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7365 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7366 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7367 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7368 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7369 DAG.getConstant(BitLen, DL, MVT::i8),
7370 DAG.getConstant(BitIdx, DL, MVT::i8));
7373 if (SDValue ExtrQ = LowerAsEXTRQ())
7376 // INSERTQ: Extract lowest Len elements from lower half of second source and
7377 // insert over first source, starting at Idx.
7378 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7379 auto LowerAsInsertQ = [&]() {
7380 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7383 // Attempt to match first source from mask before insertion point.
7384 if (isUndefInRange(Mask, 0, Idx)) {
7386 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7388 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7394 // Extend the extraction length looking to match both the insertion of
7395 // the second source and the remaining elements of the first.
7396 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7401 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7403 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7409 // Match the remaining elements of the lower half.
7410 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7412 } else if ((!Base || (Base == V1)) &&
7413 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7415 } else if ((!Base || (Base == V2)) &&
7416 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7423 // We may not have a base (first source) - this can safely be undefined.
7425 Base = DAG.getUNDEF(VT);
7427 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7428 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7429 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7430 DAG.getConstant(BitLen, DL, MVT::i8),
7431 DAG.getConstant(BitIdx, DL, MVT::i8));
7438 if (SDValue InsertQ = LowerAsInsertQ())
7444 /// \brief Lower a vector shuffle as a zero or any extension.
7446 /// Given a specific number of elements, element bit width, and extension
7447 /// stride, produce either a zero or any extension based on the available
7448 /// features of the subtarget. The extended elements are consecutive and
7449 /// begin and can start from an offseted element index in the input; to
7450 /// avoid excess shuffling the offset must either being in the bottom lane
7451 /// or at the start of a higher lane. All extended elements must be from
7453 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7454 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7455 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7456 assert(Scale > 1 && "Need a scale to extend.");
7457 int EltBits = VT.getScalarSizeInBits();
7458 int NumElements = VT.getVectorNumElements();
7459 int NumEltsPerLane = 128 / EltBits;
7460 int OffsetLane = Offset / NumEltsPerLane;
7461 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7462 "Only 8, 16, and 32 bit elements can be extended.");
7463 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7464 assert(0 <= Offset && "Extension offset must be positive.");
7465 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7466 "Extension offset must be in the first lane or start an upper lane.");
7468 // Check that an index is in same lane as the base offset.
7469 auto SafeOffset = [&](int Idx) {
7470 return OffsetLane == (Idx / NumEltsPerLane);
7473 // Shift along an input so that the offset base moves to the first element.
7474 auto ShuffleOffset = [&](SDValue V) {
7478 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7479 for (int i = 0; i * Scale < NumElements; ++i) {
7480 int SrcIdx = i + Offset;
7481 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7483 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7486 // Found a valid zext mask! Try various lowering strategies based on the
7487 // input type and available ISA extensions.
7488 if (Subtarget->hasSSE41()) {
7489 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7490 // PUNPCK will catch this in a later shuffle match.
7491 if (Offset && Scale == 2 && VT.is128BitVector())
7493 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7494 NumElements / Scale);
7495 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7496 return DAG.getBitcast(VT, InputV);
7499 assert(VT.is128BitVector() && "Only 128-bit vectors can be extended.");
7501 // For any extends we can cheat for larger element sizes and use shuffle
7502 // instructions that can fold with a load and/or copy.
7503 if (AnyExt && EltBits == 32) {
7504 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7506 return DAG.getBitcast(
7507 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7508 DAG.getBitcast(MVT::v4i32, InputV),
7509 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7511 if (AnyExt && EltBits == 16 && Scale > 2) {
7512 int PSHUFDMask[4] = {Offset / 2, -1,
7513 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7514 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7515 DAG.getBitcast(MVT::v4i32, InputV),
7516 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7517 int PSHUFWMask[4] = {1, -1, -1, -1};
7518 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7519 return DAG.getBitcast(
7520 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7521 DAG.getBitcast(MVT::v8i16, InputV),
7522 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7525 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7527 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7528 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7529 assert(VT.is128BitVector() && "Unexpected vector width!");
7531 int LoIdx = Offset * EltBits;
7532 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7533 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7534 DAG.getConstant(EltBits, DL, MVT::i8),
7535 DAG.getConstant(LoIdx, DL, MVT::i8)));
7537 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7538 !SafeOffset(Offset + 1))
7539 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7541 int HiIdx = (Offset + 1) * EltBits;
7542 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7543 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7544 DAG.getConstant(EltBits, DL, MVT::i8),
7545 DAG.getConstant(HiIdx, DL, MVT::i8)));
7546 return DAG.getNode(ISD::BITCAST, DL, VT,
7547 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7550 // If this would require more than 2 unpack instructions to expand, use
7551 // pshufb when available. We can only use more than 2 unpack instructions
7552 // when zero extending i8 elements which also makes it easier to use pshufb.
7553 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7554 assert(NumElements == 16 && "Unexpected byte vector width!");
7555 SDValue PSHUFBMask[16];
7556 for (int i = 0; i < 16; ++i) {
7557 int Idx = Offset + (i / Scale);
7558 PSHUFBMask[i] = DAG.getConstant(
7559 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7561 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7562 return DAG.getBitcast(VT,
7563 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7564 DAG.getNode(ISD::BUILD_VECTOR, DL,
7565 MVT::v16i8, PSHUFBMask)));
7568 // If we are extending from an offset, ensure we start on a boundary that
7569 // we can unpack from.
7570 int AlignToUnpack = Offset % (NumElements / Scale);
7571 if (AlignToUnpack) {
7572 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7573 for (int i = AlignToUnpack; i < NumElements; ++i)
7574 ShMask[i - AlignToUnpack] = i;
7575 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7576 Offset -= AlignToUnpack;
7579 // Otherwise emit a sequence of unpacks.
7581 unsigned UnpackLoHi = X86ISD::UNPCKL;
7582 if (Offset >= (NumElements / 2)) {
7583 UnpackLoHi = X86ISD::UNPCKH;
7584 Offset -= (NumElements / 2);
7587 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7588 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7589 : getZeroVector(InputVT, Subtarget, DAG, DL);
7590 InputV = DAG.getBitcast(InputVT, InputV);
7591 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7595 } while (Scale > 1);
7596 return DAG.getBitcast(VT, InputV);
7599 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7601 /// This routine will try to do everything in its power to cleverly lower
7602 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7603 /// check for the profitability of this lowering, it tries to aggressively
7604 /// match this pattern. It will use all of the micro-architectural details it
7605 /// can to emit an efficient lowering. It handles both blends with all-zero
7606 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7607 /// masking out later).
7609 /// The reason we have dedicated lowering for zext-style shuffles is that they
7610 /// are both incredibly common and often quite performance sensitive.
7611 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7612 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7613 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7614 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7616 int Bits = VT.getSizeInBits();
7617 int NumLanes = Bits / 128;
7618 int NumElements = VT.getVectorNumElements();
7619 int NumEltsPerLane = NumElements / NumLanes;
7620 assert(VT.getScalarSizeInBits() <= 32 &&
7621 "Exceeds 32-bit integer zero extension limit");
7622 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7624 // Define a helper function to check a particular ext-scale and lower to it if
7626 auto Lower = [&](int Scale) -> SDValue {
7631 for (int i = 0; i < NumElements; ++i) {
7634 continue; // Valid anywhere but doesn't tell us anything.
7635 if (i % Scale != 0) {
7636 // Each of the extended elements need to be zeroable.
7640 // We no longer are in the anyext case.
7645 // Each of the base elements needs to be consecutive indices into the
7646 // same input vector.
7647 SDValue V = M < NumElements ? V1 : V2;
7648 M = M % NumElements;
7651 Offset = M - (i / Scale);
7652 } else if (InputV != V)
7653 return SDValue(); // Flip-flopping inputs.
7655 // Offset must start in the lowest 128-bit lane or at the start of an
7657 // FIXME: Is it ever worth allowing a negative base offset?
7658 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7659 (Offset % NumEltsPerLane) == 0))
7662 // If we are offsetting, all referenced entries must come from the same
7664 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7667 if ((M % NumElements) != (Offset + (i / Scale)))
7668 return SDValue(); // Non-consecutive strided elements.
7672 // If we fail to find an input, we have a zero-shuffle which should always
7673 // have already been handled.
7674 // FIXME: Maybe handle this here in case during blending we end up with one?
7678 // If we are offsetting, don't extend if we only match a single input, we
7679 // can always do better by using a basic PSHUF or PUNPCK.
7680 if (Offset != 0 && Matches < 2)
7683 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7684 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7687 // The widest scale possible for extending is to a 64-bit integer.
7688 assert(Bits % 64 == 0 &&
7689 "The number of bits in a vector must be divisible by 64 on x86!");
7690 int NumExtElements = Bits / 64;
7692 // Each iteration, try extending the elements half as much, but into twice as
7694 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7695 assert(NumElements % NumExtElements == 0 &&
7696 "The input vector size must be divisible by the extended size.");
7697 if (SDValue V = Lower(NumElements / NumExtElements))
7701 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7705 // Returns one of the source operands if the shuffle can be reduced to a
7706 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7707 auto CanZExtLowHalf = [&]() {
7708 for (int i = NumElements / 2; i != NumElements; ++i)
7711 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7713 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7718 if (SDValue V = CanZExtLowHalf()) {
7719 V = DAG.getBitcast(MVT::v2i64, V);
7720 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7721 return DAG.getBitcast(VT, V);
7724 // No viable ext lowering found.
7728 /// \brief Try to get a scalar value for a specific element of a vector.
7730 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7731 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7732 SelectionDAG &DAG) {
7733 MVT VT = V.getSimpleValueType();
7734 MVT EltVT = VT.getVectorElementType();
7735 while (V.getOpcode() == ISD::BITCAST)
7736 V = V.getOperand(0);
7737 // If the bitcasts shift the element size, we can't extract an equivalent
7739 MVT NewVT = V.getSimpleValueType();
7740 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7743 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7744 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7745 // Ensure the scalar operand is the same size as the destination.
7746 // FIXME: Add support for scalar truncation where possible.
7747 SDValue S = V.getOperand(Idx);
7748 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7749 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7755 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7757 /// This is particularly important because the set of instructions varies
7758 /// significantly based on whether the operand is a load or not.
7759 static bool isShuffleFoldableLoad(SDValue V) {
7760 while (V.getOpcode() == ISD::BITCAST)
7761 V = V.getOperand(0);
7763 return ISD::isNON_EXTLoad(V.getNode());
7766 /// \brief Try to lower insertion of a single element into a zero vector.
7768 /// This is a common pattern that we have especially efficient patterns to lower
7769 /// across all subtarget feature sets.
7770 static SDValue lowerVectorShuffleAsElementInsertion(
7771 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7772 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7773 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7775 MVT EltVT = VT.getVectorElementType();
7777 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7778 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7780 bool IsV1Zeroable = true;
7781 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7782 if (i != V2Index && !Zeroable[i]) {
7783 IsV1Zeroable = false;
7787 // Check for a single input from a SCALAR_TO_VECTOR node.
7788 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7789 // all the smarts here sunk into that routine. However, the current
7790 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7791 // vector shuffle lowering is dead.
7792 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7794 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7795 // We need to zext the scalar if it is smaller than an i32.
7796 V2S = DAG.getBitcast(EltVT, V2S);
7797 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7798 // Using zext to expand a narrow element won't work for non-zero
7803 // Zero-extend directly to i32.
7805 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7807 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7808 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7809 EltVT == MVT::i16) {
7810 // Either not inserting from the low element of the input or the input
7811 // element size is too small to use VZEXT_MOVL to clear the high bits.
7815 if (!IsV1Zeroable) {
7816 // If V1 can't be treated as a zero vector we have fewer options to lower
7817 // this. We can't support integer vectors or non-zero targets cheaply, and
7818 // the V1 elements can't be permuted in any way.
7819 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7820 if (!VT.isFloatingPoint() || V2Index != 0)
7822 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7823 V1Mask[V2Index] = -1;
7824 if (!isNoopShuffleMask(V1Mask))
7826 // This is essentially a special case blend operation, but if we have
7827 // general purpose blend operations, they are always faster. Bail and let
7828 // the rest of the lowering handle these as blends.
7829 if (Subtarget->hasSSE41())
7832 // Otherwise, use MOVSD or MOVSS.
7833 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7834 "Only two types of floating point element types to handle!");
7835 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7839 // This lowering only works for the low element with floating point vectors.
7840 if (VT.isFloatingPoint() && V2Index != 0)
7843 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7845 V2 = DAG.getBitcast(VT, V2);
7848 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7849 // the desired position. Otherwise it is more efficient to do a vector
7850 // shift left. We know that we can do a vector shift left because all
7851 // the inputs are zero.
7852 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7853 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7854 V2Shuffle[V2Index] = 0;
7855 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7857 V2 = DAG.getBitcast(MVT::v2i64, V2);
7859 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7860 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7861 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7862 DAG.getDataLayout(), VT)));
7863 V2 = DAG.getBitcast(VT, V2);
7869 /// \brief Try to lower broadcast of a single element.
7871 /// For convenience, this code also bundles all of the subtarget feature set
7872 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7873 /// a convenient way to factor it out.
7874 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7876 const X86Subtarget *Subtarget,
7877 SelectionDAG &DAG) {
7878 if (!Subtarget->hasAVX())
7880 if (VT.isInteger() && !Subtarget->hasAVX2())
7883 // Check that the mask is a broadcast.
7884 int BroadcastIdx = -1;
7886 if (M >= 0 && BroadcastIdx == -1)
7888 else if (M >= 0 && M != BroadcastIdx)
7891 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7892 "a sorted mask where the broadcast "
7895 // Go up the chain of (vector) values to find a scalar load that we can
7896 // combine with the broadcast.
7898 switch (V.getOpcode()) {
7899 case ISD::CONCAT_VECTORS: {
7900 int OperandSize = Mask.size() / V.getNumOperands();
7901 V = V.getOperand(BroadcastIdx / OperandSize);
7902 BroadcastIdx %= OperandSize;
7906 case ISD::INSERT_SUBVECTOR: {
7907 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7908 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7912 int BeginIdx = (int)ConstantIdx->getZExtValue();
7914 BeginIdx + (int)VInner.getSimpleValueType().getVectorNumElements();
7915 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7916 BroadcastIdx -= BeginIdx;
7927 // Check if this is a broadcast of a scalar. We special case lowering
7928 // for scalars so that we can more effectively fold with loads.
7929 // First, look through bitcast: if the original value has a larger element
7930 // type than the shuffle, the broadcast element is in essence truncated.
7931 // Make that explicit to ease folding.
7932 if (V.getOpcode() == ISD::BITCAST && VT.isInteger()) {
7933 MVT EltVT = VT.getVectorElementType();
7934 SDValue V0 = V.getOperand(0);
7935 MVT V0VT = V0.getSimpleValueType();
7937 if (V0VT.isInteger() && V0VT.getVectorElementType().bitsGT(EltVT) &&
7938 ((V0.getOpcode() == ISD::BUILD_VECTOR ||
7939 (V0.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)))) {
7940 V = DAG.getNode(ISD::TRUNCATE, DL, EltVT, V0.getOperand(BroadcastIdx));
7945 // Also check the simpler case, where we can directly reuse the scalar.
7946 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7947 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7948 V = V.getOperand(BroadcastIdx);
7950 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7951 // Only AVX2 has register broadcasts.
7952 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7954 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7955 // We can't broadcast from a vector register without AVX2, and we can only
7956 // broadcast from the zero-element of a vector register.
7960 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7963 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7964 // INSERTPS when the V1 elements are already in the correct locations
7965 // because otherwise we can just always use two SHUFPS instructions which
7966 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7967 // perform INSERTPS if a single V1 element is out of place and all V2
7968 // elements are zeroable.
7969 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7971 SelectionDAG &DAG) {
7972 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7973 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7974 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7975 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7977 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7980 int V1DstIndex = -1;
7981 int V2DstIndex = -1;
7982 bool V1UsedInPlace = false;
7984 for (int i = 0; i < 4; ++i) {
7985 // Synthesize a zero mask from the zeroable elements (includes undefs).
7991 // Flag if we use any V1 inputs in place.
7993 V1UsedInPlace = true;
7997 // We can only insert a single non-zeroable element.
7998 if (V1DstIndex != -1 || V2DstIndex != -1)
8002 // V1 input out of place for insertion.
8005 // V2 input for insertion.
8010 // Don't bother if we have no (non-zeroable) element for insertion.
8011 if (V1DstIndex == -1 && V2DstIndex == -1)
8014 // Determine element insertion src/dst indices. The src index is from the
8015 // start of the inserted vector, not the start of the concatenated vector.
8016 unsigned V2SrcIndex = 0;
8017 if (V1DstIndex != -1) {
8018 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8019 // and don't use the original V2 at all.
8020 V2SrcIndex = Mask[V1DstIndex];
8021 V2DstIndex = V1DstIndex;
8024 V2SrcIndex = Mask[V2DstIndex] - 4;
8027 // If no V1 inputs are used in place, then the result is created only from
8028 // the zero mask and the V2 insertion - so remove V1 dependency.
8030 V1 = DAG.getUNDEF(MVT::v4f32);
8032 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8033 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8035 // Insert the V2 element into the desired position.
8037 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8038 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8041 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8042 /// UNPCK instruction.
8044 /// This specifically targets cases where we end up with alternating between
8045 /// the two inputs, and so can permute them into something that feeds a single
8046 /// UNPCK instruction. Note that this routine only targets integer vectors
8047 /// because for floating point vectors we have a generalized SHUFPS lowering
8048 /// strategy that handles everything that doesn't *exactly* match an unpack,
8049 /// making this clever lowering unnecessary.
8050 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8051 SDValue V1, SDValue V2,
8053 SelectionDAG &DAG) {
8054 assert(!VT.isFloatingPoint() &&
8055 "This routine only supports integer vectors.");
8056 assert(!isSingleInputShuffleMask(Mask) &&
8057 "This routine should only be used when blending two inputs.");
8058 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8060 int Size = Mask.size();
8062 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8063 return M >= 0 && M % Size < Size / 2;
8065 int NumHiInputs = std::count_if(
8066 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8068 bool UnpackLo = NumLoInputs >= NumHiInputs;
8070 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8071 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8072 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8074 for (int i = 0; i < Size; ++i) {
8078 // Each element of the unpack contains Scale elements from this mask.
8079 int UnpackIdx = i / Scale;
8081 // We only handle the case where V1 feeds the first slots of the unpack.
8082 // We rely on canonicalization to ensure this is the case.
8083 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8086 // Setup the mask for this input. The indexing is tricky as we have to
8087 // handle the unpack stride.
8088 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8089 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8093 // If we will have to shuffle both inputs to use the unpack, check whether
8094 // we can just unpack first and shuffle the result. If so, skip this unpack.
8095 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8096 !isNoopShuffleMask(V2Mask))
8099 // Shuffle the inputs into place.
8100 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8101 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8103 // Cast the inputs to the type we will use to unpack them.
8104 V1 = DAG.getBitcast(UnpackVT, V1);
8105 V2 = DAG.getBitcast(UnpackVT, V2);
8107 // Unpack the inputs and cast the result back to the desired type.
8108 return DAG.getBitcast(
8109 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8113 // We try each unpack from the largest to the smallest to try and find one
8114 // that fits this mask.
8115 int OrigNumElements = VT.getVectorNumElements();
8116 int OrigScalarSize = VT.getScalarSizeInBits();
8117 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8118 int Scale = ScalarSize / OrigScalarSize;
8119 int NumElements = OrigNumElements / Scale;
8120 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8121 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8125 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8127 if (NumLoInputs == 0 || NumHiInputs == 0) {
8128 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8129 "We have to have *some* inputs!");
8130 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8132 // FIXME: We could consider the total complexity of the permute of each
8133 // possible unpacking. Or at the least we should consider how many
8134 // half-crossings are created.
8135 // FIXME: We could consider commuting the unpacks.
8137 SmallVector<int, 32> PermMask;
8138 PermMask.assign(Size, -1);
8139 for (int i = 0; i < Size; ++i) {
8143 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8146 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8148 return DAG.getVectorShuffle(
8149 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8151 DAG.getUNDEF(VT), PermMask);
8157 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8159 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8160 /// support for floating point shuffles but not integer shuffles. These
8161 /// instructions will incur a domain crossing penalty on some chips though so
8162 /// it is better to avoid lowering through this for integer vectors where
8164 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8165 const X86Subtarget *Subtarget,
8166 SelectionDAG &DAG) {
8168 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8169 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8170 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8171 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8172 ArrayRef<int> Mask = SVOp->getMask();
8173 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8175 if (isSingleInputShuffleMask(Mask)) {
8176 // Use low duplicate instructions for masks that match their pattern.
8177 if (Subtarget->hasSSE3())
8178 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8179 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8181 // Straight shuffle of a single input vector. Simulate this by using the
8182 // single input as both of the "inputs" to this instruction..
8183 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8185 if (Subtarget->hasAVX()) {
8186 // If we have AVX, we can use VPERMILPS which will allow folding a load
8187 // into the shuffle.
8188 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8189 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8192 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8193 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8195 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8196 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8198 // If we have a single input, insert that into V1 if we can do so cheaply.
8199 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8200 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8201 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8203 // Try inverting the insertion since for v2 masks it is easy to do and we
8204 // can't reliably sort the mask one way or the other.
8205 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8206 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8207 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8208 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8212 // Try to use one of the special instruction patterns to handle two common
8213 // blend patterns if a zero-blend above didn't work.
8214 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8215 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8216 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8217 // We can either use a special instruction to load over the low double or
8218 // to move just the low double.
8220 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8222 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8224 if (Subtarget->hasSSE41())
8225 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8229 // Use dedicated unpack instructions for masks that match their pattern.
8231 lowerVectorShuffleWithUNPCK(DL, MVT::v2f64, Mask, V1, V2, DAG))
8234 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8235 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8236 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8239 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8241 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8242 /// the integer unit to minimize domain crossing penalties. However, for blends
8243 /// it falls back to the floating point shuffle operation with appropriate bit
8245 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8246 const X86Subtarget *Subtarget,
8247 SelectionDAG &DAG) {
8249 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8250 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8251 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8252 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8253 ArrayRef<int> Mask = SVOp->getMask();
8254 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8256 if (isSingleInputShuffleMask(Mask)) {
8257 // Check for being able to broadcast a single element.
8258 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8259 Mask, Subtarget, DAG))
8262 // Straight shuffle of a single input vector. For everything from SSE2
8263 // onward this has a single fast instruction with no scary immediates.
8264 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8265 V1 = DAG.getBitcast(MVT::v4i32, V1);
8266 int WidenedMask[4] = {
8267 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8268 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8269 return DAG.getBitcast(
8271 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8272 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8274 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8275 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8276 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8277 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8279 // If we have a blend of two PACKUS operations an the blend aligns with the
8280 // low and half halves, we can just merge the PACKUS operations. This is
8281 // particularly important as it lets us merge shuffles that this routine itself
8283 auto GetPackNode = [](SDValue V) {
8284 while (V.getOpcode() == ISD::BITCAST)
8285 V = V.getOperand(0);
8287 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8289 if (SDValue V1Pack = GetPackNode(V1))
8290 if (SDValue V2Pack = GetPackNode(V2))
8291 return DAG.getBitcast(MVT::v2i64,
8292 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8293 Mask[0] == 0 ? V1Pack.getOperand(0)
8294 : V1Pack.getOperand(1),
8295 Mask[1] == 2 ? V2Pack.getOperand(0)
8296 : V2Pack.getOperand(1)));
8298 // Try to use shift instructions.
8300 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8303 // When loading a scalar and then shuffling it into a vector we can often do
8304 // the insertion cheaply.
8305 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8306 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8308 // Try inverting the insertion since for v2 masks it is easy to do and we
8309 // can't reliably sort the mask one way or the other.
8310 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8311 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8312 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8315 // We have different paths for blend lowering, but they all must use the
8316 // *exact* same predicate.
8317 bool IsBlendSupported = Subtarget->hasSSE41();
8318 if (IsBlendSupported)
8319 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8323 // Use dedicated unpack instructions for masks that match their pattern.
8325 lowerVectorShuffleWithUNPCK(DL, MVT::v2i64, Mask, V1, V2, DAG))
8328 // Try to use byte rotation instructions.
8329 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8330 if (Subtarget->hasSSSE3())
8331 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8332 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8335 // If we have direct support for blends, we should lower by decomposing into
8336 // a permute. That will be faster than the domain cross.
8337 if (IsBlendSupported)
8338 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8341 // We implement this with SHUFPD which is pretty lame because it will likely
8342 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8343 // However, all the alternatives are still more cycles and newer chips don't
8344 // have this problem. It would be really nice if x86 had better shuffles here.
8345 V1 = DAG.getBitcast(MVT::v2f64, V1);
8346 V2 = DAG.getBitcast(MVT::v2f64, V2);
8347 return DAG.getBitcast(MVT::v2i64,
8348 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8351 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8353 /// This is used to disable more specialized lowerings when the shufps lowering
8354 /// will happen to be efficient.
8355 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8356 // This routine only handles 128-bit shufps.
8357 assert(Mask.size() == 4 && "Unsupported mask size!");
8359 // To lower with a single SHUFPS we need to have the low half and high half
8360 // each requiring a single input.
8361 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8363 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8369 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8371 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8372 /// It makes no assumptions about whether this is the *best* lowering, it simply
8374 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8375 ArrayRef<int> Mask, SDValue V1,
8376 SDValue V2, SelectionDAG &DAG) {
8377 SDValue LowV = V1, HighV = V2;
8378 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8381 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8383 if (NumV2Elements == 1) {
8385 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8388 // Compute the index adjacent to V2Index and in the same half by toggling
8390 int V2AdjIndex = V2Index ^ 1;
8392 if (Mask[V2AdjIndex] == -1) {
8393 // Handles all the cases where we have a single V2 element and an undef.
8394 // This will only ever happen in the high lanes because we commute the
8395 // vector otherwise.
8397 std::swap(LowV, HighV);
8398 NewMask[V2Index] -= 4;
8400 // Handle the case where the V2 element ends up adjacent to a V1 element.
8401 // To make this work, blend them together as the first step.
8402 int V1Index = V2AdjIndex;
8403 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8404 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8405 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8407 // Now proceed to reconstruct the final blend as we have the necessary
8408 // high or low half formed.
8415 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8416 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8418 } else if (NumV2Elements == 2) {
8419 if (Mask[0] < 4 && Mask[1] < 4) {
8420 // Handle the easy case where we have V1 in the low lanes and V2 in the
8424 } else if (Mask[2] < 4 && Mask[3] < 4) {
8425 // We also handle the reversed case because this utility may get called
8426 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8427 // arrange things in the right direction.
8433 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8434 // trying to place elements directly, just blend them and set up the final
8435 // shuffle to place them.
8437 // The first two blend mask elements are for V1, the second two are for
8439 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8440 Mask[2] < 4 ? Mask[2] : Mask[3],
8441 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8442 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8443 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8444 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8446 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8449 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8450 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8451 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8452 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8455 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8456 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8459 /// \brief Lower 4-lane 32-bit floating point shuffles.
8461 /// Uses instructions exclusively from the floating point unit to minimize
8462 /// domain crossing penalties, as these are sufficient to implement all v4f32
8464 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8465 const X86Subtarget *Subtarget,
8466 SelectionDAG &DAG) {
8468 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8469 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8470 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8471 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8472 ArrayRef<int> Mask = SVOp->getMask();
8473 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8476 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8478 if (NumV2Elements == 0) {
8479 // Check for being able to broadcast a single element.
8480 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8481 Mask, Subtarget, DAG))
8484 // Use even/odd duplicate instructions for masks that match their pattern.
8485 if (Subtarget->hasSSE3()) {
8486 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8487 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8488 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8489 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8492 if (Subtarget->hasAVX()) {
8493 // If we have AVX, we can use VPERMILPS which will allow folding a load
8494 // into the shuffle.
8495 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8496 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8499 // Otherwise, use a straight shuffle of a single input vector. We pass the
8500 // input vector to both operands to simulate this with a SHUFPS.
8501 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8502 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8505 // There are special ways we can lower some single-element blends. However, we
8506 // have custom ways we can lower more complex single-element blends below that
8507 // we defer to if both this and BLENDPS fail to match, so restrict this to
8508 // when the V2 input is targeting element 0 of the mask -- that is the fast
8510 if (NumV2Elements == 1 && Mask[0] >= 4)
8511 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8512 Mask, Subtarget, DAG))
8515 if (Subtarget->hasSSE41()) {
8516 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8520 // Use INSERTPS if we can complete the shuffle efficiently.
8521 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8524 if (!isSingleSHUFPSMask(Mask))
8525 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8526 DL, MVT::v4f32, V1, V2, Mask, DAG))
8530 // Use dedicated unpack instructions for masks that match their pattern.
8532 lowerVectorShuffleWithUNPCK(DL, MVT::v4f32, Mask, V1, V2, DAG))
8535 // Otherwise fall back to a SHUFPS lowering strategy.
8536 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8539 /// \brief Lower 4-lane i32 vector shuffles.
8541 /// We try to handle these with integer-domain shuffles where we can, but for
8542 /// blends we use the floating point domain blend instructions.
8543 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8544 const X86Subtarget *Subtarget,
8545 SelectionDAG &DAG) {
8547 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8548 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8549 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8550 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8551 ArrayRef<int> Mask = SVOp->getMask();
8552 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8554 // Whenever we can lower this as a zext, that instruction is strictly faster
8555 // than any alternative. It also allows us to fold memory operands into the
8556 // shuffle in many cases.
8557 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8558 Mask, Subtarget, DAG))
8562 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8564 if (NumV2Elements == 0) {
8565 // Check for being able to broadcast a single element.
8566 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8567 Mask, Subtarget, DAG))
8570 // Straight shuffle of a single input vector. For everything from SSE2
8571 // onward this has a single fast instruction with no scary immediates.
8572 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8573 // but we aren't actually going to use the UNPCK instruction because doing
8574 // so prevents folding a load into this instruction or making a copy.
8575 const int UnpackLoMask[] = {0, 0, 1, 1};
8576 const int UnpackHiMask[] = {2, 2, 3, 3};
8577 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8578 Mask = UnpackLoMask;
8579 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8580 Mask = UnpackHiMask;
8582 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8583 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8586 // Try to use shift instructions.
8588 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8591 // There are special ways we can lower some single-element blends.
8592 if (NumV2Elements == 1)
8593 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8594 Mask, Subtarget, DAG))
8597 // We have different paths for blend lowering, but they all must use the
8598 // *exact* same predicate.
8599 bool IsBlendSupported = Subtarget->hasSSE41();
8600 if (IsBlendSupported)
8601 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8605 if (SDValue Masked =
8606 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8609 // Use dedicated unpack instructions for masks that match their pattern.
8611 lowerVectorShuffleWithUNPCK(DL, MVT::v4i32, Mask, V1, V2, DAG))
8614 // Try to use byte rotation instructions.
8615 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8616 if (Subtarget->hasSSSE3())
8617 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8618 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8621 // If we have direct support for blends, we should lower by decomposing into
8622 // a permute. That will be faster than the domain cross.
8623 if (IsBlendSupported)
8624 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8627 // Try to lower by permuting the inputs into an unpack instruction.
8628 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8632 // We implement this with SHUFPS because it can blend from two vectors.
8633 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8634 // up the inputs, bypassing domain shift penalties that we would encur if we
8635 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8637 return DAG.getBitcast(
8639 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8640 DAG.getBitcast(MVT::v4f32, V2), Mask));
8643 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8644 /// shuffle lowering, and the most complex part.
8646 /// The lowering strategy is to try to form pairs of input lanes which are
8647 /// targeted at the same half of the final vector, and then use a dword shuffle
8648 /// to place them onto the right half, and finally unpack the paired lanes into
8649 /// their final position.
8651 /// The exact breakdown of how to form these dword pairs and align them on the
8652 /// correct sides is really tricky. See the comments within the function for
8653 /// more of the details.
8655 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8656 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8657 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8658 /// vector, form the analogous 128-bit 8-element Mask.
8659 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8660 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8661 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8662 assert(VT.getVectorElementType() == MVT::i16 && "Bad input type!");
8663 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8665 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8666 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8667 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8669 SmallVector<int, 4> LoInputs;
8670 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8671 [](int M) { return M >= 0; });
8672 std::sort(LoInputs.begin(), LoInputs.end());
8673 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8674 SmallVector<int, 4> HiInputs;
8675 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8676 [](int M) { return M >= 0; });
8677 std::sort(HiInputs.begin(), HiInputs.end());
8678 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8680 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8681 int NumHToL = LoInputs.size() - NumLToL;
8683 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8684 int NumHToH = HiInputs.size() - NumLToH;
8685 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8686 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8687 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8688 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8690 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8691 // such inputs we can swap two of the dwords across the half mark and end up
8692 // with <=2 inputs to each half in each half. Once there, we can fall through
8693 // to the generic code below. For example:
8695 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8696 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8698 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8699 // and an existing 2-into-2 on the other half. In this case we may have to
8700 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8701 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8702 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8703 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8704 // half than the one we target for fixing) will be fixed when we re-enter this
8705 // path. We will also combine away any sequence of PSHUFD instructions that
8706 // result into a single instruction. Here is an example of the tricky case:
8708 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8709 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8711 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8713 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8714 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8716 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8717 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8719 // The result is fine to be handled by the generic logic.
8720 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8721 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8722 int AOffset, int BOffset) {
8723 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8724 "Must call this with A having 3 or 1 inputs from the A half.");
8725 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8726 "Must call this with B having 1 or 3 inputs from the B half.");
8727 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8728 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8730 bool ThreeAInputs = AToAInputs.size() == 3;
8732 // Compute the index of dword with only one word among the three inputs in
8733 // a half by taking the sum of the half with three inputs and subtracting
8734 // the sum of the actual three inputs. The difference is the remaining
8737 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8738 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8739 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8740 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8741 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8742 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8743 int TripleNonInputIdx =
8744 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8745 TripleDWord = TripleNonInputIdx / 2;
8747 // We use xor with one to compute the adjacent DWord to whichever one the
8749 OneInputDWord = (OneInput / 2) ^ 1;
8751 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8752 // and BToA inputs. If there is also such a problem with the BToB and AToB
8753 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8754 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8755 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8756 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8757 // Compute how many inputs will be flipped by swapping these DWords. We
8759 // to balance this to ensure we don't form a 3-1 shuffle in the other
8761 int NumFlippedAToBInputs =
8762 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8763 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8764 int NumFlippedBToBInputs =
8765 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8766 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8767 if ((NumFlippedAToBInputs == 1 &&
8768 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8769 (NumFlippedBToBInputs == 1 &&
8770 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8771 // We choose whether to fix the A half or B half based on whether that
8772 // half has zero flipped inputs. At zero, we may not be able to fix it
8773 // with that half. We also bias towards fixing the B half because that
8774 // will more commonly be the high half, and we have to bias one way.
8775 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8776 ArrayRef<int> Inputs) {
8777 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8778 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8779 PinnedIdx ^ 1) != Inputs.end();
8780 // Determine whether the free index is in the flipped dword or the
8781 // unflipped dword based on where the pinned index is. We use this bit
8782 // in an xor to conditionally select the adjacent dword.
8783 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8784 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8785 FixFreeIdx) != Inputs.end();
8786 if (IsFixIdxInput == IsFixFreeIdxInput)
8788 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8789 FixFreeIdx) != Inputs.end();
8790 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8791 "We need to be changing the number of flipped inputs!");
8792 int PSHUFHalfMask[] = {0, 1, 2, 3};
8793 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8794 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8796 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8799 if (M != -1 && M == FixIdx)
8801 else if (M != -1 && M == FixFreeIdx)
8804 if (NumFlippedBToBInputs != 0) {
8806 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8807 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8809 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8810 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8811 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8816 int PSHUFDMask[] = {0, 1, 2, 3};
8817 PSHUFDMask[ADWord] = BDWord;
8818 PSHUFDMask[BDWord] = ADWord;
8821 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8822 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8824 // Adjust the mask to match the new locations of A and B.
8826 if (M != -1 && M/2 == ADWord)
8827 M = 2 * BDWord + M % 2;
8828 else if (M != -1 && M/2 == BDWord)
8829 M = 2 * ADWord + M % 2;
8831 // Recurse back into this routine to re-compute state now that this isn't
8832 // a 3 and 1 problem.
8833 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8836 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8837 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8838 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8839 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8841 // At this point there are at most two inputs to the low and high halves from
8842 // each half. That means the inputs can always be grouped into dwords and
8843 // those dwords can then be moved to the correct half with a dword shuffle.
8844 // We use at most one low and one high word shuffle to collect these paired
8845 // inputs into dwords, and finally a dword shuffle to place them.
8846 int PSHUFLMask[4] = {-1, -1, -1, -1};
8847 int PSHUFHMask[4] = {-1, -1, -1, -1};
8848 int PSHUFDMask[4] = {-1, -1, -1, -1};
8850 // First fix the masks for all the inputs that are staying in their
8851 // original halves. This will then dictate the targets of the cross-half
8853 auto fixInPlaceInputs =
8854 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8855 MutableArrayRef<int> SourceHalfMask,
8856 MutableArrayRef<int> HalfMask, int HalfOffset) {
8857 if (InPlaceInputs.empty())
8859 if (InPlaceInputs.size() == 1) {
8860 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8861 InPlaceInputs[0] - HalfOffset;
8862 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8865 if (IncomingInputs.empty()) {
8866 // Just fix all of the in place inputs.
8867 for (int Input : InPlaceInputs) {
8868 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8869 PSHUFDMask[Input / 2] = Input / 2;
8874 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8875 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8876 InPlaceInputs[0] - HalfOffset;
8877 // Put the second input next to the first so that they are packed into
8878 // a dword. We find the adjacent index by toggling the low bit.
8879 int AdjIndex = InPlaceInputs[0] ^ 1;
8880 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8881 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8882 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8884 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8885 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8887 // Now gather the cross-half inputs and place them into a free dword of
8888 // their target half.
8889 // FIXME: This operation could almost certainly be simplified dramatically to
8890 // look more like the 3-1 fixing operation.
8891 auto moveInputsToRightHalf = [&PSHUFDMask](
8892 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8893 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8894 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8896 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8897 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8899 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8901 int LowWord = Word & ~1;
8902 int HighWord = Word | 1;
8903 return isWordClobbered(SourceHalfMask, LowWord) ||
8904 isWordClobbered(SourceHalfMask, HighWord);
8907 if (IncomingInputs.empty())
8910 if (ExistingInputs.empty()) {
8911 // Map any dwords with inputs from them into the right half.
8912 for (int Input : IncomingInputs) {
8913 // If the source half mask maps over the inputs, turn those into
8914 // swaps and use the swapped lane.
8915 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8916 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8917 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8918 Input - SourceOffset;
8919 // We have to swap the uses in our half mask in one sweep.
8920 for (int &M : HalfMask)
8921 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8923 else if (M == Input)
8924 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8926 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8927 Input - SourceOffset &&
8928 "Previous placement doesn't match!");
8930 // Note that this correctly re-maps both when we do a swap and when
8931 // we observe the other side of the swap above. We rely on that to
8932 // avoid swapping the members of the input list directly.
8933 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8936 // Map the input's dword into the correct half.
8937 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8938 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8940 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8942 "Previous placement doesn't match!");
8945 // And just directly shift any other-half mask elements to be same-half
8946 // as we will have mirrored the dword containing the element into the
8947 // same position within that half.
8948 for (int &M : HalfMask)
8949 if (M >= SourceOffset && M < SourceOffset + 4) {
8950 M = M - SourceOffset + DestOffset;
8951 assert(M >= 0 && "This should never wrap below zero!");
8956 // Ensure we have the input in a viable dword of its current half. This
8957 // is particularly tricky because the original position may be clobbered
8958 // by inputs being moved and *staying* in that half.
8959 if (IncomingInputs.size() == 1) {
8960 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8961 int InputFixed = std::find(std::begin(SourceHalfMask),
8962 std::end(SourceHalfMask), -1) -
8963 std::begin(SourceHalfMask) + SourceOffset;
8964 SourceHalfMask[InputFixed - SourceOffset] =
8965 IncomingInputs[0] - SourceOffset;
8966 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8968 IncomingInputs[0] = InputFixed;
8970 } else if (IncomingInputs.size() == 2) {
8971 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8972 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8973 // We have two non-adjacent or clobbered inputs we need to extract from
8974 // the source half. To do this, we need to map them into some adjacent
8975 // dword slot in the source mask.
8976 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8977 IncomingInputs[1] - SourceOffset};
8979 // If there is a free slot in the source half mask adjacent to one of
8980 // the inputs, place the other input in it. We use (Index XOR 1) to
8981 // compute an adjacent index.
8982 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8983 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8984 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8985 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8986 InputsFixed[1] = InputsFixed[0] ^ 1;
8987 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8988 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8989 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8990 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8991 InputsFixed[0] = InputsFixed[1] ^ 1;
8992 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8993 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8994 // The two inputs are in the same DWord but it is clobbered and the
8995 // adjacent DWord isn't used at all. Move both inputs to the free
8997 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8998 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8999 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9000 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9002 // The only way we hit this point is if there is no clobbering
9003 // (because there are no off-half inputs to this half) and there is no
9004 // free slot adjacent to one of the inputs. In this case, we have to
9005 // swap an input with a non-input.
9006 for (int i = 0; i < 4; ++i)
9007 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9008 "We can't handle any clobbers here!");
9009 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9010 "Cannot have adjacent inputs here!");
9012 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9013 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9015 // We also have to update the final source mask in this case because
9016 // it may need to undo the above swap.
9017 for (int &M : FinalSourceHalfMask)
9018 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9019 M = InputsFixed[1] + SourceOffset;
9020 else if (M == InputsFixed[1] + SourceOffset)
9021 M = (InputsFixed[0] ^ 1) + SourceOffset;
9023 InputsFixed[1] = InputsFixed[0] ^ 1;
9026 // Point everything at the fixed inputs.
9027 for (int &M : HalfMask)
9028 if (M == IncomingInputs[0])
9029 M = InputsFixed[0] + SourceOffset;
9030 else if (M == IncomingInputs[1])
9031 M = InputsFixed[1] + SourceOffset;
9033 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9034 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9037 llvm_unreachable("Unhandled input size!");
9040 // Now hoist the DWord down to the right half.
9041 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9042 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9043 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9044 for (int &M : HalfMask)
9045 for (int Input : IncomingInputs)
9047 M = FreeDWord * 2 + Input % 2;
9049 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9050 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9051 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9052 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9054 // Now enact all the shuffles we've computed to move the inputs into their
9056 if (!isNoopShuffleMask(PSHUFLMask))
9057 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9058 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9059 if (!isNoopShuffleMask(PSHUFHMask))
9060 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9061 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9062 if (!isNoopShuffleMask(PSHUFDMask))
9065 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9066 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9068 // At this point, each half should contain all its inputs, and we can then
9069 // just shuffle them into their final position.
9070 assert(std::count_if(LoMask.begin(), LoMask.end(),
9071 [](int M) { return M >= 4; }) == 0 &&
9072 "Failed to lift all the high half inputs to the low mask!");
9073 assert(std::count_if(HiMask.begin(), HiMask.end(),
9074 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9075 "Failed to lift all the low half inputs to the high mask!");
9077 // Do a half shuffle for the low mask.
9078 if (!isNoopShuffleMask(LoMask))
9079 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9080 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9082 // Do a half shuffle with the high mask after shifting its values down.
9083 for (int &M : HiMask)
9086 if (!isNoopShuffleMask(HiMask))
9087 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9088 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9093 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9094 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9095 SDValue V2, ArrayRef<int> Mask,
9096 SelectionDAG &DAG, bool &V1InUse,
9098 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9104 int Size = Mask.size();
9105 int Scale = 16 / Size;
9106 for (int i = 0; i < 16; ++i) {
9107 if (Mask[i / Scale] == -1) {
9108 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9110 const int ZeroMask = 0x80;
9111 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9113 int V2Idx = Mask[i / Scale] < Size
9115 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9116 if (Zeroable[i / Scale])
9117 V1Idx = V2Idx = ZeroMask;
9118 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9119 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9120 V1InUse |= (ZeroMask != V1Idx);
9121 V2InUse |= (ZeroMask != V2Idx);
9126 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9127 DAG.getBitcast(MVT::v16i8, V1),
9128 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9130 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9131 DAG.getBitcast(MVT::v16i8, V2),
9132 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9134 // If we need shuffled inputs from both, blend the two.
9136 if (V1InUse && V2InUse)
9137 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9139 V = V1InUse ? V1 : V2;
9141 // Cast the result back to the correct type.
9142 return DAG.getBitcast(VT, V);
9145 /// \brief Generic lowering of 8-lane i16 shuffles.
9147 /// This handles both single-input shuffles and combined shuffle/blends with
9148 /// two inputs. The single input shuffles are immediately delegated to
9149 /// a dedicated lowering routine.
9151 /// The blends are lowered in one of three fundamental ways. If there are few
9152 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9153 /// of the input is significantly cheaper when lowered as an interleaving of
9154 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9155 /// halves of the inputs separately (making them have relatively few inputs)
9156 /// and then concatenate them.
9157 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9158 const X86Subtarget *Subtarget,
9159 SelectionDAG &DAG) {
9161 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9162 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9163 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9164 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9165 ArrayRef<int> OrigMask = SVOp->getMask();
9166 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9167 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9168 MutableArrayRef<int> Mask(MaskStorage);
9170 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9172 // Whenever we can lower this as a zext, that instruction is strictly faster
9173 // than any alternative.
9174 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9175 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9178 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9180 auto isV2 = [](int M) { return M >= 8; };
9182 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9184 if (NumV2Inputs == 0) {
9185 // Check for being able to broadcast a single element.
9186 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9187 Mask, Subtarget, DAG))
9190 // Try to use shift instructions.
9192 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9195 // Use dedicated unpack instructions for masks that match their pattern.
9197 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9200 // Try to use byte rotation instructions.
9201 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9202 Mask, Subtarget, DAG))
9205 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9209 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9210 "All single-input shuffles should be canonicalized to be V1-input "
9213 // Try to use shift instructions.
9215 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9218 // See if we can use SSE4A Extraction / Insertion.
9219 if (Subtarget->hasSSE4A())
9220 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9223 // There are special ways we can lower some single-element blends.
9224 if (NumV2Inputs == 1)
9225 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9226 Mask, Subtarget, DAG))
9229 // We have different paths for blend lowering, but they all must use the
9230 // *exact* same predicate.
9231 bool IsBlendSupported = Subtarget->hasSSE41();
9232 if (IsBlendSupported)
9233 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9237 if (SDValue Masked =
9238 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9241 // Use dedicated unpack instructions for masks that match their pattern.
9243 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9246 // Try to use byte rotation instructions.
9247 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9248 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9251 if (SDValue BitBlend =
9252 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9255 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9259 // If we can't directly blend but can use PSHUFB, that will be better as it
9260 // can both shuffle and set up the inefficient blend.
9261 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9262 bool V1InUse, V2InUse;
9263 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9267 // We can always bit-blend if we have to so the fallback strategy is to
9268 // decompose into single-input permutes and blends.
9269 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9273 /// \brief Check whether a compaction lowering can be done by dropping even
9274 /// elements and compute how many times even elements must be dropped.
9276 /// This handles shuffles which take every Nth element where N is a power of
9277 /// two. Example shuffle masks:
9279 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9280 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9281 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9282 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9283 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9284 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9286 /// Any of these lanes can of course be undef.
9288 /// This routine only supports N <= 3.
9289 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9292 /// \returns N above, or the number of times even elements must be dropped if
9293 /// there is such a number. Otherwise returns zero.
9294 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9295 // Figure out whether we're looping over two inputs or just one.
9296 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9298 // The modulus for the shuffle vector entries is based on whether this is
9299 // a single input or not.
9300 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9301 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9302 "We should only be called with masks with a power-of-2 size!");
9304 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9306 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9307 // and 2^3 simultaneously. This is because we may have ambiguity with
9308 // partially undef inputs.
9309 bool ViableForN[3] = {true, true, true};
9311 for (int i = 0, e = Mask.size(); i < e; ++i) {
9312 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9317 bool IsAnyViable = false;
9318 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9319 if (ViableForN[j]) {
9322 // The shuffle mask must be equal to (i * 2^N) % M.
9323 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9326 ViableForN[j] = false;
9328 // Early exit if we exhaust the possible powers of two.
9333 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9337 // Return 0 as there is no viable power of two.
9341 /// \brief Generic lowering of v16i8 shuffles.
9343 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9344 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9345 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9346 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9348 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9349 const X86Subtarget *Subtarget,
9350 SelectionDAG &DAG) {
9352 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9353 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9354 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9355 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9356 ArrayRef<int> Mask = SVOp->getMask();
9357 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9359 // Try to use shift instructions.
9361 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9364 // Try to use byte rotation instructions.
9365 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9366 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9369 // Try to use a zext lowering.
9370 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9371 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9374 // See if we can use SSE4A Extraction / Insertion.
9375 if (Subtarget->hasSSE4A())
9376 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9380 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9382 // For single-input shuffles, there are some nicer lowering tricks we can use.
9383 if (NumV2Elements == 0) {
9384 // Check for being able to broadcast a single element.
9385 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9386 Mask, Subtarget, DAG))
9389 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9390 // Notably, this handles splat and partial-splat shuffles more efficiently.
9391 // However, it only makes sense if the pre-duplication shuffle simplifies
9392 // things significantly. Currently, this means we need to be able to
9393 // express the pre-duplication shuffle as an i16 shuffle.
9395 // FIXME: We should check for other patterns which can be widened into an
9396 // i16 shuffle as well.
9397 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9398 for (int i = 0; i < 16; i += 2)
9399 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9404 auto tryToWidenViaDuplication = [&]() -> SDValue {
9405 if (!canWidenViaDuplication(Mask))
9407 SmallVector<int, 4> LoInputs;
9408 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9409 [](int M) { return M >= 0 && M < 8; });
9410 std::sort(LoInputs.begin(), LoInputs.end());
9411 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9413 SmallVector<int, 4> HiInputs;
9414 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9415 [](int M) { return M >= 8; });
9416 std::sort(HiInputs.begin(), HiInputs.end());
9417 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9420 bool TargetLo = LoInputs.size() >= HiInputs.size();
9421 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9422 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9424 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9425 SmallDenseMap<int, int, 8> LaneMap;
9426 for (int I : InPlaceInputs) {
9427 PreDupI16Shuffle[I/2] = I/2;
9430 int j = TargetLo ? 0 : 4, je = j + 4;
9431 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9432 // Check if j is already a shuffle of this input. This happens when
9433 // there are two adjacent bytes after we move the low one.
9434 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9435 // If we haven't yet mapped the input, search for a slot into which
9437 while (j < je && PreDupI16Shuffle[j] != -1)
9441 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9444 // Map this input with the i16 shuffle.
9445 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9448 // Update the lane map based on the mapping we ended up with.
9449 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9451 V1 = DAG.getBitcast(
9453 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9454 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9456 // Unpack the bytes to form the i16s that will be shuffled into place.
9457 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9458 MVT::v16i8, V1, V1);
9460 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9461 for (int i = 0; i < 16; ++i)
9462 if (Mask[i] != -1) {
9463 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9464 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9465 if (PostDupI16Shuffle[i / 2] == -1)
9466 PostDupI16Shuffle[i / 2] = MappedMask;
9468 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9469 "Conflicting entrties in the original shuffle!");
9471 return DAG.getBitcast(
9473 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9474 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9476 if (SDValue V = tryToWidenViaDuplication())
9480 if (SDValue Masked =
9481 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9484 // Use dedicated unpack instructions for masks that match their pattern.
9486 lowerVectorShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
9489 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9490 // with PSHUFB. It is important to do this before we attempt to generate any
9491 // blends but after all of the single-input lowerings. If the single input
9492 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9493 // want to preserve that and we can DAG combine any longer sequences into
9494 // a PSHUFB in the end. But once we start blending from multiple inputs,
9495 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9496 // and there are *very* few patterns that would actually be faster than the
9497 // PSHUFB approach because of its ability to zero lanes.
9499 // FIXME: The only exceptions to the above are blends which are exact
9500 // interleavings with direct instructions supporting them. We currently don't
9501 // handle those well here.
9502 if (Subtarget->hasSSSE3()) {
9503 bool V1InUse = false;
9504 bool V2InUse = false;
9506 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9507 DAG, V1InUse, V2InUse);
9509 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9510 // do so. This avoids using them to handle blends-with-zero which is
9511 // important as a single pshufb is significantly faster for that.
9512 if (V1InUse && V2InUse) {
9513 if (Subtarget->hasSSE41())
9514 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9515 Mask, Subtarget, DAG))
9518 // We can use an unpack to do the blending rather than an or in some
9519 // cases. Even though the or may be (very minorly) more efficient, we
9520 // preference this lowering because there are common cases where part of
9521 // the complexity of the shuffles goes away when we do the final blend as
9523 // FIXME: It might be worth trying to detect if the unpack-feeding
9524 // shuffles will both be pshufb, in which case we shouldn't bother with
9526 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9527 DL, MVT::v16i8, V1, V2, Mask, DAG))
9534 // There are special ways we can lower some single-element blends.
9535 if (NumV2Elements == 1)
9536 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9537 Mask, Subtarget, DAG))
9540 if (SDValue BitBlend =
9541 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9544 // Check whether a compaction lowering can be done. This handles shuffles
9545 // which take every Nth element for some even N. See the helper function for
9548 // We special case these as they can be particularly efficiently handled with
9549 // the PACKUSB instruction on x86 and they show up in common patterns of
9550 // rearranging bytes to truncate wide elements.
9551 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9552 // NumEvenDrops is the power of two stride of the elements. Another way of
9553 // thinking about it is that we need to drop the even elements this many
9554 // times to get the original input.
9555 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9557 // First we need to zero all the dropped bytes.
9558 assert(NumEvenDrops <= 3 &&
9559 "No support for dropping even elements more than 3 times.");
9560 // We use the mask type to pick which bytes are preserved based on how many
9561 // elements are dropped.
9562 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9563 SDValue ByteClearMask = DAG.getBitcast(
9564 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9565 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9567 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9569 // Now pack things back together.
9570 V1 = DAG.getBitcast(MVT::v8i16, V1);
9571 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9572 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9573 for (int i = 1; i < NumEvenDrops; ++i) {
9574 Result = DAG.getBitcast(MVT::v8i16, Result);
9575 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9581 // Handle multi-input cases by blending single-input shuffles.
9582 if (NumV2Elements > 0)
9583 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9586 // The fallback path for single-input shuffles widens this into two v8i16
9587 // vectors with unpacks, shuffles those, and then pulls them back together
9591 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9592 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9593 for (int i = 0; i < 16; ++i)
9595 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9597 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9599 SDValue VLoHalf, VHiHalf;
9600 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9601 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9603 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9604 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9605 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9606 [](int M) { return M >= 0 && M % 2 == 1; })) {
9607 // Use a mask to drop the high bytes.
9608 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9609 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9610 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9612 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9613 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9615 // Squash the masks to point directly into VLoHalf.
9616 for (int &M : LoBlendMask)
9619 for (int &M : HiBlendMask)
9623 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9624 // VHiHalf so that we can blend them as i16s.
9625 VLoHalf = DAG.getBitcast(
9626 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9627 VHiHalf = DAG.getBitcast(
9628 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9631 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9632 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9634 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9637 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9639 /// This routine breaks down the specific type of 128-bit shuffle and
9640 /// dispatches to the lowering routines accordingly.
9641 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9642 MVT VT, const X86Subtarget *Subtarget,
9643 SelectionDAG &DAG) {
9644 switch (VT.SimpleTy) {
9646 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9648 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9650 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9652 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9654 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9656 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9659 llvm_unreachable("Unimplemented!");
9663 /// \brief Helper function to test whether a shuffle mask could be
9664 /// simplified by widening the elements being shuffled.
9666 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9667 /// leaves it in an unspecified state.
9669 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9670 /// shuffle masks. The latter have the special property of a '-2' representing
9671 /// a zero-ed lane of a vector.
9672 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9673 SmallVectorImpl<int> &WidenedMask) {
9674 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9675 // If both elements are undef, its trivial.
9676 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9677 WidenedMask.push_back(SM_SentinelUndef);
9681 // Check for an undef mask and a mask value properly aligned to fit with
9682 // a pair of values. If we find such a case, use the non-undef mask's value.
9683 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9684 WidenedMask.push_back(Mask[i + 1] / 2);
9687 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9688 WidenedMask.push_back(Mask[i] / 2);
9692 // When zeroing, we need to spread the zeroing across both lanes to widen.
9693 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9694 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9695 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9696 WidenedMask.push_back(SM_SentinelZero);
9702 // Finally check if the two mask values are adjacent and aligned with
9704 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9705 WidenedMask.push_back(Mask[i] / 2);
9709 // Otherwise we can't safely widen the elements used in this shuffle.
9712 assert(WidenedMask.size() == Mask.size() / 2 &&
9713 "Incorrect size of mask after widening the elements!");
9718 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9720 /// This routine just extracts two subvectors, shuffles them independently, and
9721 /// then concatenates them back together. This should work effectively with all
9722 /// AVX vector shuffle types.
9723 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9724 SDValue V2, ArrayRef<int> Mask,
9725 SelectionDAG &DAG) {
9726 assert(VT.getSizeInBits() >= 256 &&
9727 "Only for 256-bit or wider vector shuffles!");
9728 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9729 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9731 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9732 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9734 int NumElements = VT.getVectorNumElements();
9735 int SplitNumElements = NumElements / 2;
9736 MVT ScalarVT = VT.getVectorElementType();
9737 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9739 // Rather than splitting build-vectors, just build two narrower build
9740 // vectors. This helps shuffling with splats and zeros.
9741 auto SplitVector = [&](SDValue V) {
9742 while (V.getOpcode() == ISD::BITCAST)
9743 V = V->getOperand(0);
9745 MVT OrigVT = V.getSimpleValueType();
9746 int OrigNumElements = OrigVT.getVectorNumElements();
9747 int OrigSplitNumElements = OrigNumElements / 2;
9748 MVT OrigScalarVT = OrigVT.getVectorElementType();
9749 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9753 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9755 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9756 DAG.getIntPtrConstant(0, DL));
9757 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9758 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9761 SmallVector<SDValue, 16> LoOps, HiOps;
9762 for (int i = 0; i < OrigSplitNumElements; ++i) {
9763 LoOps.push_back(BV->getOperand(i));
9764 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9766 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9767 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9769 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9770 DAG.getBitcast(SplitVT, HiV));
9773 SDValue LoV1, HiV1, LoV2, HiV2;
9774 std::tie(LoV1, HiV1) = SplitVector(V1);
9775 std::tie(LoV2, HiV2) = SplitVector(V2);
9777 // Now create two 4-way blends of these half-width vectors.
9778 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9779 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9780 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9781 for (int i = 0; i < SplitNumElements; ++i) {
9782 int M = HalfMask[i];
9783 if (M >= NumElements) {
9784 if (M >= NumElements + SplitNumElements)
9788 V2BlendMask.push_back(M - NumElements);
9789 V1BlendMask.push_back(-1);
9790 BlendMask.push_back(SplitNumElements + i);
9791 } else if (M >= 0) {
9792 if (M >= SplitNumElements)
9796 V2BlendMask.push_back(-1);
9797 V1BlendMask.push_back(M);
9798 BlendMask.push_back(i);
9800 V2BlendMask.push_back(-1);
9801 V1BlendMask.push_back(-1);
9802 BlendMask.push_back(-1);
9806 // Because the lowering happens after all combining takes place, we need to
9807 // manually combine these blend masks as much as possible so that we create
9808 // a minimal number of high-level vector shuffle nodes.
9810 // First try just blending the halves of V1 or V2.
9811 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9812 return DAG.getUNDEF(SplitVT);
9813 if (!UseLoV2 && !UseHiV2)
9814 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9815 if (!UseLoV1 && !UseHiV1)
9816 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9818 SDValue V1Blend, V2Blend;
9819 if (UseLoV1 && UseHiV1) {
9821 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9823 // We only use half of V1 so map the usage down into the final blend mask.
9824 V1Blend = UseLoV1 ? LoV1 : HiV1;
9825 for (int i = 0; i < SplitNumElements; ++i)
9826 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9827 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9829 if (UseLoV2 && UseHiV2) {
9831 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9833 // We only use half of V2 so map the usage down into the final blend mask.
9834 V2Blend = UseLoV2 ? LoV2 : HiV2;
9835 for (int i = 0; i < SplitNumElements; ++i)
9836 if (BlendMask[i] >= SplitNumElements)
9837 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9839 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9841 SDValue Lo = HalfBlend(LoMask);
9842 SDValue Hi = HalfBlend(HiMask);
9843 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9846 /// \brief Either split a vector in halves or decompose the shuffles and the
9849 /// This is provided as a good fallback for many lowerings of non-single-input
9850 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9851 /// between splitting the shuffle into 128-bit components and stitching those
9852 /// back together vs. extracting the single-input shuffles and blending those
9854 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9855 SDValue V2, ArrayRef<int> Mask,
9856 SelectionDAG &DAG) {
9857 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9858 "lower single-input shuffles as it "
9859 "could then recurse on itself.");
9860 int Size = Mask.size();
9862 // If this can be modeled as a broadcast of two elements followed by a blend,
9863 // prefer that lowering. This is especially important because broadcasts can
9864 // often fold with memory operands.
9865 auto DoBothBroadcast = [&] {
9866 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9869 if (V2BroadcastIdx == -1)
9870 V2BroadcastIdx = M - Size;
9871 else if (M - Size != V2BroadcastIdx)
9873 } else if (M >= 0) {
9874 if (V1BroadcastIdx == -1)
9876 else if (M != V1BroadcastIdx)
9881 if (DoBothBroadcast())
9882 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9885 // If the inputs all stem from a single 128-bit lane of each input, then we
9886 // split them rather than blending because the split will decompose to
9887 // unusually few instructions.
9888 int LaneCount = VT.getSizeInBits() / 128;
9889 int LaneSize = Size / LaneCount;
9890 SmallBitVector LaneInputs[2];
9891 LaneInputs[0].resize(LaneCount, false);
9892 LaneInputs[1].resize(LaneCount, false);
9893 for (int i = 0; i < Size; ++i)
9895 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9896 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9897 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9899 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9900 // that the decomposed single-input shuffles don't end up here.
9901 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9904 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9905 /// a permutation and blend of those lanes.
9907 /// This essentially blends the out-of-lane inputs to each lane into the lane
9908 /// from a permuted copy of the vector. This lowering strategy results in four
9909 /// instructions in the worst case for a single-input cross lane shuffle which
9910 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9911 /// of. Special cases for each particular shuffle pattern should be handled
9912 /// prior to trying this lowering.
9913 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9914 SDValue V1, SDValue V2,
9916 SelectionDAG &DAG) {
9917 // FIXME: This should probably be generalized for 512-bit vectors as well.
9918 assert(VT.is256BitVector() && "Only for 256-bit vector shuffles!");
9919 int LaneSize = Mask.size() / 2;
9921 // If there are only inputs from one 128-bit lane, splitting will in fact be
9922 // less expensive. The flags track whether the given lane contains an element
9923 // that crosses to another lane.
9924 bool LaneCrossing[2] = {false, false};
9925 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9926 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9927 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9928 if (!LaneCrossing[0] || !LaneCrossing[1])
9929 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9931 if (isSingleInputShuffleMask(Mask)) {
9932 SmallVector<int, 32> FlippedBlendMask;
9933 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9934 FlippedBlendMask.push_back(
9935 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9937 : Mask[i] % LaneSize +
9938 (i / LaneSize) * LaneSize + Size));
9940 // Flip the vector, and blend the results which should now be in-lane. The
9941 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9942 // 5 for the high source. The value 3 selects the high half of source 2 and
9943 // the value 2 selects the low half of source 2. We only use source 2 to
9944 // allow folding it into a memory operand.
9945 unsigned PERMMask = 3 | 2 << 4;
9946 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9947 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9948 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9951 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9952 // will be handled by the above logic and a blend of the results, much like
9953 // other patterns in AVX.
9954 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9957 /// \brief Handle lowering 2-lane 128-bit shuffles.
9958 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9959 SDValue V2, ArrayRef<int> Mask,
9960 const X86Subtarget *Subtarget,
9961 SelectionDAG &DAG) {
9962 // TODO: If minimizing size and one of the inputs is a zero vector and the
9963 // the zero vector has only one use, we could use a VPERM2X128 to save the
9964 // instruction bytes needed to explicitly generate the zero vector.
9966 // Blends are faster and handle all the non-lane-crossing cases.
9967 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9971 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9972 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9974 // If either input operand is a zero vector, use VPERM2X128 because its mask
9975 // allows us to replace the zero input with an implicit zero.
9976 if (!IsV1Zero && !IsV2Zero) {
9977 // Check for patterns which can be matched with a single insert of a 128-bit
9979 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9980 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9981 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9982 VT.getVectorNumElements() / 2);
9983 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9984 DAG.getIntPtrConstant(0, DL));
9985 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9986 OnlyUsesV1 ? V1 : V2,
9987 DAG.getIntPtrConstant(0, DL));
9988 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9992 // Otherwise form a 128-bit permutation. After accounting for undefs,
9993 // convert the 64-bit shuffle mask selection values into 128-bit
9994 // selection bits by dividing the indexes by 2 and shifting into positions
9995 // defined by a vperm2*128 instruction's immediate control byte.
9997 // The immediate permute control byte looks like this:
9998 // [1:0] - select 128 bits from sources for low half of destination
10000 // [3] - zero low half of destination
10001 // [5:4] - select 128 bits from sources for high half of destination
10003 // [7] - zero high half of destination
10005 int MaskLO = Mask[0];
10006 if (MaskLO == SM_SentinelUndef)
10007 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10009 int MaskHI = Mask[2];
10010 if (MaskHI == SM_SentinelUndef)
10011 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10013 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10015 // If either input is a zero vector, replace it with an undef input.
10016 // Shuffle mask values < 4 are selecting elements of V1.
10017 // Shuffle mask values >= 4 are selecting elements of V2.
10018 // Adjust each half of the permute mask by clearing the half that was
10019 // selecting the zero vector and setting the zero mask bit.
10021 V1 = DAG.getUNDEF(VT);
10023 PermMask = (PermMask & 0xf0) | 0x08;
10025 PermMask = (PermMask & 0x0f) | 0x80;
10028 V2 = DAG.getUNDEF(VT);
10030 PermMask = (PermMask & 0xf0) | 0x08;
10032 PermMask = (PermMask & 0x0f) | 0x80;
10035 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10036 DAG.getConstant(PermMask, DL, MVT::i8));
10039 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10040 /// shuffling each lane.
10042 /// This will only succeed when the result of fixing the 128-bit lanes results
10043 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10044 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10045 /// the lane crosses early and then use simpler shuffles within each lane.
10047 /// FIXME: It might be worthwhile at some point to support this without
10048 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10049 /// in x86 only floating point has interesting non-repeating shuffles, and even
10050 /// those are still *marginally* more expensive.
10051 static SDValue lowerVectorShuffleByMerging128BitLanes(
10052 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10053 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10054 assert(!isSingleInputShuffleMask(Mask) &&
10055 "This is only useful with multiple inputs.");
10057 int Size = Mask.size();
10058 int LaneSize = 128 / VT.getScalarSizeInBits();
10059 int NumLanes = Size / LaneSize;
10060 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10062 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10063 // check whether the in-128-bit lane shuffles share a repeating pattern.
10064 SmallVector<int, 4> Lanes;
10065 Lanes.resize(NumLanes, -1);
10066 SmallVector<int, 4> InLaneMask;
10067 InLaneMask.resize(LaneSize, -1);
10068 for (int i = 0; i < Size; ++i) {
10072 int j = i / LaneSize;
10074 if (Lanes[j] < 0) {
10075 // First entry we've seen for this lane.
10076 Lanes[j] = Mask[i] / LaneSize;
10077 } else if (Lanes[j] != Mask[i] / LaneSize) {
10078 // This doesn't match the lane selected previously!
10082 // Check that within each lane we have a consistent shuffle mask.
10083 int k = i % LaneSize;
10084 if (InLaneMask[k] < 0) {
10085 InLaneMask[k] = Mask[i] % LaneSize;
10086 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10087 // This doesn't fit a repeating in-lane mask.
10092 // First shuffle the lanes into place.
10093 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10094 VT.getSizeInBits() / 64);
10095 SmallVector<int, 8> LaneMask;
10096 LaneMask.resize(NumLanes * 2, -1);
10097 for (int i = 0; i < NumLanes; ++i)
10098 if (Lanes[i] >= 0) {
10099 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10100 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10103 V1 = DAG.getBitcast(LaneVT, V1);
10104 V2 = DAG.getBitcast(LaneVT, V2);
10105 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10107 // Cast it back to the type we actually want.
10108 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10110 // Now do a simple shuffle that isn't lane crossing.
10111 SmallVector<int, 8> NewMask;
10112 NewMask.resize(Size, -1);
10113 for (int i = 0; i < Size; ++i)
10115 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10116 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10117 "Must not introduce lane crosses at this point!");
10119 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10122 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10125 /// This returns true if the elements from a particular input are already in the
10126 /// slot required by the given mask and require no permutation.
10127 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10128 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10129 int Size = Mask.size();
10130 for (int i = 0; i < Size; ++i)
10131 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10137 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10138 ArrayRef<int> Mask, SDValue V1,
10139 SDValue V2, SelectionDAG &DAG) {
10141 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10142 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10143 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10144 int NumElts = VT.getVectorNumElements();
10145 bool ShufpdMask = true;
10146 bool CommutableMask = true;
10147 unsigned Immediate = 0;
10148 for (int i = 0; i < NumElts; ++i) {
10151 int Val = (i & 6) + NumElts * (i & 1);
10152 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10153 if (Mask[i] < Val || Mask[i] > Val + 1)
10154 ShufpdMask = false;
10155 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10156 CommutableMask = false;
10157 Immediate |= (Mask[i] % 2) << i;
10160 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10161 DAG.getConstant(Immediate, DL, MVT::i8));
10162 if (CommutableMask)
10163 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10164 DAG.getConstant(Immediate, DL, MVT::i8));
10168 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10170 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10171 /// isn't available.
10172 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10173 const X86Subtarget *Subtarget,
10174 SelectionDAG &DAG) {
10176 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10177 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10178 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10179 ArrayRef<int> Mask = SVOp->getMask();
10180 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10182 SmallVector<int, 4> WidenedMask;
10183 if (canWidenShuffleElements(Mask, WidenedMask))
10184 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10187 if (isSingleInputShuffleMask(Mask)) {
10188 // Check for being able to broadcast a single element.
10189 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10190 Mask, Subtarget, DAG))
10193 // Use low duplicate instructions for masks that match their pattern.
10194 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10195 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10197 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10198 // Non-half-crossing single input shuffles can be lowerid with an
10199 // interleaved permutation.
10200 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10201 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10202 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10203 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10206 // With AVX2 we have direct support for this permutation.
10207 if (Subtarget->hasAVX2())
10208 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10209 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10211 // Otherwise, fall back.
10212 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10216 // Use dedicated unpack instructions for masks that match their pattern.
10218 lowerVectorShuffleWithUNPCK(DL, MVT::v4f64, Mask, V1, V2, DAG))
10221 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10225 // Check if the blend happens to exactly fit that of SHUFPD.
10227 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10230 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10231 // shuffle. However, if we have AVX2 and either inputs are already in place,
10232 // we will be able to shuffle even across lanes the other input in a single
10233 // instruction so skip this pattern.
10234 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10235 isShuffleMaskInputInPlace(1, Mask))))
10236 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10237 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10240 // If we have AVX2 then we always want to lower with a blend because an v4 we
10241 // can fully permute the elements.
10242 if (Subtarget->hasAVX2())
10243 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10246 // Otherwise fall back on generic lowering.
10247 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10250 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10252 /// This routine is only called when we have AVX2 and thus a reasonable
10253 /// instruction set for v4i64 shuffling..
10254 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10255 const X86Subtarget *Subtarget,
10256 SelectionDAG &DAG) {
10258 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10259 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10260 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10261 ArrayRef<int> Mask = SVOp->getMask();
10262 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10263 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10265 SmallVector<int, 4> WidenedMask;
10266 if (canWidenShuffleElements(Mask, WidenedMask))
10267 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10270 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10274 // Check for being able to broadcast a single element.
10275 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10276 Mask, Subtarget, DAG))
10279 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10280 // use lower latency instructions that will operate on both 128-bit lanes.
10281 SmallVector<int, 2> RepeatedMask;
10282 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10283 if (isSingleInputShuffleMask(Mask)) {
10284 int PSHUFDMask[] = {-1, -1, -1, -1};
10285 for (int i = 0; i < 2; ++i)
10286 if (RepeatedMask[i] >= 0) {
10287 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10288 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10290 return DAG.getBitcast(
10292 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10293 DAG.getBitcast(MVT::v8i32, V1),
10294 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10298 // AVX2 provides a direct instruction for permuting a single input across
10300 if (isSingleInputShuffleMask(Mask))
10301 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10302 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10304 // Try to use shift instructions.
10305 if (SDValue Shift =
10306 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10309 // Use dedicated unpack instructions for masks that match their pattern.
10311 lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
10314 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10315 // shuffle. However, if we have AVX2 and either inputs are already in place,
10316 // we will be able to shuffle even across lanes the other input in a single
10317 // instruction so skip this pattern.
10318 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10319 isShuffleMaskInputInPlace(1, Mask))))
10320 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10321 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10324 // Otherwise fall back on generic blend lowering.
10325 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10329 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10331 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10332 /// isn't available.
10333 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10334 const X86Subtarget *Subtarget,
10335 SelectionDAG &DAG) {
10337 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10338 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10339 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10340 ArrayRef<int> Mask = SVOp->getMask();
10341 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10343 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10347 // Check for being able to broadcast a single element.
10348 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10349 Mask, Subtarget, DAG))
10352 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10353 // options to efficiently lower the shuffle.
10354 SmallVector<int, 4> RepeatedMask;
10355 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10356 assert(RepeatedMask.size() == 4 &&
10357 "Repeated masks must be half the mask width!");
10359 // Use even/odd duplicate instructions for masks that match their pattern.
10360 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10361 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10362 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10363 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10365 if (isSingleInputShuffleMask(Mask))
10366 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10367 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10369 // Use dedicated unpack instructions for masks that match their pattern.
10371 lowerVectorShuffleWithUNPCK(DL, MVT::v8f32, Mask, V1, V2, DAG))
10374 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10375 // have already handled any direct blends. We also need to squash the
10376 // repeated mask into a simulated v4f32 mask.
10377 for (int i = 0; i < 4; ++i)
10378 if (RepeatedMask[i] >= 8)
10379 RepeatedMask[i] -= 4;
10380 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10383 // If we have a single input shuffle with different shuffle patterns in the
10384 // two 128-bit lanes use the variable mask to VPERMILPS.
10385 if (isSingleInputShuffleMask(Mask)) {
10386 SDValue VPermMask[8];
10387 for (int i = 0; i < 8; ++i)
10388 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10389 : DAG.getConstant(Mask[i], DL, MVT::i32);
10390 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10391 return DAG.getNode(
10392 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10393 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10395 if (Subtarget->hasAVX2())
10396 return DAG.getNode(
10397 X86ISD::VPERMV, DL, MVT::v8f32,
10398 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10399 MVT::v8i32, VPermMask)),
10402 // Otherwise, fall back.
10403 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10407 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10409 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10410 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10413 // If we have AVX2 then we always want to lower with a blend because at v8 we
10414 // can fully permute the elements.
10415 if (Subtarget->hasAVX2())
10416 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10419 // Otherwise fall back on generic lowering.
10420 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10423 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10425 /// This routine is only called when we have AVX2 and thus a reasonable
10426 /// instruction set for v8i32 shuffling..
10427 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10428 const X86Subtarget *Subtarget,
10429 SelectionDAG &DAG) {
10431 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10432 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10433 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10434 ArrayRef<int> Mask = SVOp->getMask();
10435 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10436 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10438 // Whenever we can lower this as a zext, that instruction is strictly faster
10439 // than any alternative. It also allows us to fold memory operands into the
10440 // shuffle in many cases.
10441 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10442 Mask, Subtarget, DAG))
10445 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10449 // Check for being able to broadcast a single element.
10450 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10451 Mask, Subtarget, DAG))
10454 // If the shuffle mask is repeated in each 128-bit lane we can use more
10455 // efficient instructions that mirror the shuffles across the two 128-bit
10457 SmallVector<int, 4> RepeatedMask;
10458 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10459 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10460 if (isSingleInputShuffleMask(Mask))
10461 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10462 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10464 // Use dedicated unpack instructions for masks that match their pattern.
10466 lowerVectorShuffleWithUNPCK(DL, MVT::v8i32, Mask, V1, V2, DAG))
10470 // Try to use shift instructions.
10471 if (SDValue Shift =
10472 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10475 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10476 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10479 // If the shuffle patterns aren't repeated but it is a single input, directly
10480 // generate a cross-lane VPERMD instruction.
10481 if (isSingleInputShuffleMask(Mask)) {
10482 SDValue VPermMask[8];
10483 for (int i = 0; i < 8; ++i)
10484 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10485 : DAG.getConstant(Mask[i], DL, MVT::i32);
10486 return DAG.getNode(
10487 X86ISD::VPERMV, DL, MVT::v8i32,
10488 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10491 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10493 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10494 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10497 // Otherwise fall back on generic blend lowering.
10498 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10502 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10504 /// This routine is only called when we have AVX2 and thus a reasonable
10505 /// instruction set for v16i16 shuffling..
10506 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10507 const X86Subtarget *Subtarget,
10508 SelectionDAG &DAG) {
10510 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10511 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10512 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10513 ArrayRef<int> Mask = SVOp->getMask();
10514 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10515 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10517 // Whenever we can lower this as a zext, that instruction is strictly faster
10518 // than any alternative. It also allows us to fold memory operands into the
10519 // shuffle in many cases.
10520 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10521 Mask, Subtarget, DAG))
10524 // Check for being able to broadcast a single element.
10525 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10526 Mask, Subtarget, DAG))
10529 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10533 // Use dedicated unpack instructions for masks that match their pattern.
10535 lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG))
10538 // Try to use shift instructions.
10539 if (SDValue Shift =
10540 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10543 // Try to use byte rotation instructions.
10544 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10545 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10548 if (isSingleInputShuffleMask(Mask)) {
10549 // There are no generalized cross-lane shuffle operations available on i16
10551 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10552 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10555 SmallVector<int, 8> RepeatedMask;
10556 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10557 // As this is a single-input shuffle, the repeated mask should be
10558 // a strictly valid v8i16 mask that we can pass through to the v8i16
10559 // lowering to handle even the v16 case.
10560 return lowerV8I16GeneralSingleInputVectorShuffle(
10561 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10564 SDValue PSHUFBMask[32];
10565 for (int i = 0; i < 16; ++i) {
10566 if (Mask[i] == -1) {
10567 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10571 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10572 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10573 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10574 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10576 return DAG.getBitcast(MVT::v16i16,
10577 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10578 DAG.getBitcast(MVT::v32i8, V1),
10579 DAG.getNode(ISD::BUILD_VECTOR, DL,
10580 MVT::v32i8, PSHUFBMask)));
10583 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10585 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10586 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10589 // Otherwise fall back on generic lowering.
10590 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10593 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10595 /// This routine is only called when we have AVX2 and thus a reasonable
10596 /// instruction set for v32i8 shuffling..
10597 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10598 const X86Subtarget *Subtarget,
10599 SelectionDAG &DAG) {
10601 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10602 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10603 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10604 ArrayRef<int> Mask = SVOp->getMask();
10605 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10606 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10608 // Whenever we can lower this as a zext, that instruction is strictly faster
10609 // than any alternative. It also allows us to fold memory operands into the
10610 // shuffle in many cases.
10611 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10612 Mask, Subtarget, DAG))
10615 // Check for being able to broadcast a single element.
10616 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10617 Mask, Subtarget, DAG))
10620 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10624 // Use dedicated unpack instructions for masks that match their pattern.
10626 lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
10629 // Try to use shift instructions.
10630 if (SDValue Shift =
10631 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10634 // Try to use byte rotation instructions.
10635 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10636 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10639 if (isSingleInputShuffleMask(Mask)) {
10640 // There are no generalized cross-lane shuffle operations available on i8
10642 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10643 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10646 SDValue PSHUFBMask[32];
10647 for (int i = 0; i < 32; ++i)
10650 ? DAG.getUNDEF(MVT::i8)
10651 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10654 return DAG.getNode(
10655 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10656 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10659 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10661 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10662 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10665 // Otherwise fall back on generic lowering.
10666 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10669 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10671 /// This routine either breaks down the specific type of a 256-bit x86 vector
10672 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10673 /// together based on the available instructions.
10674 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10675 MVT VT, const X86Subtarget *Subtarget,
10676 SelectionDAG &DAG) {
10678 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10679 ArrayRef<int> Mask = SVOp->getMask();
10681 // If we have a single input to the zero element, insert that into V1 if we
10682 // can do so cheaply.
10683 int NumElts = VT.getVectorNumElements();
10684 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10685 return M >= NumElts;
10688 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10689 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10690 DL, VT, V1, V2, Mask, Subtarget, DAG))
10693 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10694 // can check for those subtargets here and avoid much of the subtarget
10695 // querying in the per-vector-type lowering routines. With AVX1 we have
10696 // essentially *zero* ability to manipulate a 256-bit vector with integer
10697 // types. Since we'll use floating point types there eventually, just
10698 // immediately cast everything to a float and operate entirely in that domain.
10699 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10700 int ElementBits = VT.getScalarSizeInBits();
10701 if (ElementBits < 32)
10702 // No floating point type available, decompose into 128-bit vectors.
10703 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10705 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10706 VT.getVectorNumElements());
10707 V1 = DAG.getBitcast(FpVT, V1);
10708 V2 = DAG.getBitcast(FpVT, V2);
10709 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10712 switch (VT.SimpleTy) {
10714 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10716 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10718 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10720 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10722 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10724 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10727 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10731 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
10732 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
10733 ArrayRef<int> Mask,
10734 SDValue V1, SDValue V2,
10735 SelectionDAG &DAG) {
10736 assert(VT.getScalarSizeInBits() == 64 &&
10737 "Unexpected element type size for 128bit shuffle.");
10739 // To handle 256 bit vector requires VLX and most probably
10740 // function lowerV2X128VectorShuffle() is better solution.
10741 assert(VT.is512BitVector() && "Unexpected vector size for 128bit shuffle.");
10743 SmallVector<int, 4> WidenedMask;
10744 if (!canWidenShuffleElements(Mask, WidenedMask))
10747 // Form a 128-bit permutation.
10748 // Convert the 64-bit shuffle mask selection values into 128-bit selection
10749 // bits defined by a vshuf64x2 instruction's immediate control byte.
10750 unsigned PermMask = 0, Imm = 0;
10751 unsigned ControlBitsNum = WidenedMask.size() / 2;
10753 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
10754 if (WidenedMask[i] == SM_SentinelZero)
10757 // Use first element in place of undef mask.
10758 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
10759 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
10762 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
10763 DAG.getConstant(PermMask, DL, MVT::i8));
10766 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10767 ArrayRef<int> Mask, SDValue V1,
10768 SDValue V2, SelectionDAG &DAG) {
10770 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10772 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10773 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10775 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
10776 if (isSingleInputShuffleMask(Mask))
10777 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10779 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10782 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10783 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10784 const X86Subtarget *Subtarget,
10785 SelectionDAG &DAG) {
10787 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10788 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10789 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10790 ArrayRef<int> Mask = SVOp->getMask();
10791 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10793 if (SDValue Shuf128 =
10794 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
10797 if (SDValue Unpck =
10798 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10801 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10804 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10805 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10806 const X86Subtarget *Subtarget,
10807 SelectionDAG &DAG) {
10809 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10810 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10811 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10812 ArrayRef<int> Mask = SVOp->getMask();
10813 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10815 if (SDValue Unpck =
10816 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10819 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10822 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10823 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10824 const X86Subtarget *Subtarget,
10825 SelectionDAG &DAG) {
10827 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10828 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10829 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10830 ArrayRef<int> Mask = SVOp->getMask();
10831 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10833 if (SDValue Shuf128 =
10834 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
10837 if (SDValue Unpck =
10838 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10841 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10844 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10845 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10846 const X86Subtarget *Subtarget,
10847 SelectionDAG &DAG) {
10849 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10850 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10851 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10852 ArrayRef<int> Mask = SVOp->getMask();
10853 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10855 if (SDValue Unpck =
10856 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
10859 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
10862 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10863 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10864 const X86Subtarget *Subtarget,
10865 SelectionDAG &DAG) {
10867 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10868 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10869 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10870 ArrayRef<int> Mask = SVOp->getMask();
10871 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10872 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10874 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
10877 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10878 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10879 const X86Subtarget *Subtarget,
10880 SelectionDAG &DAG) {
10882 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10883 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10884 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10885 ArrayRef<int> Mask = SVOp->getMask();
10886 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10887 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10889 // FIXME: Implement direct support for this type!
10890 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10893 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10895 /// This routine either breaks down the specific type of a 512-bit x86 vector
10896 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10897 /// together based on the available instructions.
10898 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10899 MVT VT, const X86Subtarget *Subtarget,
10900 SelectionDAG &DAG) {
10902 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10903 ArrayRef<int> Mask = SVOp->getMask();
10904 assert(Subtarget->hasAVX512() &&
10905 "Cannot lower 512-bit vectors w/ basic ISA!");
10907 // Check for being able to broadcast a single element.
10908 if (SDValue Broadcast =
10909 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10912 // Dispatch to each element type for lowering. If we don't have supprot for
10913 // specific element type shuffles at 512 bits, immediately split them and
10914 // lower them. Each lowering routine of a given type is allowed to assume that
10915 // the requisite ISA extensions for that element type are available.
10916 switch (VT.SimpleTy) {
10918 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10920 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10922 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10924 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10926 if (Subtarget->hasBWI())
10927 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10930 if (Subtarget->hasBWI())
10931 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10935 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10938 // Otherwise fall back on splitting.
10939 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10942 // Lower vXi1 vector shuffles.
10943 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
10944 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
10945 // vector, shuffle and then truncate it back.
10946 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10947 MVT VT, const X86Subtarget *Subtarget,
10948 SelectionDAG &DAG) {
10950 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10951 ArrayRef<int> Mask = SVOp->getMask();
10952 assert(Subtarget->hasAVX512() &&
10953 "Cannot lower 512-bit vectors w/o basic ISA!");
10955 switch (VT.SimpleTy) {
10957 llvm_unreachable("Expected a vector of i1 elements");
10959 ExtVT = MVT::v2i64;
10962 ExtVT = MVT::v4i32;
10965 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
10968 ExtVT = MVT::v16i32;
10971 ExtVT = MVT::v32i16;
10974 ExtVT = MVT::v64i8;
10978 if (ISD::isBuildVectorAllZeros(V1.getNode()))
10979 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10980 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
10981 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10983 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
10986 V2 = DAG.getUNDEF(ExtVT);
10987 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
10988 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10989 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
10990 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10992 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
10993 return DAG.getNode(ISD::TRUNCATE, DL, VT,
10994 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
10996 /// \brief Top-level lowering for x86 vector shuffles.
10998 /// This handles decomposition, canonicalization, and lowering of all x86
10999 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11000 /// above in helper routines. The canonicalization attempts to widen shuffles
11001 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11002 /// s.t. only one of the two inputs needs to be tested, etc.
11003 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11004 SelectionDAG &DAG) {
11005 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11006 ArrayRef<int> Mask = SVOp->getMask();
11007 SDValue V1 = Op.getOperand(0);
11008 SDValue V2 = Op.getOperand(1);
11009 MVT VT = Op.getSimpleValueType();
11010 int NumElements = VT.getVectorNumElements();
11012 bool Is1BitVector = (VT.getVectorElementType() == MVT::i1);
11014 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11015 "Can't lower MMX shuffles");
11017 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11018 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11019 if (V1IsUndef && V2IsUndef)
11020 return DAG.getUNDEF(VT);
11022 // When we create a shuffle node we put the UNDEF node to second operand,
11023 // but in some cases the first operand may be transformed to UNDEF.
11024 // In this case we should just commute the node.
11026 return DAG.getCommutedVectorShuffle(*SVOp);
11028 // Check for non-undef masks pointing at an undef vector and make the masks
11029 // undef as well. This makes it easier to match the shuffle based solely on
11033 if (M >= NumElements) {
11034 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11035 for (int &M : NewMask)
11036 if (M >= NumElements)
11038 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11041 // We actually see shuffles that are entirely re-arrangements of a set of
11042 // zero inputs. This mostly happens while decomposing complex shuffles into
11043 // simple ones. Directly lower these as a buildvector of zeros.
11044 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11045 if (Zeroable.all())
11046 return getZeroVector(VT, Subtarget, DAG, dl);
11048 // Try to collapse shuffles into using a vector type with fewer elements but
11049 // wider element types. We cap this to not form integers or floating point
11050 // elements wider than 64 bits, but it might be interesting to form i128
11051 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11052 SmallVector<int, 16> WidenedMask;
11053 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11054 canWidenShuffleElements(Mask, WidenedMask)) {
11055 MVT NewEltVT = VT.isFloatingPoint()
11056 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11057 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11058 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11059 // Make sure that the new vector type is legal. For example, v2f64 isn't
11061 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11062 V1 = DAG.getBitcast(NewVT, V1);
11063 V2 = DAG.getBitcast(NewVT, V2);
11064 return DAG.getBitcast(
11065 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11069 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11070 for (int M : SVOp->getMask())
11072 ++NumUndefElements;
11073 else if (M < NumElements)
11078 // Commute the shuffle as needed such that more elements come from V1 than
11079 // V2. This allows us to match the shuffle pattern strictly on how many
11080 // elements come from V1 without handling the symmetric cases.
11081 if (NumV2Elements > NumV1Elements)
11082 return DAG.getCommutedVectorShuffle(*SVOp);
11084 // When the number of V1 and V2 elements are the same, try to minimize the
11085 // number of uses of V2 in the low half of the vector. When that is tied,
11086 // ensure that the sum of indices for V1 is equal to or lower than the sum
11087 // indices for V2. When those are equal, try to ensure that the number of odd
11088 // indices for V1 is lower than the number of odd indices for V2.
11089 if (NumV1Elements == NumV2Elements) {
11090 int LowV1Elements = 0, LowV2Elements = 0;
11091 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11092 if (M >= NumElements)
11096 if (LowV2Elements > LowV1Elements) {
11097 return DAG.getCommutedVectorShuffle(*SVOp);
11098 } else if (LowV2Elements == LowV1Elements) {
11099 int SumV1Indices = 0, SumV2Indices = 0;
11100 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11101 if (SVOp->getMask()[i] >= NumElements)
11103 else if (SVOp->getMask()[i] >= 0)
11105 if (SumV2Indices < SumV1Indices) {
11106 return DAG.getCommutedVectorShuffle(*SVOp);
11107 } else if (SumV2Indices == SumV1Indices) {
11108 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11109 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11110 if (SVOp->getMask()[i] >= NumElements)
11111 NumV2OddIndices += i % 2;
11112 else if (SVOp->getMask()[i] >= 0)
11113 NumV1OddIndices += i % 2;
11114 if (NumV2OddIndices < NumV1OddIndices)
11115 return DAG.getCommutedVectorShuffle(*SVOp);
11120 // For each vector width, delegate to a specialized lowering routine.
11121 if (VT.is128BitVector())
11122 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11124 if (VT.is256BitVector())
11125 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11127 if (VT.is512BitVector())
11128 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11131 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11132 llvm_unreachable("Unimplemented!");
11135 // This function assumes its argument is a BUILD_VECTOR of constants or
11136 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11138 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11139 unsigned &MaskValue) {
11141 unsigned NumElems = BuildVector->getNumOperands();
11143 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11144 // We don't handle the >2 lanes case right now.
11145 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11149 unsigned NumElemsInLane = NumElems / NumLanes;
11151 // Blend for v16i16 should be symmetric for the both lanes.
11152 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11153 SDValue EltCond = BuildVector->getOperand(i);
11154 SDValue SndLaneEltCond =
11155 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11157 int Lane1Cond = -1, Lane2Cond = -1;
11158 if (isa<ConstantSDNode>(EltCond))
11159 Lane1Cond = !isZero(EltCond);
11160 if (isa<ConstantSDNode>(SndLaneEltCond))
11161 Lane2Cond = !isZero(SndLaneEltCond);
11163 unsigned LaneMask = 0;
11164 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11165 // Lane1Cond != 0, means we want the first argument.
11166 // Lane1Cond == 0, means we want the second argument.
11167 // The encoding of this argument is 0 for the first argument, 1
11168 // for the second. Therefore, invert the condition.
11169 LaneMask = !Lane1Cond << i;
11170 else if (Lane1Cond < 0)
11171 LaneMask = !Lane2Cond << i;
11175 MaskValue |= LaneMask;
11177 MaskValue |= LaneMask << NumElemsInLane;
11182 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11183 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11184 const X86Subtarget *Subtarget,
11185 SelectionDAG &DAG) {
11186 SDValue Cond = Op.getOperand(0);
11187 SDValue LHS = Op.getOperand(1);
11188 SDValue RHS = Op.getOperand(2);
11190 MVT VT = Op.getSimpleValueType();
11192 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11194 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11196 // Only non-legal VSELECTs reach this lowering, convert those into generic
11197 // shuffles and re-use the shuffle lowering path for blends.
11198 SmallVector<int, 32> Mask;
11199 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11200 SDValue CondElt = CondBV->getOperand(i);
11202 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11204 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11207 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11208 // A vselect where all conditions and data are constants can be optimized into
11209 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11210 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11211 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11212 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11215 // Try to lower this to a blend-style vector shuffle. This can handle all
11216 // constant condition cases.
11217 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11220 // Variable blends are only legal from SSE4.1 onward.
11221 if (!Subtarget->hasSSE41())
11224 // Only some types will be legal on some subtargets. If we can emit a legal
11225 // VSELECT-matching blend, return Op, and but if we need to expand, return
11227 switch (Op.getSimpleValueType().SimpleTy) {
11229 // Most of the vector types have blends past SSE4.1.
11233 // The byte blends for AVX vectors were introduced only in AVX2.
11234 if (Subtarget->hasAVX2())
11241 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11242 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11245 // FIXME: We should custom lower this by fixing the condition and using i8
11251 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11252 MVT VT = Op.getSimpleValueType();
11255 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11258 if (VT.getSizeInBits() == 8) {
11259 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11260 Op.getOperand(0), Op.getOperand(1));
11261 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11262 DAG.getValueType(VT));
11263 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11266 if (VT.getSizeInBits() == 16) {
11267 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11268 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11270 return DAG.getNode(
11271 ISD::TRUNCATE, dl, MVT::i16,
11272 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11273 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11274 Op.getOperand(1)));
11275 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11276 Op.getOperand(0), Op.getOperand(1));
11277 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11278 DAG.getValueType(VT));
11279 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11282 if (VT == MVT::f32) {
11283 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11284 // the result back to FR32 register. It's only worth matching if the
11285 // result has a single use which is a store or a bitcast to i32. And in
11286 // the case of a store, it's not worth it if the index is a constant 0,
11287 // because a MOVSSmr can be used instead, which is smaller and faster.
11288 if (!Op.hasOneUse())
11290 SDNode *User = *Op.getNode()->use_begin();
11291 if ((User->getOpcode() != ISD::STORE ||
11292 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11293 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11294 (User->getOpcode() != ISD::BITCAST ||
11295 User->getValueType(0) != MVT::i32))
11297 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11298 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11300 return DAG.getBitcast(MVT::f32, Extract);
11303 if (VT == MVT::i32 || VT == MVT::i64) {
11304 // ExtractPS/pextrq works with constant index.
11305 if (isa<ConstantSDNode>(Op.getOperand(1)))
11311 /// Extract one bit from mask vector, like v16i1 or v8i1.
11312 /// AVX-512 feature.
11314 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11315 SDValue Vec = Op.getOperand(0);
11317 MVT VecVT = Vec.getSimpleValueType();
11318 SDValue Idx = Op.getOperand(1);
11319 MVT EltVT = Op.getSimpleValueType();
11321 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11322 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11323 "Unexpected vector type in ExtractBitFromMaskVector");
11325 // variable index can't be handled in mask registers,
11326 // extend vector to VR512
11327 if (!isa<ConstantSDNode>(Idx)) {
11328 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11329 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11330 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11331 ExtVT.getVectorElementType(), Ext, Idx);
11332 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11335 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11336 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11337 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11338 rc = getRegClassFor(MVT::v16i1);
11339 unsigned MaxSift = rc->getSize()*8 - 1;
11340 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11341 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11342 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11343 DAG.getConstant(MaxSift, dl, MVT::i8));
11344 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11345 DAG.getIntPtrConstant(0, dl));
11349 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11350 SelectionDAG &DAG) const {
11352 SDValue Vec = Op.getOperand(0);
11353 MVT VecVT = Vec.getSimpleValueType();
11354 SDValue Idx = Op.getOperand(1);
11356 if (Op.getSimpleValueType() == MVT::i1)
11357 return ExtractBitFromMaskVector(Op, DAG);
11359 if (!isa<ConstantSDNode>(Idx)) {
11360 if (VecVT.is512BitVector() ||
11361 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11362 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11365 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11366 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11367 MaskEltVT.getSizeInBits());
11369 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11370 auto PtrVT = getPointerTy(DAG.getDataLayout());
11371 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11372 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11373 DAG.getConstant(0, dl, PtrVT));
11374 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11375 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11376 DAG.getConstant(0, dl, PtrVT));
11381 // If this is a 256-bit vector result, first extract the 128-bit vector and
11382 // then extract the element from the 128-bit vector.
11383 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11385 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11386 // Get the 128-bit vector.
11387 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11388 MVT EltVT = VecVT.getVectorElementType();
11390 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11391 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
11393 // Find IdxVal modulo ElemsPerChunk. Since ElemsPerChunk is a power of 2
11394 // this can be done with a mask.
11395 IdxVal &= ElemsPerChunk - 1;
11396 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11397 DAG.getConstant(IdxVal, dl, MVT::i32));
11400 assert(VecVT.is128BitVector() && "Unexpected vector length");
11402 if (Subtarget->hasSSE41())
11403 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11406 MVT VT = Op.getSimpleValueType();
11407 // TODO: handle v16i8.
11408 if (VT.getSizeInBits() == 16) {
11409 SDValue Vec = Op.getOperand(0);
11410 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11412 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11413 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11414 DAG.getBitcast(MVT::v4i32, Vec),
11415 Op.getOperand(1)));
11416 // Transform it so it match pextrw which produces a 32-bit result.
11417 MVT EltVT = MVT::i32;
11418 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11419 Op.getOperand(0), Op.getOperand(1));
11420 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11421 DAG.getValueType(VT));
11422 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11425 if (VT.getSizeInBits() == 32) {
11426 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11430 // SHUFPS the element to the lowest double word, then movss.
11431 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11432 MVT VVT = Op.getOperand(0).getSimpleValueType();
11433 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11434 DAG.getUNDEF(VVT), Mask);
11435 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11436 DAG.getIntPtrConstant(0, dl));
11439 if (VT.getSizeInBits() == 64) {
11440 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11441 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11442 // to match extract_elt for f64.
11443 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11447 // UNPCKHPD the element to the lowest double word, then movsd.
11448 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11449 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11450 int Mask[2] = { 1, -1 };
11451 MVT VVT = Op.getOperand(0).getSimpleValueType();
11452 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11453 DAG.getUNDEF(VVT), Mask);
11454 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11455 DAG.getIntPtrConstant(0, dl));
11461 /// Insert one bit to mask vector, like v16i1 or v8i1.
11462 /// AVX-512 feature.
11464 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11466 SDValue Vec = Op.getOperand(0);
11467 SDValue Elt = Op.getOperand(1);
11468 SDValue Idx = Op.getOperand(2);
11469 MVT VecVT = Vec.getSimpleValueType();
11471 if (!isa<ConstantSDNode>(Idx)) {
11472 // Non constant index. Extend source and destination,
11473 // insert element and then truncate the result.
11474 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11475 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11476 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11477 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11478 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11479 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11482 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11483 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11485 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11486 DAG.getConstant(IdxVal, dl, MVT::i8));
11487 if (Vec.getOpcode() == ISD::UNDEF)
11489 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11492 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11493 SelectionDAG &DAG) const {
11494 MVT VT = Op.getSimpleValueType();
11495 MVT EltVT = VT.getVectorElementType();
11497 if (EltVT == MVT::i1)
11498 return InsertBitToMaskVector(Op, DAG);
11501 SDValue N0 = Op.getOperand(0);
11502 SDValue N1 = Op.getOperand(1);
11503 SDValue N2 = Op.getOperand(2);
11504 if (!isa<ConstantSDNode>(N2))
11506 auto *N2C = cast<ConstantSDNode>(N2);
11507 unsigned IdxVal = N2C->getZExtValue();
11509 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11510 // into that, and then insert the subvector back into the result.
11511 if (VT.is256BitVector() || VT.is512BitVector()) {
11512 // With a 256-bit vector, we can insert into the zero element efficiently
11513 // using a blend if we have AVX or AVX2 and the right data type.
11514 if (VT.is256BitVector() && IdxVal == 0) {
11515 // TODO: It is worthwhile to cast integer to floating point and back
11516 // and incur a domain crossing penalty if that's what we'll end up
11517 // doing anyway after extracting to a 128-bit vector.
11518 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11519 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11520 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11521 N2 = DAG.getIntPtrConstant(1, dl);
11522 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11526 // Get the desired 128-bit vector chunk.
11527 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11529 // Insert the element into the desired chunk.
11530 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11531 assert(isPowerOf2_32(NumEltsIn128));
11532 // Since NumEltsIn128 is a power of 2 we can use mask instead of modulo.
11533 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
11535 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11536 DAG.getConstant(IdxIn128, dl, MVT::i32));
11538 // Insert the changed part back into the bigger vector
11539 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11541 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11543 if (Subtarget->hasSSE41()) {
11544 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11546 if (VT == MVT::v8i16) {
11547 Opc = X86ISD::PINSRW;
11549 assert(VT == MVT::v16i8);
11550 Opc = X86ISD::PINSRB;
11553 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11555 if (N1.getValueType() != MVT::i32)
11556 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11557 if (N2.getValueType() != MVT::i32)
11558 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11559 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11562 if (EltVT == MVT::f32) {
11563 // Bits [7:6] of the constant are the source select. This will always be
11564 // zero here. The DAG Combiner may combine an extract_elt index into
11565 // these bits. For example (insert (extract, 3), 2) could be matched by
11566 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11567 // Bits [5:4] of the constant are the destination select. This is the
11568 // value of the incoming immediate.
11569 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11570 // combine either bitwise AND or insert of float 0.0 to set these bits.
11572 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11573 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11574 // If this is an insertion of 32-bits into the low 32-bits of
11575 // a vector, we prefer to generate a blend with immediate rather
11576 // than an insertps. Blends are simpler operations in hardware and so
11577 // will always have equal or better performance than insertps.
11578 // But if optimizing for size and there's a load folding opportunity,
11579 // generate insertps because blendps does not have a 32-bit memory
11581 N2 = DAG.getIntPtrConstant(1, dl);
11582 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11583 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11585 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11586 // Create this as a scalar to vector..
11587 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11588 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11591 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11592 // PINSR* works with constant index.
11597 if (EltVT == MVT::i8)
11600 if (EltVT.getSizeInBits() == 16) {
11601 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11602 // as its second argument.
11603 if (N1.getValueType() != MVT::i32)
11604 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11605 if (N2.getValueType() != MVT::i32)
11606 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11607 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11612 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11614 MVT OpVT = Op.getSimpleValueType();
11616 // If this is a 256-bit vector result, first insert into a 128-bit
11617 // vector and then insert into the 256-bit vector.
11618 if (!OpVT.is128BitVector()) {
11619 // Insert into a 128-bit vector.
11620 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11621 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11622 OpVT.getVectorNumElements() / SizeFactor);
11624 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11626 // Insert the 128-bit vector.
11627 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11630 if (OpVT == MVT::v1i64 &&
11631 Op.getOperand(0).getValueType() == MVT::i64)
11632 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11634 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11635 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11636 return DAG.getBitcast(
11637 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11640 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11641 // a simple subregister reference or explicit instructions to grab
11642 // upper bits of a vector.
11643 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11644 SelectionDAG &DAG) {
11646 SDValue In = Op.getOperand(0);
11647 SDValue Idx = Op.getOperand(1);
11648 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11649 MVT ResVT = Op.getSimpleValueType();
11650 MVT InVT = In.getSimpleValueType();
11652 if (Subtarget->hasFp256()) {
11653 if (ResVT.is128BitVector() &&
11654 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11655 isa<ConstantSDNode>(Idx)) {
11656 return Extract128BitVector(In, IdxVal, DAG, dl);
11658 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11659 isa<ConstantSDNode>(Idx)) {
11660 return Extract256BitVector(In, IdxVal, DAG, dl);
11666 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11667 // simple superregister reference or explicit instructions to insert
11668 // the upper bits of a vector.
11669 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11670 SelectionDAG &DAG) {
11671 if (!Subtarget->hasAVX())
11675 SDValue Vec = Op.getOperand(0);
11676 SDValue SubVec = Op.getOperand(1);
11677 SDValue Idx = Op.getOperand(2);
11679 if (!isa<ConstantSDNode>(Idx))
11682 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11683 MVT OpVT = Op.getSimpleValueType();
11684 MVT SubVecVT = SubVec.getSimpleValueType();
11686 // Fold two 16-byte subvector loads into one 32-byte load:
11687 // (insert_subvector (insert_subvector undef, (load addr), 0),
11688 // (load addr + 16), Elts/2)
11690 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11691 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11692 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11693 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11694 if (Idx2 && Idx2->getZExtValue() == 0) {
11695 SDValue SubVec2 = Vec.getOperand(1);
11696 // If needed, look through a bitcast to get to the load.
11697 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11698 SubVec2 = SubVec2.getOperand(0);
11700 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11702 unsigned Alignment = FirstLd->getAlignment();
11703 unsigned AS = FirstLd->getAddressSpace();
11704 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11705 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11706 OpVT, AS, Alignment, &Fast) && Fast) {
11707 SDValue Ops[] = { SubVec2, SubVec };
11708 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11715 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11716 SubVecVT.is128BitVector())
11717 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11719 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11720 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11722 if (OpVT.getVectorElementType() == MVT::i1) {
11723 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11725 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11726 SDValue Undef = DAG.getUNDEF(OpVT);
11727 unsigned NumElems = OpVT.getVectorNumElements();
11728 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11730 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11731 // Zero upper bits of the Vec
11732 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11733 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11735 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11737 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11738 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11741 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11743 // Zero upper bits of the Vec2
11744 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11745 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11746 // Zero lower bits of the Vec
11747 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11748 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11749 // Merge them together
11750 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11756 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11757 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11758 // one of the above mentioned nodes. It has to be wrapped because otherwise
11759 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11760 // be used to form addressing mode. These wrapped nodes will be selected
11763 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11764 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11766 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11767 // global base reg.
11768 unsigned char OpFlag = 0;
11769 unsigned WrapperKind = X86ISD::Wrapper;
11770 CodeModel::Model M = DAG.getTarget().getCodeModel();
11772 if (Subtarget->isPICStyleRIPRel() &&
11773 (M == CodeModel::Small || M == CodeModel::Kernel))
11774 WrapperKind = X86ISD::WrapperRIP;
11775 else if (Subtarget->isPICStyleGOT())
11776 OpFlag = X86II::MO_GOTOFF;
11777 else if (Subtarget->isPICStyleStubPIC())
11778 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11780 auto PtrVT = getPointerTy(DAG.getDataLayout());
11781 SDValue Result = DAG.getTargetConstantPool(
11782 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11784 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11785 // With PIC, the address is actually $g + Offset.
11788 DAG.getNode(ISD::ADD, DL, PtrVT,
11789 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11795 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11796 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11798 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11799 // global base reg.
11800 unsigned char OpFlag = 0;
11801 unsigned WrapperKind = X86ISD::Wrapper;
11802 CodeModel::Model M = DAG.getTarget().getCodeModel();
11804 if (Subtarget->isPICStyleRIPRel() &&
11805 (M == CodeModel::Small || M == CodeModel::Kernel))
11806 WrapperKind = X86ISD::WrapperRIP;
11807 else if (Subtarget->isPICStyleGOT())
11808 OpFlag = X86II::MO_GOTOFF;
11809 else if (Subtarget->isPICStyleStubPIC())
11810 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11812 auto PtrVT = getPointerTy(DAG.getDataLayout());
11813 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11815 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11817 // With PIC, the address is actually $g + Offset.
11820 DAG.getNode(ISD::ADD, DL, PtrVT,
11821 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11827 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11828 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11830 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11831 // global base reg.
11832 unsigned char OpFlag = 0;
11833 unsigned WrapperKind = X86ISD::Wrapper;
11834 CodeModel::Model M = DAG.getTarget().getCodeModel();
11836 if (Subtarget->isPICStyleRIPRel() &&
11837 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11838 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11839 OpFlag = X86II::MO_GOTPCREL;
11840 WrapperKind = X86ISD::WrapperRIP;
11841 } else if (Subtarget->isPICStyleGOT()) {
11842 OpFlag = X86II::MO_GOT;
11843 } else if (Subtarget->isPICStyleStubPIC()) {
11844 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11845 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11846 OpFlag = X86II::MO_DARWIN_NONLAZY;
11849 auto PtrVT = getPointerTy(DAG.getDataLayout());
11850 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11853 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11855 // With PIC, the address is actually $g + Offset.
11856 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11857 !Subtarget->is64Bit()) {
11859 DAG.getNode(ISD::ADD, DL, PtrVT,
11860 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11863 // For symbols that require a load from a stub to get the address, emit the
11865 if (isGlobalStubReference(OpFlag))
11866 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11867 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11868 false, false, false, 0);
11874 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11875 // Create the TargetBlockAddressAddress node.
11876 unsigned char OpFlags =
11877 Subtarget->ClassifyBlockAddressReference();
11878 CodeModel::Model M = DAG.getTarget().getCodeModel();
11879 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11880 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11882 auto PtrVT = getPointerTy(DAG.getDataLayout());
11883 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11885 if (Subtarget->isPICStyleRIPRel() &&
11886 (M == CodeModel::Small || M == CodeModel::Kernel))
11887 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11889 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11891 // With PIC, the address is actually $g + Offset.
11892 if (isGlobalRelativeToPICBase(OpFlags)) {
11893 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11894 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11901 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11902 int64_t Offset, SelectionDAG &DAG) const {
11903 // Create the TargetGlobalAddress node, folding in the constant
11904 // offset if it is legal.
11905 unsigned char OpFlags =
11906 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11907 CodeModel::Model M = DAG.getTarget().getCodeModel();
11908 auto PtrVT = getPointerTy(DAG.getDataLayout());
11910 if (OpFlags == X86II::MO_NO_FLAG &&
11911 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11912 // A direct static reference to a global.
11913 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11916 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11919 if (Subtarget->isPICStyleRIPRel() &&
11920 (M == CodeModel::Small || M == CodeModel::Kernel))
11921 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11923 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11925 // With PIC, the address is actually $g + Offset.
11926 if (isGlobalRelativeToPICBase(OpFlags)) {
11927 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11928 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11931 // For globals that require a load from a stub to get the address, emit the
11933 if (isGlobalStubReference(OpFlags))
11934 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11935 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11936 false, false, false, 0);
11938 // If there was a non-zero offset that we didn't fold, create an explicit
11939 // addition for it.
11941 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11942 DAG.getConstant(Offset, dl, PtrVT));
11948 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11949 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11950 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11951 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11955 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11956 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11957 unsigned char OperandFlags, bool LocalDynamic = false) {
11958 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11959 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11961 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11962 GA->getValueType(0),
11966 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11970 SDValue Ops[] = { Chain, TGA, *InFlag };
11971 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11973 SDValue Ops[] = { Chain, TGA };
11974 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11977 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11978 MFI->setAdjustsStack(true);
11979 MFI->setHasCalls(true);
11981 SDValue Flag = Chain.getValue(1);
11982 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11985 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11987 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11990 SDLoc dl(GA); // ? function entry point might be better
11991 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11992 DAG.getNode(X86ISD::GlobalBaseReg,
11993 SDLoc(), PtrVT), InFlag);
11994 InFlag = Chain.getValue(1);
11996 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11999 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12001 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12003 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12004 X86::RAX, X86II::MO_TLSGD);
12007 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12013 // Get the start address of the TLS block for this module.
12014 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12015 .getInfo<X86MachineFunctionInfo>();
12016 MFI->incNumLocalDynamicTLSAccesses();
12020 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12021 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12024 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12025 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12026 InFlag = Chain.getValue(1);
12027 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12028 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12031 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12035 unsigned char OperandFlags = X86II::MO_DTPOFF;
12036 unsigned WrapperKind = X86ISD::Wrapper;
12037 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12038 GA->getValueType(0),
12039 GA->getOffset(), OperandFlags);
12040 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12042 // Add x@dtpoff with the base.
12043 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12046 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12047 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12048 const EVT PtrVT, TLSModel::Model model,
12049 bool is64Bit, bool isPIC) {
12052 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12053 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12054 is64Bit ? 257 : 256));
12056 SDValue ThreadPointer =
12057 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12058 MachinePointerInfo(Ptr), false, false, false, 0);
12060 unsigned char OperandFlags = 0;
12061 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12063 unsigned WrapperKind = X86ISD::Wrapper;
12064 if (model == TLSModel::LocalExec) {
12065 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12066 } else if (model == TLSModel::InitialExec) {
12068 OperandFlags = X86II::MO_GOTTPOFF;
12069 WrapperKind = X86ISD::WrapperRIP;
12071 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12074 llvm_unreachable("Unexpected model");
12077 // emit "addl x@ntpoff,%eax" (local exec)
12078 // or "addl x@indntpoff,%eax" (initial exec)
12079 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12081 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12082 GA->getOffset(), OperandFlags);
12083 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12085 if (model == TLSModel::InitialExec) {
12086 if (isPIC && !is64Bit) {
12087 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12088 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12092 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12093 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12094 false, false, false, 0);
12097 // The address of the thread local variable is the add of the thread
12098 // pointer with the offset of the variable.
12099 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12103 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12105 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12106 const GlobalValue *GV = GA->getGlobal();
12107 auto PtrVT = getPointerTy(DAG.getDataLayout());
12109 if (Subtarget->isTargetELF()) {
12110 if (DAG.getTarget().Options.EmulatedTLS)
12111 return LowerToTLSEmulatedModel(GA, DAG);
12112 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12114 case TLSModel::GeneralDynamic:
12115 if (Subtarget->is64Bit())
12116 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12117 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12118 case TLSModel::LocalDynamic:
12119 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12120 Subtarget->is64Bit());
12121 case TLSModel::InitialExec:
12122 case TLSModel::LocalExec:
12123 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12124 DAG.getTarget().getRelocationModel() ==
12127 llvm_unreachable("Unknown TLS model.");
12130 if (Subtarget->isTargetDarwin()) {
12131 // Darwin only has one model of TLS. Lower to that.
12132 unsigned char OpFlag = 0;
12133 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12134 X86ISD::WrapperRIP : X86ISD::Wrapper;
12136 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12137 // global base reg.
12138 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12139 !Subtarget->is64Bit();
12141 OpFlag = X86II::MO_TLVP_PIC_BASE;
12143 OpFlag = X86II::MO_TLVP;
12145 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12146 GA->getValueType(0),
12147 GA->getOffset(), OpFlag);
12148 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12150 // With PIC32, the address is actually $g + Offset.
12152 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12153 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12156 // Lowering the machine isd will make sure everything is in the right
12158 SDValue Chain = DAG.getEntryNode();
12159 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12160 SDValue Args[] = { Chain, Offset };
12161 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12163 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12164 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12165 MFI->setAdjustsStack(true);
12167 // And our return value (tls address) is in the standard call return value
12169 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12170 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12173 if (Subtarget->isTargetKnownWindowsMSVC() ||
12174 Subtarget->isTargetWindowsGNU()) {
12175 // Just use the implicit TLS architecture
12176 // Need to generate someting similar to:
12177 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12179 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12180 // mov rcx, qword [rdx+rcx*8]
12181 // mov eax, .tls$:tlsvar
12182 // [rax+rcx] contains the address
12183 // Windows 64bit: gs:0x58
12184 // Windows 32bit: fs:__tls_array
12187 SDValue Chain = DAG.getEntryNode();
12189 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12190 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12191 // use its literal value of 0x2C.
12192 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12193 ? Type::getInt8PtrTy(*DAG.getContext(),
12195 : Type::getInt32PtrTy(*DAG.getContext(),
12198 SDValue TlsArray = Subtarget->is64Bit()
12199 ? DAG.getIntPtrConstant(0x58, dl)
12200 : (Subtarget->isTargetWindowsGNU()
12201 ? DAG.getIntPtrConstant(0x2C, dl)
12202 : DAG.getExternalSymbol("_tls_array", PtrVT));
12204 SDValue ThreadPointer =
12205 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12209 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12210 res = ThreadPointer;
12212 // Load the _tls_index variable
12213 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12214 if (Subtarget->is64Bit())
12215 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12216 MachinePointerInfo(), MVT::i32, false, false,
12219 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12222 auto &DL = DAG.getDataLayout();
12224 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12225 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12227 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12230 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12233 // Get the offset of start of .tls section
12234 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12235 GA->getValueType(0),
12236 GA->getOffset(), X86II::MO_SECREL);
12237 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12239 // The address of the thread local variable is the add of the thread
12240 // pointer with the offset of the variable.
12241 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12244 llvm_unreachable("TLS not implemented for this target.");
12247 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12248 /// and take a 2 x i32 value to shift plus a shift amount.
12249 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12250 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12251 MVT VT = Op.getSimpleValueType();
12252 unsigned VTBits = VT.getSizeInBits();
12254 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12255 SDValue ShOpLo = Op.getOperand(0);
12256 SDValue ShOpHi = Op.getOperand(1);
12257 SDValue ShAmt = Op.getOperand(2);
12258 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12259 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12261 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12262 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12263 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12264 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12265 : DAG.getConstant(0, dl, VT);
12267 SDValue Tmp2, Tmp3;
12268 if (Op.getOpcode() == ISD::SHL_PARTS) {
12269 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12270 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12272 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12273 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12276 // If the shift amount is larger or equal than the width of a part we can't
12277 // rely on the results of shld/shrd. Insert a test and select the appropriate
12278 // values for large shift amounts.
12279 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12280 DAG.getConstant(VTBits, dl, MVT::i8));
12281 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12282 AndNode, DAG.getConstant(0, dl, MVT::i8));
12285 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12286 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12287 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12289 if (Op.getOpcode() == ISD::SHL_PARTS) {
12290 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12291 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12293 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12294 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12297 SDValue Ops[2] = { Lo, Hi };
12298 return DAG.getMergeValues(Ops, dl);
12301 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12302 SelectionDAG &DAG) const {
12303 SDValue Src = Op.getOperand(0);
12304 MVT SrcVT = Src.getSimpleValueType();
12305 MVT VT = Op.getSimpleValueType();
12308 if (SrcVT.isVector()) {
12309 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12310 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12311 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12312 DAG.getUNDEF(SrcVT)));
12314 if (SrcVT.getVectorElementType() == MVT::i1) {
12315 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12316 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12317 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12322 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12323 "Unknown SINT_TO_FP to lower!");
12325 // These are really Legal; return the operand so the caller accepts it as
12327 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12329 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12330 Subtarget->is64Bit()) {
12334 unsigned Size = SrcVT.getSizeInBits()/8;
12335 MachineFunction &MF = DAG.getMachineFunction();
12336 auto PtrVT = getPointerTy(MF.getDataLayout());
12337 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12338 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12339 SDValue Chain = DAG.getStore(
12340 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12341 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12343 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12346 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12348 SelectionDAG &DAG) const {
12352 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12354 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12356 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12358 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12360 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12361 MachineMemOperand *MMO;
12363 int SSFI = FI->getIndex();
12364 MMO = DAG.getMachineFunction().getMachineMemOperand(
12365 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12366 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12368 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12369 StackSlot = StackSlot.getOperand(1);
12371 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12372 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12374 Tys, Ops, SrcVT, MMO);
12377 Chain = Result.getValue(1);
12378 SDValue InFlag = Result.getValue(2);
12380 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12381 // shouldn't be necessary except that RFP cannot be live across
12382 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12383 MachineFunction &MF = DAG.getMachineFunction();
12384 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12385 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12386 auto PtrVT = getPointerTy(MF.getDataLayout());
12387 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12388 Tys = DAG.getVTList(MVT::Other);
12390 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12392 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12393 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12394 MachineMemOperand::MOStore, SSFISize, SSFISize);
12396 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12397 Ops, Op.getValueType(), MMO);
12398 Result = DAG.getLoad(
12399 Op.getValueType(), DL, Chain, StackSlot,
12400 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12401 false, false, false, 0);
12407 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12408 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12409 SelectionDAG &DAG) const {
12410 // This algorithm is not obvious. Here it is what we're trying to output:
12413 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12414 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12416 haddpd %xmm0, %xmm0
12418 pshufd $0x4e, %xmm0, %xmm1
12424 LLVMContext *Context = DAG.getContext();
12426 // Build some magic constants.
12427 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12428 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12429 auto PtrVT = getPointerTy(DAG.getDataLayout());
12430 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12432 SmallVector<Constant*,2> CV1;
12434 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12435 APInt(64, 0x4330000000000000ULL))));
12437 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12438 APInt(64, 0x4530000000000000ULL))));
12439 Constant *C1 = ConstantVector::get(CV1);
12440 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12442 // Load the 64-bit value into an XMM register.
12443 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12446 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12447 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12448 false, false, false, 16);
12450 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12453 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12454 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12455 false, false, false, 16);
12456 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12457 // TODO: Are there any fast-math-flags to propagate here?
12458 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12461 if (Subtarget->hasSSE3()) {
12462 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12463 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12465 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12466 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12468 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12469 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12472 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12473 DAG.getIntPtrConstant(0, dl));
12476 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12477 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12478 SelectionDAG &DAG) const {
12480 // FP constant to bias correct the final result.
12481 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12484 // Load the 32-bit value into an XMM register.
12485 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12488 // Zero out the upper parts of the register.
12489 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12491 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12492 DAG.getBitcast(MVT::v2f64, Load),
12493 DAG.getIntPtrConstant(0, dl));
12495 // Or the load with the bias.
12496 SDValue Or = DAG.getNode(
12497 ISD::OR, dl, MVT::v2i64,
12498 DAG.getBitcast(MVT::v2i64,
12499 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12500 DAG.getBitcast(MVT::v2i64,
12501 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12503 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12504 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12506 // Subtract the bias.
12507 // TODO: Are there any fast-math-flags to propagate here?
12508 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12510 // Handle final rounding.
12511 MVT DestVT = Op.getSimpleValueType();
12513 if (DestVT.bitsLT(MVT::f64))
12514 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12515 DAG.getIntPtrConstant(0, dl));
12516 if (DestVT.bitsGT(MVT::f64))
12517 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12519 // Handle final rounding.
12523 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12524 const X86Subtarget &Subtarget) {
12525 // The algorithm is the following:
12526 // #ifdef __SSE4_1__
12527 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12528 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12529 // (uint4) 0x53000000, 0xaa);
12531 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12532 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12534 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12535 // return (float4) lo + fhi;
12537 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12538 // reassociate the two FADDs, and if we do that, the algorithm fails
12539 // spectacularly (PR24512).
12540 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12541 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12542 // there's also the MachineCombiner reassociations happening on Machine IR.
12543 if (DAG.getTarget().Options.UnsafeFPMath)
12547 SDValue V = Op->getOperand(0);
12548 MVT VecIntVT = V.getSimpleValueType();
12549 bool Is128 = VecIntVT == MVT::v4i32;
12550 MVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12551 // If we convert to something else than the supported type, e.g., to v4f64,
12553 if (VecFloatVT != Op->getSimpleValueType(0))
12556 unsigned NumElts = VecIntVT.getVectorNumElements();
12557 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12558 "Unsupported custom type");
12559 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12561 // In the #idef/#else code, we have in common:
12562 // - The vector of constants:
12568 // Create the splat vector for 0x4b000000.
12569 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12570 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12571 CstLow, CstLow, CstLow, CstLow};
12572 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12573 makeArrayRef(&CstLowArray[0], NumElts));
12574 // Create the splat vector for 0x53000000.
12575 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12576 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12577 CstHigh, CstHigh, CstHigh, CstHigh};
12578 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12579 makeArrayRef(&CstHighArray[0], NumElts));
12581 // Create the right shift.
12582 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12583 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12584 CstShift, CstShift, CstShift, CstShift};
12585 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12586 makeArrayRef(&CstShiftArray[0], NumElts));
12587 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12590 if (Subtarget.hasSSE41()) {
12591 MVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12592 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12593 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12594 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12595 // Low will be bitcasted right away, so do not bother bitcasting back to its
12597 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12598 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12599 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12600 // (uint4) 0x53000000, 0xaa);
12601 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12602 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12603 // High will be bitcasted right away, so do not bother bitcasting back to
12604 // its original type.
12605 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12606 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12608 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12609 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12610 CstMask, CstMask, CstMask);
12611 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12612 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12613 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12615 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12616 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12619 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12620 SDValue CstFAdd = DAG.getConstantFP(
12621 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12622 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12623 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12624 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12625 makeArrayRef(&CstFAddArray[0], NumElts));
12627 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12628 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12629 // TODO: Are there any fast-math-flags to propagate here?
12631 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12632 // return (float4) lo + fhi;
12633 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12634 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12637 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12638 SelectionDAG &DAG) const {
12639 SDValue N0 = Op.getOperand(0);
12640 MVT SVT = N0.getSimpleValueType();
12643 switch (SVT.SimpleTy) {
12645 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12650 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12651 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12652 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12656 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12659 assert(Subtarget->hasAVX512());
12660 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12661 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12665 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12666 SelectionDAG &DAG) const {
12667 SDValue N0 = Op.getOperand(0);
12669 auto PtrVT = getPointerTy(DAG.getDataLayout());
12671 if (Op.getSimpleValueType().isVector())
12672 return lowerUINT_TO_FP_vec(Op, DAG);
12674 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12675 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12676 // the optimization here.
12677 if (DAG.SignBitIsZero(N0))
12678 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12680 MVT SrcVT = N0.getSimpleValueType();
12681 MVT DstVT = Op.getSimpleValueType();
12683 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12684 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12685 // Conversions from unsigned i32 to f32/f64 are legal,
12686 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12690 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12691 return LowerUINT_TO_FP_i64(Op, DAG);
12692 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12693 return LowerUINT_TO_FP_i32(Op, DAG);
12694 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12697 // Make a 64-bit buffer, and use it to build an FILD.
12698 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12699 if (SrcVT == MVT::i32) {
12700 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12701 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12702 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12703 StackSlot, MachinePointerInfo(),
12705 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12706 OffsetSlot, MachinePointerInfo(),
12708 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12712 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12713 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12714 StackSlot, MachinePointerInfo(),
12716 // For i64 source, we need to add the appropriate power of 2 if the input
12717 // was negative. This is the same as the optimization in
12718 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12719 // we must be careful to do the computation in x87 extended precision, not
12720 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12721 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12722 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12723 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12724 MachineMemOperand::MOLoad, 8, 8);
12726 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12727 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12728 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12731 APInt FF(32, 0x5F800000ULL);
12733 // Check whether the sign bit is set.
12734 SDValue SignSet = DAG.getSetCC(
12735 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12736 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12738 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12739 SDValue FudgePtr = DAG.getConstantPool(
12740 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12742 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12743 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12744 SDValue Four = DAG.getIntPtrConstant(4, dl);
12745 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12747 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12749 // Load the value out, extending it from f32 to f80.
12750 // FIXME: Avoid the extend by constructing the right constant pool?
12751 SDValue Fudge = DAG.getExtLoad(
12752 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12753 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12754 false, false, false, 4);
12755 // Extend everything to 80 bits to force it to be done on x87.
12756 // TODO: Are there any fast-math-flags to propagate here?
12757 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12758 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12759 DAG.getIntPtrConstant(0, dl));
12762 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12763 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
12764 // just return an <SDValue(), SDValue()> pair.
12765 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12766 // to i16, i32 or i64, and we lower it to a legal sequence.
12767 // If lowered to the final integer result we return a <result, SDValue()> pair.
12768 // Otherwise we lower it to a sequence ending with a FIST, return a
12769 // <FIST, StackSlot> pair, and the caller is responsible for loading
12770 // the final integer result from StackSlot.
12771 std::pair<SDValue,SDValue>
12772 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12773 bool IsSigned, bool IsReplace) const {
12776 EVT DstTy = Op.getValueType();
12777 EVT TheVT = Op.getOperand(0).getValueType();
12778 auto PtrVT = getPointerTy(DAG.getDataLayout());
12780 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
12781 // f16 must be promoted before using the lowering in this routine.
12782 // fp128 does not use this lowering.
12783 return std::make_pair(SDValue(), SDValue());
12786 // If using FIST to compute an unsigned i64, we'll need some fixup
12787 // to handle values above the maximum signed i64. A FIST is always
12788 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12789 bool UnsignedFixup = !IsSigned &&
12790 DstTy == MVT::i64 &&
12791 (!Subtarget->is64Bit() ||
12792 !isScalarFPTypeInSSEReg(TheVT));
12794 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12795 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12796 // The low 32 bits of the fist result will have the correct uint32 result.
12797 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12801 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12802 DstTy.getSimpleVT() >= MVT::i16 &&
12803 "Unknown FP_TO_INT to lower!");
12805 // These are really Legal.
12806 if (DstTy == MVT::i32 &&
12807 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12808 return std::make_pair(SDValue(), SDValue());
12809 if (Subtarget->is64Bit() &&
12810 DstTy == MVT::i64 &&
12811 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12812 return std::make_pair(SDValue(), SDValue());
12814 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12816 MachineFunction &MF = DAG.getMachineFunction();
12817 unsigned MemSize = DstTy.getSizeInBits()/8;
12818 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12819 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12822 switch (DstTy.getSimpleVT().SimpleTy) {
12823 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12824 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12825 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12826 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12829 SDValue Chain = DAG.getEntryNode();
12830 SDValue Value = Op.getOperand(0);
12831 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12833 if (UnsignedFixup) {
12835 // Conversion to unsigned i64 is implemented with a select,
12836 // depending on whether the source value fits in the range
12837 // of a signed i64. Let Thresh be the FP equivalent of
12838 // 0x8000000000000000ULL.
12840 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12841 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12842 // Fist-to-mem64 FistSrc
12843 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12844 // to XOR'ing the high 32 bits with Adjust.
12846 // Being a power of 2, Thresh is exactly representable in all FP formats.
12847 // For X87 we'd like to use the smallest FP type for this constant, but
12848 // for DAG type consistency we have to match the FP operand type.
12850 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12851 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12852 bool LosesInfo = false;
12853 if (TheVT == MVT::f64)
12854 // The rounding mode is irrelevant as the conversion should be exact.
12855 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12857 else if (TheVT == MVT::f80)
12858 Status = Thresh.convert(APFloat::x87DoubleExtended,
12859 APFloat::rmNearestTiesToEven, &LosesInfo);
12861 assert(Status == APFloat::opOK && !LosesInfo &&
12862 "FP conversion should have been exact");
12864 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12866 SDValue Cmp = DAG.getSetCC(DL,
12867 getSetCCResultType(DAG.getDataLayout(),
12868 *DAG.getContext(), TheVT),
12869 Value, ThreshVal, ISD::SETLT);
12870 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12871 DAG.getConstant(0, DL, MVT::i32),
12872 DAG.getConstant(0x80000000, DL, MVT::i32));
12873 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12874 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12875 *DAG.getContext(), TheVT),
12876 Value, ThreshVal, ISD::SETLT);
12877 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12880 // FIXME This causes a redundant load/store if the SSE-class value is already
12881 // in memory, such as if it is on the callstack.
12882 if (isScalarFPTypeInSSEReg(TheVT)) {
12883 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12884 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12885 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12887 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12889 Chain, StackSlot, DAG.getValueType(TheVT)
12892 MachineMemOperand *MMO =
12893 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12894 MachineMemOperand::MOLoad, MemSize, MemSize);
12895 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12896 Chain = Value.getValue(1);
12897 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12898 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12901 MachineMemOperand *MMO =
12902 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12903 MachineMemOperand::MOStore, MemSize, MemSize);
12905 if (UnsignedFixup) {
12907 // Insert the FIST, load its result as two i32's,
12908 // and XOR the high i32 with Adjust.
12910 SDValue FistOps[] = { Chain, Value, StackSlot };
12911 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12912 FistOps, DstTy, MMO);
12914 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
12915 MachinePointerInfo(),
12916 false, false, false, 0);
12917 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
12918 DAG.getConstant(4, DL, PtrVT));
12920 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
12921 MachinePointerInfo(),
12922 false, false, false, 0);
12923 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
12925 if (Subtarget->is64Bit()) {
12926 // Join High32 and Low32 into a 64-bit result.
12927 // (High32 << 32) | Low32
12928 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
12929 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
12930 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
12931 DAG.getConstant(32, DL, MVT::i8));
12932 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
12933 return std::make_pair(Result, SDValue());
12936 SDValue ResultOps[] = { Low32, High32 };
12938 SDValue pair = IsReplace
12939 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
12940 : DAG.getMergeValues(ResultOps, DL);
12941 return std::make_pair(pair, SDValue());
12943 // Build the FP_TO_INT*_IN_MEM
12944 SDValue Ops[] = { Chain, Value, StackSlot };
12945 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12947 return std::make_pair(FIST, StackSlot);
12951 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12952 const X86Subtarget *Subtarget) {
12953 MVT VT = Op->getSimpleValueType(0);
12954 SDValue In = Op->getOperand(0);
12955 MVT InVT = In.getSimpleValueType();
12958 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
12959 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12961 // Optimize vectors in AVX mode:
12964 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12965 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12966 // Concat upper and lower parts.
12969 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12970 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12971 // Concat upper and lower parts.
12974 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12975 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12976 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12979 if (Subtarget->hasInt256())
12980 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12982 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12983 SDValue Undef = DAG.getUNDEF(InVT);
12984 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12985 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12986 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12988 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12989 VT.getVectorNumElements()/2);
12991 OpLo = DAG.getBitcast(HVT, OpLo);
12992 OpHi = DAG.getBitcast(HVT, OpHi);
12994 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12997 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12998 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12999 MVT VT = Op->getSimpleValueType(0);
13000 SDValue In = Op->getOperand(0);
13001 MVT InVT = In.getSimpleValueType();
13003 unsigned int NumElts = VT.getVectorNumElements();
13004 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13007 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13008 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13010 assert(InVT.getVectorElementType() == MVT::i1);
13011 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13013 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13015 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13017 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13018 if (VT.is512BitVector())
13020 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13023 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13024 SelectionDAG &DAG) {
13025 if (Subtarget->hasFp256())
13026 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13032 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13033 SelectionDAG &DAG) {
13035 MVT VT = Op.getSimpleValueType();
13036 SDValue In = Op.getOperand(0);
13037 MVT SVT = In.getSimpleValueType();
13039 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13040 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13042 if (Subtarget->hasFp256())
13043 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13046 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13047 VT.getVectorNumElements() != SVT.getVectorNumElements());
13051 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13053 MVT VT = Op.getSimpleValueType();
13054 SDValue In = Op.getOperand(0);
13055 MVT InVT = In.getSimpleValueType();
13057 if (VT == MVT::i1) {
13058 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13059 "Invalid scalar TRUNCATE operation");
13060 if (InVT.getSizeInBits() >= 32)
13062 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13063 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13065 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13066 "Invalid TRUNCATE operation");
13068 // move vector to mask - truncate solution for SKX
13069 if (VT.getVectorElementType() == MVT::i1) {
13070 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13071 Subtarget->hasBWI())
13072 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13073 if ((InVT.is256BitVector() || InVT.is128BitVector())
13074 && InVT.getScalarSizeInBits() <= 16 &&
13075 Subtarget->hasBWI() && Subtarget->hasVLX())
13076 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13077 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13078 Subtarget->hasDQI())
13079 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13080 if ((InVT.is256BitVector() || InVT.is128BitVector())
13081 && InVT.getScalarSizeInBits() >= 32 &&
13082 Subtarget->hasDQI() && Subtarget->hasVLX())
13083 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13086 if (VT.getVectorElementType() == MVT::i1) {
13087 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13088 unsigned NumElts = InVT.getVectorNumElements();
13089 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13090 if (InVT.getSizeInBits() < 512) {
13091 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13092 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13097 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13098 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13099 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13102 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13103 if (Subtarget->hasAVX512()) {
13104 // word to byte only under BWI
13105 if (InVT == MVT::v16i16 && !Subtarget->hasBWI()) // v16i16 -> v16i8
13106 return DAG.getNode(X86ISD::VTRUNC, DL, VT,
13107 DAG.getNode(X86ISD::VSEXT, DL, MVT::v16i32, In));
13108 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13110 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13111 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13112 if (Subtarget->hasInt256()) {
13113 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13114 In = DAG.getBitcast(MVT::v8i32, In);
13115 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13117 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13118 DAG.getIntPtrConstant(0, DL));
13121 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13122 DAG.getIntPtrConstant(0, DL));
13123 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13124 DAG.getIntPtrConstant(2, DL));
13125 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13126 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13127 static const int ShufMask[] = {0, 2, 4, 6};
13128 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13131 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13132 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13133 if (Subtarget->hasInt256()) {
13134 In = DAG.getBitcast(MVT::v32i8, In);
13136 SmallVector<SDValue,32> pshufbMask;
13137 for (unsigned i = 0; i < 2; ++i) {
13138 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13139 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13140 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13141 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13142 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13143 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13144 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13145 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13146 for (unsigned j = 0; j < 8; ++j)
13147 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13149 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13150 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13151 In = DAG.getBitcast(MVT::v4i64, In);
13153 static const int ShufMask[] = {0, 2, -1, -1};
13154 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13156 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13157 DAG.getIntPtrConstant(0, DL));
13158 return DAG.getBitcast(VT, In);
13161 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13162 DAG.getIntPtrConstant(0, DL));
13164 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13165 DAG.getIntPtrConstant(4, DL));
13167 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13168 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13170 // The PSHUFB mask:
13171 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13172 -1, -1, -1, -1, -1, -1, -1, -1};
13174 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13175 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13176 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13178 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13179 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13181 // The MOVLHPS Mask:
13182 static const int ShufMask2[] = {0, 1, 4, 5};
13183 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13184 return DAG.getBitcast(MVT::v8i16, res);
13187 // Handle truncation of V256 to V128 using shuffles.
13188 if (!VT.is128BitVector() || !InVT.is256BitVector())
13191 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13193 unsigned NumElems = VT.getVectorNumElements();
13194 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13196 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13197 // Prepare truncation shuffle mask
13198 for (unsigned i = 0; i != NumElems; ++i)
13199 MaskVec[i] = i * 2;
13200 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13201 DAG.getUNDEF(NVT), &MaskVec[0]);
13202 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13203 DAG.getIntPtrConstant(0, DL));
13206 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13207 SelectionDAG &DAG) const {
13208 assert(!Op.getSimpleValueType().isVector());
13210 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13211 /*IsSigned=*/ true, /*IsReplace=*/ false);
13212 SDValue FIST = Vals.first, StackSlot = Vals.second;
13213 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13214 if (!FIST.getNode())
13217 if (StackSlot.getNode())
13218 // Load the result.
13219 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13220 FIST, StackSlot, MachinePointerInfo(),
13221 false, false, false, 0);
13223 // The node is the result.
13227 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13228 SelectionDAG &DAG) const {
13229 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13230 /*IsSigned=*/ false, /*IsReplace=*/ false);
13231 SDValue FIST = Vals.first, StackSlot = Vals.second;
13232 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13233 if (!FIST.getNode())
13236 if (StackSlot.getNode())
13237 // Load the result.
13238 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13239 FIST, StackSlot, MachinePointerInfo(),
13240 false, false, false, 0);
13242 // The node is the result.
13246 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13248 MVT VT = Op.getSimpleValueType();
13249 SDValue In = Op.getOperand(0);
13250 MVT SVT = In.getSimpleValueType();
13252 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13254 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13255 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13256 In, DAG.getUNDEF(SVT)));
13259 /// The only differences between FABS and FNEG are the mask and the logic op.
13260 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13261 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13262 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13263 "Wrong opcode for lowering FABS or FNEG.");
13265 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13267 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13268 // into an FNABS. We'll lower the FABS after that if it is still in use.
13270 for (SDNode *User : Op->uses())
13271 if (User->getOpcode() == ISD::FNEG)
13275 MVT VT = Op.getSimpleValueType();
13277 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13278 // decide if we should generate a 16-byte constant mask when we only need 4 or
13279 // 8 bytes for the scalar case.
13285 if (VT.isVector()) {
13287 EltVT = VT.getVectorElementType();
13288 NumElts = VT.getVectorNumElements();
13290 // There are no scalar bitwise logical SSE/AVX instructions, so we
13291 // generate a 16-byte vector constant and logic op even for the scalar case.
13292 // Using a 16-byte mask allows folding the load of the mask with
13293 // the logic op, so it can save (~4 bytes) on code size.
13294 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13296 NumElts = (VT == MVT::f64) ? 2 : 4;
13299 unsigned EltBits = EltVT.getSizeInBits();
13300 LLVMContext *Context = DAG.getContext();
13301 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13303 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13304 Constant *C = ConstantInt::get(*Context, MaskElt);
13305 C = ConstantVector::getSplat(NumElts, C);
13306 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13307 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13308 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13310 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13311 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13312 false, false, false, Alignment);
13314 SDValue Op0 = Op.getOperand(0);
13315 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13317 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13318 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13321 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13323 // For the scalar case extend to a 128-bit vector, perform the logic op,
13324 // and extract the scalar result back out.
13325 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13326 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13327 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13328 DAG.getIntPtrConstant(0, dl));
13331 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13332 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13333 LLVMContext *Context = DAG.getContext();
13334 SDValue Op0 = Op.getOperand(0);
13335 SDValue Op1 = Op.getOperand(1);
13337 MVT VT = Op.getSimpleValueType();
13338 MVT SrcVT = Op1.getSimpleValueType();
13340 // If second operand is smaller, extend it first.
13341 if (SrcVT.bitsLT(VT)) {
13342 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13345 // And if it is bigger, shrink it first.
13346 if (SrcVT.bitsGT(VT)) {
13347 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13351 // At this point the operands and the result should have the same
13352 // type, and that won't be f80 since that is not custom lowered.
13354 const fltSemantics &Sem =
13355 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13356 const unsigned SizeInBits = VT.getSizeInBits();
13358 SmallVector<Constant *, 4> CV(
13359 VT == MVT::f64 ? 2 : 4,
13360 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13362 // First, clear all bits but the sign bit from the second operand (sign).
13363 CV[0] = ConstantFP::get(*Context,
13364 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13365 Constant *C = ConstantVector::get(CV);
13366 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13367 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13369 // Perform all logic operations as 16-byte vectors because there are no
13370 // scalar FP logic instructions in SSE. This allows load folding of the
13371 // constants into the logic instructions.
13372 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13374 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13375 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13376 false, false, false, 16);
13377 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13378 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13380 // Next, clear the sign bit from the first operand (magnitude).
13381 // If it's a constant, we can clear it here.
13382 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13383 APFloat APF = Op0CN->getValueAPF();
13384 // If the magnitude is a positive zero, the sign bit alone is enough.
13385 if (APF.isPosZero())
13386 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13387 DAG.getIntPtrConstant(0, dl));
13389 CV[0] = ConstantFP::get(*Context, APF);
13391 CV[0] = ConstantFP::get(
13393 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13395 C = ConstantVector::get(CV);
13396 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13398 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13399 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13400 false, false, false, 16);
13401 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13402 if (!isa<ConstantFPSDNode>(Op0)) {
13403 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13404 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13406 // OR the magnitude value with the sign bit.
13407 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13408 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13409 DAG.getIntPtrConstant(0, dl));
13412 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13413 SDValue N0 = Op.getOperand(0);
13415 MVT VT = Op.getSimpleValueType();
13417 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13418 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13419 DAG.getConstant(1, dl, VT));
13420 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13423 // Check whether an OR'd tree is PTEST-able.
13424 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13425 SelectionDAG &DAG) {
13426 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13428 if (!Subtarget->hasSSE41())
13431 if (!Op->hasOneUse())
13434 SDNode *N = Op.getNode();
13437 SmallVector<SDValue, 8> Opnds;
13438 DenseMap<SDValue, unsigned> VecInMap;
13439 SmallVector<SDValue, 8> VecIns;
13440 EVT VT = MVT::Other;
13442 // Recognize a special case where a vector is casted into wide integer to
13444 Opnds.push_back(N->getOperand(0));
13445 Opnds.push_back(N->getOperand(1));
13447 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13448 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13449 // BFS traverse all OR'd operands.
13450 if (I->getOpcode() == ISD::OR) {
13451 Opnds.push_back(I->getOperand(0));
13452 Opnds.push_back(I->getOperand(1));
13453 // Re-evaluate the number of nodes to be traversed.
13454 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13458 // Quit if a non-EXTRACT_VECTOR_ELT
13459 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13462 // Quit if without a constant index.
13463 SDValue Idx = I->getOperand(1);
13464 if (!isa<ConstantSDNode>(Idx))
13467 SDValue ExtractedFromVec = I->getOperand(0);
13468 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13469 if (M == VecInMap.end()) {
13470 VT = ExtractedFromVec.getValueType();
13471 // Quit if not 128/256-bit vector.
13472 if (!VT.is128BitVector() && !VT.is256BitVector())
13474 // Quit if not the same type.
13475 if (VecInMap.begin() != VecInMap.end() &&
13476 VT != VecInMap.begin()->first.getValueType())
13478 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13479 VecIns.push_back(ExtractedFromVec);
13481 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13484 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13485 "Not extracted from 128-/256-bit vector.");
13487 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13489 for (DenseMap<SDValue, unsigned>::const_iterator
13490 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13491 // Quit if not all elements are used.
13492 if (I->second != FullMask)
13496 MVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13498 // Cast all vectors into TestVT for PTEST.
13499 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13500 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13502 // If more than one full vectors are evaluated, OR them first before PTEST.
13503 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13504 // Each iteration will OR 2 nodes and append the result until there is only
13505 // 1 node left, i.e. the final OR'd value of all vectors.
13506 SDValue LHS = VecIns[Slot];
13507 SDValue RHS = VecIns[Slot + 1];
13508 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13511 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13512 VecIns.back(), VecIns.back());
13515 /// \brief return true if \c Op has a use that doesn't just read flags.
13516 static bool hasNonFlagsUse(SDValue Op) {
13517 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13519 SDNode *User = *UI;
13520 unsigned UOpNo = UI.getOperandNo();
13521 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13522 // Look pass truncate.
13523 UOpNo = User->use_begin().getOperandNo();
13524 User = *User->use_begin();
13527 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13528 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13534 /// Emit nodes that will be selected as "test Op0,Op0", or something
13536 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13537 SelectionDAG &DAG) const {
13538 if (Op.getValueType() == MVT::i1) {
13539 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13540 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13541 DAG.getConstant(0, dl, MVT::i8));
13543 // CF and OF aren't always set the way we want. Determine which
13544 // of these we need.
13545 bool NeedCF = false;
13546 bool NeedOF = false;
13549 case X86::COND_A: case X86::COND_AE:
13550 case X86::COND_B: case X86::COND_BE:
13553 case X86::COND_G: case X86::COND_GE:
13554 case X86::COND_L: case X86::COND_LE:
13555 case X86::COND_O: case X86::COND_NO: {
13556 // Check if we really need to set the
13557 // Overflow flag. If NoSignedWrap is present
13558 // that is not actually needed.
13559 switch (Op->getOpcode()) {
13564 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13565 if (BinNode->Flags.hasNoSignedWrap())
13575 // See if we can use the EFLAGS value from the operand instead of
13576 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13577 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13578 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13579 // Emit a CMP with 0, which is the TEST pattern.
13580 //if (Op.getValueType() == MVT::i1)
13581 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13582 // DAG.getConstant(0, MVT::i1));
13583 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13584 DAG.getConstant(0, dl, Op.getValueType()));
13586 unsigned Opcode = 0;
13587 unsigned NumOperands = 0;
13589 // Truncate operations may prevent the merge of the SETCC instruction
13590 // and the arithmetic instruction before it. Attempt to truncate the operands
13591 // of the arithmetic instruction and use a reduced bit-width instruction.
13592 bool NeedTruncation = false;
13593 SDValue ArithOp = Op;
13594 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13595 SDValue Arith = Op->getOperand(0);
13596 // Both the trunc and the arithmetic op need to have one user each.
13597 if (Arith->hasOneUse())
13598 switch (Arith.getOpcode()) {
13605 NeedTruncation = true;
13611 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13612 // which may be the result of a CAST. We use the variable 'Op', which is the
13613 // non-casted variable when we check for possible users.
13614 switch (ArithOp.getOpcode()) {
13616 // Due to an isel shortcoming, be conservative if this add is likely to be
13617 // selected as part of a load-modify-store instruction. When the root node
13618 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13619 // uses of other nodes in the match, such as the ADD in this case. This
13620 // leads to the ADD being left around and reselected, with the result being
13621 // two adds in the output. Alas, even if none our users are stores, that
13622 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13623 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13624 // climbing the DAG back to the root, and it doesn't seem to be worth the
13626 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13627 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13628 if (UI->getOpcode() != ISD::CopyToReg &&
13629 UI->getOpcode() != ISD::SETCC &&
13630 UI->getOpcode() != ISD::STORE)
13633 if (ConstantSDNode *C =
13634 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13635 // An add of one will be selected as an INC.
13636 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13637 Opcode = X86ISD::INC;
13642 // An add of negative one (subtract of one) will be selected as a DEC.
13643 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13644 Opcode = X86ISD::DEC;
13650 // Otherwise use a regular EFLAGS-setting add.
13651 Opcode = X86ISD::ADD;
13656 // If we have a constant logical shift that's only used in a comparison
13657 // against zero turn it into an equivalent AND. This allows turning it into
13658 // a TEST instruction later.
13659 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13660 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13661 EVT VT = Op.getValueType();
13662 unsigned BitWidth = VT.getSizeInBits();
13663 unsigned ShAmt = Op->getConstantOperandVal(1);
13664 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13666 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13667 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13668 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13669 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13671 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13672 DAG.getConstant(Mask, dl, VT));
13673 DAG.ReplaceAllUsesWith(Op, New);
13679 // If the primary and result isn't used, don't bother using X86ISD::AND,
13680 // because a TEST instruction will be better.
13681 if (!hasNonFlagsUse(Op))
13687 // Due to the ISEL shortcoming noted above, be conservative if this op is
13688 // likely to be selected as part of a load-modify-store instruction.
13689 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13690 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13691 if (UI->getOpcode() == ISD::STORE)
13694 // Otherwise use a regular EFLAGS-setting instruction.
13695 switch (ArithOp.getOpcode()) {
13696 default: llvm_unreachable("unexpected operator!");
13697 case ISD::SUB: Opcode = X86ISD::SUB; break;
13698 case ISD::XOR: Opcode = X86ISD::XOR; break;
13699 case ISD::AND: Opcode = X86ISD::AND; break;
13701 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13702 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13703 if (EFLAGS.getNode())
13706 Opcode = X86ISD::OR;
13720 return SDValue(Op.getNode(), 1);
13726 // If we found that truncation is beneficial, perform the truncation and
13728 if (NeedTruncation) {
13729 EVT VT = Op.getValueType();
13730 SDValue WideVal = Op->getOperand(0);
13731 EVT WideVT = WideVal.getValueType();
13732 unsigned ConvertedOp = 0;
13733 // Use a target machine opcode to prevent further DAGCombine
13734 // optimizations that may separate the arithmetic operations
13735 // from the setcc node.
13736 switch (WideVal.getOpcode()) {
13738 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13739 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13740 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13741 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13742 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13746 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13747 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13748 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13749 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13750 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13756 // Emit a CMP with 0, which is the TEST pattern.
13757 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13758 DAG.getConstant(0, dl, Op.getValueType()));
13760 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13761 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13763 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13764 DAG.ReplaceAllUsesWith(Op, New);
13765 return SDValue(New.getNode(), 1);
13768 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13770 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13771 SDLoc dl, SelectionDAG &DAG) const {
13772 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13773 if (C->getAPIntValue() == 0)
13774 return EmitTest(Op0, X86CC, dl, DAG);
13776 assert(Op0.getValueType() != MVT::i1 &&
13777 "Unexpected comparison operation for MVT::i1 operands");
13780 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13781 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13782 // Do the comparison at i32 if it's smaller, besides the Atom case.
13783 // This avoids subregister aliasing issues. Keep the smaller reference
13784 // if we're optimizing for size, however, as that'll allow better folding
13785 // of memory operations.
13786 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13787 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13788 !Subtarget->isAtom()) {
13789 unsigned ExtendOp =
13790 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13791 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13792 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13794 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13795 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13796 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13798 return SDValue(Sub.getNode(), 1);
13800 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13803 /// Convert a comparison if required by the subtarget.
13804 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13805 SelectionDAG &DAG) const {
13806 // If the subtarget does not support the FUCOMI instruction, floating-point
13807 // comparisons have to be converted.
13808 if (Subtarget->hasCMov() ||
13809 Cmp.getOpcode() != X86ISD::CMP ||
13810 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13811 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13814 // The instruction selector will select an FUCOM instruction instead of
13815 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13816 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13817 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13819 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13820 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13821 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13822 DAG.getConstant(8, dl, MVT::i8));
13823 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13824 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13827 /// The minimum architected relative accuracy is 2^-12. We need one
13828 /// Newton-Raphson step to have a good float result (24 bits of precision).
13829 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13830 DAGCombinerInfo &DCI,
13831 unsigned &RefinementSteps,
13832 bool &UseOneConstNR) const {
13833 EVT VT = Op.getValueType();
13834 const char *RecipOp;
13836 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13837 // TODO: Add support for AVX512 (v16f32).
13838 // It is likely not profitable to do this for f64 because a double-precision
13839 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13840 // instructions: convert to single, rsqrtss, convert back to double, refine
13841 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13842 // along with FMA, this could be a throughput win.
13843 if (VT == MVT::f32 && Subtarget->hasSSE1())
13845 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13846 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13847 RecipOp = "vec-sqrtf";
13851 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13852 if (!Recips.isEnabled(RecipOp))
13855 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13856 UseOneConstNR = false;
13857 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13860 /// The minimum architected relative accuracy is 2^-12. We need one
13861 /// Newton-Raphson step to have a good float result (24 bits of precision).
13862 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13863 DAGCombinerInfo &DCI,
13864 unsigned &RefinementSteps) const {
13865 EVT VT = Op.getValueType();
13866 const char *RecipOp;
13868 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13869 // TODO: Add support for AVX512 (v16f32).
13870 // It is likely not profitable to do this for f64 because a double-precision
13871 // reciprocal estimate with refinement on x86 prior to FMA requires
13872 // 15 instructions: convert to single, rcpss, convert back to double, refine
13873 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13874 // along with FMA, this could be a throughput win.
13875 if (VT == MVT::f32 && Subtarget->hasSSE1())
13877 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13878 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13879 RecipOp = "vec-divf";
13883 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13884 if (!Recips.isEnabled(RecipOp))
13887 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13888 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13891 /// If we have at least two divisions that use the same divisor, convert to
13892 /// multplication by a reciprocal. This may need to be adjusted for a given
13893 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13894 /// This is because we still need one division to calculate the reciprocal and
13895 /// then we need two multiplies by that reciprocal as replacements for the
13896 /// original divisions.
13897 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13901 static bool isAllOnes(SDValue V) {
13902 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13903 return C && C->isAllOnesValue();
13906 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13907 /// if it's possible.
13908 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13909 SDLoc dl, SelectionDAG &DAG) const {
13910 SDValue Op0 = And.getOperand(0);
13911 SDValue Op1 = And.getOperand(1);
13912 if (Op0.getOpcode() == ISD::TRUNCATE)
13913 Op0 = Op0.getOperand(0);
13914 if (Op1.getOpcode() == ISD::TRUNCATE)
13915 Op1 = Op1.getOperand(0);
13918 if (Op1.getOpcode() == ISD::SHL)
13919 std::swap(Op0, Op1);
13920 if (Op0.getOpcode() == ISD::SHL) {
13921 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13922 if (And00C->getZExtValue() == 1) {
13923 // If we looked past a truncate, check that it's only truncating away
13925 unsigned BitWidth = Op0.getValueSizeInBits();
13926 unsigned AndBitWidth = And.getValueSizeInBits();
13927 if (BitWidth > AndBitWidth) {
13929 DAG.computeKnownBits(Op0, Zeros, Ones);
13930 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13934 RHS = Op0.getOperand(1);
13936 } else if (Op1.getOpcode() == ISD::Constant) {
13937 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13938 uint64_t AndRHSVal = AndRHS->getZExtValue();
13939 SDValue AndLHS = Op0;
13941 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13942 LHS = AndLHS.getOperand(0);
13943 RHS = AndLHS.getOperand(1);
13946 // Use BT if the immediate can't be encoded in a TEST instruction.
13947 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13949 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13953 if (LHS.getNode()) {
13954 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13955 // instruction. Since the shift amount is in-range-or-undefined, we know
13956 // that doing a bittest on the i32 value is ok. We extend to i32 because
13957 // the encoding for the i16 version is larger than the i32 version.
13958 // Also promote i16 to i32 for performance / code size reason.
13959 if (LHS.getValueType() == MVT::i8 ||
13960 LHS.getValueType() == MVT::i16)
13961 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13963 // If the operand types disagree, extend the shift amount to match. Since
13964 // BT ignores high bits (like shifts) we can use anyextend.
13965 if (LHS.getValueType() != RHS.getValueType())
13966 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13968 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13969 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13970 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13971 DAG.getConstant(Cond, dl, MVT::i8), BT);
13977 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13979 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13984 // SSE Condition code mapping:
13993 switch (SetCCOpcode) {
13994 default: llvm_unreachable("Unexpected SETCC condition");
13996 case ISD::SETEQ: SSECC = 0; break;
13998 case ISD::SETGT: Swap = true; // Fallthrough
14000 case ISD::SETOLT: SSECC = 1; break;
14002 case ISD::SETGE: Swap = true; // Fallthrough
14004 case ISD::SETOLE: SSECC = 2; break;
14005 case ISD::SETUO: SSECC = 3; break;
14007 case ISD::SETNE: SSECC = 4; break;
14008 case ISD::SETULE: Swap = true; // Fallthrough
14009 case ISD::SETUGE: SSECC = 5; break;
14010 case ISD::SETULT: Swap = true; // Fallthrough
14011 case ISD::SETUGT: SSECC = 6; break;
14012 case ISD::SETO: SSECC = 7; break;
14014 case ISD::SETONE: SSECC = 8; break;
14017 std::swap(Op0, Op1);
14022 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14023 // ones, and then concatenate the result back.
14024 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14025 MVT VT = Op.getSimpleValueType();
14027 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14028 "Unsupported value type for operation");
14030 unsigned NumElems = VT.getVectorNumElements();
14032 SDValue CC = Op.getOperand(2);
14034 // Extract the LHS vectors
14035 SDValue LHS = Op.getOperand(0);
14036 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14037 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14039 // Extract the RHS vectors
14040 SDValue RHS = Op.getOperand(1);
14041 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14042 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14044 // Issue the operation on the smaller types and concatenate the result back
14045 MVT EltVT = VT.getVectorElementType();
14046 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14047 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14048 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14049 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14052 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14053 SDValue Op0 = Op.getOperand(0);
14054 SDValue Op1 = Op.getOperand(1);
14055 SDValue CC = Op.getOperand(2);
14056 MVT VT = Op.getSimpleValueType();
14059 assert(Op0.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14060 "Unexpected type for boolean compare operation");
14061 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14062 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14063 DAG.getConstant(-1, dl, VT));
14064 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14065 DAG.getConstant(-1, dl, VT));
14066 switch (SetCCOpcode) {
14067 default: llvm_unreachable("Unexpected SETCC condition");
14069 // (x == y) -> ~(x ^ y)
14070 return DAG.getNode(ISD::XOR, dl, VT,
14071 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14072 DAG.getConstant(-1, dl, VT));
14074 // (x != y) -> (x ^ y)
14075 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14078 // (x > y) -> (x & ~y)
14079 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14082 // (x < y) -> (~x & y)
14083 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14086 // (x <= y) -> (~x | y)
14087 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14090 // (x >=y) -> (x | ~y)
14091 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14095 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14096 const X86Subtarget *Subtarget) {
14097 SDValue Op0 = Op.getOperand(0);
14098 SDValue Op1 = Op.getOperand(1);
14099 SDValue CC = Op.getOperand(2);
14100 MVT VT = Op.getSimpleValueType();
14103 assert(Op0.getSimpleValueType().getVectorElementType().getSizeInBits() >= 8 &&
14104 Op.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14105 "Cannot set masked compare for this operation");
14107 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14109 bool Unsigned = false;
14112 switch (SetCCOpcode) {
14113 default: llvm_unreachable("Unexpected SETCC condition");
14114 case ISD::SETNE: SSECC = 4; break;
14115 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14116 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14117 case ISD::SETLT: Swap = true; //fall-through
14118 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14119 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14120 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14121 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14122 case ISD::SETULE: Unsigned = true; //fall-through
14123 case ISD::SETLE: SSECC = 2; break;
14127 std::swap(Op0, Op1);
14129 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14130 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14131 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14132 DAG.getConstant(SSECC, dl, MVT::i8));
14135 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14136 /// operand \p Op1. If non-trivial (for example because it's not constant)
14137 /// return an empty value.
14138 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14140 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14144 MVT VT = Op1.getSimpleValueType();
14145 MVT EVT = VT.getVectorElementType();
14146 unsigned n = VT.getVectorNumElements();
14147 SmallVector<SDValue, 8> ULTOp1;
14149 for (unsigned i = 0; i < n; ++i) {
14150 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14151 if (!Elt || Elt->isOpaque() || Elt->getSimpleValueType(0) != EVT)
14154 // Avoid underflow.
14155 APInt Val = Elt->getAPIntValue();
14159 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14162 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14165 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14166 SelectionDAG &DAG) {
14167 SDValue Op0 = Op.getOperand(0);
14168 SDValue Op1 = Op.getOperand(1);
14169 SDValue CC = Op.getOperand(2);
14170 MVT VT = Op.getSimpleValueType();
14171 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14172 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14177 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14178 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14181 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14182 unsigned Opc = X86ISD::CMPP;
14183 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14184 assert(VT.getVectorNumElements() <= 16);
14185 Opc = X86ISD::CMPM;
14187 // In the two special cases we can't handle, emit two comparisons.
14190 unsigned CombineOpc;
14191 if (SetCCOpcode == ISD::SETUEQ) {
14192 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14194 assert(SetCCOpcode == ISD::SETONE);
14195 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14198 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14199 DAG.getConstant(CC0, dl, MVT::i8));
14200 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14201 DAG.getConstant(CC1, dl, MVT::i8));
14202 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14204 // Handle all other FP comparisons here.
14205 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14206 DAG.getConstant(SSECC, dl, MVT::i8));
14209 MVT VTOp0 = Op0.getSimpleValueType();
14210 assert(VTOp0 == Op1.getSimpleValueType() &&
14211 "Expected operands with same type!");
14212 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14213 "Invalid number of packed elements for source and destination!");
14215 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14216 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14217 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14218 // legalizer firstly checks if the first operand in input to the setcc has
14219 // a legal type. If so, then it promotes the return type to that same type.
14220 // Otherwise, the return type is promoted to the 'next legal type' which,
14221 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14223 // We reach this code only if the following two conditions are met:
14224 // 1. Both return type and operand type have been promoted to wider types
14225 // by the type legalizer.
14226 // 2. The original operand type has been promoted to a 256-bit vector.
14228 // Note that condition 2. only applies for AVX targets.
14229 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14230 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14233 // The non-AVX512 code below works under the assumption that source and
14234 // destination types are the same.
14235 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14236 "Value types for source and destination must be the same!");
14238 // Break 256-bit integer vector compare into smaller ones.
14239 if (VT.is256BitVector() && !Subtarget->hasInt256())
14240 return Lower256IntVSETCC(Op, DAG);
14242 MVT OpVT = Op1.getSimpleValueType();
14243 if (OpVT.getVectorElementType() == MVT::i1)
14244 return LowerBoolVSETCC_AVX512(Op, DAG);
14246 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14247 if (Subtarget->hasAVX512()) {
14248 if (Op1.getSimpleValueType().is512BitVector() ||
14249 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14250 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14251 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14253 // In AVX-512 architecture setcc returns mask with i1 elements,
14254 // But there is no compare instruction for i8 and i16 elements in KNL.
14255 // We are not talking about 512-bit operands in this case, these
14256 // types are illegal.
14258 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14259 OpVT.getVectorElementType().getSizeInBits() >= 8))
14260 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14261 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14264 // Lower using XOP integer comparisons.
14265 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14266 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14267 // Translate compare code to XOP PCOM compare mode.
14268 unsigned CmpMode = 0;
14269 switch (SetCCOpcode) {
14270 default: llvm_unreachable("Unexpected SETCC condition");
14272 case ISD::SETLT: CmpMode = 0x00; break;
14274 case ISD::SETLE: CmpMode = 0x01; break;
14276 case ISD::SETGT: CmpMode = 0x02; break;
14278 case ISD::SETGE: CmpMode = 0x03; break;
14279 case ISD::SETEQ: CmpMode = 0x04; break;
14280 case ISD::SETNE: CmpMode = 0x05; break;
14283 // Are we comparing unsigned or signed integers?
14284 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14285 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14287 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14288 DAG.getConstant(CmpMode, dl, MVT::i8));
14291 // We are handling one of the integer comparisons here. Since SSE only has
14292 // GT and EQ comparisons for integer, swapping operands and multiple
14293 // operations may be required for some comparisons.
14295 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14296 bool Subus = false;
14298 switch (SetCCOpcode) {
14299 default: llvm_unreachable("Unexpected SETCC condition");
14300 case ISD::SETNE: Invert = true;
14301 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14302 case ISD::SETLT: Swap = true;
14303 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14304 case ISD::SETGE: Swap = true;
14305 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14306 Invert = true; break;
14307 case ISD::SETULT: Swap = true;
14308 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14309 FlipSigns = true; break;
14310 case ISD::SETUGE: Swap = true;
14311 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14312 FlipSigns = true; Invert = true; break;
14315 // Special case: Use min/max operations for SETULE/SETUGE
14316 MVT VET = VT.getVectorElementType();
14318 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14319 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14322 switch (SetCCOpcode) {
14324 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14325 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14328 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14331 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14332 if (!MinMax && hasSubus) {
14333 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14335 // t = psubus Op0, Op1
14336 // pcmpeq t, <0..0>
14337 switch (SetCCOpcode) {
14339 case ISD::SETULT: {
14340 // If the comparison is against a constant we can turn this into a
14341 // setule. With psubus, setule does not require a swap. This is
14342 // beneficial because the constant in the register is no longer
14343 // destructed as the destination so it can be hoisted out of a loop.
14344 // Only do this pre-AVX since vpcmp* is no longer destructive.
14345 if (Subtarget->hasAVX())
14347 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14348 if (ULEOp1.getNode()) {
14350 Subus = true; Invert = false; Swap = false;
14354 // Psubus is better than flip-sign because it requires no inversion.
14355 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14356 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14360 Opc = X86ISD::SUBUS;
14366 std::swap(Op0, Op1);
14368 // Check that the operation in question is available (most are plain SSE2,
14369 // but PCMPGTQ and PCMPEQQ have different requirements).
14370 if (VT == MVT::v2i64) {
14371 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14372 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14374 // First cast everything to the right type.
14375 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14376 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14378 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14379 // bits of the inputs before performing those operations. The lower
14380 // compare is always unsigned.
14383 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14385 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14386 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14387 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14388 Sign, Zero, Sign, Zero);
14390 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14391 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14393 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14394 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14395 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14397 // Create masks for only the low parts/high parts of the 64 bit integers.
14398 static const int MaskHi[] = { 1, 1, 3, 3 };
14399 static const int MaskLo[] = { 0, 0, 2, 2 };
14400 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14401 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14402 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14404 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14405 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14408 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14410 return DAG.getBitcast(VT, Result);
14413 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14414 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14415 // pcmpeqd + pshufd + pand.
14416 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14418 // First cast everything to the right type.
14419 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14420 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14423 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14425 // Make sure the lower and upper halves are both all-ones.
14426 static const int Mask[] = { 1, 0, 3, 2 };
14427 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14428 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14431 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14433 return DAG.getBitcast(VT, Result);
14437 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14438 // bits of the inputs before performing those operations.
14440 MVT EltVT = VT.getVectorElementType();
14441 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14443 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14444 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14447 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14449 // If the logical-not of the result is required, perform that now.
14451 Result = DAG.getNOT(dl, Result, VT);
14454 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14457 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14458 getZeroVector(VT, Subtarget, DAG, dl));
14463 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14465 MVT VT = Op.getSimpleValueType();
14467 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14469 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14470 && "SetCC type must be 8-bit or 1-bit integer");
14471 SDValue Op0 = Op.getOperand(0);
14472 SDValue Op1 = Op.getOperand(1);
14474 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14476 // Optimize to BT if possible.
14477 // Lower (X & (1 << N)) == 0 to BT(X, N).
14478 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14479 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14480 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14481 Op1.getOpcode() == ISD::Constant &&
14482 cast<ConstantSDNode>(Op1)->isNullValue() &&
14483 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14484 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14485 if (NewSetCC.getNode()) {
14487 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14492 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14494 if (Op1.getOpcode() == ISD::Constant &&
14495 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14496 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14497 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14499 // If the input is a setcc, then reuse the input setcc or use a new one with
14500 // the inverted condition.
14501 if (Op0.getOpcode() == X86ISD::SETCC) {
14502 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14503 bool Invert = (CC == ISD::SETNE) ^
14504 cast<ConstantSDNode>(Op1)->isNullValue();
14508 CCode = X86::GetOppositeBranchCondition(CCode);
14509 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14510 DAG.getConstant(CCode, dl, MVT::i8),
14511 Op0.getOperand(1));
14513 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14517 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14518 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14519 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14521 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14522 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14525 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14526 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14527 if (X86CC == X86::COND_INVALID)
14530 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14531 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14532 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14533 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14535 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14539 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14540 static bool isX86LogicalCmp(SDValue Op) {
14541 unsigned Opc = Op.getNode()->getOpcode();
14542 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14543 Opc == X86ISD::SAHF)
14545 if (Op.getResNo() == 1 &&
14546 (Opc == X86ISD::ADD ||
14547 Opc == X86ISD::SUB ||
14548 Opc == X86ISD::ADC ||
14549 Opc == X86ISD::SBB ||
14550 Opc == X86ISD::SMUL ||
14551 Opc == X86ISD::UMUL ||
14552 Opc == X86ISD::INC ||
14553 Opc == X86ISD::DEC ||
14554 Opc == X86ISD::OR ||
14555 Opc == X86ISD::XOR ||
14556 Opc == X86ISD::AND))
14559 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14565 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14566 if (V.getOpcode() != ISD::TRUNCATE)
14569 SDValue VOp0 = V.getOperand(0);
14570 unsigned InBits = VOp0.getValueSizeInBits();
14571 unsigned Bits = V.getValueSizeInBits();
14572 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14575 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14576 bool addTest = true;
14577 SDValue Cond = Op.getOperand(0);
14578 SDValue Op1 = Op.getOperand(1);
14579 SDValue Op2 = Op.getOperand(2);
14581 MVT VT = Op1.getSimpleValueType();
14584 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14585 // are available or VBLENDV if AVX is available.
14586 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14587 if (Cond.getOpcode() == ISD::SETCC &&
14588 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14589 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14590 VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
14591 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14592 int SSECC = translateX86FSETCC(
14593 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14596 if (Subtarget->hasAVX512()) {
14597 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14598 DAG.getConstant(SSECC, DL, MVT::i8));
14599 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14602 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14603 DAG.getConstant(SSECC, DL, MVT::i8));
14605 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14606 // of 3 logic instructions for size savings and potentially speed.
14607 // Unfortunately, there is no scalar form of VBLENDV.
14609 // If either operand is a constant, don't try this. We can expect to
14610 // optimize away at least one of the logic instructions later in that
14611 // case, so that sequence would be faster than a variable blend.
14613 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14614 // uses XMM0 as the selection register. That may need just as many
14615 // instructions as the AND/ANDN/OR sequence due to register moves, so
14618 if (Subtarget->hasAVX() &&
14619 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14621 // Convert to vectors, do a VSELECT, and convert back to scalar.
14622 // All of the conversions should be optimized away.
14624 MVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14625 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14626 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14627 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14629 MVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14630 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14632 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14634 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14635 VSel, DAG.getIntPtrConstant(0, DL));
14637 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14638 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14639 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14643 if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
14645 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14646 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14647 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14648 Op1Scalar = Op1.getOperand(0);
14650 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14651 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14652 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14653 Op2Scalar = Op2.getOperand(0);
14654 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14655 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14656 Op1Scalar.getValueType(),
14657 Cond, Op1Scalar, Op2Scalar);
14658 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14659 return DAG.getBitcast(VT, newSelect);
14660 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14661 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14662 DAG.getIntPtrConstant(0, DL));
14666 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14667 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14668 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14669 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14670 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14671 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14672 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14674 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14677 if (Cond.getOpcode() == ISD::SETCC) {
14678 SDValue NewCond = LowerSETCC(Cond, DAG);
14679 if (NewCond.getNode())
14683 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14684 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14685 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14686 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14687 if (Cond.getOpcode() == X86ISD::SETCC &&
14688 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14689 isZero(Cond.getOperand(1).getOperand(1))) {
14690 SDValue Cmp = Cond.getOperand(1);
14692 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14694 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14695 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14696 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14698 SDValue CmpOp0 = Cmp.getOperand(0);
14699 // Apply further optimizations for special cases
14700 // (select (x != 0), -1, 0) -> neg & sbb
14701 // (select (x == 0), 0, -1) -> neg & sbb
14702 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14703 if (YC->isNullValue() &&
14704 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14705 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14706 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14707 DAG.getConstant(0, DL,
14708 CmpOp0.getValueType()),
14710 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14711 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14712 SDValue(Neg.getNode(), 1));
14716 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14717 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14718 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14720 SDValue Res = // Res = 0 or -1.
14721 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14722 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14724 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14725 Res = DAG.getNOT(DL, Res, Res.getValueType());
14727 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14728 if (!N2C || !N2C->isNullValue())
14729 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14734 // Look past (and (setcc_carry (cmp ...)), 1).
14735 if (Cond.getOpcode() == ISD::AND &&
14736 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14737 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14738 if (C && C->getAPIntValue() == 1)
14739 Cond = Cond.getOperand(0);
14742 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14743 // setting operand in place of the X86ISD::SETCC.
14744 unsigned CondOpcode = Cond.getOpcode();
14745 if (CondOpcode == X86ISD::SETCC ||
14746 CondOpcode == X86ISD::SETCC_CARRY) {
14747 CC = Cond.getOperand(0);
14749 SDValue Cmp = Cond.getOperand(1);
14750 unsigned Opc = Cmp.getOpcode();
14751 MVT VT = Op.getSimpleValueType();
14753 bool IllegalFPCMov = false;
14754 if (VT.isFloatingPoint() && !VT.isVector() &&
14755 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14756 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14758 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14759 Opc == X86ISD::BT) { // FIXME
14763 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14764 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14765 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14766 Cond.getOperand(0).getValueType() != MVT::i8)) {
14767 SDValue LHS = Cond.getOperand(0);
14768 SDValue RHS = Cond.getOperand(1);
14769 unsigned X86Opcode;
14772 switch (CondOpcode) {
14773 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14774 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14775 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14776 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14777 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14778 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14779 default: llvm_unreachable("unexpected overflowing operator");
14781 if (CondOpcode == ISD::UMULO)
14782 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14785 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14787 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14789 if (CondOpcode == ISD::UMULO)
14790 Cond = X86Op.getValue(2);
14792 Cond = X86Op.getValue(1);
14794 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14799 // Look past the truncate if the high bits are known zero.
14800 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14801 Cond = Cond.getOperand(0);
14803 // We know the result of AND is compared against zero. Try to match
14805 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14806 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14807 if (NewSetCC.getNode()) {
14808 CC = NewSetCC.getOperand(0);
14809 Cond = NewSetCC.getOperand(1);
14816 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14817 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14820 // a < b ? -1 : 0 -> RES = ~setcc_carry
14821 // a < b ? 0 : -1 -> RES = setcc_carry
14822 // a >= b ? -1 : 0 -> RES = setcc_carry
14823 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14824 if (Cond.getOpcode() == X86ISD::SUB) {
14825 Cond = ConvertCmpIfNecessary(Cond, DAG);
14826 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14828 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14829 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14830 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14831 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14833 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14834 return DAG.getNOT(DL, Res, Res.getValueType());
14839 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14840 // widen the cmov and push the truncate through. This avoids introducing a new
14841 // branch during isel and doesn't add any extensions.
14842 if (Op.getValueType() == MVT::i8 &&
14843 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14844 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14845 if (T1.getValueType() == T2.getValueType() &&
14846 // Blacklist CopyFromReg to avoid partial register stalls.
14847 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14848 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14849 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14850 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14854 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14855 // condition is true.
14856 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14857 SDValue Ops[] = { Op2, Op1, CC, Cond };
14858 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14861 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14862 const X86Subtarget *Subtarget,
14863 SelectionDAG &DAG) {
14864 MVT VT = Op->getSimpleValueType(0);
14865 SDValue In = Op->getOperand(0);
14866 MVT InVT = In.getSimpleValueType();
14867 MVT VTElt = VT.getVectorElementType();
14868 MVT InVTElt = InVT.getVectorElementType();
14872 if ((InVTElt == MVT::i1) &&
14873 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14874 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14876 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14877 VTElt.getSizeInBits() <= 16)) ||
14879 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14880 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14882 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14883 VTElt.getSizeInBits() >= 32))))
14884 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14886 unsigned int NumElts = VT.getVectorNumElements();
14888 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14891 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14892 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14893 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14894 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14897 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14898 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14900 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14903 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14905 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14906 if (VT.is512BitVector())
14908 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14911 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14912 const X86Subtarget *Subtarget,
14913 SelectionDAG &DAG) {
14914 SDValue In = Op->getOperand(0);
14915 MVT VT = Op->getSimpleValueType(0);
14916 MVT InVT = In.getSimpleValueType();
14917 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14919 MVT InSVT = InVT.getVectorElementType();
14920 assert(VT.getVectorElementType().getSizeInBits() > InSVT.getSizeInBits());
14922 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14924 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14929 // SSE41 targets can use the pmovsx* instructions directly.
14930 if (Subtarget->hasSSE41())
14931 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14933 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14937 // As SRAI is only available on i16/i32 types, we expand only up to i32
14938 // and handle i64 separately.
14939 while (CurrVT != VT && CurrVT.getVectorElementType() != MVT::i32) {
14940 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14941 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14942 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14943 Curr = DAG.getBitcast(CurrVT, Curr);
14946 SDValue SignExt = Curr;
14947 if (CurrVT != InVT) {
14948 unsigned SignExtShift =
14949 CurrVT.getVectorElementType().getSizeInBits() - InSVT.getSizeInBits();
14950 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14951 DAG.getConstant(SignExtShift, dl, MVT::i8));
14957 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14958 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14959 DAG.getConstant(31, dl, MVT::i8));
14960 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14961 return DAG.getBitcast(VT, Ext);
14967 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14968 SelectionDAG &DAG) {
14969 MVT VT = Op->getSimpleValueType(0);
14970 SDValue In = Op->getOperand(0);
14971 MVT InVT = In.getSimpleValueType();
14974 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14975 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14977 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14978 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14979 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14982 if (Subtarget->hasInt256())
14983 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14985 // Optimize vectors in AVX mode
14986 // Sign extend v8i16 to v8i32 and
14989 // Divide input vector into two parts
14990 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14991 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14992 // concat the vectors to original VT
14994 unsigned NumElems = InVT.getVectorNumElements();
14995 SDValue Undef = DAG.getUNDEF(InVT);
14997 SmallVector<int,8> ShufMask1(NumElems, -1);
14998 for (unsigned i = 0; i != NumElems/2; ++i)
15001 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15003 SmallVector<int,8> ShufMask2(NumElems, -1);
15004 for (unsigned i = 0; i != NumElems/2; ++i)
15005 ShufMask2[i] = i + NumElems/2;
15007 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15009 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(),
15010 VT.getVectorNumElements()/2);
15012 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15013 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15015 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15018 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15019 // may emit an illegal shuffle but the expansion is still better than scalar
15020 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15021 // we'll emit a shuffle and a arithmetic shift.
15022 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15023 // TODO: It is possible to support ZExt by zeroing the undef values during
15024 // the shuffle phase or after the shuffle.
15025 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15026 SelectionDAG &DAG) {
15027 MVT RegVT = Op.getSimpleValueType();
15028 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15029 assert(RegVT.isInteger() &&
15030 "We only custom lower integer vector sext loads.");
15032 // Nothing useful we can do without SSE2 shuffles.
15033 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15035 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15037 EVT MemVT = Ld->getMemoryVT();
15038 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15039 unsigned RegSz = RegVT.getSizeInBits();
15041 ISD::LoadExtType Ext = Ld->getExtensionType();
15043 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15044 && "Only anyext and sext are currently implemented.");
15045 assert(MemVT != RegVT && "Cannot extend to the same type");
15046 assert(MemVT.isVector() && "Must load a vector from memory");
15048 unsigned NumElems = RegVT.getVectorNumElements();
15049 unsigned MemSz = MemVT.getSizeInBits();
15050 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15052 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15053 // The only way in which we have a legal 256-bit vector result but not the
15054 // integer 256-bit operations needed to directly lower a sextload is if we
15055 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15056 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15057 // correctly legalized. We do this late to allow the canonical form of
15058 // sextload to persist throughout the rest of the DAG combiner -- it wants
15059 // to fold together any extensions it can, and so will fuse a sign_extend
15060 // of an sextload into a sextload targeting a wider value.
15062 if (MemSz == 128) {
15063 // Just switch this to a normal load.
15064 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15065 "it must be a legal 128-bit vector "
15067 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15068 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15069 Ld->isInvariant(), Ld->getAlignment());
15071 assert(MemSz < 128 &&
15072 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15073 // Do an sext load to a 128-bit vector type. We want to use the same
15074 // number of elements, but elements half as wide. This will end up being
15075 // recursively lowered by this routine, but will succeed as we definitely
15076 // have all the necessary features if we're using AVX1.
15078 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15079 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15081 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15082 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15083 Ld->isNonTemporal(), Ld->isInvariant(),
15084 Ld->getAlignment());
15087 // Replace chain users with the new chain.
15088 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15089 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15091 // Finally, do a normal sign-extend to the desired register.
15092 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15095 // All sizes must be a power of two.
15096 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15097 "Non-power-of-two elements are not custom lowered!");
15099 // Attempt to load the original value using scalar loads.
15100 // Find the largest scalar type that divides the total loaded size.
15101 MVT SclrLoadTy = MVT::i8;
15102 for (MVT Tp : MVT::integer_valuetypes()) {
15103 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15108 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15109 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15111 SclrLoadTy = MVT::f64;
15113 // Calculate the number of scalar loads that we need to perform
15114 // in order to load our vector from memory.
15115 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15117 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15118 "Can only lower sext loads with a single scalar load!");
15120 unsigned loadRegZize = RegSz;
15121 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15124 // Represent our vector as a sequence of elements which are the
15125 // largest scalar that we can load.
15126 EVT LoadUnitVecVT = EVT::getVectorVT(
15127 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15129 // Represent the data using the same element type that is stored in
15130 // memory. In practice, we ''widen'' MemVT.
15132 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15133 loadRegZize / MemVT.getScalarSizeInBits());
15135 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15136 "Invalid vector type");
15138 // We can't shuffle using an illegal type.
15139 assert(TLI.isTypeLegal(WideVecVT) &&
15140 "We only lower types that form legal widened vector types");
15142 SmallVector<SDValue, 8> Chains;
15143 SDValue Ptr = Ld->getBasePtr();
15144 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15145 TLI.getPointerTy(DAG.getDataLayout()));
15146 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15148 for (unsigned i = 0; i < NumLoads; ++i) {
15149 // Perform a single load.
15150 SDValue ScalarLoad =
15151 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15152 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15153 Ld->getAlignment());
15154 Chains.push_back(ScalarLoad.getValue(1));
15155 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15156 // another round of DAGCombining.
15158 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15160 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15161 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15163 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15166 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15168 // Bitcast the loaded value to a vector of the original element type, in
15169 // the size of the target vector type.
15170 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15171 unsigned SizeRatio = RegSz / MemSz;
15173 if (Ext == ISD::SEXTLOAD) {
15174 // If we have SSE4.1, we can directly emit a VSEXT node.
15175 if (Subtarget->hasSSE41()) {
15176 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15177 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15181 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15183 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15184 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15186 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15187 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15191 // Redistribute the loaded elements into the different locations.
15192 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15193 for (unsigned i = 0; i != NumElems; ++i)
15194 ShuffleVec[i * SizeRatio] = i;
15196 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15197 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15199 // Bitcast to the requested type.
15200 Shuff = DAG.getBitcast(RegVT, Shuff);
15201 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15205 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15206 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15207 // from the AND / OR.
15208 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15209 Opc = Op.getOpcode();
15210 if (Opc != ISD::OR && Opc != ISD::AND)
15212 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15213 Op.getOperand(0).hasOneUse() &&
15214 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15215 Op.getOperand(1).hasOneUse());
15218 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15219 // 1 and that the SETCC node has a single use.
15220 static bool isXor1OfSetCC(SDValue Op) {
15221 if (Op.getOpcode() != ISD::XOR)
15223 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15224 if (N1C && N1C->getAPIntValue() == 1) {
15225 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15226 Op.getOperand(0).hasOneUse();
15231 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15232 bool addTest = true;
15233 SDValue Chain = Op.getOperand(0);
15234 SDValue Cond = Op.getOperand(1);
15235 SDValue Dest = Op.getOperand(2);
15238 bool Inverted = false;
15240 if (Cond.getOpcode() == ISD::SETCC) {
15241 // Check for setcc([su]{add,sub,mul}o == 0).
15242 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15243 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15244 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15245 Cond.getOperand(0).getResNo() == 1 &&
15246 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15247 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15248 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15249 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15250 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15251 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15253 Cond = Cond.getOperand(0);
15255 SDValue NewCond = LowerSETCC(Cond, DAG);
15256 if (NewCond.getNode())
15261 // FIXME: LowerXALUO doesn't handle these!!
15262 else if (Cond.getOpcode() == X86ISD::ADD ||
15263 Cond.getOpcode() == X86ISD::SUB ||
15264 Cond.getOpcode() == X86ISD::SMUL ||
15265 Cond.getOpcode() == X86ISD::UMUL)
15266 Cond = LowerXALUO(Cond, DAG);
15269 // Look pass (and (setcc_carry (cmp ...)), 1).
15270 if (Cond.getOpcode() == ISD::AND &&
15271 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15272 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15273 if (C && C->getAPIntValue() == 1)
15274 Cond = Cond.getOperand(0);
15277 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15278 // setting operand in place of the X86ISD::SETCC.
15279 unsigned CondOpcode = Cond.getOpcode();
15280 if (CondOpcode == X86ISD::SETCC ||
15281 CondOpcode == X86ISD::SETCC_CARRY) {
15282 CC = Cond.getOperand(0);
15284 SDValue Cmp = Cond.getOperand(1);
15285 unsigned Opc = Cmp.getOpcode();
15286 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15287 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15291 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15295 // These can only come from an arithmetic instruction with overflow,
15296 // e.g. SADDO, UADDO.
15297 Cond = Cond.getNode()->getOperand(1);
15303 CondOpcode = Cond.getOpcode();
15304 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15305 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15306 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15307 Cond.getOperand(0).getValueType() != MVT::i8)) {
15308 SDValue LHS = Cond.getOperand(0);
15309 SDValue RHS = Cond.getOperand(1);
15310 unsigned X86Opcode;
15313 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15314 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15316 switch (CondOpcode) {
15317 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15319 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15321 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15324 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15325 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15327 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15329 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15332 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15333 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15334 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15335 default: llvm_unreachable("unexpected overflowing operator");
15338 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15339 if (CondOpcode == ISD::UMULO)
15340 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15343 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15345 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15347 if (CondOpcode == ISD::UMULO)
15348 Cond = X86Op.getValue(2);
15350 Cond = X86Op.getValue(1);
15352 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15356 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15357 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15358 if (CondOpc == ISD::OR) {
15359 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15360 // two branches instead of an explicit OR instruction with a
15362 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15363 isX86LogicalCmp(Cmp)) {
15364 CC = Cond.getOperand(0).getOperand(0);
15365 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15366 Chain, Dest, CC, Cmp);
15367 CC = Cond.getOperand(1).getOperand(0);
15371 } else { // ISD::AND
15372 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15373 // two branches instead of an explicit AND instruction with a
15374 // separate test. However, we only do this if this block doesn't
15375 // have a fall-through edge, because this requires an explicit
15376 // jmp when the condition is false.
15377 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15378 isX86LogicalCmp(Cmp) &&
15379 Op.getNode()->hasOneUse()) {
15380 X86::CondCode CCode =
15381 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15382 CCode = X86::GetOppositeBranchCondition(CCode);
15383 CC = DAG.getConstant(CCode, dl, MVT::i8);
15384 SDNode *User = *Op.getNode()->use_begin();
15385 // Look for an unconditional branch following this conditional branch.
15386 // We need this because we need to reverse the successors in order
15387 // to implement FCMP_OEQ.
15388 if (User->getOpcode() == ISD::BR) {
15389 SDValue FalseBB = User->getOperand(1);
15391 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15392 assert(NewBR == User);
15396 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15397 Chain, Dest, CC, Cmp);
15398 X86::CondCode CCode =
15399 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15400 CCode = X86::GetOppositeBranchCondition(CCode);
15401 CC = DAG.getConstant(CCode, dl, MVT::i8);
15407 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15408 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15409 // It should be transformed during dag combiner except when the condition
15410 // is set by a arithmetics with overflow node.
15411 X86::CondCode CCode =
15412 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15413 CCode = X86::GetOppositeBranchCondition(CCode);
15414 CC = DAG.getConstant(CCode, dl, MVT::i8);
15415 Cond = Cond.getOperand(0).getOperand(1);
15417 } else if (Cond.getOpcode() == ISD::SETCC &&
15418 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15419 // For FCMP_OEQ, we can emit
15420 // two branches instead of an explicit AND instruction with a
15421 // separate test. However, we only do this if this block doesn't
15422 // have a fall-through edge, because this requires an explicit
15423 // jmp when the condition is false.
15424 if (Op.getNode()->hasOneUse()) {
15425 SDNode *User = *Op.getNode()->use_begin();
15426 // Look for an unconditional branch following this conditional branch.
15427 // We need this because we need to reverse the successors in order
15428 // to implement FCMP_OEQ.
15429 if (User->getOpcode() == ISD::BR) {
15430 SDValue FalseBB = User->getOperand(1);
15432 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15433 assert(NewBR == User);
15437 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15438 Cond.getOperand(0), Cond.getOperand(1));
15439 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15440 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15441 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15442 Chain, Dest, CC, Cmp);
15443 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15448 } else if (Cond.getOpcode() == ISD::SETCC &&
15449 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15450 // For FCMP_UNE, we can emit
15451 // two branches instead of an explicit AND instruction with a
15452 // separate test. However, we only do this if this block doesn't
15453 // have a fall-through edge, because this requires an explicit
15454 // jmp when the condition is false.
15455 if (Op.getNode()->hasOneUse()) {
15456 SDNode *User = *Op.getNode()->use_begin();
15457 // Look for an unconditional branch following this conditional branch.
15458 // We need this because we need to reverse the successors in order
15459 // to implement FCMP_UNE.
15460 if (User->getOpcode() == ISD::BR) {
15461 SDValue FalseBB = User->getOperand(1);
15463 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15464 assert(NewBR == User);
15467 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15468 Cond.getOperand(0), Cond.getOperand(1));
15469 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15470 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15471 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15472 Chain, Dest, CC, Cmp);
15473 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15483 // Look pass the truncate if the high bits are known zero.
15484 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15485 Cond = Cond.getOperand(0);
15487 // We know the result of AND is compared against zero. Try to match
15489 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15490 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15491 if (NewSetCC.getNode()) {
15492 CC = NewSetCC.getOperand(0);
15493 Cond = NewSetCC.getOperand(1);
15500 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15501 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15502 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15504 Cond = ConvertCmpIfNecessary(Cond, DAG);
15505 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15506 Chain, Dest, CC, Cond);
15509 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15510 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15511 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15512 // that the guard pages used by the OS virtual memory manager are allocated in
15513 // correct sequence.
15515 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15516 SelectionDAG &DAG) const {
15517 MachineFunction &MF = DAG.getMachineFunction();
15518 bool SplitStack = MF.shouldSplitStack();
15519 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15524 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15525 SDNode* Node = Op.getNode();
15527 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15528 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15529 " not tell us which reg is the stack pointer!");
15530 EVT VT = Node->getValueType(0);
15531 SDValue Tmp1 = SDValue(Node, 0);
15532 SDValue Tmp2 = SDValue(Node, 1);
15533 SDValue Tmp3 = Node->getOperand(2);
15534 SDValue Chain = Tmp1.getOperand(0);
15536 // Chain the dynamic stack allocation so that it doesn't modify the stack
15537 // pointer when other instructions are using the stack.
15538 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15541 SDValue Size = Tmp2.getOperand(1);
15542 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15543 Chain = SP.getValue(1);
15544 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15545 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15546 unsigned StackAlign = TFI.getStackAlignment();
15547 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15548 if (Align > StackAlign)
15549 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15550 DAG.getConstant(-(uint64_t)Align, dl, VT));
15551 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15553 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15554 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15557 SDValue Ops[2] = { Tmp1, Tmp2 };
15558 return DAG.getMergeValues(Ops, dl);
15562 SDValue Chain = Op.getOperand(0);
15563 SDValue Size = Op.getOperand(1);
15564 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15565 EVT VT = Op.getNode()->getValueType(0);
15567 bool Is64Bit = Subtarget->is64Bit();
15568 MVT SPTy = getPointerTy(DAG.getDataLayout());
15571 MachineRegisterInfo &MRI = MF.getRegInfo();
15574 // The 64 bit implementation of segmented stacks needs to clobber both r10
15575 // r11. This makes it impossible to use it along with nested parameters.
15576 const Function *F = MF.getFunction();
15578 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15580 if (I->hasNestAttr())
15581 report_fatal_error("Cannot use segmented stacks with functions that "
15582 "have nested arguments.");
15585 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15586 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15587 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15588 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15589 DAG.getRegister(Vreg, SPTy));
15590 SDValue Ops1[2] = { Value, Chain };
15591 return DAG.getMergeValues(Ops1, dl);
15594 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15596 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15597 Flag = Chain.getValue(1);
15598 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15600 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15602 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15603 unsigned SPReg = RegInfo->getStackRegister();
15604 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15605 Chain = SP.getValue(1);
15608 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15609 DAG.getConstant(-(uint64_t)Align, dl, VT));
15610 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15613 SDValue Ops1[2] = { SP, Chain };
15614 return DAG.getMergeValues(Ops1, dl);
15618 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15619 MachineFunction &MF = DAG.getMachineFunction();
15620 auto PtrVT = getPointerTy(MF.getDataLayout());
15621 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15623 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15626 if (!Subtarget->is64Bit() ||
15627 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15628 // vastart just stores the address of the VarArgsFrameIndex slot into the
15629 // memory location argument.
15630 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15631 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15632 MachinePointerInfo(SV), false, false, 0);
15636 // gp_offset (0 - 6 * 8)
15637 // fp_offset (48 - 48 + 8 * 16)
15638 // overflow_arg_area (point to parameters coming in memory).
15640 SmallVector<SDValue, 8> MemOps;
15641 SDValue FIN = Op.getOperand(1);
15643 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15644 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15646 FIN, MachinePointerInfo(SV), false, false, 0);
15647 MemOps.push_back(Store);
15650 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15651 Store = DAG.getStore(Op.getOperand(0), DL,
15652 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15654 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15655 MemOps.push_back(Store);
15657 // Store ptr to overflow_arg_area
15658 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15659 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15660 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15661 MachinePointerInfo(SV, 8),
15663 MemOps.push_back(Store);
15665 // Store ptr to reg_save_area.
15666 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15667 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15668 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15669 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15670 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15671 MemOps.push_back(Store);
15672 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15675 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15676 assert(Subtarget->is64Bit() &&
15677 "LowerVAARG only handles 64-bit va_arg!");
15678 assert(Op.getNode()->getNumOperands() == 4);
15680 MachineFunction &MF = DAG.getMachineFunction();
15681 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15682 // The Win64 ABI uses char* instead of a structure.
15683 return DAG.expandVAArg(Op.getNode());
15685 SDValue Chain = Op.getOperand(0);
15686 SDValue SrcPtr = Op.getOperand(1);
15687 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15688 unsigned Align = Op.getConstantOperandVal(3);
15691 EVT ArgVT = Op.getNode()->getValueType(0);
15692 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15693 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15696 // Decide which area this value should be read from.
15697 // TODO: Implement the AMD64 ABI in its entirety. This simple
15698 // selection mechanism works only for the basic types.
15699 if (ArgVT == MVT::f80) {
15700 llvm_unreachable("va_arg for f80 not yet implemented");
15701 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15702 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15703 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15704 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15706 llvm_unreachable("Unhandled argument type in LowerVAARG");
15709 if (ArgMode == 2) {
15710 // Sanity Check: Make sure using fp_offset makes sense.
15711 assert(!Subtarget->useSoftFloat() &&
15712 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15713 Subtarget->hasSSE1());
15716 // Insert VAARG_64 node into the DAG
15717 // VAARG_64 returns two values: Variable Argument Address, Chain
15718 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15719 DAG.getConstant(ArgMode, dl, MVT::i8),
15720 DAG.getConstant(Align, dl, MVT::i32)};
15721 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15722 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15723 VTs, InstOps, MVT::i64,
15724 MachinePointerInfo(SV),
15726 /*Volatile=*/false,
15728 /*WriteMem=*/true);
15729 Chain = VAARG.getValue(1);
15731 // Load the next argument and return it
15732 return DAG.getLoad(ArgVT, dl,
15735 MachinePointerInfo(),
15736 false, false, false, 0);
15739 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15740 SelectionDAG &DAG) {
15741 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15742 // where a va_list is still an i8*.
15743 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15744 if (Subtarget->isCallingConvWin64(
15745 DAG.getMachineFunction().getFunction()->getCallingConv()))
15746 // Probably a Win64 va_copy.
15747 return DAG.expandVACopy(Op.getNode());
15749 SDValue Chain = Op.getOperand(0);
15750 SDValue DstPtr = Op.getOperand(1);
15751 SDValue SrcPtr = Op.getOperand(2);
15752 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15753 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15756 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15757 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15759 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15762 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15763 // amount is a constant. Takes immediate version of shift as input.
15764 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15765 SDValue SrcOp, uint64_t ShiftAmt,
15766 SelectionDAG &DAG) {
15767 MVT ElementType = VT.getVectorElementType();
15769 // Fold this packed shift into its first operand if ShiftAmt is 0.
15773 // Check for ShiftAmt >= element width
15774 if (ShiftAmt >= ElementType.getSizeInBits()) {
15775 if (Opc == X86ISD::VSRAI)
15776 ShiftAmt = ElementType.getSizeInBits() - 1;
15778 return DAG.getConstant(0, dl, VT);
15781 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15782 && "Unknown target vector shift-by-constant node");
15784 // Fold this packed vector shift into a build vector if SrcOp is a
15785 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15786 if (VT == SrcOp.getSimpleValueType() &&
15787 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15788 SmallVector<SDValue, 8> Elts;
15789 unsigned NumElts = SrcOp->getNumOperands();
15790 ConstantSDNode *ND;
15793 default: llvm_unreachable(nullptr);
15794 case X86ISD::VSHLI:
15795 for (unsigned i=0; i!=NumElts; ++i) {
15796 SDValue CurrentOp = SrcOp->getOperand(i);
15797 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15798 Elts.push_back(CurrentOp);
15801 ND = cast<ConstantSDNode>(CurrentOp);
15802 const APInt &C = ND->getAPIntValue();
15803 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15806 case X86ISD::VSRLI:
15807 for (unsigned i=0; i!=NumElts; ++i) {
15808 SDValue CurrentOp = SrcOp->getOperand(i);
15809 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15810 Elts.push_back(CurrentOp);
15813 ND = cast<ConstantSDNode>(CurrentOp);
15814 const APInt &C = ND->getAPIntValue();
15815 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15818 case X86ISD::VSRAI:
15819 for (unsigned i=0; i!=NumElts; ++i) {
15820 SDValue CurrentOp = SrcOp->getOperand(i);
15821 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15822 Elts.push_back(CurrentOp);
15825 ND = cast<ConstantSDNode>(CurrentOp);
15826 const APInt &C = ND->getAPIntValue();
15827 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15832 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15835 return DAG.getNode(Opc, dl, VT, SrcOp,
15836 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15839 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15840 // may or may not be a constant. Takes immediate version of shift as input.
15841 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15842 SDValue SrcOp, SDValue ShAmt,
15843 SelectionDAG &DAG) {
15844 MVT SVT = ShAmt.getSimpleValueType();
15845 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15847 // Catch shift-by-constant.
15848 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15849 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15850 CShAmt->getZExtValue(), DAG);
15852 // Change opcode to non-immediate version
15854 default: llvm_unreachable("Unknown target vector shift node");
15855 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15856 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15857 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15860 const X86Subtarget &Subtarget =
15861 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15862 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15863 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15864 // Let the shuffle legalizer expand this shift amount node.
15865 SDValue Op0 = ShAmt.getOperand(0);
15866 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15867 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15869 // Need to build a vector containing shift amount.
15870 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15871 SmallVector<SDValue, 4> ShOps;
15872 ShOps.push_back(ShAmt);
15873 if (SVT == MVT::i32) {
15874 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15875 ShOps.push_back(DAG.getUNDEF(SVT));
15877 ShOps.push_back(DAG.getUNDEF(SVT));
15879 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15880 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15883 // The return type has to be a 128-bit type with the same element
15884 // type as the input type.
15885 MVT EltVT = VT.getVectorElementType();
15886 MVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15888 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15889 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15892 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15893 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15894 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15895 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15896 SDValue PreservedSrc,
15897 const X86Subtarget *Subtarget,
15898 SelectionDAG &DAG) {
15899 MVT VT = Op.getSimpleValueType();
15900 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
15902 unsigned OpcodeSelect = ISD::VSELECT;
15905 if (isAllOnes(Mask))
15908 if (MaskVT.bitsGT(Mask.getSimpleValueType())) {
15909 MVT newMaskVT = MVT::getIntegerVT(MaskVT.getSizeInBits());
15910 VMask = DAG.getBitcast(MaskVT,
15911 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15913 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
15914 Mask.getSimpleValueType().getSizeInBits());
15915 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15916 // are extracted by EXTRACT_SUBVECTOR.
15917 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15918 DAG.getBitcast(BitcastVT, Mask),
15919 DAG.getIntPtrConstant(0, dl));
15922 switch (Op.getOpcode()) {
15924 case X86ISD::PCMPEQM:
15925 case X86ISD::PCMPGTM:
15927 case X86ISD::CMPMU:
15928 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15929 case X86ISD::VFPCLASS:
15930 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
15931 case X86ISD::VTRUNC:
15932 case X86ISD::VTRUNCS:
15933 case X86ISD::VTRUNCUS:
15934 // We can't use ISD::VSELECT here because it is not always "Legal"
15935 // for the destination type. For example vpmovqb require only AVX512
15936 // and vselect that can operate on byte element type require BWI
15937 OpcodeSelect = X86ISD::SELECT;
15940 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15941 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15942 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
15945 /// \brief Creates an SDNode for a predicated scalar operation.
15946 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15947 /// The mask is coming as MVT::i8 and it should be truncated
15948 /// to MVT::i1 while lowering masking intrinsics.
15949 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15950 /// "X86select" instead of "vselect". We just can't create the "vselect" node
15951 /// for a scalar instruction.
15952 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15953 SDValue PreservedSrc,
15954 const X86Subtarget *Subtarget,
15955 SelectionDAG &DAG) {
15956 if (isAllOnes(Mask))
15959 MVT VT = Op.getSimpleValueType();
15961 // The mask should be of type MVT::i1
15962 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15964 if (Op.getOpcode() == X86ISD::FSETCC)
15965 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
15966 if (Op.getOpcode() == X86ISD::VFPCLASS)
15967 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
15969 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15970 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15971 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15974 static int getSEHRegistrationNodeSize(const Function *Fn) {
15975 if (!Fn->hasPersonalityFn())
15976 report_fatal_error(
15977 "querying registration node size for function without personality");
15978 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
15979 // WinEHStatePass for the full struct definition.
15980 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
15981 case EHPersonality::MSVC_X86SEH: return 24;
15982 case EHPersonality::MSVC_CXX: return 16;
15985 report_fatal_error("can only recover FP for MSVC EH personality functions");
15988 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
15989 /// function or when returning to a parent frame after catching an exception, we
15990 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
15991 /// Here's the math:
15992 /// RegNodeBase = EntryEBP - RegNodeSize
15993 /// ParentFP = RegNodeBase - RegNodeFrameOffset
15994 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
15995 /// subtracting the offset (negative on x86) takes us back to the parent FP.
15996 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
15997 SDValue EntryEBP) {
15998 MachineFunction &MF = DAG.getMachineFunction();
16001 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16002 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16004 // It's possible that the parent function no longer has a personality function
16005 // if the exceptional code was optimized away, in which case we just return
16006 // the incoming EBP.
16007 if (!Fn->hasPersonalityFn())
16010 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16012 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16014 MCSymbol *OffsetSym =
16015 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16016 GlobalValue::getRealLinkageName(Fn->getName()));
16017 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16018 SDValue RegNodeFrameOffset =
16019 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16021 // RegNodeBase = EntryEBP - RegNodeSize
16022 // ParentFP = RegNodeBase - RegNodeFrameOffset
16023 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16024 DAG.getConstant(RegNodeSize, dl, PtrVT));
16025 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
16028 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16029 SelectionDAG &DAG) {
16031 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16032 MVT VT = Op.getSimpleValueType();
16033 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16035 switch(IntrData->Type) {
16036 case INTR_TYPE_1OP:
16037 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16038 case INTR_TYPE_2OP:
16039 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16041 case INTR_TYPE_2OP_IMM8:
16042 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16043 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16044 case INTR_TYPE_3OP:
16045 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16046 Op.getOperand(2), Op.getOperand(3));
16047 case INTR_TYPE_4OP:
16048 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16049 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16050 case INTR_TYPE_1OP_MASK_RM: {
16051 SDValue Src = Op.getOperand(1);
16052 SDValue PassThru = Op.getOperand(2);
16053 SDValue Mask = Op.getOperand(3);
16054 SDValue RoundingMode;
16055 // We allways add rounding mode to the Node.
16056 // If the rounding mode is not specified, we add the
16057 // "current direction" mode.
16058 if (Op.getNumOperands() == 4)
16060 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16062 RoundingMode = Op.getOperand(4);
16063 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16064 if (IntrWithRoundingModeOpcode != 0)
16065 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16066 X86::STATIC_ROUNDING::CUR_DIRECTION)
16067 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16068 dl, Op.getValueType(), Src, RoundingMode),
16069 Mask, PassThru, Subtarget, DAG);
16070 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16072 Mask, PassThru, Subtarget, DAG);
16074 case INTR_TYPE_1OP_MASK: {
16075 SDValue Src = Op.getOperand(1);
16076 SDValue PassThru = Op.getOperand(2);
16077 SDValue Mask = Op.getOperand(3);
16078 // We add rounding mode to the Node when
16079 // - RM Opcode is specified and
16080 // - RM is not "current direction".
16081 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16082 if (IntrWithRoundingModeOpcode != 0) {
16083 SDValue Rnd = Op.getOperand(4);
16084 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16085 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16086 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16087 dl, Op.getValueType(),
16089 Mask, PassThru, Subtarget, DAG);
16092 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16093 Mask, PassThru, Subtarget, DAG);
16095 case INTR_TYPE_SCALAR_MASK: {
16096 SDValue Src1 = Op.getOperand(1);
16097 SDValue Src2 = Op.getOperand(2);
16098 SDValue passThru = Op.getOperand(3);
16099 SDValue Mask = Op.getOperand(4);
16100 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16101 Mask, passThru, Subtarget, DAG);
16103 case INTR_TYPE_SCALAR_MASK_RM: {
16104 SDValue Src1 = Op.getOperand(1);
16105 SDValue Src2 = Op.getOperand(2);
16106 SDValue Src0 = Op.getOperand(3);
16107 SDValue Mask = Op.getOperand(4);
16108 // There are 2 kinds of intrinsics in this group:
16109 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16110 // (2) With rounding mode and sae - 7 operands.
16111 if (Op.getNumOperands() == 6) {
16112 SDValue Sae = Op.getOperand(5);
16113 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16114 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16116 Mask, Src0, Subtarget, DAG);
16118 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16119 SDValue RoundingMode = Op.getOperand(5);
16120 SDValue Sae = Op.getOperand(6);
16121 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16122 RoundingMode, Sae),
16123 Mask, Src0, Subtarget, DAG);
16125 case INTR_TYPE_2OP_MASK:
16126 case INTR_TYPE_2OP_IMM8_MASK: {
16127 SDValue Src1 = Op.getOperand(1);
16128 SDValue Src2 = Op.getOperand(2);
16129 SDValue PassThru = Op.getOperand(3);
16130 SDValue Mask = Op.getOperand(4);
16132 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16133 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16135 // We specify 2 possible opcodes for intrinsics with rounding modes.
16136 // First, we check if the intrinsic may have non-default rounding mode,
16137 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16138 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16139 if (IntrWithRoundingModeOpcode != 0) {
16140 SDValue Rnd = Op.getOperand(5);
16141 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16142 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16143 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16144 dl, Op.getValueType(),
16146 Mask, PassThru, Subtarget, DAG);
16149 // TODO: Intrinsics should have fast-math-flags to propagate.
16150 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16151 Mask, PassThru, Subtarget, DAG);
16153 case INTR_TYPE_2OP_MASK_RM: {
16154 SDValue Src1 = Op.getOperand(1);
16155 SDValue Src2 = Op.getOperand(2);
16156 SDValue PassThru = Op.getOperand(3);
16157 SDValue Mask = Op.getOperand(4);
16158 // We specify 2 possible modes for intrinsics, with/without rounding
16160 // First, we check if the intrinsic have rounding mode (6 operands),
16161 // if not, we set rounding mode to "current".
16163 if (Op.getNumOperands() == 6)
16164 Rnd = Op.getOperand(5);
16166 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16167 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16169 Mask, PassThru, Subtarget, DAG);
16171 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16172 SDValue Src1 = Op.getOperand(1);
16173 SDValue Src2 = Op.getOperand(2);
16174 SDValue Src3 = Op.getOperand(3);
16175 SDValue PassThru = Op.getOperand(4);
16176 SDValue Mask = Op.getOperand(5);
16177 SDValue Sae = Op.getOperand(6);
16179 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16181 Mask, PassThru, Subtarget, DAG);
16183 case INTR_TYPE_3OP_MASK_RM: {
16184 SDValue Src1 = Op.getOperand(1);
16185 SDValue Src2 = Op.getOperand(2);
16186 SDValue Imm = Op.getOperand(3);
16187 SDValue PassThru = Op.getOperand(4);
16188 SDValue Mask = Op.getOperand(5);
16189 // We specify 2 possible modes for intrinsics, with/without rounding
16191 // First, we check if the intrinsic have rounding mode (7 operands),
16192 // if not, we set rounding mode to "current".
16194 if (Op.getNumOperands() == 7)
16195 Rnd = Op.getOperand(6);
16197 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16198 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16199 Src1, Src2, Imm, Rnd),
16200 Mask, PassThru, Subtarget, DAG);
16202 case INTR_TYPE_3OP_IMM8_MASK:
16203 case INTR_TYPE_3OP_MASK:
16204 case INSERT_SUBVEC: {
16205 SDValue Src1 = Op.getOperand(1);
16206 SDValue Src2 = Op.getOperand(2);
16207 SDValue Src3 = Op.getOperand(3);
16208 SDValue PassThru = Op.getOperand(4);
16209 SDValue Mask = Op.getOperand(5);
16211 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16212 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16213 else if (IntrData->Type == INSERT_SUBVEC) {
16214 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16215 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16216 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16217 Imm *= Src2.getSimpleValueType().getVectorNumElements();
16218 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16221 // We specify 2 possible opcodes for intrinsics with rounding modes.
16222 // First, we check if the intrinsic may have non-default rounding mode,
16223 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16224 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16225 if (IntrWithRoundingModeOpcode != 0) {
16226 SDValue Rnd = Op.getOperand(6);
16227 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16228 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16229 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16230 dl, Op.getValueType(),
16231 Src1, Src2, Src3, Rnd),
16232 Mask, PassThru, Subtarget, DAG);
16235 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16237 Mask, PassThru, Subtarget, DAG);
16239 case VPERM_3OP_MASKZ:
16240 case VPERM_3OP_MASK:
16243 case FMA_OP_MASK: {
16244 SDValue Src1 = Op.getOperand(1);
16245 SDValue Src2 = Op.getOperand(2);
16246 SDValue Src3 = Op.getOperand(3);
16247 SDValue Mask = Op.getOperand(4);
16248 MVT VT = Op.getSimpleValueType();
16249 SDValue PassThru = SDValue();
16251 // set PassThru element
16252 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
16253 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16254 else if (IntrData->Type == FMA_OP_MASK3)
16259 // We specify 2 possible opcodes for intrinsics with rounding modes.
16260 // First, we check if the intrinsic may have non-default rounding mode,
16261 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16262 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16263 if (IntrWithRoundingModeOpcode != 0) {
16264 SDValue Rnd = Op.getOperand(5);
16265 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16266 X86::STATIC_ROUNDING::CUR_DIRECTION)
16267 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16268 dl, Op.getValueType(),
16269 Src1, Src2, Src3, Rnd),
16270 Mask, PassThru, Subtarget, DAG);
16272 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16273 dl, Op.getValueType(),
16275 Mask, PassThru, Subtarget, DAG);
16277 case TERLOG_OP_MASK:
16278 case TERLOG_OP_MASKZ: {
16279 SDValue Src1 = Op.getOperand(1);
16280 SDValue Src2 = Op.getOperand(2);
16281 SDValue Src3 = Op.getOperand(3);
16282 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16283 SDValue Mask = Op.getOperand(5);
16284 MVT VT = Op.getSimpleValueType();
16285 SDValue PassThru = Src1;
16286 // Set PassThru element.
16287 if (IntrData->Type == TERLOG_OP_MASKZ)
16288 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16290 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16291 Src1, Src2, Src3, Src4),
16292 Mask, PassThru, Subtarget, DAG);
16295 // FPclass intrinsics with mask
16296 SDValue Src1 = Op.getOperand(1);
16297 MVT VT = Src1.getSimpleValueType();
16298 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16299 SDValue Imm = Op.getOperand(2);
16300 SDValue Mask = Op.getOperand(3);
16301 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16302 Mask.getSimpleValueType().getSizeInBits());
16303 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16304 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16305 DAG.getTargetConstant(0, dl, MaskVT),
16307 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16308 DAG.getUNDEF(BitcastVT), FPclassMask,
16309 DAG.getIntPtrConstant(0, dl));
16310 return DAG.getBitcast(Op.getValueType(), Res);
16313 SDValue Src1 = Op.getOperand(1);
16314 SDValue Imm = Op.getOperand(2);
16315 SDValue Mask = Op.getOperand(3);
16316 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16317 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16318 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16319 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16322 case CMP_MASK_CC: {
16323 // Comparison intrinsics with masks.
16324 // Example of transformation:
16325 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16326 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16328 // (v8i1 (insert_subvector undef,
16329 // (v2i1 (and (PCMPEQM %a, %b),
16330 // (extract_subvector
16331 // (v8i1 (bitcast %mask)), 0))), 0))))
16332 MVT VT = Op.getOperand(1).getSimpleValueType();
16333 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16334 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16335 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16336 Mask.getSimpleValueType().getSizeInBits());
16338 if (IntrData->Type == CMP_MASK_CC) {
16339 SDValue CC = Op.getOperand(3);
16340 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16341 // We specify 2 possible opcodes for intrinsics with rounding modes.
16342 // First, we check if the intrinsic may have non-default rounding mode,
16343 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16344 if (IntrData->Opc1 != 0) {
16345 SDValue Rnd = Op.getOperand(5);
16346 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16347 X86::STATIC_ROUNDING::CUR_DIRECTION)
16348 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16349 Op.getOperand(2), CC, Rnd);
16351 //default rounding mode
16353 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16354 Op.getOperand(2), CC);
16357 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16358 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16361 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16362 DAG.getTargetConstant(0, dl,
16365 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16366 DAG.getUNDEF(BitcastVT), CmpMask,
16367 DAG.getIntPtrConstant(0, dl));
16368 return DAG.getBitcast(Op.getValueType(), Res);
16370 case CMP_MASK_SCALAR_CC: {
16371 SDValue Src1 = Op.getOperand(1);
16372 SDValue Src2 = Op.getOperand(2);
16373 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16374 SDValue Mask = Op.getOperand(4);
16377 if (IntrData->Opc1 != 0) {
16378 SDValue Rnd = Op.getOperand(5);
16379 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16380 X86::STATIC_ROUNDING::CUR_DIRECTION)
16381 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16383 //default rounding mode
16385 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16387 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16388 DAG.getTargetConstant(0, dl,
16392 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16393 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16394 DAG.getValueType(MVT::i1));
16396 case COMI: { // Comparison intrinsics
16397 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16398 SDValue LHS = Op.getOperand(1);
16399 SDValue RHS = Op.getOperand(2);
16400 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16401 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16402 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16403 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16404 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16405 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16408 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16409 Op.getOperand(1), Op.getOperand(2), DAG);
16411 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16412 Op.getSimpleValueType(),
16414 Op.getOperand(2), DAG),
16415 Op.getOperand(4), Op.getOperand(3), Subtarget,
16417 case COMPRESS_EXPAND_IN_REG: {
16418 SDValue Mask = Op.getOperand(3);
16419 SDValue DataToCompress = Op.getOperand(1);
16420 SDValue PassThru = Op.getOperand(2);
16421 if (isAllOnes(Mask)) // return data as is
16422 return Op.getOperand(1);
16424 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16426 Mask, PassThru, Subtarget, DAG);
16429 SDValue Mask = Op.getOperand(3);
16430 MVT VT = Op.getSimpleValueType();
16431 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16432 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16433 Mask.getSimpleValueType().getSizeInBits());
16435 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16436 DAG.getBitcast(BitcastVT, Mask),
16437 DAG.getIntPtrConstant(0, dl));
16438 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16447 default: return SDValue(); // Don't custom lower most intrinsics.
16449 case Intrinsic::x86_avx2_permd:
16450 case Intrinsic::x86_avx2_permps:
16451 // Operands intentionally swapped. Mask is last operand to intrinsic,
16452 // but second operand for node/instruction.
16453 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16454 Op.getOperand(2), Op.getOperand(1));
16456 // ptest and testp intrinsics. The intrinsic these come from are designed to
16457 // return an integer value, not just an instruction so lower it to the ptest
16458 // or testp pattern and a setcc for the result.
16459 case Intrinsic::x86_sse41_ptestz:
16460 case Intrinsic::x86_sse41_ptestc:
16461 case Intrinsic::x86_sse41_ptestnzc:
16462 case Intrinsic::x86_avx_ptestz_256:
16463 case Intrinsic::x86_avx_ptestc_256:
16464 case Intrinsic::x86_avx_ptestnzc_256:
16465 case Intrinsic::x86_avx_vtestz_ps:
16466 case Intrinsic::x86_avx_vtestc_ps:
16467 case Intrinsic::x86_avx_vtestnzc_ps:
16468 case Intrinsic::x86_avx_vtestz_pd:
16469 case Intrinsic::x86_avx_vtestc_pd:
16470 case Intrinsic::x86_avx_vtestnzc_pd:
16471 case Intrinsic::x86_avx_vtestz_ps_256:
16472 case Intrinsic::x86_avx_vtestc_ps_256:
16473 case Intrinsic::x86_avx_vtestnzc_ps_256:
16474 case Intrinsic::x86_avx_vtestz_pd_256:
16475 case Intrinsic::x86_avx_vtestc_pd_256:
16476 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16477 bool IsTestPacked = false;
16480 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16481 case Intrinsic::x86_avx_vtestz_ps:
16482 case Intrinsic::x86_avx_vtestz_pd:
16483 case Intrinsic::x86_avx_vtestz_ps_256:
16484 case Intrinsic::x86_avx_vtestz_pd_256:
16485 IsTestPacked = true; // Fallthrough
16486 case Intrinsic::x86_sse41_ptestz:
16487 case Intrinsic::x86_avx_ptestz_256:
16489 X86CC = X86::COND_E;
16491 case Intrinsic::x86_avx_vtestc_ps:
16492 case Intrinsic::x86_avx_vtestc_pd:
16493 case Intrinsic::x86_avx_vtestc_ps_256:
16494 case Intrinsic::x86_avx_vtestc_pd_256:
16495 IsTestPacked = true; // Fallthrough
16496 case Intrinsic::x86_sse41_ptestc:
16497 case Intrinsic::x86_avx_ptestc_256:
16499 X86CC = X86::COND_B;
16501 case Intrinsic::x86_avx_vtestnzc_ps:
16502 case Intrinsic::x86_avx_vtestnzc_pd:
16503 case Intrinsic::x86_avx_vtestnzc_ps_256:
16504 case Intrinsic::x86_avx_vtestnzc_pd_256:
16505 IsTestPacked = true; // Fallthrough
16506 case Intrinsic::x86_sse41_ptestnzc:
16507 case Intrinsic::x86_avx_ptestnzc_256:
16509 X86CC = X86::COND_A;
16513 SDValue LHS = Op.getOperand(1);
16514 SDValue RHS = Op.getOperand(2);
16515 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16516 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16517 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16518 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16519 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16521 case Intrinsic::x86_avx512_kortestz_w:
16522 case Intrinsic::x86_avx512_kortestc_w: {
16523 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16524 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16525 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16526 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16527 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16528 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16529 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16532 case Intrinsic::x86_sse42_pcmpistria128:
16533 case Intrinsic::x86_sse42_pcmpestria128:
16534 case Intrinsic::x86_sse42_pcmpistric128:
16535 case Intrinsic::x86_sse42_pcmpestric128:
16536 case Intrinsic::x86_sse42_pcmpistrio128:
16537 case Intrinsic::x86_sse42_pcmpestrio128:
16538 case Intrinsic::x86_sse42_pcmpistris128:
16539 case Intrinsic::x86_sse42_pcmpestris128:
16540 case Intrinsic::x86_sse42_pcmpistriz128:
16541 case Intrinsic::x86_sse42_pcmpestriz128: {
16545 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16546 case Intrinsic::x86_sse42_pcmpistria128:
16547 Opcode = X86ISD::PCMPISTRI;
16548 X86CC = X86::COND_A;
16550 case Intrinsic::x86_sse42_pcmpestria128:
16551 Opcode = X86ISD::PCMPESTRI;
16552 X86CC = X86::COND_A;
16554 case Intrinsic::x86_sse42_pcmpistric128:
16555 Opcode = X86ISD::PCMPISTRI;
16556 X86CC = X86::COND_B;
16558 case Intrinsic::x86_sse42_pcmpestric128:
16559 Opcode = X86ISD::PCMPESTRI;
16560 X86CC = X86::COND_B;
16562 case Intrinsic::x86_sse42_pcmpistrio128:
16563 Opcode = X86ISD::PCMPISTRI;
16564 X86CC = X86::COND_O;
16566 case Intrinsic::x86_sse42_pcmpestrio128:
16567 Opcode = X86ISD::PCMPESTRI;
16568 X86CC = X86::COND_O;
16570 case Intrinsic::x86_sse42_pcmpistris128:
16571 Opcode = X86ISD::PCMPISTRI;
16572 X86CC = X86::COND_S;
16574 case Intrinsic::x86_sse42_pcmpestris128:
16575 Opcode = X86ISD::PCMPESTRI;
16576 X86CC = X86::COND_S;
16578 case Intrinsic::x86_sse42_pcmpistriz128:
16579 Opcode = X86ISD::PCMPISTRI;
16580 X86CC = X86::COND_E;
16582 case Intrinsic::x86_sse42_pcmpestriz128:
16583 Opcode = X86ISD::PCMPESTRI;
16584 X86CC = X86::COND_E;
16587 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16588 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16589 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16590 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16591 DAG.getConstant(X86CC, dl, MVT::i8),
16592 SDValue(PCMP.getNode(), 1));
16593 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16596 case Intrinsic::x86_sse42_pcmpistri128:
16597 case Intrinsic::x86_sse42_pcmpestri128: {
16599 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16600 Opcode = X86ISD::PCMPISTRI;
16602 Opcode = X86ISD::PCMPESTRI;
16604 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16605 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16606 return DAG.getNode(Opcode, dl, VTs, NewOps);
16609 case Intrinsic::x86_seh_lsda: {
16610 // Compute the symbol for the LSDA. We know it'll get emitted later.
16611 MachineFunction &MF = DAG.getMachineFunction();
16612 SDValue Op1 = Op.getOperand(1);
16613 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16614 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16615 GlobalValue::getRealLinkageName(Fn->getName()));
16617 // Generate a simple absolute symbol reference. This intrinsic is only
16618 // supported on 32-bit Windows, which isn't PIC.
16619 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16620 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16623 case Intrinsic::x86_seh_recoverfp: {
16624 SDValue FnOp = Op.getOperand(1);
16625 SDValue IncomingFPOp = Op.getOperand(2);
16626 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16627 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16629 report_fatal_error(
16630 "llvm.x86.seh.recoverfp must take a function as the first argument");
16631 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16634 case Intrinsic::localaddress: {
16635 // Returns one of the stack, base, or frame pointer registers, depending on
16636 // which is used to reference local variables.
16637 MachineFunction &MF = DAG.getMachineFunction();
16638 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16640 if (RegInfo->hasBasePointer(MF))
16641 Reg = RegInfo->getBaseRegister();
16642 else // This function handles the SP or FP case.
16643 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16644 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16649 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16650 SDValue Src, SDValue Mask, SDValue Base,
16651 SDValue Index, SDValue ScaleOp, SDValue Chain,
16652 const X86Subtarget * Subtarget) {
16654 auto *C = cast<ConstantSDNode>(ScaleOp);
16655 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16656 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16657 Index.getSimpleValueType().getVectorNumElements());
16659 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16661 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16663 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16664 Mask.getSimpleValueType().getSizeInBits());
16666 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16667 // are extracted by EXTRACT_SUBVECTOR.
16668 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16669 DAG.getBitcast(BitcastVT, Mask),
16670 DAG.getIntPtrConstant(0, dl));
16672 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16673 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16674 SDValue Segment = DAG.getRegister(0, MVT::i32);
16675 if (Src.getOpcode() == ISD::UNDEF)
16676 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16677 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16678 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16679 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16680 return DAG.getMergeValues(RetOps, dl);
16683 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16684 SDValue Src, SDValue Mask, SDValue Base,
16685 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16687 auto *C = cast<ConstantSDNode>(ScaleOp);
16688 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16689 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16690 SDValue Segment = DAG.getRegister(0, MVT::i32);
16691 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16692 Index.getSimpleValueType().getVectorNumElements());
16694 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16696 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16698 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16699 Mask.getSimpleValueType().getSizeInBits());
16701 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16702 // are extracted by EXTRACT_SUBVECTOR.
16703 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16704 DAG.getBitcast(BitcastVT, Mask),
16705 DAG.getIntPtrConstant(0, dl));
16707 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16708 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16709 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16710 return SDValue(Res, 1);
16713 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16714 SDValue Mask, SDValue Base, SDValue Index,
16715 SDValue ScaleOp, SDValue Chain) {
16717 auto *C = cast<ConstantSDNode>(ScaleOp);
16718 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16719 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16720 SDValue Segment = DAG.getRegister(0, MVT::i32);
16722 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16724 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16726 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16728 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16729 //SDVTList VTs = DAG.getVTList(MVT::Other);
16730 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16731 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16732 return SDValue(Res, 0);
16735 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16736 // read performance monitor counters (x86_rdpmc).
16737 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16738 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16739 SmallVectorImpl<SDValue> &Results) {
16740 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16741 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16744 // The ECX register is used to select the index of the performance counter
16746 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16748 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16750 // Reads the content of a 64-bit performance counter and returns it in the
16751 // registers EDX:EAX.
16752 if (Subtarget->is64Bit()) {
16753 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16754 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16757 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16758 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16761 Chain = HI.getValue(1);
16763 if (Subtarget->is64Bit()) {
16764 // The EAX register is loaded with the low-order 32 bits. The EDX register
16765 // is loaded with the supported high-order bits of the counter.
16766 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16767 DAG.getConstant(32, DL, MVT::i8));
16768 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16769 Results.push_back(Chain);
16773 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16774 SDValue Ops[] = { LO, HI };
16775 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16776 Results.push_back(Pair);
16777 Results.push_back(Chain);
16780 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16781 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16782 // also used to custom lower READCYCLECOUNTER nodes.
16783 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16784 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16785 SmallVectorImpl<SDValue> &Results) {
16786 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16787 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16790 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16791 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16792 // and the EAX register is loaded with the low-order 32 bits.
16793 if (Subtarget->is64Bit()) {
16794 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16795 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16798 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16799 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16802 SDValue Chain = HI.getValue(1);
16804 if (Opcode == X86ISD::RDTSCP_DAG) {
16805 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16807 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16808 // the ECX register. Add 'ecx' explicitly to the chain.
16809 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16811 // Explicitly store the content of ECX at the location passed in input
16812 // to the 'rdtscp' intrinsic.
16813 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16814 MachinePointerInfo(), false, false, 0);
16817 if (Subtarget->is64Bit()) {
16818 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16819 // the EAX register is loaded with the low-order 32 bits.
16820 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16821 DAG.getConstant(32, DL, MVT::i8));
16822 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16823 Results.push_back(Chain);
16827 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16828 SDValue Ops[] = { LO, HI };
16829 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16830 Results.push_back(Pair);
16831 Results.push_back(Chain);
16834 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16835 SelectionDAG &DAG) {
16836 SmallVector<SDValue, 2> Results;
16838 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16840 return DAG.getMergeValues(Results, DL);
16843 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16844 SelectionDAG &DAG) {
16845 MachineFunction &MF = DAG.getMachineFunction();
16846 const Function *Fn = MF.getFunction();
16848 SDValue Chain = Op.getOperand(0);
16850 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16851 "using llvm.x86.seh.restoreframe requires a frame pointer");
16853 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16854 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16856 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16857 unsigned FrameReg =
16858 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16859 unsigned SPReg = RegInfo->getStackRegister();
16860 unsigned SlotSize = RegInfo->getSlotSize();
16862 // Get incoming EBP.
16863 SDValue IncomingEBP =
16864 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16866 // SP is saved in the first field of every registration node, so load
16867 // [EBP-RegNodeSize] into SP.
16868 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16869 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16870 DAG.getConstant(-RegNodeSize, dl, VT));
16872 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16873 false, VT.getScalarSizeInBits() / 8);
16874 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16876 if (!RegInfo->needsStackRealignment(MF)) {
16877 // Adjust EBP to point back to the original frame position.
16878 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16879 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16881 assert(RegInfo->hasBasePointer(MF) &&
16882 "functions with Win32 EH must use frame or base pointer register");
16884 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16885 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16886 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16888 // Reload the spilled EBP value, now that the stack and base pointers are
16890 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16891 X86FI->setHasSEHFramePtrSave(true);
16892 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16893 X86FI->setSEHFramePtrSaveIndex(FI);
16894 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16895 MachinePointerInfo(), false, false, false,
16896 VT.getScalarSizeInBits() / 8);
16897 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16903 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16904 /// return truncate Store/MaskedStore Node
16905 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16909 SDValue Mask = Op.getOperand(4);
16910 SDValue DataToTruncate = Op.getOperand(3);
16911 SDValue Addr = Op.getOperand(2);
16912 SDValue Chain = Op.getOperand(0);
16914 MVT VT = DataToTruncate.getSimpleValueType();
16915 MVT SVT = MVT::getVectorVT(ElementType, VT.getVectorNumElements());
16917 if (isAllOnes(Mask)) // return just a truncate store
16918 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
16919 MachinePointerInfo(), SVT, false, false,
16920 SVT.getScalarSizeInBits()/8);
16922 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16923 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16924 Mask.getSimpleValueType().getSizeInBits());
16925 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16926 // are extracted by EXTRACT_SUBVECTOR.
16927 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16928 DAG.getBitcast(BitcastVT, Mask),
16929 DAG.getIntPtrConstant(0, dl));
16931 MachineMemOperand *MMO = DAG.getMachineFunction().
16932 getMachineMemOperand(MachinePointerInfo(),
16933 MachineMemOperand::MOStore, SVT.getStoreSize(),
16934 SVT.getScalarSizeInBits()/8);
16936 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
16937 VMask, SVT, MMO, true);
16940 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16941 SelectionDAG &DAG) {
16942 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16944 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16946 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
16947 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16952 switch(IntrData->Type) {
16953 default: llvm_unreachable("Unknown Intrinsic Type");
16956 // Emit the node with the right value type.
16957 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16958 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16960 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16961 // Otherwise return the value from Rand, which is always 0, casted to i32.
16962 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16963 DAG.getConstant(1, dl, Op->getValueType(1)),
16964 DAG.getConstant(X86::COND_B, dl, MVT::i32),
16965 SDValue(Result.getNode(), 1) };
16966 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16967 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16970 // Return { result, isValid, chain }.
16971 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16972 SDValue(Result.getNode(), 2));
16975 //gather(v1, mask, index, base, scale);
16976 SDValue Chain = Op.getOperand(0);
16977 SDValue Src = Op.getOperand(2);
16978 SDValue Base = Op.getOperand(3);
16979 SDValue Index = Op.getOperand(4);
16980 SDValue Mask = Op.getOperand(5);
16981 SDValue Scale = Op.getOperand(6);
16982 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
16986 //scatter(base, mask, index, v1, scale);
16987 SDValue Chain = Op.getOperand(0);
16988 SDValue Base = Op.getOperand(2);
16989 SDValue Mask = Op.getOperand(3);
16990 SDValue Index = Op.getOperand(4);
16991 SDValue Src = Op.getOperand(5);
16992 SDValue Scale = Op.getOperand(6);
16993 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
16997 SDValue Hint = Op.getOperand(6);
16998 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
16999 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17000 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17001 SDValue Chain = Op.getOperand(0);
17002 SDValue Mask = Op.getOperand(2);
17003 SDValue Index = Op.getOperand(3);
17004 SDValue Base = Op.getOperand(4);
17005 SDValue Scale = Op.getOperand(5);
17006 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17008 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17010 SmallVector<SDValue, 2> Results;
17011 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17013 return DAG.getMergeValues(Results, dl);
17015 // Read Performance Monitoring Counters.
17017 SmallVector<SDValue, 2> Results;
17018 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17019 return DAG.getMergeValues(Results, dl);
17021 // XTEST intrinsics.
17023 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17024 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17025 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17026 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17028 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17029 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17030 Ret, SDValue(InTrans.getNode(), 1));
17034 SmallVector<SDValue, 2> Results;
17035 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17036 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17037 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17038 DAG.getConstant(-1, dl, MVT::i8));
17039 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17040 Op.getOperand(4), GenCF.getValue(1));
17041 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17042 Op.getOperand(5), MachinePointerInfo(),
17044 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17045 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17047 Results.push_back(SetCC);
17048 Results.push_back(Store);
17049 return DAG.getMergeValues(Results, dl);
17051 case COMPRESS_TO_MEM: {
17053 SDValue Mask = Op.getOperand(4);
17054 SDValue DataToCompress = Op.getOperand(3);
17055 SDValue Addr = Op.getOperand(2);
17056 SDValue Chain = Op.getOperand(0);
17058 MVT VT = DataToCompress.getSimpleValueType();
17059 if (isAllOnes(Mask)) // return just a store
17060 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17061 MachinePointerInfo(), false, false,
17062 VT.getScalarSizeInBits()/8);
17064 SDValue Compressed =
17065 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17066 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17067 return DAG.getStore(Chain, dl, Compressed, Addr,
17068 MachinePointerInfo(), false, false,
17069 VT.getScalarSizeInBits()/8);
17071 case TRUNCATE_TO_MEM_VI8:
17072 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17073 case TRUNCATE_TO_MEM_VI16:
17074 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17075 case TRUNCATE_TO_MEM_VI32:
17076 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17077 case EXPAND_FROM_MEM: {
17079 SDValue Mask = Op.getOperand(4);
17080 SDValue PassThru = Op.getOperand(3);
17081 SDValue Addr = Op.getOperand(2);
17082 SDValue Chain = Op.getOperand(0);
17083 MVT VT = Op.getSimpleValueType();
17085 if (isAllOnes(Mask)) // return just a load
17086 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17087 false, VT.getScalarSizeInBits()/8);
17089 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17090 false, false, false,
17091 VT.getScalarSizeInBits()/8);
17093 SDValue Results[] = {
17094 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17095 Mask, PassThru, Subtarget, DAG), Chain};
17096 return DAG.getMergeValues(Results, dl);
17101 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17102 SelectionDAG &DAG) const {
17103 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17104 MFI->setReturnAddressIsTaken(true);
17106 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17109 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17111 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17114 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17115 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17116 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17117 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17118 DAG.getNode(ISD::ADD, dl, PtrVT,
17119 FrameAddr, Offset),
17120 MachinePointerInfo(), false, false, false, 0);
17123 // Just load the return address.
17124 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17125 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17126 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17129 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17130 MachineFunction &MF = DAG.getMachineFunction();
17131 MachineFrameInfo *MFI = MF.getFrameInfo();
17132 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17133 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17134 EVT VT = Op.getValueType();
17136 MFI->setFrameAddressIsTaken(true);
17138 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17139 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17140 // is not possible to crawl up the stack without looking at the unwind codes
17142 int FrameAddrIndex = FuncInfo->getFAIndex();
17143 if (!FrameAddrIndex) {
17144 // Set up a frame object for the return address.
17145 unsigned SlotSize = RegInfo->getSlotSize();
17146 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17147 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17148 FuncInfo->setFAIndex(FrameAddrIndex);
17150 return DAG.getFrameIndex(FrameAddrIndex, VT);
17153 unsigned FrameReg =
17154 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17155 SDLoc dl(Op); // FIXME probably not meaningful
17156 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17157 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17158 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17159 "Invalid Frame Register!");
17160 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17162 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17163 MachinePointerInfo(),
17164 false, false, false, 0);
17168 // FIXME? Maybe this could be a TableGen attribute on some registers and
17169 // this table could be generated automatically from RegInfo.
17170 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17171 SelectionDAG &DAG) const {
17172 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17173 const MachineFunction &MF = DAG.getMachineFunction();
17175 unsigned Reg = StringSwitch<unsigned>(RegName)
17176 .Case("esp", X86::ESP)
17177 .Case("rsp", X86::RSP)
17178 .Case("ebp", X86::EBP)
17179 .Case("rbp", X86::RBP)
17182 if (Reg == X86::EBP || Reg == X86::RBP) {
17183 if (!TFI.hasFP(MF))
17184 report_fatal_error("register " + StringRef(RegName) +
17185 " is allocatable: function has no frame pointer");
17188 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17189 unsigned FrameReg =
17190 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17191 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17192 "Invalid Frame Register!");
17200 report_fatal_error("Invalid register name global variable");
17203 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17204 SelectionDAG &DAG) const {
17205 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17206 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17209 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17210 SDValue Chain = Op.getOperand(0);
17211 SDValue Offset = Op.getOperand(1);
17212 SDValue Handler = Op.getOperand(2);
17215 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17216 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17217 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17218 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17219 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17220 "Invalid Frame Register!");
17221 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17222 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17224 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17225 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17227 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17228 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17230 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17232 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17233 DAG.getRegister(StoreAddrReg, PtrVT));
17236 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17237 SelectionDAG &DAG) const {
17239 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17240 DAG.getVTList(MVT::i32, MVT::Other),
17241 Op.getOperand(0), Op.getOperand(1));
17244 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17245 SelectionDAG &DAG) const {
17247 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17248 Op.getOperand(0), Op.getOperand(1));
17251 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17252 return Op.getOperand(0);
17255 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17256 SelectionDAG &DAG) const {
17257 SDValue Root = Op.getOperand(0);
17258 SDValue Trmp = Op.getOperand(1); // trampoline
17259 SDValue FPtr = Op.getOperand(2); // nested function
17260 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17263 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17264 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17266 if (Subtarget->is64Bit()) {
17267 SDValue OutChains[6];
17269 // Large code-model.
17270 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17271 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17273 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17274 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17276 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17278 // Load the pointer to the nested function into R11.
17279 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17280 SDValue Addr = Trmp;
17281 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17282 Addr, MachinePointerInfo(TrmpAddr),
17285 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17286 DAG.getConstant(2, dl, MVT::i64));
17287 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17288 MachinePointerInfo(TrmpAddr, 2),
17291 // Load the 'nest' parameter value into R10.
17292 // R10 is specified in X86CallingConv.td
17293 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17294 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17295 DAG.getConstant(10, dl, MVT::i64));
17296 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17297 Addr, MachinePointerInfo(TrmpAddr, 10),
17300 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17301 DAG.getConstant(12, dl, MVT::i64));
17302 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17303 MachinePointerInfo(TrmpAddr, 12),
17306 // Jump to the nested function.
17307 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17308 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17309 DAG.getConstant(20, dl, MVT::i64));
17310 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17311 Addr, MachinePointerInfo(TrmpAddr, 20),
17314 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17315 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17316 DAG.getConstant(22, dl, MVT::i64));
17317 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17318 Addr, MachinePointerInfo(TrmpAddr, 22),
17321 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17323 const Function *Func =
17324 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17325 CallingConv::ID CC = Func->getCallingConv();
17330 llvm_unreachable("Unsupported calling convention");
17331 case CallingConv::C:
17332 case CallingConv::X86_StdCall: {
17333 // Pass 'nest' parameter in ECX.
17334 // Must be kept in sync with X86CallingConv.td
17335 NestReg = X86::ECX;
17337 // Check that ECX wasn't needed by an 'inreg' parameter.
17338 FunctionType *FTy = Func->getFunctionType();
17339 const AttributeSet &Attrs = Func->getAttributes();
17341 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17342 unsigned InRegCount = 0;
17345 for (FunctionType::param_iterator I = FTy->param_begin(),
17346 E = FTy->param_end(); I != E; ++I, ++Idx)
17347 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17348 auto &DL = DAG.getDataLayout();
17349 // FIXME: should only count parameters that are lowered to integers.
17350 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17353 if (InRegCount > 2) {
17354 report_fatal_error("Nest register in use - reduce number of inreg"
17360 case CallingConv::X86_FastCall:
17361 case CallingConv::X86_ThisCall:
17362 case CallingConv::Fast:
17363 // Pass 'nest' parameter in EAX.
17364 // Must be kept in sync with X86CallingConv.td
17365 NestReg = X86::EAX;
17369 SDValue OutChains[4];
17370 SDValue Addr, Disp;
17372 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17373 DAG.getConstant(10, dl, MVT::i32));
17374 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17376 // This is storing the opcode for MOV32ri.
17377 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17378 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17379 OutChains[0] = DAG.getStore(Root, dl,
17380 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17381 Trmp, MachinePointerInfo(TrmpAddr),
17384 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17385 DAG.getConstant(1, dl, MVT::i32));
17386 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17387 MachinePointerInfo(TrmpAddr, 1),
17390 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17391 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17392 DAG.getConstant(5, dl, MVT::i32));
17393 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17394 Addr, MachinePointerInfo(TrmpAddr, 5),
17397 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17398 DAG.getConstant(6, dl, MVT::i32));
17399 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17400 MachinePointerInfo(TrmpAddr, 6),
17403 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17407 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17408 SelectionDAG &DAG) const {
17410 The rounding mode is in bits 11:10 of FPSR, and has the following
17412 00 Round to nearest
17417 FLT_ROUNDS, on the other hand, expects the following:
17424 To perform the conversion, we do:
17425 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17428 MachineFunction &MF = DAG.getMachineFunction();
17429 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17430 unsigned StackAlignment = TFI.getStackAlignment();
17431 MVT VT = Op.getSimpleValueType();
17434 // Save FP Control Word to stack slot
17435 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17436 SDValue StackSlot =
17437 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17439 MachineMemOperand *MMO =
17440 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17441 MachineMemOperand::MOStore, 2, 2);
17443 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17444 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17445 DAG.getVTList(MVT::Other),
17446 Ops, MVT::i16, MMO);
17448 // Load FP Control Word from stack slot
17449 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17450 MachinePointerInfo(), false, false, false, 0);
17452 // Transform as necessary
17454 DAG.getNode(ISD::SRL, DL, MVT::i16,
17455 DAG.getNode(ISD::AND, DL, MVT::i16,
17456 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17457 DAG.getConstant(11, DL, MVT::i8));
17459 DAG.getNode(ISD::SRL, DL, MVT::i16,
17460 DAG.getNode(ISD::AND, DL, MVT::i16,
17461 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17462 DAG.getConstant(9, DL, MVT::i8));
17465 DAG.getNode(ISD::AND, DL, MVT::i16,
17466 DAG.getNode(ISD::ADD, DL, MVT::i16,
17467 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17468 DAG.getConstant(1, DL, MVT::i16)),
17469 DAG.getConstant(3, DL, MVT::i16));
17471 return DAG.getNode((VT.getSizeInBits() < 16 ?
17472 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17475 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17477 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17478 // to 512-bit vector.
17479 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17480 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17481 // split the vector, perform operation on it's Lo a Hi part and
17482 // concatenate the results.
17483 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17485 MVT VT = Op.getSimpleValueType();
17486 MVT EltVT = VT.getVectorElementType();
17487 unsigned NumElems = VT.getVectorNumElements();
17489 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17490 // Extend to 512 bit vector.
17491 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17492 "Unsupported value type for operation");
17494 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17495 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17496 DAG.getUNDEF(NewVT),
17498 DAG.getIntPtrConstant(0, dl));
17499 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17501 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17502 DAG.getIntPtrConstant(0, dl));
17505 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17506 "Unsupported element type");
17508 if (16 < NumElems) {
17509 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17511 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17512 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17514 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17515 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17517 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17520 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17522 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17523 "Unsupported value type for operation");
17525 // Use native supported vector instruction vplzcntd.
17526 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17527 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17528 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17529 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
17531 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
17534 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17535 SelectionDAG &DAG) {
17536 MVT VT = Op.getSimpleValueType();
17538 unsigned NumBits = VT.getSizeInBits();
17541 if (VT.isVector() && Subtarget->hasAVX512())
17542 return LowerVectorCTLZ_AVX512(Op, DAG);
17544 Op = Op.getOperand(0);
17545 if (VT == MVT::i8) {
17546 // Zero extend to i32 since there is not an i8 bsr.
17548 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17551 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17552 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17553 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17555 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17558 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17559 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17562 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17564 // Finally xor with NumBits-1.
17565 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17566 DAG.getConstant(NumBits - 1, dl, OpVT));
17569 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17573 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
17574 SelectionDAG &DAG) {
17575 MVT VT = Op.getSimpleValueType();
17577 unsigned NumBits = VT.getSizeInBits();
17580 if (VT.isVector() && Subtarget->hasAVX512())
17581 return LowerVectorCTLZ_AVX512(Op, DAG);
17583 Op = Op.getOperand(0);
17584 if (VT == MVT::i8) {
17585 // Zero extend to i32 since there is not an i8 bsr.
17587 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17590 // Issue a bsr (scan bits in reverse).
17591 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17592 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17594 // And xor with NumBits-1.
17595 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17596 DAG.getConstant(NumBits - 1, dl, OpVT));
17599 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17603 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17604 MVT VT = Op.getSimpleValueType();
17605 unsigned NumBits = VT.getScalarSizeInBits();
17608 if (VT.isVector()) {
17609 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17611 SDValue N0 = Op.getOperand(0);
17612 SDValue Zero = DAG.getConstant(0, dl, VT);
17614 // lsb(x) = (x & -x)
17615 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17616 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17618 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17619 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17620 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17621 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17622 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17623 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17626 // cttz(x) = ctpop(lsb - 1)
17627 SDValue One = DAG.getConstant(1, dl, VT);
17628 return DAG.getNode(ISD::CTPOP, dl, VT,
17629 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17632 assert(Op.getOpcode() == ISD::CTTZ &&
17633 "Only scalar CTTZ requires custom lowering");
17635 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17636 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17637 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17639 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17642 DAG.getConstant(NumBits, dl, VT),
17643 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17646 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17649 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17650 // ones, and then concatenate the result back.
17651 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17652 MVT VT = Op.getSimpleValueType();
17654 assert(VT.is256BitVector() && VT.isInteger() &&
17655 "Unsupported value type for operation");
17657 unsigned NumElems = VT.getVectorNumElements();
17660 // Extract the LHS vectors
17661 SDValue LHS = Op.getOperand(0);
17662 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17663 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17665 // Extract the RHS vectors
17666 SDValue RHS = Op.getOperand(1);
17667 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17668 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17670 MVT EltVT = VT.getVectorElementType();
17671 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17673 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17674 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17675 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17678 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17679 if (Op.getValueType() == MVT::i1)
17680 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17681 Op.getOperand(0), Op.getOperand(1));
17682 assert(Op.getSimpleValueType().is256BitVector() &&
17683 Op.getSimpleValueType().isInteger() &&
17684 "Only handle AVX 256-bit vector integer operation");
17685 return Lower256IntArith(Op, DAG);
17688 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17689 if (Op.getValueType() == MVT::i1)
17690 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17691 Op.getOperand(0), Op.getOperand(1));
17692 assert(Op.getSimpleValueType().is256BitVector() &&
17693 Op.getSimpleValueType().isInteger() &&
17694 "Only handle AVX 256-bit vector integer operation");
17695 return Lower256IntArith(Op, DAG);
17698 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17699 assert(Op.getSimpleValueType().is256BitVector() &&
17700 Op.getSimpleValueType().isInteger() &&
17701 "Only handle AVX 256-bit vector integer operation");
17702 return Lower256IntArith(Op, DAG);
17705 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17706 SelectionDAG &DAG) {
17708 MVT VT = Op.getSimpleValueType();
17711 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17713 // Decompose 256-bit ops into smaller 128-bit ops.
17714 if (VT.is256BitVector() && !Subtarget->hasInt256())
17715 return Lower256IntArith(Op, DAG);
17717 SDValue A = Op.getOperand(0);
17718 SDValue B = Op.getOperand(1);
17720 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17721 // pairs, multiply and truncate.
17722 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17723 if (Subtarget->hasInt256()) {
17724 if (VT == MVT::v32i8) {
17725 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17726 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17727 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17728 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17729 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17730 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17731 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17732 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17733 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17734 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17737 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17738 return DAG.getNode(
17739 ISD::TRUNCATE, dl, VT,
17740 DAG.getNode(ISD::MUL, dl, ExVT,
17741 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17742 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17745 assert(VT == MVT::v16i8 &&
17746 "Pre-AVX2 support only supports v16i8 multiplication");
17747 MVT ExVT = MVT::v8i16;
17749 // Extract the lo parts and sign extend to i16
17751 if (Subtarget->hasSSE41()) {
17752 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17753 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17755 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17756 -1, 4, -1, 5, -1, 6, -1, 7};
17757 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17758 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17759 ALo = DAG.getBitcast(ExVT, ALo);
17760 BLo = DAG.getBitcast(ExVT, BLo);
17761 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17762 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17765 // Extract the hi parts and sign extend to i16
17767 if (Subtarget->hasSSE41()) {
17768 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17769 -1, -1, -1, -1, -1, -1, -1, -1};
17770 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17771 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17772 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17773 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17775 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17776 -1, 12, -1, 13, -1, 14, -1, 15};
17777 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17778 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17779 AHi = DAG.getBitcast(ExVT, AHi);
17780 BHi = DAG.getBitcast(ExVT, BHi);
17781 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17782 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17785 // Multiply, mask the lower 8bits of the lo/hi results and pack
17786 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17787 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17788 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17789 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17790 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17793 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17794 if (VT == MVT::v4i32) {
17795 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17796 "Should not custom lower when pmuldq is available!");
17798 // Extract the odd parts.
17799 static const int UnpackMask[] = { 1, -1, 3, -1 };
17800 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17801 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17803 // Multiply the even parts.
17804 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17805 // Now multiply odd parts.
17806 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17808 Evens = DAG.getBitcast(VT, Evens);
17809 Odds = DAG.getBitcast(VT, Odds);
17811 // Merge the two vectors back together with a shuffle. This expands into 2
17813 static const int ShufMask[] = { 0, 4, 2, 6 };
17814 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17817 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17818 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17820 // Ahi = psrlqi(a, 32);
17821 // Bhi = psrlqi(b, 32);
17823 // AloBlo = pmuludq(a, b);
17824 // AloBhi = pmuludq(a, Bhi);
17825 // AhiBlo = pmuludq(Ahi, b);
17827 // AloBhi = psllqi(AloBhi, 32);
17828 // AhiBlo = psllqi(AhiBlo, 32);
17829 // return AloBlo + AloBhi + AhiBlo;
17831 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17832 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17834 SDValue AhiBlo = Ahi;
17835 SDValue AloBhi = Bhi;
17836 // Bit cast to 32-bit vectors for MULUDQ
17837 MVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17838 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17839 A = DAG.getBitcast(MulVT, A);
17840 B = DAG.getBitcast(MulVT, B);
17841 Ahi = DAG.getBitcast(MulVT, Ahi);
17842 Bhi = DAG.getBitcast(MulVT, Bhi);
17844 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17845 // After shifting right const values the result may be all-zero.
17846 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17847 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17848 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17850 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17851 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17852 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17855 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17856 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17859 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17860 assert(Subtarget->isTargetWin64() && "Unexpected target");
17861 EVT VT = Op.getValueType();
17862 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17863 "Unexpected return type for lowering");
17867 switch (Op->getOpcode()) {
17868 default: llvm_unreachable("Unexpected request for libcall!");
17869 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17870 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17871 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17872 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17873 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17874 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17878 SDValue InChain = DAG.getEntryNode();
17880 TargetLowering::ArgListTy Args;
17881 TargetLowering::ArgListEntry Entry;
17882 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17883 EVT ArgVT = Op->getOperand(i).getValueType();
17884 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17885 "Unexpected argument type for lowering");
17886 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17887 Entry.Node = StackPtr;
17888 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17890 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17891 Entry.Ty = PointerType::get(ArgTy,0);
17892 Entry.isSExt = false;
17893 Entry.isZExt = false;
17894 Args.push_back(Entry);
17897 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17898 getPointerTy(DAG.getDataLayout()));
17900 TargetLowering::CallLoweringInfo CLI(DAG);
17901 CLI.setDebugLoc(dl).setChain(InChain)
17902 .setCallee(getLibcallCallingConv(LC),
17903 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17904 Callee, std::move(Args), 0)
17905 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17907 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17908 return DAG.getBitcast(VT, CallInfo.first);
17911 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17912 SelectionDAG &DAG) {
17913 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17914 MVT VT = Op0.getSimpleValueType();
17917 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17918 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17920 // PMULxD operations multiply each even value (starting at 0) of LHS with
17921 // the related value of RHS and produce a widen result.
17922 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17923 // => <2 x i64> <ae|cg>
17925 // In other word, to have all the results, we need to perform two PMULxD:
17926 // 1. one with the even values.
17927 // 2. one with the odd values.
17928 // To achieve #2, with need to place the odd values at an even position.
17930 // Place the odd value at an even position (basically, shift all values 1
17931 // step to the left):
17932 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17933 // <a|b|c|d> => <b|undef|d|undef>
17934 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17935 // <e|f|g|h> => <f|undef|h|undef>
17936 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17938 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17940 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17941 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17943 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17944 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17945 // => <2 x i64> <ae|cg>
17946 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17947 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17948 // => <2 x i64> <bf|dh>
17949 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17951 // Shuffle it back into the right order.
17952 SDValue Highs, Lows;
17953 if (VT == MVT::v8i32) {
17954 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17955 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17956 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17957 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17959 const int HighMask[] = {1, 5, 3, 7};
17960 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17961 const int LowMask[] = {0, 4, 2, 6};
17962 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17965 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17966 // unsigned multiply.
17967 if (IsSigned && !Subtarget->hasSSE41()) {
17968 SDValue ShAmt = DAG.getConstant(
17970 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
17971 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17972 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17973 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17974 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17976 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17977 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17980 // The first result of MUL_LOHI is actually the low value, followed by the
17982 SDValue Ops[] = {Lows, Highs};
17983 return DAG.getMergeValues(Ops, dl);
17986 // Return true if the required (according to Opcode) shift-imm form is natively
17987 // supported by the Subtarget
17988 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
17990 if (VT.getScalarSizeInBits() < 16)
17993 if (VT.is512BitVector() &&
17994 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
17997 bool LShift = VT.is128BitVector() ||
17998 (VT.is256BitVector() && Subtarget->hasInt256());
18000 bool AShift = LShift && (Subtarget->hasVLX() ||
18001 (VT != MVT::v2i64 && VT != MVT::v4i64));
18002 return (Opcode == ISD::SRA) ? AShift : LShift;
18005 // The shift amount is a variable, but it is the same for all vector lanes.
18006 // These instructions are defined together with shift-immediate.
18008 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18010 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18013 // Return true if the required (according to Opcode) variable-shift form is
18014 // natively supported by the Subtarget
18015 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18018 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18021 // vXi16 supported only on AVX-512, BWI
18022 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18025 if (VT.is512BitVector() || Subtarget->hasVLX())
18028 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18029 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18030 return (Opcode == ISD::SRA) ? AShift : LShift;
18033 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18034 const X86Subtarget *Subtarget) {
18035 MVT VT = Op.getSimpleValueType();
18037 SDValue R = Op.getOperand(0);
18038 SDValue Amt = Op.getOperand(1);
18040 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18041 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18043 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18044 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18045 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18046 SDValue Ex = DAG.getBitcast(ExVT, R);
18048 if (ShiftAmt >= 32) {
18049 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18051 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18052 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18053 ShiftAmt - 32, DAG);
18054 if (VT == MVT::v2i64)
18055 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18056 if (VT == MVT::v4i64)
18057 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18058 {9, 1, 11, 3, 13, 5, 15, 7});
18060 // SRA upper i32, SHL whole i64 and select lower i32.
18061 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18064 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18065 Lower = DAG.getBitcast(ExVT, Lower);
18066 if (VT == MVT::v2i64)
18067 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18068 if (VT == MVT::v4i64)
18069 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18070 {8, 1, 10, 3, 12, 5, 14, 7});
18072 return DAG.getBitcast(VT, Ex);
18075 // Optimize shl/srl/sra with constant shift amount.
18076 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18077 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18078 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18080 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18081 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18083 // i64 SRA needs to be performed as partial shifts.
18084 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18085 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18086 return ArithmeticShiftRight64(ShiftAmt);
18088 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
18089 unsigned NumElts = VT.getVectorNumElements();
18090 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18092 // Simple i8 add case
18093 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18094 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18096 // ashr(R, 7) === cmp_slt(R, 0)
18097 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18098 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18099 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18102 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18103 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18106 if (Op.getOpcode() == ISD::SHL) {
18107 // Make a large shift.
18108 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18110 SHL = DAG.getBitcast(VT, SHL);
18111 // Zero out the rightmost bits.
18112 SmallVector<SDValue, 32> V(
18113 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
18114 return DAG.getNode(ISD::AND, dl, VT, SHL,
18115 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18117 if (Op.getOpcode() == ISD::SRL) {
18118 // Make a large shift.
18119 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18121 SRL = DAG.getBitcast(VT, SRL);
18122 // Zero out the leftmost bits.
18123 SmallVector<SDValue, 32> V(
18124 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18125 return DAG.getNode(ISD::AND, dl, VT, SRL,
18126 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18128 if (Op.getOpcode() == ISD::SRA) {
18129 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18130 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18131 SmallVector<SDValue, 32> V(NumElts,
18132 DAG.getConstant(128 >> ShiftAmt, dl,
18134 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18135 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18136 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18139 llvm_unreachable("Unknown shift opcode.");
18144 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18145 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18146 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18148 // Peek through any splat that was introduced for i64 shift vectorization.
18149 int SplatIndex = -1;
18150 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18151 if (SVN->isSplat()) {
18152 SplatIndex = SVN->getSplatIndex();
18153 Amt = Amt.getOperand(0);
18154 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18155 "Splat shuffle referencing second operand");
18158 if (Amt.getOpcode() != ISD::BITCAST ||
18159 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18162 Amt = Amt.getOperand(0);
18163 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18164 VT.getVectorNumElements();
18165 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18166 uint64_t ShiftAmt = 0;
18167 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18168 for (unsigned i = 0; i != Ratio; ++i) {
18169 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18173 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18176 // Check remaining shift amounts (if not a splat).
18177 if (SplatIndex < 0) {
18178 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18179 uint64_t ShAmt = 0;
18180 for (unsigned j = 0; j != Ratio; ++j) {
18181 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18185 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18187 if (ShAmt != ShiftAmt)
18192 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18193 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18195 if (Op.getOpcode() == ISD::SRA)
18196 return ArithmeticShiftRight64(ShiftAmt);
18202 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18203 const X86Subtarget* Subtarget) {
18204 MVT VT = Op.getSimpleValueType();
18206 SDValue R = Op.getOperand(0);
18207 SDValue Amt = Op.getOperand(1);
18209 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18210 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18212 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18213 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18215 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18217 MVT EltVT = VT.getVectorElementType();
18219 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18220 // Check if this build_vector node is doing a splat.
18221 // If so, then set BaseShAmt equal to the splat value.
18222 BaseShAmt = BV->getSplatValue();
18223 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18224 BaseShAmt = SDValue();
18226 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18227 Amt = Amt.getOperand(0);
18229 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18230 if (SVN && SVN->isSplat()) {
18231 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18232 SDValue InVec = Amt.getOperand(0);
18233 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18234 assert((SplatIdx < InVec.getSimpleValueType().getVectorNumElements()) &&
18235 "Unexpected shuffle index found!");
18236 BaseShAmt = InVec.getOperand(SplatIdx);
18237 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18238 if (ConstantSDNode *C =
18239 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18240 if (C->getZExtValue() == SplatIdx)
18241 BaseShAmt = InVec.getOperand(1);
18246 // Avoid introducing an extract element from a shuffle.
18247 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18248 DAG.getIntPtrConstant(SplatIdx, dl));
18252 if (BaseShAmt.getNode()) {
18253 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18254 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18255 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18256 else if (EltVT.bitsLT(MVT::i32))
18257 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18259 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18263 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18264 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18265 Amt.getOpcode() == ISD::BITCAST &&
18266 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18267 Amt = Amt.getOperand(0);
18268 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18269 VT.getVectorNumElements();
18270 std::vector<SDValue> Vals(Ratio);
18271 for (unsigned i = 0; i != Ratio; ++i)
18272 Vals[i] = Amt.getOperand(i);
18273 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18274 for (unsigned j = 0; j != Ratio; ++j)
18275 if (Vals[j] != Amt.getOperand(i + j))
18279 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18280 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18285 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18286 SelectionDAG &DAG) {
18287 MVT VT = Op.getSimpleValueType();
18289 SDValue R = Op.getOperand(0);
18290 SDValue Amt = Op.getOperand(1);
18292 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18293 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18295 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18298 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18301 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18304 // XOP has 128-bit variable logical/arithmetic shifts.
18305 // +ve/-ve Amt = shift left/right.
18306 if (Subtarget->hasXOP() &&
18307 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18308 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18309 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18310 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18311 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18313 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18314 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18315 if (Op.getOpcode() == ISD::SRA)
18316 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18319 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18320 // shifts per-lane and then shuffle the partial results back together.
18321 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18322 // Splat the shift amounts so the scalar shifts above will catch it.
18323 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18324 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18325 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18326 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18327 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18330 // i64 vector arithmetic shift can be emulated with the transform:
18331 // M = lshr(SIGN_BIT, Amt)
18332 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18333 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18334 Op.getOpcode() == ISD::SRA) {
18335 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18336 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18337 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18338 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18339 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18343 // If possible, lower this packed shift into a vector multiply instead of
18344 // expanding it into a sequence of scalar shifts.
18345 // Do this only if the vector shift count is a constant build_vector.
18346 if (Op.getOpcode() == ISD::SHL &&
18347 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18348 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18349 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18350 SmallVector<SDValue, 8> Elts;
18351 MVT SVT = VT.getVectorElementType();
18352 unsigned SVTBits = SVT.getSizeInBits();
18353 APInt One(SVTBits, 1);
18354 unsigned NumElems = VT.getVectorNumElements();
18356 for (unsigned i=0; i !=NumElems; ++i) {
18357 SDValue Op = Amt->getOperand(i);
18358 if (Op->getOpcode() == ISD::UNDEF) {
18359 Elts.push_back(Op);
18363 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18364 APInt C(SVTBits, ND->getAPIntValue().getZExtValue());
18365 uint64_t ShAmt = C.getZExtValue();
18366 if (ShAmt >= SVTBits) {
18367 Elts.push_back(DAG.getUNDEF(SVT));
18370 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18372 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18373 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18376 // Lower SHL with variable shift amount.
18377 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18378 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18380 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18381 DAG.getConstant(0x3f800000U, dl, VT));
18382 Op = DAG.getBitcast(MVT::v4f32, Op);
18383 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18384 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18387 // If possible, lower this shift as a sequence of two shifts by
18388 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18390 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18392 // Could be rewritten as:
18393 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18395 // The advantage is that the two shifts from the example would be
18396 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18397 // the vector shift into four scalar shifts plus four pairs of vector
18399 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18400 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18401 unsigned TargetOpcode = X86ISD::MOVSS;
18402 bool CanBeSimplified;
18403 // The splat value for the first packed shift (the 'X' from the example).
18404 SDValue Amt1 = Amt->getOperand(0);
18405 // The splat value for the second packed shift (the 'Y' from the example).
18406 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18407 Amt->getOperand(2);
18409 // See if it is possible to replace this node with a sequence of
18410 // two shifts followed by a MOVSS/MOVSD
18411 if (VT == MVT::v4i32) {
18412 // Check if it is legal to use a MOVSS.
18413 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18414 Amt2 == Amt->getOperand(3);
18415 if (!CanBeSimplified) {
18416 // Otherwise, check if we can still simplify this node using a MOVSD.
18417 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18418 Amt->getOperand(2) == Amt->getOperand(3);
18419 TargetOpcode = X86ISD::MOVSD;
18420 Amt2 = Amt->getOperand(2);
18423 // Do similar checks for the case where the machine value type
18425 CanBeSimplified = Amt1 == Amt->getOperand(1);
18426 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18427 CanBeSimplified = Amt2 == Amt->getOperand(i);
18429 if (!CanBeSimplified) {
18430 TargetOpcode = X86ISD::MOVSD;
18431 CanBeSimplified = true;
18432 Amt2 = Amt->getOperand(4);
18433 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18434 CanBeSimplified = Amt1 == Amt->getOperand(i);
18435 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18436 CanBeSimplified = Amt2 == Amt->getOperand(j);
18440 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18441 isa<ConstantSDNode>(Amt2)) {
18442 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18443 MVT CastVT = MVT::v4i32;
18445 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18446 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18448 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18449 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18450 if (TargetOpcode == X86ISD::MOVSD)
18451 CastVT = MVT::v2i64;
18452 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18453 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18454 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18456 return DAG.getBitcast(VT, Result);
18460 // v4i32 Non Uniform Shifts.
18461 // If the shift amount is constant we can shift each lane using the SSE2
18462 // immediate shifts, else we need to zero-extend each lane to the lower i64
18463 // and shift using the SSE2 variable shifts.
18464 // The separate results can then be blended together.
18465 if (VT == MVT::v4i32) {
18466 unsigned Opc = Op.getOpcode();
18467 SDValue Amt0, Amt1, Amt2, Amt3;
18468 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18469 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18470 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18471 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18472 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18474 // ISD::SHL is handled above but we include it here for completeness.
18477 llvm_unreachable("Unknown target vector shift node");
18479 Opc = X86ISD::VSHL;
18482 Opc = X86ISD::VSRL;
18485 Opc = X86ISD::VSRA;
18488 // The SSE2 shifts use the lower i64 as the same shift amount for
18489 // all lanes and the upper i64 is ignored. These shuffle masks
18490 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18491 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18492 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18493 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18494 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18495 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18498 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18499 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18500 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18501 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18502 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18503 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18504 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18507 if (VT == MVT::v16i8 ||
18508 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18509 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18510 unsigned ShiftOpcode = Op->getOpcode();
18512 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18513 // On SSE41 targets we make use of the fact that VSELECT lowers
18514 // to PBLENDVB which selects bytes based just on the sign bit.
18515 if (Subtarget->hasSSE41()) {
18516 V0 = DAG.getBitcast(VT, V0);
18517 V1 = DAG.getBitcast(VT, V1);
18518 Sel = DAG.getBitcast(VT, Sel);
18519 return DAG.getBitcast(SelVT,
18520 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18522 // On pre-SSE41 targets we test for the sign bit by comparing to
18523 // zero - a negative value will set all bits of the lanes to true
18524 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18525 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18526 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18527 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18530 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18531 // We can safely do this using i16 shifts as we're only interested in
18532 // the 3 lower bits of each byte.
18533 Amt = DAG.getBitcast(ExtVT, Amt);
18534 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18535 Amt = DAG.getBitcast(VT, Amt);
18537 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18538 // r = VSELECT(r, shift(r, 4), a);
18540 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18541 R = SignBitSelect(VT, Amt, M, R);
18544 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18546 // r = VSELECT(r, shift(r, 2), a);
18547 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18548 R = SignBitSelect(VT, Amt, M, R);
18551 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18553 // return VSELECT(r, shift(r, 1), a);
18554 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18555 R = SignBitSelect(VT, Amt, M, R);
18559 if (Op->getOpcode() == ISD::SRA) {
18560 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18561 // so we can correctly sign extend. We don't care what happens to the
18563 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18564 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18565 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18566 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18567 ALo = DAG.getBitcast(ExtVT, ALo);
18568 AHi = DAG.getBitcast(ExtVT, AHi);
18569 RLo = DAG.getBitcast(ExtVT, RLo);
18570 RHi = DAG.getBitcast(ExtVT, RHi);
18572 // r = VSELECT(r, shift(r, 4), a);
18573 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18574 DAG.getConstant(4, dl, ExtVT));
18575 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18576 DAG.getConstant(4, dl, ExtVT));
18577 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18578 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18581 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18582 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18584 // r = VSELECT(r, shift(r, 2), a);
18585 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18586 DAG.getConstant(2, dl, ExtVT));
18587 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18588 DAG.getConstant(2, dl, ExtVT));
18589 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18590 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18593 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18594 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18596 // r = VSELECT(r, shift(r, 1), a);
18597 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18598 DAG.getConstant(1, dl, ExtVT));
18599 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18600 DAG.getConstant(1, dl, ExtVT));
18601 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18602 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18604 // Logical shift the result back to the lower byte, leaving a zero upper
18606 // meaning that we can safely pack with PACKUSWB.
18608 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18610 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18611 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18615 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18616 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18617 // solution better.
18618 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18619 MVT ExtVT = MVT::v8i32;
18621 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18622 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18623 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18624 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18625 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18628 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18629 MVT ExtVT = MVT::v8i32;
18630 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18631 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18632 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18633 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18634 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18635 ALo = DAG.getBitcast(ExtVT, ALo);
18636 AHi = DAG.getBitcast(ExtVT, AHi);
18637 RLo = DAG.getBitcast(ExtVT, RLo);
18638 RHi = DAG.getBitcast(ExtVT, RHi);
18639 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18640 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18641 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18642 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18643 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18646 if (VT == MVT::v8i16) {
18647 unsigned ShiftOpcode = Op->getOpcode();
18649 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18650 // On SSE41 targets we make use of the fact that VSELECT lowers
18651 // to PBLENDVB which selects bytes based just on the sign bit.
18652 if (Subtarget->hasSSE41()) {
18653 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18654 V0 = DAG.getBitcast(ExtVT, V0);
18655 V1 = DAG.getBitcast(ExtVT, V1);
18656 Sel = DAG.getBitcast(ExtVT, Sel);
18657 return DAG.getBitcast(
18658 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18660 // On pre-SSE41 targets we splat the sign bit - a negative value will
18661 // set all bits of the lanes to true and VSELECT uses that in
18662 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18664 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18665 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18668 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18669 if (Subtarget->hasSSE41()) {
18670 // On SSE41 targets we need to replicate the shift mask in both
18671 // bytes for PBLENDVB.
18674 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18675 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18677 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18680 // r = VSELECT(r, shift(r, 8), a);
18681 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18682 R = SignBitSelect(Amt, M, R);
18685 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18687 // r = VSELECT(r, shift(r, 4), a);
18688 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18689 R = SignBitSelect(Amt, M, R);
18692 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18694 // r = VSELECT(r, shift(r, 2), a);
18695 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18696 R = SignBitSelect(Amt, M, R);
18699 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18701 // return VSELECT(r, shift(r, 1), a);
18702 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18703 R = SignBitSelect(Amt, M, R);
18707 // Decompose 256-bit shifts into smaller 128-bit shifts.
18708 if (VT.is256BitVector()) {
18709 unsigned NumElems = VT.getVectorNumElements();
18710 MVT EltVT = VT.getVectorElementType();
18711 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18713 // Extract the two vectors
18714 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18715 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18717 // Recreate the shift amount vectors
18718 SDValue Amt1, Amt2;
18719 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18720 // Constant shift amount
18721 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18722 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18723 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18725 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18726 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18728 // Variable shift amount
18729 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18730 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18733 // Issue new vector shifts for the smaller types
18734 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18735 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18737 // Concatenate the result back
18738 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18744 static SDValue LowerRotate(SDValue Op, const X86Subtarget *Subtarget,
18745 SelectionDAG &DAG) {
18746 MVT VT = Op.getSimpleValueType();
18748 SDValue R = Op.getOperand(0);
18749 SDValue Amt = Op.getOperand(1);
18751 assert(VT.isVector() && "Custom lowering only for vector rotates!");
18752 assert(Subtarget->hasXOP() && "XOP support required for vector rotates!");
18753 assert((Op.getOpcode() == ISD::ROTL) && "Only ROTL supported");
18755 // XOP has 128-bit vector variable + immediate rotates.
18756 // +ve/-ve Amt = rotate left/right.
18758 // Split 256-bit integers.
18759 if (VT.is256BitVector())
18760 return Lower256IntArith(Op, DAG);
18762 assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
18764 // Attempt to rotate by immediate.
18765 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18766 if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
18767 uint64_t RotateAmt = RotateConst->getAPIntValue().getZExtValue();
18768 assert(RotateAmt < VT.getScalarSizeInBits() && "Rotation out of range");
18769 return DAG.getNode(X86ISD::VPROTI, DL, VT, R,
18770 DAG.getConstant(RotateAmt, DL, MVT::i8));
18774 // Use general rotate by variable (per-element).
18775 return DAG.getNode(X86ISD::VPROT, DL, VT, R, Amt);
18778 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18779 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18780 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18781 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18782 // has only one use.
18783 SDNode *N = Op.getNode();
18784 SDValue LHS = N->getOperand(0);
18785 SDValue RHS = N->getOperand(1);
18786 unsigned BaseOp = 0;
18789 switch (Op.getOpcode()) {
18790 default: llvm_unreachable("Unknown ovf instruction!");
18792 // A subtract of one will be selected as a INC. Note that INC doesn't
18793 // set CF, so we can't do this for UADDO.
18794 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18796 BaseOp = X86ISD::INC;
18797 Cond = X86::COND_O;
18800 BaseOp = X86ISD::ADD;
18801 Cond = X86::COND_O;
18804 BaseOp = X86ISD::ADD;
18805 Cond = X86::COND_B;
18808 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18809 // set CF, so we can't do this for USUBO.
18810 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18812 BaseOp = X86ISD::DEC;
18813 Cond = X86::COND_O;
18816 BaseOp = X86ISD::SUB;
18817 Cond = X86::COND_O;
18820 BaseOp = X86ISD::SUB;
18821 Cond = X86::COND_B;
18824 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18825 Cond = X86::COND_O;
18827 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18828 if (N->getValueType(0) == MVT::i8) {
18829 BaseOp = X86ISD::UMUL8;
18830 Cond = X86::COND_O;
18833 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18835 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18838 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18839 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18840 SDValue(Sum.getNode(), 2));
18842 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18846 // Also sets EFLAGS.
18847 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18848 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18851 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18852 DAG.getConstant(Cond, DL, MVT::i32),
18853 SDValue(Sum.getNode(), 1));
18855 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18858 /// Returns true if the operand type is exactly twice the native width, and
18859 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18860 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18861 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18862 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18863 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18866 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18867 else if (OpWidth == 128)
18868 return Subtarget->hasCmpxchg16b();
18873 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18874 return needsCmpXchgNb(SI->getValueOperand()->getType());
18877 // Note: this turns large loads into lock cmpxchg8b/16b.
18878 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18879 TargetLowering::AtomicExpansionKind
18880 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18881 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18882 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
18883 : AtomicExpansionKind::None;
18886 TargetLowering::AtomicExpansionKind
18887 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18888 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18889 Type *MemType = AI->getType();
18891 // If the operand is too big, we must see if cmpxchg8/16b is available
18892 // and default to library calls otherwise.
18893 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18894 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
18895 : AtomicExpansionKind::None;
18898 AtomicRMWInst::BinOp Op = AI->getOperation();
18901 llvm_unreachable("Unknown atomic operation");
18902 case AtomicRMWInst::Xchg:
18903 case AtomicRMWInst::Add:
18904 case AtomicRMWInst::Sub:
18905 // It's better to use xadd, xsub or xchg for these in all cases.
18906 return AtomicExpansionKind::None;
18907 case AtomicRMWInst::Or:
18908 case AtomicRMWInst::And:
18909 case AtomicRMWInst::Xor:
18910 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18911 // prefix to a normal instruction for these operations.
18912 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
18913 : AtomicExpansionKind::None;
18914 case AtomicRMWInst::Nand:
18915 case AtomicRMWInst::Max:
18916 case AtomicRMWInst::Min:
18917 case AtomicRMWInst::UMax:
18918 case AtomicRMWInst::UMin:
18919 // These always require a non-trivial set of data operations on x86. We must
18920 // use a cmpxchg loop.
18921 return AtomicExpansionKind::CmpXChg;
18925 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18926 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18927 // no-sse2). There isn't any reason to disable it if the target processor
18929 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18933 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18934 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18935 Type *MemType = AI->getType();
18936 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18937 // there is no benefit in turning such RMWs into loads, and it is actually
18938 // harmful as it introduces a mfence.
18939 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18942 auto Builder = IRBuilder<>(AI);
18943 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18944 auto SynchScope = AI->getSynchScope();
18945 // We must restrict the ordering to avoid generating loads with Release or
18946 // ReleaseAcquire orderings.
18947 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18948 auto Ptr = AI->getPointerOperand();
18950 // Before the load we need a fence. Here is an example lifted from
18951 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18954 // x.store(1, relaxed);
18955 // r1 = y.fetch_add(0, release);
18957 // y.fetch_add(42, acquire);
18958 // r2 = x.load(relaxed);
18959 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18960 // lowered to just a load without a fence. A mfence flushes the store buffer,
18961 // making the optimization clearly correct.
18962 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18963 // otherwise, we might be able to be more aggressive on relaxed idempotent
18964 // rmw. In practice, they do not look useful, so we don't try to be
18965 // especially clever.
18966 if (SynchScope == SingleThread)
18967 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18968 // the IR level, so we must wrap it in an intrinsic.
18971 if (!hasMFENCE(*Subtarget))
18972 // FIXME: it might make sense to use a locked operation here but on a
18973 // different cache-line to prevent cache-line bouncing. In practice it
18974 // is probably a small win, and x86 processors without mfence are rare
18975 // enough that we do not bother.
18979 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
18980 Builder.CreateCall(MFence, {});
18982 // Finally we can emit the atomic load.
18983 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18984 AI->getType()->getPrimitiveSizeInBits());
18985 Loaded->setAtomic(Order, SynchScope);
18986 AI->replaceAllUsesWith(Loaded);
18987 AI->eraseFromParent();
18991 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18992 SelectionDAG &DAG) {
18994 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18995 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18996 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18997 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18999 // The only fence that needs an instruction is a sequentially-consistent
19000 // cross-thread fence.
19001 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19002 if (hasMFENCE(*Subtarget))
19003 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19005 SDValue Chain = Op.getOperand(0);
19006 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19008 DAG.getRegister(X86::ESP, MVT::i32), // Base
19009 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19010 DAG.getRegister(0, MVT::i32), // Index
19011 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19012 DAG.getRegister(0, MVT::i32), // Segment.
19016 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19017 return SDValue(Res, 0);
19020 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19021 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19024 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19025 SelectionDAG &DAG) {
19026 MVT T = Op.getSimpleValueType();
19030 switch(T.SimpleTy) {
19031 default: llvm_unreachable("Invalid value type!");
19032 case MVT::i8: Reg = X86::AL; size = 1; break;
19033 case MVT::i16: Reg = X86::AX; size = 2; break;
19034 case MVT::i32: Reg = X86::EAX; size = 4; break;
19036 assert(Subtarget->is64Bit() && "Node not type legal!");
19037 Reg = X86::RAX; size = 8;
19040 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19041 Op.getOperand(2), SDValue());
19042 SDValue Ops[] = { cpIn.getValue(0),
19045 DAG.getTargetConstant(size, DL, MVT::i8),
19046 cpIn.getValue(1) };
19047 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19048 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19049 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19053 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19054 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19055 MVT::i32, cpOut.getValue(2));
19056 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19057 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19060 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19061 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19062 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19066 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19067 SelectionDAG &DAG) {
19068 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19069 MVT DstVT = Op.getSimpleValueType();
19071 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19072 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19073 if (DstVT != MVT::f64)
19074 // This conversion needs to be expanded.
19077 SDValue InVec = Op->getOperand(0);
19079 unsigned NumElts = SrcVT.getVectorNumElements();
19080 MVT SVT = SrcVT.getVectorElementType();
19082 // Widen the vector in input in the case of MVT::v2i32.
19083 // Example: from MVT::v2i32 to MVT::v4i32.
19084 SmallVector<SDValue, 16> Elts;
19085 for (unsigned i = 0, e = NumElts; i != e; ++i)
19086 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19087 DAG.getIntPtrConstant(i, dl)));
19089 // Explicitly mark the extra elements as Undef.
19090 Elts.append(NumElts, DAG.getUNDEF(SVT));
19092 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19093 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19094 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19095 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19096 DAG.getIntPtrConstant(0, dl));
19099 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19100 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19101 assert((DstVT == MVT::i64 ||
19102 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19103 "Unexpected custom BITCAST");
19104 // i64 <=> MMX conversions are Legal.
19105 if (SrcVT==MVT::i64 && DstVT.isVector())
19107 if (DstVT==MVT::i64 && SrcVT.isVector())
19109 // MMX <=> MMX conversions are Legal.
19110 if (SrcVT.isVector() && DstVT.isVector())
19112 // All other conversions need to be expanded.
19116 /// Compute the horizontal sum of bytes in V for the elements of VT.
19118 /// Requires V to be a byte vector and VT to be an integer vector type with
19119 /// wider elements than V's type. The width of the elements of VT determines
19120 /// how many bytes of V are summed horizontally to produce each element of the
19122 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19123 const X86Subtarget *Subtarget,
19124 SelectionDAG &DAG) {
19126 MVT ByteVecVT = V.getSimpleValueType();
19127 MVT EltVT = VT.getVectorElementType();
19128 int NumElts = VT.getVectorNumElements();
19129 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19130 "Expected value to have byte element type.");
19131 assert(EltVT != MVT::i8 &&
19132 "Horizontal byte sum only makes sense for wider elements!");
19133 unsigned VecSize = VT.getSizeInBits();
19134 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19136 // PSADBW instruction horizontally add all bytes and leave the result in i64
19137 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19138 if (EltVT == MVT::i64) {
19139 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19140 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
19141 return DAG.getBitcast(VT, V);
19144 if (EltVT == MVT::i32) {
19145 // We unpack the low half and high half into i32s interleaved with zeros so
19146 // that we can use PSADBW to horizontally sum them. The most useful part of
19147 // this is that it lines up the results of two PSADBW instructions to be
19148 // two v2i64 vectors which concatenated are the 4 population counts. We can
19149 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19150 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19151 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19152 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19154 // Do the horizontal sums into two v2i64s.
19155 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19156 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19157 DAG.getBitcast(ByteVecVT, Low), Zeros);
19158 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19159 DAG.getBitcast(ByteVecVT, High), Zeros);
19161 // Merge them together.
19162 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19163 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19164 DAG.getBitcast(ShortVecVT, Low),
19165 DAG.getBitcast(ShortVecVT, High));
19167 return DAG.getBitcast(VT, V);
19170 // The only element type left is i16.
19171 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19173 // To obtain pop count for each i16 element starting from the pop count for
19174 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19175 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19176 // directly supported.
19177 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19178 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19179 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19180 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19181 DAG.getBitcast(ByteVecVT, V));
19182 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19185 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19186 const X86Subtarget *Subtarget,
19187 SelectionDAG &DAG) {
19188 MVT VT = Op.getSimpleValueType();
19189 MVT EltVT = VT.getVectorElementType();
19190 unsigned VecSize = VT.getSizeInBits();
19192 // Implement a lookup table in register by using an algorithm based on:
19193 // http://wm.ite.pl/articles/sse-popcount.html
19195 // The general idea is that every lower byte nibble in the input vector is an
19196 // index into a in-register pre-computed pop count table. We then split up the
19197 // input vector in two new ones: (1) a vector with only the shifted-right
19198 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19199 // masked out higher ones) for each byte. PSHUB is used separately with both
19200 // to index the in-register table. Next, both are added and the result is a
19201 // i8 vector where each element contains the pop count for input byte.
19203 // To obtain the pop count for elements != i8, we follow up with the same
19204 // approach and use additional tricks as described below.
19206 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19207 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19208 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19209 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19211 int NumByteElts = VecSize / 8;
19212 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19213 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19214 SmallVector<SDValue, 16> LUTVec;
19215 for (int i = 0; i < NumByteElts; ++i)
19216 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19217 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19218 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19219 DAG.getConstant(0x0F, DL, MVT::i8));
19220 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19223 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19224 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19225 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19228 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19230 // The input vector is used as the shuffle mask that index elements into the
19231 // LUT. After counting low and high nibbles, add the vector to obtain the
19232 // final pop count per i8 element.
19233 SDValue HighPopCnt =
19234 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19235 SDValue LowPopCnt =
19236 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19237 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19239 if (EltVT == MVT::i8)
19242 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19245 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19246 const X86Subtarget *Subtarget,
19247 SelectionDAG &DAG) {
19248 MVT VT = Op.getSimpleValueType();
19249 assert(VT.is128BitVector() &&
19250 "Only 128-bit vector bitmath lowering supported.");
19252 int VecSize = VT.getSizeInBits();
19253 MVT EltVT = VT.getVectorElementType();
19254 int Len = EltVT.getSizeInBits();
19256 // This is the vectorized version of the "best" algorithm from
19257 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19258 // with a minor tweak to use a series of adds + shifts instead of vector
19259 // multiplications. Implemented for all integer vector types. We only use
19260 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19261 // much faster, even faster than using native popcnt instructions.
19263 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19264 MVT VT = V.getSimpleValueType();
19265 SmallVector<SDValue, 32> Shifters(
19266 VT.getVectorNumElements(),
19267 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19268 return DAG.getNode(OpCode, DL, VT, V,
19269 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19271 auto GetMask = [&](SDValue V, APInt Mask) {
19272 MVT VT = V.getSimpleValueType();
19273 SmallVector<SDValue, 32> Masks(
19274 VT.getVectorNumElements(),
19275 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19276 return DAG.getNode(ISD::AND, DL, VT, V,
19277 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19280 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19281 // x86, so set the SRL type to have elements at least i16 wide. This is
19282 // correct because all of our SRLs are followed immediately by a mask anyways
19283 // that handles any bits that sneak into the high bits of the byte elements.
19284 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19288 // v = v - ((v >> 1) & 0x55555555...)
19290 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19291 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19292 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19294 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19295 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19296 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19297 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19298 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19300 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19301 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19302 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19303 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19305 // At this point, V contains the byte-wise population count, and we are
19306 // merely doing a horizontal sum if necessary to get the wider element
19308 if (EltVT == MVT::i8)
19311 return LowerHorizontalByteSum(
19312 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19316 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19317 SelectionDAG &DAG) {
19318 MVT VT = Op.getSimpleValueType();
19319 // FIXME: Need to add AVX-512 support here!
19320 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19321 "Unknown CTPOP type to handle");
19322 SDLoc DL(Op.getNode());
19323 SDValue Op0 = Op.getOperand(0);
19325 if (!Subtarget->hasSSSE3()) {
19326 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19327 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19328 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19331 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19332 unsigned NumElems = VT.getVectorNumElements();
19334 // Extract each 128-bit vector, compute pop count and concat the result.
19335 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19336 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19338 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19339 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19340 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19343 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19346 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19347 SelectionDAG &DAG) {
19348 assert(Op.getSimpleValueType().isVector() &&
19349 "We only do custom lowering for vector population count.");
19350 return LowerVectorCTPOP(Op, Subtarget, DAG);
19353 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19354 SDNode *Node = Op.getNode();
19356 EVT T = Node->getValueType(0);
19357 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19358 DAG.getConstant(0, dl, T), Node->getOperand(2));
19359 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19360 cast<AtomicSDNode>(Node)->getMemoryVT(),
19361 Node->getOperand(0),
19362 Node->getOperand(1), negOp,
19363 cast<AtomicSDNode>(Node)->getMemOperand(),
19364 cast<AtomicSDNode>(Node)->getOrdering(),
19365 cast<AtomicSDNode>(Node)->getSynchScope());
19368 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19369 SDNode *Node = Op.getNode();
19371 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19373 // Convert seq_cst store -> xchg
19374 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19375 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19376 // (The only way to get a 16-byte store is cmpxchg16b)
19377 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19378 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19379 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19380 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19381 cast<AtomicSDNode>(Node)->getMemoryVT(),
19382 Node->getOperand(0),
19383 Node->getOperand(1), Node->getOperand(2),
19384 cast<AtomicSDNode>(Node)->getMemOperand(),
19385 cast<AtomicSDNode>(Node)->getOrdering(),
19386 cast<AtomicSDNode>(Node)->getSynchScope());
19387 return Swap.getValue(1);
19389 // Other atomic stores have a simple pattern.
19393 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19394 MVT VT = Op.getNode()->getSimpleValueType(0);
19396 // Let legalize expand this if it isn't a legal type yet.
19397 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19400 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19403 bool ExtraOp = false;
19404 switch (Op.getOpcode()) {
19405 default: llvm_unreachable("Invalid code");
19406 case ISD::ADDC: Opc = X86ISD::ADD; break;
19407 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19408 case ISD::SUBC: Opc = X86ISD::SUB; break;
19409 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19413 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19415 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19416 Op.getOperand(1), Op.getOperand(2));
19419 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19420 SelectionDAG &DAG) {
19421 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19423 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19424 // which returns the values as { float, float } (in XMM0) or
19425 // { double, double } (which is returned in XMM0, XMM1).
19427 SDValue Arg = Op.getOperand(0);
19428 EVT ArgVT = Arg.getValueType();
19429 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19431 TargetLowering::ArgListTy Args;
19432 TargetLowering::ArgListEntry Entry;
19436 Entry.isSExt = false;
19437 Entry.isZExt = false;
19438 Args.push_back(Entry);
19440 bool isF64 = ArgVT == MVT::f64;
19441 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19442 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19443 // the results are returned via SRet in memory.
19444 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19445 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19447 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19449 Type *RetTy = isF64
19450 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19451 : (Type*)VectorType::get(ArgTy, 4);
19453 TargetLowering::CallLoweringInfo CLI(DAG);
19454 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19455 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19457 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19460 // Returned in xmm0 and xmm1.
19461 return CallResult.first;
19463 // Returned in bits 0:31 and 32:64 xmm0.
19464 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19465 CallResult.first, DAG.getIntPtrConstant(0, dl));
19466 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19467 CallResult.first, DAG.getIntPtrConstant(1, dl));
19468 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19469 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19472 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19473 SelectionDAG &DAG) {
19474 assert(Subtarget->hasAVX512() &&
19475 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19477 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19478 MVT VT = N->getValue().getSimpleValueType();
19479 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19482 // X86 scatter kills mask register, so its type should be added to
19483 // the list of return values
19484 if (N->getNumValues() == 1) {
19485 SDValue Index = N->getIndex();
19486 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19487 !Index.getSimpleValueType().is512BitVector())
19488 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19490 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19491 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19492 N->getOperand(3), Index };
19494 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19495 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19496 return SDValue(NewScatter.getNode(), 0);
19501 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19502 SelectionDAG &DAG) {
19503 assert(Subtarget->hasAVX512() &&
19504 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19506 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19507 MVT VT = Op.getSimpleValueType();
19508 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19511 SDValue Index = N->getIndex();
19512 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19513 !Index.getSimpleValueType().is512BitVector()) {
19514 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19515 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19516 N->getOperand(3), Index };
19517 DAG.UpdateNodeOperands(N, Ops);
19522 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19523 SelectionDAG &DAG) const {
19524 // TODO: Eventually, the lowering of these nodes should be informed by or
19525 // deferred to the GC strategy for the function in which they appear. For
19526 // now, however, they must be lowered to something. Since they are logically
19527 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19528 // require special handling for these nodes), lower them as literal NOOPs for
19530 SmallVector<SDValue, 2> Ops;
19532 Ops.push_back(Op.getOperand(0));
19533 if (Op->getGluedNode())
19534 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19537 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19538 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19543 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19544 SelectionDAG &DAG) const {
19545 // TODO: Eventually, the lowering of these nodes should be informed by or
19546 // deferred to the GC strategy for the function in which they appear. For
19547 // now, however, they must be lowered to something. Since they are logically
19548 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19549 // require special handling for these nodes), lower them as literal NOOPs for
19551 SmallVector<SDValue, 2> Ops;
19553 Ops.push_back(Op.getOperand(0));
19554 if (Op->getGluedNode())
19555 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19558 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19559 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19564 /// LowerOperation - Provide custom lowering hooks for some operations.
19566 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19567 switch (Op.getOpcode()) {
19568 default: llvm_unreachable("Should not custom lower this!");
19569 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19570 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19571 return LowerCMP_SWAP(Op, Subtarget, DAG);
19572 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19573 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19574 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19575 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19576 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19577 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19578 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19579 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19580 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19581 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19582 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19583 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19584 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19585 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19586 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19587 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19588 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19589 case ISD::SHL_PARTS:
19590 case ISD::SRA_PARTS:
19591 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19592 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19593 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19594 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19595 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19596 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19597 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19598 case ISD::SIGN_EXTEND_VECTOR_INREG:
19599 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19600 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19601 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19602 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19603 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19605 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19606 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19607 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19608 case ISD::SETCC: return LowerSETCC(Op, DAG);
19609 case ISD::SELECT: return LowerSELECT(Op, DAG);
19610 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19611 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19612 case ISD::VASTART: return LowerVASTART(Op, DAG);
19613 case ISD::VAARG: return LowerVAARG(Op, DAG);
19614 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19615 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19616 case ISD::INTRINSIC_VOID:
19617 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19618 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19619 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19620 case ISD::FRAME_TO_ARGS_OFFSET:
19621 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19622 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19623 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19624 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19625 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19626 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19627 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19628 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19629 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
19630 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
19632 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19633 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19634 case ISD::UMUL_LOHI:
19635 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19636 case ISD::ROTL: return LowerRotate(Op, Subtarget, DAG);
19639 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19645 case ISD::UMULO: return LowerXALUO(Op, DAG);
19646 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19647 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19651 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19652 case ISD::ADD: return LowerADD(Op, DAG);
19653 case ISD::SUB: return LowerSUB(Op, DAG);
19657 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19658 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19659 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19660 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19661 case ISD::GC_TRANSITION_START:
19662 return LowerGC_TRANSITION_START(Op, DAG);
19663 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19667 /// ReplaceNodeResults - Replace a node with an illegal result type
19668 /// with a new node built out of custom code.
19669 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19670 SmallVectorImpl<SDValue>&Results,
19671 SelectionDAG &DAG) const {
19673 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19674 switch (N->getOpcode()) {
19676 llvm_unreachable("Do not know how to custom type legalize this operation!");
19677 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19678 case X86ISD::FMINC:
19680 case X86ISD::FMAXC:
19681 case X86ISD::FMAX: {
19682 EVT VT = N->getValueType(0);
19683 assert(VT == MVT::v2f32 && "Unexpected type (!= v2f32) on FMIN/FMAX.");
19684 SDValue UNDEF = DAG.getUNDEF(VT);
19685 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19686 N->getOperand(0), UNDEF);
19687 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19688 N->getOperand(1), UNDEF);
19689 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19692 case ISD::SIGN_EXTEND_INREG:
19697 // We don't want to expand or promote these.
19704 case ISD::UDIVREM: {
19705 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19706 Results.push_back(V);
19709 case ISD::FP_TO_SINT:
19710 case ISD::FP_TO_UINT: {
19711 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19713 std::pair<SDValue,SDValue> Vals =
19714 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19715 SDValue FIST = Vals.first, StackSlot = Vals.second;
19716 if (FIST.getNode()) {
19717 EVT VT = N->getValueType(0);
19718 // Return a load from the stack slot.
19719 if (StackSlot.getNode())
19720 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19721 MachinePointerInfo(),
19722 false, false, false, 0));
19724 Results.push_back(FIST);
19728 case ISD::UINT_TO_FP: {
19729 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19730 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19731 N->getValueType(0) != MVT::v2f32)
19733 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19735 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19737 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19738 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19739 DAG.getBitcast(MVT::v2i64, VBias));
19740 Or = DAG.getBitcast(MVT::v2f64, Or);
19741 // TODO: Are there any fast-math-flags to propagate here?
19742 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19743 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19746 case ISD::FP_ROUND: {
19747 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19749 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19750 Results.push_back(V);
19753 case ISD::FP_EXTEND: {
19754 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19755 // No other ValueType for FP_EXTEND should reach this point.
19756 assert(N->getValueType(0) == MVT::v2f32 &&
19757 "Do not know how to legalize this Node");
19760 case ISD::INTRINSIC_W_CHAIN: {
19761 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19763 default : llvm_unreachable("Do not know how to custom type "
19764 "legalize this intrinsic operation!");
19765 case Intrinsic::x86_rdtsc:
19766 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19768 case Intrinsic::x86_rdtscp:
19769 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19771 case Intrinsic::x86_rdpmc:
19772 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19775 case ISD::READCYCLECOUNTER: {
19776 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19779 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19780 EVT T = N->getValueType(0);
19781 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19782 bool Regs64bit = T == MVT::i128;
19783 MVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19784 SDValue cpInL, cpInH;
19785 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19786 DAG.getConstant(0, dl, HalfT));
19787 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19788 DAG.getConstant(1, dl, HalfT));
19789 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19790 Regs64bit ? X86::RAX : X86::EAX,
19792 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19793 Regs64bit ? X86::RDX : X86::EDX,
19794 cpInH, cpInL.getValue(1));
19795 SDValue swapInL, swapInH;
19796 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19797 DAG.getConstant(0, dl, HalfT));
19798 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19799 DAG.getConstant(1, dl, HalfT));
19800 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19801 Regs64bit ? X86::RBX : X86::EBX,
19802 swapInL, cpInH.getValue(1));
19803 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19804 Regs64bit ? X86::RCX : X86::ECX,
19805 swapInH, swapInL.getValue(1));
19806 SDValue Ops[] = { swapInH.getValue(0),
19808 swapInH.getValue(1) };
19809 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19810 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19811 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19812 X86ISD::LCMPXCHG8_DAG;
19813 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19814 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19815 Regs64bit ? X86::RAX : X86::EAX,
19816 HalfT, Result.getValue(1));
19817 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19818 Regs64bit ? X86::RDX : X86::EDX,
19819 HalfT, cpOutL.getValue(2));
19820 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19822 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19823 MVT::i32, cpOutH.getValue(2));
19825 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19826 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19827 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19829 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19830 Results.push_back(Success);
19831 Results.push_back(EFLAGS.getValue(1));
19834 case ISD::ATOMIC_SWAP:
19835 case ISD::ATOMIC_LOAD_ADD:
19836 case ISD::ATOMIC_LOAD_SUB:
19837 case ISD::ATOMIC_LOAD_AND:
19838 case ISD::ATOMIC_LOAD_OR:
19839 case ISD::ATOMIC_LOAD_XOR:
19840 case ISD::ATOMIC_LOAD_NAND:
19841 case ISD::ATOMIC_LOAD_MIN:
19842 case ISD::ATOMIC_LOAD_MAX:
19843 case ISD::ATOMIC_LOAD_UMIN:
19844 case ISD::ATOMIC_LOAD_UMAX:
19845 case ISD::ATOMIC_LOAD: {
19846 // Delegate to generic TypeLegalization. Situations we can really handle
19847 // should have already been dealt with by AtomicExpandPass.cpp.
19850 case ISD::BITCAST: {
19851 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19852 EVT DstVT = N->getValueType(0);
19853 EVT SrcVT = N->getOperand(0)->getValueType(0);
19855 if (SrcVT != MVT::f64 ||
19856 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19859 unsigned NumElts = DstVT.getVectorNumElements();
19860 EVT SVT = DstVT.getVectorElementType();
19861 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19862 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19863 MVT::v2f64, N->getOperand(0));
19864 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19866 if (ExperimentalVectorWideningLegalization) {
19867 // If we are legalizing vectors by widening, we already have the desired
19868 // legal vector type, just return it.
19869 Results.push_back(ToVecInt);
19873 SmallVector<SDValue, 8> Elts;
19874 for (unsigned i = 0, e = NumElts; i != e; ++i)
19875 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19876 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19878 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19883 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19884 switch ((X86ISD::NodeType)Opcode) {
19885 case X86ISD::FIRST_NUMBER: break;
19886 case X86ISD::BSF: return "X86ISD::BSF";
19887 case X86ISD::BSR: return "X86ISD::BSR";
19888 case X86ISD::SHLD: return "X86ISD::SHLD";
19889 case X86ISD::SHRD: return "X86ISD::SHRD";
19890 case X86ISD::FAND: return "X86ISD::FAND";
19891 case X86ISD::FANDN: return "X86ISD::FANDN";
19892 case X86ISD::FOR: return "X86ISD::FOR";
19893 case X86ISD::FXOR: return "X86ISD::FXOR";
19894 case X86ISD::FILD: return "X86ISD::FILD";
19895 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19896 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19897 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19898 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19899 case X86ISD::FLD: return "X86ISD::FLD";
19900 case X86ISD::FST: return "X86ISD::FST";
19901 case X86ISD::CALL: return "X86ISD::CALL";
19902 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19903 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19904 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19905 case X86ISD::BT: return "X86ISD::BT";
19906 case X86ISD::CMP: return "X86ISD::CMP";
19907 case X86ISD::COMI: return "X86ISD::COMI";
19908 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19909 case X86ISD::CMPM: return "X86ISD::CMPM";
19910 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19911 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
19912 case X86ISD::SETCC: return "X86ISD::SETCC";
19913 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19914 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19915 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
19916 case X86ISD::CMOV: return "X86ISD::CMOV";
19917 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19918 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19919 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19920 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19921 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19922 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19923 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19924 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
19925 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
19926 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
19927 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19928 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19929 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19930 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19931 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19932 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
19933 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19934 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19935 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19936 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19937 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19938 case X86ISD::ADDUS: return "X86ISD::ADDUS";
19939 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19940 case X86ISD::HADD: return "X86ISD::HADD";
19941 case X86ISD::HSUB: return "X86ISD::HSUB";
19942 case X86ISD::FHADD: return "X86ISD::FHADD";
19943 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19944 case X86ISD::ABS: return "X86ISD::ABS";
19945 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
19946 case X86ISD::FMAX: return "X86ISD::FMAX";
19947 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
19948 case X86ISD::FMIN: return "X86ISD::FMIN";
19949 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
19950 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19951 case X86ISD::FMINC: return "X86ISD::FMINC";
19952 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19953 case X86ISD::FRCP: return "X86ISD::FRCP";
19954 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
19955 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
19956 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19957 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19958 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19959 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19960 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19961 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19962 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19963 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19964 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19965 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19966 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19967 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19968 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19969 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19970 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19971 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19972 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19973 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
19974 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
19975 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19976 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19977 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19978 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
19979 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
19980 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19981 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19982 case X86ISD::VSHL: return "X86ISD::VSHL";
19983 case X86ISD::VSRL: return "X86ISD::VSRL";
19984 case X86ISD::VSRA: return "X86ISD::VSRA";
19985 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19986 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19987 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19988 case X86ISD::CMPP: return "X86ISD::CMPP";
19989 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19990 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19991 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19992 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19993 case X86ISD::ADD: return "X86ISD::ADD";
19994 case X86ISD::SUB: return "X86ISD::SUB";
19995 case X86ISD::ADC: return "X86ISD::ADC";
19996 case X86ISD::SBB: return "X86ISD::SBB";
19997 case X86ISD::SMUL: return "X86ISD::SMUL";
19998 case X86ISD::UMUL: return "X86ISD::UMUL";
19999 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20000 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20001 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20002 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20003 case X86ISD::INC: return "X86ISD::INC";
20004 case X86ISD::DEC: return "X86ISD::DEC";
20005 case X86ISD::OR: return "X86ISD::OR";
20006 case X86ISD::XOR: return "X86ISD::XOR";
20007 case X86ISD::AND: return "X86ISD::AND";
20008 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20009 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20010 case X86ISD::PTEST: return "X86ISD::PTEST";
20011 case X86ISD::TESTP: return "X86ISD::TESTP";
20012 case X86ISD::TESTM: return "X86ISD::TESTM";
20013 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20014 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20015 case X86ISD::KTEST: return "X86ISD::KTEST";
20016 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20017 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20018 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20019 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20020 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20021 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20022 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20023 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20024 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20025 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20026 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20027 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20028 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20029 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20030 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20031 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20032 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20033 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20034 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20035 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20036 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20037 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20038 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20039 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20040 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20041 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20042 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20043 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20044 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20045 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20046 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20047 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20048 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20049 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20050 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20051 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20052 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20053 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20054 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20055 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20056 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20057 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20058 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20059 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20060 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20061 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20062 case X86ISD::SAHF: return "X86ISD::SAHF";
20063 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20064 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20065 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20066 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20067 case X86ISD::VPROT: return "X86ISD::VPROT";
20068 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20069 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20070 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20071 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20072 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20073 case X86ISD::FMADD: return "X86ISD::FMADD";
20074 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20075 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20076 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20077 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20078 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20079 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20080 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20081 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20082 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20083 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20084 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20085 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20086 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20087 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20088 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20089 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20090 case X86ISD::XTEST: return "X86ISD::XTEST";
20091 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20092 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20093 case X86ISD::SELECT: return "X86ISD::SELECT";
20094 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20095 case X86ISD::RCP28: return "X86ISD::RCP28";
20096 case X86ISD::EXP2: return "X86ISD::EXP2";
20097 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20098 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20099 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20100 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20101 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20102 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20103 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20104 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20105 case X86ISD::ADDS: return "X86ISD::ADDS";
20106 case X86ISD::SUBS: return "X86ISD::SUBS";
20107 case X86ISD::AVG: return "X86ISD::AVG";
20108 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20109 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20110 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20111 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20112 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20113 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20118 // isLegalAddressingMode - Return true if the addressing mode represented
20119 // by AM is legal for this target, for a load/store of the specified type.
20120 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20121 const AddrMode &AM, Type *Ty,
20122 unsigned AS) const {
20123 // X86 supports extremely general addressing modes.
20124 CodeModel::Model M = getTargetMachine().getCodeModel();
20125 Reloc::Model R = getTargetMachine().getRelocationModel();
20127 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20128 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20133 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20135 // If a reference to this global requires an extra load, we can't fold it.
20136 if (isGlobalStubReference(GVFlags))
20139 // If BaseGV requires a register for the PIC base, we cannot also have a
20140 // BaseReg specified.
20141 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20144 // If lower 4G is not available, then we must use rip-relative addressing.
20145 if ((M != CodeModel::Small || R != Reloc::Static) &&
20146 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20150 switch (AM.Scale) {
20156 // These scales always work.
20161 // These scales are formed with basereg+scalereg. Only accept if there is
20166 default: // Other stuff never works.
20173 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20174 unsigned Bits = Ty->getScalarSizeInBits();
20176 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20177 // particularly cheaper than those without.
20181 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20182 // variable shifts just as cheap as scalar ones.
20183 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20186 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20187 // fully general vector.
20191 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20192 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20194 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20195 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20196 return NumBits1 > NumBits2;
20199 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20200 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20203 if (!isTypeLegal(EVT::getEVT(Ty1)))
20206 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20208 // Assuming the caller doesn't have a zeroext or signext return parameter,
20209 // truncation all the way down to i1 is valid.
20213 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20214 return isInt<32>(Imm);
20217 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20218 // Can also use sub to handle negated immediates.
20219 return isInt<32>(Imm);
20222 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20223 if (!VT1.isInteger() || !VT2.isInteger())
20225 unsigned NumBits1 = VT1.getSizeInBits();
20226 unsigned NumBits2 = VT2.getSizeInBits();
20227 return NumBits1 > NumBits2;
20230 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20231 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20232 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20235 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20236 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20237 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20240 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20241 EVT VT1 = Val.getValueType();
20242 if (isZExtFree(VT1, VT2))
20245 if (Val.getOpcode() != ISD::LOAD)
20248 if (!VT1.isSimple() || !VT1.isInteger() ||
20249 !VT2.isSimple() || !VT2.isInteger())
20252 switch (VT1.getSimpleVT().SimpleTy) {
20257 // X86 has 8, 16, and 32-bit zero-extending loads.
20264 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20267 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20268 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20271 VT = VT.getScalarType();
20273 if (!VT.isSimple())
20276 switch (VT.getSimpleVT().SimpleTy) {
20287 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20288 // i16 instructions are longer (0x66 prefix) and potentially slower.
20289 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20292 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20293 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20294 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20295 /// are assumed to be legal.
20297 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20299 if (!VT.isSimple())
20302 // Not for i1 vectors
20303 if (VT.getSimpleVT().getScalarType() == MVT::i1)
20306 // Very little shuffling can be done for 64-bit vectors right now.
20307 if (VT.getSimpleVT().getSizeInBits() == 64)
20310 // We only care that the types being shuffled are legal. The lowering can
20311 // handle any possible shuffle mask that results.
20312 return isTypeLegal(VT.getSimpleVT());
20316 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20318 // Just delegate to the generic legality, clear masks aren't special.
20319 return isShuffleMaskLegal(Mask, VT);
20322 //===----------------------------------------------------------------------===//
20323 // X86 Scheduler Hooks
20324 //===----------------------------------------------------------------------===//
20326 /// Utility function to emit xbegin specifying the start of an RTM region.
20327 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20328 const TargetInstrInfo *TII) {
20329 DebugLoc DL = MI->getDebugLoc();
20331 const BasicBlock *BB = MBB->getBasicBlock();
20332 MachineFunction::iterator I = ++MBB->getIterator();
20334 // For the v = xbegin(), we generate
20345 MachineBasicBlock *thisMBB = MBB;
20346 MachineFunction *MF = MBB->getParent();
20347 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20348 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20349 MF->insert(I, mainMBB);
20350 MF->insert(I, sinkMBB);
20352 // Transfer the remainder of BB and its successor edges to sinkMBB.
20353 sinkMBB->splice(sinkMBB->begin(), MBB,
20354 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20355 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20359 // # fallthrough to mainMBB
20360 // # abortion to sinkMBB
20361 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20362 thisMBB->addSuccessor(mainMBB);
20363 thisMBB->addSuccessor(sinkMBB);
20367 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20368 mainMBB->addSuccessor(sinkMBB);
20371 // EAX is live into the sinkMBB
20372 sinkMBB->addLiveIn(X86::EAX);
20373 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20374 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20377 MI->eraseFromParent();
20381 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20382 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20383 // in the .td file.
20384 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20385 const TargetInstrInfo *TII) {
20387 switch (MI->getOpcode()) {
20388 default: llvm_unreachable("illegal opcode!");
20389 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20390 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20391 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20392 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20393 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20394 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20395 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20396 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20399 DebugLoc dl = MI->getDebugLoc();
20400 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20402 unsigned NumArgs = MI->getNumOperands();
20403 for (unsigned i = 1; i < NumArgs; ++i) {
20404 MachineOperand &Op = MI->getOperand(i);
20405 if (!(Op.isReg() && Op.isImplicit()))
20406 MIB.addOperand(Op);
20408 if (MI->hasOneMemOperand())
20409 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20411 BuildMI(*BB, MI, dl,
20412 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20413 .addReg(X86::XMM0);
20415 MI->eraseFromParent();
20419 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20420 // defs in an instruction pattern
20421 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20422 const TargetInstrInfo *TII) {
20424 switch (MI->getOpcode()) {
20425 default: llvm_unreachable("illegal opcode!");
20426 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20427 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20428 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20429 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20430 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20431 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20432 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20433 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20436 DebugLoc dl = MI->getDebugLoc();
20437 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20439 unsigned NumArgs = MI->getNumOperands(); // remove the results
20440 for (unsigned i = 1; i < NumArgs; ++i) {
20441 MachineOperand &Op = MI->getOperand(i);
20442 if (!(Op.isReg() && Op.isImplicit()))
20443 MIB.addOperand(Op);
20445 if (MI->hasOneMemOperand())
20446 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20448 BuildMI(*BB, MI, dl,
20449 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20452 MI->eraseFromParent();
20456 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20457 const X86Subtarget *Subtarget) {
20458 DebugLoc dl = MI->getDebugLoc();
20459 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20460 // Address into RAX/EAX, other two args into ECX, EDX.
20461 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20462 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20463 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20464 for (int i = 0; i < X86::AddrNumOperands; ++i)
20465 MIB.addOperand(MI->getOperand(i));
20467 unsigned ValOps = X86::AddrNumOperands;
20468 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20469 .addReg(MI->getOperand(ValOps).getReg());
20470 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20471 .addReg(MI->getOperand(ValOps+1).getReg());
20473 // The instruction doesn't actually take any operands though.
20474 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20476 MI->eraseFromParent(); // The pseudo is gone now.
20480 MachineBasicBlock *
20481 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20482 MachineBasicBlock *MBB) const {
20483 // Emit va_arg instruction on X86-64.
20485 // Operands to this pseudo-instruction:
20486 // 0 ) Output : destination address (reg)
20487 // 1-5) Input : va_list address (addr, i64mem)
20488 // 6 ) ArgSize : Size (in bytes) of vararg type
20489 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20490 // 8 ) Align : Alignment of type
20491 // 9 ) EFLAGS (implicit-def)
20493 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20494 static_assert(X86::AddrNumOperands == 5,
20495 "VAARG_64 assumes 5 address operands");
20497 unsigned DestReg = MI->getOperand(0).getReg();
20498 MachineOperand &Base = MI->getOperand(1);
20499 MachineOperand &Scale = MI->getOperand(2);
20500 MachineOperand &Index = MI->getOperand(3);
20501 MachineOperand &Disp = MI->getOperand(4);
20502 MachineOperand &Segment = MI->getOperand(5);
20503 unsigned ArgSize = MI->getOperand(6).getImm();
20504 unsigned ArgMode = MI->getOperand(7).getImm();
20505 unsigned Align = MI->getOperand(8).getImm();
20507 // Memory Reference
20508 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20509 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20510 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20512 // Machine Information
20513 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20514 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20515 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20516 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20517 DebugLoc DL = MI->getDebugLoc();
20519 // struct va_list {
20522 // i64 overflow_area (address)
20523 // i64 reg_save_area (address)
20525 // sizeof(va_list) = 24
20526 // alignment(va_list) = 8
20528 unsigned TotalNumIntRegs = 6;
20529 unsigned TotalNumXMMRegs = 8;
20530 bool UseGPOffset = (ArgMode == 1);
20531 bool UseFPOffset = (ArgMode == 2);
20532 unsigned MaxOffset = TotalNumIntRegs * 8 +
20533 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20535 /* Align ArgSize to a multiple of 8 */
20536 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20537 bool NeedsAlign = (Align > 8);
20539 MachineBasicBlock *thisMBB = MBB;
20540 MachineBasicBlock *overflowMBB;
20541 MachineBasicBlock *offsetMBB;
20542 MachineBasicBlock *endMBB;
20544 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20545 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20546 unsigned OffsetReg = 0;
20548 if (!UseGPOffset && !UseFPOffset) {
20549 // If we only pull from the overflow region, we don't create a branch.
20550 // We don't need to alter control flow.
20551 OffsetDestReg = 0; // unused
20552 OverflowDestReg = DestReg;
20554 offsetMBB = nullptr;
20555 overflowMBB = thisMBB;
20558 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20559 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20560 // If not, pull from overflow_area. (branch to overflowMBB)
20565 // offsetMBB overflowMBB
20570 // Registers for the PHI in endMBB
20571 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20572 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20574 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20575 MachineFunction *MF = MBB->getParent();
20576 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20577 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20578 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20580 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20582 // Insert the new basic blocks
20583 MF->insert(MBBIter, offsetMBB);
20584 MF->insert(MBBIter, overflowMBB);
20585 MF->insert(MBBIter, endMBB);
20587 // Transfer the remainder of MBB and its successor edges to endMBB.
20588 endMBB->splice(endMBB->begin(), thisMBB,
20589 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20590 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20592 // Make offsetMBB and overflowMBB successors of thisMBB
20593 thisMBB->addSuccessor(offsetMBB);
20594 thisMBB->addSuccessor(overflowMBB);
20596 // endMBB is a successor of both offsetMBB and overflowMBB
20597 offsetMBB->addSuccessor(endMBB);
20598 overflowMBB->addSuccessor(endMBB);
20600 // Load the offset value into a register
20601 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20602 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20606 .addDisp(Disp, UseFPOffset ? 4 : 0)
20607 .addOperand(Segment)
20608 .setMemRefs(MMOBegin, MMOEnd);
20610 // Check if there is enough room left to pull this argument.
20611 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20613 .addImm(MaxOffset + 8 - ArgSizeA8);
20615 // Branch to "overflowMBB" if offset >= max
20616 // Fall through to "offsetMBB" otherwise
20617 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20618 .addMBB(overflowMBB);
20621 // In offsetMBB, emit code to use the reg_save_area.
20623 assert(OffsetReg != 0);
20625 // Read the reg_save_area address.
20626 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20627 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20632 .addOperand(Segment)
20633 .setMemRefs(MMOBegin, MMOEnd);
20635 // Zero-extend the offset
20636 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20637 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20640 .addImm(X86::sub_32bit);
20642 // Add the offset to the reg_save_area to get the final address.
20643 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20644 .addReg(OffsetReg64)
20645 .addReg(RegSaveReg);
20647 // Compute the offset for the next argument
20648 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20649 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20651 .addImm(UseFPOffset ? 16 : 8);
20653 // Store it back into the va_list.
20654 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20658 .addDisp(Disp, UseFPOffset ? 4 : 0)
20659 .addOperand(Segment)
20660 .addReg(NextOffsetReg)
20661 .setMemRefs(MMOBegin, MMOEnd);
20664 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20669 // Emit code to use overflow area
20672 // Load the overflow_area address into a register.
20673 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20674 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20679 .addOperand(Segment)
20680 .setMemRefs(MMOBegin, MMOEnd);
20682 // If we need to align it, do so. Otherwise, just copy the address
20683 // to OverflowDestReg.
20685 // Align the overflow address
20686 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20687 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20689 // aligned_addr = (addr + (align-1)) & ~(align-1)
20690 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20691 .addReg(OverflowAddrReg)
20694 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20696 .addImm(~(uint64_t)(Align-1));
20698 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20699 .addReg(OverflowAddrReg);
20702 // Compute the next overflow address after this argument.
20703 // (the overflow address should be kept 8-byte aligned)
20704 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20705 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20706 .addReg(OverflowDestReg)
20707 .addImm(ArgSizeA8);
20709 // Store the new overflow address.
20710 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20715 .addOperand(Segment)
20716 .addReg(NextAddrReg)
20717 .setMemRefs(MMOBegin, MMOEnd);
20719 // If we branched, emit the PHI to the front of endMBB.
20721 BuildMI(*endMBB, endMBB->begin(), DL,
20722 TII->get(X86::PHI), DestReg)
20723 .addReg(OffsetDestReg).addMBB(offsetMBB)
20724 .addReg(OverflowDestReg).addMBB(overflowMBB);
20727 // Erase the pseudo instruction
20728 MI->eraseFromParent();
20733 MachineBasicBlock *
20734 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20736 MachineBasicBlock *MBB) const {
20737 // Emit code to save XMM registers to the stack. The ABI says that the
20738 // number of registers to save is given in %al, so it's theoretically
20739 // possible to do an indirect jump trick to avoid saving all of them,
20740 // however this code takes a simpler approach and just executes all
20741 // of the stores if %al is non-zero. It's less code, and it's probably
20742 // easier on the hardware branch predictor, and stores aren't all that
20743 // expensive anyway.
20745 // Create the new basic blocks. One block contains all the XMM stores,
20746 // and one block is the final destination regardless of whether any
20747 // stores were performed.
20748 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20749 MachineFunction *F = MBB->getParent();
20750 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20751 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20752 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20753 F->insert(MBBIter, XMMSaveMBB);
20754 F->insert(MBBIter, EndMBB);
20756 // Transfer the remainder of MBB and its successor edges to EndMBB.
20757 EndMBB->splice(EndMBB->begin(), MBB,
20758 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20759 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20761 // The original block will now fall through to the XMM save block.
20762 MBB->addSuccessor(XMMSaveMBB);
20763 // The XMMSaveMBB will fall through to the end block.
20764 XMMSaveMBB->addSuccessor(EndMBB);
20766 // Now add the instructions.
20767 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20768 DebugLoc DL = MI->getDebugLoc();
20770 unsigned CountReg = MI->getOperand(0).getReg();
20771 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20772 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20774 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20775 // If %al is 0, branch around the XMM save block.
20776 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20777 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20778 MBB->addSuccessor(EndMBB);
20781 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20782 // that was just emitted, but clearly shouldn't be "saved".
20783 assert((MI->getNumOperands() <= 3 ||
20784 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20785 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20786 && "Expected last argument to be EFLAGS");
20787 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20788 // In the XMM save block, save all the XMM argument registers.
20789 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20790 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20791 MachineMemOperand *MMO = F->getMachineMemOperand(
20792 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20793 MachineMemOperand::MOStore,
20794 /*Size=*/16, /*Align=*/16);
20795 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20796 .addFrameIndex(RegSaveFrameIndex)
20797 .addImm(/*Scale=*/1)
20798 .addReg(/*IndexReg=*/0)
20799 .addImm(/*Disp=*/Offset)
20800 .addReg(/*Segment=*/0)
20801 .addReg(MI->getOperand(i).getReg())
20802 .addMemOperand(MMO);
20805 MI->eraseFromParent(); // The pseudo instruction is gone now.
20810 // The EFLAGS operand of SelectItr might be missing a kill marker
20811 // because there were multiple uses of EFLAGS, and ISel didn't know
20812 // which to mark. Figure out whether SelectItr should have had a
20813 // kill marker, and set it if it should. Returns the correct kill
20815 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20816 MachineBasicBlock* BB,
20817 const TargetRegisterInfo* TRI) {
20818 // Scan forward through BB for a use/def of EFLAGS.
20819 MachineBasicBlock::iterator miI(std::next(SelectItr));
20820 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20821 const MachineInstr& mi = *miI;
20822 if (mi.readsRegister(X86::EFLAGS))
20824 if (mi.definesRegister(X86::EFLAGS))
20825 break; // Should have kill-flag - update below.
20828 // If we hit the end of the block, check whether EFLAGS is live into a
20830 if (miI == BB->end()) {
20831 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20832 sEnd = BB->succ_end();
20833 sItr != sEnd; ++sItr) {
20834 MachineBasicBlock* succ = *sItr;
20835 if (succ->isLiveIn(X86::EFLAGS))
20840 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20841 // out. SelectMI should have a kill flag on EFLAGS.
20842 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20846 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20847 // together with other CMOV pseudo-opcodes into a single basic-block with
20848 // conditional jump around it.
20849 static bool isCMOVPseudo(MachineInstr *MI) {
20850 switch (MI->getOpcode()) {
20851 case X86::CMOV_FR32:
20852 case X86::CMOV_FR64:
20853 case X86::CMOV_GR8:
20854 case X86::CMOV_GR16:
20855 case X86::CMOV_GR32:
20856 case X86::CMOV_RFP32:
20857 case X86::CMOV_RFP64:
20858 case X86::CMOV_RFP80:
20859 case X86::CMOV_V2F64:
20860 case X86::CMOV_V2I64:
20861 case X86::CMOV_V4F32:
20862 case X86::CMOV_V4F64:
20863 case X86::CMOV_V4I64:
20864 case X86::CMOV_V16F32:
20865 case X86::CMOV_V8F32:
20866 case X86::CMOV_V8F64:
20867 case X86::CMOV_V8I64:
20868 case X86::CMOV_V8I1:
20869 case X86::CMOV_V16I1:
20870 case X86::CMOV_V32I1:
20871 case X86::CMOV_V64I1:
20879 MachineBasicBlock *
20880 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20881 MachineBasicBlock *BB) const {
20882 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20883 DebugLoc DL = MI->getDebugLoc();
20885 // To "insert" a SELECT_CC instruction, we actually have to insert the
20886 // diamond control-flow pattern. The incoming instruction knows the
20887 // destination vreg to set, the condition code register to branch on, the
20888 // true/false values to select between, and a branch opcode to use.
20889 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20890 MachineFunction::iterator It = ++BB->getIterator();
20895 // cmpTY ccX, r1, r2
20897 // fallthrough --> copy0MBB
20898 MachineBasicBlock *thisMBB = BB;
20899 MachineFunction *F = BB->getParent();
20901 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20902 // as described above, by inserting a BB, and then making a PHI at the join
20903 // point to select the true and false operands of the CMOV in the PHI.
20905 // The code also handles two different cases of multiple CMOV opcodes
20909 // In this case, there are multiple CMOVs in a row, all which are based on
20910 // the same condition setting (or the exact opposite condition setting).
20911 // In this case we can lower all the CMOVs using a single inserted BB, and
20912 // then make a number of PHIs at the join point to model the CMOVs. The only
20913 // trickiness here, is that in a case like:
20915 // t2 = CMOV cond1 t1, f1
20916 // t3 = CMOV cond1 t2, f2
20918 // when rewriting this into PHIs, we have to perform some renaming on the
20919 // temps since you cannot have a PHI operand refer to a PHI result earlier
20920 // in the same block. The "simple" but wrong lowering would be:
20922 // t2 = PHI t1(BB1), f1(BB2)
20923 // t3 = PHI t2(BB1), f2(BB2)
20925 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
20926 // renaming is to note that on the path through BB1, t2 is really just a
20927 // copy of t1, and do that renaming, properly generating:
20929 // t2 = PHI t1(BB1), f1(BB2)
20930 // t3 = PHI t1(BB1), f2(BB2)
20932 // Case 2, we lower cascaded CMOVs such as
20934 // (CMOV (CMOV F, T, cc1), T, cc2)
20936 // to two successives branches. For that, we look for another CMOV as the
20937 // following instruction.
20939 // Without this, we would add a PHI between the two jumps, which ends up
20940 // creating a few copies all around. For instance, for
20942 // (sitofp (zext (fcmp une)))
20944 // we would generate:
20946 // ucomiss %xmm1, %xmm0
20947 // movss <1.0f>, %xmm0
20948 // movaps %xmm0, %xmm1
20950 // xorps %xmm1, %xmm1
20953 // movaps %xmm1, %xmm0
20957 // because this custom-inserter would have generated:
20969 // A: X = ...; Y = ...
20971 // C: Z = PHI [X, A], [Y, B]
20973 // E: PHI [X, C], [Z, D]
20975 // If we lower both CMOVs in a single step, we can instead generate:
20987 // A: X = ...; Y = ...
20989 // E: PHI [X, A], [X, C], [Y, D]
20991 // Which, in our sitofp/fcmp example, gives us something like:
20993 // ucomiss %xmm1, %xmm0
20994 // movss <1.0f>, %xmm0
20997 // xorps %xmm0, %xmm0
21001 MachineInstr *CascadedCMOV = nullptr;
21002 MachineInstr *LastCMOV = MI;
21003 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21004 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21005 MachineBasicBlock::iterator NextMIIt =
21006 std::next(MachineBasicBlock::iterator(MI));
21008 // Check for case 1, where there are multiple CMOVs with the same condition
21009 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21010 // number of jumps the most.
21012 if (isCMOVPseudo(MI)) {
21013 // See if we have a string of CMOVS with the same condition.
21014 while (NextMIIt != BB->end() &&
21015 isCMOVPseudo(NextMIIt) &&
21016 (NextMIIt->getOperand(3).getImm() == CC ||
21017 NextMIIt->getOperand(3).getImm() == OppCC)) {
21018 LastCMOV = &*NextMIIt;
21023 // This checks for case 2, but only do this if we didn't already find
21024 // case 1, as indicated by LastCMOV == MI.
21025 if (LastCMOV == MI &&
21026 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21027 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21028 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21029 CascadedCMOV = &*NextMIIt;
21032 MachineBasicBlock *jcc1MBB = nullptr;
21034 // If we have a cascaded CMOV, we lower it to two successive branches to
21035 // the same block. EFLAGS is used by both, so mark it as live in the second.
21036 if (CascadedCMOV) {
21037 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21038 F->insert(It, jcc1MBB);
21039 jcc1MBB->addLiveIn(X86::EFLAGS);
21042 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21043 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21044 F->insert(It, copy0MBB);
21045 F->insert(It, sinkMBB);
21047 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21048 // live into the sink and copy blocks.
21049 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21051 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21052 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21053 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21054 copy0MBB->addLiveIn(X86::EFLAGS);
21055 sinkMBB->addLiveIn(X86::EFLAGS);
21058 // Transfer the remainder of BB and its successor edges to sinkMBB.
21059 sinkMBB->splice(sinkMBB->begin(), BB,
21060 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21061 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21063 // Add the true and fallthrough blocks as its successors.
21064 if (CascadedCMOV) {
21065 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21066 BB->addSuccessor(jcc1MBB);
21068 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21069 // jump to the sinkMBB.
21070 jcc1MBB->addSuccessor(copy0MBB);
21071 jcc1MBB->addSuccessor(sinkMBB);
21073 BB->addSuccessor(copy0MBB);
21076 // The true block target of the first (or only) branch is always sinkMBB.
21077 BB->addSuccessor(sinkMBB);
21079 // Create the conditional branch instruction.
21080 unsigned Opc = X86::GetCondBranchFromCond(CC);
21081 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21083 if (CascadedCMOV) {
21084 unsigned Opc2 = X86::GetCondBranchFromCond(
21085 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21086 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21090 // %FalseValue = ...
21091 // # fallthrough to sinkMBB
21092 copy0MBB->addSuccessor(sinkMBB);
21095 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21097 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21098 MachineBasicBlock::iterator MIItEnd =
21099 std::next(MachineBasicBlock::iterator(LastCMOV));
21100 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21101 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21102 MachineInstrBuilder MIB;
21104 // As we are creating the PHIs, we have to be careful if there is more than
21105 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21106 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21107 // That also means that PHI construction must work forward from earlier to
21108 // later, and that the code must maintain a mapping from earlier PHI's
21109 // destination registers, and the registers that went into the PHI.
21111 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21112 unsigned DestReg = MIIt->getOperand(0).getReg();
21113 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21114 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21116 // If this CMOV we are generating is the opposite condition from
21117 // the jump we generated, then we have to swap the operands for the
21118 // PHI that is going to be generated.
21119 if (MIIt->getOperand(3).getImm() == OppCC)
21120 std::swap(Op1Reg, Op2Reg);
21122 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21123 Op1Reg = RegRewriteTable[Op1Reg].first;
21125 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21126 Op2Reg = RegRewriteTable[Op2Reg].second;
21128 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21129 TII->get(X86::PHI), DestReg)
21130 .addReg(Op1Reg).addMBB(copy0MBB)
21131 .addReg(Op2Reg).addMBB(thisMBB);
21133 // Add this PHI to the rewrite table.
21134 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21137 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21138 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21139 if (CascadedCMOV) {
21140 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21141 // Copy the PHI result to the register defined by the second CMOV.
21142 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21143 DL, TII->get(TargetOpcode::COPY),
21144 CascadedCMOV->getOperand(0).getReg())
21145 .addReg(MI->getOperand(0).getReg());
21146 CascadedCMOV->eraseFromParent();
21149 // Now remove the CMOV(s).
21150 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21151 (MIIt++)->eraseFromParent();
21156 MachineBasicBlock *
21157 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21158 MachineBasicBlock *BB) const {
21159 // Combine the following atomic floating-point modification pattern:
21160 // a.store(reg OP a.load(acquire), release)
21161 // Transform them into:
21162 // OPss (%gpr), %xmm
21163 // movss %xmm, (%gpr)
21164 // Or sd equivalent for 64-bit operations.
21166 switch (MI->getOpcode()) {
21167 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21168 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21169 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21171 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21172 DebugLoc DL = MI->getDebugLoc();
21173 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21174 MachineOperand MSrc = MI->getOperand(0);
21175 unsigned VSrc = MI->getOperand(5).getReg();
21176 const MachineOperand &Disp = MI->getOperand(3);
21177 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21178 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21179 if (hasDisp && MSrc.isReg())
21180 MSrc.setIsKill(false);
21181 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21182 .addOperand(/*Base=*/MSrc)
21183 .addImm(/*Scale=*/1)
21184 .addReg(/*Index=*/0)
21185 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21187 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21188 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21190 .addOperand(/*Base=*/MSrc)
21191 .addImm(/*Scale=*/1)
21192 .addReg(/*Index=*/0)
21193 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21194 .addReg(/*Segment=*/0);
21195 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21196 MI->eraseFromParent(); // The pseudo instruction is gone now.
21200 MachineBasicBlock *
21201 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21202 MachineBasicBlock *BB) const {
21203 MachineFunction *MF = BB->getParent();
21204 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21205 DebugLoc DL = MI->getDebugLoc();
21206 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21208 assert(MF->shouldSplitStack());
21210 const bool Is64Bit = Subtarget->is64Bit();
21211 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21213 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21214 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21217 // ... [Till the alloca]
21218 // If stacklet is not large enough, jump to mallocMBB
21221 // Allocate by subtracting from RSP
21222 // Jump to continueMBB
21225 // Allocate by call to runtime
21229 // [rest of original BB]
21232 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21233 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21234 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21236 MachineRegisterInfo &MRI = MF->getRegInfo();
21237 const TargetRegisterClass *AddrRegClass =
21238 getRegClassFor(getPointerTy(MF->getDataLayout()));
21240 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21241 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21242 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21243 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21244 sizeVReg = MI->getOperand(1).getReg(),
21245 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21247 MachineFunction::iterator MBBIter = ++BB->getIterator();
21249 MF->insert(MBBIter, bumpMBB);
21250 MF->insert(MBBIter, mallocMBB);
21251 MF->insert(MBBIter, continueMBB);
21253 continueMBB->splice(continueMBB->begin(), BB,
21254 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21255 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21257 // Add code to the main basic block to check if the stack limit has been hit,
21258 // and if so, jump to mallocMBB otherwise to bumpMBB.
21259 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21260 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21261 .addReg(tmpSPVReg).addReg(sizeVReg);
21262 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21263 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21264 .addReg(SPLimitVReg);
21265 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21267 // bumpMBB simply decreases the stack pointer, since we know the current
21268 // stacklet has enough space.
21269 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21270 .addReg(SPLimitVReg);
21271 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21272 .addReg(SPLimitVReg);
21273 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21275 // Calls into a routine in libgcc to allocate more space from the heap.
21276 const uint32_t *RegMask =
21277 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21279 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21281 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21282 .addExternalSymbol("__morestack_allocate_stack_space")
21283 .addRegMask(RegMask)
21284 .addReg(X86::RDI, RegState::Implicit)
21285 .addReg(X86::RAX, RegState::ImplicitDefine);
21286 } else if (Is64Bit) {
21287 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21289 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21290 .addExternalSymbol("__morestack_allocate_stack_space")
21291 .addRegMask(RegMask)
21292 .addReg(X86::EDI, RegState::Implicit)
21293 .addReg(X86::EAX, RegState::ImplicitDefine);
21295 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21297 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21298 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21299 .addExternalSymbol("__morestack_allocate_stack_space")
21300 .addRegMask(RegMask)
21301 .addReg(X86::EAX, RegState::ImplicitDefine);
21305 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21308 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21309 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21310 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21312 // Set up the CFG correctly.
21313 BB->addSuccessor(bumpMBB);
21314 BB->addSuccessor(mallocMBB);
21315 mallocMBB->addSuccessor(continueMBB);
21316 bumpMBB->addSuccessor(continueMBB);
21318 // Take care of the PHI nodes.
21319 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21320 MI->getOperand(0).getReg())
21321 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21322 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21324 // Delete the original pseudo instruction.
21325 MI->eraseFromParent();
21328 return continueMBB;
21331 MachineBasicBlock *
21332 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21333 MachineBasicBlock *BB) const {
21334 DebugLoc DL = MI->getDebugLoc();
21336 assert(!Subtarget->isTargetMachO());
21338 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
21341 MI->eraseFromParent(); // The pseudo instruction is gone now.
21345 MachineBasicBlock *
21346 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21347 MachineBasicBlock *BB) const {
21348 // This is pretty easy. We're taking the value that we received from
21349 // our load from the relocation, sticking it in either RDI (x86-64)
21350 // or EAX and doing an indirect call. The return value will then
21351 // be in the normal return register.
21352 MachineFunction *F = BB->getParent();
21353 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21354 DebugLoc DL = MI->getDebugLoc();
21356 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21357 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21359 // Get a register mask for the lowered call.
21360 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21361 // proper register mask.
21362 const uint32_t *RegMask =
21363 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21364 if (Subtarget->is64Bit()) {
21365 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21366 TII->get(X86::MOV64rm), X86::RDI)
21368 .addImm(0).addReg(0)
21369 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21370 MI->getOperand(3).getTargetFlags())
21372 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21373 addDirectMem(MIB, X86::RDI);
21374 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21375 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21376 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21377 TII->get(X86::MOV32rm), X86::EAX)
21379 .addImm(0).addReg(0)
21380 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21381 MI->getOperand(3).getTargetFlags())
21383 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21384 addDirectMem(MIB, X86::EAX);
21385 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21387 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21388 TII->get(X86::MOV32rm), X86::EAX)
21389 .addReg(TII->getGlobalBaseReg(F))
21390 .addImm(0).addReg(0)
21391 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21392 MI->getOperand(3).getTargetFlags())
21394 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21395 addDirectMem(MIB, X86::EAX);
21396 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21399 MI->eraseFromParent(); // The pseudo instruction is gone now.
21403 MachineBasicBlock *
21404 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21405 MachineBasicBlock *MBB) const {
21406 DebugLoc DL = MI->getDebugLoc();
21407 MachineFunction *MF = MBB->getParent();
21408 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21409 MachineRegisterInfo &MRI = MF->getRegInfo();
21411 const BasicBlock *BB = MBB->getBasicBlock();
21412 MachineFunction::iterator I = ++MBB->getIterator();
21414 // Memory Reference
21415 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21416 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21419 unsigned MemOpndSlot = 0;
21421 unsigned CurOp = 0;
21423 DstReg = MI->getOperand(CurOp++).getReg();
21424 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21425 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21426 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21427 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21429 MemOpndSlot = CurOp;
21431 MVT PVT = getPointerTy(MF->getDataLayout());
21432 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21433 "Invalid Pointer Size!");
21435 // For v = setjmp(buf), we generate
21438 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB
21439 // SjLjSetup restoreMBB
21445 // v = phi(main, restore)
21448 // if base pointer being used, load it from frame
21451 MachineBasicBlock *thisMBB = MBB;
21452 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21453 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21454 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21455 MF->insert(I, mainMBB);
21456 MF->insert(I, sinkMBB);
21457 MF->push_back(restoreMBB);
21458 restoreMBB->setHasAddressTaken();
21460 MachineInstrBuilder MIB;
21462 // Transfer the remainder of BB and its successor edges to sinkMBB.
21463 sinkMBB->splice(sinkMBB->begin(), MBB,
21464 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21465 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21468 unsigned PtrStoreOpc = 0;
21469 unsigned LabelReg = 0;
21470 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21471 Reloc::Model RM = MF->getTarget().getRelocationModel();
21472 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21473 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21475 // Prepare IP either in reg or imm.
21476 if (!UseImmLabel) {
21477 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21478 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21479 LabelReg = MRI.createVirtualRegister(PtrRC);
21480 if (Subtarget->is64Bit()) {
21481 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21485 .addMBB(restoreMBB)
21488 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21489 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21490 .addReg(XII->getGlobalBaseReg(MF))
21493 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21497 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21499 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21500 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21501 if (i == X86::AddrDisp)
21502 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21504 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21507 MIB.addReg(LabelReg);
21509 MIB.addMBB(restoreMBB);
21510 MIB.setMemRefs(MMOBegin, MMOEnd);
21512 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21513 .addMBB(restoreMBB);
21515 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21516 MIB.addRegMask(RegInfo->getNoPreservedMask());
21517 thisMBB->addSuccessor(mainMBB);
21518 thisMBB->addSuccessor(restoreMBB);
21522 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21523 mainMBB->addSuccessor(sinkMBB);
21526 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21527 TII->get(X86::PHI), DstReg)
21528 .addReg(mainDstReg).addMBB(mainMBB)
21529 .addReg(restoreDstReg).addMBB(restoreMBB);
21532 if (RegInfo->hasBasePointer(*MF)) {
21533 const bool Uses64BitFramePtr =
21534 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21535 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21536 X86FI->setRestoreBasePointer(MF);
21537 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21538 unsigned BasePtr = RegInfo->getBaseRegister();
21539 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21540 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21541 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21542 .setMIFlag(MachineInstr::FrameSetup);
21544 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21545 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21546 restoreMBB->addSuccessor(sinkMBB);
21548 MI->eraseFromParent();
21552 MachineBasicBlock *
21553 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21554 MachineBasicBlock *MBB) const {
21555 DebugLoc DL = MI->getDebugLoc();
21556 MachineFunction *MF = MBB->getParent();
21557 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21558 MachineRegisterInfo &MRI = MF->getRegInfo();
21560 // Memory Reference
21561 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21562 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21564 MVT PVT = getPointerTy(MF->getDataLayout());
21565 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21566 "Invalid Pointer Size!");
21568 const TargetRegisterClass *RC =
21569 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21570 unsigned Tmp = MRI.createVirtualRegister(RC);
21571 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21572 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21573 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21574 unsigned SP = RegInfo->getStackRegister();
21576 MachineInstrBuilder MIB;
21578 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21579 const int64_t SPOffset = 2 * PVT.getStoreSize();
21581 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21582 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21585 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21586 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21587 MIB.addOperand(MI->getOperand(i));
21588 MIB.setMemRefs(MMOBegin, MMOEnd);
21590 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21591 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21592 if (i == X86::AddrDisp)
21593 MIB.addDisp(MI->getOperand(i), LabelOffset);
21595 MIB.addOperand(MI->getOperand(i));
21597 MIB.setMemRefs(MMOBegin, MMOEnd);
21599 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21600 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21601 if (i == X86::AddrDisp)
21602 MIB.addDisp(MI->getOperand(i), SPOffset);
21604 MIB.addOperand(MI->getOperand(i));
21606 MIB.setMemRefs(MMOBegin, MMOEnd);
21608 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21610 MI->eraseFromParent();
21614 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21615 // accumulator loops. Writing back to the accumulator allows the coalescer
21616 // to remove extra copies in the loop.
21617 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21618 MachineBasicBlock *
21619 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21620 MachineBasicBlock *MBB) const {
21621 MachineOperand &AddendOp = MI->getOperand(3);
21623 // Bail out early if the addend isn't a register - we can't switch these.
21624 if (!AddendOp.isReg())
21627 MachineFunction &MF = *MBB->getParent();
21628 MachineRegisterInfo &MRI = MF.getRegInfo();
21630 // Check whether the addend is defined by a PHI:
21631 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21632 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21633 if (!AddendDef.isPHI())
21636 // Look for the following pattern:
21638 // %addend = phi [%entry, 0], [%loop, %result]
21640 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21644 // %addend = phi [%entry, 0], [%loop, %result]
21646 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21648 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21649 assert(AddendDef.getOperand(i).isReg());
21650 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21651 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21652 if (&PHISrcInst == MI) {
21653 // Found a matching instruction.
21654 unsigned NewFMAOpc = 0;
21655 switch (MI->getOpcode()) {
21656 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21657 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21658 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21659 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21660 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21661 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21662 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21663 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21664 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21665 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21666 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21667 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21668 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21669 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21670 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21671 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21672 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21673 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21674 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21675 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21677 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21678 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21679 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21680 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21681 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21682 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21683 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21684 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21685 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21686 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21687 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21688 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21689 default: llvm_unreachable("Unrecognized FMA variant.");
21692 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21693 MachineInstrBuilder MIB =
21694 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21695 .addOperand(MI->getOperand(0))
21696 .addOperand(MI->getOperand(3))
21697 .addOperand(MI->getOperand(2))
21698 .addOperand(MI->getOperand(1));
21699 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21700 MI->eraseFromParent();
21707 MachineBasicBlock *
21708 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21709 MachineBasicBlock *BB) const {
21710 switch (MI->getOpcode()) {
21711 default: llvm_unreachable("Unexpected instr type to insert");
21712 case X86::TAILJMPd64:
21713 case X86::TAILJMPr64:
21714 case X86::TAILJMPm64:
21715 case X86::TAILJMPd64_REX:
21716 case X86::TAILJMPr64_REX:
21717 case X86::TAILJMPm64_REX:
21718 llvm_unreachable("TAILJMP64 would not be touched here.");
21719 case X86::TCRETURNdi64:
21720 case X86::TCRETURNri64:
21721 case X86::TCRETURNmi64:
21723 case X86::WIN_ALLOCA:
21724 return EmitLoweredWinAlloca(MI, BB);
21725 case X86::SEG_ALLOCA_32:
21726 case X86::SEG_ALLOCA_64:
21727 return EmitLoweredSegAlloca(MI, BB);
21728 case X86::TLSCall_32:
21729 case X86::TLSCall_64:
21730 return EmitLoweredTLSCall(MI, BB);
21731 case X86::CMOV_FR32:
21732 case X86::CMOV_FR64:
21733 case X86::CMOV_GR8:
21734 case X86::CMOV_GR16:
21735 case X86::CMOV_GR32:
21736 case X86::CMOV_RFP32:
21737 case X86::CMOV_RFP64:
21738 case X86::CMOV_RFP80:
21739 case X86::CMOV_V2F64:
21740 case X86::CMOV_V2I64:
21741 case X86::CMOV_V4F32:
21742 case X86::CMOV_V4F64:
21743 case X86::CMOV_V4I64:
21744 case X86::CMOV_V16F32:
21745 case X86::CMOV_V8F32:
21746 case X86::CMOV_V8F64:
21747 case X86::CMOV_V8I64:
21748 case X86::CMOV_V8I1:
21749 case X86::CMOV_V16I1:
21750 case X86::CMOV_V32I1:
21751 case X86::CMOV_V64I1:
21752 return EmitLoweredSelect(MI, BB);
21754 case X86::RELEASE_FADD32mr:
21755 case X86::RELEASE_FADD64mr:
21756 return EmitLoweredAtomicFP(MI, BB);
21758 case X86::FP32_TO_INT16_IN_MEM:
21759 case X86::FP32_TO_INT32_IN_MEM:
21760 case X86::FP32_TO_INT64_IN_MEM:
21761 case X86::FP64_TO_INT16_IN_MEM:
21762 case X86::FP64_TO_INT32_IN_MEM:
21763 case X86::FP64_TO_INT64_IN_MEM:
21764 case X86::FP80_TO_INT16_IN_MEM:
21765 case X86::FP80_TO_INT32_IN_MEM:
21766 case X86::FP80_TO_INT64_IN_MEM: {
21767 MachineFunction *F = BB->getParent();
21768 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21769 DebugLoc DL = MI->getDebugLoc();
21771 // Change the floating point control register to use "round towards zero"
21772 // mode when truncating to an integer value.
21773 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21774 addFrameReference(BuildMI(*BB, MI, DL,
21775 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21777 // Load the old value of the high byte of the control word...
21779 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21780 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21783 // Set the high part to be round to zero...
21784 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21787 // Reload the modified control word now...
21788 addFrameReference(BuildMI(*BB, MI, DL,
21789 TII->get(X86::FLDCW16m)), CWFrameIdx);
21791 // Restore the memory image of control word to original value
21792 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21795 // Get the X86 opcode to use.
21797 switch (MI->getOpcode()) {
21798 default: llvm_unreachable("illegal opcode!");
21799 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21800 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21801 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21802 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21803 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21804 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21805 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21806 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21807 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21811 MachineOperand &Op = MI->getOperand(0);
21813 AM.BaseType = X86AddressMode::RegBase;
21814 AM.Base.Reg = Op.getReg();
21816 AM.BaseType = X86AddressMode::FrameIndexBase;
21817 AM.Base.FrameIndex = Op.getIndex();
21819 Op = MI->getOperand(1);
21821 AM.Scale = Op.getImm();
21822 Op = MI->getOperand(2);
21824 AM.IndexReg = Op.getImm();
21825 Op = MI->getOperand(3);
21826 if (Op.isGlobal()) {
21827 AM.GV = Op.getGlobal();
21829 AM.Disp = Op.getImm();
21831 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21832 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21834 // Reload the original control word now.
21835 addFrameReference(BuildMI(*BB, MI, DL,
21836 TII->get(X86::FLDCW16m)), CWFrameIdx);
21838 MI->eraseFromParent(); // The pseudo instruction is gone now.
21841 // String/text processing lowering.
21842 case X86::PCMPISTRM128REG:
21843 case X86::VPCMPISTRM128REG:
21844 case X86::PCMPISTRM128MEM:
21845 case X86::VPCMPISTRM128MEM:
21846 case X86::PCMPESTRM128REG:
21847 case X86::VPCMPESTRM128REG:
21848 case X86::PCMPESTRM128MEM:
21849 case X86::VPCMPESTRM128MEM:
21850 assert(Subtarget->hasSSE42() &&
21851 "Target must have SSE4.2 or AVX features enabled");
21852 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21854 // String/text processing lowering.
21855 case X86::PCMPISTRIREG:
21856 case X86::VPCMPISTRIREG:
21857 case X86::PCMPISTRIMEM:
21858 case X86::VPCMPISTRIMEM:
21859 case X86::PCMPESTRIREG:
21860 case X86::VPCMPESTRIREG:
21861 case X86::PCMPESTRIMEM:
21862 case X86::VPCMPESTRIMEM:
21863 assert(Subtarget->hasSSE42() &&
21864 "Target must have SSE4.2 or AVX features enabled");
21865 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21867 // Thread synchronization.
21869 return EmitMonitor(MI, BB, Subtarget);
21873 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21875 case X86::VASTART_SAVE_XMM_REGS:
21876 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21878 case X86::VAARG_64:
21879 return EmitVAARG64WithCustomInserter(MI, BB);
21881 case X86::EH_SjLj_SetJmp32:
21882 case X86::EH_SjLj_SetJmp64:
21883 return emitEHSjLjSetJmp(MI, BB);
21885 case X86::EH_SjLj_LongJmp32:
21886 case X86::EH_SjLj_LongJmp64:
21887 return emitEHSjLjLongJmp(MI, BB);
21889 case TargetOpcode::STATEPOINT:
21890 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21891 // this point in the process. We diverge later.
21892 return emitPatchPoint(MI, BB);
21894 case TargetOpcode::STACKMAP:
21895 case TargetOpcode::PATCHPOINT:
21896 return emitPatchPoint(MI, BB);
21898 case X86::VFMADDPDr213r:
21899 case X86::VFMADDPSr213r:
21900 case X86::VFMADDSDr213r:
21901 case X86::VFMADDSSr213r:
21902 case X86::VFMSUBPDr213r:
21903 case X86::VFMSUBPSr213r:
21904 case X86::VFMSUBSDr213r:
21905 case X86::VFMSUBSSr213r:
21906 case X86::VFNMADDPDr213r:
21907 case X86::VFNMADDPSr213r:
21908 case X86::VFNMADDSDr213r:
21909 case X86::VFNMADDSSr213r:
21910 case X86::VFNMSUBPDr213r:
21911 case X86::VFNMSUBPSr213r:
21912 case X86::VFNMSUBSDr213r:
21913 case X86::VFNMSUBSSr213r:
21914 case X86::VFMADDSUBPDr213r:
21915 case X86::VFMADDSUBPSr213r:
21916 case X86::VFMSUBADDPDr213r:
21917 case X86::VFMSUBADDPSr213r:
21918 case X86::VFMADDPDr213rY:
21919 case X86::VFMADDPSr213rY:
21920 case X86::VFMSUBPDr213rY:
21921 case X86::VFMSUBPSr213rY:
21922 case X86::VFNMADDPDr213rY:
21923 case X86::VFNMADDPSr213rY:
21924 case X86::VFNMSUBPDr213rY:
21925 case X86::VFNMSUBPSr213rY:
21926 case X86::VFMADDSUBPDr213rY:
21927 case X86::VFMADDSUBPSr213rY:
21928 case X86::VFMSUBADDPDr213rY:
21929 case X86::VFMSUBADDPSr213rY:
21930 return emitFMA3Instr(MI, BB);
21934 //===----------------------------------------------------------------------===//
21935 // X86 Optimization Hooks
21936 //===----------------------------------------------------------------------===//
21938 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21941 const SelectionDAG &DAG,
21942 unsigned Depth) const {
21943 unsigned BitWidth = KnownZero.getBitWidth();
21944 unsigned Opc = Op.getOpcode();
21945 assert((Opc >= ISD::BUILTIN_OP_END ||
21946 Opc == ISD::INTRINSIC_WO_CHAIN ||
21947 Opc == ISD::INTRINSIC_W_CHAIN ||
21948 Opc == ISD::INTRINSIC_VOID) &&
21949 "Should use MaskedValueIsZero if you don't know whether Op"
21950 " is a target node!");
21952 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21966 // These nodes' second result is a boolean.
21967 if (Op.getResNo() == 0)
21970 case X86ISD::SETCC:
21971 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21973 case ISD::INTRINSIC_WO_CHAIN: {
21974 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21975 unsigned NumLoBits = 0;
21978 case Intrinsic::x86_sse_movmsk_ps:
21979 case Intrinsic::x86_avx_movmsk_ps_256:
21980 case Intrinsic::x86_sse2_movmsk_pd:
21981 case Intrinsic::x86_avx_movmsk_pd_256:
21982 case Intrinsic::x86_mmx_pmovmskb:
21983 case Intrinsic::x86_sse2_pmovmskb_128:
21984 case Intrinsic::x86_avx2_pmovmskb: {
21985 // High bits of movmskp{s|d}, pmovmskb are known zero.
21987 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21988 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21989 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21990 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21991 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21992 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21993 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21994 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21996 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22005 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22007 const SelectionDAG &,
22008 unsigned Depth) const {
22009 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22010 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22011 return Op.getValueType().getScalarSizeInBits();
22017 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22018 /// node is a GlobalAddress + offset.
22019 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22020 const GlobalValue* &GA,
22021 int64_t &Offset) const {
22022 if (N->getOpcode() == X86ISD::Wrapper) {
22023 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22024 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22025 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22029 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22032 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
22033 /// same as extracting the high 128-bit part of 256-bit vector and then
22034 /// inserting the result into the low part of a new 256-bit vector
22035 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
22036 EVT VT = SVOp->getValueType(0);
22037 unsigned NumElems = VT.getVectorNumElements();
22039 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22040 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
22041 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22042 SVOp->getMaskElt(j) >= 0)
22048 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
22049 /// same as extracting the low 128-bit part of 256-bit vector and then
22050 /// inserting the result into the high part of a new 256-bit vector
22051 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
22052 EVT VT = SVOp->getValueType(0);
22053 unsigned NumElems = VT.getVectorNumElements();
22055 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22056 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
22057 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22058 SVOp->getMaskElt(j) >= 0)
22064 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22065 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22066 TargetLowering::DAGCombinerInfo &DCI,
22067 const X86Subtarget* Subtarget) {
22069 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22070 SDValue V1 = SVOp->getOperand(0);
22071 SDValue V2 = SVOp->getOperand(1);
22072 EVT VT = SVOp->getValueType(0);
22073 unsigned NumElems = VT.getVectorNumElements();
22075 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22076 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22080 // V UNDEF BUILD_VECTOR UNDEF
22082 // CONCAT_VECTOR CONCAT_VECTOR
22085 // RESULT: V + zero extended
22087 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22088 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22089 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22092 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22095 // To match the shuffle mask, the first half of the mask should
22096 // be exactly the first vector, and all the rest a splat with the
22097 // first element of the second one.
22098 for (unsigned i = 0; i != NumElems/2; ++i)
22099 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22100 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22103 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22104 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22105 if (Ld->hasNUsesOfValue(1, 0)) {
22106 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22107 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22109 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22111 Ld->getPointerInfo(),
22112 Ld->getAlignment(),
22113 false/*isVolatile*/, true/*ReadMem*/,
22114 false/*WriteMem*/);
22116 // Make sure the newly-created LOAD is in the same position as Ld in
22117 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22118 // and update uses of Ld's output chain to use the TokenFactor.
22119 if (Ld->hasAnyUseOfValue(1)) {
22120 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22121 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22122 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22123 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22124 SDValue(ResNode.getNode(), 1));
22127 return DAG.getBitcast(VT, ResNode);
22131 // Emit a zeroed vector and insert the desired subvector on its
22133 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22134 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22135 return DCI.CombineTo(N, InsV);
22138 //===--------------------------------------------------------------------===//
22139 // Combine some shuffles into subvector extracts and inserts:
22142 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22143 if (isShuffleHigh128VectorInsertLow(SVOp)) {
22144 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
22145 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
22146 return DCI.CombineTo(N, InsV);
22149 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22150 if (isShuffleLow128VectorInsertHigh(SVOp)) {
22151 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
22152 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
22153 return DCI.CombineTo(N, InsV);
22159 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22162 /// This is the leaf of the recursive combinine below. When we have found some
22163 /// chain of single-use x86 shuffle instructions and accumulated the combined
22164 /// shuffle mask represented by them, this will try to pattern match that mask
22165 /// into either a single instruction if there is a special purpose instruction
22166 /// for this operation, or into a PSHUFB instruction which is a fully general
22167 /// instruction but should only be used to replace chains over a certain depth.
22168 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22169 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22170 TargetLowering::DAGCombinerInfo &DCI,
22171 const X86Subtarget *Subtarget) {
22172 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22174 // Find the operand that enters the chain. Note that multiple uses are OK
22175 // here, we're not going to remove the operand we find.
22176 SDValue Input = Op.getOperand(0);
22177 while (Input.getOpcode() == ISD::BITCAST)
22178 Input = Input.getOperand(0);
22180 MVT VT = Input.getSimpleValueType();
22181 MVT RootVT = Root.getSimpleValueType();
22184 if (Mask.size() == 1) {
22185 int Index = Mask[0];
22186 assert((Index >= 0 || Index == SM_SentinelUndef ||
22187 Index == SM_SentinelZero) &&
22188 "Invalid shuffle index found!");
22190 // We may end up with an accumulated mask of size 1 as a result of
22191 // widening of shuffle operands (see function canWidenShuffleElements).
22192 // If the only shuffle index is equal to SM_SentinelZero then propagate
22193 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22194 // mask, and therefore the entire chain of shuffles can be folded away.
22195 if (Index == SM_SentinelZero)
22196 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22198 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22203 // Use the float domain if the operand type is a floating point type.
22204 bool FloatDomain = VT.isFloatingPoint();
22206 // For floating point shuffles, we don't have free copies in the shuffle
22207 // instructions or the ability to load as part of the instruction, so
22208 // canonicalize their shuffles to UNPCK or MOV variants.
22210 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22211 // vectors because it can have a load folded into it that UNPCK cannot. This
22212 // doesn't preclude something switching to the shorter encoding post-RA.
22214 // FIXME: Should teach these routines about AVX vector widths.
22215 if (FloatDomain && VT.is128BitVector()) {
22216 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22217 bool Lo = Mask.equals({0, 0});
22220 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22221 // is no slower than UNPCKLPD but has the option to fold the input operand
22222 // into even an unaligned memory load.
22223 if (Lo && Subtarget->hasSSE3()) {
22224 Shuffle = X86ISD::MOVDDUP;
22225 ShuffleVT = MVT::v2f64;
22227 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22228 // than the UNPCK variants.
22229 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22230 ShuffleVT = MVT::v4f32;
22232 if (Depth == 1 && Root->getOpcode() == Shuffle)
22233 return false; // Nothing to do!
22234 Op = DAG.getBitcast(ShuffleVT, Input);
22235 DCI.AddToWorklist(Op.getNode());
22236 if (Shuffle == X86ISD::MOVDDUP)
22237 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22239 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22240 DCI.AddToWorklist(Op.getNode());
22241 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22245 if (Subtarget->hasSSE3() &&
22246 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22247 bool Lo = Mask.equals({0, 0, 2, 2});
22248 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22249 MVT ShuffleVT = MVT::v4f32;
22250 if (Depth == 1 && Root->getOpcode() == Shuffle)
22251 return false; // Nothing to do!
22252 Op = DAG.getBitcast(ShuffleVT, Input);
22253 DCI.AddToWorklist(Op.getNode());
22254 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22255 DCI.AddToWorklist(Op.getNode());
22256 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22260 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22261 bool Lo = Mask.equals({0, 0, 1, 1});
22262 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22263 MVT ShuffleVT = MVT::v4f32;
22264 if (Depth == 1 && Root->getOpcode() == Shuffle)
22265 return false; // Nothing to do!
22266 Op = DAG.getBitcast(ShuffleVT, Input);
22267 DCI.AddToWorklist(Op.getNode());
22268 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22269 DCI.AddToWorklist(Op.getNode());
22270 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22276 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22277 // variants as none of these have single-instruction variants that are
22278 // superior to the UNPCK formulation.
22279 if (!FloatDomain && VT.is128BitVector() &&
22280 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22281 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22282 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22284 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22285 bool Lo = Mask[0] == 0;
22286 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22287 if (Depth == 1 && Root->getOpcode() == Shuffle)
22288 return false; // Nothing to do!
22290 switch (Mask.size()) {
22292 ShuffleVT = MVT::v8i16;
22295 ShuffleVT = MVT::v16i8;
22298 llvm_unreachable("Impossible mask size!");
22300 Op = DAG.getBitcast(ShuffleVT, Input);
22301 DCI.AddToWorklist(Op.getNode());
22302 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22303 DCI.AddToWorklist(Op.getNode());
22304 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22309 // Don't try to re-form single instruction chains under any circumstances now
22310 // that we've done encoding canonicalization for them.
22314 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22315 // can replace them with a single PSHUFB instruction profitably. Intel's
22316 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22317 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22318 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22319 SmallVector<SDValue, 16> PSHUFBMask;
22320 int NumBytes = VT.getSizeInBits() / 8;
22321 int Ratio = NumBytes / Mask.size();
22322 for (int i = 0; i < NumBytes; ++i) {
22323 if (Mask[i / Ratio] == SM_SentinelUndef) {
22324 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22327 int M = Mask[i / Ratio] != SM_SentinelZero
22328 ? Ratio * Mask[i / Ratio] + i % Ratio
22330 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22332 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22333 Op = DAG.getBitcast(ByteVT, Input);
22334 DCI.AddToWorklist(Op.getNode());
22335 SDValue PSHUFBMaskOp =
22336 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22337 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22338 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22339 DCI.AddToWorklist(Op.getNode());
22340 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22345 // Failed to find any combines.
22349 /// \brief Fully generic combining of x86 shuffle instructions.
22351 /// This should be the last combine run over the x86 shuffle instructions. Once
22352 /// they have been fully optimized, this will recursively consider all chains
22353 /// of single-use shuffle instructions, build a generic model of the cumulative
22354 /// shuffle operation, and check for simpler instructions which implement this
22355 /// operation. We use this primarily for two purposes:
22357 /// 1) Collapse generic shuffles to specialized single instructions when
22358 /// equivalent. In most cases, this is just an encoding size win, but
22359 /// sometimes we will collapse multiple generic shuffles into a single
22360 /// special-purpose shuffle.
22361 /// 2) Look for sequences of shuffle instructions with 3 or more total
22362 /// instructions, and replace them with the slightly more expensive SSSE3
22363 /// PSHUFB instruction if available. We do this as the last combining step
22364 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22365 /// a suitable short sequence of other instructions. The PHUFB will either
22366 /// use a register or have to read from memory and so is slightly (but only
22367 /// slightly) more expensive than the other shuffle instructions.
22369 /// Because this is inherently a quadratic operation (for each shuffle in
22370 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22371 /// This should never be an issue in practice as the shuffle lowering doesn't
22372 /// produce sequences of more than 8 instructions.
22374 /// FIXME: We will currently miss some cases where the redundant shuffling
22375 /// would simplify under the threshold for PSHUFB formation because of
22376 /// combine-ordering. To fix this, we should do the redundant instruction
22377 /// combining in this recursive walk.
22378 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22379 ArrayRef<int> RootMask,
22380 int Depth, bool HasPSHUFB,
22382 TargetLowering::DAGCombinerInfo &DCI,
22383 const X86Subtarget *Subtarget) {
22384 // Bound the depth of our recursive combine because this is ultimately
22385 // quadratic in nature.
22389 // Directly rip through bitcasts to find the underlying operand.
22390 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22391 Op = Op.getOperand(0);
22393 MVT VT = Op.getSimpleValueType();
22394 if (!VT.isVector())
22395 return false; // Bail if we hit a non-vector.
22397 assert(Root.getSimpleValueType().isVector() &&
22398 "Shuffles operate on vector types!");
22399 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22400 "Can only combine shuffles of the same vector register size.");
22402 if (!isTargetShuffle(Op.getOpcode()))
22404 SmallVector<int, 16> OpMask;
22406 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22407 // We only can combine unary shuffles which we can decode the mask for.
22408 if (!HaveMask || !IsUnary)
22411 assert(VT.getVectorNumElements() == OpMask.size() &&
22412 "Different mask size from vector size!");
22413 assert(((RootMask.size() > OpMask.size() &&
22414 RootMask.size() % OpMask.size() == 0) ||
22415 (OpMask.size() > RootMask.size() &&
22416 OpMask.size() % RootMask.size() == 0) ||
22417 OpMask.size() == RootMask.size()) &&
22418 "The smaller number of elements must divide the larger.");
22419 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22420 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22421 assert(((RootRatio == 1 && OpRatio == 1) ||
22422 (RootRatio == 1) != (OpRatio == 1)) &&
22423 "Must not have a ratio for both incoming and op masks!");
22425 SmallVector<int, 16> Mask;
22426 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22428 // Merge this shuffle operation's mask into our accumulated mask. Note that
22429 // this shuffle's mask will be the first applied to the input, followed by the
22430 // root mask to get us all the way to the root value arrangement. The reason
22431 // for this order is that we are recursing up the operation chain.
22432 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22433 int RootIdx = i / RootRatio;
22434 if (RootMask[RootIdx] < 0) {
22435 // This is a zero or undef lane, we're done.
22436 Mask.push_back(RootMask[RootIdx]);
22440 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22441 int OpIdx = RootMaskedIdx / OpRatio;
22442 if (OpMask[OpIdx] < 0) {
22443 // The incoming lanes are zero or undef, it doesn't matter which ones we
22445 Mask.push_back(OpMask[OpIdx]);
22449 // Ok, we have non-zero lanes, map them through.
22450 Mask.push_back(OpMask[OpIdx] * OpRatio +
22451 RootMaskedIdx % OpRatio);
22454 // See if we can recurse into the operand to combine more things.
22455 switch (Op.getOpcode()) {
22456 case X86ISD::PSHUFB:
22458 case X86ISD::PSHUFD:
22459 case X86ISD::PSHUFHW:
22460 case X86ISD::PSHUFLW:
22461 if (Op.getOperand(0).hasOneUse() &&
22462 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22463 HasPSHUFB, DAG, DCI, Subtarget))
22467 case X86ISD::UNPCKL:
22468 case X86ISD::UNPCKH:
22469 assert(Op.getOperand(0) == Op.getOperand(1) &&
22470 "We only combine unary shuffles!");
22471 // We can't check for single use, we have to check that this shuffle is the
22473 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22474 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22475 HasPSHUFB, DAG, DCI, Subtarget))
22480 // Minor canonicalization of the accumulated shuffle mask to make it easier
22481 // to match below. All this does is detect masks with squential pairs of
22482 // elements, and shrink them to the half-width mask. It does this in a loop
22483 // so it will reduce the size of the mask to the minimal width mask which
22484 // performs an equivalent shuffle.
22485 SmallVector<int, 16> WidenedMask;
22486 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22487 Mask = std::move(WidenedMask);
22488 WidenedMask.clear();
22491 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22495 /// \brief Get the PSHUF-style mask from PSHUF node.
22497 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22498 /// PSHUF-style masks that can be reused with such instructions.
22499 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22500 MVT VT = N.getSimpleValueType();
22501 SmallVector<int, 4> Mask;
22503 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22507 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22508 // matter. Check that the upper masks are repeats and remove them.
22509 if (VT.getSizeInBits() > 128) {
22510 int LaneElts = 128 / VT.getScalarSizeInBits();
22512 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22513 for (int j = 0; j < LaneElts; ++j)
22514 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22515 "Mask doesn't repeat in high 128-bit lanes!");
22517 Mask.resize(LaneElts);
22520 switch (N.getOpcode()) {
22521 case X86ISD::PSHUFD:
22523 case X86ISD::PSHUFLW:
22526 case X86ISD::PSHUFHW:
22527 Mask.erase(Mask.begin(), Mask.begin() + 4);
22528 for (int &M : Mask)
22532 llvm_unreachable("No valid shuffle instruction found!");
22536 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22538 /// We walk up the chain and look for a combinable shuffle, skipping over
22539 /// shuffles that we could hoist this shuffle's transformation past without
22540 /// altering anything.
22542 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22544 TargetLowering::DAGCombinerInfo &DCI) {
22545 assert(N.getOpcode() == X86ISD::PSHUFD &&
22546 "Called with something other than an x86 128-bit half shuffle!");
22549 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22550 // of the shuffles in the chain so that we can form a fresh chain to replace
22552 SmallVector<SDValue, 8> Chain;
22553 SDValue V = N.getOperand(0);
22554 for (; V.hasOneUse(); V = V.getOperand(0)) {
22555 switch (V.getOpcode()) {
22557 return SDValue(); // Nothing combined!
22560 // Skip bitcasts as we always know the type for the target specific
22564 case X86ISD::PSHUFD:
22565 // Found another dword shuffle.
22568 case X86ISD::PSHUFLW:
22569 // Check that the low words (being shuffled) are the identity in the
22570 // dword shuffle, and the high words are self-contained.
22571 if (Mask[0] != 0 || Mask[1] != 1 ||
22572 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22575 Chain.push_back(V);
22578 case X86ISD::PSHUFHW:
22579 // Check that the high words (being shuffled) are the identity in the
22580 // dword shuffle, and the low words are self-contained.
22581 if (Mask[2] != 2 || Mask[3] != 3 ||
22582 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22585 Chain.push_back(V);
22588 case X86ISD::UNPCKL:
22589 case X86ISD::UNPCKH:
22590 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22591 // shuffle into a preceding word shuffle.
22592 if (V.getSimpleValueType().getVectorElementType() != MVT::i8 &&
22593 V.getSimpleValueType().getVectorElementType() != MVT::i16)
22596 // Search for a half-shuffle which we can combine with.
22597 unsigned CombineOp =
22598 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22599 if (V.getOperand(0) != V.getOperand(1) ||
22600 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22602 Chain.push_back(V);
22603 V = V.getOperand(0);
22605 switch (V.getOpcode()) {
22607 return SDValue(); // Nothing to combine.
22609 case X86ISD::PSHUFLW:
22610 case X86ISD::PSHUFHW:
22611 if (V.getOpcode() == CombineOp)
22614 Chain.push_back(V);
22618 V = V.getOperand(0);
22622 } while (V.hasOneUse());
22625 // Break out of the loop if we break out of the switch.
22629 if (!V.hasOneUse())
22630 // We fell out of the loop without finding a viable combining instruction.
22633 // Merge this node's mask and our incoming mask.
22634 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22635 for (int &M : Mask)
22637 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22638 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22640 // Rebuild the chain around this new shuffle.
22641 while (!Chain.empty()) {
22642 SDValue W = Chain.pop_back_val();
22644 if (V.getValueType() != W.getOperand(0).getValueType())
22645 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22647 switch (W.getOpcode()) {
22649 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22651 case X86ISD::UNPCKL:
22652 case X86ISD::UNPCKH:
22653 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22656 case X86ISD::PSHUFD:
22657 case X86ISD::PSHUFLW:
22658 case X86ISD::PSHUFHW:
22659 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22663 if (V.getValueType() != N.getValueType())
22664 V = DAG.getBitcast(N.getValueType(), V);
22666 // Return the new chain to replace N.
22670 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22673 /// We walk up the chain, skipping shuffles of the other half and looking
22674 /// through shuffles which switch halves trying to find a shuffle of the same
22675 /// pair of dwords.
22676 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22678 TargetLowering::DAGCombinerInfo &DCI) {
22680 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22681 "Called with something other than an x86 128-bit half shuffle!");
22683 unsigned CombineOpcode = N.getOpcode();
22685 // Walk up a single-use chain looking for a combinable shuffle.
22686 SDValue V = N.getOperand(0);
22687 for (; V.hasOneUse(); V = V.getOperand(0)) {
22688 switch (V.getOpcode()) {
22690 return false; // Nothing combined!
22693 // Skip bitcasts as we always know the type for the target specific
22697 case X86ISD::PSHUFLW:
22698 case X86ISD::PSHUFHW:
22699 if (V.getOpcode() == CombineOpcode)
22702 // Other-half shuffles are no-ops.
22705 // Break out of the loop if we break out of the switch.
22709 if (!V.hasOneUse())
22710 // We fell out of the loop without finding a viable combining instruction.
22713 // Combine away the bottom node as its shuffle will be accumulated into
22714 // a preceding shuffle.
22715 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22717 // Record the old value.
22720 // Merge this node's mask and our incoming mask (adjusted to account for all
22721 // the pshufd instructions encountered).
22722 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22723 for (int &M : Mask)
22725 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22726 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22728 // Check that the shuffles didn't cancel each other out. If not, we need to
22729 // combine to the new one.
22731 // Replace the combinable shuffle with the combined one, updating all users
22732 // so that we re-evaluate the chain here.
22733 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22738 /// \brief Try to combine x86 target specific shuffles.
22739 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22740 TargetLowering::DAGCombinerInfo &DCI,
22741 const X86Subtarget *Subtarget) {
22743 MVT VT = N.getSimpleValueType();
22744 SmallVector<int, 4> Mask;
22746 switch (N.getOpcode()) {
22747 case X86ISD::PSHUFD:
22748 case X86ISD::PSHUFLW:
22749 case X86ISD::PSHUFHW:
22750 Mask = getPSHUFShuffleMask(N);
22751 assert(Mask.size() == 4);
22757 // Nuke no-op shuffles that show up after combining.
22758 if (isNoopShuffleMask(Mask))
22759 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22761 // Look for simplifications involving one or two shuffle instructions.
22762 SDValue V = N.getOperand(0);
22763 switch (N.getOpcode()) {
22766 case X86ISD::PSHUFLW:
22767 case X86ISD::PSHUFHW:
22768 assert(VT.getVectorElementType() == MVT::i16 && "Bad word shuffle type!");
22770 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22771 return SDValue(); // We combined away this shuffle, so we're done.
22773 // See if this reduces to a PSHUFD which is no more expensive and can
22774 // combine with more operations. Note that it has to at least flip the
22775 // dwords as otherwise it would have been removed as a no-op.
22776 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
22777 int DMask[] = {0, 1, 2, 3};
22778 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22779 DMask[DOffset + 0] = DOffset + 1;
22780 DMask[DOffset + 1] = DOffset + 0;
22781 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
22782 V = DAG.getBitcast(DVT, V);
22783 DCI.AddToWorklist(V.getNode());
22784 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
22785 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
22786 DCI.AddToWorklist(V.getNode());
22787 return DAG.getBitcast(VT, V);
22790 // Look for shuffle patterns which can be implemented as a single unpack.
22791 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22792 // only works when we have a PSHUFD followed by two half-shuffles.
22793 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22794 (V.getOpcode() == X86ISD::PSHUFLW ||
22795 V.getOpcode() == X86ISD::PSHUFHW) &&
22796 V.getOpcode() != N.getOpcode() &&
22798 SDValue D = V.getOperand(0);
22799 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22800 D = D.getOperand(0);
22801 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22802 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22803 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22804 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22805 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22807 for (int i = 0; i < 4; ++i) {
22808 WordMask[i + NOffset] = Mask[i] + NOffset;
22809 WordMask[i + VOffset] = VMask[i] + VOffset;
22811 // Map the word mask through the DWord mask.
22813 for (int i = 0; i < 8; ++i)
22814 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22815 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22816 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
22817 // We can replace all three shuffles with an unpack.
22818 V = DAG.getBitcast(VT, D.getOperand(0));
22819 DCI.AddToWorklist(V.getNode());
22820 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22829 case X86ISD::PSHUFD:
22830 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22839 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22841 /// We combine this directly on the abstract vector shuffle nodes so it is
22842 /// easier to generically match. We also insert dummy vector shuffle nodes for
22843 /// the operands which explicitly discard the lanes which are unused by this
22844 /// operation to try to flow through the rest of the combiner the fact that
22845 /// they're unused.
22846 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22848 EVT VT = N->getValueType(0);
22850 // We only handle target-independent shuffles.
22851 // FIXME: It would be easy and harmless to use the target shuffle mask
22852 // extraction tool to support more.
22853 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22856 auto *SVN = cast<ShuffleVectorSDNode>(N);
22857 ArrayRef<int> Mask = SVN->getMask();
22858 SDValue V1 = N->getOperand(0);
22859 SDValue V2 = N->getOperand(1);
22861 // We require the first shuffle operand to be the SUB node, and the second to
22862 // be the ADD node.
22863 // FIXME: We should support the commuted patterns.
22864 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22867 // If there are other uses of these operations we can't fold them.
22868 if (!V1->hasOneUse() || !V2->hasOneUse())
22871 // Ensure that both operations have the same operands. Note that we can
22872 // commute the FADD operands.
22873 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22874 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22875 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22878 // We're looking for blends between FADD and FSUB nodes. We insist on these
22879 // nodes being lined up in a specific expected pattern.
22880 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22881 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22882 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22885 // Only specific types are legal at this point, assert so we notice if and
22886 // when these change.
22887 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22888 VT == MVT::v4f64) &&
22889 "Unknown vector type encountered!");
22891 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22894 /// PerformShuffleCombine - Performs several different shuffle combines.
22895 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22896 TargetLowering::DAGCombinerInfo &DCI,
22897 const X86Subtarget *Subtarget) {
22899 SDValue N0 = N->getOperand(0);
22900 SDValue N1 = N->getOperand(1);
22901 EVT VT = N->getValueType(0);
22903 // Don't create instructions with illegal types after legalize types has run.
22904 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22905 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22908 // If we have legalized the vector types, look for blends of FADD and FSUB
22909 // nodes that we can fuse into an ADDSUB node.
22910 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22911 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22914 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22915 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22916 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22917 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22919 // During Type Legalization, when promoting illegal vector types,
22920 // the backend might introduce new shuffle dag nodes and bitcasts.
22922 // This code performs the following transformation:
22923 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22924 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22926 // We do this only if both the bitcast and the BINOP dag nodes have
22927 // one use. Also, perform this transformation only if the new binary
22928 // operation is legal. This is to avoid introducing dag nodes that
22929 // potentially need to be further expanded (or custom lowered) into a
22930 // less optimal sequence of dag nodes.
22931 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22932 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22933 N0.getOpcode() == ISD::BITCAST) {
22934 SDValue BC0 = N0.getOperand(0);
22935 EVT SVT = BC0.getValueType();
22936 unsigned Opcode = BC0.getOpcode();
22937 unsigned NumElts = VT.getVectorNumElements();
22939 if (BC0.hasOneUse() && SVT.isVector() &&
22940 SVT.getVectorNumElements() * 2 == NumElts &&
22941 TLI.isOperationLegal(Opcode, VT)) {
22942 bool CanFold = false;
22954 unsigned SVTNumElts = SVT.getVectorNumElements();
22955 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22956 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22957 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22958 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22959 CanFold = SVOp->getMaskElt(i) < 0;
22962 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
22963 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
22964 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22965 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22970 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22971 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22972 // consecutive, non-overlapping, and in the right order.
22973 SmallVector<SDValue, 16> Elts;
22974 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22975 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22977 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
22980 if (isTargetShuffle(N->getOpcode())) {
22982 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22983 if (Shuffle.getNode())
22986 // Try recursively combining arbitrary sequences of x86 shuffle
22987 // instructions into higher-order shuffles. We do this after combining
22988 // specific PSHUF instruction sequences into their minimal form so that we
22989 // can evaluate how many specialized shuffle instructions are involved in
22990 // a particular chain.
22991 SmallVector<int, 1> NonceMask; // Just a placeholder.
22992 NonceMask.push_back(0);
22993 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22994 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22996 return SDValue(); // This routine will use CombineTo to replace N.
23002 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23003 /// specific shuffle of a load can be folded into a single element load.
23004 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23005 /// shuffles have been custom lowered so we need to handle those here.
23006 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23007 TargetLowering::DAGCombinerInfo &DCI) {
23008 if (DCI.isBeforeLegalizeOps())
23011 SDValue InVec = N->getOperand(0);
23012 SDValue EltNo = N->getOperand(1);
23014 if (!isa<ConstantSDNode>(EltNo))
23017 EVT OriginalVT = InVec.getValueType();
23019 if (InVec.getOpcode() == ISD::BITCAST) {
23020 // Don't duplicate a load with other uses.
23021 if (!InVec.hasOneUse())
23023 EVT BCVT = InVec.getOperand(0).getValueType();
23024 if (!BCVT.isVector() ||
23025 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23027 InVec = InVec.getOperand(0);
23030 EVT CurrentVT = InVec.getValueType();
23032 if (!isTargetShuffle(InVec.getOpcode()))
23035 // Don't duplicate a load with other uses.
23036 if (!InVec.hasOneUse())
23039 SmallVector<int, 16> ShuffleMask;
23041 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
23042 ShuffleMask, UnaryShuffle))
23045 // Select the input vector, guarding against out of range extract vector.
23046 unsigned NumElems = CurrentVT.getVectorNumElements();
23047 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23048 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
23049 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23050 : InVec.getOperand(1);
23052 // If inputs to shuffle are the same for both ops, then allow 2 uses
23053 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23054 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23056 if (LdNode.getOpcode() == ISD::BITCAST) {
23057 // Don't duplicate a load with other uses.
23058 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23061 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23062 LdNode = LdNode.getOperand(0);
23065 if (!ISD::isNormalLoad(LdNode.getNode()))
23068 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23070 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23073 EVT EltVT = N->getValueType(0);
23074 // If there's a bitcast before the shuffle, check if the load type and
23075 // alignment is valid.
23076 unsigned Align = LN0->getAlignment();
23077 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23078 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23079 EltVT.getTypeForEVT(*DAG.getContext()));
23081 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23084 // All checks match so transform back to vector_shuffle so that DAG combiner
23085 // can finish the job
23088 // Create shuffle node taking into account the case that its a unary shuffle
23089 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23090 : InVec.getOperand(1);
23091 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23092 InVec.getOperand(0), Shuffle,
23094 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23095 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23099 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
23100 const X86Subtarget *Subtarget) {
23101 SDValue N0 = N->getOperand(0);
23102 EVT VT = N->getValueType(0);
23104 // Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23105 // special and don't usually play with other vector types, it's better to
23106 // handle them early to be sure we emit efficient code by avoiding
23107 // store-load conversions.
23108 if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
23109 N0.getValueType() == MVT::v2i32 &&
23110 isa<ConstantSDNode>(N0.getOperand(1))) {
23111 SDValue N00 = N0->getOperand(0);
23112 if (N0.getConstantOperandVal(1) == 0 && N00.getValueType() == MVT::i32)
23113 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
23116 // Convert a bitcasted integer logic operation that has one bitcasted
23117 // floating-point operand and one constant operand into a floating-point
23118 // logic operation. This may create a load of the constant, but that is
23119 // cheaper than materializing the constant in an integer register and
23120 // transferring it to an SSE register or transferring the SSE operand to
23121 // integer register and back.
23123 switch (N0.getOpcode()) {
23124 case ISD::AND: FPOpcode = X86ISD::FAND; break;
23125 case ISD::OR: FPOpcode = X86ISD::FOR; break;
23126 case ISD::XOR: FPOpcode = X86ISD::FXOR; break;
23127 default: return SDValue();
23129 if (((Subtarget->hasSSE1() && VT == MVT::f32) ||
23130 (Subtarget->hasSSE2() && VT == MVT::f64)) &&
23131 isa<ConstantSDNode>(N0.getOperand(1)) &&
23132 N0.getOperand(0).getOpcode() == ISD::BITCAST &&
23133 N0.getOperand(0).getOperand(0).getValueType() == VT) {
23134 SDValue N000 = N0.getOperand(0).getOperand(0);
23135 SDValue FPConst = DAG.getBitcast(VT, N0.getOperand(1));
23136 return DAG.getNode(FPOpcode, SDLoc(N0), VT, N000, FPConst);
23142 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23143 /// generation and convert it from being a bunch of shuffles and extracts
23144 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23145 /// storing the value and loading scalars back, while for x64 we should
23146 /// use 64-bit extracts and shifts.
23147 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23148 TargetLowering::DAGCombinerInfo &DCI) {
23149 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23152 SDValue InputVector = N->getOperand(0);
23153 SDLoc dl(InputVector);
23154 // Detect mmx to i32 conversion through a v2i32 elt extract.
23155 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23156 N->getValueType(0) == MVT::i32 &&
23157 InputVector.getValueType() == MVT::v2i32) {
23159 // The bitcast source is a direct mmx result.
23160 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23161 if (MMXSrc.getValueType() == MVT::x86mmx)
23162 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23163 N->getValueType(0),
23164 InputVector.getNode()->getOperand(0));
23166 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23167 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23168 MMXSrc.getValueType() == MVT::i64) {
23169 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23170 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23171 MMXSrcOp.getValueType() == MVT::v1i64 &&
23172 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23173 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23174 N->getValueType(0), MMXSrcOp.getOperand(0));
23178 EVT VT = N->getValueType(0);
23180 if (VT == MVT::i1 && isa<ConstantSDNode>(N->getOperand(1)) &&
23181 InputVector.getOpcode() == ISD::BITCAST &&
23182 isa<ConstantSDNode>(InputVector.getOperand(0))) {
23183 uint64_t ExtractedElt =
23184 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23185 uint64_t InputValue =
23186 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23187 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23188 return DAG.getConstant(Res, dl, MVT::i1);
23190 // Only operate on vectors of 4 elements, where the alternative shuffling
23191 // gets to be more expensive.
23192 if (InputVector.getValueType() != MVT::v4i32)
23195 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23196 // single use which is a sign-extend or zero-extend, and all elements are
23198 SmallVector<SDNode *, 4> Uses;
23199 unsigned ExtractedElements = 0;
23200 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23201 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23202 if (UI.getUse().getResNo() != InputVector.getResNo())
23205 SDNode *Extract = *UI;
23206 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23209 if (Extract->getValueType(0) != MVT::i32)
23211 if (!Extract->hasOneUse())
23213 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23214 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23216 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23219 // Record which element was extracted.
23220 ExtractedElements |=
23221 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23223 Uses.push_back(Extract);
23226 // If not all the elements were used, this may not be worthwhile.
23227 if (ExtractedElements != 15)
23230 // Ok, we've now decided to do the transformation.
23231 // If 64-bit shifts are legal, use the extract-shift sequence,
23232 // otherwise bounce the vector off the cache.
23233 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23236 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23237 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23238 auto &DL = DAG.getDataLayout();
23239 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23240 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23241 DAG.getConstant(0, dl, VecIdxTy));
23242 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23243 DAG.getConstant(1, dl, VecIdxTy));
23245 SDValue ShAmt = DAG.getConstant(
23246 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23247 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23248 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23249 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23250 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23251 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23252 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23254 // Store the value to a temporary stack slot.
23255 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23256 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23257 MachinePointerInfo(), false, false, 0);
23259 EVT ElementType = InputVector.getValueType().getVectorElementType();
23260 unsigned EltSize = ElementType.getSizeInBits() / 8;
23262 // Replace each use (extract) with a load of the appropriate element.
23263 for (unsigned i = 0; i < 4; ++i) {
23264 uint64_t Offset = EltSize * i;
23265 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23266 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23268 SDValue ScalarAddr =
23269 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23271 // Load the scalar.
23272 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23273 ScalarAddr, MachinePointerInfo(),
23274 false, false, false, 0);
23279 // Replace the extracts
23280 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23281 UE = Uses.end(); UI != UE; ++UI) {
23282 SDNode *Extract = *UI;
23284 SDValue Idx = Extract->getOperand(1);
23285 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23286 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23289 // The replacement was made in place; don't return anything.
23294 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23295 const X86Subtarget *Subtarget) {
23297 SDValue Cond = N->getOperand(0);
23298 SDValue LHS = N->getOperand(1);
23299 SDValue RHS = N->getOperand(2);
23301 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23302 SDValue CondSrc = Cond->getOperand(0);
23303 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23304 Cond = CondSrc->getOperand(0);
23307 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23310 // A vselect where all conditions and data are constants can be optimized into
23311 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23312 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23313 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23316 unsigned MaskValue = 0;
23317 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23320 MVT VT = N->getSimpleValueType(0);
23321 unsigned NumElems = VT.getVectorNumElements();
23322 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23323 for (unsigned i = 0; i < NumElems; ++i) {
23324 // Be sure we emit undef where we can.
23325 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23326 ShuffleMask[i] = -1;
23328 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23331 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23332 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23334 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23337 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23339 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23340 TargetLowering::DAGCombinerInfo &DCI,
23341 const X86Subtarget *Subtarget) {
23343 SDValue Cond = N->getOperand(0);
23344 // Get the LHS/RHS of the select.
23345 SDValue LHS = N->getOperand(1);
23346 SDValue RHS = N->getOperand(2);
23347 EVT VT = LHS.getValueType();
23348 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23350 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23351 // instructions match the semantics of the common C idiom x<y?x:y but not
23352 // x<=y?x:y, because of how they handle negative zero (which can be
23353 // ignored in unsafe-math mode).
23354 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23355 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23356 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23357 (Subtarget->hasSSE2() ||
23358 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23359 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23361 unsigned Opcode = 0;
23362 // Check for x CC y ? x : y.
23363 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23364 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23368 // Converting this to a min would handle NaNs incorrectly, and swapping
23369 // the operands would cause it to handle comparisons between positive
23370 // and negative zero incorrectly.
23371 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23372 if (!DAG.getTarget().Options.UnsafeFPMath &&
23373 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23375 std::swap(LHS, RHS);
23377 Opcode = X86ISD::FMIN;
23380 // Converting this to a min would handle comparisons between positive
23381 // and negative zero incorrectly.
23382 if (!DAG.getTarget().Options.UnsafeFPMath &&
23383 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23385 Opcode = X86ISD::FMIN;
23388 // Converting this to a min would handle both negative zeros and NaNs
23389 // incorrectly, but we can swap the operands to fix both.
23390 std::swap(LHS, RHS);
23394 Opcode = X86ISD::FMIN;
23398 // Converting this to a max would handle comparisons between positive
23399 // and negative zero incorrectly.
23400 if (!DAG.getTarget().Options.UnsafeFPMath &&
23401 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23403 Opcode = X86ISD::FMAX;
23406 // Converting this to a max would handle NaNs incorrectly, and swapping
23407 // the operands would cause it to handle comparisons between positive
23408 // and negative zero incorrectly.
23409 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23410 if (!DAG.getTarget().Options.UnsafeFPMath &&
23411 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23413 std::swap(LHS, RHS);
23415 Opcode = X86ISD::FMAX;
23418 // Converting this to a max would handle both negative zeros and NaNs
23419 // incorrectly, but we can swap the operands to fix both.
23420 std::swap(LHS, RHS);
23424 Opcode = X86ISD::FMAX;
23427 // Check for x CC y ? y : x -- a min/max with reversed arms.
23428 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23429 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23433 // Converting this to a min would handle comparisons between positive
23434 // and negative zero incorrectly, and swapping the operands would
23435 // cause it to handle NaNs incorrectly.
23436 if (!DAG.getTarget().Options.UnsafeFPMath &&
23437 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23438 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23440 std::swap(LHS, RHS);
23442 Opcode = X86ISD::FMIN;
23445 // Converting this to a min would handle NaNs incorrectly.
23446 if (!DAG.getTarget().Options.UnsafeFPMath &&
23447 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23449 Opcode = X86ISD::FMIN;
23452 // Converting this to a min would handle both negative zeros and NaNs
23453 // incorrectly, but we can swap the operands to fix both.
23454 std::swap(LHS, RHS);
23458 Opcode = X86ISD::FMIN;
23462 // Converting this to a max would handle NaNs incorrectly.
23463 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23465 Opcode = X86ISD::FMAX;
23468 // Converting this to a max would handle comparisons between positive
23469 // and negative zero incorrectly, and swapping the operands would
23470 // cause it to handle NaNs incorrectly.
23471 if (!DAG.getTarget().Options.UnsafeFPMath &&
23472 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23473 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23475 std::swap(LHS, RHS);
23477 Opcode = X86ISD::FMAX;
23480 // Converting this to a max would handle both negative zeros and NaNs
23481 // incorrectly, but we can swap the operands to fix both.
23482 std::swap(LHS, RHS);
23486 Opcode = X86ISD::FMAX;
23492 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23495 EVT CondVT = Cond.getValueType();
23496 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23497 CondVT.getVectorElementType() == MVT::i1) {
23498 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23499 // lowering on KNL. In this case we convert it to
23500 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23501 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23502 // Since SKX these selects have a proper lowering.
23503 EVT OpVT = LHS.getValueType();
23504 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23505 (OpVT.getVectorElementType() == MVT::i8 ||
23506 OpVT.getVectorElementType() == MVT::i16) &&
23507 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23508 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23509 DCI.AddToWorklist(Cond.getNode());
23510 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23513 // If this is a select between two integer constants, try to do some
23515 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23516 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23517 // Don't do this for crazy integer types.
23518 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23519 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23520 // so that TrueC (the true value) is larger than FalseC.
23521 bool NeedsCondInvert = false;
23523 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23524 // Efficiently invertible.
23525 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23526 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23527 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23528 NeedsCondInvert = true;
23529 std::swap(TrueC, FalseC);
23532 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23533 if (FalseC->getAPIntValue() == 0 &&
23534 TrueC->getAPIntValue().isPowerOf2()) {
23535 if (NeedsCondInvert) // Invert the condition if needed.
23536 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23537 DAG.getConstant(1, DL, Cond.getValueType()));
23539 // Zero extend the condition if needed.
23540 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23542 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23543 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23544 DAG.getConstant(ShAmt, DL, MVT::i8));
23547 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23548 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23549 if (NeedsCondInvert) // Invert the condition if needed.
23550 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23551 DAG.getConstant(1, DL, Cond.getValueType()));
23553 // Zero extend the condition if needed.
23554 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23555 FalseC->getValueType(0), Cond);
23556 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23557 SDValue(FalseC, 0));
23560 // Optimize cases that will turn into an LEA instruction. This requires
23561 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23562 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23563 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23564 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23566 bool isFastMultiplier = false;
23568 switch ((unsigned char)Diff) {
23570 case 1: // result = add base, cond
23571 case 2: // result = lea base( , cond*2)
23572 case 3: // result = lea base(cond, cond*2)
23573 case 4: // result = lea base( , cond*4)
23574 case 5: // result = lea base(cond, cond*4)
23575 case 8: // result = lea base( , cond*8)
23576 case 9: // result = lea base(cond, cond*8)
23577 isFastMultiplier = true;
23582 if (isFastMultiplier) {
23583 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23584 if (NeedsCondInvert) // Invert the condition if needed.
23585 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23586 DAG.getConstant(1, DL, Cond.getValueType()));
23588 // Zero extend the condition if needed.
23589 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23591 // Scale the condition by the difference.
23593 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23594 DAG.getConstant(Diff, DL,
23595 Cond.getValueType()));
23597 // Add the base if non-zero.
23598 if (FalseC->getAPIntValue() != 0)
23599 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23600 SDValue(FalseC, 0));
23607 // Canonicalize max and min:
23608 // (x > y) ? x : y -> (x >= y) ? x : y
23609 // (x < y) ? x : y -> (x <= y) ? x : y
23610 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23611 // the need for an extra compare
23612 // against zero. e.g.
23613 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23615 // testl %edi, %edi
23617 // cmovgl %edi, %eax
23621 // cmovsl %eax, %edi
23622 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23623 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23624 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23625 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23630 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23631 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23632 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23633 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23638 // Early exit check
23639 if (!TLI.isTypeLegal(VT))
23642 // Match VSELECTs into subs with unsigned saturation.
23643 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23644 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23645 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23646 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23647 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23649 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23650 // left side invert the predicate to simplify logic below.
23652 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23654 CC = ISD::getSetCCInverse(CC, true);
23655 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23659 if (Other.getNode() && Other->getNumOperands() == 2 &&
23660 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23661 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23662 SDValue CondRHS = Cond->getOperand(1);
23664 // Look for a general sub with unsigned saturation first.
23665 // x >= y ? x-y : 0 --> subus x, y
23666 // x > y ? x-y : 0 --> subus x, y
23667 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23668 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23669 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23671 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23672 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23673 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23674 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23675 // If the RHS is a constant we have to reverse the const
23676 // canonicalization.
23677 // x > C-1 ? x+-C : 0 --> subus x, C
23678 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23679 CondRHSConst->getAPIntValue() ==
23680 (-OpRHSConst->getAPIntValue() - 1))
23681 return DAG.getNode(
23682 X86ISD::SUBUS, DL, VT, OpLHS,
23683 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23685 // Another special case: If C was a sign bit, the sub has been
23686 // canonicalized into a xor.
23687 // FIXME: Would it be better to use computeKnownBits to determine
23688 // whether it's safe to decanonicalize the xor?
23689 // x s< 0 ? x^C : 0 --> subus x, C
23690 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23691 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23692 OpRHSConst->getAPIntValue().isSignBit())
23693 // Note that we have to rebuild the RHS constant here to ensure we
23694 // don't rely on particular values of undef lanes.
23695 return DAG.getNode(
23696 X86ISD::SUBUS, DL, VT, OpLHS,
23697 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23702 // Simplify vector selection if condition value type matches vselect
23704 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23705 assert(Cond.getValueType().isVector() &&
23706 "vector select expects a vector selector!");
23708 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23709 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23711 // Try invert the condition if true value is not all 1s and false value
23713 if (!TValIsAllOnes && !FValIsAllZeros &&
23714 // Check if the selector will be produced by CMPP*/PCMP*
23715 Cond.getOpcode() == ISD::SETCC &&
23716 // Check if SETCC has already been promoted
23717 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23719 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23720 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23722 if (TValIsAllZeros || FValIsAllOnes) {
23723 SDValue CC = Cond.getOperand(2);
23724 ISD::CondCode NewCC =
23725 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23726 Cond.getOperand(0).getValueType().isInteger());
23727 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23728 std::swap(LHS, RHS);
23729 TValIsAllOnes = FValIsAllOnes;
23730 FValIsAllZeros = TValIsAllZeros;
23734 if (TValIsAllOnes || FValIsAllZeros) {
23737 if (TValIsAllOnes && FValIsAllZeros)
23739 else if (TValIsAllOnes)
23741 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
23742 else if (FValIsAllZeros)
23743 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23744 DAG.getBitcast(CondVT, LHS));
23746 return DAG.getBitcast(VT, Ret);
23750 // We should generate an X86ISD::BLENDI from a vselect if its argument
23751 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23752 // constants. This specific pattern gets generated when we split a
23753 // selector for a 512 bit vector in a machine without AVX512 (but with
23754 // 256-bit vectors), during legalization:
23756 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23758 // Iff we find this pattern and the build_vectors are built from
23759 // constants, we translate the vselect into a shuffle_vector that we
23760 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23761 if ((N->getOpcode() == ISD::VSELECT ||
23762 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23763 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
23764 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23765 if (Shuffle.getNode())
23769 // If this is a *dynamic* select (non-constant condition) and we can match
23770 // this node with one of the variable blend instructions, restructure the
23771 // condition so that the blends can use the high bit of each element and use
23772 // SimplifyDemandedBits to simplify the condition operand.
23773 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23774 !DCI.isBeforeLegalize() &&
23775 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23776 unsigned BitWidth = Cond.getValueType().getScalarSizeInBits();
23778 // Don't optimize vector selects that map to mask-registers.
23782 // We can only handle the cases where VSELECT is directly legal on the
23783 // subtarget. We custom lower VSELECT nodes with constant conditions and
23784 // this makes it hard to see whether a dynamic VSELECT will correctly
23785 // lower, so we both check the operation's status and explicitly handle the
23786 // cases where a *dynamic* blend will fail even though a constant-condition
23787 // blend could be custom lowered.
23788 // FIXME: We should find a better way to handle this class of problems.
23789 // Potentially, we should combine constant-condition vselect nodes
23790 // pre-legalization into shuffles and not mark as many types as custom
23792 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
23794 // FIXME: We don't support i16-element blends currently. We could and
23795 // should support them by making *all* the bits in the condition be set
23796 // rather than just the high bit and using an i8-element blend.
23797 if (VT.getVectorElementType() == MVT::i16)
23799 // Dynamic blending was only available from SSE4.1 onward.
23800 if (VT.is128BitVector() && !Subtarget->hasSSE41())
23802 // Byte blends are only available in AVX2
23803 if (VT == MVT::v32i8 && !Subtarget->hasAVX2())
23806 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23807 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23809 APInt KnownZero, KnownOne;
23810 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23811 DCI.isBeforeLegalizeOps());
23812 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23813 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23815 // If we changed the computation somewhere in the DAG, this change
23816 // will affect all users of Cond.
23817 // Make sure it is fine and update all the nodes so that we do not
23818 // use the generic VSELECT anymore. Otherwise, we may perform
23819 // wrong optimizations as we messed up with the actual expectation
23820 // for the vector boolean values.
23821 if (Cond != TLO.Old) {
23822 // Check all uses of that condition operand to check whether it will be
23823 // consumed by non-BLEND instructions, which may depend on all bits are
23825 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23827 if (I->getOpcode() != ISD::VSELECT)
23828 // TODO: Add other opcodes eventually lowered into BLEND.
23831 // Update all the users of the condition, before committing the change,
23832 // so that the VSELECT optimizations that expect the correct vector
23833 // boolean value will not be triggered.
23834 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23836 DAG.ReplaceAllUsesOfValueWith(
23838 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23839 Cond, I->getOperand(1), I->getOperand(2)));
23840 DCI.CommitTargetLoweringOpt(TLO);
23843 // At this point, only Cond is changed. Change the condition
23844 // just for N to keep the opportunity to optimize all other
23845 // users their own way.
23846 DAG.ReplaceAllUsesOfValueWith(
23848 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23849 TLO.New, N->getOperand(1), N->getOperand(2)));
23857 // Check whether a boolean test is testing a boolean value generated by
23858 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23861 // Simplify the following patterns:
23862 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23863 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23864 // to (Op EFLAGS Cond)
23866 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23867 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23868 // to (Op EFLAGS !Cond)
23870 // where Op could be BRCOND or CMOV.
23872 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23873 // Quit if not CMP and SUB with its value result used.
23874 if (Cmp.getOpcode() != X86ISD::CMP &&
23875 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23878 // Quit if not used as a boolean value.
23879 if (CC != X86::COND_E && CC != X86::COND_NE)
23882 // Check CMP operands. One of them should be 0 or 1 and the other should be
23883 // an SetCC or extended from it.
23884 SDValue Op1 = Cmp.getOperand(0);
23885 SDValue Op2 = Cmp.getOperand(1);
23888 const ConstantSDNode* C = nullptr;
23889 bool needOppositeCond = (CC == X86::COND_E);
23890 bool checkAgainstTrue = false; // Is it a comparison against 1?
23892 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23894 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23896 else // Quit if all operands are not constants.
23899 if (C->getZExtValue() == 1) {
23900 needOppositeCond = !needOppositeCond;
23901 checkAgainstTrue = true;
23902 } else if (C->getZExtValue() != 0)
23903 // Quit if the constant is neither 0 or 1.
23906 bool truncatedToBoolWithAnd = false;
23907 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23908 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23909 SetCC.getOpcode() == ISD::TRUNCATE ||
23910 SetCC.getOpcode() == ISD::AND) {
23911 if (SetCC.getOpcode() == ISD::AND) {
23913 ConstantSDNode *CS;
23914 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23915 CS->getZExtValue() == 1)
23917 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23918 CS->getZExtValue() == 1)
23922 SetCC = SetCC.getOperand(OpIdx);
23923 truncatedToBoolWithAnd = true;
23925 SetCC = SetCC.getOperand(0);
23928 switch (SetCC.getOpcode()) {
23929 case X86ISD::SETCC_CARRY:
23930 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23931 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23932 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23933 // truncated to i1 using 'and'.
23934 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23936 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23937 "Invalid use of SETCC_CARRY!");
23939 case X86ISD::SETCC:
23940 // Set the condition code or opposite one if necessary.
23941 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23942 if (needOppositeCond)
23943 CC = X86::GetOppositeBranchCondition(CC);
23944 return SetCC.getOperand(1);
23945 case X86ISD::CMOV: {
23946 // Check whether false/true value has canonical one, i.e. 0 or 1.
23947 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23948 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23949 // Quit if true value is not a constant.
23952 // Quit if false value is not a constant.
23954 SDValue Op = SetCC.getOperand(0);
23955 // Skip 'zext' or 'trunc' node.
23956 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23957 Op.getOpcode() == ISD::TRUNCATE)
23958 Op = Op.getOperand(0);
23959 // A special case for rdrand/rdseed, where 0 is set if false cond is
23961 if ((Op.getOpcode() != X86ISD::RDRAND &&
23962 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23965 // Quit if false value is not the constant 0 or 1.
23966 bool FValIsFalse = true;
23967 if (FVal && FVal->getZExtValue() != 0) {
23968 if (FVal->getZExtValue() != 1)
23970 // If FVal is 1, opposite cond is needed.
23971 needOppositeCond = !needOppositeCond;
23972 FValIsFalse = false;
23974 // Quit if TVal is not the constant opposite of FVal.
23975 if (FValIsFalse && TVal->getZExtValue() != 1)
23977 if (!FValIsFalse && TVal->getZExtValue() != 0)
23979 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23980 if (needOppositeCond)
23981 CC = X86::GetOppositeBranchCondition(CC);
23982 return SetCC.getOperand(3);
23989 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
23991 /// (X86or (X86setcc) (X86setcc))
23992 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
23993 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
23994 X86::CondCode &CC1, SDValue &Flags,
23996 if (Cond->getOpcode() == X86ISD::CMP) {
23997 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
23998 if (!CondOp1C || !CondOp1C->isNullValue())
24001 Cond = Cond->getOperand(0);
24006 SDValue SetCC0, SetCC1;
24007 switch (Cond->getOpcode()) {
24008 default: return false;
24015 SetCC0 = Cond->getOperand(0);
24016 SetCC1 = Cond->getOperand(1);
24020 // Make sure we have SETCC nodes, using the same flags value.
24021 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24022 SetCC1.getOpcode() != X86ISD::SETCC ||
24023 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24026 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24027 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24028 Flags = SetCC0->getOperand(1);
24032 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24033 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24034 TargetLowering::DAGCombinerInfo &DCI,
24035 const X86Subtarget *Subtarget) {
24038 // If the flag operand isn't dead, don't touch this CMOV.
24039 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24042 SDValue FalseOp = N->getOperand(0);
24043 SDValue TrueOp = N->getOperand(1);
24044 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24045 SDValue Cond = N->getOperand(3);
24047 if (CC == X86::COND_E || CC == X86::COND_NE) {
24048 switch (Cond.getOpcode()) {
24052 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24053 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24054 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24060 Flags = checkBoolTestSetCCCombine(Cond, CC);
24061 if (Flags.getNode() &&
24062 // Extra check as FCMOV only supports a subset of X86 cond.
24063 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24064 SDValue Ops[] = { FalseOp, TrueOp,
24065 DAG.getConstant(CC, DL, MVT::i8), Flags };
24066 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24069 // If this is a select between two integer constants, try to do some
24070 // optimizations. Note that the operands are ordered the opposite of SELECT
24072 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24073 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24074 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24075 // larger than FalseC (the false value).
24076 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24077 CC = X86::GetOppositeBranchCondition(CC);
24078 std::swap(TrueC, FalseC);
24079 std::swap(TrueOp, FalseOp);
24082 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24083 // This is efficient for any integer data type (including i8/i16) and
24085 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24086 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24087 DAG.getConstant(CC, DL, MVT::i8), Cond);
24089 // Zero extend the condition if needed.
24090 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24092 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24093 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24094 DAG.getConstant(ShAmt, DL, MVT::i8));
24095 if (N->getNumValues() == 2) // Dead flag value?
24096 return DCI.CombineTo(N, Cond, SDValue());
24100 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24101 // for any integer data type, including i8/i16.
24102 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24103 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24104 DAG.getConstant(CC, DL, MVT::i8), Cond);
24106 // Zero extend the condition if needed.
24107 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24108 FalseC->getValueType(0), Cond);
24109 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24110 SDValue(FalseC, 0));
24112 if (N->getNumValues() == 2) // Dead flag value?
24113 return DCI.CombineTo(N, Cond, SDValue());
24117 // Optimize cases that will turn into an LEA instruction. This requires
24118 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24119 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24120 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24121 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24123 bool isFastMultiplier = false;
24125 switch ((unsigned char)Diff) {
24127 case 1: // result = add base, cond
24128 case 2: // result = lea base( , cond*2)
24129 case 3: // result = lea base(cond, cond*2)
24130 case 4: // result = lea base( , cond*4)
24131 case 5: // result = lea base(cond, cond*4)
24132 case 8: // result = lea base( , cond*8)
24133 case 9: // result = lea base(cond, cond*8)
24134 isFastMultiplier = true;
24139 if (isFastMultiplier) {
24140 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24141 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24142 DAG.getConstant(CC, DL, MVT::i8), Cond);
24143 // Zero extend the condition if needed.
24144 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24146 // Scale the condition by the difference.
24148 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24149 DAG.getConstant(Diff, DL, Cond.getValueType()));
24151 // Add the base if non-zero.
24152 if (FalseC->getAPIntValue() != 0)
24153 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24154 SDValue(FalseC, 0));
24155 if (N->getNumValues() == 2) // Dead flag value?
24156 return DCI.CombineTo(N, Cond, SDValue());
24163 // Handle these cases:
24164 // (select (x != c), e, c) -> select (x != c), e, x),
24165 // (select (x == c), c, e) -> select (x == c), x, e)
24166 // where the c is an integer constant, and the "select" is the combination
24167 // of CMOV and CMP.
24169 // The rationale for this change is that the conditional-move from a constant
24170 // needs two instructions, however, conditional-move from a register needs
24171 // only one instruction.
24173 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24174 // some instruction-combining opportunities. This opt needs to be
24175 // postponed as late as possible.
24177 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24178 // the DCI.xxxx conditions are provided to postpone the optimization as
24179 // late as possible.
24181 ConstantSDNode *CmpAgainst = nullptr;
24182 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24183 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24184 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24186 if (CC == X86::COND_NE &&
24187 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24188 CC = X86::GetOppositeBranchCondition(CC);
24189 std::swap(TrueOp, FalseOp);
24192 if (CC == X86::COND_E &&
24193 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24194 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24195 DAG.getConstant(CC, DL, MVT::i8), Cond };
24196 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24201 // Fold and/or of setcc's to double CMOV:
24202 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24203 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24205 // This combine lets us generate:
24206 // cmovcc1 (jcc1 if we don't have CMOV)
24212 // cmovne (jne if we don't have CMOV)
24213 // When we can't use the CMOV instruction, it might increase branch
24215 // When we can use CMOV, or when there is no mispredict, this improves
24216 // throughput and reduces register pressure.
24218 if (CC == X86::COND_NE) {
24220 X86::CondCode CC0, CC1;
24222 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24224 std::swap(FalseOp, TrueOp);
24225 CC0 = X86::GetOppositeBranchCondition(CC0);
24226 CC1 = X86::GetOppositeBranchCondition(CC1);
24229 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24231 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24232 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24233 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24234 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24242 /// PerformMulCombine - Optimize a single multiply with constant into two
24243 /// in order to implement it with two cheaper instructions, e.g.
24244 /// LEA + SHL, LEA + LEA.
24245 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24246 TargetLowering::DAGCombinerInfo &DCI) {
24247 // An imul is usually smaller than the alternative sequence.
24248 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24251 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24254 EVT VT = N->getValueType(0);
24255 if (VT != MVT::i64 && VT != MVT::i32)
24258 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24261 uint64_t MulAmt = C->getZExtValue();
24262 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24265 uint64_t MulAmt1 = 0;
24266 uint64_t MulAmt2 = 0;
24267 if ((MulAmt % 9) == 0) {
24269 MulAmt2 = MulAmt / 9;
24270 } else if ((MulAmt % 5) == 0) {
24272 MulAmt2 = MulAmt / 5;
24273 } else if ((MulAmt % 3) == 0) {
24275 MulAmt2 = MulAmt / 3;
24278 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24281 if (isPowerOf2_64(MulAmt2) &&
24282 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24283 // If second multiplifer is pow2, issue it first. We want the multiply by
24284 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24286 std::swap(MulAmt1, MulAmt2);
24289 if (isPowerOf2_64(MulAmt1))
24290 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24291 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24293 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24294 DAG.getConstant(MulAmt1, DL, VT));
24296 if (isPowerOf2_64(MulAmt2))
24297 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24298 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24300 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24301 DAG.getConstant(MulAmt2, DL, VT));
24303 // Do not add new nodes to DAG combiner worklist.
24304 DCI.CombineTo(N, NewMul, false);
24309 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24310 SDValue N0 = N->getOperand(0);
24311 SDValue N1 = N->getOperand(1);
24312 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24313 EVT VT = N0.getValueType();
24315 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24316 // since the result of setcc_c is all zero's or all ones.
24317 if (VT.isInteger() && !VT.isVector() &&
24318 N1C && N0.getOpcode() == ISD::AND &&
24319 N0.getOperand(1).getOpcode() == ISD::Constant) {
24320 SDValue N00 = N0.getOperand(0);
24321 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24322 APInt ShAmt = N1C->getAPIntValue();
24323 Mask = Mask.shl(ShAmt);
24324 bool MaskOK = false;
24325 // We can handle cases concerning bit-widening nodes containing setcc_c if
24326 // we carefully interrogate the mask to make sure we are semantics
24328 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24329 // of the underlying setcc_c operation if the setcc_c was zero extended.
24330 // Consider the following example:
24331 // zext(setcc_c) -> i32 0x0000FFFF
24332 // c1 -> i32 0x0000FFFF
24333 // c2 -> i32 0x00000001
24334 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24335 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24336 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24338 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24339 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24341 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24342 N00.getOpcode() == ISD::ANY_EXTEND) &&
24343 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24344 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24346 if (MaskOK && Mask != 0) {
24348 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24352 // Hardware support for vector shifts is sparse which makes us scalarize the
24353 // vector operations in many cases. Also, on sandybridge ADD is faster than
24355 // (shl V, 1) -> add V,V
24356 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24357 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24358 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24359 // We shift all of the values by one. In many cases we do not have
24360 // hardware support for this operation. This is better expressed as an ADD
24362 if (N1SplatC->getAPIntValue() == 1)
24363 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24369 /// \brief Returns a vector of 0s if the node in input is a vector logical
24370 /// shift by a constant amount which is known to be bigger than or equal
24371 /// to the vector element size in bits.
24372 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24373 const X86Subtarget *Subtarget) {
24374 EVT VT = N->getValueType(0);
24376 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24377 (!Subtarget->hasInt256() ||
24378 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24381 SDValue Amt = N->getOperand(1);
24383 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24384 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24385 APInt ShiftAmt = AmtSplat->getAPIntValue();
24386 unsigned MaxAmount =
24387 VT.getSimpleVT().getVectorElementType().getSizeInBits();
24389 // SSE2/AVX2 logical shifts always return a vector of 0s
24390 // if the shift amount is bigger than or equal to
24391 // the element size. The constant shift amount will be
24392 // encoded as a 8-bit immediate.
24393 if (ShiftAmt.trunc(8).uge(MaxAmount))
24394 return getZeroVector(VT, Subtarget, DAG, DL);
24400 /// PerformShiftCombine - Combine shifts.
24401 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24402 TargetLowering::DAGCombinerInfo &DCI,
24403 const X86Subtarget *Subtarget) {
24404 if (N->getOpcode() == ISD::SHL)
24405 if (SDValue V = PerformSHLCombine(N, DAG))
24408 // Try to fold this logical shift into a zero vector.
24409 if (N->getOpcode() != ISD::SRA)
24410 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24416 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24417 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24418 // and friends. Likewise for OR -> CMPNEQSS.
24419 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24420 TargetLowering::DAGCombinerInfo &DCI,
24421 const X86Subtarget *Subtarget) {
24424 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24425 // we're requiring SSE2 for both.
24426 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24427 SDValue N0 = N->getOperand(0);
24428 SDValue N1 = N->getOperand(1);
24429 SDValue CMP0 = N0->getOperand(1);
24430 SDValue CMP1 = N1->getOperand(1);
24433 // The SETCCs should both refer to the same CMP.
24434 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24437 SDValue CMP00 = CMP0->getOperand(0);
24438 SDValue CMP01 = CMP0->getOperand(1);
24439 EVT VT = CMP00.getValueType();
24441 if (VT == MVT::f32 || VT == MVT::f64) {
24442 bool ExpectingFlags = false;
24443 // Check for any users that want flags:
24444 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24445 !ExpectingFlags && UI != UE; ++UI)
24446 switch (UI->getOpcode()) {
24451 ExpectingFlags = true;
24453 case ISD::CopyToReg:
24454 case ISD::SIGN_EXTEND:
24455 case ISD::ZERO_EXTEND:
24456 case ISD::ANY_EXTEND:
24460 if (!ExpectingFlags) {
24461 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24462 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24464 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24465 X86::CondCode tmp = cc0;
24470 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24471 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24472 // FIXME: need symbolic constants for these magic numbers.
24473 // See X86ATTInstPrinter.cpp:printSSECC().
24474 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24475 if (Subtarget->hasAVX512()) {
24476 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24478 DAG.getConstant(x86cc, DL, MVT::i8));
24479 if (N->getValueType(0) != MVT::i1)
24480 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24484 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24485 CMP00.getValueType(), CMP00, CMP01,
24486 DAG.getConstant(x86cc, DL,
24489 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24490 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24492 if (is64BitFP && !Subtarget->is64Bit()) {
24493 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24494 // 64-bit integer, since that's not a legal type. Since
24495 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24496 // bits, but can do this little dance to extract the lowest 32 bits
24497 // and work with those going forward.
24498 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24500 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24501 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24502 Vector32, DAG.getIntPtrConstant(0, DL));
24506 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24507 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24508 DAG.getConstant(1, DL, IntVT));
24509 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24511 return OneBitOfTruth;
24519 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24520 /// so it can be folded inside ANDNP.
24521 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24522 EVT VT = N->getValueType(0);
24524 // Match direct AllOnes for 128 and 256-bit vectors
24525 if (ISD::isBuildVectorAllOnes(N))
24528 // Look through a bit convert.
24529 if (N->getOpcode() == ISD::BITCAST)
24530 N = N->getOperand(0).getNode();
24532 // Sometimes the operand may come from a insert_subvector building a 256-bit
24534 if (VT.is256BitVector() &&
24535 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24536 SDValue V1 = N->getOperand(0);
24537 SDValue V2 = N->getOperand(1);
24539 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24540 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24541 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24542 ISD::isBuildVectorAllOnes(V2.getNode()))
24549 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24550 // register. In most cases we actually compare or select YMM-sized registers
24551 // and mixing the two types creates horrible code. This method optimizes
24552 // some of the transition sequences.
24553 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24554 TargetLowering::DAGCombinerInfo &DCI,
24555 const X86Subtarget *Subtarget) {
24556 EVT VT = N->getValueType(0);
24557 if (!VT.is256BitVector())
24560 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24561 N->getOpcode() == ISD::ZERO_EXTEND ||
24562 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24564 SDValue Narrow = N->getOperand(0);
24565 EVT NarrowVT = Narrow->getValueType(0);
24566 if (!NarrowVT.is128BitVector())
24569 if (Narrow->getOpcode() != ISD::XOR &&
24570 Narrow->getOpcode() != ISD::AND &&
24571 Narrow->getOpcode() != ISD::OR)
24574 SDValue N0 = Narrow->getOperand(0);
24575 SDValue N1 = Narrow->getOperand(1);
24578 // The Left side has to be a trunc.
24579 if (N0.getOpcode() != ISD::TRUNCATE)
24582 // The type of the truncated inputs.
24583 EVT WideVT = N0->getOperand(0)->getValueType(0);
24587 // The right side has to be a 'trunc' or a constant vector.
24588 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24589 ConstantSDNode *RHSConstSplat = nullptr;
24590 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24591 RHSConstSplat = RHSBV->getConstantSplatNode();
24592 if (!RHSTrunc && !RHSConstSplat)
24595 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24597 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24600 // Set N0 and N1 to hold the inputs to the new wide operation.
24601 N0 = N0->getOperand(0);
24602 if (RHSConstSplat) {
24603 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(),
24604 SDValue(RHSConstSplat, 0));
24605 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24606 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24607 } else if (RHSTrunc) {
24608 N1 = N1->getOperand(0);
24611 // Generate the wide operation.
24612 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24613 unsigned Opcode = N->getOpcode();
24615 case ISD::ANY_EXTEND:
24617 case ISD::ZERO_EXTEND: {
24618 unsigned InBits = NarrowVT.getScalarSizeInBits();
24619 APInt Mask = APInt::getAllOnesValue(InBits);
24620 Mask = Mask.zext(VT.getScalarSizeInBits());
24621 return DAG.getNode(ISD::AND, DL, VT,
24622 Op, DAG.getConstant(Mask, DL, VT));
24624 case ISD::SIGN_EXTEND:
24625 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24626 Op, DAG.getValueType(NarrowVT));
24628 llvm_unreachable("Unexpected opcode");
24632 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24633 TargetLowering::DAGCombinerInfo &DCI,
24634 const X86Subtarget *Subtarget) {
24635 SDValue N0 = N->getOperand(0);
24636 SDValue N1 = N->getOperand(1);
24639 // A vector zext_in_reg may be represented as a shuffle,
24640 // feeding into a bitcast (this represents anyext) feeding into
24641 // an and with a mask.
24642 // We'd like to try to combine that into a shuffle with zero
24643 // plus a bitcast, removing the and.
24644 if (N0.getOpcode() != ISD::BITCAST ||
24645 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24648 // The other side of the AND should be a splat of 2^C, where C
24649 // is the number of bits in the source type.
24650 if (N1.getOpcode() == ISD::BITCAST)
24651 N1 = N1.getOperand(0);
24652 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24654 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24656 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24657 EVT SrcType = Shuffle->getValueType(0);
24659 // We expect a single-source shuffle
24660 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24663 unsigned SrcSize = SrcType.getScalarSizeInBits();
24665 APInt SplatValue, SplatUndef;
24666 unsigned SplatBitSize;
24668 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24669 SplatBitSize, HasAnyUndefs))
24672 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24673 // Make sure the splat matches the mask we expect
24674 if (SplatBitSize > ResSize ||
24675 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24678 // Make sure the input and output size make sense
24679 if (SrcSize >= ResSize || ResSize % SrcSize)
24682 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24683 // The number of u's between each two values depends on the ratio between
24684 // the source and dest type.
24685 unsigned ZextRatio = ResSize / SrcSize;
24686 bool IsZext = true;
24687 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24688 if (i % ZextRatio) {
24689 if (Shuffle->getMaskElt(i) > 0) {
24695 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24696 // Expected element number
24706 // Ok, perform the transformation - replace the shuffle with
24707 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24708 // (instead of undef) where the k elements come from the zero vector.
24709 SmallVector<int, 8> Mask;
24710 unsigned NumElems = SrcType.getVectorNumElements();
24711 for (unsigned i = 0; i < NumElems; ++i)
24713 Mask.push_back(NumElems);
24715 Mask.push_back(i / ZextRatio);
24717 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24718 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24719 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24722 /// If both input operands of a logic op are being cast from floating point
24723 /// types, try to convert this into a floating point logic node to avoid
24724 /// unnecessary moves from SSE to integer registers.
24725 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
24726 const X86Subtarget *Subtarget) {
24727 unsigned FPOpcode = ISD::DELETED_NODE;
24728 if (N->getOpcode() == ISD::AND)
24729 FPOpcode = X86ISD::FAND;
24730 else if (N->getOpcode() == ISD::OR)
24731 FPOpcode = X86ISD::FOR;
24732 else if (N->getOpcode() == ISD::XOR)
24733 FPOpcode = X86ISD::FXOR;
24735 assert(FPOpcode != ISD::DELETED_NODE &&
24736 "Unexpected input node for FP logic conversion");
24738 EVT VT = N->getValueType(0);
24739 SDValue N0 = N->getOperand(0);
24740 SDValue N1 = N->getOperand(1);
24742 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
24743 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
24744 (Subtarget->hasSSE2() && VT == MVT::i64))) {
24745 SDValue N00 = N0.getOperand(0);
24746 SDValue N10 = N1.getOperand(0);
24747 EVT N00Type = N00.getValueType();
24748 EVT N10Type = N10.getValueType();
24749 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
24750 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
24751 return DAG.getBitcast(VT, FPLogic);
24757 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24758 TargetLowering::DAGCombinerInfo &DCI,
24759 const X86Subtarget *Subtarget) {
24760 if (DCI.isBeforeLegalizeOps())
24763 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
24766 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24769 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24772 EVT VT = N->getValueType(0);
24773 SDValue N0 = N->getOperand(0);
24774 SDValue N1 = N->getOperand(1);
24777 // Create BEXTR instructions
24778 // BEXTR is ((X >> imm) & (2**size-1))
24779 if (VT == MVT::i32 || VT == MVT::i64) {
24780 // Check for BEXTR.
24781 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24782 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24783 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24784 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24785 if (MaskNode && ShiftNode) {
24786 uint64_t Mask = MaskNode->getZExtValue();
24787 uint64_t Shift = ShiftNode->getZExtValue();
24788 if (isMask_64(Mask)) {
24789 uint64_t MaskSize = countPopulation(Mask);
24790 if (Shift + MaskSize <= VT.getSizeInBits())
24791 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24792 DAG.getConstant(Shift | (MaskSize << 8), DL,
24801 // Want to form ANDNP nodes:
24802 // 1) In the hopes of then easily combining them with OR and AND nodes
24803 // to form PBLEND/PSIGN.
24804 // 2) To match ANDN packed intrinsics
24805 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24808 // Check LHS for vnot
24809 if (N0.getOpcode() == ISD::XOR &&
24810 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24811 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24812 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24814 // Check RHS for vnot
24815 if (N1.getOpcode() == ISD::XOR &&
24816 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24817 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24818 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24823 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24824 TargetLowering::DAGCombinerInfo &DCI,
24825 const X86Subtarget *Subtarget) {
24826 if (DCI.isBeforeLegalizeOps())
24829 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24832 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24835 SDValue N0 = N->getOperand(0);
24836 SDValue N1 = N->getOperand(1);
24837 EVT VT = N->getValueType(0);
24839 // look for psign/blend
24840 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24841 if (!Subtarget->hasSSSE3() ||
24842 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24845 // Canonicalize pandn to RHS
24846 if (N0.getOpcode() == X86ISD::ANDNP)
24848 // or (and (m, y), (pandn m, x))
24849 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24850 SDValue Mask = N1.getOperand(0);
24851 SDValue X = N1.getOperand(1);
24853 if (N0.getOperand(0) == Mask)
24854 Y = N0.getOperand(1);
24855 if (N0.getOperand(1) == Mask)
24856 Y = N0.getOperand(0);
24858 // Check to see if the mask appeared in both the AND and ANDNP and
24862 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24863 // Look through mask bitcast.
24864 if (Mask.getOpcode() == ISD::BITCAST)
24865 Mask = Mask.getOperand(0);
24866 if (X.getOpcode() == ISD::BITCAST)
24867 X = X.getOperand(0);
24868 if (Y.getOpcode() == ISD::BITCAST)
24869 Y = Y.getOperand(0);
24871 EVT MaskVT = Mask.getValueType();
24873 // Validate that the Mask operand is a vector sra node.
24874 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24875 // there is no psrai.b
24876 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24877 unsigned SraAmt = ~0;
24878 if (Mask.getOpcode() == ISD::SRA) {
24879 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24880 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24881 SraAmt = AmtConst->getZExtValue();
24882 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24883 SDValue SraC = Mask.getOperand(1);
24884 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24886 if ((SraAmt + 1) != EltBits)
24891 // Now we know we at least have a plendvb with the mask val. See if
24892 // we can form a psignb/w/d.
24893 // psign = x.type == y.type == mask.type && y = sub(0, x);
24894 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24895 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24896 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24897 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24898 "Unsupported VT for PSIGN");
24899 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24900 return DAG.getBitcast(VT, Mask);
24902 // PBLENDVB only available on SSE 4.1
24903 if (!Subtarget->hasSSE41())
24906 MVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24908 X = DAG.getBitcast(BlendVT, X);
24909 Y = DAG.getBitcast(BlendVT, Y);
24910 Mask = DAG.getBitcast(BlendVT, Mask);
24911 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24912 return DAG.getBitcast(VT, Mask);
24916 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24919 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24920 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
24922 // SHLD/SHRD instructions have lower register pressure, but on some
24923 // platforms they have higher latency than the equivalent
24924 // series of shifts/or that would otherwise be generated.
24925 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24926 // have higher latencies and we are not optimizing for size.
24927 if (!OptForSize && Subtarget->isSHLDSlow())
24930 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24932 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24934 if (!N0.hasOneUse() || !N1.hasOneUse())
24937 SDValue ShAmt0 = N0.getOperand(1);
24938 if (ShAmt0.getValueType() != MVT::i8)
24940 SDValue ShAmt1 = N1.getOperand(1);
24941 if (ShAmt1.getValueType() != MVT::i8)
24943 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24944 ShAmt0 = ShAmt0.getOperand(0);
24945 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24946 ShAmt1 = ShAmt1.getOperand(0);
24949 unsigned Opc = X86ISD::SHLD;
24950 SDValue Op0 = N0.getOperand(0);
24951 SDValue Op1 = N1.getOperand(0);
24952 if (ShAmt0.getOpcode() == ISD::SUB) {
24953 Opc = X86ISD::SHRD;
24954 std::swap(Op0, Op1);
24955 std::swap(ShAmt0, ShAmt1);
24958 unsigned Bits = VT.getSizeInBits();
24959 if (ShAmt1.getOpcode() == ISD::SUB) {
24960 SDValue Sum = ShAmt1.getOperand(0);
24961 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24962 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24963 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24964 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24965 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24966 return DAG.getNode(Opc, DL, VT,
24968 DAG.getNode(ISD::TRUNCATE, DL,
24971 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24972 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24974 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24975 return DAG.getNode(Opc, DL, VT,
24976 N0.getOperand(0), N1.getOperand(0),
24977 DAG.getNode(ISD::TRUNCATE, DL,
24984 // Generate NEG and CMOV for integer abs.
24985 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24986 EVT VT = N->getValueType(0);
24988 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24989 // 8-bit integer abs to NEG and CMOV.
24990 if (VT.isInteger() && VT.getSizeInBits() == 8)
24993 SDValue N0 = N->getOperand(0);
24994 SDValue N1 = N->getOperand(1);
24997 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24998 // and change it to SUB and CMOV.
24999 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25000 N0.getOpcode() == ISD::ADD &&
25001 N0.getOperand(1) == N1 &&
25002 N1.getOpcode() == ISD::SRA &&
25003 N1.getOperand(0) == N0.getOperand(0))
25004 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25005 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25006 // Generate SUB & CMOV.
25007 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25008 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25010 SDValue Ops[] = { N0.getOperand(0), Neg,
25011 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25012 SDValue(Neg.getNode(), 1) };
25013 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25018 // Try to turn tests against the signbit in the form of:
25019 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25022 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25023 // This is only worth doing if the output type is i8.
25024 if (N->getValueType(0) != MVT::i8)
25027 SDValue N0 = N->getOperand(0);
25028 SDValue N1 = N->getOperand(1);
25030 // We should be performing an xor against a truncated shift.
25031 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25034 // Make sure we are performing an xor against one.
25035 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
25038 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25039 SDValue Shift = N0.getOperand(0);
25040 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25043 // Make sure we are truncating from one of i16, i32 or i64.
25044 EVT ShiftTy = Shift.getValueType();
25045 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25048 // Make sure the shift amount extracts the sign bit.
25049 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25050 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25053 // Create a greater-than comparison against -1.
25054 // N.B. Using SETGE against 0 works but we want a canonical looking
25055 // comparison, using SETGT matches up with what TranslateX86CC.
25057 SDValue ShiftOp = Shift.getOperand(0);
25058 EVT ShiftOpTy = ShiftOp.getValueType();
25059 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
25060 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
25064 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25065 TargetLowering::DAGCombinerInfo &DCI,
25066 const X86Subtarget *Subtarget) {
25067 if (DCI.isBeforeLegalizeOps())
25070 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
25073 if (Subtarget->hasCMov())
25074 if (SDValue RV = performIntegerAbsCombine(N, DAG))
25077 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25083 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
25084 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
25085 TargetLowering::DAGCombinerInfo &DCI,
25086 const X86Subtarget *Subtarget) {
25087 LoadSDNode *Ld = cast<LoadSDNode>(N);
25088 EVT RegVT = Ld->getValueType(0);
25089 EVT MemVT = Ld->getMemoryVT();
25091 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25093 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
25094 // into two 16-byte operations.
25095 ISD::LoadExtType Ext = Ld->getExtensionType();
25097 unsigned AddressSpace = Ld->getAddressSpace();
25098 unsigned Alignment = Ld->getAlignment();
25099 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
25100 Ext == ISD::NON_EXTLOAD &&
25101 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25102 AddressSpace, Alignment, &Fast) && !Fast) {
25103 unsigned NumElems = RegVT.getVectorNumElements();
25107 SDValue Ptr = Ld->getBasePtr();
25108 SDValue Increment =
25109 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25111 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
25113 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25114 Ld->getPointerInfo(), Ld->isVolatile(),
25115 Ld->isNonTemporal(), Ld->isInvariant(),
25117 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25118 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25119 Ld->getPointerInfo(), Ld->isVolatile(),
25120 Ld->isNonTemporal(), Ld->isInvariant(),
25121 std::min(16U, Alignment));
25122 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
25124 Load2.getValue(1));
25126 SDValue NewVec = DAG.getUNDEF(RegVT);
25127 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
25128 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
25129 return DCI.CombineTo(N, NewVec, TF, true);
25135 /// PerformMLOADCombine - Resolve extending loads
25136 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
25137 TargetLowering::DAGCombinerInfo &DCI,
25138 const X86Subtarget *Subtarget) {
25139 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
25140 if (Mld->getExtensionType() != ISD::SEXTLOAD)
25143 EVT VT = Mld->getValueType(0);
25144 unsigned NumElems = VT.getVectorNumElements();
25145 EVT LdVT = Mld->getMemoryVT();
25148 assert(LdVT != VT && "Cannot extend to the same type");
25149 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
25150 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
25151 // From, To sizes and ElemCount must be pow of two
25152 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25153 "Unexpected size for extending masked load");
25155 unsigned SizeRatio = ToSz / FromSz;
25156 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
25158 // Create a type on which we perform the shuffle
25159 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25160 LdVT.getScalarType(), NumElems*SizeRatio);
25161 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25163 // Convert Src0 value
25164 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
25165 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
25166 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25167 for (unsigned i = 0; i != NumElems; ++i)
25168 ShuffleVec[i] = i * SizeRatio;
25170 // Can't shuffle using an illegal type.
25171 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25172 "WideVecVT should be legal");
25173 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
25174 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
25176 // Prepare the new mask
25178 SDValue Mask = Mld->getMask();
25179 if (Mask.getValueType() == VT) {
25180 // Mask and original value have the same type
25181 NewMask = DAG.getBitcast(WideVecVT, Mask);
25182 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25183 for (unsigned i = 0; i != NumElems; ++i)
25184 ShuffleVec[i] = i * SizeRatio;
25185 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25186 ShuffleVec[i] = NumElems*SizeRatio;
25187 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25188 DAG.getConstant(0, dl, WideVecVT),
25192 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25193 unsigned WidenNumElts = NumElems*SizeRatio;
25194 unsigned MaskNumElts = VT.getVectorNumElements();
25195 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25198 unsigned NumConcat = WidenNumElts / MaskNumElts;
25199 SmallVector<SDValue, 16> Ops(NumConcat);
25200 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25202 for (unsigned i = 1; i != NumConcat; ++i)
25205 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25208 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
25209 Mld->getBasePtr(), NewMask, WideSrc0,
25210 Mld->getMemoryVT(), Mld->getMemOperand(),
25212 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
25213 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
25215 /// PerformMSTORECombine - Resolve truncating stores
25216 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
25217 const X86Subtarget *Subtarget) {
25218 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
25219 if (!Mst->isTruncatingStore())
25222 EVT VT = Mst->getValue().getValueType();
25223 unsigned NumElems = VT.getVectorNumElements();
25224 EVT StVT = Mst->getMemoryVT();
25227 assert(StVT != VT && "Cannot truncate to the same type");
25228 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25229 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25231 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25233 // The truncating store is legal in some cases. For example
25234 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25235 // are designated for truncate store.
25236 // In this case we don't need any further transformations.
25237 if (TLI.isTruncStoreLegal(VT, StVT))
25240 // From, To sizes and ElemCount must be pow of two
25241 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25242 "Unexpected size for truncating masked store");
25243 // We are going to use the original vector elt for storing.
25244 // Accumulated smaller vector elements must be a multiple of the store size.
25245 assert (((NumElems * FromSz) % ToSz) == 0 &&
25246 "Unexpected ratio for truncating masked store");
25248 unsigned SizeRatio = FromSz / ToSz;
25249 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25251 // Create a type on which we perform the shuffle
25252 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25253 StVT.getScalarType(), NumElems*SizeRatio);
25255 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25257 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25258 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25259 for (unsigned i = 0; i != NumElems; ++i)
25260 ShuffleVec[i] = i * SizeRatio;
25262 // Can't shuffle using an illegal type.
25263 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25264 "WideVecVT should be legal");
25266 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25267 DAG.getUNDEF(WideVecVT),
25271 SDValue Mask = Mst->getMask();
25272 if (Mask.getValueType() == VT) {
25273 // Mask and original value have the same type
25274 NewMask = DAG.getBitcast(WideVecVT, Mask);
25275 for (unsigned i = 0; i != NumElems; ++i)
25276 ShuffleVec[i] = i * SizeRatio;
25277 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25278 ShuffleVec[i] = NumElems*SizeRatio;
25279 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25280 DAG.getConstant(0, dl, WideVecVT),
25284 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25285 unsigned WidenNumElts = NumElems*SizeRatio;
25286 unsigned MaskNumElts = VT.getVectorNumElements();
25287 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25290 unsigned NumConcat = WidenNumElts / MaskNumElts;
25291 SmallVector<SDValue, 16> Ops(NumConcat);
25292 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25294 for (unsigned i = 1; i != NumConcat; ++i)
25297 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25300 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
25301 NewMask, StVT, Mst->getMemOperand(), false);
25303 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25304 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25305 const X86Subtarget *Subtarget) {
25306 StoreSDNode *St = cast<StoreSDNode>(N);
25307 EVT VT = St->getValue().getValueType();
25308 EVT StVT = St->getMemoryVT();
25310 SDValue StoredVal = St->getOperand(1);
25311 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25313 // If we are saving a concatenation of two XMM registers and 32-byte stores
25314 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25316 unsigned AddressSpace = St->getAddressSpace();
25317 unsigned Alignment = St->getAlignment();
25318 if (VT.is256BitVector() && StVT == VT &&
25319 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25320 AddressSpace, Alignment, &Fast) && !Fast) {
25321 unsigned NumElems = VT.getVectorNumElements();
25325 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25326 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25329 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25330 SDValue Ptr0 = St->getBasePtr();
25331 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25333 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25334 St->getPointerInfo(), St->isVolatile(),
25335 St->isNonTemporal(), Alignment);
25336 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25337 St->getPointerInfo(), St->isVolatile(),
25338 St->isNonTemporal(),
25339 std::min(16U, Alignment));
25340 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25343 // Optimize trunc store (of multiple scalars) to shuffle and store.
25344 // First, pack all of the elements in one place. Next, store to memory
25345 // in fewer chunks.
25346 if (St->isTruncatingStore() && VT.isVector()) {
25347 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25348 unsigned NumElems = VT.getVectorNumElements();
25349 assert(StVT != VT && "Cannot truncate to the same type");
25350 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25351 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25353 // The truncating store is legal in some cases. For example
25354 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25355 // are designated for truncate store.
25356 // In this case we don't need any further transformations.
25357 if (TLI.isTruncStoreLegal(VT, StVT))
25360 // From, To sizes and ElemCount must be pow of two
25361 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25362 // We are going to use the original vector elt for storing.
25363 // Accumulated smaller vector elements must be a multiple of the store size.
25364 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25366 unsigned SizeRatio = FromSz / ToSz;
25368 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25370 // Create a type on which we perform the shuffle
25371 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25372 StVT.getScalarType(), NumElems*SizeRatio);
25374 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25376 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25377 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25378 for (unsigned i = 0; i != NumElems; ++i)
25379 ShuffleVec[i] = i * SizeRatio;
25381 // Can't shuffle using an illegal type.
25382 if (!TLI.isTypeLegal(WideVecVT))
25385 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25386 DAG.getUNDEF(WideVecVT),
25388 // At this point all of the data is stored at the bottom of the
25389 // register. We now need to save it to mem.
25391 // Find the largest store unit
25392 MVT StoreType = MVT::i8;
25393 for (MVT Tp : MVT::integer_valuetypes()) {
25394 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25398 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25399 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25400 (64 <= NumElems * ToSz))
25401 StoreType = MVT::f64;
25403 // Bitcast the original vector into a vector of store-size units
25404 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25405 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25406 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25407 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25408 SmallVector<SDValue, 8> Chains;
25409 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25410 TLI.getPointerTy(DAG.getDataLayout()));
25411 SDValue Ptr = St->getBasePtr();
25413 // Perform one or more big stores into memory.
25414 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25415 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25416 StoreType, ShuffWide,
25417 DAG.getIntPtrConstant(i, dl));
25418 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25419 St->getPointerInfo(), St->isVolatile(),
25420 St->isNonTemporal(), St->getAlignment());
25421 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25422 Chains.push_back(Ch);
25425 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25428 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25429 // the FP state in cases where an emms may be missing.
25430 // A preferable solution to the general problem is to figure out the right
25431 // places to insert EMMS. This qualifies as a quick hack.
25433 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25434 if (VT.getSizeInBits() != 64)
25437 const Function *F = DAG.getMachineFunction().getFunction();
25438 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25440 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25441 if ((VT.isVector() ||
25442 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25443 isa<LoadSDNode>(St->getValue()) &&
25444 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25445 St->getChain().hasOneUse() && !St->isVolatile()) {
25446 SDNode* LdVal = St->getValue().getNode();
25447 LoadSDNode *Ld = nullptr;
25448 int TokenFactorIndex = -1;
25449 SmallVector<SDValue, 8> Ops;
25450 SDNode* ChainVal = St->getChain().getNode();
25451 // Must be a store of a load. We currently handle two cases: the load
25452 // is a direct child, and it's under an intervening TokenFactor. It is
25453 // possible to dig deeper under nested TokenFactors.
25454 if (ChainVal == LdVal)
25455 Ld = cast<LoadSDNode>(St->getChain());
25456 else if (St->getValue().hasOneUse() &&
25457 ChainVal->getOpcode() == ISD::TokenFactor) {
25458 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25459 if (ChainVal->getOperand(i).getNode() == LdVal) {
25460 TokenFactorIndex = i;
25461 Ld = cast<LoadSDNode>(St->getValue());
25463 Ops.push_back(ChainVal->getOperand(i));
25467 if (!Ld || !ISD::isNormalLoad(Ld))
25470 // If this is not the MMX case, i.e. we are just turning i64 load/store
25471 // into f64 load/store, avoid the transformation if there are multiple
25472 // uses of the loaded value.
25473 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25478 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25479 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25481 if (Subtarget->is64Bit() || F64IsLegal) {
25482 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25483 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25484 Ld->getPointerInfo(), Ld->isVolatile(),
25485 Ld->isNonTemporal(), Ld->isInvariant(),
25486 Ld->getAlignment());
25487 SDValue NewChain = NewLd.getValue(1);
25488 if (TokenFactorIndex != -1) {
25489 Ops.push_back(NewChain);
25490 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25492 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25493 St->getPointerInfo(),
25494 St->isVolatile(), St->isNonTemporal(),
25495 St->getAlignment());
25498 // Otherwise, lower to two pairs of 32-bit loads / stores.
25499 SDValue LoAddr = Ld->getBasePtr();
25500 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25501 DAG.getConstant(4, LdDL, MVT::i32));
25503 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25504 Ld->getPointerInfo(),
25505 Ld->isVolatile(), Ld->isNonTemporal(),
25506 Ld->isInvariant(), Ld->getAlignment());
25507 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25508 Ld->getPointerInfo().getWithOffset(4),
25509 Ld->isVolatile(), Ld->isNonTemporal(),
25511 MinAlign(Ld->getAlignment(), 4));
25513 SDValue NewChain = LoLd.getValue(1);
25514 if (TokenFactorIndex != -1) {
25515 Ops.push_back(LoLd);
25516 Ops.push_back(HiLd);
25517 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25520 LoAddr = St->getBasePtr();
25521 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25522 DAG.getConstant(4, StDL, MVT::i32));
25524 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25525 St->getPointerInfo(),
25526 St->isVolatile(), St->isNonTemporal(),
25527 St->getAlignment());
25528 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25529 St->getPointerInfo().getWithOffset(4),
25531 St->isNonTemporal(),
25532 MinAlign(St->getAlignment(), 4));
25533 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25536 // This is similar to the above case, but here we handle a scalar 64-bit
25537 // integer store that is extracted from a vector on a 32-bit target.
25538 // If we have SSE2, then we can treat it like a floating-point double
25539 // to get past legalization. The execution dependencies fixup pass will
25540 // choose the optimal machine instruction for the store if this really is
25541 // an integer or v2f32 rather than an f64.
25542 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25543 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25544 SDValue OldExtract = St->getOperand(1);
25545 SDValue ExtOp0 = OldExtract.getOperand(0);
25546 unsigned VecSize = ExtOp0.getValueSizeInBits();
25547 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25548 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25549 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25550 BitCast, OldExtract.getOperand(1));
25551 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25552 St->getPointerInfo(), St->isVolatile(),
25553 St->isNonTemporal(), St->getAlignment());
25559 /// Return 'true' if this vector operation is "horizontal"
25560 /// and return the operands for the horizontal operation in LHS and RHS. A
25561 /// horizontal operation performs the binary operation on successive elements
25562 /// of its first operand, then on successive elements of its second operand,
25563 /// returning the resulting values in a vector. For example, if
25564 /// A = < float a0, float a1, float a2, float a3 >
25566 /// B = < float b0, float b1, float b2, float b3 >
25567 /// then the result of doing a horizontal operation on A and B is
25568 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25569 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25570 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25571 /// set to A, RHS to B, and the routine returns 'true'.
25572 /// Note that the binary operation should have the property that if one of the
25573 /// operands is UNDEF then the result is UNDEF.
25574 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25575 // Look for the following pattern: if
25576 // A = < float a0, float a1, float a2, float a3 >
25577 // B = < float b0, float b1, float b2, float b3 >
25579 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25580 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25581 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25582 // which is A horizontal-op B.
25584 // At least one of the operands should be a vector shuffle.
25585 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25586 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25589 MVT VT = LHS.getSimpleValueType();
25591 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25592 "Unsupported vector type for horizontal add/sub");
25594 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25595 // operate independently on 128-bit lanes.
25596 unsigned NumElts = VT.getVectorNumElements();
25597 unsigned NumLanes = VT.getSizeInBits()/128;
25598 unsigned NumLaneElts = NumElts / NumLanes;
25599 assert((NumLaneElts % 2 == 0) &&
25600 "Vector type should have an even number of elements in each lane");
25601 unsigned HalfLaneElts = NumLaneElts/2;
25603 // View LHS in the form
25604 // LHS = VECTOR_SHUFFLE A, B, LMask
25605 // If LHS is not a shuffle then pretend it is the shuffle
25606 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25607 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25610 SmallVector<int, 16> LMask(NumElts);
25611 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25612 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25613 A = LHS.getOperand(0);
25614 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25615 B = LHS.getOperand(1);
25616 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25617 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25619 if (LHS.getOpcode() != ISD::UNDEF)
25621 for (unsigned i = 0; i != NumElts; ++i)
25625 // Likewise, view RHS in the form
25626 // RHS = VECTOR_SHUFFLE C, D, RMask
25628 SmallVector<int, 16> RMask(NumElts);
25629 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25630 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25631 C = RHS.getOperand(0);
25632 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25633 D = RHS.getOperand(1);
25634 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25635 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25637 if (RHS.getOpcode() != ISD::UNDEF)
25639 for (unsigned i = 0; i != NumElts; ++i)
25643 // Check that the shuffles are both shuffling the same vectors.
25644 if (!(A == C && B == D) && !(A == D && B == C))
25647 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25648 if (!A.getNode() && !B.getNode())
25651 // If A and B occur in reverse order in RHS, then "swap" them (which means
25652 // rewriting the mask).
25654 ShuffleVectorSDNode::commuteMask(RMask);
25656 // At this point LHS and RHS are equivalent to
25657 // LHS = VECTOR_SHUFFLE A, B, LMask
25658 // RHS = VECTOR_SHUFFLE A, B, RMask
25659 // Check that the masks correspond to performing a horizontal operation.
25660 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25661 for (unsigned i = 0; i != NumLaneElts; ++i) {
25662 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25664 // Ignore any UNDEF components.
25665 if (LIdx < 0 || RIdx < 0 ||
25666 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25667 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25670 // Check that successive elements are being operated on. If not, this is
25671 // not a horizontal operation.
25672 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25673 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25674 if (!(LIdx == Index && RIdx == Index + 1) &&
25675 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25680 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25681 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25685 /// Do target-specific dag combines on floating point adds.
25686 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25687 const X86Subtarget *Subtarget) {
25688 EVT VT = N->getValueType(0);
25689 SDValue LHS = N->getOperand(0);
25690 SDValue RHS = N->getOperand(1);
25692 // Try to synthesize horizontal adds from adds of shuffles.
25693 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25694 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25695 isHorizontalBinOp(LHS, RHS, true))
25696 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25700 /// Do target-specific dag combines on floating point subs.
25701 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25702 const X86Subtarget *Subtarget) {
25703 EVT VT = N->getValueType(0);
25704 SDValue LHS = N->getOperand(0);
25705 SDValue RHS = N->getOperand(1);
25707 // Try to synthesize horizontal subs from subs of shuffles.
25708 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25709 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25710 isHorizontalBinOp(LHS, RHS, false))
25711 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25715 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25716 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
25717 const X86Subtarget *Subtarget) {
25718 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25720 // F[X]OR(0.0, x) -> x
25721 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25722 if (C->getValueAPF().isPosZero())
25723 return N->getOperand(1);
25725 // F[X]OR(x, 0.0) -> x
25726 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25727 if (C->getValueAPF().isPosZero())
25728 return N->getOperand(0);
25730 EVT VT = N->getValueType(0);
25731 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
25733 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
25734 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
25736 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
25737 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
25738 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
25739 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
25740 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
25745 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25746 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25747 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25749 // Only perform optimizations if UnsafeMath is used.
25750 if (!DAG.getTarget().Options.UnsafeFPMath)
25753 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25754 // into FMINC and FMAXC, which are Commutative operations.
25755 unsigned NewOp = 0;
25756 switch (N->getOpcode()) {
25757 default: llvm_unreachable("unknown opcode");
25758 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25759 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25762 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25763 N->getOperand(0), N->getOperand(1));
25766 /// Do target-specific dag combines on X86ISD::FAND nodes.
25767 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25768 // FAND(0.0, x) -> 0.0
25769 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25770 if (C->getValueAPF().isPosZero())
25771 return N->getOperand(0);
25773 // FAND(x, 0.0) -> 0.0
25774 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25775 if (C->getValueAPF().isPosZero())
25776 return N->getOperand(1);
25781 /// Do target-specific dag combines on X86ISD::FANDN nodes
25782 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25783 // FANDN(0.0, x) -> x
25784 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25785 if (C->getValueAPF().isPosZero())
25786 return N->getOperand(1);
25788 // FANDN(x, 0.0) -> 0.0
25789 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25790 if (C->getValueAPF().isPosZero())
25791 return N->getOperand(1);
25796 static SDValue PerformBTCombine(SDNode *N,
25798 TargetLowering::DAGCombinerInfo &DCI) {
25799 // BT ignores high bits in the bit index operand.
25800 SDValue Op1 = N->getOperand(1);
25801 if (Op1.hasOneUse()) {
25802 unsigned BitWidth = Op1.getValueSizeInBits();
25803 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25804 APInt KnownZero, KnownOne;
25805 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25806 !DCI.isBeforeLegalizeOps());
25807 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25808 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25809 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25810 DCI.CommitTargetLoweringOpt(TLO);
25815 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25816 SDValue Op = N->getOperand(0);
25817 if (Op.getOpcode() == ISD::BITCAST)
25818 Op = Op.getOperand(0);
25819 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25820 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25821 VT.getVectorElementType().getSizeInBits() ==
25822 OpVT.getVectorElementType().getSizeInBits()) {
25823 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25828 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25829 const X86Subtarget *Subtarget) {
25830 EVT VT = N->getValueType(0);
25831 if (!VT.isVector())
25834 SDValue N0 = N->getOperand(0);
25835 SDValue N1 = N->getOperand(1);
25836 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25839 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25840 // both SSE and AVX2 since there is no sign-extended shift right
25841 // operation on a vector with 64-bit elements.
25842 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25843 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25844 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25845 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25846 SDValue N00 = N0.getOperand(0);
25848 // EXTLOAD has a better solution on AVX2,
25849 // it may be replaced with X86ISD::VSEXT node.
25850 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25851 if (!ISD::isNormalLoad(N00.getNode()))
25854 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25855 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25857 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25863 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
25864 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
25865 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
25866 /// eliminate extend, add, and shift instructions.
25867 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
25868 const X86Subtarget *Subtarget) {
25869 // TODO: This should be valid for other integer types.
25870 EVT VT = Sext->getValueType(0);
25871 if (VT != MVT::i64)
25874 // We need an 'add nsw' feeding into the 'sext'.
25875 SDValue Add = Sext->getOperand(0);
25876 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
25879 // Having a constant operand to the 'add' ensures that we are not increasing
25880 // the instruction count because the constant is extended for free below.
25881 // A constant operand can also become the displacement field of an LEA.
25882 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
25886 // Don't make the 'add' bigger if there's no hope of combining it with some
25887 // other 'add' or 'shl' instruction.
25888 // TODO: It may be profitable to generate simpler LEA instructions in place
25889 // of single 'add' instructions, but the cost model for selecting an LEA
25890 // currently has a high threshold.
25891 bool HasLEAPotential = false;
25892 for (auto *User : Sext->uses()) {
25893 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
25894 HasLEAPotential = true;
25898 if (!HasLEAPotential)
25901 // Everything looks good, so pull the 'sext' ahead of the 'add'.
25902 int64_t AddConstant = AddOp1->getSExtValue();
25903 SDValue AddOp0 = Add.getOperand(0);
25904 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
25905 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
25907 // The wider add is guaranteed to not wrap because both operands are
25910 Flags.setNoSignedWrap(true);
25911 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
25914 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25915 TargetLowering::DAGCombinerInfo &DCI,
25916 const X86Subtarget *Subtarget) {
25917 SDValue N0 = N->getOperand(0);
25918 EVT VT = N->getValueType(0);
25919 EVT SVT = VT.getScalarType();
25920 EVT InVT = N0.getValueType();
25921 EVT InSVT = InVT.getScalarType();
25924 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25925 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25926 // This exposes the sext to the sdivrem lowering, so that it directly extends
25927 // from AH (which we otherwise need to do contortions to access).
25928 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25929 InVT == MVT::i8 && VT == MVT::i32) {
25930 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25931 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
25932 N0.getOperand(0), N0.getOperand(1));
25933 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25934 return R.getValue(1);
25937 if (!DCI.isBeforeLegalizeOps()) {
25938 if (InVT == MVT::i1) {
25939 SDValue Zero = DAG.getConstant(0, DL, VT);
25941 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
25942 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
25947 if (VT.isVector() && Subtarget->hasSSE2()) {
25948 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
25949 EVT InVT = N.getValueType();
25950 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
25951 Size / InVT.getScalarSizeInBits());
25952 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
25953 DAG.getUNDEF(InVT));
25955 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
25958 // If target-size is less than 128-bits, extend to a type that would extend
25959 // to 128 bits, extend that and extract the original target vector.
25960 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
25961 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25962 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25963 unsigned Scale = 128 / VT.getSizeInBits();
25965 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
25966 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
25967 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
25968 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
25969 DAG.getIntPtrConstant(0, DL));
25972 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
25973 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
25974 if (VT.getSizeInBits() == 128 &&
25975 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25976 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25977 SDValue ExOp = ExtendVecSize(DL, N0, 128);
25978 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
25981 // On pre-AVX2 targets, split into 128-bit nodes of
25982 // ISD::SIGN_EXTEND_VECTOR_INREG.
25983 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
25984 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25985 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25986 unsigned NumVecs = VT.getSizeInBits() / 128;
25987 unsigned NumSubElts = 128 / SVT.getSizeInBits();
25988 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
25989 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
25991 SmallVector<SDValue, 8> Opnds;
25992 for (unsigned i = 0, Offset = 0; i != NumVecs;
25993 ++i, Offset += NumSubElts) {
25994 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
25995 DAG.getIntPtrConstant(Offset, DL));
25996 SrcVec = ExtendVecSize(DL, SrcVec, 128);
25997 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
25998 Opnds.push_back(SrcVec);
26000 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
26004 if (Subtarget->hasAVX() && VT.is256BitVector())
26005 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26008 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
26014 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
26015 const X86Subtarget* Subtarget) {
26017 EVT VT = N->getValueType(0);
26019 // Let legalize expand this if it isn't a legal type yet.
26020 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26023 EVT ScalarVT = VT.getScalarType();
26024 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
26025 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
26026 !Subtarget->hasAVX512()))
26029 SDValue A = N->getOperand(0);
26030 SDValue B = N->getOperand(1);
26031 SDValue C = N->getOperand(2);
26033 bool NegA = (A.getOpcode() == ISD::FNEG);
26034 bool NegB = (B.getOpcode() == ISD::FNEG);
26035 bool NegC = (C.getOpcode() == ISD::FNEG);
26037 // Negative multiplication when NegA xor NegB
26038 bool NegMul = (NegA != NegB);
26040 A = A.getOperand(0);
26042 B = B.getOperand(0);
26044 C = C.getOperand(0);
26048 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
26050 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
26052 return DAG.getNode(Opcode, dl, VT, A, B, C);
26055 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
26056 TargetLowering::DAGCombinerInfo &DCI,
26057 const X86Subtarget *Subtarget) {
26058 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
26059 // (and (i32 x86isd::setcc_carry), 1)
26060 // This eliminates the zext. This transformation is necessary because
26061 // ISD::SETCC is always legalized to i8.
26063 SDValue N0 = N->getOperand(0);
26064 EVT VT = N->getValueType(0);
26066 if (N0.getOpcode() == ISD::AND &&
26068 N0.getOperand(0).hasOneUse()) {
26069 SDValue N00 = N0.getOperand(0);
26070 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26071 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
26072 if (!C || C->getZExtValue() != 1)
26074 return DAG.getNode(ISD::AND, dl, VT,
26075 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26076 N00.getOperand(0), N00.getOperand(1)),
26077 DAG.getConstant(1, dl, VT));
26081 if (N0.getOpcode() == ISD::TRUNCATE &&
26083 N0.getOperand(0).hasOneUse()) {
26084 SDValue N00 = N0.getOperand(0);
26085 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26086 return DAG.getNode(ISD::AND, dl, VT,
26087 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26088 N00.getOperand(0), N00.getOperand(1)),
26089 DAG.getConstant(1, dl, VT));
26093 if (VT.is256BitVector())
26094 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26097 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
26098 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
26099 // This exposes the zext to the udivrem lowering, so that it directly extends
26100 // from AH (which we otherwise need to do contortions to access).
26101 if (N0.getOpcode() == ISD::UDIVREM &&
26102 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
26103 (VT == MVT::i32 || VT == MVT::i64)) {
26104 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26105 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
26106 N0.getOperand(0), N0.getOperand(1));
26107 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26108 return R.getValue(1);
26114 // Optimize x == -y --> x+y == 0
26115 // x != -y --> x+y != 0
26116 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
26117 const X86Subtarget* Subtarget) {
26118 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
26119 SDValue LHS = N->getOperand(0);
26120 SDValue RHS = N->getOperand(1);
26121 EVT VT = N->getValueType(0);
26124 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
26125 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
26126 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
26127 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
26128 LHS.getOperand(1));
26129 return DAG.getSetCC(DL, N->getValueType(0), addV,
26130 DAG.getConstant(0, DL, addV.getValueType()), CC);
26132 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
26133 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
26134 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
26135 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
26136 RHS.getOperand(1));
26137 return DAG.getSetCC(DL, N->getValueType(0), addV,
26138 DAG.getConstant(0, DL, addV.getValueType()), CC);
26141 if (VT.getScalarType() == MVT::i1 &&
26142 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
26144 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26145 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26146 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26148 if (!IsSEXT0 || !IsVZero1) {
26149 // Swap the operands and update the condition code.
26150 std::swap(LHS, RHS);
26151 CC = ISD::getSetCCSwappedOperands(CC);
26153 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26154 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26155 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26158 if (IsSEXT0 && IsVZero1) {
26159 assert(VT == LHS.getOperand(0).getValueType() &&
26160 "Uexpected operand type");
26161 if (CC == ISD::SETGT)
26162 return DAG.getConstant(0, DL, VT);
26163 if (CC == ISD::SETLE)
26164 return DAG.getConstant(1, DL, VT);
26165 if (CC == ISD::SETEQ || CC == ISD::SETGE)
26166 return DAG.getNOT(DL, LHS.getOperand(0), VT);
26168 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
26169 "Unexpected condition code!");
26170 return LHS.getOperand(0);
26177 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
26178 SelectionDAG &DAG) {
26180 MVT VT = Load->getSimpleValueType(0);
26181 MVT EVT = VT.getVectorElementType();
26182 SDValue Addr = Load->getOperand(1);
26183 SDValue NewAddr = DAG.getNode(
26184 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
26185 DAG.getConstant(Index * EVT.getStoreSize(), dl,
26186 Addr.getSimpleValueType()));
26189 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
26190 DAG.getMachineFunction().getMachineMemOperand(
26191 Load->getMemOperand(), 0, EVT.getStoreSize()));
26195 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
26196 const X86Subtarget *Subtarget) {
26198 MVT VT = N->getOperand(1)->getSimpleValueType(0);
26199 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
26200 "X86insertps is only defined for v4x32");
26202 SDValue Ld = N->getOperand(1);
26203 if (MayFoldLoad(Ld)) {
26204 // Extract the countS bits from the immediate so we can get the proper
26205 // address when narrowing the vector load to a specific element.
26206 // When the second source op is a memory address, insertps doesn't use
26207 // countS and just gets an f32 from that address.
26208 unsigned DestIndex =
26209 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
26211 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
26213 // Create this as a scalar to vector to match the instruction pattern.
26214 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
26215 // countS bits are ignored when loading from memory on insertps, which
26216 // means we don't need to explicitly set them to 0.
26217 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
26218 LoadScalarToVector, N->getOperand(2));
26223 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
26224 SDValue V0 = N->getOperand(0);
26225 SDValue V1 = N->getOperand(1);
26227 EVT VT = N->getValueType(0);
26229 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
26230 // operands and changing the mask to 1. This saves us a bunch of
26231 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
26232 // x86InstrInfo knows how to commute this back after instruction selection
26233 // if it would help register allocation.
26235 // TODO: If optimizing for size or a processor that doesn't suffer from
26236 // partial register update stalls, this should be transformed into a MOVSD
26237 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
26239 if (VT == MVT::v2f64)
26240 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
26241 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
26242 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
26243 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
26249 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
26250 // as "sbb reg,reg", since it can be extended without zext and produces
26251 // an all-ones bit which is more useful than 0/1 in some cases.
26252 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
26255 return DAG.getNode(ISD::AND, DL, VT,
26256 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26257 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26259 DAG.getConstant(1, DL, VT));
26260 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
26261 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
26262 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26263 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26267 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
26268 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
26269 TargetLowering::DAGCombinerInfo &DCI,
26270 const X86Subtarget *Subtarget) {
26272 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
26273 SDValue EFLAGS = N->getOperand(1);
26275 if (CC == X86::COND_A) {
26276 // Try to convert COND_A into COND_B in an attempt to facilitate
26277 // materializing "setb reg".
26279 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
26280 // cannot take an immediate as its first operand.
26282 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
26283 EFLAGS.getValueType().isInteger() &&
26284 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
26285 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
26286 EFLAGS.getNode()->getVTList(),
26287 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
26288 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
26289 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
26293 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
26294 // a zext and produces an all-ones bit which is more useful than 0/1 in some
26296 if (CC == X86::COND_B)
26297 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
26299 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26300 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26301 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26307 // Optimize branch condition evaluation.
26309 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26310 TargetLowering::DAGCombinerInfo &DCI,
26311 const X86Subtarget *Subtarget) {
26313 SDValue Chain = N->getOperand(0);
26314 SDValue Dest = N->getOperand(1);
26315 SDValue EFLAGS = N->getOperand(3);
26316 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26318 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26319 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26320 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26327 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26328 SelectionDAG &DAG) {
26329 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26330 // optimize away operation when it's from a constant.
26332 // The general transformation is:
26333 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26334 // AND(VECTOR_CMP(x,y), constant2)
26335 // constant2 = UNARYOP(constant)
26337 // Early exit if this isn't a vector operation, the operand of the
26338 // unary operation isn't a bitwise AND, or if the sizes of the operations
26339 // aren't the same.
26340 EVT VT = N->getValueType(0);
26341 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26342 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26343 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26346 // Now check that the other operand of the AND is a constant. We could
26347 // make the transformation for non-constant splats as well, but it's unclear
26348 // that would be a benefit as it would not eliminate any operations, just
26349 // perform one more step in scalar code before moving to the vector unit.
26350 if (BuildVectorSDNode *BV =
26351 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26352 // Bail out if the vector isn't a constant.
26353 if (!BV->isConstant())
26356 // Everything checks out. Build up the new and improved node.
26358 EVT IntVT = BV->getValueType(0);
26359 // Create a new constant of the appropriate type for the transformed
26361 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26362 // The AND node needs bitcasts to/from an integer vector type around it.
26363 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26364 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26365 N->getOperand(0)->getOperand(0), MaskConst);
26366 SDValue Res = DAG.getBitcast(VT, NewAnd);
26373 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26374 const X86Subtarget *Subtarget) {
26375 SDValue Op0 = N->getOperand(0);
26376 EVT VT = N->getValueType(0);
26377 EVT InVT = Op0.getValueType();
26378 EVT InSVT = InVT.getScalarType();
26379 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26381 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26382 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26383 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26385 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26386 InVT.getVectorNumElements());
26387 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26389 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26390 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26392 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26398 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26399 const X86Subtarget *Subtarget) {
26400 // First try to optimize away the conversion entirely when it's
26401 // conditionally from a constant. Vectors only.
26402 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26405 // Now move on to more general possibilities.
26406 SDValue Op0 = N->getOperand(0);
26407 EVT VT = N->getValueType(0);
26408 EVT InVT = Op0.getValueType();
26409 EVT InSVT = InVT.getScalarType();
26411 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26412 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26413 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26415 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26416 InVT.getVectorNumElements());
26417 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26418 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26421 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26422 // a 32-bit target where SSE doesn't support i64->FP operations.
26423 if (Op0.getOpcode() == ISD::LOAD) {
26424 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26425 EVT LdVT = Ld->getValueType(0);
26427 // This transformation is not supported if the result type is f16
26428 if (VT == MVT::f16)
26431 if (!Ld->isVolatile() && !VT.isVector() &&
26432 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26433 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26434 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26435 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26436 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26443 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26444 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26445 X86TargetLowering::DAGCombinerInfo &DCI) {
26446 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26447 // the result is either zero or one (depending on the input carry bit).
26448 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26449 if (X86::isZeroNode(N->getOperand(0)) &&
26450 X86::isZeroNode(N->getOperand(1)) &&
26451 // We don't have a good way to replace an EFLAGS use, so only do this when
26453 SDValue(N, 1).use_empty()) {
26455 EVT VT = N->getValueType(0);
26456 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26457 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26458 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26459 DAG.getConstant(X86::COND_B, DL,
26462 DAG.getConstant(1, DL, VT));
26463 return DCI.CombineTo(N, Res1, CarryOut);
26469 // fold (add Y, (sete X, 0)) -> adc 0, Y
26470 // (add Y, (setne X, 0)) -> sbb -1, Y
26471 // (sub (sete X, 0), Y) -> sbb 0, Y
26472 // (sub (setne X, 0), Y) -> adc -1, Y
26473 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26476 // Look through ZExts.
26477 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26478 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26481 SDValue SetCC = Ext.getOperand(0);
26482 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26485 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26486 if (CC != X86::COND_E && CC != X86::COND_NE)
26489 SDValue Cmp = SetCC.getOperand(1);
26490 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26491 !X86::isZeroNode(Cmp.getOperand(1)) ||
26492 !Cmp.getOperand(0).getValueType().isInteger())
26495 SDValue CmpOp0 = Cmp.getOperand(0);
26496 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26497 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26499 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26500 if (CC == X86::COND_NE)
26501 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26502 DL, OtherVal.getValueType(), OtherVal,
26503 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26505 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26506 DL, OtherVal.getValueType(), OtherVal,
26507 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26510 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26511 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26512 const X86Subtarget *Subtarget) {
26513 EVT VT = N->getValueType(0);
26514 SDValue Op0 = N->getOperand(0);
26515 SDValue Op1 = N->getOperand(1);
26517 // Try to synthesize horizontal adds from adds of shuffles.
26518 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26519 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26520 isHorizontalBinOp(Op0, Op1, true))
26521 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26523 return OptimizeConditionalInDecrement(N, DAG);
26526 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26527 const X86Subtarget *Subtarget) {
26528 SDValue Op0 = N->getOperand(0);
26529 SDValue Op1 = N->getOperand(1);
26531 // X86 can't encode an immediate LHS of a sub. See if we can push the
26532 // negation into a preceding instruction.
26533 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26534 // If the RHS of the sub is a XOR with one use and a constant, invert the
26535 // immediate. Then add one to the LHS of the sub so we can turn
26536 // X-Y -> X+~Y+1, saving one register.
26537 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26538 isa<ConstantSDNode>(Op1.getOperand(1))) {
26539 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26540 EVT VT = Op0.getValueType();
26541 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26543 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26544 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26545 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26549 // Try to synthesize horizontal adds from adds of shuffles.
26550 EVT VT = N->getValueType(0);
26551 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26552 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26553 isHorizontalBinOp(Op0, Op1, true))
26554 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26556 return OptimizeConditionalInDecrement(N, DAG);
26559 /// performVZEXTCombine - Performs build vector combines
26560 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26561 TargetLowering::DAGCombinerInfo &DCI,
26562 const X86Subtarget *Subtarget) {
26564 MVT VT = N->getSimpleValueType(0);
26565 SDValue Op = N->getOperand(0);
26566 MVT OpVT = Op.getSimpleValueType();
26567 MVT OpEltVT = OpVT.getVectorElementType();
26568 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26570 // (vzext (bitcast (vzext (x)) -> (vzext x)
26572 while (V.getOpcode() == ISD::BITCAST)
26573 V = V.getOperand(0);
26575 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26576 MVT InnerVT = V.getSimpleValueType();
26577 MVT InnerEltVT = InnerVT.getVectorElementType();
26579 // If the element sizes match exactly, we can just do one larger vzext. This
26580 // is always an exact type match as vzext operates on integer types.
26581 if (OpEltVT == InnerEltVT) {
26582 assert(OpVT == InnerVT && "Types must match for vzext!");
26583 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
26586 // The only other way we can combine them is if only a single element of the
26587 // inner vzext is used in the input to the outer vzext.
26588 if (InnerEltVT.getSizeInBits() < InputBits)
26591 // In this case, the inner vzext is completely dead because we're going to
26592 // only look at bits inside of the low element. Just do the outer vzext on
26593 // a bitcast of the input to the inner.
26594 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
26597 // Check if we can bypass extracting and re-inserting an element of an input
26598 // vector. Essentially:
26599 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
26600 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
26601 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
26602 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
26603 SDValue ExtractedV = V.getOperand(0);
26604 SDValue OrigV = ExtractedV.getOperand(0);
26605 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
26606 if (ExtractIdx->getZExtValue() == 0) {
26607 MVT OrigVT = OrigV.getSimpleValueType();
26608 // Extract a subvector if necessary...
26609 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
26610 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
26611 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
26612 OrigVT.getVectorNumElements() / Ratio);
26613 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
26614 DAG.getIntPtrConstant(0, DL));
26616 Op = DAG.getBitcast(OpVT, OrigV);
26617 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
26624 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
26625 DAGCombinerInfo &DCI) const {
26626 SelectionDAG &DAG = DCI.DAG;
26627 switch (N->getOpcode()) {
26629 case ISD::EXTRACT_VECTOR_ELT:
26630 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
26633 case X86ISD::SHRUNKBLEND:
26634 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
26635 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG, Subtarget);
26636 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
26637 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
26638 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
26639 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
26640 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26643 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26644 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26645 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26646 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26647 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26648 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26649 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26650 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26651 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26652 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26653 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26654 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26656 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
26658 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26659 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26660 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26661 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26662 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26663 case ISD::ANY_EXTEND:
26664 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26665 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26666 case ISD::SIGN_EXTEND_INREG:
26667 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26668 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26669 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26670 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26671 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26672 case X86ISD::SHUFP: // Handle all target specific shuffles
26673 case X86ISD::PALIGNR:
26674 case X86ISD::UNPCKH:
26675 case X86ISD::UNPCKL:
26676 case X86ISD::MOVHLPS:
26677 case X86ISD::MOVLHPS:
26678 case X86ISD::PSHUFB:
26679 case X86ISD::PSHUFD:
26680 case X86ISD::PSHUFHW:
26681 case X86ISD::PSHUFLW:
26682 case X86ISD::MOVSS:
26683 case X86ISD::MOVSD:
26684 case X86ISD::VPERMILPI:
26685 case X86ISD::VPERM2X128:
26686 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26687 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26688 case X86ISD::INSERTPS: {
26689 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
26690 return PerformINSERTPSCombine(N, DAG, Subtarget);
26693 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26699 /// isTypeDesirableForOp - Return true if the target has native support for
26700 /// the specified value type and it is 'desirable' to use the type for the
26701 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26702 /// instruction encodings are longer and some i16 instructions are slow.
26703 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26704 if (!isTypeLegal(VT))
26706 if (VT != MVT::i16)
26713 case ISD::SIGN_EXTEND:
26714 case ISD::ZERO_EXTEND:
26715 case ISD::ANY_EXTEND:
26728 /// IsDesirableToPromoteOp - This method query the target whether it is
26729 /// beneficial for dag combiner to promote the specified node. If true, it
26730 /// should return the desired promotion type by reference.
26731 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26732 EVT VT = Op.getValueType();
26733 if (VT != MVT::i16)
26736 bool Promote = false;
26737 bool Commute = false;
26738 switch (Op.getOpcode()) {
26741 LoadSDNode *LD = cast<LoadSDNode>(Op);
26742 // If the non-extending load has a single use and it's not live out, then it
26743 // might be folded.
26744 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26745 Op.hasOneUse()*/) {
26746 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26747 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26748 // The only case where we'd want to promote LOAD (rather then it being
26749 // promoted as an operand is when it's only use is liveout.
26750 if (UI->getOpcode() != ISD::CopyToReg)
26757 case ISD::SIGN_EXTEND:
26758 case ISD::ZERO_EXTEND:
26759 case ISD::ANY_EXTEND:
26764 SDValue N0 = Op.getOperand(0);
26765 // Look out for (store (shl (load), x)).
26766 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26779 SDValue N0 = Op.getOperand(0);
26780 SDValue N1 = Op.getOperand(1);
26781 if (!Commute && MayFoldLoad(N1))
26783 // Avoid disabling potential load folding opportunities.
26784 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26786 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26796 //===----------------------------------------------------------------------===//
26797 // X86 Inline Assembly Support
26798 //===----------------------------------------------------------------------===//
26800 // Helper to match a string separated by whitespace.
26801 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
26802 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
26804 for (StringRef Piece : Pieces) {
26805 if (!S.startswith(Piece)) // Check if the piece matches.
26808 S = S.substr(Piece.size());
26809 StringRef::size_type Pos = S.find_first_not_of(" \t");
26810 if (Pos == 0) // We matched a prefix.
26819 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26821 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26822 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26823 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26824 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26826 if (AsmPieces.size() == 3)
26828 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26835 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26836 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26838 std::string AsmStr = IA->getAsmString();
26840 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26841 if (!Ty || Ty->getBitWidth() % 16 != 0)
26844 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26845 SmallVector<StringRef, 4> AsmPieces;
26846 SplitString(AsmStr, AsmPieces, ";\n");
26848 switch (AsmPieces.size()) {
26849 default: return false;
26851 // FIXME: this should verify that we are targeting a 486 or better. If not,
26852 // we will turn this bswap into something that will be lowered to logical
26853 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26854 // lower so don't worry about this.
26856 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
26857 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
26858 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
26859 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
26860 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
26861 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
26862 // No need to check constraints, nothing other than the equivalent of
26863 // "=r,0" would be valid here.
26864 return IntrinsicLowering::LowerToByteSwap(CI);
26867 // rorw $$8, ${0:w} --> llvm.bswap.i16
26868 if (CI->getType()->isIntegerTy(16) &&
26869 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26870 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
26871 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
26873 StringRef ConstraintsStr = IA->getConstraintString();
26874 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26875 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26876 if (clobbersFlagRegisters(AsmPieces))
26877 return IntrinsicLowering::LowerToByteSwap(CI);
26881 if (CI->getType()->isIntegerTy(32) &&
26882 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26883 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
26884 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
26885 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
26887 StringRef ConstraintsStr = IA->getConstraintString();
26888 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26889 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26890 if (clobbersFlagRegisters(AsmPieces))
26891 return IntrinsicLowering::LowerToByteSwap(CI);
26894 if (CI->getType()->isIntegerTy(64)) {
26895 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26896 if (Constraints.size() >= 2 &&
26897 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26898 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26899 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26900 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
26901 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
26902 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
26903 return IntrinsicLowering::LowerToByteSwap(CI);
26911 /// getConstraintType - Given a constraint letter, return the type of
26912 /// constraint it is for this target.
26913 X86TargetLowering::ConstraintType
26914 X86TargetLowering::getConstraintType(StringRef Constraint) const {
26915 if (Constraint.size() == 1) {
26916 switch (Constraint[0]) {
26927 return C_RegisterClass;
26951 return TargetLowering::getConstraintType(Constraint);
26954 /// Examine constraint type and operand type and determine a weight value.
26955 /// This object must already have been set up with the operand type
26956 /// and the current alternative constraint selected.
26957 TargetLowering::ConstraintWeight
26958 X86TargetLowering::getSingleConstraintMatchWeight(
26959 AsmOperandInfo &info, const char *constraint) const {
26960 ConstraintWeight weight = CW_Invalid;
26961 Value *CallOperandVal = info.CallOperandVal;
26962 // If we don't have a value, we can't do a match,
26963 // but allow it at the lowest weight.
26964 if (!CallOperandVal)
26966 Type *type = CallOperandVal->getType();
26967 // Look at the constraint type.
26968 switch (*constraint) {
26970 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26981 if (CallOperandVal->getType()->isIntegerTy())
26982 weight = CW_SpecificReg;
26987 if (type->isFloatingPointTy())
26988 weight = CW_SpecificReg;
26991 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26992 weight = CW_SpecificReg;
26996 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26997 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26998 weight = CW_Register;
27001 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
27002 if (C->getZExtValue() <= 31)
27003 weight = CW_Constant;
27007 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27008 if (C->getZExtValue() <= 63)
27009 weight = CW_Constant;
27013 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27014 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
27015 weight = CW_Constant;
27019 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27020 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
27021 weight = CW_Constant;
27025 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27026 if (C->getZExtValue() <= 3)
27027 weight = CW_Constant;
27031 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27032 if (C->getZExtValue() <= 0xff)
27033 weight = CW_Constant;
27038 if (isa<ConstantFP>(CallOperandVal)) {
27039 weight = CW_Constant;
27043 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27044 if ((C->getSExtValue() >= -0x80000000LL) &&
27045 (C->getSExtValue() <= 0x7fffffffLL))
27046 weight = CW_Constant;
27050 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27051 if (C->getZExtValue() <= 0xffffffff)
27052 weight = CW_Constant;
27059 /// LowerXConstraint - try to replace an X constraint, which matches anything,
27060 /// with another that has more specific requirements based on the type of the
27061 /// corresponding operand.
27062 const char *X86TargetLowering::
27063 LowerXConstraint(EVT ConstraintVT) const {
27064 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
27065 // 'f' like normal targets.
27066 if (ConstraintVT.isFloatingPoint()) {
27067 if (Subtarget->hasSSE2())
27069 if (Subtarget->hasSSE1())
27073 return TargetLowering::LowerXConstraint(ConstraintVT);
27076 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
27077 /// vector. If it is invalid, don't add anything to Ops.
27078 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
27079 std::string &Constraint,
27080 std::vector<SDValue>&Ops,
27081 SelectionDAG &DAG) const {
27084 // Only support length 1 constraints for now.
27085 if (Constraint.length() > 1) return;
27087 char ConstraintLetter = Constraint[0];
27088 switch (ConstraintLetter) {
27091 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27092 if (C->getZExtValue() <= 31) {
27093 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27094 Op.getValueType());
27100 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27101 if (C->getZExtValue() <= 63) {
27102 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27103 Op.getValueType());
27109 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27110 if (isInt<8>(C->getSExtValue())) {
27111 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27112 Op.getValueType());
27118 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27119 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
27120 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
27121 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
27122 Op.getValueType());
27128 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27129 if (C->getZExtValue() <= 3) {
27130 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27131 Op.getValueType());
27137 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27138 if (C->getZExtValue() <= 255) {
27139 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27140 Op.getValueType());
27146 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27147 if (C->getZExtValue() <= 127) {
27148 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27149 Op.getValueType());
27155 // 32-bit signed value
27156 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27157 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27158 C->getSExtValue())) {
27159 // Widen to 64 bits here to get it sign extended.
27160 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
27163 // FIXME gcc accepts some relocatable values here too, but only in certain
27164 // memory models; it's complicated.
27169 // 32-bit unsigned value
27170 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27171 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27172 C->getZExtValue())) {
27173 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27174 Op.getValueType());
27178 // FIXME gcc accepts some relocatable values here too, but only in certain
27179 // memory models; it's complicated.
27183 // Literal immediates are always ok.
27184 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
27185 // Widen to 64 bits here to get it sign extended.
27186 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
27190 // In any sort of PIC mode addresses need to be computed at runtime by
27191 // adding in a register or some sort of table lookup. These can't
27192 // be used as immediates.
27193 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
27196 // If we are in non-pic codegen mode, we allow the address of a global (with
27197 // an optional displacement) to be used with 'i'.
27198 GlobalAddressSDNode *GA = nullptr;
27199 int64_t Offset = 0;
27201 // Match either (GA), (GA+C), (GA+C1+C2), etc.
27203 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
27204 Offset += GA->getOffset();
27206 } else if (Op.getOpcode() == ISD::ADD) {
27207 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27208 Offset += C->getZExtValue();
27209 Op = Op.getOperand(0);
27212 } else if (Op.getOpcode() == ISD::SUB) {
27213 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27214 Offset += -C->getZExtValue();
27215 Op = Op.getOperand(0);
27220 // Otherwise, this isn't something we can handle, reject it.
27224 const GlobalValue *GV = GA->getGlobal();
27225 // If we require an extra load to get this address, as in PIC mode, we
27226 // can't accept it.
27227 if (isGlobalStubReference(
27228 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
27231 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
27232 GA->getValueType(0), Offset);
27237 if (Result.getNode()) {
27238 Ops.push_back(Result);
27241 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
27244 std::pair<unsigned, const TargetRegisterClass *>
27245 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
27246 StringRef Constraint,
27248 // First, see if this is a constraint that directly corresponds to an LLVM
27250 if (Constraint.size() == 1) {
27251 // GCC Constraint Letters
27252 switch (Constraint[0]) {
27254 // TODO: Slight differences here in allocation order and leaving
27255 // RIP in the class. Do they matter any more here than they do
27256 // in the normal allocation?
27257 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
27258 if (Subtarget->is64Bit()) {
27259 if (VT == MVT::i32 || VT == MVT::f32)
27260 return std::make_pair(0U, &X86::GR32RegClass);
27261 if (VT == MVT::i16)
27262 return std::make_pair(0U, &X86::GR16RegClass);
27263 if (VT == MVT::i8 || VT == MVT::i1)
27264 return std::make_pair(0U, &X86::GR8RegClass);
27265 if (VT == MVT::i64 || VT == MVT::f64)
27266 return std::make_pair(0U, &X86::GR64RegClass);
27269 // 32-bit fallthrough
27270 case 'Q': // Q_REGS
27271 if (VT == MVT::i32 || VT == MVT::f32)
27272 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
27273 if (VT == MVT::i16)
27274 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
27275 if (VT == MVT::i8 || VT == MVT::i1)
27276 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
27277 if (VT == MVT::i64)
27278 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
27280 case 'r': // GENERAL_REGS
27281 case 'l': // INDEX_REGS
27282 if (VT == MVT::i8 || VT == MVT::i1)
27283 return std::make_pair(0U, &X86::GR8RegClass);
27284 if (VT == MVT::i16)
27285 return std::make_pair(0U, &X86::GR16RegClass);
27286 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
27287 return std::make_pair(0U, &X86::GR32RegClass);
27288 return std::make_pair(0U, &X86::GR64RegClass);
27289 case 'R': // LEGACY_REGS
27290 if (VT == MVT::i8 || VT == MVT::i1)
27291 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
27292 if (VT == MVT::i16)
27293 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
27294 if (VT == MVT::i32 || !Subtarget->is64Bit())
27295 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
27296 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
27297 case 'f': // FP Stack registers.
27298 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
27299 // value to the correct fpstack register class.
27300 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
27301 return std::make_pair(0U, &X86::RFP32RegClass);
27302 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27303 return std::make_pair(0U, &X86::RFP64RegClass);
27304 return std::make_pair(0U, &X86::RFP80RegClass);
27305 case 'y': // MMX_REGS if MMX allowed.
27306 if (!Subtarget->hasMMX()) break;
27307 return std::make_pair(0U, &X86::VR64RegClass);
27308 case 'Y': // SSE_REGS if SSE2 allowed
27309 if (!Subtarget->hasSSE2()) break;
27311 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27312 if (!Subtarget->hasSSE1()) break;
27314 switch (VT.SimpleTy) {
27316 // Scalar SSE types.
27319 return std::make_pair(0U, &X86::FR32RegClass);
27322 return std::make_pair(0U, &X86::FR64RegClass);
27330 return std::make_pair(0U, &X86::VR128RegClass);
27338 return std::make_pair(0U, &X86::VR256RegClass);
27343 return std::make_pair(0U, &X86::VR512RegClass);
27349 // Use the default implementation in TargetLowering to convert the register
27350 // constraint into a member of a register class.
27351 std::pair<unsigned, const TargetRegisterClass*> Res;
27352 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27354 // Not found as a standard register?
27356 // Map st(0) -> st(7) -> ST0
27357 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27358 tolower(Constraint[1]) == 's' &&
27359 tolower(Constraint[2]) == 't' &&
27360 Constraint[3] == '(' &&
27361 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27362 Constraint[5] == ')' &&
27363 Constraint[6] == '}') {
27365 Res.first = X86::FP0+Constraint[4]-'0';
27366 Res.second = &X86::RFP80RegClass;
27370 // GCC allows "st(0)" to be called just plain "st".
27371 if (StringRef("{st}").equals_lower(Constraint)) {
27372 Res.first = X86::FP0;
27373 Res.second = &X86::RFP80RegClass;
27378 if (StringRef("{flags}").equals_lower(Constraint)) {
27379 Res.first = X86::EFLAGS;
27380 Res.second = &X86::CCRRegClass;
27384 // 'A' means EAX + EDX.
27385 if (Constraint == "A") {
27386 Res.first = X86::EAX;
27387 Res.second = &X86::GR32_ADRegClass;
27393 // Otherwise, check to see if this is a register class of the wrong value
27394 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27395 // turn into {ax},{dx}.
27396 // MVT::Other is used to specify clobber names.
27397 if (Res.second->hasType(VT) || VT == MVT::Other)
27398 return Res; // Correct type already, nothing to do.
27400 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27401 // return "eax". This should even work for things like getting 64bit integer
27402 // registers when given an f64 type.
27403 const TargetRegisterClass *Class = Res.second;
27404 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27405 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27406 unsigned Size = VT.getSizeInBits();
27407 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27408 : Size == 16 ? MVT::i16
27409 : Size == 32 ? MVT::i32
27410 : Size == 64 ? MVT::i64
27412 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27414 Res.first = DestReg;
27415 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27416 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27417 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27418 : &X86::GR64RegClass;
27419 assert(Res.second->contains(Res.first) && "Register in register class");
27421 // No register found/type mismatch.
27423 Res.second = nullptr;
27425 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27426 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27427 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27428 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27429 Class == &X86::VR512RegClass) {
27430 // Handle references to XMM physical registers that got mapped into the
27431 // wrong class. This can happen with constraints like {xmm0} where the
27432 // target independent register mapper will just pick the first match it can
27433 // find, ignoring the required type.
27435 if (VT == MVT::f32 || VT == MVT::i32)
27436 Res.second = &X86::FR32RegClass;
27437 else if (VT == MVT::f64 || VT == MVT::i64)
27438 Res.second = &X86::FR64RegClass;
27439 else if (X86::VR128RegClass.hasType(VT))
27440 Res.second = &X86::VR128RegClass;
27441 else if (X86::VR256RegClass.hasType(VT))
27442 Res.second = &X86::VR256RegClass;
27443 else if (X86::VR512RegClass.hasType(VT))
27444 Res.second = &X86::VR512RegClass;
27446 // Type mismatch and not a clobber: Return an error;
27448 Res.second = nullptr;
27455 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27456 const AddrMode &AM, Type *Ty,
27457 unsigned AS) const {
27458 // Scaling factors are not free at all.
27459 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27460 // will take 2 allocations in the out of order engine instead of 1
27461 // for plain addressing mode, i.e. inst (reg1).
27463 // vaddps (%rsi,%drx), %ymm0, %ymm1
27464 // Requires two allocations (one for the load, one for the computation)
27466 // vaddps (%rsi), %ymm0, %ymm1
27467 // Requires just 1 allocation, i.e., freeing allocations for other operations
27468 // and having less micro operations to execute.
27470 // For some X86 architectures, this is even worse because for instance for
27471 // stores, the complex addressing mode forces the instruction to use the
27472 // "load" ports instead of the dedicated "store" port.
27473 // E.g., on Haswell:
27474 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27475 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27476 if (isLegalAddressingMode(DL, AM, Ty, AS))
27477 // Scale represents reg2 * scale, thus account for 1
27478 // as soon as we use a second register.
27479 return AM.Scale != 0;
27483 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27484 // Integer division on x86 is expensive. However, when aggressively optimizing
27485 // for code size, we prefer to use a div instruction, as it is usually smaller
27486 // than the alternative sequence.
27487 // The exception to this is vector division. Since x86 doesn't have vector
27488 // integer division, leaving the division as-is is a loss even in terms of
27489 // size, because it will have to be scalarized, while the alternative code
27490 // sequence can be performed in vector form.
27491 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27492 Attribute::MinSize);
27493 return OptSize && !VT.isVector();
27496 void X86TargetLowering::markInRegArguments(SelectionDAG &DAG,
27497 TargetLowering::ArgListTy& Args) const {
27498 // The MCU psABI requires some arguments to be passed in-register.
27499 // For regular calls, the inreg arguments are marked by the front-end.
27500 // However, for compiler generated library calls, we have to patch this
27502 if (!Subtarget->isTargetMCU() || !Args.size())
27505 unsigned FreeRegs = 3;
27506 for (auto &Arg : Args) {
27507 // For library functions, we do not expect any fancy types.
27508 unsigned Size = DAG.getDataLayout().getTypeSizeInBits(Arg.Ty);
27509 unsigned SizeInRegs = (Size + 31) / 32;
27510 if (SizeInRegs > 2 || SizeInRegs > FreeRegs)
27513 Arg.isInReg = true;
27514 FreeRegs -= SizeInRegs;