1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86ISelLowering.h"
17 #include "X86TargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Support/CommandLine.h"
29 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
30 cl::desc("Enable fastcc on X86"));
32 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
33 : TargetLowering(TM) {
34 // Set up the TargetLowering object.
36 // X86 is weird, it always uses i8 for shift amounts and setcc results.
37 setShiftAmountType(MVT::i8);
38 setSetCCResultType(MVT::i8);
39 setSetCCResultContents(ZeroOrOneSetCCResult);
40 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
42 // Set up the register classes.
43 addRegisterClass(MVT::i8, X86::R8RegisterClass);
44 addRegisterClass(MVT::i16, X86::R16RegisterClass);
45 addRegisterClass(MVT::i32, X86::R32RegisterClass);
47 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
49 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
50 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
51 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
52 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
54 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
56 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
57 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
60 // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64
62 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
63 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
64 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
65 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
68 // Handle FP_TO_UINT by promoting the destination to a larger signed
70 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
71 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
72 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
75 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
77 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
79 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
80 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
81 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
83 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
84 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
87 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
89 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
90 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
91 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
92 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
93 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
94 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
95 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
96 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
97 setOperationAction(ISD::FREM , MVT::f64 , Expand);
98 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
99 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
100 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
101 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
102 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
103 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
104 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
105 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
106 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
107 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
109 setOperationAction(ISD::READIO , MVT::i1 , Expand);
110 setOperationAction(ISD::READIO , MVT::i8 , Expand);
111 setOperationAction(ISD::READIO , MVT::i16 , Expand);
112 setOperationAction(ISD::READIO , MVT::i32 , Expand);
113 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand);
114 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
115 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
116 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
118 // These should be promoted to a larger select which is supported.
119 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
120 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
122 // X86 wants to expand cmov itself.
123 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
124 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
125 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
126 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
127 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
128 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
129 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
130 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
131 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
132 // X86 ret instruction may pop stack.
133 setOperationAction(ISD::RET , MVT::Other, Custom);
135 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
136 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
137 setOperationAction(ISD::ADD_PARTS , MVT::i32 , Custom);
138 setOperationAction(ISD::SUB_PARTS , MVT::i32 , Custom);
139 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
140 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
141 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
144 // We don't have line number support yet.
145 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
146 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
147 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
150 // Set up the FP register classes.
151 addRegisterClass(MVT::f32, X86::V4F4RegisterClass);
152 addRegisterClass(MVT::f64, X86::V2F8RegisterClass);
154 // SSE has no load+extend ops
155 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
156 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
158 // SSE has no i16 to fp conversion, only i32
159 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
160 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
162 // Expand FP_TO_UINT into a select.
163 // FIXME: We would like to use a Custom expander here eventually to do
164 // the optimal thing for SSE vs. the default expansion in the legalizer.
165 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
167 // We don't support sin/cos/sqrt/fmod
168 setOperationAction(ISD::FSIN , MVT::f64, Expand);
169 setOperationAction(ISD::FCOS , MVT::f64, Expand);
170 setOperationAction(ISD::FABS , MVT::f64, Expand);
171 setOperationAction(ISD::FNEG , MVT::f64, Expand);
172 setOperationAction(ISD::FREM , MVT::f64, Expand);
173 setOperationAction(ISD::FSIN , MVT::f32, Expand);
174 setOperationAction(ISD::FCOS , MVT::f32, Expand);
175 setOperationAction(ISD::FABS , MVT::f32, Expand);
176 setOperationAction(ISD::FNEG , MVT::f32, Expand);
177 setOperationAction(ISD::FREM , MVT::f32, Expand);
179 addLegalFPImmediate(+0.0); // xorps / xorpd
181 // Set up the FP register classes.
182 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
185 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
186 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
189 addLegalFPImmediate(+0.0); // FLD0
190 addLegalFPImmediate(+1.0); // FLD1
191 addLegalFPImmediate(-0.0); // FLD0/FCHS
192 addLegalFPImmediate(-1.0); // FLD1/FCHS
194 computeRegisterProperties();
196 maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores
197 maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores
198 maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores
199 allowUnalignedMemoryAccesses = true; // x86 supports it!
202 std::vector<SDOperand>
203 X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
204 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
205 return LowerFastCCArguments(F, DAG);
206 return LowerCCCArguments(F, DAG);
209 std::pair<SDOperand, SDOperand>
210 X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
211 bool isVarArg, unsigned CallingConv,
213 SDOperand Callee, ArgListTy &Args,
215 assert((!isVarArg || CallingConv == CallingConv::C) &&
216 "Only C takes varargs!");
218 // If the callee is a GlobalAddress node (quite common, every direct call is)
219 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
220 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
221 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
223 if (CallingConv == CallingConv::Fast && EnableFastCC)
224 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
225 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
228 SDOperand X86TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
231 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
234 MVT::ValueType OpVT = Op.getValueType();
236 default: assert(0 && "Unknown type to return!");
238 Copy = DAG.getCopyToReg(Chain, X86::EAX, Op, SDOperand());
241 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
242 DAG.getConstant(1, MVT::i32));
243 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
244 DAG.getConstant(0, MVT::i32));
245 Copy = DAG.getCopyToReg(Chain, X86::EDX, Hi, SDOperand());
246 Copy = DAG.getCopyToReg(Copy, X86::EAX, Lo, Copy.getValue(1));
252 if (OpVT == MVT::f32)
253 Op = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op);
254 std::vector<MVT::ValueType> Tys;
255 Tys.push_back(MVT::Other);
256 Tys.push_back(MVT::Flag);
257 std::vector<SDOperand> Ops;
258 Ops.push_back(Chain);
260 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
262 // Spill the value to memory and reload it into top of stack.
263 unsigned Size = MVT::getSizeInBits(OpVT)/8;
264 MachineFunction &MF = DAG.getMachineFunction();
265 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
266 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
267 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Op,
268 StackSlot, DAG.getSrcValue(NULL));
269 std::vector<MVT::ValueType> Tys;
270 Tys.push_back(MVT::f64);
271 Tys.push_back(MVT::Other);
272 std::vector<SDOperand> Ops;
273 Ops.push_back(Chain);
274 Ops.push_back(StackSlot);
275 Ops.push_back(DAG.getValueType(OpVT));
276 Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
278 Tys.push_back(MVT::Other);
279 Tys.push_back(MVT::Flag);
281 Ops.push_back(Copy.getValue(1));
283 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
288 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
289 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
293 //===----------------------------------------------------------------------===//
294 // C Calling Convention implementation
295 //===----------------------------------------------------------------------===//
297 std::vector<SDOperand>
298 X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
299 std::vector<SDOperand> ArgValues;
301 MachineFunction &MF = DAG.getMachineFunction();
302 MachineFrameInfo *MFI = MF.getFrameInfo();
304 // Add DAG nodes to load the arguments... On entry to a function on the X86,
305 // the stack frame looks like this:
307 // [ESP] -- return address
308 // [ESP + 4] -- first argument (leftmost lexically)
309 // [ESP + 8] -- second argument, if first argument is four bytes in size
312 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
313 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
314 MVT::ValueType ObjectVT = getValueType(I->getType());
315 unsigned ArgIncrement = 4;
318 default: assert(0 && "Unhandled argument type!");
320 case MVT::i8: ObjSize = 1; break;
321 case MVT::i16: ObjSize = 2; break;
322 case MVT::i32: ObjSize = 4; break;
323 case MVT::i64: ObjSize = ArgIncrement = 8; break;
324 case MVT::f32: ObjSize = 4; break;
325 case MVT::f64: ObjSize = ArgIncrement = 8; break;
327 // Create the frame index object for this incoming parameter...
328 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
330 // Create the SelectionDAG nodes corresponding to a load from this parameter
331 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
333 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
337 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
338 DAG.getSrcValue(NULL));
340 if (MVT::isInteger(ObjectVT))
341 ArgValue = DAG.getConstant(0, ObjectVT);
343 ArgValue = DAG.getConstantFP(0, ObjectVT);
345 ArgValues.push_back(ArgValue);
347 ArgOffset += ArgIncrement; // Move on to the next argument...
350 // If the function takes variable number of arguments, make a frame index for
351 // the start of the first vararg value... for expansion of llvm.va_start.
353 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
354 ReturnAddrIndex = 0; // No return address slot generated yet.
355 BytesToPopOnReturn = 0; // Callee pops nothing.
356 BytesCallerReserves = ArgOffset;
358 // Finally, inform the code generator which regs we return values in.
359 switch (getValueType(F.getReturnType())) {
360 default: assert(0 && "Unknown type!");
361 case MVT::isVoid: break;
366 MF.addLiveOut(X86::EAX);
369 MF.addLiveOut(X86::EAX);
370 MF.addLiveOut(X86::EDX);
374 MF.addLiveOut(X86::ST0);
380 std::pair<SDOperand, SDOperand>
381 X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
382 bool isVarArg, bool isTailCall,
383 SDOperand Callee, ArgListTy &Args,
385 // Count how many bytes are to be pushed on the stack.
386 unsigned NumBytes = 0;
390 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
391 DAG.getConstant(0, getPointerTy()));
393 for (unsigned i = 0, e = Args.size(); i != e; ++i)
394 switch (getValueType(Args[i].second)) {
395 default: assert(0 && "Unknown value type!");
409 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
410 DAG.getConstant(NumBytes, getPointerTy()));
412 // Arguments go on the stack in reverse order, as specified by the ABI.
413 unsigned ArgOffset = 0;
414 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
416 std::vector<SDOperand> Stores;
418 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
419 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
420 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
422 switch (getValueType(Args[i].second)) {
423 default: assert(0 && "Unexpected ValueType for argument!");
427 // Promote the integer to 32 bits. If the input type is signed use a
428 // sign extend, otherwise use a zero extend.
429 if (Args[i].second->isSigned())
430 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
432 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
437 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
438 Args[i].first, PtrOff,
439 DAG.getSrcValue(NULL)));
444 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
445 Args[i].first, PtrOff,
446 DAG.getSrcValue(NULL)));
451 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
454 std::vector<MVT::ValueType> RetVals;
455 MVT::ValueType RetTyVT = getValueType(RetTy);
456 RetVals.push_back(MVT::Other);
458 // The result values produced have to be legal. Promote the result.
460 case MVT::isVoid: break;
462 RetVals.push_back(RetTyVT);
467 RetVals.push_back(MVT::i32);
471 RetVals.push_back(MVT::f32);
473 RetVals.push_back(MVT::f64);
476 RetVals.push_back(MVT::i32);
477 RetVals.push_back(MVT::i32);
482 std::vector<MVT::ValueType> NodeTys;
483 NodeTys.push_back(MVT::Other); // Returns a chain
484 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
485 std::vector<SDOperand> Ops;
486 Ops.push_back(Chain);
487 Ops.push_back(Callee);
489 // FIXME: Do not generate X86ISD::TAILCALL for now.
490 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
491 SDOperand InFlag = Chain.getValue(1);
494 if (RetTyVT != MVT::isVoid) {
496 default: assert(0 && "Unknown value type to return!");
499 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
500 Chain = RetVal.getValue(1);
503 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
504 Chain = RetVal.getValue(1);
507 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
508 Chain = RetVal.getValue(1);
511 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
512 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
514 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
515 Chain = Hi.getValue(1);
520 std::vector<MVT::ValueType> Tys;
521 Tys.push_back(MVT::f64);
522 Tys.push_back(MVT::Other);
523 std::vector<SDOperand> Ops;
524 Ops.push_back(Chain);
525 Ops.push_back(InFlag);
526 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
527 Chain = RetVal.getValue(1);
529 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
530 MachineFunction &MF = DAG.getMachineFunction();
531 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
532 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
534 Tys.push_back(MVT::Other);
536 Ops.push_back(Chain);
537 Ops.push_back(RetVal);
538 Ops.push_back(StackSlot);
539 Ops.push_back(DAG.getValueType(RetTyVT));
540 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
541 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
542 DAG.getSrcValue(NULL));
543 Chain = RetVal.getValue(1);
544 } else if (RetTyVT == MVT::f32)
545 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
551 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
552 DAG.getConstant(NumBytes, getPointerTy()),
553 DAG.getConstant(0, getPointerTy()));
554 return std::make_pair(RetVal, Chain);
556 std::vector<SDOperand> Ops;
557 Ops.push_back(Chain);
558 Ops.push_back(Callee);
559 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
560 Ops.push_back(DAG.getConstant(0, getPointerTy()));
562 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
567 case MVT::isVoid: break;
569 ResultVal = TheCall.getValue(1);
574 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
577 // FIXME: we would really like to remember that this FP_ROUND operation is
578 // okay to eliminate if we allow excess FP precision.
579 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
582 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
583 TheCall.getValue(2));
587 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
588 return std::make_pair(ResultVal, Chain);
593 X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
594 Value *VAListV, SelectionDAG &DAG) {
595 // vastart just stores the address of the VarArgsFrameIndex slot.
596 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
597 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
598 DAG.getSrcValue(VAListV));
602 std::pair<SDOperand,SDOperand>
603 X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP,
604 Value *VAListV, const Type *ArgTy,
606 MVT::ValueType ArgVT = getValueType(ArgTy);
607 SDOperand Val = DAG.getLoad(MVT::i32, Chain,
608 VAListP, DAG.getSrcValue(VAListV));
609 SDOperand Result = DAG.getLoad(ArgVT, Chain, Val,
610 DAG.getSrcValue(NULL));
612 if (ArgVT == MVT::i32)
615 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
616 "Other types should have been promoted for varargs!");
619 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
620 DAG.getConstant(Amt, Val.getValueType()));
621 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
622 Val, VAListP, DAG.getSrcValue(VAListV));
623 return std::make_pair(Result, Chain);
626 //===----------------------------------------------------------------------===//
627 // Fast Calling Convention implementation
628 //===----------------------------------------------------------------------===//
630 // The X86 'fast' calling convention passes up to two integer arguments in
631 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
632 // and requires that the callee pop its arguments off the stack (allowing proper
633 // tail calls), and has the same return value conventions as C calling convs.
635 // This calling convention always arranges for the callee pop value to be 8n+4
636 // bytes, which is needed for tail recursion elimination and stack alignment
639 // Note that this can be enhanced in the future to pass fp vals in registers
640 // (when we have a global fp allocator) and do other tricks.
643 /// AddLiveIn - This helper function adds the specified physical register to the
644 /// MachineFunction as a live in value. It also creates a corresponding virtual
646 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
647 TargetRegisterClass *RC) {
648 assert(RC->contains(PReg) && "Not the correct regclass!");
649 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
650 MF.addLiveIn(PReg, VReg);
655 std::vector<SDOperand>
656 X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
657 std::vector<SDOperand> ArgValues;
659 MachineFunction &MF = DAG.getMachineFunction();
660 MachineFrameInfo *MFI = MF.getFrameInfo();
662 // Add DAG nodes to load the arguments... On entry to a function the stack
663 // frame looks like this:
665 // [ESP] -- return address
666 // [ESP + 4] -- first nonreg argument (leftmost lexically)
667 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
669 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
671 // Keep track of the number of integer regs passed so far. This can be either
672 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
674 unsigned NumIntRegs = 0;
676 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
677 MVT::ValueType ObjectVT = getValueType(I->getType());
678 unsigned ArgIncrement = 4;
679 unsigned ObjSize = 0;
683 default: assert(0 && "Unhandled argument type!");
686 if (NumIntRegs < 2) {
687 if (!I->use_empty()) {
688 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
689 X86::R8RegisterClass);
690 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
691 DAG.setRoot(ArgValue.getValue(1));
692 if (ObjectVT == MVT::i1)
693 // FIXME: Should insert a assertzext here.
694 ArgValue = DAG.getNode(ISD::TRUNCATE, MVT::i1, ArgValue);
703 if (NumIntRegs < 2) {
704 if (!I->use_empty()) {
705 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
706 X86::R16RegisterClass);
707 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
708 DAG.setRoot(ArgValue.getValue(1));
716 if (NumIntRegs < 2) {
717 if (!I->use_empty()) {
718 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
719 X86::R32RegisterClass);
720 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
721 DAG.setRoot(ArgValue.getValue(1));
729 if (NumIntRegs == 0) {
730 if (!I->use_empty()) {
731 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
732 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
734 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
735 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
736 DAG.setRoot(Hi.getValue(1));
738 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
742 } else if (NumIntRegs == 1) {
743 if (!I->use_empty()) {
744 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
745 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
746 DAG.setRoot(Low.getValue(1));
748 // Load the high part from memory.
749 // Create the frame index object for this incoming parameter...
750 int FI = MFI->CreateFixedObject(4, ArgOffset);
751 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
752 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
753 DAG.getSrcValue(NULL));
754 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
760 ObjSize = ArgIncrement = 8;
762 case MVT::f32: ObjSize = 4; break;
763 case MVT::f64: ObjSize = ArgIncrement = 8; break;
766 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
768 if (ObjSize && !I->use_empty()) {
769 // Create the frame index object for this incoming parameter...
770 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
772 // Create the SelectionDAG nodes corresponding to a load from this
774 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
776 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
777 DAG.getSrcValue(NULL));
778 } else if (ArgValue.Val == 0) {
779 if (MVT::isInteger(ObjectVT))
780 ArgValue = DAG.getConstant(0, ObjectVT);
782 ArgValue = DAG.getConstantFP(0, ObjectVT);
784 ArgValues.push_back(ArgValue);
787 ArgOffset += ArgIncrement; // Move on to the next argument.
790 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
791 // arguments and the arguments after the retaddr has been pushed are aligned.
792 if ((ArgOffset & 7) == 0)
795 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
796 ReturnAddrIndex = 0; // No return address slot generated yet.
797 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
798 BytesCallerReserves = 0;
800 // Finally, inform the code generator which regs we return values in.
801 switch (getValueType(F.getReturnType())) {
802 default: assert(0 && "Unknown type!");
803 case MVT::isVoid: break;
808 MF.addLiveOut(X86::EAX);
811 MF.addLiveOut(X86::EAX);
812 MF.addLiveOut(X86::EDX);
816 MF.addLiveOut(X86::ST0);
822 std::pair<SDOperand, SDOperand>
823 X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
824 bool isTailCall, SDOperand Callee,
825 ArgListTy &Args, SelectionDAG &DAG) {
826 // Count how many bytes are to be pushed on the stack.
827 unsigned NumBytes = 0;
829 // Keep track of the number of integer regs passed so far. This can be either
830 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
832 unsigned NumIntRegs = 0;
834 for (unsigned i = 0, e = Args.size(); i != e; ++i)
835 switch (getValueType(Args[i].second)) {
836 default: assert(0 && "Unknown value type!");
841 if (NumIntRegs < 2) {
850 if (NumIntRegs == 0) {
853 } else if (NumIntRegs == 1) {
865 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
866 // arguments and the arguments after the retaddr has been pushed are aligned.
867 if ((NumBytes & 7) == 0)
870 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
871 DAG.getConstant(NumBytes, getPointerTy()));
873 // Arguments go on the stack in reverse order, as specified by the ABI.
874 unsigned ArgOffset = 0;
875 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
878 std::vector<SDOperand> Stores;
879 std::vector<SDOperand> RegValuesToPass;
880 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
881 switch (getValueType(Args[i].second)) {
882 default: assert(0 && "Unexpected ValueType for argument!");
884 Args[i].first = DAG.getNode(ISD::ANY_EXTEND, MVT::i8, Args[i].first);
889 if (NumIntRegs < 2) {
890 RegValuesToPass.push_back(Args[i].first);
896 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
897 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
898 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
899 Args[i].first, PtrOff,
900 DAG.getSrcValue(NULL)));
905 if (NumIntRegs < 2) { // Can pass part of it in regs?
906 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
907 Args[i].first, DAG.getConstant(1, MVT::i32));
908 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
909 Args[i].first, DAG.getConstant(0, MVT::i32));
910 RegValuesToPass.push_back(Lo);
912 if (NumIntRegs < 2) { // Pass both parts in regs?
913 RegValuesToPass.push_back(Hi);
916 // Pass the high part in memory.
917 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
918 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
919 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
920 Hi, PtrOff, DAG.getSrcValue(NULL)));
927 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
928 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
929 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
930 Args[i].first, PtrOff,
931 DAG.getSrcValue(NULL)));
937 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
939 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
940 // arguments and the arguments after the retaddr has been pushed are aligned.
941 if ((ArgOffset & 7) == 0)
944 std::vector<MVT::ValueType> RetVals;
945 MVT::ValueType RetTyVT = getValueType(RetTy);
947 RetVals.push_back(MVT::Other);
949 // The result values produced have to be legal. Promote the result.
951 case MVT::isVoid: break;
953 RetVals.push_back(RetTyVT);
958 RetVals.push_back(MVT::i32);
962 RetVals.push_back(MVT::f32);
964 RetVals.push_back(MVT::f64);
967 RetVals.push_back(MVT::i32);
968 RetVals.push_back(MVT::i32);
973 // Build a sequence of copy-to-reg nodes chained together with token chain
974 // and flag operands which copy the outgoing args into registers.
976 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
978 SDOperand RegToPass = RegValuesToPass[i];
979 switch (RegToPass.getValueType()) {
980 default: assert(0 && "Bad thing to pass in regs");
982 CCReg = (i == 0) ? X86::AL : X86::DL;
985 CCReg = (i == 0) ? X86::AX : X86::DX;
988 CCReg = (i == 0) ? X86::EAX : X86::EDX;
992 Chain = DAG.getCopyToReg(Chain, CCReg, RegToPass, InFlag);
993 InFlag = Chain.getValue(1);
996 std::vector<MVT::ValueType> NodeTys;
997 NodeTys.push_back(MVT::Other); // Returns a chain
998 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
999 std::vector<SDOperand> Ops;
1000 Ops.push_back(Chain);
1001 Ops.push_back(Callee);
1003 Ops.push_back(InFlag);
1005 // FIXME: Do not generate X86ISD::TAILCALL for now.
1006 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
1007 InFlag = Chain.getValue(1);
1010 if (RetTyVT != MVT::isVoid) {
1012 default: assert(0 && "Unknown value type to return!");
1015 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
1016 Chain = RetVal.getValue(1);
1019 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
1020 Chain = RetVal.getValue(1);
1023 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
1024 Chain = RetVal.getValue(1);
1027 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
1028 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
1030 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
1031 Chain = Hi.getValue(1);
1036 std::vector<MVT::ValueType> Tys;
1037 Tys.push_back(MVT::f64);
1038 Tys.push_back(MVT::Other);
1039 std::vector<SDOperand> Ops;
1040 Ops.push_back(Chain);
1041 Ops.push_back(InFlag);
1042 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
1043 Chain = RetVal.getValue(1);
1045 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
1046 MachineFunction &MF = DAG.getMachineFunction();
1047 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
1048 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1050 Tys.push_back(MVT::Other);
1052 Ops.push_back(Chain);
1053 Ops.push_back(RetVal);
1054 Ops.push_back(StackSlot);
1055 Ops.push_back(DAG.getValueType(RetTyVT));
1056 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
1057 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
1058 DAG.getSrcValue(NULL));
1059 Chain = RetVal.getValue(1);
1060 } else if (RetTyVT == MVT::f32)
1061 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
1067 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1068 DAG.getConstant(ArgOffset, getPointerTy()),
1069 DAG.getConstant(ArgOffset, getPointerTy()));
1070 return std::make_pair(RetVal, Chain);
1072 std::vector<SDOperand> Ops;
1073 Ops.push_back(Chain);
1074 Ops.push_back(Callee);
1075 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
1076 // Callee pops all arg values on the stack.
1077 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
1079 // Pass register arguments as needed.
1080 Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end());
1082 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1084 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
1086 SDOperand ResultVal;
1088 case MVT::isVoid: break;
1090 ResultVal = TheCall.getValue(1);
1095 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
1098 // FIXME: we would really like to remember that this FP_ROUND operation is
1099 // okay to eliminate if we allow excess FP precision.
1100 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
1103 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
1104 TheCall.getValue(2));
1108 return std::make_pair(ResultVal, Chain);
1112 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1113 if (ReturnAddrIndex == 0) {
1114 // Set up a frame object for the return address.
1115 MachineFunction &MF = DAG.getMachineFunction();
1116 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1119 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
1124 std::pair<SDOperand, SDOperand> X86TargetLowering::
1125 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
1126 SelectionDAG &DAG) {
1128 if (Depth) // Depths > 0 not supported yet!
1129 Result = DAG.getConstant(0, getPointerTy());
1131 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
1132 if (!isFrameAddress)
1133 // Just load the return address
1134 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
1135 DAG.getSrcValue(NULL));
1137 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
1138 DAG.getConstant(4, MVT::i32));
1140 return std::make_pair(Result, Chain);
1143 //===----------------------------------------------------------------------===//
1144 // X86 Custom Lowering Hooks
1145 //===----------------------------------------------------------------------===//
1147 /// SetCCToX86CondCode - do a one to one translation of a ISD::CondCode to
1148 /// X86 specific CondCode. It returns a X86ISD::COND_INVALID if it cannot
1149 /// do a direct translation.
1150 static unsigned CCToX86CondCode(SDOperand CC, bool isFP) {
1151 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
1152 unsigned X86CC = X86ISD::COND_INVALID;
1154 switch (SetCCOpcode) {
1156 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1157 case ISD::SETGT: X86CC = X86ISD::COND_G; break;
1158 case ISD::SETGE: X86CC = X86ISD::COND_GE; break;
1159 case ISD::SETLT: X86CC = X86ISD::COND_L; break;
1160 case ISD::SETLE: X86CC = X86ISD::COND_LE; break;
1161 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1162 case ISD::SETULT: X86CC = X86ISD::COND_B; break;
1163 case ISD::SETUGT: X86CC = X86ISD::COND_A; break;
1164 case ISD::SETULE: X86CC = X86ISD::COND_BE; break;
1165 case ISD::SETUGE: X86CC = X86ISD::COND_AE; break;
1168 // On a floating point condition, the flags are set as follows:
1170 // 0 | 0 | 0 | X > Y
1171 // 0 | 0 | 1 | X < Y
1172 // 1 | 0 | 0 | X == Y
1173 // 1 | 1 | 1 | unordered
1174 switch (SetCCOpcode) {
1177 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1179 case ISD::SETGT: X86CC = X86ISD::COND_A; break;
1181 case ISD::SETGE: X86CC = X86ISD::COND_AE; break;
1183 case ISD::SETLT: X86CC = X86ISD::COND_B; break;
1185 case ISD::SETLE: X86CC = X86ISD::COND_BE; break;
1187 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1188 case ISD::SETUO: X86CC = X86ISD::COND_P; break;
1189 case ISD::SETO: X86CC = X86ISD::COND_NP; break;
1195 /// LowerOperation - Provide custom lowering hooks for some operations.
1197 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1198 switch (Op.getOpcode()) {
1199 default: assert(0 && "Should not custom lower this!");
1200 case ISD::ADD_PARTS:
1201 case ISD::SUB_PARTS: {
1202 assert(Op.getNumOperands() == 4 && Op.getValueType() == MVT::i32 &&
1203 "Not an i64 add/sub!");
1204 bool isAdd = Op.getOpcode() == ISD::ADD_PARTS;
1205 std::vector<MVT::ValueType> Tys;
1206 Tys.push_back(MVT::i32);
1207 Tys.push_back(MVT::Flag);
1208 std::vector<SDOperand> Ops;
1209 Ops.push_back(Op.getOperand(0));
1210 Ops.push_back(Op.getOperand(2));
1211 SDOperand Lo = DAG.getNode(isAdd ? X86ISD::ADD_FLAG : X86ISD::SUB_FLAG,
1213 SDOperand Hi = DAG.getNode(isAdd ? X86ISD::ADC : X86ISD::SBB, MVT::i32,
1214 Op.getOperand(1), Op.getOperand(3),
1217 Tys.push_back(MVT::i32);
1218 Tys.push_back(MVT::i32);
1222 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1224 case ISD::SHL_PARTS:
1225 case ISD::SRA_PARTS:
1226 case ISD::SRL_PARTS: {
1227 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1228 "Not an i64 shift!");
1229 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
1230 SDOperand ShOpLo = Op.getOperand(0);
1231 SDOperand ShOpHi = Op.getOperand(1);
1232 SDOperand ShAmt = Op.getOperand(2);
1233 SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi,
1234 DAG.getConstant(32, MVT::i32))
1235 : DAG.getConstant(0, MVT::i32);
1237 SDOperand Tmp2, Tmp3;
1238 if (Op.getOpcode() == ISD::SHL_PARTS) {
1239 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
1240 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
1242 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
1243 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SHL, MVT::i32, ShOpHi, ShAmt);
1246 SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag,
1247 ShAmt, DAG.getConstant(32, MVT::i8));
1250 SDOperand CC = DAG.getConstant(X86ISD::COND_E, MVT::i8);
1252 std::vector<MVT::ValueType> Tys;
1253 Tys.push_back(MVT::i32);
1254 Tys.push_back(MVT::Flag);
1255 std::vector<SDOperand> Ops;
1256 if (Op.getOpcode() == ISD::SHL_PARTS) {
1257 Ops.push_back(Tmp2);
1258 Ops.push_back(Tmp3);
1260 Ops.push_back(InFlag);
1261 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1262 InFlag = Hi.getValue(1);
1265 Ops.push_back(Tmp3);
1266 Ops.push_back(Tmp1);
1268 Ops.push_back(InFlag);
1269 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1271 Ops.push_back(Tmp2);
1272 Ops.push_back(Tmp3);
1274 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1275 InFlag = Lo.getValue(1);
1278 Ops.push_back(Tmp3);
1279 Ops.push_back(Tmp1);
1281 Ops.push_back(InFlag);
1282 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1286 Tys.push_back(MVT::i32);
1287 Tys.push_back(MVT::i32);
1291 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1293 case ISD::SINT_TO_FP: {
1294 assert(Op.getValueType() == MVT::f64 &&
1295 Op.getOperand(0).getValueType() == MVT::i64 &&
1296 "Unknown SINT_TO_FP to lower!");
1297 // We lower sint64->FP into a store to a temporary stack slot, followed by a
1299 MachineFunction &MF = DAG.getMachineFunction();
1300 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
1301 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1302 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
1303 Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL));
1304 std::vector<MVT::ValueType> RTs;
1305 RTs.push_back(MVT::f64);
1306 RTs.push_back(MVT::Other);
1307 std::vector<SDOperand> Ops;
1308 Ops.push_back(Store);
1309 Ops.push_back(StackSlot);
1310 return DAG.getNode(X86ISD::FILD64m, RTs, Ops);
1312 case ISD::FP_TO_SINT: {
1313 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
1314 Op.getOperand(0).getValueType() == MVT::f64 &&
1315 "Unknown FP_TO_SINT to lower!");
1316 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
1318 MachineFunction &MF = DAG.getMachineFunction();
1319 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
1320 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
1321 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1324 switch (Op.getValueType()) {
1325 default: assert(0 && "Invalid FP_TO_SINT to lower!");
1326 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
1327 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
1328 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
1331 // Build the FP_TO_INT*_IN_MEM
1332 std::vector<SDOperand> Ops;
1333 Ops.push_back(DAG.getEntryNode());
1334 Ops.push_back(Op.getOperand(0));
1335 Ops.push_back(StackSlot);
1336 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
1339 return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
1340 DAG.getSrcValue(NULL));
1342 case ISD::READCYCLECOUNTER: {
1343 std::vector<MVT::ValueType> Tys;
1344 Tys.push_back(MVT::Other);
1345 Tys.push_back(MVT::Flag);
1346 std::vector<SDOperand> Ops;
1347 Ops.push_back(Op.getOperand(0));
1348 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops);
1350 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
1351 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
1352 MVT::i32, Ops[0].getValue(2)));
1353 Ops.push_back(Ops[1].getValue(1));
1354 Tys[0] = Tys[1] = MVT::i32;
1355 Tys.push_back(MVT::Other);
1356 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1359 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
1360 SDOperand CC = Op.getOperand(2);
1361 SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1362 Op.getOperand(0), Op.getOperand(1));
1363 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
1364 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
1365 unsigned X86CC = CCToX86CondCode(CC, isFP);
1366 if (X86CC != X86ISD::COND_INVALID) {
1367 return DAG.getNode(X86ISD::SETCC, MVT::i8,
1368 DAG.getConstant(X86CC, MVT::i8), Cond);
1370 assert(isFP && "Illegal integer SetCC!");
1372 std::vector<MVT::ValueType> Tys;
1373 std::vector<SDOperand> Ops;
1374 switch (SetCCOpcode) {
1375 default: assert(false && "Illegal floating point SetCC!");
1376 case ISD::SETOEQ: { // !PF & ZF
1377 Tys.push_back(MVT::i8);
1378 Tys.push_back(MVT::Flag);
1379 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1380 Ops.push_back(Cond);
1381 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1382 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1383 DAG.getConstant(X86ISD::COND_E, MVT::i8),
1385 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1387 case ISD::SETOLT: { // !PF & CF
1388 Tys.push_back(MVT::i8);
1389 Tys.push_back(MVT::Flag);
1390 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1391 Ops.push_back(Cond);
1392 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1393 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1394 DAG.getConstant(X86ISD::COND_B, MVT::i8),
1396 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1398 case ISD::SETOLE: { // !PF & (CF || ZF)
1399 Tys.push_back(MVT::i8);
1400 Tys.push_back(MVT::Flag);
1401 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1402 Ops.push_back(Cond);
1403 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1404 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1405 DAG.getConstant(X86ISD::COND_BE, MVT::i8),
1407 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1409 case ISD::SETUGT: { // PF | (!ZF & !CF)
1410 Tys.push_back(MVT::i8);
1411 Tys.push_back(MVT::Flag);
1412 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1413 Ops.push_back(Cond);
1414 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1415 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1416 DAG.getConstant(X86ISD::COND_A, MVT::i8),
1418 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1420 case ISD::SETUGE: { // PF | !CF
1421 Tys.push_back(MVT::i8);
1422 Tys.push_back(MVT::Flag);
1423 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1424 Ops.push_back(Cond);
1425 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1426 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1427 DAG.getConstant(X86ISD::COND_AE, MVT::i8),
1429 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1431 case ISD::SETUNE: { // PF | !ZF
1432 Tys.push_back(MVT::i8);
1433 Tys.push_back(MVT::Flag);
1434 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1435 Ops.push_back(Cond);
1436 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1437 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1438 DAG.getConstant(X86ISD::COND_NE, MVT::i8),
1440 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1446 SDOperand Cond = Op.getOperand(0);
1448 if (Cond.getOpcode() == X86ISD::SETCC) {
1449 CC = Cond.getOperand(0);
1450 Cond = Cond.getOperand(1);
1451 } else if (Cond.getOpcode() == ISD::SETCC) {
1452 CC = Cond.getOperand(2);
1453 bool isFP = MVT::isFloatingPoint(Cond.getOperand(1).getValueType());
1454 unsigned X86CC = CCToX86CondCode(CC, isFP);
1455 CC = DAG.getConstant(X86CC, MVT::i8);
1456 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1457 Cond.getOperand(0), Cond.getOperand(1));
1459 CC = DAG.getConstant(X86ISD::COND_E, MVT::i8);
1460 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1463 std::vector<MVT::ValueType> Tys;
1464 Tys.push_back(Op.getValueType());
1465 Tys.push_back(MVT::Flag);
1466 std::vector<SDOperand> Ops;
1467 Ops.push_back(Op.getOperand(1));
1468 Ops.push_back(Op.getOperand(2));
1470 Ops.push_back(Cond);
1471 return DAG.getNode(X86ISD::CMOV, Tys, Ops);
1474 SDOperand Cond = Op.getOperand(1);
1475 SDOperand Dest = Op.getOperand(2);
1477 // TODO: handle Cond == OR / AND / XOR
1478 if (Cond.getOpcode() == X86ISD::SETCC) {
1479 CC = Cond.getOperand(0);
1480 Cond = Cond.getOperand(1);
1481 } else if (Cond.getOpcode() == ISD::SETCC) {
1482 CC = Cond.getOperand(2);
1483 bool isFP = MVT::isFloatingPoint(Cond.getOperand(1).getValueType());
1484 unsigned X86CC = CCToX86CondCode(CC, isFP);
1485 CC = DAG.getConstant(X86CC, MVT::i8);
1486 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1487 Cond.getOperand(0), Cond.getOperand(1));
1489 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1490 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1492 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
1493 Op.getOperand(0), Op.getOperand(2), CC, Cond);
1496 // Can only be return void.
1497 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
1498 DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
1500 case ISD::GlobalAddress: {
1501 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1502 SDOperand GVOp = DAG.getTargetGlobalAddress(GV, getPointerTy());
1503 // For Darwin, external and weak symbols are indirect, so we want to load
1504 // the value at address GV, not the value of GV itself. This means that
1505 // the GlobalAddress must be in the base or index register of the address,
1506 // not the GV offset field.
1507 if (getTargetMachine().
1508 getSubtarget<X86Subtarget>().getIndirectExternAndWeakGlobals() &&
1509 (GV->hasWeakLinkage() || GV->isExternal()))
1510 return DAG.getLoad(MVT::i32, DAG.getEntryNode(),
1511 GVOp, DAG.getSrcValue(NULL));
1519 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
1521 default: return NULL;
1522 case X86ISD::ADD_FLAG: return "X86ISD::ADD_FLAG";
1523 case X86ISD::SUB_FLAG: return "X86ISD::SUB_FLAG";
1524 case X86ISD::ADC: return "X86ISD::ADC";
1525 case X86ISD::SBB: return "X86ISD::SBB";
1526 case X86ISD::SHLD: return "X86ISD::SHLD";
1527 case X86ISD::SHRD: return "X86ISD::SHRD";
1528 case X86ISD::FILD64m: return "X86ISD::FILD64m";
1529 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
1530 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
1531 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
1532 case X86ISD::FLD: return "X86ISD::FLD";
1533 case X86ISD::FST: return "X86ISD::FST";
1534 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
1535 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
1536 case X86ISD::CALL: return "X86ISD::CALL";
1537 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
1538 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
1539 case X86ISD::CMP: return "X86ISD::CMP";
1540 case X86ISD::TEST: return "X86ISD::TEST";
1541 case X86ISD::SETCC: return "X86ISD::SETCC";
1542 case X86ISD::CMOV: return "X86ISD::CMOV";
1543 case X86ISD::BRCOND: return "X86ISD::BRCOND";
1544 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
1548 bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
1549 uint64_t Mask) const {
1551 unsigned Opc = Op.getOpcode();
1555 assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node");
1557 case X86ISD::SETCC: return (Mask & 1) == 0;