1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 // Forward declarations.
71 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
74 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
75 const X86Subtarget &STI)
76 : TargetLowering(TM), Subtarget(&STI) {
77 X86ScalarSSEf64 = Subtarget->hasSSE2();
78 X86ScalarSSEf32 = Subtarget->hasSSE1();
81 // Set up the TargetLowering object.
82 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
84 // X86 is weird. It always uses i8 for shift amounts and setcc results.
85 setBooleanContents(ZeroOrOneBooleanContent);
86 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
87 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
89 // For 64-bit, since we have so many registers, use the ILP scheduler.
90 // For 32-bit, use the register pressure specific scheduling.
91 // For Atom, always use ILP scheduling.
92 if (Subtarget->isAtom())
93 setSchedulingPreference(Sched::ILP);
94 else if (Subtarget->is64Bit())
95 setSchedulingPreference(Sched::ILP);
97 setSchedulingPreference(Sched::RegPressure);
98 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
99 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
101 // Bypass expensive divides on Atom when compiling with O2.
102 if (TM.getOptLevel() >= CodeGenOpt::Default) {
103 if (Subtarget->hasSlowDivide32())
104 addBypassSlowDiv(32, 8);
105 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
106 addBypassSlowDiv(64, 16);
109 if (Subtarget->isTargetKnownWindowsMSVC()) {
110 // Setup Windows compiler runtime calls.
111 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
112 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
113 setLibcallName(RTLIB::SREM_I64, "_allrem");
114 setLibcallName(RTLIB::UREM_I64, "_aullrem");
115 setLibcallName(RTLIB::MUL_I64, "_allmul");
116 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
117 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
118 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
119 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
120 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
122 // The _ftol2 runtime function has an unusual calling conv, which
123 // is modeled by a special pseudo-instruction.
124 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
125 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
126 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
127 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
130 if (Subtarget->isTargetDarwin()) {
131 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
132 setUseUnderscoreSetJmp(false);
133 setUseUnderscoreLongJmp(false);
134 } else if (Subtarget->isTargetWindowsGNU()) {
135 // MS runtime is weird: it exports _setjmp, but longjmp!
136 setUseUnderscoreSetJmp(true);
137 setUseUnderscoreLongJmp(false);
139 setUseUnderscoreSetJmp(true);
140 setUseUnderscoreLongJmp(true);
143 // Set up the register classes.
144 addRegisterClass(MVT::i8, &X86::GR8RegClass);
145 addRegisterClass(MVT::i16, &X86::GR16RegClass);
146 addRegisterClass(MVT::i32, &X86::GR32RegClass);
147 if (Subtarget->is64Bit())
148 addRegisterClass(MVT::i64, &X86::GR64RegClass);
150 for (MVT VT : MVT::integer_valuetypes())
151 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
153 // We don't accept any truncstore of integer registers.
154 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
155 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
156 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
157 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
158 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
159 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
161 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
163 // SETOEQ and SETUNE require checking two conditions.
164 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
165 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
166 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
167 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
168 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
169 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
171 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
173 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
174 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
175 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
177 if (Subtarget->is64Bit()) {
178 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
179 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
180 } else if (!Subtarget->useSoftFloat()) {
181 // We have an algorithm for SSE2->double, and we turn this into a
182 // 64-bit FILD followed by conditional FADD for other targets.
183 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
184 // We have an algorithm for SSE2, and we turn this into a 64-bit
185 // FILD for other targets.
186 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
189 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
191 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
192 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
194 if (!Subtarget->useSoftFloat()) {
195 // SSE has no i16 to fp conversion, only i32
196 if (X86ScalarSSEf32) {
197 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
198 // f32 and f64 cases are Legal, f80 case is not
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
201 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
202 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
206 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
209 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
210 // are Legal, f80 is custom lowered.
211 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
214 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
216 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
219 if (X86ScalarSSEf32) {
220 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
221 // f32 and f64 cases are Legal, f80 case is not
222 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
225 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
228 // Handle FP_TO_UINT by promoting the destination to a larger signed
230 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
232 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
234 if (Subtarget->is64Bit()) {
235 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
237 } else if (!Subtarget->useSoftFloat()) {
238 // Since AVX is a superset of SSE3, only check for SSE here.
239 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
240 // Expand FP_TO_UINT into a select.
241 // FIXME: We would like to use a Custom expander here eventually to do
242 // the optimal thing for SSE vs. the default expansion in the legalizer.
243 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
250 if (isTargetFTOL()) {
251 // Use the _ftol2 runtime function, which has a pseudo-instruction
252 // to handle its weird calling convention.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
256 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
257 if (!X86ScalarSSEf64) {
258 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
259 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
260 if (Subtarget->is64Bit()) {
261 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
262 // Without SSE, i64->f64 goes through memory.
263 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
267 // Scalar integer divide and remainder are lowered to use operations that
268 // produce two results, to match the available instructions. This exposes
269 // the two-result form to trivial CSE, which is able to combine x/y and x%y
270 // into a single instruction.
272 // Scalar integer multiply-high is also lowered to use two-result
273 // operations, to match the available instructions. However, plain multiply
274 // (low) operations are left as Legal, as there are single-result
275 // instructions for this in x86. Using the two-result multiply instructions
276 // when both high and low results are needed must be arranged by dagcombine.
277 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
279 setOperationAction(ISD::MULHS, VT, Expand);
280 setOperationAction(ISD::MULHU, VT, Expand);
281 setOperationAction(ISD::SDIV, VT, Expand);
282 setOperationAction(ISD::UDIV, VT, Expand);
283 setOperationAction(ISD::SREM, VT, Expand);
284 setOperationAction(ISD::UREM, VT, Expand);
286 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
287 setOperationAction(ISD::ADDC, VT, Custom);
288 setOperationAction(ISD::ADDE, VT, Custom);
289 setOperationAction(ISD::SUBC, VT, Custom);
290 setOperationAction(ISD::SUBE, VT, Custom);
293 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
294 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
295 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
296 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
298 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
299 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
309 if (Subtarget->is64Bit())
310 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
314 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
315 setOperationAction(ISD::FREM , MVT::f32 , Expand);
316 setOperationAction(ISD::FREM , MVT::f64 , Expand);
317 setOperationAction(ISD::FREM , MVT::f80 , Expand);
318 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
320 // Promote the i8 variants and force them on up to i32 which has a shorter
322 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
323 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
324 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
325 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
326 if (Subtarget->hasBMI()) {
327 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
328 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
329 if (Subtarget->is64Bit())
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
332 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
333 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
334 if (Subtarget->is64Bit())
335 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
338 if (Subtarget->hasLZCNT()) {
339 // When promoting the i8 variants, force them to i32 for a shorter
341 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
342 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
343 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
344 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
345 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
346 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
347 if (Subtarget->is64Bit())
348 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
350 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
351 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
352 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
353 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
355 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
356 if (Subtarget->is64Bit()) {
357 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
358 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
362 // Special handling for half-precision floating point conversions.
363 // If we don't have F16C support, then lower half float conversions
364 // into library calls.
365 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
366 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
367 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
370 // There's never any support for operations beyond MVT::f32.
371 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
372 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
374 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
376 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
377 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
378 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
379 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
380 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
381 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
383 if (Subtarget->hasPOPCNT()) {
384 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
386 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
387 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
388 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
393 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
395 if (!Subtarget->hasMOVBE())
396 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
398 // These should be promoted to a larger select which is supported.
399 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
400 // X86 wants to expand cmov itself.
401 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
402 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
403 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
404 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
405 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
406 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
407 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
408 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
409 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
410 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
411 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
412 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
413 if (Subtarget->is64Bit()) {
414 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
417 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
418 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
419 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
420 // support continuation, user-level threading, and etc.. As a result, no
421 // other SjLj exception interfaces are implemented and please don't build
422 // your own exception handling based on them.
423 // LLVM/Clang supports zero-cost DWARF exception handling.
424 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
425 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
428 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
429 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
430 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
431 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
432 if (Subtarget->is64Bit())
433 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
434 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
435 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
436 if (Subtarget->is64Bit()) {
437 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
438 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
439 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
440 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
443 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
444 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
447 if (Subtarget->is64Bit()) {
448 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
449 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
450 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
453 if (Subtarget->hasSSE1())
454 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
456 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
458 // Expand certain atomics
459 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
461 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
462 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
463 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
466 if (Subtarget->hasCmpxchg16b()) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
470 // FIXME - use subtarget debug flags
471 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
472 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
473 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
476 if (Subtarget->is64Bit()) {
477 setExceptionPointerRegister(X86::RAX);
478 setExceptionSelectorRegister(X86::RDX);
480 setExceptionPointerRegister(X86::EAX);
481 setExceptionSelectorRegister(X86::EDX);
483 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
484 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
486 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
487 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
489 setOperationAction(ISD::TRAP, MVT::Other, Legal);
490 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
492 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
493 setOperationAction(ISD::VASTART , MVT::Other, Custom);
494 setOperationAction(ISD::VAEND , MVT::Other, Expand);
495 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
496 // TargetInfo::X86_64ABIBuiltinVaList
497 setOperationAction(ISD::VAARG , MVT::Other, Custom);
498 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
500 // TargetInfo::CharPtrBuiltinVaList
501 setOperationAction(ISD::VAARG , MVT::Other, Expand);
502 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
505 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
506 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
508 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
510 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
511 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
512 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
514 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
515 // f32 and f64 use SSE.
516 // Set up the FP register classes.
517 addRegisterClass(MVT::f32, &X86::FR32RegClass);
518 addRegisterClass(MVT::f64, &X86::FR64RegClass);
520 // Use ANDPD to simulate FABS.
521 setOperationAction(ISD::FABS , MVT::f64, Custom);
522 setOperationAction(ISD::FABS , MVT::f32, Custom);
524 // Use XORP to simulate FNEG.
525 setOperationAction(ISD::FNEG , MVT::f64, Custom);
526 setOperationAction(ISD::FNEG , MVT::f32, Custom);
528 // Use ANDPD and ORPD to simulate FCOPYSIGN.
529 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
530 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
532 // Lower this to FGETSIGNx86 plus an AND.
533 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
534 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
536 // We don't support sin/cos/fmod
537 setOperationAction(ISD::FSIN , MVT::f64, Expand);
538 setOperationAction(ISD::FCOS , MVT::f64, Expand);
539 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
540 setOperationAction(ISD::FSIN , MVT::f32, Expand);
541 setOperationAction(ISD::FCOS , MVT::f32, Expand);
542 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
544 // Expand FP immediates into loads from the stack, except for the special
546 addLegalFPImmediate(APFloat(+0.0)); // xorpd
547 addLegalFPImmediate(APFloat(+0.0f)); // xorps
548 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
549 // Use SSE for f32, x87 for f64.
550 // Set up the FP register classes.
551 addRegisterClass(MVT::f32, &X86::FR32RegClass);
552 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
554 // Use ANDPS to simulate FABS.
555 setOperationAction(ISD::FABS , MVT::f32, Custom);
557 // Use XORP to simulate FNEG.
558 setOperationAction(ISD::FNEG , MVT::f32, Custom);
560 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
562 // Use ANDPS and ORPS to simulate FCOPYSIGN.
563 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
564 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
566 // We don't support sin/cos/fmod
567 setOperationAction(ISD::FSIN , MVT::f32, Expand);
568 setOperationAction(ISD::FCOS , MVT::f32, Expand);
569 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
571 // Special cases we handle for FP constants.
572 addLegalFPImmediate(APFloat(+0.0f)); // xorps
573 addLegalFPImmediate(APFloat(+0.0)); // FLD0
574 addLegalFPImmediate(APFloat(+1.0)); // FLD1
575 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
576 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
578 if (!TM.Options.UnsafeFPMath) {
579 setOperationAction(ISD::FSIN , MVT::f64, Expand);
580 setOperationAction(ISD::FCOS , MVT::f64, Expand);
581 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
583 } else if (!Subtarget->useSoftFloat()) {
584 // f32 and f64 in x87.
585 // Set up the FP register classes.
586 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
587 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
589 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
590 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
591 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
592 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
594 if (!TM.Options.UnsafeFPMath) {
595 setOperationAction(ISD::FSIN , MVT::f64, Expand);
596 setOperationAction(ISD::FSIN , MVT::f32, Expand);
597 setOperationAction(ISD::FCOS , MVT::f64, Expand);
598 setOperationAction(ISD::FCOS , MVT::f32, Expand);
599 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
600 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
602 addLegalFPImmediate(APFloat(+0.0)); // FLD0
603 addLegalFPImmediate(APFloat(+1.0)); // FLD1
604 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
605 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
606 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
607 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
608 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
609 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
612 // We don't support FMA.
613 setOperationAction(ISD::FMA, MVT::f64, Expand);
614 setOperationAction(ISD::FMA, MVT::f32, Expand);
616 // Long double always uses X87.
617 if (!Subtarget->useSoftFloat()) {
618 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
619 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
620 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
622 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
623 addLegalFPImmediate(TmpFlt); // FLD0
625 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
628 APFloat TmpFlt2(+1.0);
629 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
631 addLegalFPImmediate(TmpFlt2); // FLD1
632 TmpFlt2.changeSign();
633 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
636 if (!TM.Options.UnsafeFPMath) {
637 setOperationAction(ISD::FSIN , MVT::f80, Expand);
638 setOperationAction(ISD::FCOS , MVT::f80, Expand);
639 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
642 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
643 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
644 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
645 setOperationAction(ISD::FRINT, MVT::f80, Expand);
646 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
647 setOperationAction(ISD::FMA, MVT::f80, Expand);
650 // Always use a library call for pow.
651 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
652 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
653 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
655 setOperationAction(ISD::FLOG, MVT::f80, Expand);
656 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
657 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
658 setOperationAction(ISD::FEXP, MVT::f80, Expand);
659 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
660 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
661 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
663 // First set operation action for all vector types to either promote
664 // (for widening) or expand (for scalarization). Then we will selectively
665 // turn on ones that can be effectively codegen'd.
666 for (MVT VT : MVT::vector_valuetypes()) {
667 setOperationAction(ISD::ADD , VT, Expand);
668 setOperationAction(ISD::SUB , VT, Expand);
669 setOperationAction(ISD::FADD, VT, Expand);
670 setOperationAction(ISD::FNEG, VT, Expand);
671 setOperationAction(ISD::FSUB, VT, Expand);
672 setOperationAction(ISD::MUL , VT, Expand);
673 setOperationAction(ISD::FMUL, VT, Expand);
674 setOperationAction(ISD::SDIV, VT, Expand);
675 setOperationAction(ISD::UDIV, VT, Expand);
676 setOperationAction(ISD::FDIV, VT, Expand);
677 setOperationAction(ISD::SREM, VT, Expand);
678 setOperationAction(ISD::UREM, VT, Expand);
679 setOperationAction(ISD::LOAD, VT, Expand);
680 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
681 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
682 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
683 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
684 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
685 setOperationAction(ISD::FABS, VT, Expand);
686 setOperationAction(ISD::FSIN, VT, Expand);
687 setOperationAction(ISD::FSINCOS, VT, Expand);
688 setOperationAction(ISD::FCOS, VT, Expand);
689 setOperationAction(ISD::FSINCOS, VT, Expand);
690 setOperationAction(ISD::FREM, VT, Expand);
691 setOperationAction(ISD::FMA, VT, Expand);
692 setOperationAction(ISD::FPOWI, VT, Expand);
693 setOperationAction(ISD::FSQRT, VT, Expand);
694 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
695 setOperationAction(ISD::FFLOOR, VT, Expand);
696 setOperationAction(ISD::FCEIL, VT, Expand);
697 setOperationAction(ISD::FTRUNC, VT, Expand);
698 setOperationAction(ISD::FRINT, VT, Expand);
699 setOperationAction(ISD::FNEARBYINT, VT, Expand);
700 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
701 setOperationAction(ISD::MULHS, VT, Expand);
702 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHU, VT, Expand);
704 setOperationAction(ISD::SDIVREM, VT, Expand);
705 setOperationAction(ISD::UDIVREM, VT, Expand);
706 setOperationAction(ISD::FPOW, VT, Expand);
707 setOperationAction(ISD::CTPOP, VT, Expand);
708 setOperationAction(ISD::CTTZ, VT, Expand);
709 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
710 setOperationAction(ISD::CTLZ, VT, Expand);
711 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
712 setOperationAction(ISD::SHL, VT, Expand);
713 setOperationAction(ISD::SRA, VT, Expand);
714 setOperationAction(ISD::SRL, VT, Expand);
715 setOperationAction(ISD::ROTL, VT, Expand);
716 setOperationAction(ISD::ROTR, VT, Expand);
717 setOperationAction(ISD::BSWAP, VT, Expand);
718 setOperationAction(ISD::SETCC, VT, Expand);
719 setOperationAction(ISD::FLOG, VT, Expand);
720 setOperationAction(ISD::FLOG2, VT, Expand);
721 setOperationAction(ISD::FLOG10, VT, Expand);
722 setOperationAction(ISD::FEXP, VT, Expand);
723 setOperationAction(ISD::FEXP2, VT, Expand);
724 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
725 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
726 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
727 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
728 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
729 setOperationAction(ISD::TRUNCATE, VT, Expand);
730 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
731 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
732 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
733 setOperationAction(ISD::VSELECT, VT, Expand);
734 setOperationAction(ISD::SELECT_CC, VT, Expand);
735 for (MVT InnerVT : MVT::vector_valuetypes()) {
736 setTruncStoreAction(InnerVT, VT, Expand);
738 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
739 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
741 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
742 // types, we have to deal with them whether we ask for Expansion or not.
743 // Setting Expand causes its own optimisation problems though, so leave
745 if (VT.getVectorElementType() == MVT::i1)
746 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
748 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
749 // split/scalarized right now.
750 if (VT.getVectorElementType() == MVT::f16)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
755 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
756 // with -msoft-float, disable use of MMX as well.
757 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
758 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
759 // No operations on x86mmx supported, everything uses intrinsics.
762 // MMX-sized vectors (other than x86mmx) are expected to be expanded
763 // into smaller operations.
764 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
765 setOperationAction(ISD::MULHS, MMXTy, Expand);
766 setOperationAction(ISD::AND, MMXTy, Expand);
767 setOperationAction(ISD::OR, MMXTy, Expand);
768 setOperationAction(ISD::XOR, MMXTy, Expand);
769 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
770 setOperationAction(ISD::SELECT, MMXTy, Expand);
771 setOperationAction(ISD::BITCAST, MMXTy, Expand);
773 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
775 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
776 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
778 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
779 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
780 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
781 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
782 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
783 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
784 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
785 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
786 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
787 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
788 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
789 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
790 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
791 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
794 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
795 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
797 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
798 // registers cannot be used even for integer operations.
799 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
800 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
801 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
802 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
804 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
805 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
806 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
807 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
808 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
809 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
810 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
811 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
812 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
813 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
814 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
815 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
816 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
817 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
818 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
819 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
820 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
821 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
822 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
823 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
824 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
825 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
826 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
828 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
829 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
830 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
831 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
833 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
834 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
835 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
837 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
839 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
840 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
841 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
842 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
844 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
845 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
846 MVT VT = (MVT::SimpleValueType)i;
847 // Do not attempt to custom lower non-power-of-2 vectors
848 if (!isPowerOf2_32(VT.getVectorNumElements()))
850 // Do not attempt to custom lower non-128-bit vectors
851 if (!VT.is128BitVector())
853 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
854 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
855 setOperationAction(ISD::VSELECT, VT, Custom);
856 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
859 // We support custom legalizing of sext and anyext loads for specific
860 // memory vector types which we can load as a scalar (or sequence of
861 // scalars) and extend in-register to a legal 128-bit vector type. For sext
862 // loads these must work with a single scalar load.
863 for (MVT VT : MVT::integer_vector_valuetypes()) {
864 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
865 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
866 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
867 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
868 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
869 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
870 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
871 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
872 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
875 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
876 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
877 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
878 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
879 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
880 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
881 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
882 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
884 if (Subtarget->is64Bit()) {
885 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
886 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
889 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
890 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
891 MVT VT = (MVT::SimpleValueType)i;
893 // Do not attempt to promote non-128-bit vectors
894 if (!VT.is128BitVector())
897 setOperationAction(ISD::AND, VT, Promote);
898 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
899 setOperationAction(ISD::OR, VT, Promote);
900 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
901 setOperationAction(ISD::XOR, VT, Promote);
902 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
903 setOperationAction(ISD::LOAD, VT, Promote);
904 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
905 setOperationAction(ISD::SELECT, VT, Promote);
906 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
909 // Custom lower v2i64 and v2f64 selects.
910 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
911 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
912 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
913 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
915 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
916 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
918 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
919 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
920 // As there is no 64-bit GPR available, we need build a special custom
921 // sequence to convert from v2i32 to v2f32.
922 if (!Subtarget->is64Bit())
923 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
925 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
926 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
928 for (MVT VT : MVT::fp_vector_valuetypes())
929 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
931 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
932 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
933 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
936 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
937 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
938 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
939 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
940 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
941 setOperationAction(ISD::FRINT, RoundedTy, Legal);
942 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
945 // FIXME: Do we need to handle scalar-to-vector here?
946 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
948 // We directly match byte blends in the backend as they match the VSELECT
950 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
952 // SSE41 brings specific instructions for doing vector sign extend even in
953 // cases where we don't have SRA.
954 for (MVT VT : MVT::integer_vector_valuetypes()) {
955 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
956 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
957 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
960 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
961 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
962 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
963 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
964 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
965 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
966 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
968 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
969 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
970 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
971 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
972 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
973 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
975 // i8 and i16 vectors are custom because the source register and source
976 // source memory operand types are not the same width. f32 vectors are
977 // custom since the immediate controlling the insert encodes additional
979 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
980 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
981 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
982 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
984 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
985 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
989 // FIXME: these should be Legal, but that's only for the case where
990 // the index is constant. For now custom expand to deal with that.
991 if (Subtarget->is64Bit()) {
992 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
993 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
997 if (Subtarget->hasSSE2()) {
998 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
999 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1000 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1002 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1003 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1005 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1006 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1008 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1009 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1011 // In the customized shift lowering, the legal cases in AVX2 will be
1013 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1014 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1016 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1017 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1019 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1022 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1023 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1024 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1025 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1026 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1027 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1028 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1030 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1031 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1032 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1034 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1035 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1036 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1037 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1038 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1039 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1040 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1041 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1042 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1043 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1044 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1045 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1047 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1048 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1049 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1050 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1051 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1052 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1053 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1054 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1055 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1056 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1057 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1058 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1060 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1061 // even though v8i16 is a legal type.
1062 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1063 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1064 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1066 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1067 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1068 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1070 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1071 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1073 for (MVT VT : MVT::fp_vector_valuetypes())
1074 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1076 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1077 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1079 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1080 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1082 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1083 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1085 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1086 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1087 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1088 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1090 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1091 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1092 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1094 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1095 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1096 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1097 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1098 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1099 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1100 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1101 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1102 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1103 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1104 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1105 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1107 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1108 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1109 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1110 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1112 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1113 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1114 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1115 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1116 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1117 setOperationAction(ISD::FMA, MVT::f32, Legal);
1118 setOperationAction(ISD::FMA, MVT::f64, Legal);
1121 if (Subtarget->hasInt256()) {
1122 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1123 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1124 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1125 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1127 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1128 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1129 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1130 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1132 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1133 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1134 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1135 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1137 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1138 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1139 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1140 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1142 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1143 // when we have a 256bit-wide blend with immediate.
1144 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1146 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1147 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1148 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1149 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1150 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1151 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1152 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1154 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1155 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1156 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1157 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1158 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1159 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1161 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1162 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1163 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1164 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1166 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1167 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1168 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1169 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1171 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1172 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1173 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1174 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1177 // In the customized shift lowering, the legal cases in AVX2 will be
1179 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1180 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1182 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1183 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1185 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1187 // Custom lower several nodes for 256-bit types.
1188 for (MVT VT : MVT::vector_valuetypes()) {
1189 if (VT.getScalarSizeInBits() >= 32) {
1190 setOperationAction(ISD::MLOAD, VT, Legal);
1191 setOperationAction(ISD::MSTORE, VT, Legal);
1193 // Extract subvector is special because the value type
1194 // (result) is 128-bit but the source is 256-bit wide.
1195 if (VT.is128BitVector()) {
1196 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1198 // Do not attempt to custom lower other non-256-bit vectors
1199 if (!VT.is256BitVector())
1202 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1203 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1204 setOperationAction(ISD::VSELECT, VT, Custom);
1205 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1206 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1207 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1208 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1209 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1212 if (Subtarget->hasInt256())
1213 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1216 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1217 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1218 MVT VT = (MVT::SimpleValueType)i;
1220 // Do not attempt to promote non-256-bit vectors
1221 if (!VT.is256BitVector())
1224 setOperationAction(ISD::AND, VT, Promote);
1225 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1226 setOperationAction(ISD::OR, VT, Promote);
1227 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1228 setOperationAction(ISD::XOR, VT, Promote);
1229 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1230 setOperationAction(ISD::LOAD, VT, Promote);
1231 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1232 setOperationAction(ISD::SELECT, VT, Promote);
1233 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1237 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1238 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1239 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1240 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1241 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1243 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1244 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1245 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1247 for (MVT VT : MVT::fp_vector_valuetypes())
1248 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1250 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1251 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1252 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1253 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1254 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1255 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1256 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1257 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1258 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1259 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1260 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1261 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1263 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1264 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1265 setOperationAction(ISD::XOR, MVT::i1, Legal);
1266 setOperationAction(ISD::OR, MVT::i1, Legal);
1267 setOperationAction(ISD::AND, MVT::i1, Legal);
1268 setOperationAction(ISD::SUB, MVT::i1, Custom);
1269 setOperationAction(ISD::ADD, MVT::i1, Custom);
1270 setOperationAction(ISD::MUL, MVT::i1, Custom);
1271 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1272 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1273 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1274 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1275 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1277 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1278 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1279 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1280 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1281 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1282 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1284 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1285 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1286 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1287 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1288 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1289 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1290 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1291 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1293 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1294 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1295 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1296 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1297 if (Subtarget->is64Bit()) {
1298 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1299 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1300 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1301 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1303 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1304 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1305 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1306 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1307 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1308 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1309 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1310 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1311 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1312 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1313 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1314 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1315 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1316 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1317 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1318 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1320 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1321 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1322 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1323 if (Subtarget->hasDQI()) {
1324 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1325 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1327 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1328 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1329 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1330 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1331 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1332 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1333 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1334 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1335 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1336 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1337 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1338 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1339 if (Subtarget->hasDQI()) {
1340 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1341 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1343 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1344 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1345 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1346 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1348 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1349 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1350 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1352 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1354 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1355 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1356 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1357 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1358 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1360 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1361 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1363 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1365 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1366 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1367 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1368 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1369 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1370 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1371 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1372 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1373 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1374 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1375 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1377 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1378 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1380 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1381 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1383 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1385 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1386 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1388 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1389 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1391 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1392 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1394 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1395 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1396 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1397 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1398 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1399 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1401 if (Subtarget->hasCDI()) {
1402 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1403 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1405 if (Subtarget->hasDQI()) {
1406 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1407 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1408 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1410 // Custom lower several nodes.
1411 for (MVT VT : MVT::vector_valuetypes()) {
1412 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1414 setOperationAction(ISD::AND, VT, Legal);
1415 setOperationAction(ISD::OR, VT, Legal);
1416 setOperationAction(ISD::XOR, VT, Legal);
1418 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1419 setOperationAction(ISD::MGATHER, VT, Custom);
1420 setOperationAction(ISD::MSCATTER, VT, Custom);
1422 // Extract subvector is special because the value type
1423 // (result) is 256/128-bit but the source is 512-bit wide.
1424 if (VT.is128BitVector() || VT.is256BitVector()) {
1425 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1427 if (VT.getVectorElementType() == MVT::i1)
1428 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1430 // Do not attempt to custom lower other non-512-bit vectors
1431 if (!VT.is512BitVector())
1434 if (EltSize >= 32) {
1435 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1436 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1437 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1438 setOperationAction(ISD::VSELECT, VT, Legal);
1439 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1440 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1441 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1442 setOperationAction(ISD::MLOAD, VT, Legal);
1443 setOperationAction(ISD::MSTORE, VT, Legal);
1446 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1447 MVT VT = (MVT::SimpleValueType)i;
1449 // Do not attempt to promote non-512-bit vectors.
1450 if (!VT.is512BitVector())
1453 setOperationAction(ISD::SELECT, VT, Promote);
1454 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1458 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1459 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1460 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1462 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1463 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1465 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1466 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1467 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1468 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1469 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1470 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1471 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1472 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1473 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1474 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1475 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1476 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1477 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1478 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1479 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1480 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1481 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1482 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1483 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1484 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1485 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1486 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1487 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1488 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1489 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1490 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1491 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1493 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1494 const MVT VT = (MVT::SimpleValueType)i;
1496 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1498 // Do not attempt to promote non-512-bit vectors.
1499 if (!VT.is512BitVector())
1503 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1504 setOperationAction(ISD::VSELECT, VT, Legal);
1509 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1510 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1511 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1513 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1514 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1515 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1516 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1517 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1518 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1519 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1520 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1521 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1522 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1524 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1525 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1526 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1527 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1528 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1529 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1530 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1531 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1534 // We want to custom lower some of our intrinsics.
1535 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1536 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1537 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1538 if (!Subtarget->is64Bit())
1539 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1541 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1542 // handle type legalization for these operations here.
1544 // FIXME: We really should do custom legalization for addition and
1545 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1546 // than generic legalization for 64-bit multiplication-with-overflow, though.
1547 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1548 // Add/Sub/Mul with overflow operations are custom lowered.
1550 setOperationAction(ISD::SADDO, VT, Custom);
1551 setOperationAction(ISD::UADDO, VT, Custom);
1552 setOperationAction(ISD::SSUBO, VT, Custom);
1553 setOperationAction(ISD::USUBO, VT, Custom);
1554 setOperationAction(ISD::SMULO, VT, Custom);
1555 setOperationAction(ISD::UMULO, VT, Custom);
1559 if (!Subtarget->is64Bit()) {
1560 // These libcalls are not available in 32-bit.
1561 setLibcallName(RTLIB::SHL_I128, nullptr);
1562 setLibcallName(RTLIB::SRL_I128, nullptr);
1563 setLibcallName(RTLIB::SRA_I128, nullptr);
1566 // Combine sin / cos into one node or libcall if possible.
1567 if (Subtarget->hasSinCos()) {
1568 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1569 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1570 if (Subtarget->isTargetDarwin()) {
1571 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1572 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1573 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1574 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1578 if (Subtarget->isTargetWin64()) {
1579 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1580 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1581 setOperationAction(ISD::SREM, MVT::i128, Custom);
1582 setOperationAction(ISD::UREM, MVT::i128, Custom);
1583 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1584 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1587 // We have target-specific dag combine patterns for the following nodes:
1588 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1589 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1590 setTargetDAGCombine(ISD::BITCAST);
1591 setTargetDAGCombine(ISD::VSELECT);
1592 setTargetDAGCombine(ISD::SELECT);
1593 setTargetDAGCombine(ISD::SHL);
1594 setTargetDAGCombine(ISD::SRA);
1595 setTargetDAGCombine(ISD::SRL);
1596 setTargetDAGCombine(ISD::OR);
1597 setTargetDAGCombine(ISD::AND);
1598 setTargetDAGCombine(ISD::ADD);
1599 setTargetDAGCombine(ISD::FADD);
1600 setTargetDAGCombine(ISD::FSUB);
1601 setTargetDAGCombine(ISD::FMA);
1602 setTargetDAGCombine(ISD::SUB);
1603 setTargetDAGCombine(ISD::LOAD);
1604 setTargetDAGCombine(ISD::MLOAD);
1605 setTargetDAGCombine(ISD::STORE);
1606 setTargetDAGCombine(ISD::MSTORE);
1607 setTargetDAGCombine(ISD::ZERO_EXTEND);
1608 setTargetDAGCombine(ISD::ANY_EXTEND);
1609 setTargetDAGCombine(ISD::SIGN_EXTEND);
1610 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1611 setTargetDAGCombine(ISD::SINT_TO_FP);
1612 setTargetDAGCombine(ISD::SETCC);
1613 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1614 setTargetDAGCombine(ISD::BUILD_VECTOR);
1615 setTargetDAGCombine(ISD::MUL);
1616 setTargetDAGCombine(ISD::XOR);
1618 computeRegisterProperties(Subtarget->getRegisterInfo());
1620 // On Darwin, -Os means optimize for size without hurting performance,
1621 // do not reduce the limit.
1622 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1623 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1624 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1625 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1626 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1627 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1628 setPrefLoopAlignment(4); // 2^4 bytes.
1630 // Predictable cmov don't hurt on atom because it's in-order.
1631 PredictableSelectIsExpensive = !Subtarget->isAtom();
1632 EnableExtLdPromotion = true;
1633 setPrefFunctionAlignment(4); // 2^4 bytes.
1635 verifyIntrinsicTables();
1638 // This has so far only been implemented for 64-bit MachO.
1639 bool X86TargetLowering::useLoadStackGuardNode() const {
1640 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1643 TargetLoweringBase::LegalizeTypeAction
1644 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1645 if (ExperimentalVectorWideningLegalization &&
1646 VT.getVectorNumElements() != 1 &&
1647 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1648 return TypeWidenVector;
1650 return TargetLoweringBase::getPreferredVectorAction(VT);
1653 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1655 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1657 const unsigned NumElts = VT.getVectorNumElements();
1658 const EVT EltVT = VT.getVectorElementType();
1659 if (VT.is512BitVector()) {
1660 if (Subtarget->hasAVX512())
1661 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1662 EltVT == MVT::f32 || EltVT == MVT::f64)
1664 case 8: return MVT::v8i1;
1665 case 16: return MVT::v16i1;
1667 if (Subtarget->hasBWI())
1668 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1670 case 32: return MVT::v32i1;
1671 case 64: return MVT::v64i1;
1675 if (VT.is256BitVector() || VT.is128BitVector()) {
1676 if (Subtarget->hasVLX())
1677 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1678 EltVT == MVT::f32 || EltVT == MVT::f64)
1680 case 2: return MVT::v2i1;
1681 case 4: return MVT::v4i1;
1682 case 8: return MVT::v8i1;
1684 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1685 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1687 case 8: return MVT::v8i1;
1688 case 16: return MVT::v16i1;
1689 case 32: return MVT::v32i1;
1693 return VT.changeVectorElementTypeToInteger();
1696 /// Helper for getByValTypeAlignment to determine
1697 /// the desired ByVal argument alignment.
1698 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1701 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1702 if (VTy->getBitWidth() == 128)
1704 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1705 unsigned EltAlign = 0;
1706 getMaxByValAlign(ATy->getElementType(), EltAlign);
1707 if (EltAlign > MaxAlign)
1708 MaxAlign = EltAlign;
1709 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1710 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1711 unsigned EltAlign = 0;
1712 getMaxByValAlign(STy->getElementType(i), EltAlign);
1713 if (EltAlign > MaxAlign)
1714 MaxAlign = EltAlign;
1721 /// Return the desired alignment for ByVal aggregate
1722 /// function arguments in the caller parameter area. For X86, aggregates
1723 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1724 /// are at 4-byte boundaries.
1725 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1726 if (Subtarget->is64Bit()) {
1727 // Max of 8 and alignment of type.
1728 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1735 if (Subtarget->hasSSE1())
1736 getMaxByValAlign(Ty, Align);
1740 /// Returns the target specific optimal type for load
1741 /// and store operations as a result of memset, memcpy, and memmove
1742 /// lowering. If DstAlign is zero that means it's safe to destination
1743 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1744 /// means there isn't a need to check it against alignment requirement,
1745 /// probably because the source does not need to be loaded. If 'IsMemset' is
1746 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1747 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1748 /// source is constant so it does not need to be loaded.
1749 /// It returns EVT::Other if the type should be determined using generic
1750 /// target-independent logic.
1752 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1753 unsigned DstAlign, unsigned SrcAlign,
1754 bool IsMemset, bool ZeroMemset,
1756 MachineFunction &MF) const {
1757 const Function *F = MF.getFunction();
1758 if ((!IsMemset || ZeroMemset) &&
1759 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1761 (Subtarget->isUnalignedMemAccessFast() ||
1762 ((DstAlign == 0 || DstAlign >= 16) &&
1763 (SrcAlign == 0 || SrcAlign >= 16)))) {
1765 if (Subtarget->hasInt256())
1767 if (Subtarget->hasFp256())
1770 if (Subtarget->hasSSE2())
1772 if (Subtarget->hasSSE1())
1774 } else if (!MemcpyStrSrc && Size >= 8 &&
1775 !Subtarget->is64Bit() &&
1776 Subtarget->hasSSE2()) {
1777 // Do not use f64 to lower memcpy if source is string constant. It's
1778 // better to use i32 to avoid the loads.
1782 if (Subtarget->is64Bit() && Size >= 8)
1787 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1789 return X86ScalarSSEf32;
1790 else if (VT == MVT::f64)
1791 return X86ScalarSSEf64;
1796 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1801 *Fast = Subtarget->isUnalignedMemAccessFast();
1805 /// Return the entry encoding for a jump table in the
1806 /// current function. The returned value is a member of the
1807 /// MachineJumpTableInfo::JTEntryKind enum.
1808 unsigned X86TargetLowering::getJumpTableEncoding() const {
1809 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1811 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1812 Subtarget->isPICStyleGOT())
1813 return MachineJumpTableInfo::EK_Custom32;
1815 // Otherwise, use the normal jump table encoding heuristics.
1816 return TargetLowering::getJumpTableEncoding();
1819 bool X86TargetLowering::useSoftFloat() const {
1820 return Subtarget->useSoftFloat();
1824 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1825 const MachineBasicBlock *MBB,
1826 unsigned uid,MCContext &Ctx) const{
1827 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1828 Subtarget->isPICStyleGOT());
1829 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1831 return MCSymbolRefExpr::create(MBB->getSymbol(),
1832 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1835 /// Returns relocation base for the given PIC jumptable.
1836 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1837 SelectionDAG &DAG) const {
1838 if (!Subtarget->is64Bit())
1839 // This doesn't have SDLoc associated with it, but is not really the
1840 // same as a Register.
1841 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1845 /// This returns the relocation base for the given PIC jumptable,
1846 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1847 const MCExpr *X86TargetLowering::
1848 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1849 MCContext &Ctx) const {
1850 // X86-64 uses RIP relative addressing based on the jump table label.
1851 if (Subtarget->isPICStyleRIPRel())
1852 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1854 // Otherwise, the reference is relative to the PIC base.
1855 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
1858 std::pair<const TargetRegisterClass *, uint8_t>
1859 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1861 const TargetRegisterClass *RRC = nullptr;
1863 switch (VT.SimpleTy) {
1865 return TargetLowering::findRepresentativeClass(TRI, VT);
1866 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1867 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1870 RRC = &X86::VR64RegClass;
1872 case MVT::f32: case MVT::f64:
1873 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1874 case MVT::v4f32: case MVT::v2f64:
1875 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1877 RRC = &X86::VR128RegClass;
1880 return std::make_pair(RRC, Cost);
1883 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1884 unsigned &Offset) const {
1885 if (!Subtarget->isTargetLinux())
1888 if (Subtarget->is64Bit()) {
1889 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1891 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1903 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1904 unsigned DestAS) const {
1905 assert(SrcAS != DestAS && "Expected different address spaces!");
1907 return SrcAS < 256 && DestAS < 256;
1910 //===----------------------------------------------------------------------===//
1911 // Return Value Calling Convention Implementation
1912 //===----------------------------------------------------------------------===//
1914 #include "X86GenCallingConv.inc"
1917 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1918 MachineFunction &MF, bool isVarArg,
1919 const SmallVectorImpl<ISD::OutputArg> &Outs,
1920 LLVMContext &Context) const {
1921 SmallVector<CCValAssign, 16> RVLocs;
1922 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1923 return CCInfo.CheckReturn(Outs, RetCC_X86);
1926 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1927 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1932 X86TargetLowering::LowerReturn(SDValue Chain,
1933 CallingConv::ID CallConv, bool isVarArg,
1934 const SmallVectorImpl<ISD::OutputArg> &Outs,
1935 const SmallVectorImpl<SDValue> &OutVals,
1936 SDLoc dl, SelectionDAG &DAG) const {
1937 MachineFunction &MF = DAG.getMachineFunction();
1938 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1940 SmallVector<CCValAssign, 16> RVLocs;
1941 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1942 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1945 SmallVector<SDValue, 6> RetOps;
1946 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1947 // Operand #1 = Bytes To Pop
1948 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
1951 // Copy the result values into the output registers.
1952 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1953 CCValAssign &VA = RVLocs[i];
1954 assert(VA.isRegLoc() && "Can only return in registers!");
1955 SDValue ValToCopy = OutVals[i];
1956 EVT ValVT = ValToCopy.getValueType();
1958 // Promote values to the appropriate types.
1959 if (VA.getLocInfo() == CCValAssign::SExt)
1960 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1961 else if (VA.getLocInfo() == CCValAssign::ZExt)
1962 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1963 else if (VA.getLocInfo() == CCValAssign::AExt) {
1964 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
1965 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1967 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1969 else if (VA.getLocInfo() == CCValAssign::BCvt)
1970 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
1972 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1973 "Unexpected FP-extend for return value.");
1975 // If this is x86-64, and we disabled SSE, we can't return FP values,
1976 // or SSE or MMX vectors.
1977 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1978 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1979 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1980 report_fatal_error("SSE register return with SSE disabled");
1982 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1983 // llvm-gcc has never done it right and no one has noticed, so this
1984 // should be OK for now.
1985 if (ValVT == MVT::f64 &&
1986 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1987 report_fatal_error("SSE2 register return with SSE2 disabled");
1989 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1990 // the RET instruction and handled by the FP Stackifier.
1991 if (VA.getLocReg() == X86::FP0 ||
1992 VA.getLocReg() == X86::FP1) {
1993 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1994 // change the value to the FP stack register class.
1995 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1996 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1997 RetOps.push_back(ValToCopy);
1998 // Don't emit a copytoreg.
2002 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2003 // which is returned in RAX / RDX.
2004 if (Subtarget->is64Bit()) {
2005 if (ValVT == MVT::x86mmx) {
2006 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2007 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2008 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2010 // If we don't have SSE2 available, convert to v4f32 so the generated
2011 // register is legal.
2012 if (!Subtarget->hasSSE2())
2013 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2018 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2019 Flag = Chain.getValue(1);
2020 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2023 // All x86 ABIs require that for returning structs by value we copy
2024 // the sret argument into %rax/%eax (depending on ABI) for the return.
2025 // We saved the argument into a virtual register in the entry block,
2026 // so now we copy the value out and into %rax/%eax.
2028 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2029 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2030 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2031 // either case FuncInfo->setSRetReturnReg() will have been called.
2032 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2033 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
2036 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2037 X86::RAX : X86::EAX;
2038 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2039 Flag = Chain.getValue(1);
2041 // RAX/EAX now acts like a return value.
2042 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2045 RetOps[0] = Chain; // Update chain.
2047 // Add the flag if we have it.
2049 RetOps.push_back(Flag);
2051 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2054 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2055 if (N->getNumValues() != 1)
2057 if (!N->hasNUsesOfValue(1, 0))
2060 SDValue TCChain = Chain;
2061 SDNode *Copy = *N->use_begin();
2062 if (Copy->getOpcode() == ISD::CopyToReg) {
2063 // If the copy has a glue operand, we conservatively assume it isn't safe to
2064 // perform a tail call.
2065 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2067 TCChain = Copy->getOperand(0);
2068 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2071 bool HasRet = false;
2072 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2074 if (UI->getOpcode() != X86ISD::RET_FLAG)
2076 // If we are returning more than one value, we can definitely
2077 // not make a tail call see PR19530
2078 if (UI->getNumOperands() > 4)
2080 if (UI->getNumOperands() == 4 &&
2081 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2094 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2095 ISD::NodeType ExtendKind) const {
2097 // TODO: Is this also valid on 32-bit?
2098 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2099 ReturnMVT = MVT::i8;
2101 ReturnMVT = MVT::i32;
2103 EVT MinVT = getRegisterType(Context, ReturnMVT);
2104 return VT.bitsLT(MinVT) ? MinVT : VT;
2107 /// Lower the result values of a call into the
2108 /// appropriate copies out of appropriate physical registers.
2111 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2112 CallingConv::ID CallConv, bool isVarArg,
2113 const SmallVectorImpl<ISD::InputArg> &Ins,
2114 SDLoc dl, SelectionDAG &DAG,
2115 SmallVectorImpl<SDValue> &InVals) const {
2117 // Assign locations to each value returned by this call.
2118 SmallVector<CCValAssign, 16> RVLocs;
2119 bool Is64Bit = Subtarget->is64Bit();
2120 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2122 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2124 // Copy all of the result registers out of their specified physreg.
2125 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2126 CCValAssign &VA = RVLocs[i];
2127 EVT CopyVT = VA.getLocVT();
2129 // If this is x86-64, and we disabled SSE, we can't return FP values
2130 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2131 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2132 report_fatal_error("SSE register return with SSE disabled");
2135 // If we prefer to use the value in xmm registers, copy it out as f80 and
2136 // use a truncate to move it from fp stack reg to xmm reg.
2137 bool RoundAfterCopy = false;
2138 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2139 isScalarFPTypeInSSEReg(VA.getValVT())) {
2141 RoundAfterCopy = (CopyVT != VA.getLocVT());
2144 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2145 CopyVT, InFlag).getValue(1);
2146 SDValue Val = Chain.getValue(0);
2149 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2150 // This truncation won't change the value.
2151 DAG.getIntPtrConstant(1, dl));
2153 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2154 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2156 InFlag = Chain.getValue(2);
2157 InVals.push_back(Val);
2163 //===----------------------------------------------------------------------===//
2164 // C & StdCall & Fast Calling Convention implementation
2165 //===----------------------------------------------------------------------===//
2166 // StdCall calling convention seems to be standard for many Windows' API
2167 // routines and around. It differs from C calling convention just a little:
2168 // callee should clean up the stack, not caller. Symbols should be also
2169 // decorated in some fancy way :) It doesn't support any vector arguments.
2170 // For info on fast calling convention see Fast Calling Convention (tail call)
2171 // implementation LowerX86_32FastCCCallTo.
2173 /// CallIsStructReturn - Determines whether a call uses struct return
2175 enum StructReturnType {
2180 static StructReturnType
2181 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2183 return NotStructReturn;
2185 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2186 if (!Flags.isSRet())
2187 return NotStructReturn;
2188 if (Flags.isInReg())
2189 return RegStructReturn;
2190 return StackStructReturn;
2193 /// Determines whether a function uses struct return semantics.
2194 static StructReturnType
2195 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2197 return NotStructReturn;
2199 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2200 if (!Flags.isSRet())
2201 return NotStructReturn;
2202 if (Flags.isInReg())
2203 return RegStructReturn;
2204 return StackStructReturn;
2207 /// Make a copy of an aggregate at address specified by "Src" to address
2208 /// "Dst" with size and alignment information specified by the specific
2209 /// parameter attribute. The copy will be passed as a byval function parameter.
2211 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2212 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2214 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2216 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2217 /*isVolatile*/false, /*AlwaysInline=*/true,
2218 /*isTailCall*/false,
2219 MachinePointerInfo(), MachinePointerInfo());
2222 /// Return true if the calling convention is one that
2223 /// supports tail call optimization.
2224 static bool IsTailCallConvention(CallingConv::ID CC) {
2225 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2226 CC == CallingConv::HiPE);
2229 /// \brief Return true if the calling convention is a C calling convention.
2230 static bool IsCCallConvention(CallingConv::ID CC) {
2231 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2232 CC == CallingConv::X86_64_SysV);
2235 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2236 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2240 CallingConv::ID CalleeCC = CS.getCallingConv();
2241 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2247 /// Return true if the function is being made into
2248 /// a tailcall target by changing its ABI.
2249 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2250 bool GuaranteedTailCallOpt) {
2251 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2255 X86TargetLowering::LowerMemArgument(SDValue Chain,
2256 CallingConv::ID CallConv,
2257 const SmallVectorImpl<ISD::InputArg> &Ins,
2258 SDLoc dl, SelectionDAG &DAG,
2259 const CCValAssign &VA,
2260 MachineFrameInfo *MFI,
2262 // Create the nodes corresponding to a load from this parameter slot.
2263 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2264 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2265 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2266 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2269 // If value is passed by pointer we have address passed instead of the value
2271 bool ExtendedInMem = VA.isExtInLoc() &&
2272 VA.getValVT().getScalarType() == MVT::i1;
2274 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2275 ValVT = VA.getLocVT();
2277 ValVT = VA.getValVT();
2279 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2280 // changed with more analysis.
2281 // In case of tail call optimization mark all arguments mutable. Since they
2282 // could be overwritten by lowering of arguments in case of a tail call.
2283 if (Flags.isByVal()) {
2284 unsigned Bytes = Flags.getByValSize();
2285 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2286 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2287 return DAG.getFrameIndex(FI, getPointerTy());
2289 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2290 VA.getLocMemOffset(), isImmutable);
2291 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2292 SDValue Val = DAG.getLoad(ValVT, dl, Chain, FIN,
2293 MachinePointerInfo::getFixedStack(FI),
2294 false, false, false, 0);
2295 return ExtendedInMem ?
2296 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2300 // FIXME: Get this from tablegen.
2301 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2302 const X86Subtarget *Subtarget) {
2303 assert(Subtarget->is64Bit());
2305 if (Subtarget->isCallingConvWin64(CallConv)) {
2306 static const MCPhysReg GPR64ArgRegsWin64[] = {
2307 X86::RCX, X86::RDX, X86::R8, X86::R9
2309 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2312 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2313 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2315 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2318 // FIXME: Get this from tablegen.
2319 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2320 CallingConv::ID CallConv,
2321 const X86Subtarget *Subtarget) {
2322 assert(Subtarget->is64Bit());
2323 if (Subtarget->isCallingConvWin64(CallConv)) {
2324 // The XMM registers which might contain var arg parameters are shadowed
2325 // in their paired GPR. So we only need to save the GPR to their home
2327 // TODO: __vectorcall will change this.
2331 const Function *Fn = MF.getFunction();
2332 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2333 bool isSoftFloat = Subtarget->useSoftFloat();
2334 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2335 "SSE register cannot be used when SSE is disabled!");
2336 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2337 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2341 static const MCPhysReg XMMArgRegs64Bit[] = {
2342 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2343 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2345 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2349 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2350 CallingConv::ID CallConv,
2352 const SmallVectorImpl<ISD::InputArg> &Ins,
2355 SmallVectorImpl<SDValue> &InVals)
2357 MachineFunction &MF = DAG.getMachineFunction();
2358 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2359 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2361 const Function* Fn = MF.getFunction();
2362 if (Fn->hasExternalLinkage() &&
2363 Subtarget->isTargetCygMing() &&
2364 Fn->getName() == "main")
2365 FuncInfo->setForceFramePointer(true);
2367 MachineFrameInfo *MFI = MF.getFrameInfo();
2368 bool Is64Bit = Subtarget->is64Bit();
2369 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2371 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2372 "Var args not supported with calling convention fastcc, ghc or hipe");
2374 // Assign locations to all of the incoming arguments.
2375 SmallVector<CCValAssign, 16> ArgLocs;
2376 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2378 // Allocate shadow area for Win64
2380 CCInfo.AllocateStack(32, 8);
2382 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2384 unsigned LastVal = ~0U;
2386 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2387 CCValAssign &VA = ArgLocs[i];
2388 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2390 assert(VA.getValNo() != LastVal &&
2391 "Don't support value assigned to multiple locs yet");
2393 LastVal = VA.getValNo();
2395 if (VA.isRegLoc()) {
2396 EVT RegVT = VA.getLocVT();
2397 const TargetRegisterClass *RC;
2398 if (RegVT == MVT::i32)
2399 RC = &X86::GR32RegClass;
2400 else if (Is64Bit && RegVT == MVT::i64)
2401 RC = &X86::GR64RegClass;
2402 else if (RegVT == MVT::f32)
2403 RC = &X86::FR32RegClass;
2404 else if (RegVT == MVT::f64)
2405 RC = &X86::FR64RegClass;
2406 else if (RegVT.is512BitVector())
2407 RC = &X86::VR512RegClass;
2408 else if (RegVT.is256BitVector())
2409 RC = &X86::VR256RegClass;
2410 else if (RegVT.is128BitVector())
2411 RC = &X86::VR128RegClass;
2412 else if (RegVT == MVT::x86mmx)
2413 RC = &X86::VR64RegClass;
2414 else if (RegVT == MVT::i1)
2415 RC = &X86::VK1RegClass;
2416 else if (RegVT == MVT::v8i1)
2417 RC = &X86::VK8RegClass;
2418 else if (RegVT == MVT::v16i1)
2419 RC = &X86::VK16RegClass;
2420 else if (RegVT == MVT::v32i1)
2421 RC = &X86::VK32RegClass;
2422 else if (RegVT == MVT::v64i1)
2423 RC = &X86::VK64RegClass;
2425 llvm_unreachable("Unknown argument type!");
2427 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2428 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2430 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2431 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2433 if (VA.getLocInfo() == CCValAssign::SExt)
2434 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2435 DAG.getValueType(VA.getValVT()));
2436 else if (VA.getLocInfo() == CCValAssign::ZExt)
2437 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2438 DAG.getValueType(VA.getValVT()));
2439 else if (VA.getLocInfo() == CCValAssign::BCvt)
2440 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2442 if (VA.isExtInLoc()) {
2443 // Handle MMX values passed in XMM regs.
2444 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2445 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2447 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2450 assert(VA.isMemLoc());
2451 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2454 // If value is passed via pointer - do a load.
2455 if (VA.getLocInfo() == CCValAssign::Indirect)
2456 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2457 MachinePointerInfo(), false, false, false, 0);
2459 InVals.push_back(ArgValue);
2462 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2463 // All x86 ABIs require that for returning structs by value we copy the
2464 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2465 // the argument into a virtual register so that we can access it from the
2467 if (Ins[i].Flags.isSRet()) {
2468 unsigned Reg = FuncInfo->getSRetReturnReg();
2470 MVT PtrTy = getPointerTy();
2471 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2472 FuncInfo->setSRetReturnReg(Reg);
2474 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2475 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2480 unsigned StackSize = CCInfo.getNextStackOffset();
2481 // Align stack specially for tail calls.
2482 if (FuncIsMadeTailCallSafe(CallConv,
2483 MF.getTarget().Options.GuaranteedTailCallOpt))
2484 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2486 // If the function takes variable number of arguments, make a frame index for
2487 // the start of the first vararg value... for expansion of llvm.va_start. We
2488 // can skip this if there are no va_start calls.
2489 if (MFI->hasVAStart() &&
2490 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2491 CallConv != CallingConv::X86_ThisCall))) {
2492 FuncInfo->setVarArgsFrameIndex(
2493 MFI->CreateFixedObject(1, StackSize, true));
2496 MachineModuleInfo &MMI = MF.getMMI();
2497 const Function *WinEHParent = nullptr;
2498 if (IsWin64 && MMI.hasWinEHFuncInfo(Fn))
2499 WinEHParent = MMI.getWinEHParent(Fn);
2500 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2501 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2503 // Figure out if XMM registers are in use.
2504 assert(!(Subtarget->useSoftFloat() &&
2505 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2506 "SSE register cannot be used when SSE is disabled!");
2508 // 64-bit calling conventions support varargs and register parameters, so we
2509 // have to do extra work to spill them in the prologue.
2510 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2511 // Find the first unallocated argument registers.
2512 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2513 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2514 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2515 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2516 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2517 "SSE register cannot be used when SSE is disabled!");
2519 // Gather all the live in physical registers.
2520 SmallVector<SDValue, 6> LiveGPRs;
2521 SmallVector<SDValue, 8> LiveXMMRegs;
2523 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2524 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2526 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2528 if (!ArgXMMs.empty()) {
2529 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2530 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2531 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2532 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2533 LiveXMMRegs.push_back(
2534 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2539 // Get to the caller-allocated home save location. Add 8 to account
2540 // for the return address.
2541 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2542 FuncInfo->setRegSaveFrameIndex(
2543 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2544 // Fixup to set vararg frame on shadow area (4 x i64).
2546 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2548 // For X86-64, if there are vararg parameters that are passed via
2549 // registers, then we must store them to their spots on the stack so
2550 // they may be loaded by deferencing the result of va_next.
2551 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2552 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2553 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2554 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2557 // Store the integer parameter registers.
2558 SmallVector<SDValue, 8> MemOps;
2559 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2561 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2562 for (SDValue Val : LiveGPRs) {
2563 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2564 DAG.getIntPtrConstant(Offset, dl));
2566 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2567 MachinePointerInfo::getFixedStack(
2568 FuncInfo->getRegSaveFrameIndex(), Offset),
2570 MemOps.push_back(Store);
2574 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2575 // Now store the XMM (fp + vector) parameter registers.
2576 SmallVector<SDValue, 12> SaveXMMOps;
2577 SaveXMMOps.push_back(Chain);
2578 SaveXMMOps.push_back(ALVal);
2579 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2580 FuncInfo->getRegSaveFrameIndex(), dl));
2581 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2582 FuncInfo->getVarArgsFPOffset(), dl));
2583 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2585 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2586 MVT::Other, SaveXMMOps));
2589 if (!MemOps.empty())
2590 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2591 } else if (IsWinEHOutlined) {
2592 // Get to the caller-allocated home save location. Add 8 to account
2593 // for the return address.
2594 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2595 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2596 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2598 MMI.getWinEHFuncInfo(Fn)
2599 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2600 FuncInfo->getRegSaveFrameIndex();
2602 // Store the second integer parameter (rdx) into rsp+16 relative to the
2603 // stack pointer at the entry of the function.
2605 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), getPointerTy());
2606 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2607 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2608 Chain = DAG.getStore(
2609 Val.getValue(1), dl, Val, RSFIN,
2610 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2611 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2614 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2615 // Find the largest legal vector type.
2616 MVT VecVT = MVT::Other;
2617 // FIXME: Only some x86_32 calling conventions support AVX512.
2618 if (Subtarget->hasAVX512() &&
2619 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2620 CallConv == CallingConv::Intel_OCL_BI)))
2621 VecVT = MVT::v16f32;
2622 else if (Subtarget->hasAVX())
2624 else if (Subtarget->hasSSE2())
2627 // We forward some GPRs and some vector types.
2628 SmallVector<MVT, 2> RegParmTypes;
2629 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2630 RegParmTypes.push_back(IntVT);
2631 if (VecVT != MVT::Other)
2632 RegParmTypes.push_back(VecVT);
2634 // Compute the set of forwarded registers. The rest are scratch.
2635 SmallVectorImpl<ForwardedRegister> &Forwards =
2636 FuncInfo->getForwardedMustTailRegParms();
2637 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2639 // Conservatively forward AL on x86_64, since it might be used for varargs.
2640 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2641 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2642 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2645 // Copy all forwards from physical to virtual registers.
2646 for (ForwardedRegister &F : Forwards) {
2647 // FIXME: Can we use a less constrained schedule?
2648 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2649 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2650 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2654 // Some CCs need callee pop.
2655 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2656 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2657 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2659 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2660 // If this is an sret function, the return should pop the hidden pointer.
2661 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2662 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2663 argsAreStructReturn(Ins) == StackStructReturn)
2664 FuncInfo->setBytesToPopOnReturn(4);
2668 // RegSaveFrameIndex is X86-64 only.
2669 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2670 if (CallConv == CallingConv::X86_FastCall ||
2671 CallConv == CallingConv::X86_ThisCall)
2672 // fastcc functions can't have varargs.
2673 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2676 FuncInfo->setArgumentStackSize(StackSize);
2678 if (IsWinEHParent) {
2679 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2680 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2681 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2682 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2683 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2684 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2685 /*isVolatile=*/true,
2686 /*isNonTemporal=*/false, /*Alignment=*/0);
2693 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2694 SDValue StackPtr, SDValue Arg,
2695 SDLoc dl, SelectionDAG &DAG,
2696 const CCValAssign &VA,
2697 ISD::ArgFlagsTy Flags) const {
2698 unsigned LocMemOffset = VA.getLocMemOffset();
2699 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2700 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2701 if (Flags.isByVal())
2702 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2704 return DAG.getStore(Chain, dl, Arg, PtrOff,
2705 MachinePointerInfo::getStack(LocMemOffset),
2709 /// Emit a load of return address if tail call
2710 /// optimization is performed and it is required.
2712 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2713 SDValue &OutRetAddr, SDValue Chain,
2714 bool IsTailCall, bool Is64Bit,
2715 int FPDiff, SDLoc dl) const {
2716 // Adjust the Return address stack slot.
2717 EVT VT = getPointerTy();
2718 OutRetAddr = getReturnAddressFrameIndex(DAG);
2720 // Load the "old" Return address.
2721 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2722 false, false, false, 0);
2723 return SDValue(OutRetAddr.getNode(), 1);
2726 /// Emit a store of the return address if tail call
2727 /// optimization is performed and it is required (FPDiff!=0).
2728 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2729 SDValue Chain, SDValue RetAddrFrIdx,
2730 EVT PtrVT, unsigned SlotSize,
2731 int FPDiff, SDLoc dl) {
2732 // Store the return address to the appropriate stack slot.
2733 if (!FPDiff) return Chain;
2734 // Calculate the new stack slot for the return address.
2735 int NewReturnAddrFI =
2736 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2738 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2739 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2740 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2746 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2747 SmallVectorImpl<SDValue> &InVals) const {
2748 SelectionDAG &DAG = CLI.DAG;
2750 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2751 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2752 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2753 SDValue Chain = CLI.Chain;
2754 SDValue Callee = CLI.Callee;
2755 CallingConv::ID CallConv = CLI.CallConv;
2756 bool &isTailCall = CLI.IsTailCall;
2757 bool isVarArg = CLI.IsVarArg;
2759 MachineFunction &MF = DAG.getMachineFunction();
2760 bool Is64Bit = Subtarget->is64Bit();
2761 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2762 StructReturnType SR = callIsStructReturn(Outs);
2763 bool IsSibcall = false;
2764 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2766 if (MF.getTarget().Options.DisableTailCalls)
2769 if (Subtarget->isPICStyleGOT() &&
2770 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2771 // If we are using a GOT, disable tail calls to external symbols with
2772 // default visibility. Tail calling such a symbol requires using a GOT
2773 // relocation, which forces early binding of the symbol. This breaks code
2774 // that require lazy function symbol resolution. Using musttail or
2775 // GuaranteedTailCallOpt will override this.
2776 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2777 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2778 G->getGlobal()->hasDefaultVisibility()))
2782 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2784 // Force this to be a tail call. The verifier rules are enough to ensure
2785 // that we can lower this successfully without moving the return address
2788 } else if (isTailCall) {
2789 // Check if it's really possible to do a tail call.
2790 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2791 isVarArg, SR != NotStructReturn,
2792 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2793 Outs, OutVals, Ins, DAG);
2795 // Sibcalls are automatically detected tailcalls which do not require
2797 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2804 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2805 "Var args not supported with calling convention fastcc, ghc or hipe");
2807 // Analyze operands of the call, assigning locations to each operand.
2808 SmallVector<CCValAssign, 16> ArgLocs;
2809 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2811 // Allocate shadow area for Win64
2813 CCInfo.AllocateStack(32, 8);
2815 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2817 // Get a count of how many bytes are to be pushed on the stack.
2818 unsigned NumBytes = CCInfo.getNextStackOffset();
2820 // This is a sibcall. The memory operands are available in caller's
2821 // own caller's stack.
2823 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2824 IsTailCallConvention(CallConv))
2825 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2828 if (isTailCall && !IsSibcall && !IsMustTail) {
2829 // Lower arguments at fp - stackoffset + fpdiff.
2830 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2832 FPDiff = NumBytesCallerPushed - NumBytes;
2834 // Set the delta of movement of the returnaddr stackslot.
2835 // But only set if delta is greater than previous delta.
2836 if (FPDiff < X86Info->getTCReturnAddrDelta())
2837 X86Info->setTCReturnAddrDelta(FPDiff);
2840 unsigned NumBytesToPush = NumBytes;
2841 unsigned NumBytesToPop = NumBytes;
2843 // If we have an inalloca argument, all stack space has already been allocated
2844 // for us and be right at the top of the stack. We don't support multiple
2845 // arguments passed in memory when using inalloca.
2846 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2848 if (!ArgLocs.back().isMemLoc())
2849 report_fatal_error("cannot use inalloca attribute on a register "
2851 if (ArgLocs.back().getLocMemOffset() != 0)
2852 report_fatal_error("any parameter with the inalloca attribute must be "
2853 "the only memory argument");
2857 Chain = DAG.getCALLSEQ_START(
2858 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
2860 SDValue RetAddrFrIdx;
2861 // Load return address for tail calls.
2862 if (isTailCall && FPDiff)
2863 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2864 Is64Bit, FPDiff, dl);
2866 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2867 SmallVector<SDValue, 8> MemOpChains;
2870 // Walk the register/memloc assignments, inserting copies/loads. In the case
2871 // of tail call optimization arguments are handle later.
2872 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2873 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2874 // Skip inalloca arguments, they have already been written.
2875 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2876 if (Flags.isInAlloca())
2879 CCValAssign &VA = ArgLocs[i];
2880 EVT RegVT = VA.getLocVT();
2881 SDValue Arg = OutVals[i];
2882 bool isByVal = Flags.isByVal();
2884 // Promote the value if needed.
2885 switch (VA.getLocInfo()) {
2886 default: llvm_unreachable("Unknown loc info!");
2887 case CCValAssign::Full: break;
2888 case CCValAssign::SExt:
2889 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2891 case CCValAssign::ZExt:
2892 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2894 case CCValAssign::AExt:
2895 if (Arg.getValueType().isVector() &&
2896 Arg.getValueType().getScalarType() == MVT::i1)
2897 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2898 else if (RegVT.is128BitVector()) {
2899 // Special case: passing MMX values in XMM registers.
2900 Arg = DAG.getBitcast(MVT::i64, Arg);
2901 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2902 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2904 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2906 case CCValAssign::BCvt:
2907 Arg = DAG.getBitcast(RegVT, Arg);
2909 case CCValAssign::Indirect: {
2910 // Store the argument.
2911 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2912 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2913 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2914 MachinePointerInfo::getFixedStack(FI),
2921 if (VA.isRegLoc()) {
2922 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2923 if (isVarArg && IsWin64) {
2924 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2925 // shadow reg if callee is a varargs function.
2926 unsigned ShadowReg = 0;
2927 switch (VA.getLocReg()) {
2928 case X86::XMM0: ShadowReg = X86::RCX; break;
2929 case X86::XMM1: ShadowReg = X86::RDX; break;
2930 case X86::XMM2: ShadowReg = X86::R8; break;
2931 case X86::XMM3: ShadowReg = X86::R9; break;
2934 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2936 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2937 assert(VA.isMemLoc());
2938 if (!StackPtr.getNode())
2939 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2941 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2942 dl, DAG, VA, Flags));
2946 if (!MemOpChains.empty())
2947 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2949 if (Subtarget->isPICStyleGOT()) {
2950 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2953 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2954 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2956 // If we are tail calling and generating PIC/GOT style code load the
2957 // address of the callee into ECX. The value in ecx is used as target of
2958 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2959 // for tail calls on PIC/GOT architectures. Normally we would just put the
2960 // address of GOT into ebx and then call target@PLT. But for tail calls
2961 // ebx would be restored (since ebx is callee saved) before jumping to the
2964 // Note: The actual moving to ECX is done further down.
2965 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2966 if (G && !G->getGlobal()->hasLocalLinkage() &&
2967 G->getGlobal()->hasDefaultVisibility())
2968 Callee = LowerGlobalAddress(Callee, DAG);
2969 else if (isa<ExternalSymbolSDNode>(Callee))
2970 Callee = LowerExternalSymbol(Callee, DAG);
2974 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2975 // From AMD64 ABI document:
2976 // For calls that may call functions that use varargs or stdargs
2977 // (prototype-less calls or calls to functions containing ellipsis (...) in
2978 // the declaration) %al is used as hidden argument to specify the number
2979 // of SSE registers used. The contents of %al do not need to match exactly
2980 // the number of registers, but must be an ubound on the number of SSE
2981 // registers used and is in the range 0 - 8 inclusive.
2983 // Count the number of XMM registers allocated.
2984 static const MCPhysReg XMMArgRegs[] = {
2985 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2986 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2988 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
2989 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2990 && "SSE registers cannot be used when SSE is disabled");
2992 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2993 DAG.getConstant(NumXMMRegs, dl,
2997 if (isVarArg && IsMustTail) {
2998 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2999 for (const auto &F : Forwards) {
3000 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3001 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3005 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3006 // don't need this because the eligibility check rejects calls that require
3007 // shuffling arguments passed in memory.
3008 if (!IsSibcall && isTailCall) {
3009 // Force all the incoming stack arguments to be loaded from the stack
3010 // before any new outgoing arguments are stored to the stack, because the
3011 // outgoing stack slots may alias the incoming argument stack slots, and
3012 // the alias isn't otherwise explicit. This is slightly more conservative
3013 // than necessary, because it means that each store effectively depends
3014 // on every argument instead of just those arguments it would clobber.
3015 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3017 SmallVector<SDValue, 8> MemOpChains2;
3020 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3021 CCValAssign &VA = ArgLocs[i];
3024 assert(VA.isMemLoc());
3025 SDValue Arg = OutVals[i];
3026 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3027 // Skip inalloca arguments. They don't require any work.
3028 if (Flags.isInAlloca())
3030 // Create frame index.
3031 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3032 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3033 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3034 FIN = DAG.getFrameIndex(FI, getPointerTy());
3036 if (Flags.isByVal()) {
3037 // Copy relative to framepointer.
3038 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3039 if (!StackPtr.getNode())
3040 StackPtr = DAG.getCopyFromReg(Chain, dl,
3041 RegInfo->getStackRegister(),
3043 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3045 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3049 // Store relative to framepointer.
3050 MemOpChains2.push_back(
3051 DAG.getStore(ArgChain, dl, Arg, FIN,
3052 MachinePointerInfo::getFixedStack(FI),
3057 if (!MemOpChains2.empty())
3058 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3060 // Store the return address to the appropriate stack slot.
3061 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3062 getPointerTy(), RegInfo->getSlotSize(),
3066 // Build a sequence of copy-to-reg nodes chained together with token chain
3067 // and flag operands which copy the outgoing args into registers.
3069 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3070 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3071 RegsToPass[i].second, InFlag);
3072 InFlag = Chain.getValue(1);
3075 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3076 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3077 // In the 64-bit large code model, we have to make all calls
3078 // through a register, since the call instruction's 32-bit
3079 // pc-relative offset may not be large enough to hold the whole
3081 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3082 // If the callee is a GlobalAddress node (quite common, every direct call
3083 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3085 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3087 // We should use extra load for direct calls to dllimported functions in
3089 const GlobalValue *GV = G->getGlobal();
3090 if (!GV->hasDLLImportStorageClass()) {
3091 unsigned char OpFlags = 0;
3092 bool ExtraLoad = false;
3093 unsigned WrapperKind = ISD::DELETED_NODE;
3095 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3096 // external symbols most go through the PLT in PIC mode. If the symbol
3097 // has hidden or protected visibility, or if it is static or local, then
3098 // we don't need to use the PLT - we can directly call it.
3099 if (Subtarget->isTargetELF() &&
3100 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3101 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3102 OpFlags = X86II::MO_PLT;
3103 } else if (Subtarget->isPICStyleStubAny() &&
3104 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3105 (!Subtarget->getTargetTriple().isMacOSX() ||
3106 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3107 // PC-relative references to external symbols should go through $stub,
3108 // unless we're building with the leopard linker or later, which
3109 // automatically synthesizes these stubs.
3110 OpFlags = X86II::MO_DARWIN_STUB;
3111 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3112 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3113 // If the function is marked as non-lazy, generate an indirect call
3114 // which loads from the GOT directly. This avoids runtime overhead
3115 // at the cost of eager binding (and one extra byte of encoding).
3116 OpFlags = X86II::MO_GOTPCREL;
3117 WrapperKind = X86ISD::WrapperRIP;
3121 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3122 G->getOffset(), OpFlags);
3124 // Add a wrapper if needed.
3125 if (WrapperKind != ISD::DELETED_NODE)
3126 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3127 // Add extra indirection if needed.
3129 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3130 MachinePointerInfo::getGOT(),
3131 false, false, false, 0);
3133 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3134 unsigned char OpFlags = 0;
3136 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3137 // external symbols should go through the PLT.
3138 if (Subtarget->isTargetELF() &&
3139 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3140 OpFlags = X86II::MO_PLT;
3141 } else if (Subtarget->isPICStyleStubAny() &&
3142 (!Subtarget->getTargetTriple().isMacOSX() ||
3143 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3144 // PC-relative references to external symbols should go through $stub,
3145 // unless we're building with the leopard linker or later, which
3146 // automatically synthesizes these stubs.
3147 OpFlags = X86II::MO_DARWIN_STUB;
3150 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3152 } else if (Subtarget->isTarget64BitILP32() &&
3153 Callee->getValueType(0) == MVT::i32) {
3154 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3155 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3158 // Returns a chain & a flag for retval copy to use.
3159 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3160 SmallVector<SDValue, 8> Ops;
3162 if (!IsSibcall && isTailCall) {
3163 Chain = DAG.getCALLSEQ_END(Chain,
3164 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3165 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3166 InFlag = Chain.getValue(1);
3169 Ops.push_back(Chain);
3170 Ops.push_back(Callee);
3173 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3175 // Add argument registers to the end of the list so that they are known live
3177 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3178 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3179 RegsToPass[i].second.getValueType()));
3181 // Add a register mask operand representing the call-preserved registers.
3182 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3183 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3184 assert(Mask && "Missing call preserved mask for calling convention");
3185 Ops.push_back(DAG.getRegisterMask(Mask));
3187 if (InFlag.getNode())
3188 Ops.push_back(InFlag);
3192 //// If this is the first return lowered for this function, add the regs
3193 //// to the liveout set for the function.
3194 // This isn't right, although it's probably harmless on x86; liveouts
3195 // should be computed from returns not tail calls. Consider a void
3196 // function making a tail call to a function returning int.
3197 MF.getFrameInfo()->setHasTailCall();
3198 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3201 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3202 InFlag = Chain.getValue(1);
3204 // Create the CALLSEQ_END node.
3205 unsigned NumBytesForCalleeToPop;
3206 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3207 DAG.getTarget().Options.GuaranteedTailCallOpt))
3208 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3209 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3210 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3211 SR == StackStructReturn)
3212 // If this is a call to a struct-return function, the callee
3213 // pops the hidden struct pointer, so we have to push it back.
3214 // This is common for Darwin/X86, Linux & Mingw32 targets.
3215 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3216 NumBytesForCalleeToPop = 4;
3218 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3220 // Returns a flag for retval copy to use.
3222 Chain = DAG.getCALLSEQ_END(Chain,
3223 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3224 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3227 InFlag = Chain.getValue(1);
3230 // Handle result values, copying them out of physregs into vregs that we
3232 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3233 Ins, dl, DAG, InVals);
3236 //===----------------------------------------------------------------------===//
3237 // Fast Calling Convention (tail call) implementation
3238 //===----------------------------------------------------------------------===//
3240 // Like std call, callee cleans arguments, convention except that ECX is
3241 // reserved for storing the tail called function address. Only 2 registers are
3242 // free for argument passing (inreg). Tail call optimization is performed
3244 // * tailcallopt is enabled
3245 // * caller/callee are fastcc
3246 // On X86_64 architecture with GOT-style position independent code only local
3247 // (within module) calls are supported at the moment.
3248 // To keep the stack aligned according to platform abi the function
3249 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3250 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3251 // If a tail called function callee has more arguments than the caller the
3252 // caller needs to make sure that there is room to move the RETADDR to. This is
3253 // achieved by reserving an area the size of the argument delta right after the
3254 // original RETADDR, but before the saved framepointer or the spilled registers
3255 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3267 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3268 /// for a 16 byte align requirement.
3270 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3271 SelectionDAG& DAG) const {
3272 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3273 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3274 unsigned StackAlignment = TFI.getStackAlignment();
3275 uint64_t AlignMask = StackAlignment - 1;
3276 int64_t Offset = StackSize;
3277 unsigned SlotSize = RegInfo->getSlotSize();
3278 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3279 // Number smaller than 12 so just add the difference.
3280 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3282 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3283 Offset = ((~AlignMask) & Offset) + StackAlignment +
3284 (StackAlignment-SlotSize);
3289 /// MatchingStackOffset - Return true if the given stack call argument is
3290 /// already available in the same position (relatively) of the caller's
3291 /// incoming argument stack.
3293 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3294 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3295 const X86InstrInfo *TII) {
3296 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3298 if (Arg.getOpcode() == ISD::CopyFromReg) {
3299 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3300 if (!TargetRegisterInfo::isVirtualRegister(VR))
3302 MachineInstr *Def = MRI->getVRegDef(VR);
3305 if (!Flags.isByVal()) {
3306 if (!TII->isLoadFromStackSlot(Def, FI))
3309 unsigned Opcode = Def->getOpcode();
3310 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3311 Opcode == X86::LEA64_32r) &&
3312 Def->getOperand(1).isFI()) {
3313 FI = Def->getOperand(1).getIndex();
3314 Bytes = Flags.getByValSize();
3318 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3319 if (Flags.isByVal())
3320 // ByVal argument is passed in as a pointer but it's now being
3321 // dereferenced. e.g.
3322 // define @foo(%struct.X* %A) {
3323 // tail call @bar(%struct.X* byval %A)
3326 SDValue Ptr = Ld->getBasePtr();
3327 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3330 FI = FINode->getIndex();
3331 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3332 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3333 FI = FINode->getIndex();
3334 Bytes = Flags.getByValSize();
3338 assert(FI != INT_MAX);
3339 if (!MFI->isFixedObjectIndex(FI))
3341 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3344 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3345 /// for tail call optimization. Targets which want to do tail call
3346 /// optimization should implement this function.
3348 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3349 CallingConv::ID CalleeCC,
3351 bool isCalleeStructRet,
3352 bool isCallerStructRet,
3354 const SmallVectorImpl<ISD::OutputArg> &Outs,
3355 const SmallVectorImpl<SDValue> &OutVals,
3356 const SmallVectorImpl<ISD::InputArg> &Ins,
3357 SelectionDAG &DAG) const {
3358 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3361 // If -tailcallopt is specified, make fastcc functions tail-callable.
3362 const MachineFunction &MF = DAG.getMachineFunction();
3363 const Function *CallerF = MF.getFunction();
3365 // If the function return type is x86_fp80 and the callee return type is not,
3366 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3367 // perform a tailcall optimization here.
3368 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3371 CallingConv::ID CallerCC = CallerF->getCallingConv();
3372 bool CCMatch = CallerCC == CalleeCC;
3373 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3374 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3376 // Win64 functions have extra shadow space for argument homing. Don't do the
3377 // sibcall if the caller and callee have mismatched expectations for this
3379 if (IsCalleeWin64 != IsCallerWin64)
3382 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3383 if (IsTailCallConvention(CalleeCC) && CCMatch)
3388 // Look for obvious safe cases to perform tail call optimization that do not
3389 // require ABI changes. This is what gcc calls sibcall.
3391 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3392 // emit a special epilogue.
3393 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3394 if (RegInfo->needsStackRealignment(MF))
3397 // Also avoid sibcall optimization if either caller or callee uses struct
3398 // return semantics.
3399 if (isCalleeStructRet || isCallerStructRet)
3402 // An stdcall/thiscall caller is expected to clean up its arguments; the
3403 // callee isn't going to do that.
3404 // FIXME: this is more restrictive than needed. We could produce a tailcall
3405 // when the stack adjustment matches. For example, with a thiscall that takes
3406 // only one argument.
3407 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3408 CallerCC == CallingConv::X86_ThisCall))
3411 // Do not sibcall optimize vararg calls unless all arguments are passed via
3413 if (isVarArg && !Outs.empty()) {
3415 // Optimizing for varargs on Win64 is unlikely to be safe without
3416 // additional testing.
3417 if (IsCalleeWin64 || IsCallerWin64)
3420 SmallVector<CCValAssign, 16> ArgLocs;
3421 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3424 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3425 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3426 if (!ArgLocs[i].isRegLoc())
3430 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3431 // stack. Therefore, if it's not used by the call it is not safe to optimize
3432 // this into a sibcall.
3433 bool Unused = false;
3434 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3441 SmallVector<CCValAssign, 16> RVLocs;
3442 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3444 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3445 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3446 CCValAssign &VA = RVLocs[i];
3447 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3452 // If the calling conventions do not match, then we'd better make sure the
3453 // results are returned in the same way as what the caller expects.
3455 SmallVector<CCValAssign, 16> RVLocs1;
3456 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3458 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3460 SmallVector<CCValAssign, 16> RVLocs2;
3461 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3463 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3465 if (RVLocs1.size() != RVLocs2.size())
3467 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3468 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3470 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3472 if (RVLocs1[i].isRegLoc()) {
3473 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3476 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3482 // If the callee takes no arguments then go on to check the results of the
3484 if (!Outs.empty()) {
3485 // Check if stack adjustment is needed. For now, do not do this if any
3486 // argument is passed on the stack.
3487 SmallVector<CCValAssign, 16> ArgLocs;
3488 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3491 // Allocate shadow area for Win64
3493 CCInfo.AllocateStack(32, 8);
3495 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3496 if (CCInfo.getNextStackOffset()) {
3497 MachineFunction &MF = DAG.getMachineFunction();
3498 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3501 // Check if the arguments are already laid out in the right way as
3502 // the caller's fixed stack objects.
3503 MachineFrameInfo *MFI = MF.getFrameInfo();
3504 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3505 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3506 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3507 CCValAssign &VA = ArgLocs[i];
3508 SDValue Arg = OutVals[i];
3509 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3510 if (VA.getLocInfo() == CCValAssign::Indirect)
3512 if (!VA.isRegLoc()) {
3513 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3520 // If the tailcall address may be in a register, then make sure it's
3521 // possible to register allocate for it. In 32-bit, the call address can
3522 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3523 // callee-saved registers are restored. These happen to be the same
3524 // registers used to pass 'inreg' arguments so watch out for those.
3525 if (!Subtarget->is64Bit() &&
3526 ((!isa<GlobalAddressSDNode>(Callee) &&
3527 !isa<ExternalSymbolSDNode>(Callee)) ||
3528 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3529 unsigned NumInRegs = 0;
3530 // In PIC we need an extra register to formulate the address computation
3532 unsigned MaxInRegs =
3533 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3535 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3536 CCValAssign &VA = ArgLocs[i];
3539 unsigned Reg = VA.getLocReg();
3542 case X86::EAX: case X86::EDX: case X86::ECX:
3543 if (++NumInRegs == MaxInRegs)
3555 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3556 const TargetLibraryInfo *libInfo) const {
3557 return X86::createFastISel(funcInfo, libInfo);
3560 //===----------------------------------------------------------------------===//
3561 // Other Lowering Hooks
3562 //===----------------------------------------------------------------------===//
3564 static bool MayFoldLoad(SDValue Op) {
3565 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3568 static bool MayFoldIntoStore(SDValue Op) {
3569 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3572 static bool isTargetShuffle(unsigned Opcode) {
3574 default: return false;
3575 case X86ISD::BLENDI:
3576 case X86ISD::PSHUFB:
3577 case X86ISD::PSHUFD:
3578 case X86ISD::PSHUFHW:
3579 case X86ISD::PSHUFLW:
3581 case X86ISD::PALIGNR:
3582 case X86ISD::MOVLHPS:
3583 case X86ISD::MOVLHPD:
3584 case X86ISD::MOVHLPS:
3585 case X86ISD::MOVLPS:
3586 case X86ISD::MOVLPD:
3587 case X86ISD::MOVSHDUP:
3588 case X86ISD::MOVSLDUP:
3589 case X86ISD::MOVDDUP:
3592 case X86ISD::UNPCKL:
3593 case X86ISD::UNPCKH:
3594 case X86ISD::VPERMILPI:
3595 case X86ISD::VPERM2X128:
3596 case X86ISD::VPERMI:
3601 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3602 SDValue V1, unsigned TargetMask,
3603 SelectionDAG &DAG) {
3605 default: llvm_unreachable("Unknown x86 shuffle node");
3606 case X86ISD::PSHUFD:
3607 case X86ISD::PSHUFHW:
3608 case X86ISD::PSHUFLW:
3609 case X86ISD::VPERMILPI:
3610 case X86ISD::VPERMI:
3611 return DAG.getNode(Opc, dl, VT, V1,
3612 DAG.getConstant(TargetMask, dl, MVT::i8));
3616 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3617 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3619 default: llvm_unreachable("Unknown x86 shuffle node");
3620 case X86ISD::MOVLHPS:
3621 case X86ISD::MOVLHPD:
3622 case X86ISD::MOVHLPS:
3623 case X86ISD::MOVLPS:
3624 case X86ISD::MOVLPD:
3627 case X86ISD::UNPCKL:
3628 case X86ISD::UNPCKH:
3629 return DAG.getNode(Opc, dl, VT, V1, V2);
3633 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3634 MachineFunction &MF = DAG.getMachineFunction();
3635 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3636 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3637 int ReturnAddrIndex = FuncInfo->getRAIndex();
3639 if (ReturnAddrIndex == 0) {
3640 // Set up a frame object for the return address.
3641 unsigned SlotSize = RegInfo->getSlotSize();
3642 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3645 FuncInfo->setRAIndex(ReturnAddrIndex);
3648 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3651 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3652 bool hasSymbolicDisplacement) {
3653 // Offset should fit into 32 bit immediate field.
3654 if (!isInt<32>(Offset))
3657 // If we don't have a symbolic displacement - we don't have any extra
3659 if (!hasSymbolicDisplacement)
3662 // FIXME: Some tweaks might be needed for medium code model.
3663 if (M != CodeModel::Small && M != CodeModel::Kernel)
3666 // For small code model we assume that latest object is 16MB before end of 31
3667 // bits boundary. We may also accept pretty large negative constants knowing
3668 // that all objects are in the positive half of address space.
3669 if (M == CodeModel::Small && Offset < 16*1024*1024)
3672 // For kernel code model we know that all object resist in the negative half
3673 // of 32bits address space. We may not accept negative offsets, since they may
3674 // be just off and we may accept pretty large positive ones.
3675 if (M == CodeModel::Kernel && Offset >= 0)
3681 /// isCalleePop - Determines whether the callee is required to pop its
3682 /// own arguments. Callee pop is necessary to support tail calls.
3683 bool X86::isCalleePop(CallingConv::ID CallingConv,
3684 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3685 switch (CallingConv) {
3688 case CallingConv::X86_StdCall:
3689 case CallingConv::X86_FastCall:
3690 case CallingConv::X86_ThisCall:
3692 case CallingConv::Fast:
3693 case CallingConv::GHC:
3694 case CallingConv::HiPE:
3701 /// \brief Return true if the condition is an unsigned comparison operation.
3702 static bool isX86CCUnsigned(unsigned X86CC) {
3704 default: llvm_unreachable("Invalid integer condition!");
3705 case X86::COND_E: return true;
3706 case X86::COND_G: return false;
3707 case X86::COND_GE: return false;
3708 case X86::COND_L: return false;
3709 case X86::COND_LE: return false;
3710 case X86::COND_NE: return true;
3711 case X86::COND_B: return true;
3712 case X86::COND_A: return true;
3713 case X86::COND_BE: return true;
3714 case X86::COND_AE: return true;
3716 llvm_unreachable("covered switch fell through?!");
3719 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3720 /// specific condition code, returning the condition code and the LHS/RHS of the
3721 /// comparison to make.
3722 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3723 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3725 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3726 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3727 // X > -1 -> X == 0, jump !sign.
3728 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3729 return X86::COND_NS;
3731 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3732 // X < 0 -> X == 0, jump on sign.
3735 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3737 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3738 return X86::COND_LE;
3742 switch (SetCCOpcode) {
3743 default: llvm_unreachable("Invalid integer condition!");
3744 case ISD::SETEQ: return X86::COND_E;
3745 case ISD::SETGT: return X86::COND_G;
3746 case ISD::SETGE: return X86::COND_GE;
3747 case ISD::SETLT: return X86::COND_L;
3748 case ISD::SETLE: return X86::COND_LE;
3749 case ISD::SETNE: return X86::COND_NE;
3750 case ISD::SETULT: return X86::COND_B;
3751 case ISD::SETUGT: return X86::COND_A;
3752 case ISD::SETULE: return X86::COND_BE;
3753 case ISD::SETUGE: return X86::COND_AE;
3757 // First determine if it is required or is profitable to flip the operands.
3759 // If LHS is a foldable load, but RHS is not, flip the condition.
3760 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3761 !ISD::isNON_EXTLoad(RHS.getNode())) {
3762 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3763 std::swap(LHS, RHS);
3766 switch (SetCCOpcode) {
3772 std::swap(LHS, RHS);
3776 // On a floating point condition, the flags are set as follows:
3778 // 0 | 0 | 0 | X > Y
3779 // 0 | 0 | 1 | X < Y
3780 // 1 | 0 | 0 | X == Y
3781 // 1 | 1 | 1 | unordered
3782 switch (SetCCOpcode) {
3783 default: llvm_unreachable("Condcode should be pre-legalized away");
3785 case ISD::SETEQ: return X86::COND_E;
3786 case ISD::SETOLT: // flipped
3788 case ISD::SETGT: return X86::COND_A;
3789 case ISD::SETOLE: // flipped
3791 case ISD::SETGE: return X86::COND_AE;
3792 case ISD::SETUGT: // flipped
3794 case ISD::SETLT: return X86::COND_B;
3795 case ISD::SETUGE: // flipped
3797 case ISD::SETLE: return X86::COND_BE;
3799 case ISD::SETNE: return X86::COND_NE;
3800 case ISD::SETUO: return X86::COND_P;
3801 case ISD::SETO: return X86::COND_NP;
3803 case ISD::SETUNE: return X86::COND_INVALID;
3807 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3808 /// code. Current x86 isa includes the following FP cmov instructions:
3809 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3810 static bool hasFPCMov(unsigned X86CC) {
3826 /// isFPImmLegal - Returns true if the target can instruction select the
3827 /// specified FP immediate natively. If false, the legalizer will
3828 /// materialize the FP immediate as a load from a constant pool.
3829 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3830 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3831 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3837 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3838 ISD::LoadExtType ExtTy,
3840 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3841 // relocation target a movq or addq instruction: don't let the load shrink.
3842 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3843 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3844 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3845 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3849 /// \brief Returns true if it is beneficial to convert a load of a constant
3850 /// to just the constant itself.
3851 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3853 assert(Ty->isIntegerTy());
3855 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3856 if (BitSize == 0 || BitSize > 64)
3861 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3862 unsigned Index) const {
3863 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3866 return (Index == 0 || Index == ResVT.getVectorNumElements());
3869 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3870 // Speculate cttz only if we can directly use TZCNT.
3871 return Subtarget->hasBMI();
3874 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3875 // Speculate ctlz only if we can directly use LZCNT.
3876 return Subtarget->hasLZCNT();
3879 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3880 /// the specified range (L, H].
3881 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3882 return (Val < 0) || (Val >= Low && Val < Hi);
3885 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3886 /// specified value.
3887 static bool isUndefOrEqual(int Val, int CmpVal) {
3888 return (Val < 0 || Val == CmpVal);
3891 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3892 /// from position Pos and ending in Pos+Size, falls within the specified
3893 /// sequential range (Low, Low+Size]. or is undef.
3894 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3895 unsigned Pos, unsigned Size, int Low) {
3896 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3897 if (!isUndefOrEqual(Mask[i], Low))
3902 /// isVEXTRACTIndex - Return true if the specified
3903 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3904 /// suitable for instruction that extract 128 or 256 bit vectors
3905 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3906 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3907 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3910 // The index should be aligned on a vecWidth-bit boundary.
3912 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3914 MVT VT = N->getSimpleValueType(0);
3915 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3916 bool Result = (Index * ElSize) % vecWidth == 0;
3921 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3922 /// operand specifies a subvector insert that is suitable for input to
3923 /// insertion of 128 or 256-bit subvectors
3924 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3925 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3926 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3928 // The index should be aligned on a vecWidth-bit boundary.
3930 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3932 MVT VT = N->getSimpleValueType(0);
3933 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3934 bool Result = (Index * ElSize) % vecWidth == 0;
3939 bool X86::isVINSERT128Index(SDNode *N) {
3940 return isVINSERTIndex(N, 128);
3943 bool X86::isVINSERT256Index(SDNode *N) {
3944 return isVINSERTIndex(N, 256);
3947 bool X86::isVEXTRACT128Index(SDNode *N) {
3948 return isVEXTRACTIndex(N, 128);
3951 bool X86::isVEXTRACT256Index(SDNode *N) {
3952 return isVEXTRACTIndex(N, 256);
3955 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
3956 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3957 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3958 llvm_unreachable("Illegal extract subvector for VEXTRACT");
3961 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3963 MVT VecVT = N->getOperand(0).getSimpleValueType();
3964 MVT ElVT = VecVT.getVectorElementType();
3966 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3967 return Index / NumElemsPerChunk;
3970 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
3971 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3972 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3973 llvm_unreachable("Illegal insert subvector for VINSERT");
3976 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3978 MVT VecVT = N->getSimpleValueType(0);
3979 MVT ElVT = VecVT.getVectorElementType();
3981 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3982 return Index / NumElemsPerChunk;
3985 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
3986 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3987 /// and VINSERTI128 instructions.
3988 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
3989 return getExtractVEXTRACTImmediate(N, 128);
3992 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
3993 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
3994 /// and VINSERTI64x4 instructions.
3995 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
3996 return getExtractVEXTRACTImmediate(N, 256);
3999 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4000 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4001 /// and VINSERTI128 instructions.
4002 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4003 return getInsertVINSERTImmediate(N, 128);
4006 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4007 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4008 /// and VINSERTI64x4 instructions.
4009 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4010 return getInsertVINSERTImmediate(N, 256);
4013 /// isZero - Returns true if Elt is a constant integer zero
4014 static bool isZero(SDValue V) {
4015 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4016 return C && C->isNullValue();
4019 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4021 bool X86::isZeroNode(SDValue Elt) {
4024 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4025 return CFP->getValueAPF().isPosZero();
4029 /// getZeroVector - Returns a vector of specified type with all zero elements.
4031 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4032 SelectionDAG &DAG, SDLoc dl) {
4033 assert(VT.isVector() && "Expected a vector type");
4035 // Always build SSE zero vectors as <4 x i32> bitcasted
4036 // to their dest type. This ensures they get CSE'd.
4038 if (VT.is128BitVector()) { // SSE
4039 if (Subtarget->hasSSE2()) { // SSE2
4040 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4041 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4043 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4044 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4046 } else if (VT.is256BitVector()) { // AVX
4047 if (Subtarget->hasInt256()) { // AVX2
4048 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4049 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4050 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4052 // 256-bit logic and arithmetic instructions in AVX are all
4053 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4054 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4055 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4056 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4058 } else if (VT.is512BitVector()) { // AVX-512
4059 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4060 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4061 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4062 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4063 } else if (VT.getScalarType() == MVT::i1) {
4065 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4066 && "Unexpected vector type");
4067 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4068 && "Unexpected vector type");
4069 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4070 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4071 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4073 llvm_unreachable("Unexpected vector type");
4075 return DAG.getBitcast(VT, Vec);
4078 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4079 SelectionDAG &DAG, SDLoc dl,
4080 unsigned vectorWidth) {
4081 assert((vectorWidth == 128 || vectorWidth == 256) &&
4082 "Unsupported vector width");
4083 EVT VT = Vec.getValueType();
4084 EVT ElVT = VT.getVectorElementType();
4085 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4086 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4087 VT.getVectorNumElements()/Factor);
4089 // Extract from UNDEF is UNDEF.
4090 if (Vec.getOpcode() == ISD::UNDEF)
4091 return DAG.getUNDEF(ResultVT);
4093 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4094 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4096 // This is the index of the first element of the vectorWidth-bit chunk
4098 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4101 // If the input is a buildvector just emit a smaller one.
4102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4104 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4108 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4111 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4112 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4113 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4114 /// instructions or a simple subregister reference. Idx is an index in the
4115 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4116 /// lowering EXTRACT_VECTOR_ELT operations easier.
4117 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4118 SelectionDAG &DAG, SDLoc dl) {
4119 assert((Vec.getValueType().is256BitVector() ||
4120 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4121 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4124 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4125 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4126 SelectionDAG &DAG, SDLoc dl) {
4127 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4128 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4131 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4132 unsigned IdxVal, SelectionDAG &DAG,
4133 SDLoc dl, unsigned vectorWidth) {
4134 assert((vectorWidth == 128 || vectorWidth == 256) &&
4135 "Unsupported vector width");
4136 // Inserting UNDEF is Result
4137 if (Vec.getOpcode() == ISD::UNDEF)
4139 EVT VT = Vec.getValueType();
4140 EVT ElVT = VT.getVectorElementType();
4141 EVT ResultVT = Result.getValueType();
4143 // Insert the relevant vectorWidth bits.
4144 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4146 // This is the index of the first element of the vectorWidth-bit chunk
4148 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4151 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4152 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4155 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4156 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4157 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4158 /// simple superregister reference. Idx is an index in the 128 bits
4159 /// we want. It need not be aligned to a 128-bit boundary. That makes
4160 /// lowering INSERT_VECTOR_ELT operations easier.
4161 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4162 SelectionDAG &DAG, SDLoc dl) {
4163 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4165 // For insertion into the zero index (low half) of a 256-bit vector, it is
4166 // more efficient to generate a blend with immediate instead of an insert*128.
4167 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4168 // extend the subvector to the size of the result vector. Make sure that
4169 // we are not recursing on that node by checking for undef here.
4170 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4171 Result.getOpcode() != ISD::UNDEF) {
4172 EVT ResultVT = Result.getValueType();
4173 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4174 SDValue Undef = DAG.getUNDEF(ResultVT);
4175 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4178 // The blend instruction, and therefore its mask, depend on the data type.
4179 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4180 if (ScalarType.isFloatingPoint()) {
4181 // Choose either vblendps (float) or vblendpd (double).
4182 unsigned ScalarSize = ScalarType.getSizeInBits();
4183 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4184 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4185 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4186 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4189 const X86Subtarget &Subtarget =
4190 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4192 // AVX2 is needed for 256-bit integer blend support.
4193 // Integers must be cast to 32-bit because there is only vpblendd;
4194 // vpblendw can't be used for this because it has a handicapped mask.
4196 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4197 // is still more efficient than using the wrong domain vinsertf128 that
4198 // will be created by InsertSubVector().
4199 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4201 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4202 Vec256 = DAG.getBitcast(CastVT, Vec256);
4203 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4204 return DAG.getBitcast(ResultVT, Vec256);
4207 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4210 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4211 SelectionDAG &DAG, SDLoc dl) {
4212 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4213 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4216 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4217 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4218 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4219 /// large BUILD_VECTORS.
4220 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4221 unsigned NumElems, SelectionDAG &DAG,
4223 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4224 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4227 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4228 unsigned NumElems, SelectionDAG &DAG,
4230 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4231 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4234 /// getOnesVector - Returns a vector of specified type with all bits set.
4235 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4236 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4237 /// Then bitcast to their original type, ensuring they get CSE'd.
4238 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4240 assert(VT.isVector() && "Expected a vector type");
4242 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4244 if (VT.is256BitVector()) {
4245 if (HasInt256) { // AVX2
4246 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4247 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4249 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4250 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4252 } else if (VT.is128BitVector()) {
4253 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4255 llvm_unreachable("Unexpected vector type");
4257 return DAG.getBitcast(VT, Vec);
4260 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4261 /// operation of specified width.
4262 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4264 unsigned NumElems = VT.getVectorNumElements();
4265 SmallVector<int, 8> Mask;
4266 Mask.push_back(NumElems);
4267 for (unsigned i = 1; i != NumElems; ++i)
4269 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4272 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4273 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4275 unsigned NumElems = VT.getVectorNumElements();
4276 SmallVector<int, 8> Mask;
4277 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4279 Mask.push_back(i + NumElems);
4281 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4284 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4285 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4287 unsigned NumElems = VT.getVectorNumElements();
4288 SmallVector<int, 8> Mask;
4289 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4290 Mask.push_back(i + Half);
4291 Mask.push_back(i + NumElems + Half);
4293 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4296 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4297 /// vector of zero or undef vector. This produces a shuffle where the low
4298 /// element of V2 is swizzled into the zero/undef vector, landing at element
4299 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4300 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4302 const X86Subtarget *Subtarget,
4303 SelectionDAG &DAG) {
4304 MVT VT = V2.getSimpleValueType();
4306 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4307 unsigned NumElems = VT.getVectorNumElements();
4308 SmallVector<int, 16> MaskVec;
4309 for (unsigned i = 0; i != NumElems; ++i)
4310 // If this is the insertion idx, put the low elt of V2 here.
4311 MaskVec.push_back(i == Idx ? NumElems : i);
4312 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4315 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4316 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4317 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4318 /// shuffles which use a single input multiple times, and in those cases it will
4319 /// adjust the mask to only have indices within that single input.
4320 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4321 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4322 unsigned NumElems = VT.getVectorNumElements();
4326 bool IsFakeUnary = false;
4327 switch(N->getOpcode()) {
4328 case X86ISD::BLENDI:
4329 ImmN = N->getOperand(N->getNumOperands()-1);
4330 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4333 ImmN = N->getOperand(N->getNumOperands()-1);
4334 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4335 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4337 case X86ISD::UNPCKH:
4338 DecodeUNPCKHMask(VT, Mask);
4339 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4341 case X86ISD::UNPCKL:
4342 DecodeUNPCKLMask(VT, Mask);
4343 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4345 case X86ISD::MOVHLPS:
4346 DecodeMOVHLPSMask(NumElems, Mask);
4347 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4349 case X86ISD::MOVLHPS:
4350 DecodeMOVLHPSMask(NumElems, Mask);
4351 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4353 case X86ISD::PALIGNR:
4354 ImmN = N->getOperand(N->getNumOperands()-1);
4355 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4357 case X86ISD::PSHUFD:
4358 case X86ISD::VPERMILPI:
4359 ImmN = N->getOperand(N->getNumOperands()-1);
4360 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4363 case X86ISD::PSHUFHW:
4364 ImmN = N->getOperand(N->getNumOperands()-1);
4365 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4368 case X86ISD::PSHUFLW:
4369 ImmN = N->getOperand(N->getNumOperands()-1);
4370 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4373 case X86ISD::PSHUFB: {
4375 SDValue MaskNode = N->getOperand(1);
4376 while (MaskNode->getOpcode() == ISD::BITCAST)
4377 MaskNode = MaskNode->getOperand(0);
4379 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4380 // If we have a build-vector, then things are easy.
4381 EVT VT = MaskNode.getValueType();
4382 assert(VT.isVector() &&
4383 "Can't produce a non-vector with a build_vector!");
4384 if (!VT.isInteger())
4387 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4389 SmallVector<uint64_t, 32> RawMask;
4390 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4391 SDValue Op = MaskNode->getOperand(i);
4392 if (Op->getOpcode() == ISD::UNDEF) {
4393 RawMask.push_back((uint64_t)SM_SentinelUndef);
4396 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4399 APInt MaskElement = CN->getAPIntValue();
4401 // We now have to decode the element which could be any integer size and
4402 // extract each byte of it.
4403 for (int j = 0; j < NumBytesPerElement; ++j) {
4404 // Note that this is x86 and so always little endian: the low byte is
4405 // the first byte of the mask.
4406 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4407 MaskElement = MaskElement.lshr(8);
4410 DecodePSHUFBMask(RawMask, Mask);
4414 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4418 SDValue Ptr = MaskLoad->getBasePtr();
4419 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4420 Ptr->getOpcode() == X86ISD::WrapperRIP)
4421 Ptr = Ptr->getOperand(0);
4423 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4424 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4427 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4428 DecodePSHUFBMask(C, Mask);
4436 case X86ISD::VPERMI:
4437 ImmN = N->getOperand(N->getNumOperands()-1);
4438 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4443 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4445 case X86ISD::VPERM2X128:
4446 ImmN = N->getOperand(N->getNumOperands()-1);
4447 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4448 if (Mask.empty()) return false;
4450 case X86ISD::MOVSLDUP:
4451 DecodeMOVSLDUPMask(VT, Mask);
4454 case X86ISD::MOVSHDUP:
4455 DecodeMOVSHDUPMask(VT, Mask);
4458 case X86ISD::MOVDDUP:
4459 DecodeMOVDDUPMask(VT, Mask);
4462 case X86ISD::MOVLHPD:
4463 case X86ISD::MOVLPD:
4464 case X86ISD::MOVLPS:
4465 // Not yet implemented
4467 default: llvm_unreachable("unknown target shuffle node");
4470 // If we have a fake unary shuffle, the shuffle mask is spread across two
4471 // inputs that are actually the same node. Re-map the mask to always point
4472 // into the first input.
4475 if (M >= (int)Mask.size())
4481 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4482 /// element of the result of the vector shuffle.
4483 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4486 return SDValue(); // Limit search depth.
4488 SDValue V = SDValue(N, 0);
4489 EVT VT = V.getValueType();
4490 unsigned Opcode = V.getOpcode();
4492 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4493 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4494 int Elt = SV->getMaskElt(Index);
4497 return DAG.getUNDEF(VT.getVectorElementType());
4499 unsigned NumElems = VT.getVectorNumElements();
4500 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4501 : SV->getOperand(1);
4502 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4505 // Recurse into target specific vector shuffles to find scalars.
4506 if (isTargetShuffle(Opcode)) {
4507 MVT ShufVT = V.getSimpleValueType();
4508 unsigned NumElems = ShufVT.getVectorNumElements();
4509 SmallVector<int, 16> ShuffleMask;
4512 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4515 int Elt = ShuffleMask[Index];
4517 return DAG.getUNDEF(ShufVT.getVectorElementType());
4519 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4521 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4525 // Actual nodes that may contain scalar elements
4526 if (Opcode == ISD::BITCAST) {
4527 V = V.getOperand(0);
4528 EVT SrcVT = V.getValueType();
4529 unsigned NumElems = VT.getVectorNumElements();
4531 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4535 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4536 return (Index == 0) ? V.getOperand(0)
4537 : DAG.getUNDEF(VT.getVectorElementType());
4539 if (V.getOpcode() == ISD::BUILD_VECTOR)
4540 return V.getOperand(Index);
4545 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4547 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4548 unsigned NumNonZero, unsigned NumZero,
4550 const X86Subtarget* Subtarget,
4551 const TargetLowering &TLI) {
4559 // SSE4.1 - use PINSRB to insert each byte directly.
4560 if (Subtarget->hasSSE41()) {
4561 for (unsigned i = 0; i < 16; ++i) {
4562 bool isNonZero = (NonZeros & (1 << i)) != 0;
4566 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4568 V = DAG.getUNDEF(MVT::v16i8);
4571 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4572 MVT::v16i8, V, Op.getOperand(i),
4573 DAG.getIntPtrConstant(i, dl));
4580 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4581 for (unsigned i = 0; i < 16; ++i) {
4582 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4583 if (ThisIsNonZero && First) {
4585 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4587 V = DAG.getUNDEF(MVT::v8i16);
4592 SDValue ThisElt, LastElt;
4593 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4594 if (LastIsNonZero) {
4595 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4596 MVT::i16, Op.getOperand(i-1));
4598 if (ThisIsNonZero) {
4599 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4600 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4601 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4603 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4607 if (ThisElt.getNode())
4608 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4609 DAG.getIntPtrConstant(i/2, dl));
4613 return DAG.getBitcast(MVT::v16i8, V);
4616 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4618 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4619 unsigned NumNonZero, unsigned NumZero,
4621 const X86Subtarget* Subtarget,
4622 const TargetLowering &TLI) {
4629 for (unsigned i = 0; i < 8; ++i) {
4630 bool isNonZero = (NonZeros & (1 << i)) != 0;
4634 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4636 V = DAG.getUNDEF(MVT::v8i16);
4639 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4640 MVT::v8i16, V, Op.getOperand(i),
4641 DAG.getIntPtrConstant(i, dl));
4648 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4649 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4650 const X86Subtarget *Subtarget,
4651 const TargetLowering &TLI) {
4652 // Find all zeroable elements.
4653 std::bitset<4> Zeroable;
4654 for (int i=0; i < 4; ++i) {
4655 SDValue Elt = Op->getOperand(i);
4656 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4658 assert(Zeroable.size() - Zeroable.count() > 1 &&
4659 "We expect at least two non-zero elements!");
4661 // We only know how to deal with build_vector nodes where elements are either
4662 // zeroable or extract_vector_elt with constant index.
4663 SDValue FirstNonZero;
4664 unsigned FirstNonZeroIdx;
4665 for (unsigned i=0; i < 4; ++i) {
4668 SDValue Elt = Op->getOperand(i);
4669 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4670 !isa<ConstantSDNode>(Elt.getOperand(1)))
4672 // Make sure that this node is extracting from a 128-bit vector.
4673 MVT VT = Elt.getOperand(0).getSimpleValueType();
4674 if (!VT.is128BitVector())
4676 if (!FirstNonZero.getNode()) {
4678 FirstNonZeroIdx = i;
4682 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4683 SDValue V1 = FirstNonZero.getOperand(0);
4684 MVT VT = V1.getSimpleValueType();
4686 // See if this build_vector can be lowered as a blend with zero.
4688 unsigned EltMaskIdx, EltIdx;
4690 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4691 if (Zeroable[EltIdx]) {
4692 // The zero vector will be on the right hand side.
4693 Mask[EltIdx] = EltIdx+4;
4697 Elt = Op->getOperand(EltIdx);
4698 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4699 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4700 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4702 Mask[EltIdx] = EltIdx;
4706 // Let the shuffle legalizer deal with blend operations.
4707 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4708 if (V1.getSimpleValueType() != VT)
4709 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4710 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4713 // See if we can lower this build_vector to a INSERTPS.
4714 if (!Subtarget->hasSSE41())
4717 SDValue V2 = Elt.getOperand(0);
4718 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4721 bool CanFold = true;
4722 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4726 SDValue Current = Op->getOperand(i);
4727 SDValue SrcVector = Current->getOperand(0);
4730 CanFold = SrcVector == V1 &&
4731 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4737 assert(V1.getNode() && "Expected at least two non-zero elements!");
4738 if (V1.getSimpleValueType() != MVT::v4f32)
4739 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4740 if (V2.getSimpleValueType() != MVT::v4f32)
4741 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4743 // Ok, we can emit an INSERTPS instruction.
4744 unsigned ZMask = Zeroable.to_ulong();
4746 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4747 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4749 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
4750 DAG.getIntPtrConstant(InsertPSMask, DL));
4751 return DAG.getBitcast(VT, Result);
4754 /// Return a vector logical shift node.
4755 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4756 unsigned NumBits, SelectionDAG &DAG,
4757 const TargetLowering &TLI, SDLoc dl) {
4758 assert(VT.is128BitVector() && "Unknown type for VShift");
4759 MVT ShVT = MVT::v2i64;
4760 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4761 SrcOp = DAG.getBitcast(ShVT, SrcOp);
4762 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4763 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4764 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
4765 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4769 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4771 // Check if the scalar load can be widened into a vector load. And if
4772 // the address is "base + cst" see if the cst can be "absorbed" into
4773 // the shuffle mask.
4774 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4775 SDValue Ptr = LD->getBasePtr();
4776 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4778 EVT PVT = LD->getValueType(0);
4779 if (PVT != MVT::i32 && PVT != MVT::f32)
4784 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4785 FI = FINode->getIndex();
4787 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4788 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4789 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4790 Offset = Ptr.getConstantOperandVal(1);
4791 Ptr = Ptr.getOperand(0);
4796 // FIXME: 256-bit vector instructions don't require a strict alignment,
4797 // improve this code to support it better.
4798 unsigned RequiredAlign = VT.getSizeInBits()/8;
4799 SDValue Chain = LD->getChain();
4800 // Make sure the stack object alignment is at least 16 or 32.
4801 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4802 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4803 if (MFI->isFixedObjectIndex(FI)) {
4804 // Can't change the alignment. FIXME: It's possible to compute
4805 // the exact stack offset and reference FI + adjust offset instead.
4806 // If someone *really* cares about this. That's the way to implement it.
4809 MFI->setObjectAlignment(FI, RequiredAlign);
4813 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4814 // Ptr + (Offset & ~15).
4817 if ((Offset % RequiredAlign) & 3)
4819 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4822 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4823 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
4826 int EltNo = (Offset - StartOffset) >> 2;
4827 unsigned NumElems = VT.getVectorNumElements();
4829 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4830 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4831 LD->getPointerInfo().getWithOffset(StartOffset),
4832 false, false, false, 0);
4834 SmallVector<int, 8> Mask(NumElems, EltNo);
4836 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4842 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4843 /// elements can be replaced by a single large load which has the same value as
4844 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4846 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4848 /// FIXME: we'd also like to handle the case where the last elements are zero
4849 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4850 /// There's even a handy isZeroNode for that purpose.
4851 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4852 SDLoc &DL, SelectionDAG &DAG,
4853 bool isAfterLegalize) {
4854 unsigned NumElems = Elts.size();
4856 LoadSDNode *LDBase = nullptr;
4857 unsigned LastLoadedElt = -1U;
4859 // For each element in the initializer, see if we've found a load or an undef.
4860 // If we don't find an initial load element, or later load elements are
4861 // non-consecutive, bail out.
4862 for (unsigned i = 0; i < NumElems; ++i) {
4863 SDValue Elt = Elts[i];
4864 // Look through a bitcast.
4865 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4866 Elt = Elt.getOperand(0);
4867 if (!Elt.getNode() ||
4868 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4871 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4873 LDBase = cast<LoadSDNode>(Elt.getNode());
4877 if (Elt.getOpcode() == ISD::UNDEF)
4880 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4881 EVT LdVT = Elt.getValueType();
4882 // Each loaded element must be the correct fractional portion of the
4883 // requested vector load.
4884 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4886 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4891 // If we have found an entire vector of loads and undefs, then return a large
4892 // load of the entire vector width starting at the base pointer. If we found
4893 // consecutive loads for the low half, generate a vzext_load node.
4894 if (LastLoadedElt == NumElems - 1) {
4895 assert(LDBase && "Did not find base load for merging consecutive loads");
4896 EVT EltVT = LDBase->getValueType(0);
4897 // Ensure that the input vector size for the merged loads matches the
4898 // cumulative size of the input elements.
4899 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4902 if (isAfterLegalize &&
4903 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4906 SDValue NewLd = SDValue();
4908 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4909 LDBase->getPointerInfo(), LDBase->isVolatile(),
4910 LDBase->isNonTemporal(), LDBase->isInvariant(),
4911 LDBase->getAlignment());
4913 if (LDBase->hasAnyUseOfValue(1)) {
4914 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4916 SDValue(NewLd.getNode(), 1));
4917 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4918 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4919 SDValue(NewLd.getNode(), 1));
4925 //TODO: The code below fires only for for loading the low v2i32 / v2f32
4926 //of a v4i32 / v4f32. It's probably worth generalizing.
4927 EVT EltVT = VT.getVectorElementType();
4928 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
4929 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4930 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4931 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4933 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
4934 LDBase->getPointerInfo(),
4935 LDBase->getAlignment(),
4936 false/*isVolatile*/, true/*ReadMem*/,
4939 // Make sure the newly-created LOAD is in the same position as LDBase in
4940 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
4941 // update uses of LDBase's output chain to use the TokenFactor.
4942 if (LDBase->hasAnyUseOfValue(1)) {
4943 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4944 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
4945 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4946 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4947 SDValue(ResNode.getNode(), 1));
4950 return DAG.getBitcast(VT, ResNode);
4955 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4956 /// to generate a splat value for the following cases:
4957 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4958 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4959 /// a scalar load, or a constant.
4960 /// The VBROADCAST node is returned when a pattern is found,
4961 /// or SDValue() otherwise.
4962 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
4963 SelectionDAG &DAG) {
4964 // VBROADCAST requires AVX.
4965 // TODO: Splats could be generated for non-AVX CPUs using SSE
4966 // instructions, but there's less potential gain for only 128-bit vectors.
4967 if (!Subtarget->hasAVX())
4970 MVT VT = Op.getSimpleValueType();
4973 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
4974 "Unsupported vector type for broadcast.");
4979 switch (Op.getOpcode()) {
4981 // Unknown pattern found.
4984 case ISD::BUILD_VECTOR: {
4985 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
4986 BitVector UndefElements;
4987 SDValue Splat = BVOp->getSplatValue(&UndefElements);
4989 // We need a splat of a single value to use broadcast, and it doesn't
4990 // make any sense if the value is only in one element of the vector.
4991 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
4995 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4996 Ld.getOpcode() == ISD::ConstantFP);
4998 // Make sure that all of the users of a non-constant load are from the
4999 // BUILD_VECTOR node.
5000 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5005 case ISD::VECTOR_SHUFFLE: {
5006 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5008 // Shuffles must have a splat mask where the first element is
5010 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5013 SDValue Sc = Op.getOperand(0);
5014 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5015 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5017 if (!Subtarget->hasInt256())
5020 // Use the register form of the broadcast instruction available on AVX2.
5021 if (VT.getSizeInBits() >= 256)
5022 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5023 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5026 Ld = Sc.getOperand(0);
5027 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5028 Ld.getOpcode() == ISD::ConstantFP);
5030 // The scalar_to_vector node and the suspected
5031 // load node must have exactly one user.
5032 // Constants may have multiple users.
5034 // AVX-512 has register version of the broadcast
5035 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5036 Ld.getValueType().getSizeInBits() >= 32;
5037 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5044 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5045 bool IsGE256 = (VT.getSizeInBits() >= 256);
5047 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5048 // instruction to save 8 or more bytes of constant pool data.
5049 // TODO: If multiple splats are generated to load the same constant,
5050 // it may be detrimental to overall size. There needs to be a way to detect
5051 // that condition to know if this is truly a size win.
5052 const Function *F = DAG.getMachineFunction().getFunction();
5053 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
5055 // Handle broadcasting a single constant scalar from the constant pool
5057 // On Sandybridge (no AVX2), it is still better to load a constant vector
5058 // from the constant pool and not to broadcast it from a scalar.
5059 // But override that restriction when optimizing for size.
5060 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5061 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5062 EVT CVT = Ld.getValueType();
5063 assert(!CVT.isVector() && "Must not broadcast a vector type");
5065 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5066 // For size optimization, also splat v2f64 and v2i64, and for size opt
5067 // with AVX2, also splat i8 and i16.
5068 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5069 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5070 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5071 const Constant *C = nullptr;
5072 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5073 C = CI->getConstantIntValue();
5074 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5075 C = CF->getConstantFPValue();
5077 assert(C && "Invalid constant type");
5079 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5080 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5081 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5082 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5083 MachinePointerInfo::getConstantPool(),
5084 false, false, false, Alignment);
5086 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5090 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5092 // Handle AVX2 in-register broadcasts.
5093 if (!IsLoad && Subtarget->hasInt256() &&
5094 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5095 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5097 // The scalar source must be a normal load.
5101 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5102 (Subtarget->hasVLX() && ScalarSize == 64))
5103 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5105 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5106 // double since there is no vbroadcastsd xmm
5107 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5108 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5109 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5112 // Unsupported broadcast.
5116 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5117 /// underlying vector and index.
5119 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5121 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5123 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5124 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5127 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5129 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5131 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5132 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5135 // In this case the vector is the extract_subvector expression and the index
5136 // is 2, as specified by the shuffle.
5137 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5138 SDValue ShuffleVec = SVOp->getOperand(0);
5139 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5140 assert(ShuffleVecVT.getVectorElementType() ==
5141 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5143 int ShuffleIdx = SVOp->getMaskElt(Idx);
5144 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5145 ExtractedFromVec = ShuffleVec;
5151 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5152 MVT VT = Op.getSimpleValueType();
5154 // Skip if insert_vec_elt is not supported.
5155 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5156 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5160 unsigned NumElems = Op.getNumOperands();
5164 SmallVector<unsigned, 4> InsertIndices;
5165 SmallVector<int, 8> Mask(NumElems, -1);
5167 for (unsigned i = 0; i != NumElems; ++i) {
5168 unsigned Opc = Op.getOperand(i).getOpcode();
5170 if (Opc == ISD::UNDEF)
5173 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5174 // Quit if more than 1 elements need inserting.
5175 if (InsertIndices.size() > 1)
5178 InsertIndices.push_back(i);
5182 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5183 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5184 // Quit if non-constant index.
5185 if (!isa<ConstantSDNode>(ExtIdx))
5187 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5189 // Quit if extracted from vector of different type.
5190 if (ExtractedFromVec.getValueType() != VT)
5193 if (!VecIn1.getNode())
5194 VecIn1 = ExtractedFromVec;
5195 else if (VecIn1 != ExtractedFromVec) {
5196 if (!VecIn2.getNode())
5197 VecIn2 = ExtractedFromVec;
5198 else if (VecIn2 != ExtractedFromVec)
5199 // Quit if more than 2 vectors to shuffle
5203 if (ExtractedFromVec == VecIn1)
5205 else if (ExtractedFromVec == VecIn2)
5206 Mask[i] = Idx + NumElems;
5209 if (!VecIn1.getNode())
5212 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5213 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5214 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5215 unsigned Idx = InsertIndices[i];
5216 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5217 DAG.getIntPtrConstant(Idx, DL));
5223 static SDValue ConvertI1VectorToInterger(SDValue Op, SelectionDAG &DAG) {
5224 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5225 Op.getScalarValueSizeInBits() == 1 &&
5226 "Can not convert non-constant vector");
5227 uint64_t Immediate = 0;
5228 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5229 SDValue In = Op.getOperand(idx);
5230 if (In.getOpcode() != ISD::UNDEF)
5231 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5235 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5236 return DAG.getConstant(Immediate, dl, VT);
5238 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5240 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5242 MVT VT = Op.getSimpleValueType();
5243 assert((VT.getVectorElementType() == MVT::i1) &&
5244 "Unexpected type in LowerBUILD_VECTORvXi1!");
5247 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5248 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5249 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5250 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5253 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5254 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5255 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5256 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5259 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5260 SDValue Imm = ConvertI1VectorToInterger(Op, DAG);
5261 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5262 return DAG.getBitcast(VT, Imm);
5263 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5264 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5265 DAG.getIntPtrConstant(0, dl));
5268 // Vector has one or more non-const elements
5269 uint64_t Immediate = 0;
5270 SmallVector<unsigned, 16> NonConstIdx;
5271 bool IsSplat = true;
5272 bool HasConstElts = false;
5274 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5275 SDValue In = Op.getOperand(idx);
5276 if (In.getOpcode() == ISD::UNDEF)
5278 if (!isa<ConstantSDNode>(In))
5279 NonConstIdx.push_back(idx);
5281 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5282 HasConstElts = true;
5286 else if (In != Op.getOperand(SplatIdx))
5290 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5292 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5293 DAG.getConstant(1, dl, VT),
5294 DAG.getConstant(0, dl, VT));
5296 // insert elements one by one
5300 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5301 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5303 else if (HasConstElts)
5304 Imm = DAG.getConstant(0, dl, VT);
5306 Imm = DAG.getUNDEF(VT);
5307 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5308 DstVec = DAG.getBitcast(VT, Imm);
5310 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5311 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5312 DAG.getIntPtrConstant(0, dl));
5315 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5316 unsigned InsertIdx = NonConstIdx[i];
5317 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5318 Op.getOperand(InsertIdx),
5319 DAG.getIntPtrConstant(InsertIdx, dl));
5324 /// \brief Return true if \p N implements a horizontal binop and return the
5325 /// operands for the horizontal binop into V0 and V1.
5327 /// This is a helper function of LowerToHorizontalOp().
5328 /// This function checks that the build_vector \p N in input implements a
5329 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5330 /// operation to match.
5331 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5332 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5333 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5336 /// This function only analyzes elements of \p N whose indices are
5337 /// in range [BaseIdx, LastIdx).
5338 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5340 unsigned BaseIdx, unsigned LastIdx,
5341 SDValue &V0, SDValue &V1) {
5342 EVT VT = N->getValueType(0);
5344 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5345 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5346 "Invalid Vector in input!");
5348 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5349 bool CanFold = true;
5350 unsigned ExpectedVExtractIdx = BaseIdx;
5351 unsigned NumElts = LastIdx - BaseIdx;
5352 V0 = DAG.getUNDEF(VT);
5353 V1 = DAG.getUNDEF(VT);
5355 // Check if N implements a horizontal binop.
5356 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5357 SDValue Op = N->getOperand(i + BaseIdx);
5360 if (Op->getOpcode() == ISD::UNDEF) {
5361 // Update the expected vector extract index.
5362 if (i * 2 == NumElts)
5363 ExpectedVExtractIdx = BaseIdx;
5364 ExpectedVExtractIdx += 2;
5368 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5373 SDValue Op0 = Op.getOperand(0);
5374 SDValue Op1 = Op.getOperand(1);
5376 // Try to match the following pattern:
5377 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5378 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5379 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5380 Op0.getOperand(0) == Op1.getOperand(0) &&
5381 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5382 isa<ConstantSDNode>(Op1.getOperand(1)));
5386 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5387 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5389 if (i * 2 < NumElts) {
5390 if (V0.getOpcode() == ISD::UNDEF) {
5391 V0 = Op0.getOperand(0);
5392 if (V0.getValueType() != VT)
5396 if (V1.getOpcode() == ISD::UNDEF) {
5397 V1 = Op0.getOperand(0);
5398 if (V1.getValueType() != VT)
5401 if (i * 2 == NumElts)
5402 ExpectedVExtractIdx = BaseIdx;
5405 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5406 if (I0 == ExpectedVExtractIdx)
5407 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5408 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5409 // Try to match the following dag sequence:
5410 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5411 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5415 ExpectedVExtractIdx += 2;
5421 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5422 /// a concat_vector.
5424 /// This is a helper function of LowerToHorizontalOp().
5425 /// This function expects two 256-bit vectors called V0 and V1.
5426 /// At first, each vector is split into two separate 128-bit vectors.
5427 /// Then, the resulting 128-bit vectors are used to implement two
5428 /// horizontal binary operations.
5430 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5432 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5433 /// the two new horizontal binop.
5434 /// When Mode is set, the first horizontal binop dag node would take as input
5435 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5436 /// horizontal binop dag node would take as input the lower 128-bit of V1
5437 /// and the upper 128-bit of V1.
5439 /// HADD V0_LO, V0_HI
5440 /// HADD V1_LO, V1_HI
5442 /// Otherwise, the first horizontal binop dag node takes as input the lower
5443 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5444 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
5446 /// HADD V0_LO, V1_LO
5447 /// HADD V0_HI, V1_HI
5449 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5450 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5451 /// the upper 128-bits of the result.
5452 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5453 SDLoc DL, SelectionDAG &DAG,
5454 unsigned X86Opcode, bool Mode,
5455 bool isUndefLO, bool isUndefHI) {
5456 EVT VT = V0.getValueType();
5457 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5458 "Invalid nodes in input!");
5460 unsigned NumElts = VT.getVectorNumElements();
5461 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5462 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5463 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5464 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5465 EVT NewVT = V0_LO.getValueType();
5467 SDValue LO = DAG.getUNDEF(NewVT);
5468 SDValue HI = DAG.getUNDEF(NewVT);
5471 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5472 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5473 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5474 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5475 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5477 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5478 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5479 V1_LO->getOpcode() != ISD::UNDEF))
5480 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5482 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5483 V1_HI->getOpcode() != ISD::UNDEF))
5484 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5487 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5490 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5492 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5493 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5494 EVT VT = BV->getValueType(0);
5495 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5496 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5500 unsigned NumElts = VT.getVectorNumElements();
5501 SDValue InVec0 = DAG.getUNDEF(VT);
5502 SDValue InVec1 = DAG.getUNDEF(VT);
5504 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5505 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5507 // Odd-numbered elements in the input build vector are obtained from
5508 // adding two integer/float elements.
5509 // Even-numbered elements in the input build vector are obtained from
5510 // subtracting two integer/float elements.
5511 unsigned ExpectedOpcode = ISD::FSUB;
5512 unsigned NextExpectedOpcode = ISD::FADD;
5513 bool AddFound = false;
5514 bool SubFound = false;
5516 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5517 SDValue Op = BV->getOperand(i);
5519 // Skip 'undef' values.
5520 unsigned Opcode = Op.getOpcode();
5521 if (Opcode == ISD::UNDEF) {
5522 std::swap(ExpectedOpcode, NextExpectedOpcode);
5526 // Early exit if we found an unexpected opcode.
5527 if (Opcode != ExpectedOpcode)
5530 SDValue Op0 = Op.getOperand(0);
5531 SDValue Op1 = Op.getOperand(1);
5533 // Try to match the following pattern:
5534 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5535 // Early exit if we cannot match that sequence.
5536 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5537 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5538 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5539 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5540 Op0.getOperand(1) != Op1.getOperand(1))
5543 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5547 // We found a valid add/sub node. Update the information accordingly.
5553 // Update InVec0 and InVec1.
5554 if (InVec0.getOpcode() == ISD::UNDEF) {
5555 InVec0 = Op0.getOperand(0);
5556 if (InVec0.getValueType() != VT)
5559 if (InVec1.getOpcode() == ISD::UNDEF) {
5560 InVec1 = Op1.getOperand(0);
5561 if (InVec1.getValueType() != VT)
5565 // Make sure that operands in input to each add/sub node always
5566 // come from a same pair of vectors.
5567 if (InVec0 != Op0.getOperand(0)) {
5568 if (ExpectedOpcode == ISD::FSUB)
5571 // FADD is commutable. Try to commute the operands
5572 // and then test again.
5573 std::swap(Op0, Op1);
5574 if (InVec0 != Op0.getOperand(0))
5578 if (InVec1 != Op1.getOperand(0))
5581 // Update the pair of expected opcodes.
5582 std::swap(ExpectedOpcode, NextExpectedOpcode);
5585 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5586 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5587 InVec1.getOpcode() != ISD::UNDEF)
5588 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5593 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5594 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5595 const X86Subtarget *Subtarget,
5596 SelectionDAG &DAG) {
5597 EVT VT = BV->getValueType(0);
5598 unsigned NumElts = VT.getVectorNumElements();
5599 unsigned NumUndefsLO = 0;
5600 unsigned NumUndefsHI = 0;
5601 unsigned Half = NumElts/2;
5603 // Count the number of UNDEF operands in the build_vector in input.
5604 for (unsigned i = 0, e = Half; i != e; ++i)
5605 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5608 for (unsigned i = Half, e = NumElts; i != e; ++i)
5609 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5612 // Early exit if this is either a build_vector of all UNDEFs or all the
5613 // operands but one are UNDEF.
5614 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5618 SDValue InVec0, InVec1;
5619 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5620 // Try to match an SSE3 float HADD/HSUB.
5621 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5622 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5624 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5625 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5626 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5627 // Try to match an SSSE3 integer HADD/HSUB.
5628 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5629 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5631 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5632 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5635 if (!Subtarget->hasAVX())
5638 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5639 // Try to match an AVX horizontal add/sub of packed single/double
5640 // precision floating point values from 256-bit vectors.
5641 SDValue InVec2, InVec3;
5642 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5643 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5644 ((InVec0.getOpcode() == ISD::UNDEF ||
5645 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5646 ((InVec1.getOpcode() == ISD::UNDEF ||
5647 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5648 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5650 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5651 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5652 ((InVec0.getOpcode() == ISD::UNDEF ||
5653 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5654 ((InVec1.getOpcode() == ISD::UNDEF ||
5655 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5656 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5657 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5658 // Try to match an AVX2 horizontal add/sub of signed integers.
5659 SDValue InVec2, InVec3;
5661 bool CanFold = true;
5663 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5664 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5665 ((InVec0.getOpcode() == ISD::UNDEF ||
5666 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5667 ((InVec1.getOpcode() == ISD::UNDEF ||
5668 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5669 X86Opcode = X86ISD::HADD;
5670 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5671 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5672 ((InVec0.getOpcode() == ISD::UNDEF ||
5673 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5674 ((InVec1.getOpcode() == ISD::UNDEF ||
5675 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5676 X86Opcode = X86ISD::HSUB;
5681 // Fold this build_vector into a single horizontal add/sub.
5682 // Do this only if the target has AVX2.
5683 if (Subtarget->hasAVX2())
5684 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5686 // Do not try to expand this build_vector into a pair of horizontal
5687 // add/sub if we can emit a pair of scalar add/sub.
5688 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5691 // Convert this build_vector into a pair of horizontal binop followed by
5693 bool isUndefLO = NumUndefsLO == Half;
5694 bool isUndefHI = NumUndefsHI == Half;
5695 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5696 isUndefLO, isUndefHI);
5700 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5701 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5703 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5704 X86Opcode = X86ISD::HADD;
5705 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5706 X86Opcode = X86ISD::HSUB;
5707 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5708 X86Opcode = X86ISD::FHADD;
5709 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5710 X86Opcode = X86ISD::FHSUB;
5714 // Don't try to expand this build_vector into a pair of horizontal add/sub
5715 // if we can simply emit a pair of scalar add/sub.
5716 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5719 // Convert this build_vector into two horizontal add/sub followed by
5721 bool isUndefLO = NumUndefsLO == Half;
5722 bool isUndefHI = NumUndefsHI == Half;
5723 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5724 isUndefLO, isUndefHI);
5731 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5734 MVT VT = Op.getSimpleValueType();
5735 MVT ExtVT = VT.getVectorElementType();
5736 unsigned NumElems = Op.getNumOperands();
5738 // Generate vectors for predicate vectors.
5739 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5740 return LowerBUILD_VECTORvXi1(Op, DAG);
5742 // Vectors containing all zeros can be matched by pxor and xorps later
5743 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5744 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5745 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5746 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5749 return getZeroVector(VT, Subtarget, DAG, dl);
5752 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5753 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5754 // vpcmpeqd on 256-bit vectors.
5755 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5756 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5759 if (!VT.is512BitVector())
5760 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5763 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
5764 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
5766 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
5767 return HorizontalOp;
5768 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5771 unsigned EVTBits = ExtVT.getSizeInBits();
5773 unsigned NumZero = 0;
5774 unsigned NumNonZero = 0;
5775 unsigned NonZeros = 0;
5776 bool IsAllConstants = true;
5777 SmallSet<SDValue, 8> Values;
5778 for (unsigned i = 0; i < NumElems; ++i) {
5779 SDValue Elt = Op.getOperand(i);
5780 if (Elt.getOpcode() == ISD::UNDEF)
5783 if (Elt.getOpcode() != ISD::Constant &&
5784 Elt.getOpcode() != ISD::ConstantFP)
5785 IsAllConstants = false;
5786 if (X86::isZeroNode(Elt))
5789 NonZeros |= (1 << i);
5794 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5795 if (NumNonZero == 0)
5796 return DAG.getUNDEF(VT);
5798 // Special case for single non-zero, non-undef, element.
5799 if (NumNonZero == 1) {
5800 unsigned Idx = countTrailingZeros(NonZeros);
5801 SDValue Item = Op.getOperand(Idx);
5803 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5804 // the value are obviously zero, truncate the value to i32 and do the
5805 // insertion that way. Only do this if the value is non-constant or if the
5806 // value is a constant being inserted into element 0. It is cheaper to do
5807 // a constant pool load than it is to do a movd + shuffle.
5808 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5809 (!IsAllConstants || Idx == 0)) {
5810 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5812 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5813 EVT VecVT = MVT::v4i32;
5815 // Truncate the value (which may itself be a constant) to i32, and
5816 // convert it to a vector with movd (S2V+shuffle to zero extend).
5817 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5818 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5819 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
5820 Item, Idx * 2, true, Subtarget, DAG));
5824 // If we have a constant or non-constant insertion into the low element of
5825 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5826 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5827 // depending on what the source datatype is.
5830 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5832 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5833 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5834 if (VT.is512BitVector()) {
5835 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5836 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5837 Item, DAG.getIntPtrConstant(0, dl));
5839 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5840 "Expected an SSE value type!");
5841 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5842 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5843 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5846 // We can't directly insert an i8 or i16 into a vector, so zero extend
5848 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5849 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5850 if (VT.is256BitVector()) {
5851 if (Subtarget->hasAVX()) {
5852 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5853 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5855 // Without AVX, we need to extend to a 128-bit vector and then
5856 // insert into the 256-bit vector.
5857 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5858 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5859 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5862 assert(VT.is128BitVector() && "Expected an SSE value type!");
5863 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5864 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5866 return DAG.getBitcast(VT, Item);
5870 // Is it a vector logical left shift?
5871 if (NumElems == 2 && Idx == 1 &&
5872 X86::isZeroNode(Op.getOperand(0)) &&
5873 !X86::isZeroNode(Op.getOperand(1))) {
5874 unsigned NumBits = VT.getSizeInBits();
5875 return getVShift(true, VT,
5876 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5877 VT, Op.getOperand(1)),
5878 NumBits/2, DAG, *this, dl);
5881 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5884 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5885 // is a non-constant being inserted into an element other than the low one,
5886 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5887 // movd/movss) to move this into the low element, then shuffle it into
5889 if (EVTBits == 32) {
5890 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5891 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5895 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5896 if (Values.size() == 1) {
5897 if (EVTBits == 32) {
5898 // Instead of a shuffle like this:
5899 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5900 // Check if it's possible to issue this instead.
5901 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5902 unsigned Idx = countTrailingZeros(NonZeros);
5903 SDValue Item = Op.getOperand(Idx);
5904 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5905 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5910 // A vector full of immediates; various special cases are already
5911 // handled, so this is best done with a single constant-pool load.
5915 // For AVX-length vectors, see if we can use a vector load to get all of the
5916 // elements, otherwise build the individual 128-bit pieces and use
5917 // shuffles to put them in place.
5918 if (VT.is256BitVector() || VT.is512BitVector()) {
5919 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5921 // Check for a build vector of consecutive loads.
5922 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5925 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5927 // Build both the lower and upper subvector.
5928 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5929 makeArrayRef(&V[0], NumElems/2));
5930 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5931 makeArrayRef(&V[NumElems / 2], NumElems/2));
5933 // Recreate the wider vector with the lower and upper part.
5934 if (VT.is256BitVector())
5935 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5936 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5939 // Let legalizer expand 2-wide build_vectors.
5940 if (EVTBits == 64) {
5941 if (NumNonZero == 1) {
5942 // One half is zero or undef.
5943 unsigned Idx = countTrailingZeros(NonZeros);
5944 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5945 Op.getOperand(Idx));
5946 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5951 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5952 if (EVTBits == 8 && NumElems == 16)
5953 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5957 if (EVTBits == 16 && NumElems == 8)
5958 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5962 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
5963 if (EVTBits == 32 && NumElems == 4)
5964 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
5967 // If element VT is == 32 bits, turn it into a number of shuffles.
5968 SmallVector<SDValue, 8> V(NumElems);
5969 if (NumElems == 4 && NumZero > 0) {
5970 for (unsigned i = 0; i < 4; ++i) {
5971 bool isZero = !(NonZeros & (1 << i));
5973 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5975 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5978 for (unsigned i = 0; i < 2; ++i) {
5979 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5982 V[i] = V[i*2]; // Must be a zero vector.
5985 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5988 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5991 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5996 bool Reverse1 = (NonZeros & 0x3) == 2;
5997 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6001 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6002 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6004 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6007 if (Values.size() > 1 && VT.is128BitVector()) {
6008 // Check for a build vector of consecutive loads.
6009 for (unsigned i = 0; i < NumElems; ++i)
6010 V[i] = Op.getOperand(i);
6012 // Check for elements which are consecutive loads.
6013 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6016 // Check for a build vector from mostly shuffle plus few inserting.
6017 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6020 // For SSE 4.1, use insertps to put the high elements into the low element.
6021 if (Subtarget->hasSSE41()) {
6023 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6024 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6026 Result = DAG.getUNDEF(VT);
6028 for (unsigned i = 1; i < NumElems; ++i) {
6029 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6030 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6031 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6036 // Otherwise, expand into a number of unpckl*, start by extending each of
6037 // our (non-undef) elements to the full vector width with the element in the
6038 // bottom slot of the vector (which generates no code for SSE).
6039 for (unsigned i = 0; i < NumElems; ++i) {
6040 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6041 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6043 V[i] = DAG.getUNDEF(VT);
6046 // Next, we iteratively mix elements, e.g. for v4f32:
6047 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6048 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6049 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6050 unsigned EltStride = NumElems >> 1;
6051 while (EltStride != 0) {
6052 for (unsigned i = 0; i < EltStride; ++i) {
6053 // If V[i+EltStride] is undef and this is the first round of mixing,
6054 // then it is safe to just drop this shuffle: V[i] is already in the
6055 // right place, the one element (since it's the first round) being
6056 // inserted as undef can be dropped. This isn't safe for successive
6057 // rounds because they will permute elements within both vectors.
6058 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6059 EltStride == NumElems/2)
6062 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6071 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6072 // to create 256-bit vectors from two other 128-bit ones.
6073 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6075 MVT ResVT = Op.getSimpleValueType();
6077 assert((ResVT.is256BitVector() ||
6078 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6080 SDValue V1 = Op.getOperand(0);
6081 SDValue V2 = Op.getOperand(1);
6082 unsigned NumElems = ResVT.getVectorNumElements();
6083 if (ResVT.is256BitVector())
6084 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6086 if (Op.getNumOperands() == 4) {
6087 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6088 ResVT.getVectorNumElements()/2);
6089 SDValue V3 = Op.getOperand(2);
6090 SDValue V4 = Op.getOperand(3);
6091 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6092 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6094 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6097 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6098 const X86Subtarget *Subtarget,
6099 SelectionDAG & DAG) {
6101 MVT ResVT = Op.getSimpleValueType();
6102 unsigned NumOfOperands = Op.getNumOperands();
6104 assert(isPowerOf2_32(NumOfOperands) &&
6105 "Unexpected number of operands in CONCAT_VECTORS");
6107 if (NumOfOperands > 2) {
6108 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6109 ResVT.getVectorNumElements()/2);
6110 SmallVector<SDValue, 2> Ops;
6111 for (unsigned i = 0; i < NumOfOperands/2; i++)
6112 Ops.push_back(Op.getOperand(i));
6113 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6115 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6116 Ops.push_back(Op.getOperand(i));
6117 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6118 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6121 SDValue V1 = Op.getOperand(0);
6122 SDValue V2 = Op.getOperand(1);
6123 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6124 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6126 if (IsZeroV1 && IsZeroV2)
6127 return getZeroVector(ResVT, Subtarget, DAG, dl);
6129 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6130 SDValue Undef = DAG.getUNDEF(ResVT);
6131 unsigned NumElems = ResVT.getVectorNumElements();
6132 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6134 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6135 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6139 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6140 // Zero the upper bits of V1
6141 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6142 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6145 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6148 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6149 const X86Subtarget *Subtarget,
6150 SelectionDAG &DAG) {
6151 MVT VT = Op.getSimpleValueType();
6152 if (VT.getVectorElementType() == MVT::i1)
6153 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6155 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6156 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6157 Op.getNumOperands() == 4)));
6159 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6160 // from two other 128-bit ones.
6162 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6163 return LowerAVXCONCAT_VECTORS(Op, DAG);
6167 //===----------------------------------------------------------------------===//
6168 // Vector shuffle lowering
6170 // This is an experimental code path for lowering vector shuffles on x86. It is
6171 // designed to handle arbitrary vector shuffles and blends, gracefully
6172 // degrading performance as necessary. It works hard to recognize idiomatic
6173 // shuffles and lower them to optimal instruction patterns without leaving
6174 // a framework that allows reasonably efficient handling of all vector shuffle
6176 //===----------------------------------------------------------------------===//
6178 /// \brief Tiny helper function to identify a no-op mask.
6180 /// This is a somewhat boring predicate function. It checks whether the mask
6181 /// array input, which is assumed to be a single-input shuffle mask of the kind
6182 /// used by the X86 shuffle instructions (not a fully general
6183 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6184 /// in-place shuffle are 'no-op's.
6185 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6186 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6187 if (Mask[i] != -1 && Mask[i] != i)
6192 /// \brief Helper function to classify a mask as a single-input mask.
6194 /// This isn't a generic single-input test because in the vector shuffle
6195 /// lowering we canonicalize single inputs to be the first input operand. This
6196 /// means we can more quickly test for a single input by only checking whether
6197 /// an input from the second operand exists. We also assume that the size of
6198 /// mask corresponds to the size of the input vectors which isn't true in the
6199 /// fully general case.
6200 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6202 if (M >= (int)Mask.size())
6207 /// \brief Test whether there are elements crossing 128-bit lanes in this
6210 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6211 /// and we routinely test for these.
6212 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6213 int LaneSize = 128 / VT.getScalarSizeInBits();
6214 int Size = Mask.size();
6215 for (int i = 0; i < Size; ++i)
6216 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6221 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6223 /// This checks a shuffle mask to see if it is performing the same
6224 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6225 /// that it is also not lane-crossing. It may however involve a blend from the
6226 /// same lane of a second vector.
6228 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6229 /// non-trivial to compute in the face of undef lanes. The representation is
6230 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6231 /// entries from both V1 and V2 inputs to the wider mask.
6233 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6234 SmallVectorImpl<int> &RepeatedMask) {
6235 int LaneSize = 128 / VT.getScalarSizeInBits();
6236 RepeatedMask.resize(LaneSize, -1);
6237 int Size = Mask.size();
6238 for (int i = 0; i < Size; ++i) {
6241 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6242 // This entry crosses lanes, so there is no way to model this shuffle.
6245 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6246 if (RepeatedMask[i % LaneSize] == -1)
6247 // This is the first non-undef entry in this slot of a 128-bit lane.
6248 RepeatedMask[i % LaneSize] =
6249 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6250 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6251 // Found a mismatch with the repeated mask.
6257 /// \brief Test whether a shuffle mask is equivalent within each 256-bit lane.
6259 /// This checks a shuffle mask to see if it is performing the same
6260 /// 256-bit lane-relative shuffle in each 256-bit lane. This trivially implies
6261 /// that it is also not lane-crossing. It may however involve a blend from the
6262 /// same lane of a second vector.
6264 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6265 /// non-trivial to compute in the face of undef lanes. The representation is
6266 /// *not* suitable for use with existing 256-bit shuffles as it will contain
6267 /// entries from both V1 and V2 inputs to the wider mask.
6269 is256BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6270 SmallVectorImpl<int> &RepeatedMask) {
6271 int LaneSize = 256 / VT.getScalarSizeInBits();
6272 RepeatedMask.resize(LaneSize, -1);
6273 int Size = Mask.size();
6274 for (int i = 0; i < Size; ++i) {
6277 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6278 // This entry crosses lanes, so there is no way to model this shuffle.
6281 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6282 if (RepeatedMask[i % LaneSize] == -1)
6283 // This is the first non-undef entry in this slot of a 256-bit lane.
6284 RepeatedMask[i % LaneSize] =
6285 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6286 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6287 // Found a mismatch with the repeated mask.
6293 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6296 /// This is a fast way to test a shuffle mask against a fixed pattern:
6298 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6300 /// It returns true if the mask is exactly as wide as the argument list, and
6301 /// each element of the mask is either -1 (signifying undef) or the value given
6302 /// in the argument.
6303 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6304 ArrayRef<int> ExpectedMask) {
6305 if (Mask.size() != ExpectedMask.size())
6308 int Size = Mask.size();
6310 // If the values are build vectors, we can look through them to find
6311 // equivalent inputs that make the shuffles equivalent.
6312 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6313 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6315 for (int i = 0; i < Size; ++i)
6316 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6317 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6318 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6319 if (!MaskBV || !ExpectedBV ||
6320 MaskBV->getOperand(Mask[i] % Size) !=
6321 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6328 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6330 /// This helper function produces an 8-bit shuffle immediate corresponding to
6331 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6332 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6335 /// NB: We rely heavily on "undef" masks preserving the input lane.
6336 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6337 SelectionDAG &DAG) {
6338 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6339 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6340 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6341 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6342 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6345 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6346 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6347 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6348 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6349 return DAG.getConstant(Imm, DL, MVT::i8);
6352 /// \brief Get a 8-bit shuffle, 1 bit per lane, immediate for a mask.
6354 /// This helper function produces an 8-bit shuffle immediate corresponding to
6355 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6356 /// shuffling 8 lanes.
6357 static SDValue get1bitLaneShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6358 SelectionDAG &DAG) {
6359 assert(Mask.size() <= 8 &&
6360 "Up to 8 elts may be in Imm8 1-bit lane shuffle mask");
6362 for (unsigned i = 0; i < Mask.size(); ++i)
6363 Imm |= (Mask[i] % 2) << i;
6364 return DAG.getConstant(Imm, DL, MVT::i8);
6367 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6369 /// This is used as a fallback approach when first class blend instructions are
6370 /// unavailable. Currently it is only suitable for integer vectors, but could
6371 /// be generalized for floating point vectors if desirable.
6372 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6373 SDValue V2, ArrayRef<int> Mask,
6374 SelectionDAG &DAG) {
6375 assert(VT.isInteger() && "Only supports integer vector types!");
6376 MVT EltVT = VT.getScalarType();
6377 int NumEltBits = EltVT.getSizeInBits();
6378 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6379 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6381 SmallVector<SDValue, 16> MaskOps;
6382 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6383 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6384 return SDValue(); // Shuffled input!
6385 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6388 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6389 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6390 // We have to cast V2 around.
6391 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6392 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6393 DAG.getBitcast(MaskVT, V1Mask),
6394 DAG.getBitcast(MaskVT, V2)));
6395 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6398 /// \brief Try to emit a blend instruction for a shuffle.
6400 /// This doesn't do any checks for the availability of instructions for blending
6401 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6402 /// be matched in the backend with the type given. What it does check for is
6403 /// that the shuffle mask is in fact a blend.
6404 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6405 SDValue V2, ArrayRef<int> Mask,
6406 const X86Subtarget *Subtarget,
6407 SelectionDAG &DAG) {
6408 unsigned BlendMask = 0;
6409 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6410 if (Mask[i] >= Size) {
6411 if (Mask[i] != i + Size)
6412 return SDValue(); // Shuffled V2 input!
6413 BlendMask |= 1u << i;
6416 if (Mask[i] >= 0 && Mask[i] != i)
6417 return SDValue(); // Shuffled V1 input!
6419 switch (VT.SimpleTy) {
6424 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6425 DAG.getConstant(BlendMask, DL, MVT::i8));
6429 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6433 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6434 // that instruction.
6435 if (Subtarget->hasAVX2()) {
6436 // Scale the blend by the number of 32-bit dwords per element.
6437 int Scale = VT.getScalarSizeInBits() / 32;
6439 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6440 if (Mask[i] >= Size)
6441 for (int j = 0; j < Scale; ++j)
6442 BlendMask |= 1u << (i * Scale + j);
6444 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6445 V1 = DAG.getBitcast(BlendVT, V1);
6446 V2 = DAG.getBitcast(BlendVT, V2);
6447 return DAG.getBitcast(
6448 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6449 DAG.getConstant(BlendMask, DL, MVT::i8)));
6453 // For integer shuffles we need to expand the mask and cast the inputs to
6454 // v8i16s prior to blending.
6455 int Scale = 8 / VT.getVectorNumElements();
6457 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6458 if (Mask[i] >= Size)
6459 for (int j = 0; j < Scale; ++j)
6460 BlendMask |= 1u << (i * Scale + j);
6462 V1 = DAG.getBitcast(MVT::v8i16, V1);
6463 V2 = DAG.getBitcast(MVT::v8i16, V2);
6464 return DAG.getBitcast(VT,
6465 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6466 DAG.getConstant(BlendMask, DL, MVT::i8)));
6470 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6471 SmallVector<int, 8> RepeatedMask;
6472 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6473 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6474 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6476 for (int i = 0; i < 8; ++i)
6477 if (RepeatedMask[i] >= 16)
6478 BlendMask |= 1u << i;
6479 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6480 DAG.getConstant(BlendMask, DL, MVT::i8));
6486 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6487 "256-bit byte-blends require AVX2 support!");
6489 // Scale the blend by the number of bytes per element.
6490 int Scale = VT.getScalarSizeInBits() / 8;
6492 // This form of blend is always done on bytes. Compute the byte vector
6494 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6496 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6497 // mix of LLVM's code generator and the x86 backend. We tell the code
6498 // generator that boolean values in the elements of an x86 vector register
6499 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6500 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6501 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6502 // of the element (the remaining are ignored) and 0 in that high bit would
6503 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6504 // the LLVM model for boolean values in vector elements gets the relevant
6505 // bit set, it is set backwards and over constrained relative to x86's
6507 SmallVector<SDValue, 32> VSELECTMask;
6508 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6509 for (int j = 0; j < Scale; ++j)
6510 VSELECTMask.push_back(
6511 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6512 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6515 V1 = DAG.getBitcast(BlendVT, V1);
6516 V2 = DAG.getBitcast(BlendVT, V2);
6517 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6518 DAG.getNode(ISD::BUILD_VECTOR, DL,
6519 BlendVT, VSELECTMask),
6524 llvm_unreachable("Not a supported integer vector type!");
6528 /// \brief Try to lower as a blend of elements from two inputs followed by
6529 /// a single-input permutation.
6531 /// This matches the pattern where we can blend elements from two inputs and
6532 /// then reduce the shuffle to a single-input permutation.
6533 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6536 SelectionDAG &DAG) {
6537 // We build up the blend mask while checking whether a blend is a viable way
6538 // to reduce the shuffle.
6539 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6540 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6542 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6546 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6548 if (BlendMask[Mask[i] % Size] == -1)
6549 BlendMask[Mask[i] % Size] = Mask[i];
6550 else if (BlendMask[Mask[i] % Size] != Mask[i])
6551 return SDValue(); // Can't blend in the needed input!
6553 PermuteMask[i] = Mask[i] % Size;
6556 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6557 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6560 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6561 /// blends and permutes.
6563 /// This matches the extremely common pattern for handling combined
6564 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6565 /// operations. It will try to pick the best arrangement of shuffles and
6567 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6571 SelectionDAG &DAG) {
6572 // Shuffle the input elements into the desired positions in V1 and V2 and
6573 // blend them together.
6574 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6575 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6576 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6577 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6578 if (Mask[i] >= 0 && Mask[i] < Size) {
6579 V1Mask[i] = Mask[i];
6581 } else if (Mask[i] >= Size) {
6582 V2Mask[i] = Mask[i] - Size;
6583 BlendMask[i] = i + Size;
6586 // Try to lower with the simpler initial blend strategy unless one of the
6587 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6588 // shuffle may be able to fold with a load or other benefit. However, when
6589 // we'll have to do 2x as many shuffles in order to achieve this, blending
6590 // first is a better strategy.
6591 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6592 if (SDValue BlendPerm =
6593 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6596 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6597 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6598 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6601 /// \brief Try to lower a vector shuffle as a byte rotation.
6603 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6604 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6605 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6606 /// try to generically lower a vector shuffle through such an pattern. It
6607 /// does not check for the profitability of lowering either as PALIGNR or
6608 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6609 /// This matches shuffle vectors that look like:
6611 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6613 /// Essentially it concatenates V1 and V2, shifts right by some number of
6614 /// elements, and takes the low elements as the result. Note that while this is
6615 /// specified as a *right shift* because x86 is little-endian, it is a *left
6616 /// rotate* of the vector lanes.
6617 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6620 const X86Subtarget *Subtarget,
6621 SelectionDAG &DAG) {
6622 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6624 int NumElts = Mask.size();
6625 int NumLanes = VT.getSizeInBits() / 128;
6626 int NumLaneElts = NumElts / NumLanes;
6628 // We need to detect various ways of spelling a rotation:
6629 // [11, 12, 13, 14, 15, 0, 1, 2]
6630 // [-1, 12, 13, 14, -1, -1, 1, -1]
6631 // [-1, -1, -1, -1, -1, -1, 1, 2]
6632 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6633 // [-1, 4, 5, 6, -1, -1, 9, -1]
6634 // [-1, 4, 5, 6, -1, -1, -1, -1]
6637 for (int l = 0; l < NumElts; l += NumLaneElts) {
6638 for (int i = 0; i < NumLaneElts; ++i) {
6639 if (Mask[l + i] == -1)
6641 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6643 // Get the mod-Size index and lane correct it.
6644 int LaneIdx = (Mask[l + i] % NumElts) - l;
6645 // Make sure it was in this lane.
6646 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6649 // Determine where a rotated vector would have started.
6650 int StartIdx = i - LaneIdx;
6652 // The identity rotation isn't interesting, stop.
6655 // If we found the tail of a vector the rotation must be the missing
6656 // front. If we found the head of a vector, it must be how much of the
6658 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6661 Rotation = CandidateRotation;
6662 else if (Rotation != CandidateRotation)
6663 // The rotations don't match, so we can't match this mask.
6666 // Compute which value this mask is pointing at.
6667 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6669 // Compute which of the two target values this index should be assigned
6670 // to. This reflects whether the high elements are remaining or the low
6671 // elements are remaining.
6672 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6674 // Either set up this value if we've not encountered it before, or check
6675 // that it remains consistent.
6678 else if (TargetV != MaskV)
6679 // This may be a rotation, but it pulls from the inputs in some
6680 // unsupported interleaving.
6685 // Check that we successfully analyzed the mask, and normalize the results.
6686 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6687 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6693 // The actual rotate instruction rotates bytes, so we need to scale the
6694 // rotation based on how many bytes are in the vector lane.
6695 int Scale = 16 / NumLaneElts;
6697 // SSSE3 targets can use the palignr instruction.
6698 if (Subtarget->hasSSSE3()) {
6699 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6700 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6701 Lo = DAG.getBitcast(AlignVT, Lo);
6702 Hi = DAG.getBitcast(AlignVT, Hi);
6704 return DAG.getBitcast(
6705 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6706 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
6709 assert(VT.getSizeInBits() == 128 &&
6710 "Rotate-based lowering only supports 128-bit lowering!");
6711 assert(Mask.size() <= 16 &&
6712 "Can shuffle at most 16 bytes in a 128-bit vector!");
6714 // Default SSE2 implementation
6715 int LoByteShift = 16 - Rotation * Scale;
6716 int HiByteShift = Rotation * Scale;
6718 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6719 Lo = DAG.getBitcast(MVT::v2i64, Lo);
6720 Hi = DAG.getBitcast(MVT::v2i64, Hi);
6722 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6723 DAG.getConstant(LoByteShift, DL, MVT::i8));
6724 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6725 DAG.getConstant(HiByteShift, DL, MVT::i8));
6726 return DAG.getBitcast(VT,
6727 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6730 /// \brief Compute whether each element of a shuffle is zeroable.
6732 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6733 /// Either it is an undef element in the shuffle mask, the element of the input
6734 /// referenced is undef, or the element of the input referenced is known to be
6735 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6736 /// as many lanes with this technique as possible to simplify the remaining
6738 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6739 SDValue V1, SDValue V2) {
6740 SmallBitVector Zeroable(Mask.size(), false);
6742 while (V1.getOpcode() == ISD::BITCAST)
6743 V1 = V1->getOperand(0);
6744 while (V2.getOpcode() == ISD::BITCAST)
6745 V2 = V2->getOperand(0);
6747 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6748 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6750 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6752 // Handle the easy cases.
6753 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6758 // If this is an index into a build_vector node (which has the same number
6759 // of elements), dig out the input value and use it.
6760 SDValue V = M < Size ? V1 : V2;
6761 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6764 SDValue Input = V.getOperand(M % Size);
6765 // The UNDEF opcode check really should be dead code here, but not quite
6766 // worth asserting on (it isn't invalid, just unexpected).
6767 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6774 /// \brief Try to emit a bitmask instruction for a shuffle.
6776 /// This handles cases where we can model a blend exactly as a bitmask due to
6777 /// one of the inputs being zeroable.
6778 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6779 SDValue V2, ArrayRef<int> Mask,
6780 SelectionDAG &DAG) {
6781 MVT EltVT = VT.getScalarType();
6782 int NumEltBits = EltVT.getSizeInBits();
6783 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6784 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6785 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6787 if (EltVT.isFloatingPoint()) {
6788 Zero = DAG.getBitcast(EltVT, Zero);
6789 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6791 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6792 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6794 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6797 if (Mask[i] % Size != i)
6798 return SDValue(); // Not a blend.
6800 V = Mask[i] < Size ? V1 : V2;
6801 else if (V != (Mask[i] < Size ? V1 : V2))
6802 return SDValue(); // Can only let one input through the mask.
6804 VMaskOps[i] = AllOnes;
6807 return SDValue(); // No non-zeroable elements!
6809 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6810 V = DAG.getNode(VT.isFloatingPoint()
6811 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6816 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6818 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6819 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6820 /// matches elements from one of the input vectors shuffled to the left or
6821 /// right with zeroable elements 'shifted in'. It handles both the strictly
6822 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6825 /// PSHL : (little-endian) left bit shift.
6826 /// [ zz, 0, zz, 2 ]
6827 /// [ -1, 4, zz, -1 ]
6828 /// PSRL : (little-endian) right bit shift.
6830 /// [ -1, -1, 7, zz]
6831 /// PSLLDQ : (little-endian) left byte shift
6832 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6833 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6834 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6835 /// PSRLDQ : (little-endian) right byte shift
6836 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6837 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6838 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6839 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6840 SDValue V2, ArrayRef<int> Mask,
6841 SelectionDAG &DAG) {
6842 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6844 int Size = Mask.size();
6845 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6847 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6848 for (int i = 0; i < Size; i += Scale)
6849 for (int j = 0; j < Shift; ++j)
6850 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6856 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6857 for (int i = 0; i != Size; i += Scale) {
6858 unsigned Pos = Left ? i + Shift : i;
6859 unsigned Low = Left ? i : i + Shift;
6860 unsigned Len = Scale - Shift;
6861 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6862 Low + (V == V1 ? 0 : Size)))
6866 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6867 bool ByteShift = ShiftEltBits > 64;
6868 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6869 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6870 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6872 // Normalize the scale for byte shifts to still produce an i64 element
6874 Scale = ByteShift ? Scale / 2 : Scale;
6876 // We need to round trip through the appropriate type for the shift.
6877 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6878 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6879 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6880 "Illegal integer vector type");
6881 V = DAG.getBitcast(ShiftVT, V);
6883 V = DAG.getNode(OpCode, DL, ShiftVT, V,
6884 DAG.getConstant(ShiftAmt, DL, MVT::i8));
6885 return DAG.getBitcast(VT, V);
6888 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6889 // keep doubling the size of the integer elements up to that. We can
6890 // then shift the elements of the integer vector by whole multiples of
6891 // their width within the elements of the larger integer vector. Test each
6892 // multiple to see if we can find a match with the moved element indices
6893 // and that the shifted in elements are all zeroable.
6894 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6895 for (int Shift = 1; Shift != Scale; ++Shift)
6896 for (bool Left : {true, false})
6897 if (CheckZeros(Shift, Scale, Left))
6898 for (SDValue V : {V1, V2})
6899 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6906 /// \brief Lower a vector shuffle as a zero or any extension.
6908 /// Given a specific number of elements, element bit width, and extension
6909 /// stride, produce either a zero or any extension based on the available
6910 /// features of the subtarget.
6911 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6912 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
6913 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6914 assert(Scale > 1 && "Need a scale to extend.");
6915 int NumElements = VT.getVectorNumElements();
6916 int EltBits = VT.getScalarSizeInBits();
6917 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
6918 "Only 8, 16, and 32 bit elements can be extended.");
6919 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
6921 // Found a valid zext mask! Try various lowering strategies based on the
6922 // input type and available ISA extensions.
6923 if (Subtarget->hasSSE41()) {
6924 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
6925 NumElements / Scale);
6926 return DAG.getBitcast(VT, DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
6929 // For any extends we can cheat for larger element sizes and use shuffle
6930 // instructions that can fold with a load and/or copy.
6931 if (AnyExt && EltBits == 32) {
6932 int PSHUFDMask[4] = {0, -1, 1, -1};
6933 return DAG.getBitcast(
6934 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6935 DAG.getBitcast(MVT::v4i32, InputV),
6936 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
6938 if (AnyExt && EltBits == 16 && Scale > 2) {
6939 int PSHUFDMask[4] = {0, -1, 0, -1};
6940 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6941 DAG.getBitcast(MVT::v4i32, InputV),
6942 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
6943 int PSHUFHWMask[4] = {1, -1, -1, -1};
6944 return DAG.getBitcast(
6945 VT, DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
6946 DAG.getBitcast(MVT::v8i16, InputV),
6947 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
6950 // If this would require more than 2 unpack instructions to expand, use
6951 // pshufb when available. We can only use more than 2 unpack instructions
6952 // when zero extending i8 elements which also makes it easier to use pshufb.
6953 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
6954 assert(NumElements == 16 && "Unexpected byte vector width!");
6955 SDValue PSHUFBMask[16];
6956 for (int i = 0; i < 16; ++i)
6958 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
6959 InputV = DAG.getBitcast(MVT::v16i8, InputV);
6960 return DAG.getBitcast(VT,
6961 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
6962 DAG.getNode(ISD::BUILD_VECTOR, DL,
6963 MVT::v16i8, PSHUFBMask)));
6966 // Otherwise emit a sequence of unpacks.
6968 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
6969 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
6970 : getZeroVector(InputVT, Subtarget, DAG, DL);
6971 InputV = DAG.getBitcast(InputVT, InputV);
6972 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
6976 } while (Scale > 1);
6977 return DAG.getBitcast(VT, InputV);
6980 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
6982 /// This routine will try to do everything in its power to cleverly lower
6983 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
6984 /// check for the profitability of this lowering, it tries to aggressively
6985 /// match this pattern. It will use all of the micro-architectural details it
6986 /// can to emit an efficient lowering. It handles both blends with all-zero
6987 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
6988 /// masking out later).
6990 /// The reason we have dedicated lowering for zext-style shuffles is that they
6991 /// are both incredibly common and often quite performance sensitive.
6992 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
6993 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6994 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6995 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6997 int Bits = VT.getSizeInBits();
6998 int NumElements = VT.getVectorNumElements();
6999 assert(VT.getScalarSizeInBits() <= 32 &&
7000 "Exceeds 32-bit integer zero extension limit");
7001 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7003 // Define a helper function to check a particular ext-scale and lower to it if
7005 auto Lower = [&](int Scale) -> SDValue {
7008 for (int i = 0; i < NumElements; ++i) {
7010 continue; // Valid anywhere but doesn't tell us anything.
7011 if (i % Scale != 0) {
7012 // Each of the extended elements need to be zeroable.
7016 // We no longer are in the anyext case.
7021 // Each of the base elements needs to be consecutive indices into the
7022 // same input vector.
7023 SDValue V = Mask[i] < NumElements ? V1 : V2;
7026 else if (InputV != V)
7027 return SDValue(); // Flip-flopping inputs.
7029 if (Mask[i] % NumElements != i / Scale)
7030 return SDValue(); // Non-consecutive strided elements.
7033 // If we fail to find an input, we have a zero-shuffle which should always
7034 // have already been handled.
7035 // FIXME: Maybe handle this here in case during blending we end up with one?
7039 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7040 DL, VT, Scale, AnyExt, InputV, Subtarget, DAG);
7043 // The widest scale possible for extending is to a 64-bit integer.
7044 assert(Bits % 64 == 0 &&
7045 "The number of bits in a vector must be divisible by 64 on x86!");
7046 int NumExtElements = Bits / 64;
7048 // Each iteration, try extending the elements half as much, but into twice as
7050 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7051 assert(NumElements % NumExtElements == 0 &&
7052 "The input vector size must be divisible by the extended size.");
7053 if (SDValue V = Lower(NumElements / NumExtElements))
7057 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7061 // Returns one of the source operands if the shuffle can be reduced to a
7062 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7063 auto CanZExtLowHalf = [&]() {
7064 for (int i = NumElements / 2; i != NumElements; ++i)
7067 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7069 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7074 if (SDValue V = CanZExtLowHalf()) {
7075 V = DAG.getBitcast(MVT::v2i64, V);
7076 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7077 return DAG.getBitcast(VT, V);
7080 // No viable ext lowering found.
7084 /// \brief Try to get a scalar value for a specific element of a vector.
7086 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7087 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7088 SelectionDAG &DAG) {
7089 MVT VT = V.getSimpleValueType();
7090 MVT EltVT = VT.getVectorElementType();
7091 while (V.getOpcode() == ISD::BITCAST)
7092 V = V.getOperand(0);
7093 // If the bitcasts shift the element size, we can't extract an equivalent
7095 MVT NewVT = V.getSimpleValueType();
7096 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7099 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7100 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7101 // Ensure the scalar operand is the same size as the destination.
7102 // FIXME: Add support for scalar truncation where possible.
7103 SDValue S = V.getOperand(Idx);
7104 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7105 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7111 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7113 /// This is particularly important because the set of instructions varies
7114 /// significantly based on whether the operand is a load or not.
7115 static bool isShuffleFoldableLoad(SDValue V) {
7116 while (V.getOpcode() == ISD::BITCAST)
7117 V = V.getOperand(0);
7119 return ISD::isNON_EXTLoad(V.getNode());
7122 /// \brief Try to lower insertion of a single element into a zero vector.
7124 /// This is a common pattern that we have especially efficient patterns to lower
7125 /// across all subtarget feature sets.
7126 static SDValue lowerVectorShuffleAsElementInsertion(
7127 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7128 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7129 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7131 MVT EltVT = VT.getVectorElementType();
7133 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7134 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7136 bool IsV1Zeroable = true;
7137 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7138 if (i != V2Index && !Zeroable[i]) {
7139 IsV1Zeroable = false;
7143 // Check for a single input from a SCALAR_TO_VECTOR node.
7144 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7145 // all the smarts here sunk into that routine. However, the current
7146 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7147 // vector shuffle lowering is dead.
7148 if (SDValue V2S = getScalarValueForVectorElement(
7149 V2, Mask[V2Index] - Mask.size(), DAG)) {
7150 // We need to zext the scalar if it is smaller than an i32.
7151 V2S = DAG.getBitcast(EltVT, V2S);
7152 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7153 // Using zext to expand a narrow element won't work for non-zero
7158 // Zero-extend directly to i32.
7160 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7162 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7163 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7164 EltVT == MVT::i16) {
7165 // Either not inserting from the low element of the input or the input
7166 // element size is too small to use VZEXT_MOVL to clear the high bits.
7170 if (!IsV1Zeroable) {
7171 // If V1 can't be treated as a zero vector we have fewer options to lower
7172 // this. We can't support integer vectors or non-zero targets cheaply, and
7173 // the V1 elements can't be permuted in any way.
7174 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7175 if (!VT.isFloatingPoint() || V2Index != 0)
7177 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7178 V1Mask[V2Index] = -1;
7179 if (!isNoopShuffleMask(V1Mask))
7181 // This is essentially a special case blend operation, but if we have
7182 // general purpose blend operations, they are always faster. Bail and let
7183 // the rest of the lowering handle these as blends.
7184 if (Subtarget->hasSSE41())
7187 // Otherwise, use MOVSD or MOVSS.
7188 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7189 "Only two types of floating point element types to handle!");
7190 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7194 // This lowering only works for the low element with floating point vectors.
7195 if (VT.isFloatingPoint() && V2Index != 0)
7198 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7200 V2 = DAG.getBitcast(VT, V2);
7203 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7204 // the desired position. Otherwise it is more efficient to do a vector
7205 // shift left. We know that we can do a vector shift left because all
7206 // the inputs are zero.
7207 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7208 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7209 V2Shuffle[V2Index] = 0;
7210 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7212 V2 = DAG.getBitcast(MVT::v2i64, V2);
7214 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7216 V2Index * EltVT.getSizeInBits()/8, DL,
7217 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7218 V2 = DAG.getBitcast(VT, V2);
7224 /// \brief Try to lower broadcast of a single element.
7226 /// For convenience, this code also bundles all of the subtarget feature set
7227 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7228 /// a convenient way to factor it out.
7229 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7231 const X86Subtarget *Subtarget,
7232 SelectionDAG &DAG) {
7233 if (!Subtarget->hasAVX())
7235 if (VT.isInteger() && !Subtarget->hasAVX2())
7238 // Check that the mask is a broadcast.
7239 int BroadcastIdx = -1;
7241 if (M >= 0 && BroadcastIdx == -1)
7243 else if (M >= 0 && M != BroadcastIdx)
7246 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7247 "a sorted mask where the broadcast "
7250 // Go up the chain of (vector) values to find a scalar load that we can
7251 // combine with the broadcast.
7253 switch (V.getOpcode()) {
7254 case ISD::CONCAT_VECTORS: {
7255 int OperandSize = Mask.size() / V.getNumOperands();
7256 V = V.getOperand(BroadcastIdx / OperandSize);
7257 BroadcastIdx %= OperandSize;
7261 case ISD::INSERT_SUBVECTOR: {
7262 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7263 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7267 int BeginIdx = (int)ConstantIdx->getZExtValue();
7269 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7270 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7271 BroadcastIdx -= BeginIdx;
7282 // Check if this is a broadcast of a scalar. We special case lowering
7283 // for scalars so that we can more effectively fold with loads.
7284 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7285 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7286 V = V.getOperand(BroadcastIdx);
7288 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7289 // Only AVX2 has register broadcasts.
7290 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7292 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7293 // We can't broadcast from a vector register without AVX2, and we can only
7294 // broadcast from the zero-element of a vector register.
7298 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7301 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7302 // INSERTPS when the V1 elements are already in the correct locations
7303 // because otherwise we can just always use two SHUFPS instructions which
7304 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7305 // perform INSERTPS if a single V1 element is out of place and all V2
7306 // elements are zeroable.
7307 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7309 SelectionDAG &DAG) {
7310 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7311 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7312 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7313 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7315 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7318 int V1DstIndex = -1;
7319 int V2DstIndex = -1;
7320 bool V1UsedInPlace = false;
7322 for (int i = 0; i < 4; ++i) {
7323 // Synthesize a zero mask from the zeroable elements (includes undefs).
7329 // Flag if we use any V1 inputs in place.
7331 V1UsedInPlace = true;
7335 // We can only insert a single non-zeroable element.
7336 if (V1DstIndex != -1 || V2DstIndex != -1)
7340 // V1 input out of place for insertion.
7343 // V2 input for insertion.
7348 // Don't bother if we have no (non-zeroable) element for insertion.
7349 if (V1DstIndex == -1 && V2DstIndex == -1)
7352 // Determine element insertion src/dst indices. The src index is from the
7353 // start of the inserted vector, not the start of the concatenated vector.
7354 unsigned V2SrcIndex = 0;
7355 if (V1DstIndex != -1) {
7356 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7357 // and don't use the original V2 at all.
7358 V2SrcIndex = Mask[V1DstIndex];
7359 V2DstIndex = V1DstIndex;
7362 V2SrcIndex = Mask[V2DstIndex] - 4;
7365 // If no V1 inputs are used in place, then the result is created only from
7366 // the zero mask and the V2 insertion - so remove V1 dependency.
7368 V1 = DAG.getUNDEF(MVT::v4f32);
7370 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7371 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7373 // Insert the V2 element into the desired position.
7375 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7376 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7379 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7380 /// UNPCK instruction.
7382 /// This specifically targets cases where we end up with alternating between
7383 /// the two inputs, and so can permute them into something that feeds a single
7384 /// UNPCK instruction. Note that this routine only targets integer vectors
7385 /// because for floating point vectors we have a generalized SHUFPS lowering
7386 /// strategy that handles everything that doesn't *exactly* match an unpack,
7387 /// making this clever lowering unnecessary.
7388 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7389 SDValue V2, ArrayRef<int> Mask,
7390 SelectionDAG &DAG) {
7391 assert(!VT.isFloatingPoint() &&
7392 "This routine only supports integer vectors.");
7393 assert(!isSingleInputShuffleMask(Mask) &&
7394 "This routine should only be used when blending two inputs.");
7395 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7397 int Size = Mask.size();
7399 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7400 return M >= 0 && M % Size < Size / 2;
7402 int NumHiInputs = std::count_if(
7403 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7405 bool UnpackLo = NumLoInputs >= NumHiInputs;
7407 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7408 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7409 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7411 for (int i = 0; i < Size; ++i) {
7415 // Each element of the unpack contains Scale elements from this mask.
7416 int UnpackIdx = i / Scale;
7418 // We only handle the case where V1 feeds the first slots of the unpack.
7419 // We rely on canonicalization to ensure this is the case.
7420 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7423 // Setup the mask for this input. The indexing is tricky as we have to
7424 // handle the unpack stride.
7425 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7426 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7430 // If we will have to shuffle both inputs to use the unpack, check whether
7431 // we can just unpack first and shuffle the result. If so, skip this unpack.
7432 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7433 !isNoopShuffleMask(V2Mask))
7436 // Shuffle the inputs into place.
7437 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7438 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7440 // Cast the inputs to the type we will use to unpack them.
7441 V1 = DAG.getBitcast(UnpackVT, V1);
7442 V2 = DAG.getBitcast(UnpackVT, V2);
7444 // Unpack the inputs and cast the result back to the desired type.
7445 return DAG.getBitcast(
7446 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7450 // We try each unpack from the largest to the smallest to try and find one
7451 // that fits this mask.
7452 int OrigNumElements = VT.getVectorNumElements();
7453 int OrigScalarSize = VT.getScalarSizeInBits();
7454 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7455 int Scale = ScalarSize / OrigScalarSize;
7456 int NumElements = OrigNumElements / Scale;
7457 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7458 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7462 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7464 if (NumLoInputs == 0 || NumHiInputs == 0) {
7465 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7466 "We have to have *some* inputs!");
7467 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7469 // FIXME: We could consider the total complexity of the permute of each
7470 // possible unpacking. Or at the least we should consider how many
7471 // half-crossings are created.
7472 // FIXME: We could consider commuting the unpacks.
7474 SmallVector<int, 32> PermMask;
7475 PermMask.assign(Size, -1);
7476 for (int i = 0; i < Size; ++i) {
7480 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7483 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7485 return DAG.getVectorShuffle(
7486 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7488 DAG.getUNDEF(VT), PermMask);
7494 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7496 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7497 /// support for floating point shuffles but not integer shuffles. These
7498 /// instructions will incur a domain crossing penalty on some chips though so
7499 /// it is better to avoid lowering through this for integer vectors where
7501 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7502 const X86Subtarget *Subtarget,
7503 SelectionDAG &DAG) {
7505 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7506 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7507 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7508 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7509 ArrayRef<int> Mask = SVOp->getMask();
7510 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7512 if (isSingleInputShuffleMask(Mask)) {
7513 // Use low duplicate instructions for masks that match their pattern.
7514 if (Subtarget->hasSSE3())
7515 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7516 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7518 // Straight shuffle of a single input vector. Simulate this by using the
7519 // single input as both of the "inputs" to this instruction..
7520 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7522 if (Subtarget->hasAVX()) {
7523 // If we have AVX, we can use VPERMILPS which will allow folding a load
7524 // into the shuffle.
7525 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7526 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7529 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7530 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7532 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7533 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7535 // If we have a single input, insert that into V1 if we can do so cheaply.
7536 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7537 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7538 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7540 // Try inverting the insertion since for v2 masks it is easy to do and we
7541 // can't reliably sort the mask one way or the other.
7542 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7543 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7544 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7545 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7549 // Try to use one of the special instruction patterns to handle two common
7550 // blend patterns if a zero-blend above didn't work.
7551 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7552 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7553 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7554 // We can either use a special instruction to load over the low double or
7555 // to move just the low double.
7557 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7559 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7561 if (Subtarget->hasSSE41())
7562 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7566 // Use dedicated unpack instructions for masks that match their pattern.
7567 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7568 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7569 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7570 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7572 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7573 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
7574 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7577 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7579 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7580 /// the integer unit to minimize domain crossing penalties. However, for blends
7581 /// it falls back to the floating point shuffle operation with appropriate bit
7583 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7584 const X86Subtarget *Subtarget,
7585 SelectionDAG &DAG) {
7587 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7588 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7589 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7590 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7591 ArrayRef<int> Mask = SVOp->getMask();
7592 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7594 if (isSingleInputShuffleMask(Mask)) {
7595 // Check for being able to broadcast a single element.
7596 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7597 Mask, Subtarget, DAG))
7600 // Straight shuffle of a single input vector. For everything from SSE2
7601 // onward this has a single fast instruction with no scary immediates.
7602 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7603 V1 = DAG.getBitcast(MVT::v4i32, V1);
7604 int WidenedMask[4] = {
7605 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7606 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7607 return DAG.getBitcast(
7609 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7610 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
7612 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7613 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7614 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7615 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7617 // If we have a blend of two PACKUS operations an the blend aligns with the
7618 // low and half halves, we can just merge the PACKUS operations. This is
7619 // particularly important as it lets us merge shuffles that this routine itself
7621 auto GetPackNode = [](SDValue V) {
7622 while (V.getOpcode() == ISD::BITCAST)
7623 V = V.getOperand(0);
7625 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7627 if (SDValue V1Pack = GetPackNode(V1))
7628 if (SDValue V2Pack = GetPackNode(V2))
7629 return DAG.getBitcast(MVT::v2i64,
7630 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7631 Mask[0] == 0 ? V1Pack.getOperand(0)
7632 : V1Pack.getOperand(1),
7633 Mask[1] == 2 ? V2Pack.getOperand(0)
7634 : V2Pack.getOperand(1)));
7636 // Try to use shift instructions.
7638 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7641 // When loading a scalar and then shuffling it into a vector we can often do
7642 // the insertion cheaply.
7643 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7644 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7646 // Try inverting the insertion since for v2 masks it is easy to do and we
7647 // can't reliably sort the mask one way or the other.
7648 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7649 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7650 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7653 // We have different paths for blend lowering, but they all must use the
7654 // *exact* same predicate.
7655 bool IsBlendSupported = Subtarget->hasSSE41();
7656 if (IsBlendSupported)
7657 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7661 // Use dedicated unpack instructions for masks that match their pattern.
7662 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7663 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7664 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7665 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7667 // Try to use byte rotation instructions.
7668 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7669 if (Subtarget->hasSSSE3())
7670 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7671 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7674 // If we have direct support for blends, we should lower by decomposing into
7675 // a permute. That will be faster than the domain cross.
7676 if (IsBlendSupported)
7677 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7680 // We implement this with SHUFPD which is pretty lame because it will likely
7681 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7682 // However, all the alternatives are still more cycles and newer chips don't
7683 // have this problem. It would be really nice if x86 had better shuffles here.
7684 V1 = DAG.getBitcast(MVT::v2f64, V1);
7685 V2 = DAG.getBitcast(MVT::v2f64, V2);
7686 return DAG.getBitcast(MVT::v2i64,
7687 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7690 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7692 /// This is used to disable more specialized lowerings when the shufps lowering
7693 /// will happen to be efficient.
7694 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7695 // This routine only handles 128-bit shufps.
7696 assert(Mask.size() == 4 && "Unsupported mask size!");
7698 // To lower with a single SHUFPS we need to have the low half and high half
7699 // each requiring a single input.
7700 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7702 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7708 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7710 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7711 /// It makes no assumptions about whether this is the *best* lowering, it simply
7713 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7714 ArrayRef<int> Mask, SDValue V1,
7715 SDValue V2, SelectionDAG &DAG) {
7716 SDValue LowV = V1, HighV = V2;
7717 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7720 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7722 if (NumV2Elements == 1) {
7724 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7727 // Compute the index adjacent to V2Index and in the same half by toggling
7729 int V2AdjIndex = V2Index ^ 1;
7731 if (Mask[V2AdjIndex] == -1) {
7732 // Handles all the cases where we have a single V2 element and an undef.
7733 // This will only ever happen in the high lanes because we commute the
7734 // vector otherwise.
7736 std::swap(LowV, HighV);
7737 NewMask[V2Index] -= 4;
7739 // Handle the case where the V2 element ends up adjacent to a V1 element.
7740 // To make this work, blend them together as the first step.
7741 int V1Index = V2AdjIndex;
7742 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7743 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7744 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7746 // Now proceed to reconstruct the final blend as we have the necessary
7747 // high or low half formed.
7754 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7755 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7757 } else if (NumV2Elements == 2) {
7758 if (Mask[0] < 4 && Mask[1] < 4) {
7759 // Handle the easy case where we have V1 in the low lanes and V2 in the
7763 } else if (Mask[2] < 4 && Mask[3] < 4) {
7764 // We also handle the reversed case because this utility may get called
7765 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7766 // arrange things in the right direction.
7772 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7773 // trying to place elements directly, just blend them and set up the final
7774 // shuffle to place them.
7776 // The first two blend mask elements are for V1, the second two are for
7778 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7779 Mask[2] < 4 ? Mask[2] : Mask[3],
7780 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7781 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7782 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7783 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7785 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7788 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7789 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7790 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7791 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7794 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7795 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
7798 /// \brief Lower 4-lane 32-bit floating point shuffles.
7800 /// Uses instructions exclusively from the floating point unit to minimize
7801 /// domain crossing penalties, as these are sufficient to implement all v4f32
7803 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7804 const X86Subtarget *Subtarget,
7805 SelectionDAG &DAG) {
7807 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7808 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7809 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7810 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7811 ArrayRef<int> Mask = SVOp->getMask();
7812 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7815 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7817 if (NumV2Elements == 0) {
7818 // Check for being able to broadcast a single element.
7819 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
7820 Mask, Subtarget, DAG))
7823 // Use even/odd duplicate instructions for masks that match their pattern.
7824 if (Subtarget->hasSSE3()) {
7825 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
7826 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
7827 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
7828 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
7831 if (Subtarget->hasAVX()) {
7832 // If we have AVX, we can use VPERMILPS which will allow folding a load
7833 // into the shuffle.
7834 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7835 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7838 // Otherwise, use a straight shuffle of a single input vector. We pass the
7839 // input vector to both operands to simulate this with a SHUFPS.
7840 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7841 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7844 // There are special ways we can lower some single-element blends. However, we
7845 // have custom ways we can lower more complex single-element blends below that
7846 // we defer to if both this and BLENDPS fail to match, so restrict this to
7847 // when the V2 input is targeting element 0 of the mask -- that is the fast
7849 if (NumV2Elements == 1 && Mask[0] >= 4)
7850 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
7851 Mask, Subtarget, DAG))
7854 if (Subtarget->hasSSE41()) {
7855 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7859 // Use INSERTPS if we can complete the shuffle efficiently.
7860 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
7863 if (!isSingleSHUFPSMask(Mask))
7864 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
7865 DL, MVT::v4f32, V1, V2, Mask, DAG))
7869 // Use dedicated unpack instructions for masks that match their pattern.
7870 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7871 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7872 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7873 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7874 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7875 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
7876 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7877 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
7879 // Otherwise fall back to a SHUFPS lowering strategy.
7880 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7883 /// \brief Lower 4-lane i32 vector shuffles.
7885 /// We try to handle these with integer-domain shuffles where we can, but for
7886 /// blends we use the floating point domain blend instructions.
7887 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7888 const X86Subtarget *Subtarget,
7889 SelectionDAG &DAG) {
7891 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7892 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7893 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7894 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7895 ArrayRef<int> Mask = SVOp->getMask();
7896 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7898 // Whenever we can lower this as a zext, that instruction is strictly faster
7899 // than any alternative. It also allows us to fold memory operands into the
7900 // shuffle in many cases.
7901 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7902 Mask, Subtarget, DAG))
7906 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7908 if (NumV2Elements == 0) {
7909 // Check for being able to broadcast a single element.
7910 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
7911 Mask, Subtarget, DAG))
7914 // Straight shuffle of a single input vector. For everything from SSE2
7915 // onward this has a single fast instruction with no scary immediates.
7916 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7917 // but we aren't actually going to use the UNPCK instruction because doing
7918 // so prevents folding a load into this instruction or making a copy.
7919 const int UnpackLoMask[] = {0, 0, 1, 1};
7920 const int UnpackHiMask[] = {2, 2, 3, 3};
7921 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
7922 Mask = UnpackLoMask;
7923 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
7924 Mask = UnpackHiMask;
7926 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7927 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7930 // Try to use shift instructions.
7932 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
7935 // There are special ways we can lower some single-element blends.
7936 if (NumV2Elements == 1)
7937 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
7938 Mask, Subtarget, DAG))
7941 // We have different paths for blend lowering, but they all must use the
7942 // *exact* same predicate.
7943 bool IsBlendSupported = Subtarget->hasSSE41();
7944 if (IsBlendSupported)
7945 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
7949 if (SDValue Masked =
7950 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
7953 // Use dedicated unpack instructions for masks that match their pattern.
7954 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7955 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7956 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7957 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7958 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7959 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
7960 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7961 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
7963 // Try to use byte rotation instructions.
7964 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7965 if (Subtarget->hasSSSE3())
7966 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7967 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
7970 // If we have direct support for blends, we should lower by decomposing into
7971 // a permute. That will be faster than the domain cross.
7972 if (IsBlendSupported)
7973 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
7976 // Try to lower by permuting the inputs into an unpack instruction.
7977 if (SDValue Unpack =
7978 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
7981 // We implement this with SHUFPS because it can blend from two vectors.
7982 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7983 // up the inputs, bypassing domain shift penalties that we would encur if we
7984 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7986 return DAG.getBitcast(
7988 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
7989 DAG.getBitcast(MVT::v4f32, V2), Mask));
7992 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7993 /// shuffle lowering, and the most complex part.
7995 /// The lowering strategy is to try to form pairs of input lanes which are
7996 /// targeted at the same half of the final vector, and then use a dword shuffle
7997 /// to place them onto the right half, and finally unpack the paired lanes into
7998 /// their final position.
8000 /// The exact breakdown of how to form these dword pairs and align them on the
8001 /// correct sides is really tricky. See the comments within the function for
8002 /// more of the details.
8004 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8005 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8006 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8007 /// vector, form the analogous 128-bit 8-element Mask.
8008 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8009 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8010 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8011 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8012 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8014 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8015 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8016 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8018 SmallVector<int, 4> LoInputs;
8019 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8020 [](int M) { return M >= 0; });
8021 std::sort(LoInputs.begin(), LoInputs.end());
8022 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8023 SmallVector<int, 4> HiInputs;
8024 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8025 [](int M) { return M >= 0; });
8026 std::sort(HiInputs.begin(), HiInputs.end());
8027 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8029 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8030 int NumHToL = LoInputs.size() - NumLToL;
8032 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8033 int NumHToH = HiInputs.size() - NumLToH;
8034 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8035 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8036 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8037 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8039 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8040 // such inputs we can swap two of the dwords across the half mark and end up
8041 // with <=2 inputs to each half in each half. Once there, we can fall through
8042 // to the generic code below. For example:
8044 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8045 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8047 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8048 // and an existing 2-into-2 on the other half. In this case we may have to
8049 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8050 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8051 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8052 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8053 // half than the one we target for fixing) will be fixed when we re-enter this
8054 // path. We will also combine away any sequence of PSHUFD instructions that
8055 // result into a single instruction. Here is an example of the tricky case:
8057 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8058 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8060 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8062 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8063 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8065 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8066 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8068 // The result is fine to be handled by the generic logic.
8069 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8070 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8071 int AOffset, int BOffset) {
8072 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8073 "Must call this with A having 3 or 1 inputs from the A half.");
8074 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8075 "Must call this with B having 1 or 3 inputs from the B half.");
8076 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8077 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8079 // Compute the index of dword with only one word among the three inputs in
8080 // a half by taking the sum of the half with three inputs and subtracting
8081 // the sum of the actual three inputs. The difference is the remaining
8084 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8085 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8086 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8087 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8088 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8089 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8090 int TripleNonInputIdx =
8091 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8092 TripleDWord = TripleNonInputIdx / 2;
8094 // We use xor with one to compute the adjacent DWord to whichever one the
8096 OneInputDWord = (OneInput / 2) ^ 1;
8098 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8099 // and BToA inputs. If there is also such a problem with the BToB and AToB
8100 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8101 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8102 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8103 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8104 // Compute how many inputs will be flipped by swapping these DWords. We
8106 // to balance this to ensure we don't form a 3-1 shuffle in the other
8108 int NumFlippedAToBInputs =
8109 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8110 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8111 int NumFlippedBToBInputs =
8112 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8113 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8114 if ((NumFlippedAToBInputs == 1 &&
8115 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8116 (NumFlippedBToBInputs == 1 &&
8117 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8118 // We choose whether to fix the A half or B half based on whether that
8119 // half has zero flipped inputs. At zero, we may not be able to fix it
8120 // with that half. We also bias towards fixing the B half because that
8121 // will more commonly be the high half, and we have to bias one way.
8122 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8123 ArrayRef<int> Inputs) {
8124 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8125 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8126 PinnedIdx ^ 1) != Inputs.end();
8127 // Determine whether the free index is in the flipped dword or the
8128 // unflipped dword based on where the pinned index is. We use this bit
8129 // in an xor to conditionally select the adjacent dword.
8130 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8131 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8132 FixFreeIdx) != Inputs.end();
8133 if (IsFixIdxInput == IsFixFreeIdxInput)
8135 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8136 FixFreeIdx) != Inputs.end();
8137 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8138 "We need to be changing the number of flipped inputs!");
8139 int PSHUFHalfMask[] = {0, 1, 2, 3};
8140 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8141 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8143 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8146 if (M != -1 && M == FixIdx)
8148 else if (M != -1 && M == FixFreeIdx)
8151 if (NumFlippedBToBInputs != 0) {
8153 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8154 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8156 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8158 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8159 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8164 int PSHUFDMask[] = {0, 1, 2, 3};
8165 PSHUFDMask[ADWord] = BDWord;
8166 PSHUFDMask[BDWord] = ADWord;
8169 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8170 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8172 // Adjust the mask to match the new locations of A and B.
8174 if (M != -1 && M/2 == ADWord)
8175 M = 2 * BDWord + M % 2;
8176 else if (M != -1 && M/2 == BDWord)
8177 M = 2 * ADWord + M % 2;
8179 // Recurse back into this routine to re-compute state now that this isn't
8180 // a 3 and 1 problem.
8181 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8184 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8185 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8186 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8187 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8189 // At this point there are at most two inputs to the low and high halves from
8190 // each half. That means the inputs can always be grouped into dwords and
8191 // those dwords can then be moved to the correct half with a dword shuffle.
8192 // We use at most one low and one high word shuffle to collect these paired
8193 // inputs into dwords, and finally a dword shuffle to place them.
8194 int PSHUFLMask[4] = {-1, -1, -1, -1};
8195 int PSHUFHMask[4] = {-1, -1, -1, -1};
8196 int PSHUFDMask[4] = {-1, -1, -1, -1};
8198 // First fix the masks for all the inputs that are staying in their
8199 // original halves. This will then dictate the targets of the cross-half
8201 auto fixInPlaceInputs =
8202 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8203 MutableArrayRef<int> SourceHalfMask,
8204 MutableArrayRef<int> HalfMask, int HalfOffset) {
8205 if (InPlaceInputs.empty())
8207 if (InPlaceInputs.size() == 1) {
8208 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8209 InPlaceInputs[0] - HalfOffset;
8210 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8213 if (IncomingInputs.empty()) {
8214 // Just fix all of the in place inputs.
8215 for (int Input : InPlaceInputs) {
8216 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8217 PSHUFDMask[Input / 2] = Input / 2;
8222 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8223 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8224 InPlaceInputs[0] - HalfOffset;
8225 // Put the second input next to the first so that they are packed into
8226 // a dword. We find the adjacent index by toggling the low bit.
8227 int AdjIndex = InPlaceInputs[0] ^ 1;
8228 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8229 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8230 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8232 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8233 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8235 // Now gather the cross-half inputs and place them into a free dword of
8236 // their target half.
8237 // FIXME: This operation could almost certainly be simplified dramatically to
8238 // look more like the 3-1 fixing operation.
8239 auto moveInputsToRightHalf = [&PSHUFDMask](
8240 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8241 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8242 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8244 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8245 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8247 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8249 int LowWord = Word & ~1;
8250 int HighWord = Word | 1;
8251 return isWordClobbered(SourceHalfMask, LowWord) ||
8252 isWordClobbered(SourceHalfMask, HighWord);
8255 if (IncomingInputs.empty())
8258 if (ExistingInputs.empty()) {
8259 // Map any dwords with inputs from them into the right half.
8260 for (int Input : IncomingInputs) {
8261 // If the source half mask maps over the inputs, turn those into
8262 // swaps and use the swapped lane.
8263 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8264 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8265 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8266 Input - SourceOffset;
8267 // We have to swap the uses in our half mask in one sweep.
8268 for (int &M : HalfMask)
8269 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8271 else if (M == Input)
8272 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8274 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8275 Input - SourceOffset &&
8276 "Previous placement doesn't match!");
8278 // Note that this correctly re-maps both when we do a swap and when
8279 // we observe the other side of the swap above. We rely on that to
8280 // avoid swapping the members of the input list directly.
8281 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8284 // Map the input's dword into the correct half.
8285 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8286 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8288 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8290 "Previous placement doesn't match!");
8293 // And just directly shift any other-half mask elements to be same-half
8294 // as we will have mirrored the dword containing the element into the
8295 // same position within that half.
8296 for (int &M : HalfMask)
8297 if (M >= SourceOffset && M < SourceOffset + 4) {
8298 M = M - SourceOffset + DestOffset;
8299 assert(M >= 0 && "This should never wrap below zero!");
8304 // Ensure we have the input in a viable dword of its current half. This
8305 // is particularly tricky because the original position may be clobbered
8306 // by inputs being moved and *staying* in that half.
8307 if (IncomingInputs.size() == 1) {
8308 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8309 int InputFixed = std::find(std::begin(SourceHalfMask),
8310 std::end(SourceHalfMask), -1) -
8311 std::begin(SourceHalfMask) + SourceOffset;
8312 SourceHalfMask[InputFixed - SourceOffset] =
8313 IncomingInputs[0] - SourceOffset;
8314 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8316 IncomingInputs[0] = InputFixed;
8318 } else if (IncomingInputs.size() == 2) {
8319 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8320 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8321 // We have two non-adjacent or clobbered inputs we need to extract from
8322 // the source half. To do this, we need to map them into some adjacent
8323 // dword slot in the source mask.
8324 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8325 IncomingInputs[1] - SourceOffset};
8327 // If there is a free slot in the source half mask adjacent to one of
8328 // the inputs, place the other input in it. We use (Index XOR 1) to
8329 // compute an adjacent index.
8330 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8331 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8332 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8333 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8334 InputsFixed[1] = InputsFixed[0] ^ 1;
8335 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8336 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8337 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8338 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8339 InputsFixed[0] = InputsFixed[1] ^ 1;
8340 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8341 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8342 // The two inputs are in the same DWord but it is clobbered and the
8343 // adjacent DWord isn't used at all. Move both inputs to the free
8345 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8346 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8347 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8348 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8350 // The only way we hit this point is if there is no clobbering
8351 // (because there are no off-half inputs to this half) and there is no
8352 // free slot adjacent to one of the inputs. In this case, we have to
8353 // swap an input with a non-input.
8354 for (int i = 0; i < 4; ++i)
8355 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8356 "We can't handle any clobbers here!");
8357 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8358 "Cannot have adjacent inputs here!");
8360 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8361 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8363 // We also have to update the final source mask in this case because
8364 // it may need to undo the above swap.
8365 for (int &M : FinalSourceHalfMask)
8366 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8367 M = InputsFixed[1] + SourceOffset;
8368 else if (M == InputsFixed[1] + SourceOffset)
8369 M = (InputsFixed[0] ^ 1) + SourceOffset;
8371 InputsFixed[1] = InputsFixed[0] ^ 1;
8374 // Point everything at the fixed inputs.
8375 for (int &M : HalfMask)
8376 if (M == IncomingInputs[0])
8377 M = InputsFixed[0] + SourceOffset;
8378 else if (M == IncomingInputs[1])
8379 M = InputsFixed[1] + SourceOffset;
8381 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8382 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8385 llvm_unreachable("Unhandled input size!");
8388 // Now hoist the DWord down to the right half.
8389 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8390 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8391 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8392 for (int &M : HalfMask)
8393 for (int Input : IncomingInputs)
8395 M = FreeDWord * 2 + Input % 2;
8397 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8398 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8399 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8400 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8402 // Now enact all the shuffles we've computed to move the inputs into their
8404 if (!isNoopShuffleMask(PSHUFLMask))
8405 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8406 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8407 if (!isNoopShuffleMask(PSHUFHMask))
8408 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8409 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8410 if (!isNoopShuffleMask(PSHUFDMask))
8413 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8414 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8416 // At this point, each half should contain all its inputs, and we can then
8417 // just shuffle them into their final position.
8418 assert(std::count_if(LoMask.begin(), LoMask.end(),
8419 [](int M) { return M >= 4; }) == 0 &&
8420 "Failed to lift all the high half inputs to the low mask!");
8421 assert(std::count_if(HiMask.begin(), HiMask.end(),
8422 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8423 "Failed to lift all the low half inputs to the high mask!");
8425 // Do a half shuffle for the low mask.
8426 if (!isNoopShuffleMask(LoMask))
8427 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8428 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8430 // Do a half shuffle with the high mask after shifting its values down.
8431 for (int &M : HiMask)
8434 if (!isNoopShuffleMask(HiMask))
8435 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8436 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8441 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8442 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8443 SDValue V2, ArrayRef<int> Mask,
8444 SelectionDAG &DAG, bool &V1InUse,
8446 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8452 int Size = Mask.size();
8453 int Scale = 16 / Size;
8454 for (int i = 0; i < 16; ++i) {
8455 if (Mask[i / Scale] == -1) {
8456 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8458 const int ZeroMask = 0x80;
8459 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8461 int V2Idx = Mask[i / Scale] < Size
8463 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8464 if (Zeroable[i / Scale])
8465 V1Idx = V2Idx = ZeroMask;
8466 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8467 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8468 V1InUse |= (ZeroMask != V1Idx);
8469 V2InUse |= (ZeroMask != V2Idx);
8474 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8475 DAG.getBitcast(MVT::v16i8, V1),
8476 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8478 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8479 DAG.getBitcast(MVT::v16i8, V2),
8480 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8482 // If we need shuffled inputs from both, blend the two.
8484 if (V1InUse && V2InUse)
8485 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8487 V = V1InUse ? V1 : V2;
8489 // Cast the result back to the correct type.
8490 return DAG.getBitcast(VT, V);
8493 /// \brief Generic lowering of 8-lane i16 shuffles.
8495 /// This handles both single-input shuffles and combined shuffle/blends with
8496 /// two inputs. The single input shuffles are immediately delegated to
8497 /// a dedicated lowering routine.
8499 /// The blends are lowered in one of three fundamental ways. If there are few
8500 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8501 /// of the input is significantly cheaper when lowered as an interleaving of
8502 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8503 /// halves of the inputs separately (making them have relatively few inputs)
8504 /// and then concatenate them.
8505 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8506 const X86Subtarget *Subtarget,
8507 SelectionDAG &DAG) {
8509 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8510 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8511 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8512 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8513 ArrayRef<int> OrigMask = SVOp->getMask();
8514 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8515 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8516 MutableArrayRef<int> Mask(MaskStorage);
8518 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8520 // Whenever we can lower this as a zext, that instruction is strictly faster
8521 // than any alternative.
8522 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8523 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8526 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8528 auto isV2 = [](int M) { return M >= 8; };
8530 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8532 if (NumV2Inputs == 0) {
8533 // Check for being able to broadcast a single element.
8534 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8535 Mask, Subtarget, DAG))
8538 // Try to use shift instructions.
8540 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8543 // Use dedicated unpack instructions for masks that match their pattern.
8544 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8545 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8546 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8547 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8549 // Try to use byte rotation instructions.
8550 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8551 Mask, Subtarget, DAG))
8554 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8558 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8559 "All single-input shuffles should be canonicalized to be V1-input "
8562 // Try to use shift instructions.
8564 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8567 // There are special ways we can lower some single-element blends.
8568 if (NumV2Inputs == 1)
8569 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8570 Mask, Subtarget, DAG))
8573 // We have different paths for blend lowering, but they all must use the
8574 // *exact* same predicate.
8575 bool IsBlendSupported = Subtarget->hasSSE41();
8576 if (IsBlendSupported)
8577 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8581 if (SDValue Masked =
8582 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8585 // Use dedicated unpack instructions for masks that match their pattern.
8586 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8587 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8588 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8589 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8591 // Try to use byte rotation instructions.
8592 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8593 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8596 if (SDValue BitBlend =
8597 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8600 if (SDValue Unpack =
8601 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8604 // If we can't directly blend but can use PSHUFB, that will be better as it
8605 // can both shuffle and set up the inefficient blend.
8606 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8607 bool V1InUse, V2InUse;
8608 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8612 // We can always bit-blend if we have to so the fallback strategy is to
8613 // decompose into single-input permutes and blends.
8614 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8618 /// \brief Check whether a compaction lowering can be done by dropping even
8619 /// elements and compute how many times even elements must be dropped.
8621 /// This handles shuffles which take every Nth element where N is a power of
8622 /// two. Example shuffle masks:
8624 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8625 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8626 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8627 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8628 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8629 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8631 /// Any of these lanes can of course be undef.
8633 /// This routine only supports N <= 3.
8634 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8637 /// \returns N above, or the number of times even elements must be dropped if
8638 /// there is such a number. Otherwise returns zero.
8639 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8640 // Figure out whether we're looping over two inputs or just one.
8641 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8643 // The modulus for the shuffle vector entries is based on whether this is
8644 // a single input or not.
8645 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8646 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8647 "We should only be called with masks with a power-of-2 size!");
8649 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8651 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8652 // and 2^3 simultaneously. This is because we may have ambiguity with
8653 // partially undef inputs.
8654 bool ViableForN[3] = {true, true, true};
8656 for (int i = 0, e = Mask.size(); i < e; ++i) {
8657 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8662 bool IsAnyViable = false;
8663 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8664 if (ViableForN[j]) {
8667 // The shuffle mask must be equal to (i * 2^N) % M.
8668 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8671 ViableForN[j] = false;
8673 // Early exit if we exhaust the possible powers of two.
8678 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8682 // Return 0 as there is no viable power of two.
8686 /// \brief Generic lowering of v16i8 shuffles.
8688 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8689 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8690 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8691 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8693 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8694 const X86Subtarget *Subtarget,
8695 SelectionDAG &DAG) {
8697 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8698 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8699 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8700 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8701 ArrayRef<int> Mask = SVOp->getMask();
8702 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8704 // Try to use shift instructions.
8706 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8709 // Try to use byte rotation instructions.
8710 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8711 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8714 // Try to use a zext lowering.
8715 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8716 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8720 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8722 // For single-input shuffles, there are some nicer lowering tricks we can use.
8723 if (NumV2Elements == 0) {
8724 // Check for being able to broadcast a single element.
8725 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8726 Mask, Subtarget, DAG))
8729 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8730 // Notably, this handles splat and partial-splat shuffles more efficiently.
8731 // However, it only makes sense if the pre-duplication shuffle simplifies
8732 // things significantly. Currently, this means we need to be able to
8733 // express the pre-duplication shuffle as an i16 shuffle.
8735 // FIXME: We should check for other patterns which can be widened into an
8736 // i16 shuffle as well.
8737 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8738 for (int i = 0; i < 16; i += 2)
8739 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8744 auto tryToWidenViaDuplication = [&]() -> SDValue {
8745 if (!canWidenViaDuplication(Mask))
8747 SmallVector<int, 4> LoInputs;
8748 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8749 [](int M) { return M >= 0 && M < 8; });
8750 std::sort(LoInputs.begin(), LoInputs.end());
8751 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8753 SmallVector<int, 4> HiInputs;
8754 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8755 [](int M) { return M >= 8; });
8756 std::sort(HiInputs.begin(), HiInputs.end());
8757 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8760 bool TargetLo = LoInputs.size() >= HiInputs.size();
8761 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8762 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8764 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8765 SmallDenseMap<int, int, 8> LaneMap;
8766 for (int I : InPlaceInputs) {
8767 PreDupI16Shuffle[I/2] = I/2;
8770 int j = TargetLo ? 0 : 4, je = j + 4;
8771 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8772 // Check if j is already a shuffle of this input. This happens when
8773 // there are two adjacent bytes after we move the low one.
8774 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8775 // If we haven't yet mapped the input, search for a slot into which
8777 while (j < je && PreDupI16Shuffle[j] != -1)
8781 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8784 // Map this input with the i16 shuffle.
8785 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8788 // Update the lane map based on the mapping we ended up with.
8789 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8791 V1 = DAG.getBitcast(
8793 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
8794 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8796 // Unpack the bytes to form the i16s that will be shuffled into place.
8797 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8798 MVT::v16i8, V1, V1);
8800 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8801 for (int i = 0; i < 16; ++i)
8802 if (Mask[i] != -1) {
8803 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8804 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8805 if (PostDupI16Shuffle[i / 2] == -1)
8806 PostDupI16Shuffle[i / 2] = MappedMask;
8808 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8809 "Conflicting entrties in the original shuffle!");
8811 return DAG.getBitcast(
8813 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
8814 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8816 if (SDValue V = tryToWidenViaDuplication())
8820 // Use dedicated unpack instructions for masks that match their pattern.
8821 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8822 0, 16, 1, 17, 2, 18, 3, 19,
8824 4, 20, 5, 21, 6, 22, 7, 23}))
8825 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
8826 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8827 8, 24, 9, 25, 10, 26, 11, 27,
8829 12, 28, 13, 29, 14, 30, 15, 31}))
8830 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
8832 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8833 // with PSHUFB. It is important to do this before we attempt to generate any
8834 // blends but after all of the single-input lowerings. If the single input
8835 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8836 // want to preserve that and we can DAG combine any longer sequences into
8837 // a PSHUFB in the end. But once we start blending from multiple inputs,
8838 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8839 // and there are *very* few patterns that would actually be faster than the
8840 // PSHUFB approach because of its ability to zero lanes.
8842 // FIXME: The only exceptions to the above are blends which are exact
8843 // interleavings with direct instructions supporting them. We currently don't
8844 // handle those well here.
8845 if (Subtarget->hasSSSE3()) {
8846 bool V1InUse = false;
8847 bool V2InUse = false;
8849 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
8850 DAG, V1InUse, V2InUse);
8852 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
8853 // do so. This avoids using them to handle blends-with-zero which is
8854 // important as a single pshufb is significantly faster for that.
8855 if (V1InUse && V2InUse) {
8856 if (Subtarget->hasSSE41())
8857 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
8858 Mask, Subtarget, DAG))
8861 // We can use an unpack to do the blending rather than an or in some
8862 // cases. Even though the or may be (very minorly) more efficient, we
8863 // preference this lowering because there are common cases where part of
8864 // the complexity of the shuffles goes away when we do the final blend as
8866 // FIXME: It might be worth trying to detect if the unpack-feeding
8867 // shuffles will both be pshufb, in which case we shouldn't bother with
8869 if (SDValue Unpack =
8870 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
8877 // There are special ways we can lower some single-element blends.
8878 if (NumV2Elements == 1)
8879 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
8880 Mask, Subtarget, DAG))
8883 if (SDValue BitBlend =
8884 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
8887 // Check whether a compaction lowering can be done. This handles shuffles
8888 // which take every Nth element for some even N. See the helper function for
8891 // We special case these as they can be particularly efficiently handled with
8892 // the PACKUSB instruction on x86 and they show up in common patterns of
8893 // rearranging bytes to truncate wide elements.
8894 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8895 // NumEvenDrops is the power of two stride of the elements. Another way of
8896 // thinking about it is that we need to drop the even elements this many
8897 // times to get the original input.
8898 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8900 // First we need to zero all the dropped bytes.
8901 assert(NumEvenDrops <= 3 &&
8902 "No support for dropping even elements more than 3 times.");
8903 // We use the mask type to pick which bytes are preserved based on how many
8904 // elements are dropped.
8905 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8906 SDValue ByteClearMask = DAG.getBitcast(
8907 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
8908 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8910 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8912 // Now pack things back together.
8913 V1 = DAG.getBitcast(MVT::v8i16, V1);
8914 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
8915 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8916 for (int i = 1; i < NumEvenDrops; ++i) {
8917 Result = DAG.getBitcast(MVT::v8i16, Result);
8918 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8924 // Handle multi-input cases by blending single-input shuffles.
8925 if (NumV2Elements > 0)
8926 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
8929 // The fallback path for single-input shuffles widens this into two v8i16
8930 // vectors with unpacks, shuffles those, and then pulls them back together
8934 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8935 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8936 for (int i = 0; i < 16; ++i)
8938 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
8940 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8942 SDValue VLoHalf, VHiHalf;
8943 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8944 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8946 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
8947 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8948 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
8949 [](int M) { return M >= 0 && M % 2 == 1; })) {
8950 // Use a mask to drop the high bytes.
8951 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
8952 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
8953 DAG.getConstant(0x00FF, DL, MVT::v8i16));
8955 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
8956 VHiHalf = DAG.getUNDEF(MVT::v8i16);
8958 // Squash the masks to point directly into VLoHalf.
8959 for (int &M : LoBlendMask)
8962 for (int &M : HiBlendMask)
8966 // Otherwise just unpack the low half of V into VLoHalf and the high half into
8967 // VHiHalf so that we can blend them as i16s.
8968 VLoHalf = DAG.getBitcast(
8969 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8970 VHiHalf = DAG.getBitcast(
8971 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8974 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
8975 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
8977 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8980 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8982 /// This routine breaks down the specific type of 128-bit shuffle and
8983 /// dispatches to the lowering routines accordingly.
8984 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8985 MVT VT, const X86Subtarget *Subtarget,
8986 SelectionDAG &DAG) {
8987 switch (VT.SimpleTy) {
8989 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8991 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8993 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8995 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8997 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8999 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9002 llvm_unreachable("Unimplemented!");
9006 /// \brief Helper function to test whether a shuffle mask could be
9007 /// simplified by widening the elements being shuffled.
9009 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9010 /// leaves it in an unspecified state.
9012 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9013 /// shuffle masks. The latter have the special property of a '-2' representing
9014 /// a zero-ed lane of a vector.
9015 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9016 SmallVectorImpl<int> &WidenedMask) {
9017 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9018 // If both elements are undef, its trivial.
9019 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9020 WidenedMask.push_back(SM_SentinelUndef);
9024 // Check for an undef mask and a mask value properly aligned to fit with
9025 // a pair of values. If we find such a case, use the non-undef mask's value.
9026 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9027 WidenedMask.push_back(Mask[i + 1] / 2);
9030 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9031 WidenedMask.push_back(Mask[i] / 2);
9035 // When zeroing, we need to spread the zeroing across both lanes to widen.
9036 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9037 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9038 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9039 WidenedMask.push_back(SM_SentinelZero);
9045 // Finally check if the two mask values are adjacent and aligned with
9047 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9048 WidenedMask.push_back(Mask[i] / 2);
9052 // Otherwise we can't safely widen the elements used in this shuffle.
9055 assert(WidenedMask.size() == Mask.size() / 2 &&
9056 "Incorrect size of mask after widening the elements!");
9061 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9063 /// This routine just extracts two subvectors, shuffles them independently, and
9064 /// then concatenates them back together. This should work effectively with all
9065 /// AVX vector shuffle types.
9066 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9067 SDValue V2, ArrayRef<int> Mask,
9068 SelectionDAG &DAG) {
9069 assert(VT.getSizeInBits() >= 256 &&
9070 "Only for 256-bit or wider vector shuffles!");
9071 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9072 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9074 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9075 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9077 int NumElements = VT.getVectorNumElements();
9078 int SplitNumElements = NumElements / 2;
9079 MVT ScalarVT = VT.getScalarType();
9080 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9082 // Rather than splitting build-vectors, just build two narrower build
9083 // vectors. This helps shuffling with splats and zeros.
9084 auto SplitVector = [&](SDValue V) {
9085 while (V.getOpcode() == ISD::BITCAST)
9086 V = V->getOperand(0);
9088 MVT OrigVT = V.getSimpleValueType();
9089 int OrigNumElements = OrigVT.getVectorNumElements();
9090 int OrigSplitNumElements = OrigNumElements / 2;
9091 MVT OrigScalarVT = OrigVT.getScalarType();
9092 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9096 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9098 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9099 DAG.getIntPtrConstant(0, DL));
9100 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9101 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9104 SmallVector<SDValue, 16> LoOps, HiOps;
9105 for (int i = 0; i < OrigSplitNumElements; ++i) {
9106 LoOps.push_back(BV->getOperand(i));
9107 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9109 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9110 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9112 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9113 DAG.getBitcast(SplitVT, HiV));
9116 SDValue LoV1, HiV1, LoV2, HiV2;
9117 std::tie(LoV1, HiV1) = SplitVector(V1);
9118 std::tie(LoV2, HiV2) = SplitVector(V2);
9120 // Now create two 4-way blends of these half-width vectors.
9121 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9122 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9123 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9124 for (int i = 0; i < SplitNumElements; ++i) {
9125 int M = HalfMask[i];
9126 if (M >= NumElements) {
9127 if (M >= NumElements + SplitNumElements)
9131 V2BlendMask.push_back(M - NumElements);
9132 V1BlendMask.push_back(-1);
9133 BlendMask.push_back(SplitNumElements + i);
9134 } else if (M >= 0) {
9135 if (M >= SplitNumElements)
9139 V2BlendMask.push_back(-1);
9140 V1BlendMask.push_back(M);
9141 BlendMask.push_back(i);
9143 V2BlendMask.push_back(-1);
9144 V1BlendMask.push_back(-1);
9145 BlendMask.push_back(-1);
9149 // Because the lowering happens after all combining takes place, we need to
9150 // manually combine these blend masks as much as possible so that we create
9151 // a minimal number of high-level vector shuffle nodes.
9153 // First try just blending the halves of V1 or V2.
9154 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9155 return DAG.getUNDEF(SplitVT);
9156 if (!UseLoV2 && !UseHiV2)
9157 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9158 if (!UseLoV1 && !UseHiV1)
9159 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9161 SDValue V1Blend, V2Blend;
9162 if (UseLoV1 && UseHiV1) {
9164 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9166 // We only use half of V1 so map the usage down into the final blend mask.
9167 V1Blend = UseLoV1 ? LoV1 : HiV1;
9168 for (int i = 0; i < SplitNumElements; ++i)
9169 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9170 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9172 if (UseLoV2 && UseHiV2) {
9174 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9176 // We only use half of V2 so map the usage down into the final blend mask.
9177 V2Blend = UseLoV2 ? LoV2 : HiV2;
9178 for (int i = 0; i < SplitNumElements; ++i)
9179 if (BlendMask[i] >= SplitNumElements)
9180 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9182 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9184 SDValue Lo = HalfBlend(LoMask);
9185 SDValue Hi = HalfBlend(HiMask);
9186 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9189 /// \brief Either split a vector in halves or decompose the shuffles and the
9192 /// This is provided as a good fallback for many lowerings of non-single-input
9193 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9194 /// between splitting the shuffle into 128-bit components and stitching those
9195 /// back together vs. extracting the single-input shuffles and blending those
9197 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9198 SDValue V2, ArrayRef<int> Mask,
9199 SelectionDAG &DAG) {
9200 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9201 "lower single-input shuffles as it "
9202 "could then recurse on itself.");
9203 int Size = Mask.size();
9205 // If this can be modeled as a broadcast of two elements followed by a blend,
9206 // prefer that lowering. This is especially important because broadcasts can
9207 // often fold with memory operands.
9208 auto DoBothBroadcast = [&] {
9209 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9212 if (V2BroadcastIdx == -1)
9213 V2BroadcastIdx = M - Size;
9214 else if (M - Size != V2BroadcastIdx)
9216 } else if (M >= 0) {
9217 if (V1BroadcastIdx == -1)
9219 else if (M != V1BroadcastIdx)
9224 if (DoBothBroadcast())
9225 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9228 // If the inputs all stem from a single 128-bit lane of each input, then we
9229 // split them rather than blending because the split will decompose to
9230 // unusually few instructions.
9231 int LaneCount = VT.getSizeInBits() / 128;
9232 int LaneSize = Size / LaneCount;
9233 SmallBitVector LaneInputs[2];
9234 LaneInputs[0].resize(LaneCount, false);
9235 LaneInputs[1].resize(LaneCount, false);
9236 for (int i = 0; i < Size; ++i)
9238 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9239 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9240 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9242 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9243 // that the decomposed single-input shuffles don't end up here.
9244 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9247 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9248 /// a permutation and blend of those lanes.
9250 /// This essentially blends the out-of-lane inputs to each lane into the lane
9251 /// from a permuted copy of the vector. This lowering strategy results in four
9252 /// instructions in the worst case for a single-input cross lane shuffle which
9253 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9254 /// of. Special cases for each particular shuffle pattern should be handled
9255 /// prior to trying this lowering.
9256 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9257 SDValue V1, SDValue V2,
9259 SelectionDAG &DAG) {
9260 // FIXME: This should probably be generalized for 512-bit vectors as well.
9261 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9262 int LaneSize = Mask.size() / 2;
9264 // If there are only inputs from one 128-bit lane, splitting will in fact be
9265 // less expensive. The flags track whether the given lane contains an element
9266 // that crosses to another lane.
9267 bool LaneCrossing[2] = {false, false};
9268 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9269 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9270 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9271 if (!LaneCrossing[0] || !LaneCrossing[1])
9272 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9274 if (isSingleInputShuffleMask(Mask)) {
9275 SmallVector<int, 32> FlippedBlendMask;
9276 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9277 FlippedBlendMask.push_back(
9278 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9280 : Mask[i] % LaneSize +
9281 (i / LaneSize) * LaneSize + Size));
9283 // Flip the vector, and blend the results which should now be in-lane. The
9284 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9285 // 5 for the high source. The value 3 selects the high half of source 2 and
9286 // the value 2 selects the low half of source 2. We only use source 2 to
9287 // allow folding it into a memory operand.
9288 unsigned PERMMask = 3 | 2 << 4;
9289 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9290 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9291 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9294 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9295 // will be handled by the above logic and a blend of the results, much like
9296 // other patterns in AVX.
9297 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9300 /// \brief Handle lowering 2-lane 128-bit shuffles.
9301 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9302 SDValue V2, ArrayRef<int> Mask,
9303 const X86Subtarget *Subtarget,
9304 SelectionDAG &DAG) {
9305 // TODO: If minimizing size and one of the inputs is a zero vector and the
9306 // the zero vector has only one use, we could use a VPERM2X128 to save the
9307 // instruction bytes needed to explicitly generate the zero vector.
9309 // Blends are faster and handle all the non-lane-crossing cases.
9310 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9314 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9315 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9317 // If either input operand is a zero vector, use VPERM2X128 because its mask
9318 // allows us to replace the zero input with an implicit zero.
9319 if (!IsV1Zero && !IsV2Zero) {
9320 // Check for patterns which can be matched with a single insert of a 128-bit
9322 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9323 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9324 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9325 VT.getVectorNumElements() / 2);
9326 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9327 DAG.getIntPtrConstant(0, DL));
9328 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9329 OnlyUsesV1 ? V1 : V2,
9330 DAG.getIntPtrConstant(0, DL));
9331 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9335 // Otherwise form a 128-bit permutation. After accounting for undefs,
9336 // convert the 64-bit shuffle mask selection values into 128-bit
9337 // selection bits by dividing the indexes by 2 and shifting into positions
9338 // defined by a vperm2*128 instruction's immediate control byte.
9340 // The immediate permute control byte looks like this:
9341 // [1:0] - select 128 bits from sources for low half of destination
9343 // [3] - zero low half of destination
9344 // [5:4] - select 128 bits from sources for high half of destination
9346 // [7] - zero high half of destination
9348 int MaskLO = Mask[0];
9349 if (MaskLO == SM_SentinelUndef)
9350 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9352 int MaskHI = Mask[2];
9353 if (MaskHI == SM_SentinelUndef)
9354 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9356 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9358 // If either input is a zero vector, replace it with an undef input.
9359 // Shuffle mask values < 4 are selecting elements of V1.
9360 // Shuffle mask values >= 4 are selecting elements of V2.
9361 // Adjust each half of the permute mask by clearing the half that was
9362 // selecting the zero vector and setting the zero mask bit.
9364 V1 = DAG.getUNDEF(VT);
9366 PermMask = (PermMask & 0xf0) | 0x08;
9368 PermMask = (PermMask & 0x0f) | 0x80;
9371 V2 = DAG.getUNDEF(VT);
9373 PermMask = (PermMask & 0xf0) | 0x08;
9375 PermMask = (PermMask & 0x0f) | 0x80;
9378 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9379 DAG.getConstant(PermMask, DL, MVT::i8));
9382 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9383 /// shuffling each lane.
9385 /// This will only succeed when the result of fixing the 128-bit lanes results
9386 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9387 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9388 /// the lane crosses early and then use simpler shuffles within each lane.
9390 /// FIXME: It might be worthwhile at some point to support this without
9391 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9392 /// in x86 only floating point has interesting non-repeating shuffles, and even
9393 /// those are still *marginally* more expensive.
9394 static SDValue lowerVectorShuffleByMerging128BitLanes(
9395 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9396 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9397 assert(!isSingleInputShuffleMask(Mask) &&
9398 "This is only useful with multiple inputs.");
9400 int Size = Mask.size();
9401 int LaneSize = 128 / VT.getScalarSizeInBits();
9402 int NumLanes = Size / LaneSize;
9403 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9405 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9406 // check whether the in-128-bit lane shuffles share a repeating pattern.
9407 SmallVector<int, 4> Lanes;
9408 Lanes.resize(NumLanes, -1);
9409 SmallVector<int, 4> InLaneMask;
9410 InLaneMask.resize(LaneSize, -1);
9411 for (int i = 0; i < Size; ++i) {
9415 int j = i / LaneSize;
9418 // First entry we've seen for this lane.
9419 Lanes[j] = Mask[i] / LaneSize;
9420 } else if (Lanes[j] != Mask[i] / LaneSize) {
9421 // This doesn't match the lane selected previously!
9425 // Check that within each lane we have a consistent shuffle mask.
9426 int k = i % LaneSize;
9427 if (InLaneMask[k] < 0) {
9428 InLaneMask[k] = Mask[i] % LaneSize;
9429 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9430 // This doesn't fit a repeating in-lane mask.
9435 // First shuffle the lanes into place.
9436 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9437 VT.getSizeInBits() / 64);
9438 SmallVector<int, 8> LaneMask;
9439 LaneMask.resize(NumLanes * 2, -1);
9440 for (int i = 0; i < NumLanes; ++i)
9441 if (Lanes[i] >= 0) {
9442 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9443 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9446 V1 = DAG.getBitcast(LaneVT, V1);
9447 V2 = DAG.getBitcast(LaneVT, V2);
9448 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9450 // Cast it back to the type we actually want.
9451 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
9453 // Now do a simple shuffle that isn't lane crossing.
9454 SmallVector<int, 8> NewMask;
9455 NewMask.resize(Size, -1);
9456 for (int i = 0; i < Size; ++i)
9458 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9459 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9460 "Must not introduce lane crosses at this point!");
9462 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9465 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9468 /// This returns true if the elements from a particular input are already in the
9469 /// slot required by the given mask and require no permutation.
9470 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9471 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9472 int Size = Mask.size();
9473 for (int i = 0; i < Size; ++i)
9474 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9480 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
9481 ArrayRef<int> Mask, SDValue V1,
9482 SDValue V2, SelectionDAG &DAG) {
9484 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
9485 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
9486 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
9487 int NumElts = VT.getVectorNumElements();
9488 bool ShufpdMask = true;
9489 bool CommutableMask = true;
9490 unsigned Immediate = 0;
9491 for (int i = 0; i < NumElts; ++i) {
9494 int Val = (i & 6) + NumElts * (i & 1);
9495 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
9496 if (Mask[i] < Val || Mask[i] > Val + 1)
9498 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
9499 CommutableMask = false;
9500 Immediate |= (Mask[i] % 2) << i;
9503 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
9504 DAG.getConstant(Immediate, DL, MVT::i8));
9506 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
9507 DAG.getConstant(Immediate, DL, MVT::i8));
9511 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9513 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9514 /// isn't available.
9515 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9516 const X86Subtarget *Subtarget,
9517 SelectionDAG &DAG) {
9519 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9520 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9521 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9522 ArrayRef<int> Mask = SVOp->getMask();
9523 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9525 SmallVector<int, 4> WidenedMask;
9526 if (canWidenShuffleElements(Mask, WidenedMask))
9527 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9530 if (isSingleInputShuffleMask(Mask)) {
9531 // Check for being able to broadcast a single element.
9532 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9533 Mask, Subtarget, DAG))
9536 // Use low duplicate instructions for masks that match their pattern.
9537 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9538 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9540 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9541 // Non-half-crossing single input shuffles can be lowerid with an
9542 // interleaved permutation.
9543 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9544 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9545 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9546 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
9549 // With AVX2 we have direct support for this permutation.
9550 if (Subtarget->hasAVX2())
9551 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9552 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9554 // Otherwise, fall back.
9555 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9559 // X86 has dedicated unpack instructions that can handle specific blend
9560 // operations: UNPCKH and UNPCKL.
9561 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9562 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9563 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9564 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9565 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9566 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9567 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9568 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9570 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9574 // Check if the blend happens to exactly fit that of SHUFPD.
9576 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
9579 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9580 // shuffle. However, if we have AVX2 and either inputs are already in place,
9581 // we will be able to shuffle even across lanes the other input in a single
9582 // instruction so skip this pattern.
9583 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9584 isShuffleMaskInputInPlace(1, Mask))))
9585 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9586 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9589 // If we have AVX2 then we always want to lower with a blend because an v4 we
9590 // can fully permute the elements.
9591 if (Subtarget->hasAVX2())
9592 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9595 // Otherwise fall back on generic lowering.
9596 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9599 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9601 /// This routine is only called when we have AVX2 and thus a reasonable
9602 /// instruction set for v4i64 shuffling..
9603 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9604 const X86Subtarget *Subtarget,
9605 SelectionDAG &DAG) {
9607 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9608 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9609 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9610 ArrayRef<int> Mask = SVOp->getMask();
9611 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9612 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9614 SmallVector<int, 4> WidenedMask;
9615 if (canWidenShuffleElements(Mask, WidenedMask))
9616 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9619 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9623 // Check for being able to broadcast a single element.
9624 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9625 Mask, Subtarget, DAG))
9628 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9629 // use lower latency instructions that will operate on both 128-bit lanes.
9630 SmallVector<int, 2> RepeatedMask;
9631 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9632 if (isSingleInputShuffleMask(Mask)) {
9633 int PSHUFDMask[] = {-1, -1, -1, -1};
9634 for (int i = 0; i < 2; ++i)
9635 if (RepeatedMask[i] >= 0) {
9636 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9637 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9639 return DAG.getBitcast(
9641 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9642 DAG.getBitcast(MVT::v8i32, V1),
9643 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9647 // AVX2 provides a direct instruction for permuting a single input across
9649 if (isSingleInputShuffleMask(Mask))
9650 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9651 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9653 // Try to use shift instructions.
9655 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9658 // Use dedicated unpack instructions for masks that match their pattern.
9659 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9660 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9661 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9662 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9663 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9664 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9665 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9666 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9668 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9669 // shuffle. However, if we have AVX2 and either inputs are already in place,
9670 // we will be able to shuffle even across lanes the other input in a single
9671 // instruction so skip this pattern.
9672 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9673 isShuffleMaskInputInPlace(1, Mask))))
9674 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9675 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9678 // Otherwise fall back on generic blend lowering.
9679 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9683 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9685 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9686 /// isn't available.
9687 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9688 const X86Subtarget *Subtarget,
9689 SelectionDAG &DAG) {
9691 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9692 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9693 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9694 ArrayRef<int> Mask = SVOp->getMask();
9695 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9697 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9701 // Check for being able to broadcast a single element.
9702 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9703 Mask, Subtarget, DAG))
9706 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9707 // options to efficiently lower the shuffle.
9708 SmallVector<int, 4> RepeatedMask;
9709 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9710 assert(RepeatedMask.size() == 4 &&
9711 "Repeated masks must be half the mask width!");
9713 // Use even/odd duplicate instructions for masks that match their pattern.
9714 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9715 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9716 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9717 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9719 if (isSingleInputShuffleMask(Mask))
9720 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9721 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9723 // Use dedicated unpack instructions for masks that match their pattern.
9724 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9725 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9726 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9727 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9728 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9729 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9730 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9731 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9733 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9734 // have already handled any direct blends. We also need to squash the
9735 // repeated mask into a simulated v4f32 mask.
9736 for (int i = 0; i < 4; ++i)
9737 if (RepeatedMask[i] >= 8)
9738 RepeatedMask[i] -= 4;
9739 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9742 // If we have a single input shuffle with different shuffle patterns in the
9743 // two 128-bit lanes use the variable mask to VPERMILPS.
9744 if (isSingleInputShuffleMask(Mask)) {
9745 SDValue VPermMask[8];
9746 for (int i = 0; i < 8; ++i)
9747 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9748 : DAG.getConstant(Mask[i], DL, MVT::i32);
9749 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9751 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9752 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9754 if (Subtarget->hasAVX2())
9756 X86ISD::VPERMV, DL, MVT::v8f32,
9757 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
9758 MVT::v8i32, VPermMask)),
9761 // Otherwise, fall back.
9762 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9766 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9768 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9769 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9772 // If we have AVX2 then we always want to lower with a blend because at v8 we
9773 // can fully permute the elements.
9774 if (Subtarget->hasAVX2())
9775 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9778 // Otherwise fall back on generic lowering.
9779 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9782 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9784 /// This routine is only called when we have AVX2 and thus a reasonable
9785 /// instruction set for v8i32 shuffling..
9786 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9787 const X86Subtarget *Subtarget,
9788 SelectionDAG &DAG) {
9790 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9791 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9792 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9793 ArrayRef<int> Mask = SVOp->getMask();
9794 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9795 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9797 // Whenever we can lower this as a zext, that instruction is strictly faster
9798 // than any alternative. It also allows us to fold memory operands into the
9799 // shuffle in many cases.
9800 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9801 Mask, Subtarget, DAG))
9804 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9808 // Check for being able to broadcast a single element.
9809 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
9810 Mask, Subtarget, DAG))
9813 // If the shuffle mask is repeated in each 128-bit lane we can use more
9814 // efficient instructions that mirror the shuffles across the two 128-bit
9816 SmallVector<int, 4> RepeatedMask;
9817 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9818 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9819 if (isSingleInputShuffleMask(Mask))
9820 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9821 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9823 // Use dedicated unpack instructions for masks that match their pattern.
9824 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9825 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9826 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9827 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9828 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9829 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
9830 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9831 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
9834 // Try to use shift instructions.
9836 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
9839 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9840 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9843 // If the shuffle patterns aren't repeated but it is a single input, directly
9844 // generate a cross-lane VPERMD instruction.
9845 if (isSingleInputShuffleMask(Mask)) {
9846 SDValue VPermMask[8];
9847 for (int i = 0; i < 8; ++i)
9848 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9849 : DAG.getConstant(Mask[i], DL, MVT::i32);
9851 X86ISD::VPERMV, DL, MVT::v8i32,
9852 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9855 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9857 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9858 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9861 // Otherwise fall back on generic blend lowering.
9862 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9866 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9868 /// This routine is only called when we have AVX2 and thus a reasonable
9869 /// instruction set for v16i16 shuffling..
9870 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9871 const X86Subtarget *Subtarget,
9872 SelectionDAG &DAG) {
9874 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9875 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9876 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9877 ArrayRef<int> Mask = SVOp->getMask();
9878 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9879 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9881 // Whenever we can lower this as a zext, that instruction is strictly faster
9882 // than any alternative. It also allows us to fold memory operands into the
9883 // shuffle in many cases.
9884 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
9885 Mask, Subtarget, DAG))
9888 // Check for being able to broadcast a single element.
9889 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
9890 Mask, Subtarget, DAG))
9893 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9897 // Use dedicated unpack instructions for masks that match their pattern.
9898 if (isShuffleEquivalent(V1, V2, Mask,
9899 {// First 128-bit lane:
9900 0, 16, 1, 17, 2, 18, 3, 19,
9901 // Second 128-bit lane:
9902 8, 24, 9, 25, 10, 26, 11, 27}))
9903 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9904 if (isShuffleEquivalent(V1, V2, Mask,
9905 {// First 128-bit lane:
9906 4, 20, 5, 21, 6, 22, 7, 23,
9907 // Second 128-bit lane:
9908 12, 28, 13, 29, 14, 30, 15, 31}))
9909 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9911 // Try to use shift instructions.
9913 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
9916 // Try to use byte rotation instructions.
9917 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9918 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9921 if (isSingleInputShuffleMask(Mask)) {
9922 // There are no generalized cross-lane shuffle operations available on i16
9924 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9925 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9928 SmallVector<int, 8> RepeatedMask;
9929 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
9930 // As this is a single-input shuffle, the repeated mask should be
9931 // a strictly valid v8i16 mask that we can pass through to the v8i16
9932 // lowering to handle even the v16 case.
9933 return lowerV8I16GeneralSingleInputVectorShuffle(
9934 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
9937 SDValue PSHUFBMask[32];
9938 for (int i = 0; i < 16; ++i) {
9939 if (Mask[i] == -1) {
9940 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9944 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9945 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9946 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
9947 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
9949 return DAG.getBitcast(MVT::v16i16,
9950 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
9951 DAG.getBitcast(MVT::v32i8, V1),
9952 DAG.getNode(ISD::BUILD_VECTOR, DL,
9953 MVT::v32i8, PSHUFBMask)));
9956 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9958 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9959 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9962 // Otherwise fall back on generic lowering.
9963 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
9966 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9968 /// This routine is only called when we have AVX2 and thus a reasonable
9969 /// instruction set for v32i8 shuffling..
9970 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9971 const X86Subtarget *Subtarget,
9972 SelectionDAG &DAG) {
9974 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9975 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9976 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9977 ArrayRef<int> Mask = SVOp->getMask();
9978 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9979 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9981 // Whenever we can lower this as a zext, that instruction is strictly faster
9982 // than any alternative. It also allows us to fold memory operands into the
9983 // shuffle in many cases.
9984 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
9985 Mask, Subtarget, DAG))
9988 // Check for being able to broadcast a single element.
9989 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
9990 Mask, Subtarget, DAG))
9993 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9997 // Use dedicated unpack instructions for masks that match their pattern.
9998 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10000 if (isShuffleEquivalent(
10002 {// First 128-bit lane:
10003 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10004 // Second 128-bit lane:
10005 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10006 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10007 if (isShuffleEquivalent(
10009 {// First 128-bit lane:
10010 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10011 // Second 128-bit lane:
10012 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10013 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10015 // Try to use shift instructions.
10016 if (SDValue Shift =
10017 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10020 // Try to use byte rotation instructions.
10021 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10022 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10025 if (isSingleInputShuffleMask(Mask)) {
10026 // There are no generalized cross-lane shuffle operations available on i8
10028 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10029 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10032 SDValue PSHUFBMask[32];
10033 for (int i = 0; i < 32; ++i)
10036 ? DAG.getUNDEF(MVT::i8)
10037 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10040 return DAG.getNode(
10041 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10042 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10045 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10047 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10048 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10051 // Otherwise fall back on generic lowering.
10052 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10055 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10057 /// This routine either breaks down the specific type of a 256-bit x86 vector
10058 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10059 /// together based on the available instructions.
10060 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10061 MVT VT, const X86Subtarget *Subtarget,
10062 SelectionDAG &DAG) {
10064 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10065 ArrayRef<int> Mask = SVOp->getMask();
10067 // If we have a single input to the zero element, insert that into V1 if we
10068 // can do so cheaply.
10069 int NumElts = VT.getVectorNumElements();
10070 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10071 return M >= NumElts;
10074 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10075 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10076 DL, VT, V1, V2, Mask, Subtarget, DAG))
10079 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10080 // check for those subtargets here and avoid much of the subtarget querying in
10081 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10082 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10083 // floating point types there eventually, just immediately cast everything to
10084 // a float and operate entirely in that domain.
10085 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10086 int ElementBits = VT.getScalarSizeInBits();
10087 if (ElementBits < 32)
10088 // No floating point type available, decompose into 128-bit vectors.
10089 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10091 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10092 VT.getVectorNumElements());
10093 V1 = DAG.getBitcast(FpVT, V1);
10094 V2 = DAG.getBitcast(FpVT, V2);
10095 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10098 switch (VT.SimpleTy) {
10100 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10102 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10104 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10106 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10108 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10110 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10113 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10117 static SDValue lowerVectorShuffleWithVALIGN(SDLoc DL, MVT VT,
10118 ArrayRef<int> Mask, SDValue V1,
10119 SDValue V2, SelectionDAG &DAG) {
10121 assert(VT.getScalarSizeInBits() >= 32 && "Unexpected data type for VALIGN");
10122 // VALIGN pattern 2, 3, 4, 5, .. (sequential, shifted right)
10124 for (int i = 0; i < (signed)VT.getVectorNumElements(); ++i) {
10129 if (AlignVal == -1)
10130 AlignVal = Mask[i] - i;
10131 else if (Mask[i] - i != AlignVal)
10134 return DAG.getNode(X86ISD::VALIGN, DL, VT, V1, V2,
10135 DAG.getConstant(AlignVal, DL, MVT::i8));
10138 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10139 ArrayRef<int> Mask, SDValue V1,
10140 SDValue V2, SelectionDAG &DAG) {
10142 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10144 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10145 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10147 SmallVector<SDValue, 32> VPermMask;
10148 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i)
10149 VPermMask.push_back(Mask[i] < 0 ? DAG.getUNDEF(MaskEltVT) :
10150 DAG.getConstant(Mask[i], DL,MaskEltVT));
10151 SDValue MaskNode = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecVT,
10153 if (isSingleInputShuffleMask(Mask))
10154 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10156 return DAG.getNode(X86ISD::VPERMV3, DL, VT, MaskNode, V1, V2);
10160 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10161 static SDValue lowerV8X64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10162 const X86Subtarget *Subtarget,
10163 SelectionDAG &DAG) {
10165 MVT VT = Op.getSimpleValueType();
10166 assert((V1.getSimpleValueType() == MVT::v8f64 ||
10167 V1.getSimpleValueType() == MVT::v8i64) && "Bad operand type!");
10168 assert((V2.getSimpleValueType() == MVT::v8f64 ||
10169 V2.getSimpleValueType() == MVT::v8i64) && "Bad operand type!");
10170 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10171 ArrayRef<int> Mask = SVOp->getMask();
10172 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10174 // X86 has dedicated unpack instructions that can handle specific blend
10175 // operations: UNPCKH and UNPCKL.
10176 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10177 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
10178 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10179 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
10181 if (SDValue Op = lowerVectorShuffleWithVALIGN(DL, VT, Mask, V1, V2, DAG))
10184 if (SDValue Op = lowerVectorShuffleWithSHUFPD(DL, VT, Mask, V1, V2, DAG))
10187 // PERMILPD instruction - mask 0/1, 0/1, 2/3, 2/3, 4/5, 4/5, 6/7, 6/7
10188 if (isSingleInputShuffleMask(Mask)) {
10189 if (!is128BitLaneCrossingShuffleMask(VT, Mask))
10190 return DAG.getNode(X86ISD::VPERMILPI, DL, VT, V1,
10191 get1bitLaneShuffleImm8ForMask(Mask, DL, DAG));
10193 SmallVector<int, 4> RepeatedMask;
10194 if (is256BitLaneRepeatedShuffleMask(VT, Mask, RepeatedMask))
10195 return DAG.getNode(X86ISD::VPERMI, DL, VT, V1,
10196 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10198 return lowerVectorShuffleWithPERMV(DL, VT, Mask, V1, V2, DAG);
10201 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10202 static SDValue lowerV16X32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10203 const X86Subtarget *Subtarget,
10204 SelectionDAG &DAG) {
10205 MVT VT = Op.getSimpleValueType();
10207 assert((V1.getSimpleValueType() == MVT::v16i32 ||
10208 V1.getSimpleValueType() == MVT::v16f32) && "Bad operand type!");
10209 assert((V2.getSimpleValueType() == MVT::v16i32 ||
10210 V2.getSimpleValueType() == MVT::v16f32) && "Bad operand type!");
10211 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10212 ArrayRef<int> Mask = SVOp->getMask();
10213 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10215 // Use dedicated unpack instructions for masks that match their pattern.
10216 if (isShuffleEquivalent(V1, V2, Mask,
10217 {// First 128-bit lane.
10218 0, 16, 1, 17, 4, 20, 5, 21,
10219 // Second 128-bit lane.
10220 8, 24, 9, 25, 12, 28, 13, 29}))
10221 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
10222 if (isShuffleEquivalent(V1, V2, Mask,
10223 {// First 128-bit lane.
10224 2, 18, 3, 19, 6, 22, 7, 23,
10225 // Second 128-bit lane.
10226 10, 26, 11, 27, 14, 30, 15, 31}))
10227 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
10229 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10,
10231 return DAG.getNode(X86ISD::MOVSLDUP, DL, VT, V1);
10232 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7, 9, 9, 11, 11,
10234 return DAG.getNode(X86ISD::MOVSHDUP, DL, VT, V1);
10236 SmallVector<int, 4> RepeatedMask;
10237 if (is128BitLaneRepeatedShuffleMask(VT, Mask, RepeatedMask)) {
10238 if (isSingleInputShuffleMask(Mask)) {
10239 unsigned Opc = VT.isInteger() ? X86ISD::PSHUFD : X86ISD::VPERMILPI;
10240 return DAG.getNode(Opc, DL, VT, V1,
10241 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10244 for (int i = 0; i < 4; ++i) {
10245 if (RepeatedMask[i] >= 16)
10246 RepeatedMask[i] -= 12;
10248 return lowerVectorShuffleWithSHUFPS(DL, VT, RepeatedMask, V1, V2, DAG);
10251 if (SDValue Op = lowerVectorShuffleWithVALIGN(DL, VT, Mask, V1, V2, DAG))
10254 return lowerVectorShuffleWithPERMV(DL, VT, Mask, V1, V2, DAG);
10257 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10258 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10259 const X86Subtarget *Subtarget,
10260 SelectionDAG &DAG) {
10262 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10263 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10264 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10265 ArrayRef<int> Mask = SVOp->getMask();
10266 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10267 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10269 // FIXME: Implement direct support for this type!
10270 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10273 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10274 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10275 const X86Subtarget *Subtarget,
10276 SelectionDAG &DAG) {
10278 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10279 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10280 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10281 ArrayRef<int> Mask = SVOp->getMask();
10282 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10283 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10285 // FIXME: Implement direct support for this type!
10286 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10289 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10291 /// This routine either breaks down the specific type of a 512-bit x86 vector
10292 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10293 /// together based on the available instructions.
10294 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10295 MVT VT, const X86Subtarget *Subtarget,
10296 SelectionDAG &DAG) {
10298 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10299 ArrayRef<int> Mask = SVOp->getMask();
10300 assert(Subtarget->hasAVX512() &&
10301 "Cannot lower 512-bit vectors w/ basic ISA!");
10303 // Check for being able to broadcast a single element.
10304 if (SDValue Broadcast =
10305 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10308 // Dispatch to each element type for lowering. If we don't have supprot for
10309 // specific element type shuffles at 512 bits, immediately split them and
10310 // lower them. Each lowering routine of a given type is allowed to assume that
10311 // the requisite ISA extensions for that element type are available.
10312 switch (VT.SimpleTy) {
10315 return lowerV8X64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10318 return lowerV16X32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10320 if (Subtarget->hasBWI())
10321 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10324 if (Subtarget->hasBWI())
10325 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10329 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10332 // Otherwise fall back on splitting.
10333 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10336 /// \brief Top-level lowering for x86 vector shuffles.
10338 /// This handles decomposition, canonicalization, and lowering of all x86
10339 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10340 /// above in helper routines. The canonicalization attempts to widen shuffles
10341 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10342 /// s.t. only one of the two inputs needs to be tested, etc.
10343 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10344 SelectionDAG &DAG) {
10345 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10346 ArrayRef<int> Mask = SVOp->getMask();
10347 SDValue V1 = Op.getOperand(0);
10348 SDValue V2 = Op.getOperand(1);
10349 MVT VT = Op.getSimpleValueType();
10350 int NumElements = VT.getVectorNumElements();
10353 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10355 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10356 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10357 if (V1IsUndef && V2IsUndef)
10358 return DAG.getUNDEF(VT);
10360 // When we create a shuffle node we put the UNDEF node to second operand,
10361 // but in some cases the first operand may be transformed to UNDEF.
10362 // In this case we should just commute the node.
10364 return DAG.getCommutedVectorShuffle(*SVOp);
10366 // Check for non-undef masks pointing at an undef vector and make the masks
10367 // undef as well. This makes it easier to match the shuffle based solely on
10371 if (M >= NumElements) {
10372 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10373 for (int &M : NewMask)
10374 if (M >= NumElements)
10376 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10379 // We actually see shuffles that are entirely re-arrangements of a set of
10380 // zero inputs. This mostly happens while decomposing complex shuffles into
10381 // simple ones. Directly lower these as a buildvector of zeros.
10382 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10383 if (Zeroable.all())
10384 return getZeroVector(VT, Subtarget, DAG, dl);
10386 // Try to collapse shuffles into using a vector type with fewer elements but
10387 // wider element types. We cap this to not form integers or floating point
10388 // elements wider than 64 bits, but it might be interesting to form i128
10389 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10390 SmallVector<int, 16> WidenedMask;
10391 if (VT.getScalarSizeInBits() < 64 &&
10392 canWidenShuffleElements(Mask, WidenedMask)) {
10393 MVT NewEltVT = VT.isFloatingPoint()
10394 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10395 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10396 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10397 // Make sure that the new vector type is legal. For example, v2f64 isn't
10399 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10400 V1 = DAG.getBitcast(NewVT, V1);
10401 V2 = DAG.getBitcast(NewVT, V2);
10402 return DAG.getBitcast(
10403 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10407 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10408 for (int M : SVOp->getMask())
10410 ++NumUndefElements;
10411 else if (M < NumElements)
10416 // Commute the shuffle as needed such that more elements come from V1 than
10417 // V2. This allows us to match the shuffle pattern strictly on how many
10418 // elements come from V1 without handling the symmetric cases.
10419 if (NumV2Elements > NumV1Elements)
10420 return DAG.getCommutedVectorShuffle(*SVOp);
10422 // When the number of V1 and V2 elements are the same, try to minimize the
10423 // number of uses of V2 in the low half of the vector. When that is tied,
10424 // ensure that the sum of indices for V1 is equal to or lower than the sum
10425 // indices for V2. When those are equal, try to ensure that the number of odd
10426 // indices for V1 is lower than the number of odd indices for V2.
10427 if (NumV1Elements == NumV2Elements) {
10428 int LowV1Elements = 0, LowV2Elements = 0;
10429 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10430 if (M >= NumElements)
10434 if (LowV2Elements > LowV1Elements) {
10435 return DAG.getCommutedVectorShuffle(*SVOp);
10436 } else if (LowV2Elements == LowV1Elements) {
10437 int SumV1Indices = 0, SumV2Indices = 0;
10438 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10439 if (SVOp->getMask()[i] >= NumElements)
10441 else if (SVOp->getMask()[i] >= 0)
10443 if (SumV2Indices < SumV1Indices) {
10444 return DAG.getCommutedVectorShuffle(*SVOp);
10445 } else if (SumV2Indices == SumV1Indices) {
10446 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10447 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10448 if (SVOp->getMask()[i] >= NumElements)
10449 NumV2OddIndices += i % 2;
10450 else if (SVOp->getMask()[i] >= 0)
10451 NumV1OddIndices += i % 2;
10452 if (NumV2OddIndices < NumV1OddIndices)
10453 return DAG.getCommutedVectorShuffle(*SVOp);
10458 // For each vector width, delegate to a specialized lowering routine.
10459 if (VT.getSizeInBits() == 128)
10460 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10462 if (VT.getSizeInBits() == 256)
10463 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10465 // Force AVX-512 vectors to be scalarized for now.
10466 // FIXME: Implement AVX-512 support!
10467 if (VT.getSizeInBits() == 512)
10468 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10470 llvm_unreachable("Unimplemented!");
10473 // This function assumes its argument is a BUILD_VECTOR of constants or
10474 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10476 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10477 unsigned &MaskValue) {
10479 unsigned NumElems = BuildVector->getNumOperands();
10480 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10481 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10482 unsigned NumElemsInLane = NumElems / NumLanes;
10484 // Blend for v16i16 should be symetric for the both lanes.
10485 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10486 SDValue EltCond = BuildVector->getOperand(i);
10487 SDValue SndLaneEltCond =
10488 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10490 int Lane1Cond = -1, Lane2Cond = -1;
10491 if (isa<ConstantSDNode>(EltCond))
10492 Lane1Cond = !isZero(EltCond);
10493 if (isa<ConstantSDNode>(SndLaneEltCond))
10494 Lane2Cond = !isZero(SndLaneEltCond);
10496 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10497 // Lane1Cond != 0, means we want the first argument.
10498 // Lane1Cond == 0, means we want the second argument.
10499 // The encoding of this argument is 0 for the first argument, 1
10500 // for the second. Therefore, invert the condition.
10501 MaskValue |= !Lane1Cond << i;
10502 else if (Lane1Cond < 0)
10503 MaskValue |= !Lane2Cond << i;
10510 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10511 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10512 const X86Subtarget *Subtarget,
10513 SelectionDAG &DAG) {
10514 SDValue Cond = Op.getOperand(0);
10515 SDValue LHS = Op.getOperand(1);
10516 SDValue RHS = Op.getOperand(2);
10518 MVT VT = Op.getSimpleValueType();
10520 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10522 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10524 // Only non-legal VSELECTs reach this lowering, convert those into generic
10525 // shuffles and re-use the shuffle lowering path for blends.
10526 SmallVector<int, 32> Mask;
10527 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10528 SDValue CondElt = CondBV->getOperand(i);
10530 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10532 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10535 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10536 // A vselect where all conditions and data are constants can be optimized into
10537 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10538 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10539 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10540 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10543 // Try to lower this to a blend-style vector shuffle. This can handle all
10544 // constant condition cases.
10545 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10548 // Variable blends are only legal from SSE4.1 onward.
10549 if (!Subtarget->hasSSE41())
10552 // Only some types will be legal on some subtargets. If we can emit a legal
10553 // VSELECT-matching blend, return Op, and but if we need to expand, return
10555 switch (Op.getSimpleValueType().SimpleTy) {
10557 // Most of the vector types have blends past SSE4.1.
10561 // The byte blends for AVX vectors were introduced only in AVX2.
10562 if (Subtarget->hasAVX2())
10569 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10570 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10573 // FIXME: We should custom lower this by fixing the condition and using i8
10579 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10580 MVT VT = Op.getSimpleValueType();
10583 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10586 if (VT.getSizeInBits() == 8) {
10587 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10588 Op.getOperand(0), Op.getOperand(1));
10589 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10590 DAG.getValueType(VT));
10591 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10594 if (VT.getSizeInBits() == 16) {
10595 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10596 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10598 return DAG.getNode(
10599 ISD::TRUNCATE, dl, MVT::i16,
10600 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10601 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10602 Op.getOperand(1)));
10603 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10604 Op.getOperand(0), Op.getOperand(1));
10605 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10606 DAG.getValueType(VT));
10607 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10610 if (VT == MVT::f32) {
10611 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10612 // the result back to FR32 register. It's only worth matching if the
10613 // result has a single use which is a store or a bitcast to i32. And in
10614 // the case of a store, it's not worth it if the index is a constant 0,
10615 // because a MOVSSmr can be used instead, which is smaller and faster.
10616 if (!Op.hasOneUse())
10618 SDNode *User = *Op.getNode()->use_begin();
10619 if ((User->getOpcode() != ISD::STORE ||
10620 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10621 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10622 (User->getOpcode() != ISD::BITCAST ||
10623 User->getValueType(0) != MVT::i32))
10625 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10626 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10628 return DAG.getBitcast(MVT::f32, Extract);
10631 if (VT == MVT::i32 || VT == MVT::i64) {
10632 // ExtractPS/pextrq works with constant index.
10633 if (isa<ConstantSDNode>(Op.getOperand(1)))
10639 /// Extract one bit from mask vector, like v16i1 or v8i1.
10640 /// AVX-512 feature.
10642 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10643 SDValue Vec = Op.getOperand(0);
10645 MVT VecVT = Vec.getSimpleValueType();
10646 SDValue Idx = Op.getOperand(1);
10647 MVT EltVT = Op.getSimpleValueType();
10649 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10650 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10651 "Unexpected vector type in ExtractBitFromMaskVector");
10653 // variable index can't be handled in mask registers,
10654 // extend vector to VR512
10655 if (!isa<ConstantSDNode>(Idx)) {
10656 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10657 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10658 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10659 ExtVT.getVectorElementType(), Ext, Idx);
10660 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10663 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10664 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10665 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10666 rc = getRegClassFor(MVT::v16i1);
10667 unsigned MaxSift = rc->getSize()*8 - 1;
10668 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10669 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10670 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10671 DAG.getConstant(MaxSift, dl, MVT::i8));
10672 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10673 DAG.getIntPtrConstant(0, dl));
10677 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10678 SelectionDAG &DAG) const {
10680 SDValue Vec = Op.getOperand(0);
10681 MVT VecVT = Vec.getSimpleValueType();
10682 SDValue Idx = Op.getOperand(1);
10684 if (Op.getSimpleValueType() == MVT::i1)
10685 return ExtractBitFromMaskVector(Op, DAG);
10687 if (!isa<ConstantSDNode>(Idx)) {
10688 if (VecVT.is512BitVector() ||
10689 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10690 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10693 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10694 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10695 MaskEltVT.getSizeInBits());
10697 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10698 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10699 getZeroVector(MaskVT, Subtarget, DAG, dl),
10700 Idx, DAG.getConstant(0, dl, getPointerTy()));
10701 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10702 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10703 Perm, DAG.getConstant(0, dl, getPointerTy()));
10708 // If this is a 256-bit vector result, first extract the 128-bit vector and
10709 // then extract the element from the 128-bit vector.
10710 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10712 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10713 // Get the 128-bit vector.
10714 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10715 MVT EltVT = VecVT.getVectorElementType();
10717 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10719 //if (IdxVal >= NumElems/2)
10720 // IdxVal -= NumElems/2;
10721 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10722 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10723 DAG.getConstant(IdxVal, dl, MVT::i32));
10726 assert(VecVT.is128BitVector() && "Unexpected vector length");
10728 if (Subtarget->hasSSE41()) {
10729 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10734 MVT VT = Op.getSimpleValueType();
10735 // TODO: handle v16i8.
10736 if (VT.getSizeInBits() == 16) {
10737 SDValue Vec = Op.getOperand(0);
10738 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10740 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10741 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10742 DAG.getBitcast(MVT::v4i32, Vec),
10743 Op.getOperand(1)));
10744 // Transform it so it match pextrw which produces a 32-bit result.
10745 MVT EltVT = MVT::i32;
10746 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10747 Op.getOperand(0), Op.getOperand(1));
10748 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10749 DAG.getValueType(VT));
10750 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10753 if (VT.getSizeInBits() == 32) {
10754 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10758 // SHUFPS the element to the lowest double word, then movss.
10759 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10760 MVT VVT = Op.getOperand(0).getSimpleValueType();
10761 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10762 DAG.getUNDEF(VVT), Mask);
10763 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10764 DAG.getIntPtrConstant(0, dl));
10767 if (VT.getSizeInBits() == 64) {
10768 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10769 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10770 // to match extract_elt for f64.
10771 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10775 // UNPCKHPD the element to the lowest double word, then movsd.
10776 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10777 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10778 int Mask[2] = { 1, -1 };
10779 MVT VVT = Op.getOperand(0).getSimpleValueType();
10780 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10781 DAG.getUNDEF(VVT), Mask);
10782 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10783 DAG.getIntPtrConstant(0, dl));
10789 /// Insert one bit to mask vector, like v16i1 or v8i1.
10790 /// AVX-512 feature.
10792 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10794 SDValue Vec = Op.getOperand(0);
10795 SDValue Elt = Op.getOperand(1);
10796 SDValue Idx = Op.getOperand(2);
10797 MVT VecVT = Vec.getSimpleValueType();
10799 if (!isa<ConstantSDNode>(Idx)) {
10800 // Non constant index. Extend source and destination,
10801 // insert element and then truncate the result.
10802 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10803 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10804 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10805 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10806 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10807 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10810 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10811 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10813 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10814 DAG.getConstant(IdxVal, dl, MVT::i8));
10815 if (Vec.getOpcode() == ISD::UNDEF)
10817 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10820 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10821 SelectionDAG &DAG) const {
10822 MVT VT = Op.getSimpleValueType();
10823 MVT EltVT = VT.getVectorElementType();
10825 if (EltVT == MVT::i1)
10826 return InsertBitToMaskVector(Op, DAG);
10829 SDValue N0 = Op.getOperand(0);
10830 SDValue N1 = Op.getOperand(1);
10831 SDValue N2 = Op.getOperand(2);
10832 if (!isa<ConstantSDNode>(N2))
10834 auto *N2C = cast<ConstantSDNode>(N2);
10835 unsigned IdxVal = N2C->getZExtValue();
10837 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10838 // into that, and then insert the subvector back into the result.
10839 if (VT.is256BitVector() || VT.is512BitVector()) {
10840 // With a 256-bit vector, we can insert into the zero element efficiently
10841 // using a blend if we have AVX or AVX2 and the right data type.
10842 if (VT.is256BitVector() && IdxVal == 0) {
10843 // TODO: It is worthwhile to cast integer to floating point and back
10844 // and incur a domain crossing penalty if that's what we'll end up
10845 // doing anyway after extracting to a 128-bit vector.
10846 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
10847 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
10848 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
10849 N2 = DAG.getIntPtrConstant(1, dl);
10850 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
10854 // Get the desired 128-bit vector chunk.
10855 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10857 // Insert the element into the desired chunk.
10858 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10859 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
10861 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10862 DAG.getConstant(IdxIn128, dl, MVT::i32));
10864 // Insert the changed part back into the bigger vector
10865 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10867 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
10869 if (Subtarget->hasSSE41()) {
10870 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
10872 if (VT == MVT::v8i16) {
10873 Opc = X86ISD::PINSRW;
10875 assert(VT == MVT::v16i8);
10876 Opc = X86ISD::PINSRB;
10879 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10881 if (N1.getValueType() != MVT::i32)
10882 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10883 if (N2.getValueType() != MVT::i32)
10884 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10885 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10888 if (EltVT == MVT::f32) {
10889 // Bits [7:6] of the constant are the source select. This will always be
10890 // zero here. The DAG Combiner may combine an extract_elt index into
10891 // these bits. For example (insert (extract, 3), 2) could be matched by
10892 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
10893 // Bits [5:4] of the constant are the destination select. This is the
10894 // value of the incoming immediate.
10895 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10896 // combine either bitwise AND or insert of float 0.0 to set these bits.
10898 const Function *F = DAG.getMachineFunction().getFunction();
10899 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
10900 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
10901 // If this is an insertion of 32-bits into the low 32-bits of
10902 // a vector, we prefer to generate a blend with immediate rather
10903 // than an insertps. Blends are simpler operations in hardware and so
10904 // will always have equal or better performance than insertps.
10905 // But if optimizing for size and there's a load folding opportunity,
10906 // generate insertps because blendps does not have a 32-bit memory
10908 N2 = DAG.getIntPtrConstant(1, dl);
10909 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10910 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
10912 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
10913 // Create this as a scalar to vector..
10914 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10915 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10918 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
10919 // PINSR* works with constant index.
10924 if (EltVT == MVT::i8)
10927 if (EltVT.getSizeInBits() == 16) {
10928 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10929 // as its second argument.
10930 if (N1.getValueType() != MVT::i32)
10931 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10932 if (N2.getValueType() != MVT::i32)
10933 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10934 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10939 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10941 MVT OpVT = Op.getSimpleValueType();
10943 // If this is a 256-bit vector result, first insert into a 128-bit
10944 // vector and then insert into the 256-bit vector.
10945 if (!OpVT.is128BitVector()) {
10946 // Insert into a 128-bit vector.
10947 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10948 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10949 OpVT.getVectorNumElements() / SizeFactor);
10951 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10953 // Insert the 128-bit vector.
10954 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10957 if (OpVT == MVT::v1i64 &&
10958 Op.getOperand(0).getValueType() == MVT::i64)
10959 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10961 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10962 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10963 return DAG.getBitcast(
10964 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
10967 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10968 // a simple subregister reference or explicit instructions to grab
10969 // upper bits of a vector.
10970 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10971 SelectionDAG &DAG) {
10973 SDValue In = Op.getOperand(0);
10974 SDValue Idx = Op.getOperand(1);
10975 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10976 MVT ResVT = Op.getSimpleValueType();
10977 MVT InVT = In.getSimpleValueType();
10979 if (Subtarget->hasFp256()) {
10980 if (ResVT.is128BitVector() &&
10981 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10982 isa<ConstantSDNode>(Idx)) {
10983 return Extract128BitVector(In, IdxVal, DAG, dl);
10985 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10986 isa<ConstantSDNode>(Idx)) {
10987 return Extract256BitVector(In, IdxVal, DAG, dl);
10993 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10994 // simple superregister reference or explicit instructions to insert
10995 // the upper bits of a vector.
10996 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10997 SelectionDAG &DAG) {
10998 if (!Subtarget->hasAVX())
11002 SDValue Vec = Op.getOperand(0);
11003 SDValue SubVec = Op.getOperand(1);
11004 SDValue Idx = Op.getOperand(2);
11006 if (!isa<ConstantSDNode>(Idx))
11009 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11010 MVT OpVT = Op.getSimpleValueType();
11011 MVT SubVecVT = SubVec.getSimpleValueType();
11013 // Fold two 16-byte subvector loads into one 32-byte load:
11014 // (insert_subvector (insert_subvector undef, (load addr), 0),
11015 // (load addr + 16), Elts/2)
11017 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11018 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11019 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
11020 !Subtarget->isUnalignedMem32Slow()) {
11021 SDValue SubVec2 = Vec.getOperand(1);
11022 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
11023 if (Idx2->getZExtValue() == 0) {
11024 SDValue Ops[] = { SubVec2, SubVec };
11025 SDValue LD = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false);
11032 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11033 SubVecVT.is128BitVector())
11034 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11036 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11037 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11039 if (OpVT.getVectorElementType() == MVT::i1) {
11040 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11042 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11043 SDValue Undef = DAG.getUNDEF(OpVT);
11044 unsigned NumElems = OpVT.getVectorNumElements();
11045 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11047 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11048 // Zero upper bits of the Vec
11049 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11050 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11052 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11054 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11055 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11058 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11060 // Zero upper bits of the Vec2
11061 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11062 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11063 // Zero lower bits of the Vec
11064 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11065 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11066 // Merge them together
11067 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11073 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11074 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11075 // one of the above mentioned nodes. It has to be wrapped because otherwise
11076 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11077 // be used to form addressing mode. These wrapped nodes will be selected
11080 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11081 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11083 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11084 // global base reg.
11085 unsigned char OpFlag = 0;
11086 unsigned WrapperKind = X86ISD::Wrapper;
11087 CodeModel::Model M = DAG.getTarget().getCodeModel();
11089 if (Subtarget->isPICStyleRIPRel() &&
11090 (M == CodeModel::Small || M == CodeModel::Kernel))
11091 WrapperKind = X86ISD::WrapperRIP;
11092 else if (Subtarget->isPICStyleGOT())
11093 OpFlag = X86II::MO_GOTOFF;
11094 else if (Subtarget->isPICStyleStubPIC())
11095 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11097 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11098 CP->getAlignment(),
11099 CP->getOffset(), OpFlag);
11101 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11102 // With PIC, the address is actually $g + Offset.
11104 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11105 DAG.getNode(X86ISD::GlobalBaseReg,
11106 SDLoc(), getPointerTy()),
11113 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11114 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11116 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11117 // global base reg.
11118 unsigned char OpFlag = 0;
11119 unsigned WrapperKind = X86ISD::Wrapper;
11120 CodeModel::Model M = DAG.getTarget().getCodeModel();
11122 if (Subtarget->isPICStyleRIPRel() &&
11123 (M == CodeModel::Small || M == CodeModel::Kernel))
11124 WrapperKind = X86ISD::WrapperRIP;
11125 else if (Subtarget->isPICStyleGOT())
11126 OpFlag = X86II::MO_GOTOFF;
11127 else if (Subtarget->isPICStyleStubPIC())
11128 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11130 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11133 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11135 // With PIC, the address is actually $g + Offset.
11137 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11138 DAG.getNode(X86ISD::GlobalBaseReg,
11139 SDLoc(), getPointerTy()),
11146 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11147 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11149 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11150 // global base reg.
11151 unsigned char OpFlag = 0;
11152 unsigned WrapperKind = X86ISD::Wrapper;
11153 CodeModel::Model M = DAG.getTarget().getCodeModel();
11155 if (Subtarget->isPICStyleRIPRel() &&
11156 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11157 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11158 OpFlag = X86II::MO_GOTPCREL;
11159 WrapperKind = X86ISD::WrapperRIP;
11160 } else if (Subtarget->isPICStyleGOT()) {
11161 OpFlag = X86II::MO_GOT;
11162 } else if (Subtarget->isPICStyleStubPIC()) {
11163 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11164 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11165 OpFlag = X86II::MO_DARWIN_NONLAZY;
11168 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11171 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11173 // With PIC, the address is actually $g + Offset.
11174 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11175 !Subtarget->is64Bit()) {
11176 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11177 DAG.getNode(X86ISD::GlobalBaseReg,
11178 SDLoc(), getPointerTy()),
11182 // For symbols that require a load from a stub to get the address, emit the
11184 if (isGlobalStubReference(OpFlag))
11185 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11186 MachinePointerInfo::getGOT(), false, false, false, 0);
11192 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11193 // Create the TargetBlockAddressAddress node.
11194 unsigned char OpFlags =
11195 Subtarget->ClassifyBlockAddressReference();
11196 CodeModel::Model M = DAG.getTarget().getCodeModel();
11197 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11198 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11200 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11203 if (Subtarget->isPICStyleRIPRel() &&
11204 (M == CodeModel::Small || M == CodeModel::Kernel))
11205 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11207 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11209 // With PIC, the address is actually $g + Offset.
11210 if (isGlobalRelativeToPICBase(OpFlags)) {
11211 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11212 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11220 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11221 int64_t Offset, SelectionDAG &DAG) const {
11222 // Create the TargetGlobalAddress node, folding in the constant
11223 // offset if it is legal.
11224 unsigned char OpFlags =
11225 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11226 CodeModel::Model M = DAG.getTarget().getCodeModel();
11228 if (OpFlags == X86II::MO_NO_FLAG &&
11229 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11230 // A direct static reference to a global.
11231 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11234 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11237 if (Subtarget->isPICStyleRIPRel() &&
11238 (M == CodeModel::Small || M == CodeModel::Kernel))
11239 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11241 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11243 // With PIC, the address is actually $g + Offset.
11244 if (isGlobalRelativeToPICBase(OpFlags)) {
11245 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11246 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11250 // For globals that require a load from a stub to get the address, emit the
11252 if (isGlobalStubReference(OpFlags))
11253 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11254 MachinePointerInfo::getGOT(), false, false, false, 0);
11256 // If there was a non-zero offset that we didn't fold, create an explicit
11257 // addition for it.
11259 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11260 DAG.getConstant(Offset, dl, getPointerTy()));
11266 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11267 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11268 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11269 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11273 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11274 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11275 unsigned char OperandFlags, bool LocalDynamic = false) {
11276 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11277 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11279 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11280 GA->getValueType(0),
11284 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11288 SDValue Ops[] = { Chain, TGA, *InFlag };
11289 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11291 SDValue Ops[] = { Chain, TGA };
11292 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11295 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11296 MFI->setAdjustsStack(true);
11297 MFI->setHasCalls(true);
11299 SDValue Flag = Chain.getValue(1);
11300 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11303 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11305 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11308 SDLoc dl(GA); // ? function entry point might be better
11309 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11310 DAG.getNode(X86ISD::GlobalBaseReg,
11311 SDLoc(), PtrVT), InFlag);
11312 InFlag = Chain.getValue(1);
11314 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11317 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11319 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11321 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11322 X86::RAX, X86II::MO_TLSGD);
11325 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11331 // Get the start address of the TLS block for this module.
11332 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11333 .getInfo<X86MachineFunctionInfo>();
11334 MFI->incNumLocalDynamicTLSAccesses();
11338 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11339 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11342 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11343 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11344 InFlag = Chain.getValue(1);
11345 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11346 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11349 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11353 unsigned char OperandFlags = X86II::MO_DTPOFF;
11354 unsigned WrapperKind = X86ISD::Wrapper;
11355 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11356 GA->getValueType(0),
11357 GA->getOffset(), OperandFlags);
11358 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11360 // Add x@dtpoff with the base.
11361 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11364 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11365 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11366 const EVT PtrVT, TLSModel::Model model,
11367 bool is64Bit, bool isPIC) {
11370 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11371 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11372 is64Bit ? 257 : 256));
11374 SDValue ThreadPointer =
11375 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11376 MachinePointerInfo(Ptr), false, false, false, 0);
11378 unsigned char OperandFlags = 0;
11379 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11381 unsigned WrapperKind = X86ISD::Wrapper;
11382 if (model == TLSModel::LocalExec) {
11383 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11384 } else if (model == TLSModel::InitialExec) {
11386 OperandFlags = X86II::MO_GOTTPOFF;
11387 WrapperKind = X86ISD::WrapperRIP;
11389 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11392 llvm_unreachable("Unexpected model");
11395 // emit "addl x@ntpoff,%eax" (local exec)
11396 // or "addl x@indntpoff,%eax" (initial exec)
11397 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11399 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11400 GA->getOffset(), OperandFlags);
11401 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11403 if (model == TLSModel::InitialExec) {
11404 if (isPIC && !is64Bit) {
11405 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11406 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11410 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11411 MachinePointerInfo::getGOT(), false, false, false, 0);
11414 // The address of the thread local variable is the add of the thread
11415 // pointer with the offset of the variable.
11416 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11420 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11422 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11423 const GlobalValue *GV = GA->getGlobal();
11425 if (Subtarget->isTargetELF()) {
11426 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11428 case TLSModel::GeneralDynamic:
11429 if (Subtarget->is64Bit())
11430 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11431 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11432 case TLSModel::LocalDynamic:
11433 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11434 Subtarget->is64Bit());
11435 case TLSModel::InitialExec:
11436 case TLSModel::LocalExec:
11437 return LowerToTLSExecModel(
11438 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11439 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11441 llvm_unreachable("Unknown TLS model.");
11444 if (Subtarget->isTargetDarwin()) {
11445 // Darwin only has one model of TLS. Lower to that.
11446 unsigned char OpFlag = 0;
11447 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11448 X86ISD::WrapperRIP : X86ISD::Wrapper;
11450 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11451 // global base reg.
11452 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11453 !Subtarget->is64Bit();
11455 OpFlag = X86II::MO_TLVP_PIC_BASE;
11457 OpFlag = X86II::MO_TLVP;
11459 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11460 GA->getValueType(0),
11461 GA->getOffset(), OpFlag);
11462 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11464 // With PIC32, the address is actually $g + Offset.
11466 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11467 DAG.getNode(X86ISD::GlobalBaseReg,
11468 SDLoc(), getPointerTy()),
11471 // Lowering the machine isd will make sure everything is in the right
11473 SDValue Chain = DAG.getEntryNode();
11474 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11475 SDValue Args[] = { Chain, Offset };
11476 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11478 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11479 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11480 MFI->setAdjustsStack(true);
11482 // And our return value (tls address) is in the standard call return value
11484 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11485 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11486 Chain.getValue(1));
11489 if (Subtarget->isTargetKnownWindowsMSVC() ||
11490 Subtarget->isTargetWindowsGNU()) {
11491 // Just use the implicit TLS architecture
11492 // Need to generate someting similar to:
11493 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11495 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11496 // mov rcx, qword [rdx+rcx*8]
11497 // mov eax, .tls$:tlsvar
11498 // [rax+rcx] contains the address
11499 // Windows 64bit: gs:0x58
11500 // Windows 32bit: fs:__tls_array
11503 SDValue Chain = DAG.getEntryNode();
11505 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11506 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11507 // use its literal value of 0x2C.
11508 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11509 ? Type::getInt8PtrTy(*DAG.getContext(),
11511 : Type::getInt32PtrTy(*DAG.getContext(),
11515 Subtarget->is64Bit()
11516 ? DAG.getIntPtrConstant(0x58, dl)
11517 : (Subtarget->isTargetWindowsGNU()
11518 ? DAG.getIntPtrConstant(0x2C, dl)
11519 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11521 SDValue ThreadPointer =
11522 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11523 MachinePointerInfo(Ptr), false, false, false, 0);
11526 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
11527 res = ThreadPointer;
11529 // Load the _tls_index variable
11530 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11531 if (Subtarget->is64Bit())
11532 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, IDX,
11533 MachinePointerInfo(), MVT::i32, false, false,
11536 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11537 false, false, false, 0);
11539 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), dl,
11541 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11543 res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11546 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11547 false, false, false, 0);
11549 // Get the offset of start of .tls section
11550 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11551 GA->getValueType(0),
11552 GA->getOffset(), X86II::MO_SECREL);
11553 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11555 // The address of the thread local variable is the add of the thread
11556 // pointer with the offset of the variable.
11557 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11560 llvm_unreachable("TLS not implemented for this target.");
11563 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11564 /// and take a 2 x i32 value to shift plus a shift amount.
11565 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11566 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11567 MVT VT = Op.getSimpleValueType();
11568 unsigned VTBits = VT.getSizeInBits();
11570 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11571 SDValue ShOpLo = Op.getOperand(0);
11572 SDValue ShOpHi = Op.getOperand(1);
11573 SDValue ShAmt = Op.getOperand(2);
11574 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11575 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11577 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11578 DAG.getConstant(VTBits - 1, dl, MVT::i8));
11579 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11580 DAG.getConstant(VTBits - 1, dl, MVT::i8))
11581 : DAG.getConstant(0, dl, VT);
11583 SDValue Tmp2, Tmp3;
11584 if (Op.getOpcode() == ISD::SHL_PARTS) {
11585 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11586 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11588 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11589 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11592 // If the shift amount is larger or equal than the width of a part we can't
11593 // rely on the results of shld/shrd. Insert a test and select the appropriate
11594 // values for large shift amounts.
11595 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11596 DAG.getConstant(VTBits, dl, MVT::i8));
11597 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11598 AndNode, DAG.getConstant(0, dl, MVT::i8));
11601 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
11602 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11603 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11605 if (Op.getOpcode() == ISD::SHL_PARTS) {
11606 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11607 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11609 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11610 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11613 SDValue Ops[2] = { Lo, Hi };
11614 return DAG.getMergeValues(Ops, dl);
11617 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11618 SelectionDAG &DAG) const {
11619 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11622 if (SrcVT.isVector()) {
11623 if (SrcVT.getVectorElementType() == MVT::i1) {
11624 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11625 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11626 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
11627 Op.getOperand(0)));
11632 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11633 "Unknown SINT_TO_FP to lower!");
11635 // These are really Legal; return the operand so the caller accepts it as
11637 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11639 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11640 Subtarget->is64Bit()) {
11644 unsigned Size = SrcVT.getSizeInBits()/8;
11645 MachineFunction &MF = DAG.getMachineFunction();
11646 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11647 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11648 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11650 MachinePointerInfo::getFixedStack(SSFI),
11652 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11655 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11657 SelectionDAG &DAG) const {
11661 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11663 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11665 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11667 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11669 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11670 MachineMemOperand *MMO;
11672 int SSFI = FI->getIndex();
11674 DAG.getMachineFunction()
11675 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11676 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11678 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11679 StackSlot = StackSlot.getOperand(1);
11681 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11682 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11684 Tys, Ops, SrcVT, MMO);
11687 Chain = Result.getValue(1);
11688 SDValue InFlag = Result.getValue(2);
11690 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11691 // shouldn't be necessary except that RFP cannot be live across
11692 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11693 MachineFunction &MF = DAG.getMachineFunction();
11694 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11695 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11696 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11697 Tys = DAG.getVTList(MVT::Other);
11699 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11701 MachineMemOperand *MMO =
11702 DAG.getMachineFunction()
11703 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11704 MachineMemOperand::MOStore, SSFISize, SSFISize);
11706 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11707 Ops, Op.getValueType(), MMO);
11708 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11709 MachinePointerInfo::getFixedStack(SSFI),
11710 false, false, false, 0);
11716 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11717 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11718 SelectionDAG &DAG) const {
11719 // This algorithm is not obvious. Here it is what we're trying to output:
11722 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11723 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11725 haddpd %xmm0, %xmm0
11727 pshufd $0x4e, %xmm0, %xmm1
11733 LLVMContext *Context = DAG.getContext();
11735 // Build some magic constants.
11736 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11737 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11738 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11740 SmallVector<Constant*,2> CV1;
11742 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11743 APInt(64, 0x4330000000000000ULL))));
11745 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11746 APInt(64, 0x4530000000000000ULL))));
11747 Constant *C1 = ConstantVector::get(CV1);
11748 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11750 // Load the 64-bit value into an XMM register.
11751 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11753 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11754 MachinePointerInfo::getConstantPool(),
11755 false, false, false, 16);
11757 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
11759 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11760 MachinePointerInfo::getConstantPool(),
11761 false, false, false, 16);
11762 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
11763 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11766 if (Subtarget->hasSSE3()) {
11767 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11768 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11770 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
11771 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11773 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11774 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
11777 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11778 DAG.getIntPtrConstant(0, dl));
11781 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11782 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11783 SelectionDAG &DAG) const {
11785 // FP constant to bias correct the final result.
11786 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
11789 // Load the 32-bit value into an XMM register.
11790 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11793 // Zero out the upper parts of the register.
11794 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11796 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11797 DAG.getBitcast(MVT::v2f64, Load),
11798 DAG.getIntPtrConstant(0, dl));
11800 // Or the load with the bias.
11801 SDValue Or = DAG.getNode(
11802 ISD::OR, dl, MVT::v2i64,
11803 DAG.getBitcast(MVT::v2i64,
11804 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
11805 DAG.getBitcast(MVT::v2i64,
11806 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
11808 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11809 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
11811 // Subtract the bias.
11812 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11814 // Handle final rounding.
11815 EVT DestVT = Op.getValueType();
11817 if (DestVT.bitsLT(MVT::f64))
11818 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11819 DAG.getIntPtrConstant(0, dl));
11820 if (DestVT.bitsGT(MVT::f64))
11821 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11823 // Handle final rounding.
11827 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11828 const X86Subtarget &Subtarget) {
11829 // The algorithm is the following:
11830 // #ifdef __SSE4_1__
11831 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11832 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11833 // (uint4) 0x53000000, 0xaa);
11835 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11836 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11838 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11839 // return (float4) lo + fhi;
11842 SDValue V = Op->getOperand(0);
11843 EVT VecIntVT = V.getValueType();
11844 bool Is128 = VecIntVT == MVT::v4i32;
11845 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
11846 // If we convert to something else than the supported type, e.g., to v4f64,
11848 if (VecFloatVT != Op->getValueType(0))
11851 unsigned NumElts = VecIntVT.getVectorNumElements();
11852 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
11853 "Unsupported custom type");
11854 assert(NumElts <= 8 && "The size of the constant array must be fixed");
11856 // In the #idef/#else code, we have in common:
11857 // - The vector of constants:
11863 // Create the splat vector for 0x4b000000.
11864 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
11865 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
11866 CstLow, CstLow, CstLow, CstLow};
11867 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11868 makeArrayRef(&CstLowArray[0], NumElts));
11869 // Create the splat vector for 0x53000000.
11870 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
11871 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
11872 CstHigh, CstHigh, CstHigh, CstHigh};
11873 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11874 makeArrayRef(&CstHighArray[0], NumElts));
11876 // Create the right shift.
11877 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
11878 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
11879 CstShift, CstShift, CstShift, CstShift};
11880 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11881 makeArrayRef(&CstShiftArray[0], NumElts));
11882 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
11885 if (Subtarget.hasSSE41()) {
11886 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
11887 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11888 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
11889 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
11890 // Low will be bitcasted right away, so do not bother bitcasting back to its
11892 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
11893 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11894 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11895 // (uint4) 0x53000000, 0xaa);
11896 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
11897 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
11898 // High will be bitcasted right away, so do not bother bitcasting back to
11899 // its original type.
11900 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
11901 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11903 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
11904 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
11905 CstMask, CstMask, CstMask);
11906 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11907 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
11908 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
11910 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11911 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
11914 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
11915 SDValue CstFAdd = DAG.getConstantFP(
11916 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
11917 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
11918 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
11919 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
11920 makeArrayRef(&CstFAddArray[0], NumElts));
11922 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11923 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
11925 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
11926 // return (float4) lo + fhi;
11927 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
11928 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
11931 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11932 SelectionDAG &DAG) const {
11933 SDValue N0 = Op.getOperand(0);
11934 MVT SVT = N0.getSimpleValueType();
11937 switch (SVT.SimpleTy) {
11939 llvm_unreachable("Custom UINT_TO_FP is not supported!");
11944 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11945 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11946 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11950 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
11953 if (Subtarget->hasAVX512())
11954 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
11955 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
11957 llvm_unreachable(nullptr);
11960 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11961 SelectionDAG &DAG) const {
11962 SDValue N0 = Op.getOperand(0);
11965 if (Op.getValueType().isVector())
11966 return lowerUINT_TO_FP_vec(Op, DAG);
11968 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11969 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11970 // the optimization here.
11971 if (DAG.SignBitIsZero(N0))
11972 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11974 MVT SrcVT = N0.getSimpleValueType();
11975 MVT DstVT = Op.getSimpleValueType();
11976 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11977 return LowerUINT_TO_FP_i64(Op, DAG);
11978 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11979 return LowerUINT_TO_FP_i32(Op, DAG);
11980 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11983 // Make a 64-bit buffer, and use it to build an FILD.
11984 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11985 if (SrcVT == MVT::i32) {
11986 SDValue WordOff = DAG.getConstant(4, dl, getPointerTy());
11987 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11988 getPointerTy(), StackSlot, WordOff);
11989 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11990 StackSlot, MachinePointerInfo(),
11992 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
11993 OffsetSlot, MachinePointerInfo(),
11995 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11999 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12000 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12001 StackSlot, MachinePointerInfo(),
12003 // For i64 source, we need to add the appropriate power of 2 if the input
12004 // was negative. This is the same as the optimization in
12005 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12006 // we must be careful to do the computation in x87 extended precision, not
12007 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12008 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12009 MachineMemOperand *MMO =
12010 DAG.getMachineFunction()
12011 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12012 MachineMemOperand::MOLoad, 8, 8);
12014 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12015 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12016 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12019 APInt FF(32, 0x5F800000ULL);
12021 // Check whether the sign bit is set.
12022 SDValue SignSet = DAG.getSetCC(dl,
12023 getSetCCResultType(*DAG.getContext(), MVT::i64),
12025 DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12027 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12028 SDValue FudgePtr = DAG.getConstantPool(
12029 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
12032 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12033 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12034 SDValue Four = DAG.getIntPtrConstant(4, dl);
12035 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12037 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
12039 // Load the value out, extending it from f32 to f80.
12040 // FIXME: Avoid the extend by constructing the right constant pool?
12041 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12042 FudgePtr, MachinePointerInfo::getConstantPool(),
12043 MVT::f32, false, false, false, 4);
12044 // Extend everything to 80 bits to force it to be done on x87.
12045 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12046 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12047 DAG.getIntPtrConstant(0, dl));
12050 std::pair<SDValue,SDValue>
12051 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12052 bool IsSigned, bool IsReplace) const {
12055 EVT DstTy = Op.getValueType();
12057 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12058 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12062 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12063 DstTy.getSimpleVT() >= MVT::i16 &&
12064 "Unknown FP_TO_INT to lower!");
12066 // These are really Legal.
12067 if (DstTy == MVT::i32 &&
12068 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12069 return std::make_pair(SDValue(), SDValue());
12070 if (Subtarget->is64Bit() &&
12071 DstTy == MVT::i64 &&
12072 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12073 return std::make_pair(SDValue(), SDValue());
12075 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12076 // stack slot, or into the FTOL runtime function.
12077 MachineFunction &MF = DAG.getMachineFunction();
12078 unsigned MemSize = DstTy.getSizeInBits()/8;
12079 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12080 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12083 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12084 Opc = X86ISD::WIN_FTOL;
12086 switch (DstTy.getSimpleVT().SimpleTy) {
12087 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12088 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12089 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12090 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12093 SDValue Chain = DAG.getEntryNode();
12094 SDValue Value = Op.getOperand(0);
12095 EVT TheVT = Op.getOperand(0).getValueType();
12096 // FIXME This causes a redundant load/store if the SSE-class value is already
12097 // in memory, such as if it is on the callstack.
12098 if (isScalarFPTypeInSSEReg(TheVT)) {
12099 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12100 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12101 MachinePointerInfo::getFixedStack(SSFI),
12103 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12105 Chain, StackSlot, DAG.getValueType(TheVT)
12108 MachineMemOperand *MMO =
12109 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12110 MachineMemOperand::MOLoad, MemSize, MemSize);
12111 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12112 Chain = Value.getValue(1);
12113 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12114 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12117 MachineMemOperand *MMO =
12118 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12119 MachineMemOperand::MOStore, MemSize, MemSize);
12121 if (Opc != X86ISD::WIN_FTOL) {
12122 // Build the FP_TO_INT*_IN_MEM
12123 SDValue Ops[] = { Chain, Value, StackSlot };
12124 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12126 return std::make_pair(FIST, StackSlot);
12128 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12129 DAG.getVTList(MVT::Other, MVT::Glue),
12131 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12132 MVT::i32, ftol.getValue(1));
12133 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12134 MVT::i32, eax.getValue(2));
12135 SDValue Ops[] = { eax, edx };
12136 SDValue pair = IsReplace
12137 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12138 : DAG.getMergeValues(Ops, DL);
12139 return std::make_pair(pair, SDValue());
12143 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12144 const X86Subtarget *Subtarget) {
12145 MVT VT = Op->getSimpleValueType(0);
12146 SDValue In = Op->getOperand(0);
12147 MVT InVT = In.getSimpleValueType();
12150 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12151 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12153 // Optimize vectors in AVX mode:
12156 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12157 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12158 // Concat upper and lower parts.
12161 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12162 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12163 // Concat upper and lower parts.
12166 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12167 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12168 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12171 if (Subtarget->hasInt256())
12172 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12174 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12175 SDValue Undef = DAG.getUNDEF(InVT);
12176 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12177 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12178 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12180 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12181 VT.getVectorNumElements()/2);
12183 OpLo = DAG.getBitcast(HVT, OpLo);
12184 OpHi = DAG.getBitcast(HVT, OpHi);
12186 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12189 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12190 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12191 MVT VT = Op->getSimpleValueType(0);
12192 SDValue In = Op->getOperand(0);
12193 MVT InVT = In.getSimpleValueType();
12195 unsigned int NumElts = VT.getVectorNumElements();
12196 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12199 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12200 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12202 assert(InVT.getVectorElementType() == MVT::i1);
12203 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12205 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12207 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12209 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12210 if (VT.is512BitVector())
12212 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12215 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12216 SelectionDAG &DAG) {
12217 if (Subtarget->hasFp256()) {
12218 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12226 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12227 SelectionDAG &DAG) {
12229 MVT VT = Op.getSimpleValueType();
12230 SDValue In = Op.getOperand(0);
12231 MVT SVT = In.getSimpleValueType();
12233 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12234 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12236 if (Subtarget->hasFp256()) {
12237 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12242 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12243 VT.getVectorNumElements() != SVT.getVectorNumElements());
12247 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12249 MVT VT = Op.getSimpleValueType();
12250 SDValue In = Op.getOperand(0);
12251 MVT InVT = In.getSimpleValueType();
12253 if (VT == MVT::i1) {
12254 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12255 "Invalid scalar TRUNCATE operation");
12256 if (InVT.getSizeInBits() >= 32)
12258 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12259 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12261 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12262 "Invalid TRUNCATE operation");
12264 // move vector to mask - truncate solution for SKX
12265 if (VT.getVectorElementType() == MVT::i1) {
12266 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12267 Subtarget->hasBWI())
12268 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12269 if ((InVT.is256BitVector() || InVT.is128BitVector())
12270 && InVT.getScalarSizeInBits() <= 16 &&
12271 Subtarget->hasBWI() && Subtarget->hasVLX())
12272 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12273 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12274 Subtarget->hasDQI())
12275 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12276 if ((InVT.is256BitVector() || InVT.is128BitVector())
12277 && InVT.getScalarSizeInBits() >= 32 &&
12278 Subtarget->hasDQI() && Subtarget->hasVLX())
12279 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12281 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12282 if (VT.getVectorElementType().getSizeInBits() >=8)
12283 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12285 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12286 unsigned NumElts = InVT.getVectorNumElements();
12287 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12288 if (InVT.getSizeInBits() < 512) {
12289 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12290 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12295 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12296 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12297 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12300 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12301 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12302 if (Subtarget->hasInt256()) {
12303 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12304 In = DAG.getBitcast(MVT::v8i32, In);
12305 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12307 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12308 DAG.getIntPtrConstant(0, DL));
12311 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12312 DAG.getIntPtrConstant(0, DL));
12313 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12314 DAG.getIntPtrConstant(2, DL));
12315 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12316 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12317 static const int ShufMask[] = {0, 2, 4, 6};
12318 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12321 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12322 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12323 if (Subtarget->hasInt256()) {
12324 In = DAG.getBitcast(MVT::v32i8, In);
12326 SmallVector<SDValue,32> pshufbMask;
12327 for (unsigned i = 0; i < 2; ++i) {
12328 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12329 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12330 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12331 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12332 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12333 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12334 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12335 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12336 for (unsigned j = 0; j < 8; ++j)
12337 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12339 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12340 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12341 In = DAG.getBitcast(MVT::v4i64, In);
12343 static const int ShufMask[] = {0, 2, -1, -1};
12344 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12346 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12347 DAG.getIntPtrConstant(0, DL));
12348 return DAG.getBitcast(VT, In);
12351 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12352 DAG.getIntPtrConstant(0, DL));
12354 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12355 DAG.getIntPtrConstant(4, DL));
12357 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
12358 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
12360 // The PSHUFB mask:
12361 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12362 -1, -1, -1, -1, -1, -1, -1, -1};
12364 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12365 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12366 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12368 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12369 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12371 // The MOVLHPS Mask:
12372 static const int ShufMask2[] = {0, 1, 4, 5};
12373 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12374 return DAG.getBitcast(MVT::v8i16, res);
12377 // Handle truncation of V256 to V128 using shuffles.
12378 if (!VT.is128BitVector() || !InVT.is256BitVector())
12381 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12383 unsigned NumElems = VT.getVectorNumElements();
12384 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12386 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12387 // Prepare truncation shuffle mask
12388 for (unsigned i = 0; i != NumElems; ++i)
12389 MaskVec[i] = i * 2;
12390 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
12391 DAG.getUNDEF(NVT), &MaskVec[0]);
12392 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12393 DAG.getIntPtrConstant(0, DL));
12396 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12397 SelectionDAG &DAG) const {
12398 assert(!Op.getSimpleValueType().isVector());
12400 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12401 /*IsSigned=*/ true, /*IsReplace=*/ false);
12402 SDValue FIST = Vals.first, StackSlot = Vals.second;
12403 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12404 if (!FIST.getNode()) return Op;
12406 if (StackSlot.getNode())
12407 // Load the result.
12408 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12409 FIST, StackSlot, MachinePointerInfo(),
12410 false, false, false, 0);
12412 // The node is the result.
12416 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12417 SelectionDAG &DAG) const {
12418 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12419 /*IsSigned=*/ false, /*IsReplace=*/ false);
12420 SDValue FIST = Vals.first, StackSlot = Vals.second;
12421 assert(FIST.getNode() && "Unexpected failure");
12423 if (StackSlot.getNode())
12424 // Load the result.
12425 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12426 FIST, StackSlot, MachinePointerInfo(),
12427 false, false, false, 0);
12429 // The node is the result.
12433 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12435 MVT VT = Op.getSimpleValueType();
12436 SDValue In = Op.getOperand(0);
12437 MVT SVT = In.getSimpleValueType();
12439 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12441 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12442 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12443 In, DAG.getUNDEF(SVT)));
12446 /// The only differences between FABS and FNEG are the mask and the logic op.
12447 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12448 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12449 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12450 "Wrong opcode for lowering FABS or FNEG.");
12452 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12454 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12455 // into an FNABS. We'll lower the FABS after that if it is still in use.
12457 for (SDNode *User : Op->uses())
12458 if (User->getOpcode() == ISD::FNEG)
12461 SDValue Op0 = Op.getOperand(0);
12462 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12465 MVT VT = Op.getSimpleValueType();
12466 // Assume scalar op for initialization; update for vector if needed.
12467 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12468 // generate a 16-byte vector constant and logic op even for the scalar case.
12469 // Using a 16-byte mask allows folding the load of the mask with
12470 // the logic op, so it can save (~4 bytes) on code size.
12472 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12473 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12474 // decide if we should generate a 16-byte constant mask when we only need 4 or
12475 // 8 bytes for the scalar case.
12476 if (VT.isVector()) {
12477 EltVT = VT.getVectorElementType();
12478 NumElts = VT.getVectorNumElements();
12481 unsigned EltBits = EltVT.getSizeInBits();
12482 LLVMContext *Context = DAG.getContext();
12483 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12485 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12486 Constant *C = ConstantInt::get(*Context, MaskElt);
12487 C = ConstantVector::getSplat(NumElts, C);
12488 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12489 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12490 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12491 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12492 MachinePointerInfo::getConstantPool(),
12493 false, false, false, Alignment);
12495 if (VT.isVector()) {
12496 // For a vector, cast operands to a vector type, perform the logic op,
12497 // and cast the result back to the original value type.
12498 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12499 SDValue MaskCasted = DAG.getBitcast(VecVT, Mask);
12500 SDValue Operand = IsFNABS ? DAG.getBitcast(VecVT, Op0.getOperand(0))
12501 : DAG.getBitcast(VecVT, Op0);
12502 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12503 return DAG.getBitcast(VT,
12504 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12507 // If not vector, then scalar.
12508 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12509 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12510 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12513 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12514 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12515 LLVMContext *Context = DAG.getContext();
12516 SDValue Op0 = Op.getOperand(0);
12517 SDValue Op1 = Op.getOperand(1);
12519 MVT VT = Op.getSimpleValueType();
12520 MVT SrcVT = Op1.getSimpleValueType();
12522 // If second operand is smaller, extend it first.
12523 if (SrcVT.bitsLT(VT)) {
12524 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12527 // And if it is bigger, shrink it first.
12528 if (SrcVT.bitsGT(VT)) {
12529 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
12533 // At this point the operands and the result should have the same
12534 // type, and that won't be f80 since that is not custom lowered.
12536 const fltSemantics &Sem =
12537 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12538 const unsigned SizeInBits = VT.getSizeInBits();
12540 SmallVector<Constant *, 4> CV(
12541 VT == MVT::f64 ? 2 : 4,
12542 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12544 // First, clear all bits but the sign bit from the second operand (sign).
12545 CV[0] = ConstantFP::get(*Context,
12546 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12547 Constant *C = ConstantVector::get(CV);
12548 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12549 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12550 MachinePointerInfo::getConstantPool(),
12551 false, false, false, 16);
12552 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12554 // Next, clear the sign bit from the first operand (magnitude).
12555 // If it's a constant, we can clear it here.
12556 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12557 APFloat APF = Op0CN->getValueAPF();
12558 // If the magnitude is a positive zero, the sign bit alone is enough.
12559 if (APF.isPosZero())
12562 CV[0] = ConstantFP::get(*Context, APF);
12564 CV[0] = ConstantFP::get(
12566 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12568 C = ConstantVector::get(CV);
12569 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12570 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12571 MachinePointerInfo::getConstantPool(),
12572 false, false, false, 16);
12573 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12574 if (!isa<ConstantFPSDNode>(Op0))
12575 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12577 // OR the magnitude value with the sign bit.
12578 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12581 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12582 SDValue N0 = Op.getOperand(0);
12584 MVT VT = Op.getSimpleValueType();
12586 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12587 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12588 DAG.getConstant(1, dl, VT));
12589 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
12592 // Check whether an OR'd tree is PTEST-able.
12593 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12594 SelectionDAG &DAG) {
12595 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12597 if (!Subtarget->hasSSE41())
12600 if (!Op->hasOneUse())
12603 SDNode *N = Op.getNode();
12606 SmallVector<SDValue, 8> Opnds;
12607 DenseMap<SDValue, unsigned> VecInMap;
12608 SmallVector<SDValue, 8> VecIns;
12609 EVT VT = MVT::Other;
12611 // Recognize a special case where a vector is casted into wide integer to
12613 Opnds.push_back(N->getOperand(0));
12614 Opnds.push_back(N->getOperand(1));
12616 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12617 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12618 // BFS traverse all OR'd operands.
12619 if (I->getOpcode() == ISD::OR) {
12620 Opnds.push_back(I->getOperand(0));
12621 Opnds.push_back(I->getOperand(1));
12622 // Re-evaluate the number of nodes to be traversed.
12623 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12627 // Quit if a non-EXTRACT_VECTOR_ELT
12628 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12631 // Quit if without a constant index.
12632 SDValue Idx = I->getOperand(1);
12633 if (!isa<ConstantSDNode>(Idx))
12636 SDValue ExtractedFromVec = I->getOperand(0);
12637 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12638 if (M == VecInMap.end()) {
12639 VT = ExtractedFromVec.getValueType();
12640 // Quit if not 128/256-bit vector.
12641 if (!VT.is128BitVector() && !VT.is256BitVector())
12643 // Quit if not the same type.
12644 if (VecInMap.begin() != VecInMap.end() &&
12645 VT != VecInMap.begin()->first.getValueType())
12647 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12648 VecIns.push_back(ExtractedFromVec);
12650 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12653 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12654 "Not extracted from 128-/256-bit vector.");
12656 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12658 for (DenseMap<SDValue, unsigned>::const_iterator
12659 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12660 // Quit if not all elements are used.
12661 if (I->second != FullMask)
12665 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12667 // Cast all vectors into TestVT for PTEST.
12668 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12669 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
12671 // If more than one full vectors are evaluated, OR them first before PTEST.
12672 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12673 // Each iteration will OR 2 nodes and append the result until there is only
12674 // 1 node left, i.e. the final OR'd value of all vectors.
12675 SDValue LHS = VecIns[Slot];
12676 SDValue RHS = VecIns[Slot + 1];
12677 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12680 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12681 VecIns.back(), VecIns.back());
12684 /// \brief return true if \c Op has a use that doesn't just read flags.
12685 static bool hasNonFlagsUse(SDValue Op) {
12686 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12688 SDNode *User = *UI;
12689 unsigned UOpNo = UI.getOperandNo();
12690 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12691 // Look pass truncate.
12692 UOpNo = User->use_begin().getOperandNo();
12693 User = *User->use_begin();
12696 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12697 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12703 /// Emit nodes that will be selected as "test Op0,Op0", or something
12705 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12706 SelectionDAG &DAG) const {
12707 if (Op.getValueType() == MVT::i1) {
12708 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12709 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12710 DAG.getConstant(0, dl, MVT::i8));
12712 // CF and OF aren't always set the way we want. Determine which
12713 // of these we need.
12714 bool NeedCF = false;
12715 bool NeedOF = false;
12718 case X86::COND_A: case X86::COND_AE:
12719 case X86::COND_B: case X86::COND_BE:
12722 case X86::COND_G: case X86::COND_GE:
12723 case X86::COND_L: case X86::COND_LE:
12724 case X86::COND_O: case X86::COND_NO: {
12725 // Check if we really need to set the
12726 // Overflow flag. If NoSignedWrap is present
12727 // that is not actually needed.
12728 switch (Op->getOpcode()) {
12733 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
12734 if (BinNode->Flags.hasNoSignedWrap())
12744 // See if we can use the EFLAGS value from the operand instead of
12745 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12746 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12747 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12748 // Emit a CMP with 0, which is the TEST pattern.
12749 //if (Op.getValueType() == MVT::i1)
12750 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12751 // DAG.getConstant(0, MVT::i1));
12752 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12753 DAG.getConstant(0, dl, Op.getValueType()));
12755 unsigned Opcode = 0;
12756 unsigned NumOperands = 0;
12758 // Truncate operations may prevent the merge of the SETCC instruction
12759 // and the arithmetic instruction before it. Attempt to truncate the operands
12760 // of the arithmetic instruction and use a reduced bit-width instruction.
12761 bool NeedTruncation = false;
12762 SDValue ArithOp = Op;
12763 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12764 SDValue Arith = Op->getOperand(0);
12765 // Both the trunc and the arithmetic op need to have one user each.
12766 if (Arith->hasOneUse())
12767 switch (Arith.getOpcode()) {
12774 NeedTruncation = true;
12780 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12781 // which may be the result of a CAST. We use the variable 'Op', which is the
12782 // non-casted variable when we check for possible users.
12783 switch (ArithOp.getOpcode()) {
12785 // Due to an isel shortcoming, be conservative if this add is likely to be
12786 // selected as part of a load-modify-store instruction. When the root node
12787 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12788 // uses of other nodes in the match, such as the ADD in this case. This
12789 // leads to the ADD being left around and reselected, with the result being
12790 // two adds in the output. Alas, even if none our users are stores, that
12791 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12792 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12793 // climbing the DAG back to the root, and it doesn't seem to be worth the
12795 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12796 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12797 if (UI->getOpcode() != ISD::CopyToReg &&
12798 UI->getOpcode() != ISD::SETCC &&
12799 UI->getOpcode() != ISD::STORE)
12802 if (ConstantSDNode *C =
12803 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12804 // An add of one will be selected as an INC.
12805 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12806 Opcode = X86ISD::INC;
12811 // An add of negative one (subtract of one) will be selected as a DEC.
12812 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12813 Opcode = X86ISD::DEC;
12819 // Otherwise use a regular EFLAGS-setting add.
12820 Opcode = X86ISD::ADD;
12825 // If we have a constant logical shift that's only used in a comparison
12826 // against zero turn it into an equivalent AND. This allows turning it into
12827 // a TEST instruction later.
12828 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12829 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12830 EVT VT = Op.getValueType();
12831 unsigned BitWidth = VT.getSizeInBits();
12832 unsigned ShAmt = Op->getConstantOperandVal(1);
12833 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12835 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12836 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12837 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12838 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12840 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12841 DAG.getConstant(Mask, dl, VT));
12842 DAG.ReplaceAllUsesWith(Op, New);
12848 // If the primary and result isn't used, don't bother using X86ISD::AND,
12849 // because a TEST instruction will be better.
12850 if (!hasNonFlagsUse(Op))
12856 // Due to the ISEL shortcoming noted above, be conservative if this op is
12857 // likely to be selected as part of a load-modify-store instruction.
12858 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12859 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12860 if (UI->getOpcode() == ISD::STORE)
12863 // Otherwise use a regular EFLAGS-setting instruction.
12864 switch (ArithOp.getOpcode()) {
12865 default: llvm_unreachable("unexpected operator!");
12866 case ISD::SUB: Opcode = X86ISD::SUB; break;
12867 case ISD::XOR: Opcode = X86ISD::XOR; break;
12868 case ISD::AND: Opcode = X86ISD::AND; break;
12870 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12871 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12872 if (EFLAGS.getNode())
12875 Opcode = X86ISD::OR;
12889 return SDValue(Op.getNode(), 1);
12895 // If we found that truncation is beneficial, perform the truncation and
12897 if (NeedTruncation) {
12898 EVT VT = Op.getValueType();
12899 SDValue WideVal = Op->getOperand(0);
12900 EVT WideVT = WideVal.getValueType();
12901 unsigned ConvertedOp = 0;
12902 // Use a target machine opcode to prevent further DAGCombine
12903 // optimizations that may separate the arithmetic operations
12904 // from the setcc node.
12905 switch (WideVal.getOpcode()) {
12907 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12908 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12909 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12910 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12911 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12915 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12916 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12917 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12918 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12919 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12925 // Emit a CMP with 0, which is the TEST pattern.
12926 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12927 DAG.getConstant(0, dl, Op.getValueType()));
12929 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12930 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
12932 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12933 DAG.ReplaceAllUsesWith(Op, New);
12934 return SDValue(New.getNode(), 1);
12937 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12939 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12940 SDLoc dl, SelectionDAG &DAG) const {
12941 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12942 if (C->getAPIntValue() == 0)
12943 return EmitTest(Op0, X86CC, dl, DAG);
12945 if (Op0.getValueType() == MVT::i1)
12946 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12949 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12950 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12951 // Do the comparison at i32 if it's smaller, besides the Atom case.
12952 // This avoids subregister aliasing issues. Keep the smaller reference
12953 // if we're optimizing for size, however, as that'll allow better folding
12954 // of memory operations.
12955 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12956 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
12957 Attribute::MinSize) &&
12958 !Subtarget->isAtom()) {
12959 unsigned ExtendOp =
12960 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12961 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12962 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12964 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12965 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12966 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12968 return SDValue(Sub.getNode(), 1);
12970 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12973 /// Convert a comparison if required by the subtarget.
12974 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12975 SelectionDAG &DAG) const {
12976 // If the subtarget does not support the FUCOMI instruction, floating-point
12977 // comparisons have to be converted.
12978 if (Subtarget->hasCMov() ||
12979 Cmp.getOpcode() != X86ISD::CMP ||
12980 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12981 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12984 // The instruction selector will select an FUCOM instruction instead of
12985 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12986 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12987 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12989 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12990 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12991 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12992 DAG.getConstant(8, dl, MVT::i8));
12993 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12994 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12997 /// The minimum architected relative accuracy is 2^-12. We need one
12998 /// Newton-Raphson step to have a good float result (24 bits of precision).
12999 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13000 DAGCombinerInfo &DCI,
13001 unsigned &RefinementSteps,
13002 bool &UseOneConstNR) const {
13003 EVT VT = Op.getValueType();
13004 const char *RecipOp;
13006 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13007 // TODO: Add support for AVX512 (v16f32).
13008 // It is likely not profitable to do this for f64 because a double-precision
13009 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13010 // instructions: convert to single, rsqrtss, convert back to double, refine
13011 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13012 // along with FMA, this could be a throughput win.
13013 if (VT == MVT::f32 && Subtarget->hasSSE1())
13015 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13016 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13017 RecipOp = "vec-sqrtf";
13021 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13022 if (!Recips.isEnabled(RecipOp))
13025 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13026 UseOneConstNR = false;
13027 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13030 /// The minimum architected relative accuracy is 2^-12. We need one
13031 /// Newton-Raphson step to have a good float result (24 bits of precision).
13032 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13033 DAGCombinerInfo &DCI,
13034 unsigned &RefinementSteps) const {
13035 EVT VT = Op.getValueType();
13036 const char *RecipOp;
13038 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13039 // TODO: Add support for AVX512 (v16f32).
13040 // It is likely not profitable to do this for f64 because a double-precision
13041 // reciprocal estimate with refinement on x86 prior to FMA requires
13042 // 15 instructions: convert to single, rcpss, convert back to double, refine
13043 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13044 // along with FMA, this could be a throughput win.
13045 if (VT == MVT::f32 && Subtarget->hasSSE1())
13047 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13048 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13049 RecipOp = "vec-divf";
13053 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13054 if (!Recips.isEnabled(RecipOp))
13057 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13058 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13061 /// If we have at least two divisions that use the same divisor, convert to
13062 /// multplication by a reciprocal. This may need to be adjusted for a given
13063 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13064 /// This is because we still need one division to calculate the reciprocal and
13065 /// then we need two multiplies by that reciprocal as replacements for the
13066 /// original divisions.
13067 bool X86TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
13068 return NumUsers > 1;
13071 static bool isAllOnes(SDValue V) {
13072 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13073 return C && C->isAllOnesValue();
13076 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13077 /// if it's possible.
13078 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13079 SDLoc dl, SelectionDAG &DAG) const {
13080 SDValue Op0 = And.getOperand(0);
13081 SDValue Op1 = And.getOperand(1);
13082 if (Op0.getOpcode() == ISD::TRUNCATE)
13083 Op0 = Op0.getOperand(0);
13084 if (Op1.getOpcode() == ISD::TRUNCATE)
13085 Op1 = Op1.getOperand(0);
13088 if (Op1.getOpcode() == ISD::SHL)
13089 std::swap(Op0, Op1);
13090 if (Op0.getOpcode() == ISD::SHL) {
13091 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13092 if (And00C->getZExtValue() == 1) {
13093 // If we looked past a truncate, check that it's only truncating away
13095 unsigned BitWidth = Op0.getValueSizeInBits();
13096 unsigned AndBitWidth = And.getValueSizeInBits();
13097 if (BitWidth > AndBitWidth) {
13099 DAG.computeKnownBits(Op0, Zeros, Ones);
13100 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13104 RHS = Op0.getOperand(1);
13106 } else if (Op1.getOpcode() == ISD::Constant) {
13107 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13108 uint64_t AndRHSVal = AndRHS->getZExtValue();
13109 SDValue AndLHS = Op0;
13111 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13112 LHS = AndLHS.getOperand(0);
13113 RHS = AndLHS.getOperand(1);
13116 // Use BT if the immediate can't be encoded in a TEST instruction.
13117 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13119 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13123 if (LHS.getNode()) {
13124 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13125 // instruction. Since the shift amount is in-range-or-undefined, we know
13126 // that doing a bittest on the i32 value is ok. We extend to i32 because
13127 // the encoding for the i16 version is larger than the i32 version.
13128 // Also promote i16 to i32 for performance / code size reason.
13129 if (LHS.getValueType() == MVT::i8 ||
13130 LHS.getValueType() == MVT::i16)
13131 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13133 // If the operand types disagree, extend the shift amount to match. Since
13134 // BT ignores high bits (like shifts) we can use anyextend.
13135 if (LHS.getValueType() != RHS.getValueType())
13136 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13138 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13139 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13140 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13141 DAG.getConstant(Cond, dl, MVT::i8), BT);
13147 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13149 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13154 // SSE Condition code mapping:
13163 switch (SetCCOpcode) {
13164 default: llvm_unreachable("Unexpected SETCC condition");
13166 case ISD::SETEQ: SSECC = 0; break;
13168 case ISD::SETGT: Swap = true; // Fallthrough
13170 case ISD::SETOLT: SSECC = 1; break;
13172 case ISD::SETGE: Swap = true; // Fallthrough
13174 case ISD::SETOLE: SSECC = 2; break;
13175 case ISD::SETUO: SSECC = 3; break;
13177 case ISD::SETNE: SSECC = 4; break;
13178 case ISD::SETULE: Swap = true; // Fallthrough
13179 case ISD::SETUGE: SSECC = 5; break;
13180 case ISD::SETULT: Swap = true; // Fallthrough
13181 case ISD::SETUGT: SSECC = 6; break;
13182 case ISD::SETO: SSECC = 7; break;
13184 case ISD::SETONE: SSECC = 8; break;
13187 std::swap(Op0, Op1);
13192 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13193 // ones, and then concatenate the result back.
13194 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13195 MVT VT = Op.getSimpleValueType();
13197 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13198 "Unsupported value type for operation");
13200 unsigned NumElems = VT.getVectorNumElements();
13202 SDValue CC = Op.getOperand(2);
13204 // Extract the LHS vectors
13205 SDValue LHS = Op.getOperand(0);
13206 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13207 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13209 // Extract the RHS vectors
13210 SDValue RHS = Op.getOperand(1);
13211 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13212 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13214 // Issue the operation on the smaller types and concatenate the result back
13215 MVT EltVT = VT.getVectorElementType();
13216 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13217 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13218 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13219 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13222 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13223 SDValue Op0 = Op.getOperand(0);
13224 SDValue Op1 = Op.getOperand(1);
13225 SDValue CC = Op.getOperand(2);
13226 MVT VT = Op.getSimpleValueType();
13229 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13230 "Unexpected type for boolean compare operation");
13231 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13232 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13233 DAG.getConstant(-1, dl, VT));
13234 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13235 DAG.getConstant(-1, dl, VT));
13236 switch (SetCCOpcode) {
13237 default: llvm_unreachable("Unexpected SETCC condition");
13239 // (x != y) -> ~(x ^ y)
13240 return DAG.getNode(ISD::XOR, dl, VT,
13241 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13242 DAG.getConstant(-1, dl, VT));
13244 // (x == y) -> (x ^ y)
13245 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13248 // (x > y) -> (x & ~y)
13249 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13252 // (x < y) -> (~x & y)
13253 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13256 // (x <= y) -> (~x | y)
13257 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13260 // (x >=y) -> (x | ~y)
13261 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13265 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13266 const X86Subtarget *Subtarget) {
13267 SDValue Op0 = Op.getOperand(0);
13268 SDValue Op1 = Op.getOperand(1);
13269 SDValue CC = Op.getOperand(2);
13270 MVT VT = Op.getSimpleValueType();
13273 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13274 Op.getValueType().getScalarType() == MVT::i1 &&
13275 "Cannot set masked compare for this operation");
13277 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13279 bool Unsigned = false;
13282 switch (SetCCOpcode) {
13283 default: llvm_unreachable("Unexpected SETCC condition");
13284 case ISD::SETNE: SSECC = 4; break;
13285 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13286 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13287 case ISD::SETLT: Swap = true; //fall-through
13288 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13289 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13290 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13291 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13292 case ISD::SETULE: Unsigned = true; //fall-through
13293 case ISD::SETLE: SSECC = 2; break;
13297 std::swap(Op0, Op1);
13299 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13300 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13301 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13302 DAG.getConstant(SSECC, dl, MVT::i8));
13305 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13306 /// operand \p Op1. If non-trivial (for example because it's not constant)
13307 /// return an empty value.
13308 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13310 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13314 MVT VT = Op1.getSimpleValueType();
13315 MVT EVT = VT.getVectorElementType();
13316 unsigned n = VT.getVectorNumElements();
13317 SmallVector<SDValue, 8> ULTOp1;
13319 for (unsigned i = 0; i < n; ++i) {
13320 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13321 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13324 // Avoid underflow.
13325 APInt Val = Elt->getAPIntValue();
13329 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13332 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13335 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13336 SelectionDAG &DAG) {
13337 SDValue Op0 = Op.getOperand(0);
13338 SDValue Op1 = Op.getOperand(1);
13339 SDValue CC = Op.getOperand(2);
13340 MVT VT = Op.getSimpleValueType();
13341 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13342 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13347 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13348 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13351 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13352 unsigned Opc = X86ISD::CMPP;
13353 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13354 assert(VT.getVectorNumElements() <= 16);
13355 Opc = X86ISD::CMPM;
13357 // In the two special cases we can't handle, emit two comparisons.
13360 unsigned CombineOpc;
13361 if (SetCCOpcode == ISD::SETUEQ) {
13362 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13364 assert(SetCCOpcode == ISD::SETONE);
13365 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13368 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13369 DAG.getConstant(CC0, dl, MVT::i8));
13370 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13371 DAG.getConstant(CC1, dl, MVT::i8));
13372 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13374 // Handle all other FP comparisons here.
13375 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13376 DAG.getConstant(SSECC, dl, MVT::i8));
13379 // Break 256-bit integer vector compare into smaller ones.
13380 if (VT.is256BitVector() && !Subtarget->hasInt256())
13381 return Lower256IntVSETCC(Op, DAG);
13383 EVT OpVT = Op1.getValueType();
13384 if (OpVT.getVectorElementType() == MVT::i1)
13385 return LowerBoolVSETCC_AVX512(Op, DAG);
13387 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13388 if (Subtarget->hasAVX512()) {
13389 if (Op1.getValueType().is512BitVector() ||
13390 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13391 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13392 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13394 // In AVX-512 architecture setcc returns mask with i1 elements,
13395 // But there is no compare instruction for i8 and i16 elements in KNL.
13396 // We are not talking about 512-bit operands in this case, these
13397 // types are illegal.
13399 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13400 OpVT.getVectorElementType().getSizeInBits() >= 8))
13401 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13402 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13405 // We are handling one of the integer comparisons here. Since SSE only has
13406 // GT and EQ comparisons for integer, swapping operands and multiple
13407 // operations may be required for some comparisons.
13409 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13410 bool Subus = false;
13412 switch (SetCCOpcode) {
13413 default: llvm_unreachable("Unexpected SETCC condition");
13414 case ISD::SETNE: Invert = true;
13415 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13416 case ISD::SETLT: Swap = true;
13417 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13418 case ISD::SETGE: Swap = true;
13419 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13420 Invert = true; break;
13421 case ISD::SETULT: Swap = true;
13422 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13423 FlipSigns = true; break;
13424 case ISD::SETUGE: Swap = true;
13425 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13426 FlipSigns = true; Invert = true; break;
13429 // Special case: Use min/max operations for SETULE/SETUGE
13430 MVT VET = VT.getVectorElementType();
13432 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13433 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13436 switch (SetCCOpcode) {
13438 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13439 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13442 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13445 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13446 if (!MinMax && hasSubus) {
13447 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13449 // t = psubus Op0, Op1
13450 // pcmpeq t, <0..0>
13451 switch (SetCCOpcode) {
13453 case ISD::SETULT: {
13454 // If the comparison is against a constant we can turn this into a
13455 // setule. With psubus, setule does not require a swap. This is
13456 // beneficial because the constant in the register is no longer
13457 // destructed as the destination so it can be hoisted out of a loop.
13458 // Only do this pre-AVX since vpcmp* is no longer destructive.
13459 if (Subtarget->hasAVX())
13461 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13462 if (ULEOp1.getNode()) {
13464 Subus = true; Invert = false; Swap = false;
13468 // Psubus is better than flip-sign because it requires no inversion.
13469 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13470 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13474 Opc = X86ISD::SUBUS;
13480 std::swap(Op0, Op1);
13482 // Check that the operation in question is available (most are plain SSE2,
13483 // but PCMPGTQ and PCMPEQQ have different requirements).
13484 if (VT == MVT::v2i64) {
13485 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13486 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13488 // First cast everything to the right type.
13489 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13490 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13492 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13493 // bits of the inputs before performing those operations. The lower
13494 // compare is always unsigned.
13497 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
13499 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
13500 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
13501 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13502 Sign, Zero, Sign, Zero);
13504 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13505 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13507 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13508 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13509 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13511 // Create masks for only the low parts/high parts of the 64 bit integers.
13512 static const int MaskHi[] = { 1, 1, 3, 3 };
13513 static const int MaskLo[] = { 0, 0, 2, 2 };
13514 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13515 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13516 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13518 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13519 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13522 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13524 return DAG.getBitcast(VT, Result);
13527 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13528 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13529 // pcmpeqd + pshufd + pand.
13530 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13532 // First cast everything to the right type.
13533 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13534 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13537 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13539 // Make sure the lower and upper halves are both all-ones.
13540 static const int Mask[] = { 1, 0, 3, 2 };
13541 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13542 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13545 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13547 return DAG.getBitcast(VT, Result);
13551 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13552 // bits of the inputs before performing those operations.
13554 EVT EltVT = VT.getVectorElementType();
13555 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
13557 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13558 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13561 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13563 // If the logical-not of the result is required, perform that now.
13565 Result = DAG.getNOT(dl, Result, VT);
13568 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13571 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13572 getZeroVector(VT, Subtarget, DAG, dl));
13577 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13579 MVT VT = Op.getSimpleValueType();
13581 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13583 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13584 && "SetCC type must be 8-bit or 1-bit integer");
13585 SDValue Op0 = Op.getOperand(0);
13586 SDValue Op1 = Op.getOperand(1);
13588 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13590 // Optimize to BT if possible.
13591 // Lower (X & (1 << N)) == 0 to BT(X, N).
13592 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13593 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13594 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13595 Op1.getOpcode() == ISD::Constant &&
13596 cast<ConstantSDNode>(Op1)->isNullValue() &&
13597 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13598 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13599 if (NewSetCC.getNode()) {
13601 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13606 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13608 if (Op1.getOpcode() == ISD::Constant &&
13609 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13610 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13611 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13613 // If the input is a setcc, then reuse the input setcc or use a new one with
13614 // the inverted condition.
13615 if (Op0.getOpcode() == X86ISD::SETCC) {
13616 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13617 bool Invert = (CC == ISD::SETNE) ^
13618 cast<ConstantSDNode>(Op1)->isNullValue();
13622 CCode = X86::GetOppositeBranchCondition(CCode);
13623 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13624 DAG.getConstant(CCode, dl, MVT::i8),
13625 Op0.getOperand(1));
13627 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13631 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13632 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13633 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13635 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13636 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
13639 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13640 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
13641 if (X86CC == X86::COND_INVALID)
13644 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13645 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13646 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13647 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
13649 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13653 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13654 static bool isX86LogicalCmp(SDValue Op) {
13655 unsigned Opc = Op.getNode()->getOpcode();
13656 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13657 Opc == X86ISD::SAHF)
13659 if (Op.getResNo() == 1 &&
13660 (Opc == X86ISD::ADD ||
13661 Opc == X86ISD::SUB ||
13662 Opc == X86ISD::ADC ||
13663 Opc == X86ISD::SBB ||
13664 Opc == X86ISD::SMUL ||
13665 Opc == X86ISD::UMUL ||
13666 Opc == X86ISD::INC ||
13667 Opc == X86ISD::DEC ||
13668 Opc == X86ISD::OR ||
13669 Opc == X86ISD::XOR ||
13670 Opc == X86ISD::AND))
13673 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13679 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13680 if (V.getOpcode() != ISD::TRUNCATE)
13683 SDValue VOp0 = V.getOperand(0);
13684 unsigned InBits = VOp0.getValueSizeInBits();
13685 unsigned Bits = V.getValueSizeInBits();
13686 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13689 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13690 bool addTest = true;
13691 SDValue Cond = Op.getOperand(0);
13692 SDValue Op1 = Op.getOperand(1);
13693 SDValue Op2 = Op.getOperand(2);
13695 EVT VT = Op1.getValueType();
13698 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13699 // are available or VBLENDV if AVX is available.
13700 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13701 if (Cond.getOpcode() == ISD::SETCC &&
13702 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13703 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13704 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13705 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13706 int SSECC = translateX86FSETCC(
13707 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13710 if (Subtarget->hasAVX512()) {
13711 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13712 DAG.getConstant(SSECC, DL, MVT::i8));
13713 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13716 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13717 DAG.getConstant(SSECC, DL, MVT::i8));
13719 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13720 // of 3 logic instructions for size savings and potentially speed.
13721 // Unfortunately, there is no scalar form of VBLENDV.
13723 // If either operand is a constant, don't try this. We can expect to
13724 // optimize away at least one of the logic instructions later in that
13725 // case, so that sequence would be faster than a variable blend.
13727 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13728 // uses XMM0 as the selection register. That may need just as many
13729 // instructions as the AND/ANDN/OR sequence due to register moves, so
13732 if (Subtarget->hasAVX() &&
13733 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13735 // Convert to vectors, do a VSELECT, and convert back to scalar.
13736 // All of the conversions should be optimized away.
13738 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13739 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13740 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13741 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13743 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13744 VCmp = DAG.getBitcast(VCmpVT, VCmp);
13746 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13748 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13749 VSel, DAG.getIntPtrConstant(0, DL));
13751 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13752 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13753 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13757 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
13759 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
13760 Op1Scalar = ConvertI1VectorToInterger(Op1, DAG);
13761 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
13762 Op1Scalar = Op1.getOperand(0);
13764 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
13765 Op2Scalar = ConvertI1VectorToInterger(Op2, DAG);
13766 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
13767 Op2Scalar = Op2.getOperand(0);
13768 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
13769 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
13770 Op1Scalar.getValueType(),
13771 Cond, Op1Scalar, Op2Scalar);
13772 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
13773 return DAG.getBitcast(VT, newSelect);
13774 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
13775 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
13776 DAG.getIntPtrConstant(0, DL));
13780 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
13781 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
13782 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13783 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
13784 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13785 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
13786 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
13788 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
13791 if (Cond.getOpcode() == ISD::SETCC) {
13792 SDValue NewCond = LowerSETCC(Cond, DAG);
13793 if (NewCond.getNode())
13797 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13798 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13799 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13800 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13801 if (Cond.getOpcode() == X86ISD::SETCC &&
13802 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13803 isZero(Cond.getOperand(1).getOperand(1))) {
13804 SDValue Cmp = Cond.getOperand(1);
13806 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13808 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13809 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13810 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13812 SDValue CmpOp0 = Cmp.getOperand(0);
13813 // Apply further optimizations for special cases
13814 // (select (x != 0), -1, 0) -> neg & sbb
13815 // (select (x == 0), 0, -1) -> neg & sbb
13816 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13817 if (YC->isNullValue() &&
13818 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13819 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13820 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13821 DAG.getConstant(0, DL,
13822 CmpOp0.getValueType()),
13824 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13825 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13826 SDValue(Neg.getNode(), 1));
13830 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13831 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
13832 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13834 SDValue Res = // Res = 0 or -1.
13835 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13836 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
13838 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13839 Res = DAG.getNOT(DL, Res, Res.getValueType());
13841 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13842 if (!N2C || !N2C->isNullValue())
13843 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13848 // Look past (and (setcc_carry (cmp ...)), 1).
13849 if (Cond.getOpcode() == ISD::AND &&
13850 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13851 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13852 if (C && C->getAPIntValue() == 1)
13853 Cond = Cond.getOperand(0);
13856 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13857 // setting operand in place of the X86ISD::SETCC.
13858 unsigned CondOpcode = Cond.getOpcode();
13859 if (CondOpcode == X86ISD::SETCC ||
13860 CondOpcode == X86ISD::SETCC_CARRY) {
13861 CC = Cond.getOperand(0);
13863 SDValue Cmp = Cond.getOperand(1);
13864 unsigned Opc = Cmp.getOpcode();
13865 MVT VT = Op.getSimpleValueType();
13867 bool IllegalFPCMov = false;
13868 if (VT.isFloatingPoint() && !VT.isVector() &&
13869 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13870 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13872 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13873 Opc == X86ISD::BT) { // FIXME
13877 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13878 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13879 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13880 Cond.getOperand(0).getValueType() != MVT::i8)) {
13881 SDValue LHS = Cond.getOperand(0);
13882 SDValue RHS = Cond.getOperand(1);
13883 unsigned X86Opcode;
13886 switch (CondOpcode) {
13887 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13888 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13889 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13890 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13891 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13892 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13893 default: llvm_unreachable("unexpected overflowing operator");
13895 if (CondOpcode == ISD::UMULO)
13896 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13899 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13901 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13903 if (CondOpcode == ISD::UMULO)
13904 Cond = X86Op.getValue(2);
13906 Cond = X86Op.getValue(1);
13908 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
13913 // Look pass the truncate if the high bits are known zero.
13914 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13915 Cond = Cond.getOperand(0);
13917 // We know the result of AND is compared against zero. Try to match
13919 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13920 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13921 if (NewSetCC.getNode()) {
13922 CC = NewSetCC.getOperand(0);
13923 Cond = NewSetCC.getOperand(1);
13930 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
13931 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13934 // a < b ? -1 : 0 -> RES = ~setcc_carry
13935 // a < b ? 0 : -1 -> RES = setcc_carry
13936 // a >= b ? -1 : 0 -> RES = setcc_carry
13937 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13938 if (Cond.getOpcode() == X86ISD::SUB) {
13939 Cond = ConvertCmpIfNecessary(Cond, DAG);
13940 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13942 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13943 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13944 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13945 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13947 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13948 return DAG.getNOT(DL, Res, Res.getValueType());
13953 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13954 // widen the cmov and push the truncate through. This avoids introducing a new
13955 // branch during isel and doesn't add any extensions.
13956 if (Op.getValueType() == MVT::i8 &&
13957 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13958 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13959 if (T1.getValueType() == T2.getValueType() &&
13960 // Blacklist CopyFromReg to avoid partial register stalls.
13961 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13962 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13963 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13964 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13968 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13969 // condition is true.
13970 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13971 SDValue Ops[] = { Op2, Op1, CC, Cond };
13972 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13975 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
13976 const X86Subtarget *Subtarget,
13977 SelectionDAG &DAG) {
13978 MVT VT = Op->getSimpleValueType(0);
13979 SDValue In = Op->getOperand(0);
13980 MVT InVT = In.getSimpleValueType();
13981 MVT VTElt = VT.getVectorElementType();
13982 MVT InVTElt = InVT.getVectorElementType();
13986 if ((InVTElt == MVT::i1) &&
13987 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
13988 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
13990 ((Subtarget->hasBWI() && VT.is512BitVector() &&
13991 VTElt.getSizeInBits() <= 16)) ||
13993 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
13994 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
13996 ((Subtarget->hasDQI() && VT.is512BitVector() &&
13997 VTElt.getSizeInBits() >= 32))))
13998 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14000 unsigned int NumElts = VT.getVectorNumElements();
14002 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14005 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14006 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14007 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14008 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14011 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14012 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14014 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14017 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14019 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14020 if (VT.is512BitVector())
14022 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14025 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14026 const X86Subtarget *Subtarget,
14027 SelectionDAG &DAG) {
14028 SDValue In = Op->getOperand(0);
14029 MVT VT = Op->getSimpleValueType(0);
14030 MVT InVT = In.getSimpleValueType();
14031 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14033 MVT InSVT = InVT.getScalarType();
14034 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14036 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14038 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14043 // SSE41 targets can use the pmovsx* instructions directly.
14044 if (Subtarget->hasSSE41())
14045 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14047 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14051 // As SRAI is only available on i16/i32 types, we expand only up to i32
14052 // and handle i64 separately.
14053 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14054 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14055 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14056 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14057 Curr = DAG.getBitcast(CurrVT, Curr);
14060 SDValue SignExt = Curr;
14061 if (CurrVT != InVT) {
14062 unsigned SignExtShift =
14063 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14064 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14065 DAG.getConstant(SignExtShift, dl, MVT::i8));
14071 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14072 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14073 DAG.getConstant(31, dl, MVT::i8));
14074 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14075 return DAG.getBitcast(VT, Ext);
14081 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14082 SelectionDAG &DAG) {
14083 MVT VT = Op->getSimpleValueType(0);
14084 SDValue In = Op->getOperand(0);
14085 MVT InVT = In.getSimpleValueType();
14088 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14089 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14091 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14092 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14093 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14096 if (Subtarget->hasInt256())
14097 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14099 // Optimize vectors in AVX mode
14100 // Sign extend v8i16 to v8i32 and
14103 // Divide input vector into two parts
14104 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14105 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14106 // concat the vectors to original VT
14108 unsigned NumElems = InVT.getVectorNumElements();
14109 SDValue Undef = DAG.getUNDEF(InVT);
14111 SmallVector<int,8> ShufMask1(NumElems, -1);
14112 for (unsigned i = 0; i != NumElems/2; ++i)
14115 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14117 SmallVector<int,8> ShufMask2(NumElems, -1);
14118 for (unsigned i = 0; i != NumElems/2; ++i)
14119 ShufMask2[i] = i + NumElems/2;
14121 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14123 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14124 VT.getVectorNumElements()/2);
14126 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14127 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14129 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14132 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14133 // may emit an illegal shuffle but the expansion is still better than scalar
14134 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14135 // we'll emit a shuffle and a arithmetic shift.
14136 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14137 // TODO: It is possible to support ZExt by zeroing the undef values during
14138 // the shuffle phase or after the shuffle.
14139 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14140 SelectionDAG &DAG) {
14141 MVT RegVT = Op.getSimpleValueType();
14142 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14143 assert(RegVT.isInteger() &&
14144 "We only custom lower integer vector sext loads.");
14146 // Nothing useful we can do without SSE2 shuffles.
14147 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14149 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14151 EVT MemVT = Ld->getMemoryVT();
14152 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14153 unsigned RegSz = RegVT.getSizeInBits();
14155 ISD::LoadExtType Ext = Ld->getExtensionType();
14157 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14158 && "Only anyext and sext are currently implemented.");
14159 assert(MemVT != RegVT && "Cannot extend to the same type");
14160 assert(MemVT.isVector() && "Must load a vector from memory");
14162 unsigned NumElems = RegVT.getVectorNumElements();
14163 unsigned MemSz = MemVT.getSizeInBits();
14164 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14166 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14167 // The only way in which we have a legal 256-bit vector result but not the
14168 // integer 256-bit operations needed to directly lower a sextload is if we
14169 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14170 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14171 // correctly legalized. We do this late to allow the canonical form of
14172 // sextload to persist throughout the rest of the DAG combiner -- it wants
14173 // to fold together any extensions it can, and so will fuse a sign_extend
14174 // of an sextload into a sextload targeting a wider value.
14176 if (MemSz == 128) {
14177 // Just switch this to a normal load.
14178 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14179 "it must be a legal 128-bit vector "
14181 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14182 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14183 Ld->isInvariant(), Ld->getAlignment());
14185 assert(MemSz < 128 &&
14186 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14187 // Do an sext load to a 128-bit vector type. We want to use the same
14188 // number of elements, but elements half as wide. This will end up being
14189 // recursively lowered by this routine, but will succeed as we definitely
14190 // have all the necessary features if we're using AVX1.
14192 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14193 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14195 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14196 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14197 Ld->isNonTemporal(), Ld->isInvariant(),
14198 Ld->getAlignment());
14201 // Replace chain users with the new chain.
14202 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14203 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14205 // Finally, do a normal sign-extend to the desired register.
14206 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14209 // All sizes must be a power of two.
14210 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14211 "Non-power-of-two elements are not custom lowered!");
14213 // Attempt to load the original value using scalar loads.
14214 // Find the largest scalar type that divides the total loaded size.
14215 MVT SclrLoadTy = MVT::i8;
14216 for (MVT Tp : MVT::integer_valuetypes()) {
14217 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14222 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14223 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14225 SclrLoadTy = MVT::f64;
14227 // Calculate the number of scalar loads that we need to perform
14228 // in order to load our vector from memory.
14229 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14231 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14232 "Can only lower sext loads with a single scalar load!");
14234 unsigned loadRegZize = RegSz;
14235 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14238 // Represent our vector as a sequence of elements which are the
14239 // largest scalar that we can load.
14240 EVT LoadUnitVecVT = EVT::getVectorVT(
14241 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14243 // Represent the data using the same element type that is stored in
14244 // memory. In practice, we ''widen'' MemVT.
14246 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14247 loadRegZize / MemVT.getScalarType().getSizeInBits());
14249 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14250 "Invalid vector type");
14252 // We can't shuffle using an illegal type.
14253 assert(TLI.isTypeLegal(WideVecVT) &&
14254 "We only lower types that form legal widened vector types");
14256 SmallVector<SDValue, 8> Chains;
14257 SDValue Ptr = Ld->getBasePtr();
14258 SDValue Increment =
14259 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl, TLI.getPointerTy());
14260 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14262 for (unsigned i = 0; i < NumLoads; ++i) {
14263 // Perform a single load.
14264 SDValue ScalarLoad =
14265 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14266 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14267 Ld->getAlignment());
14268 Chains.push_back(ScalarLoad.getValue(1));
14269 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14270 // another round of DAGCombining.
14272 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14274 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14275 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14277 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14280 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14282 // Bitcast the loaded value to a vector of the original element type, in
14283 // the size of the target vector type.
14284 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
14285 unsigned SizeRatio = RegSz / MemSz;
14287 if (Ext == ISD::SEXTLOAD) {
14288 // If we have SSE4.1, we can directly emit a VSEXT node.
14289 if (Subtarget->hasSSE41()) {
14290 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14291 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14295 // Otherwise we'll shuffle the small elements in the high bits of the
14296 // larger type and perform an arithmetic shift. If the shift is not legal
14297 // it's better to scalarize.
14298 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14299 "We can't implement a sext load without an arithmetic right shift!");
14301 // Redistribute the loaded elements into the different locations.
14302 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14303 for (unsigned i = 0; i != NumElems; ++i)
14304 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14306 SDValue Shuff = DAG.getVectorShuffle(
14307 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14309 Shuff = DAG.getBitcast(RegVT, Shuff);
14311 // Build the arithmetic shift.
14312 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14313 MemVT.getVectorElementType().getSizeInBits();
14315 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14316 DAG.getConstant(Amt, dl, RegVT));
14318 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14322 // Redistribute the loaded elements into the different locations.
14323 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14324 for (unsigned i = 0; i != NumElems; ++i)
14325 ShuffleVec[i * SizeRatio] = i;
14327 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14328 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14330 // Bitcast to the requested type.
14331 Shuff = DAG.getBitcast(RegVT, Shuff);
14332 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14336 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14337 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14338 // from the AND / OR.
14339 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14340 Opc = Op.getOpcode();
14341 if (Opc != ISD::OR && Opc != ISD::AND)
14343 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14344 Op.getOperand(0).hasOneUse() &&
14345 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14346 Op.getOperand(1).hasOneUse());
14349 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14350 // 1 and that the SETCC node has a single use.
14351 static bool isXor1OfSetCC(SDValue Op) {
14352 if (Op.getOpcode() != ISD::XOR)
14354 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14355 if (N1C && N1C->getAPIntValue() == 1) {
14356 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14357 Op.getOperand(0).hasOneUse();
14362 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14363 bool addTest = true;
14364 SDValue Chain = Op.getOperand(0);
14365 SDValue Cond = Op.getOperand(1);
14366 SDValue Dest = Op.getOperand(2);
14369 bool Inverted = false;
14371 if (Cond.getOpcode() == ISD::SETCC) {
14372 // Check for setcc([su]{add,sub,mul}o == 0).
14373 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14374 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14375 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14376 Cond.getOperand(0).getResNo() == 1 &&
14377 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14378 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14379 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14380 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14381 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14382 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14384 Cond = Cond.getOperand(0);
14386 SDValue NewCond = LowerSETCC(Cond, DAG);
14387 if (NewCond.getNode())
14392 // FIXME: LowerXALUO doesn't handle these!!
14393 else if (Cond.getOpcode() == X86ISD::ADD ||
14394 Cond.getOpcode() == X86ISD::SUB ||
14395 Cond.getOpcode() == X86ISD::SMUL ||
14396 Cond.getOpcode() == X86ISD::UMUL)
14397 Cond = LowerXALUO(Cond, DAG);
14400 // Look pass (and (setcc_carry (cmp ...)), 1).
14401 if (Cond.getOpcode() == ISD::AND &&
14402 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14403 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14404 if (C && C->getAPIntValue() == 1)
14405 Cond = Cond.getOperand(0);
14408 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14409 // setting operand in place of the X86ISD::SETCC.
14410 unsigned CondOpcode = Cond.getOpcode();
14411 if (CondOpcode == X86ISD::SETCC ||
14412 CondOpcode == X86ISD::SETCC_CARRY) {
14413 CC = Cond.getOperand(0);
14415 SDValue Cmp = Cond.getOperand(1);
14416 unsigned Opc = Cmp.getOpcode();
14417 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14418 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14422 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14426 // These can only come from an arithmetic instruction with overflow,
14427 // e.g. SADDO, UADDO.
14428 Cond = Cond.getNode()->getOperand(1);
14434 CondOpcode = Cond.getOpcode();
14435 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14436 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14437 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14438 Cond.getOperand(0).getValueType() != MVT::i8)) {
14439 SDValue LHS = Cond.getOperand(0);
14440 SDValue RHS = Cond.getOperand(1);
14441 unsigned X86Opcode;
14444 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14445 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14447 switch (CondOpcode) {
14448 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14450 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14452 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14455 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14456 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14458 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14460 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14463 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14464 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14465 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14466 default: llvm_unreachable("unexpected overflowing operator");
14469 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14470 if (CondOpcode == ISD::UMULO)
14471 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14474 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14476 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14478 if (CondOpcode == ISD::UMULO)
14479 Cond = X86Op.getValue(2);
14481 Cond = X86Op.getValue(1);
14483 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14487 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14488 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14489 if (CondOpc == ISD::OR) {
14490 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14491 // two branches instead of an explicit OR instruction with a
14493 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14494 isX86LogicalCmp(Cmp)) {
14495 CC = Cond.getOperand(0).getOperand(0);
14496 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14497 Chain, Dest, CC, Cmp);
14498 CC = Cond.getOperand(1).getOperand(0);
14502 } else { // ISD::AND
14503 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14504 // two branches instead of an explicit AND instruction with a
14505 // separate test. However, we only do this if this block doesn't
14506 // have a fall-through edge, because this requires an explicit
14507 // jmp when the condition is false.
14508 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14509 isX86LogicalCmp(Cmp) &&
14510 Op.getNode()->hasOneUse()) {
14511 X86::CondCode CCode =
14512 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14513 CCode = X86::GetOppositeBranchCondition(CCode);
14514 CC = DAG.getConstant(CCode, dl, MVT::i8);
14515 SDNode *User = *Op.getNode()->use_begin();
14516 // Look for an unconditional branch following this conditional branch.
14517 // We need this because we need to reverse the successors in order
14518 // to implement FCMP_OEQ.
14519 if (User->getOpcode() == ISD::BR) {
14520 SDValue FalseBB = User->getOperand(1);
14522 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14523 assert(NewBR == User);
14527 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14528 Chain, Dest, CC, Cmp);
14529 X86::CondCode CCode =
14530 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14531 CCode = X86::GetOppositeBranchCondition(CCode);
14532 CC = DAG.getConstant(CCode, dl, MVT::i8);
14538 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14539 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14540 // It should be transformed during dag combiner except when the condition
14541 // is set by a arithmetics with overflow node.
14542 X86::CondCode CCode =
14543 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14544 CCode = X86::GetOppositeBranchCondition(CCode);
14545 CC = DAG.getConstant(CCode, dl, MVT::i8);
14546 Cond = Cond.getOperand(0).getOperand(1);
14548 } else if (Cond.getOpcode() == ISD::SETCC &&
14549 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14550 // For FCMP_OEQ, we can emit
14551 // two branches instead of an explicit AND instruction with a
14552 // separate test. However, we only do this if this block doesn't
14553 // have a fall-through edge, because this requires an explicit
14554 // jmp when the condition is false.
14555 if (Op.getNode()->hasOneUse()) {
14556 SDNode *User = *Op.getNode()->use_begin();
14557 // Look for an unconditional branch following this conditional branch.
14558 // We need this because we need to reverse the successors in order
14559 // to implement FCMP_OEQ.
14560 if (User->getOpcode() == ISD::BR) {
14561 SDValue FalseBB = User->getOperand(1);
14563 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14564 assert(NewBR == User);
14568 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14569 Cond.getOperand(0), Cond.getOperand(1));
14570 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14571 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14572 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14573 Chain, Dest, CC, Cmp);
14574 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
14579 } else if (Cond.getOpcode() == ISD::SETCC &&
14580 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14581 // For FCMP_UNE, we can emit
14582 // two branches instead of an explicit AND instruction with a
14583 // separate test. However, we only do this if this block doesn't
14584 // have a fall-through edge, because this requires an explicit
14585 // jmp when the condition is false.
14586 if (Op.getNode()->hasOneUse()) {
14587 SDNode *User = *Op.getNode()->use_begin();
14588 // Look for an unconditional branch following this conditional branch.
14589 // We need this because we need to reverse the successors in order
14590 // to implement FCMP_UNE.
14591 if (User->getOpcode() == ISD::BR) {
14592 SDValue FalseBB = User->getOperand(1);
14594 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14595 assert(NewBR == User);
14598 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14599 Cond.getOperand(0), Cond.getOperand(1));
14600 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14601 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14602 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14603 Chain, Dest, CC, Cmp);
14604 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
14614 // Look pass the truncate if the high bits are known zero.
14615 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14616 Cond = Cond.getOperand(0);
14618 // We know the result of AND is compared against zero. Try to match
14620 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14621 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14622 if (NewSetCC.getNode()) {
14623 CC = NewSetCC.getOperand(0);
14624 Cond = NewSetCC.getOperand(1);
14631 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14632 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14633 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14635 Cond = ConvertCmpIfNecessary(Cond, DAG);
14636 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14637 Chain, Dest, CC, Cond);
14640 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14641 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14642 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14643 // that the guard pages used by the OS virtual memory manager are allocated in
14644 // correct sequence.
14646 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14647 SelectionDAG &DAG) const {
14648 MachineFunction &MF = DAG.getMachineFunction();
14649 bool SplitStack = MF.shouldSplitStack();
14650 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14655 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14656 SDNode* Node = Op.getNode();
14658 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14659 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14660 " not tell us which reg is the stack pointer!");
14661 EVT VT = Node->getValueType(0);
14662 SDValue Tmp1 = SDValue(Node, 0);
14663 SDValue Tmp2 = SDValue(Node, 1);
14664 SDValue Tmp3 = Node->getOperand(2);
14665 SDValue Chain = Tmp1.getOperand(0);
14667 // Chain the dynamic stack allocation so that it doesn't modify the stack
14668 // pointer when other instructions are using the stack.
14669 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
14672 SDValue Size = Tmp2.getOperand(1);
14673 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14674 Chain = SP.getValue(1);
14675 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14676 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14677 unsigned StackAlign = TFI.getStackAlignment();
14678 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14679 if (Align > StackAlign)
14680 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14681 DAG.getConstant(-(uint64_t)Align, dl, VT));
14682 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14684 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
14685 DAG.getIntPtrConstant(0, dl, true), SDValue(),
14688 SDValue Ops[2] = { Tmp1, Tmp2 };
14689 return DAG.getMergeValues(Ops, dl);
14693 SDValue Chain = Op.getOperand(0);
14694 SDValue Size = Op.getOperand(1);
14695 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14696 EVT VT = Op.getNode()->getValueType(0);
14698 bool Is64Bit = Subtarget->is64Bit();
14699 EVT SPTy = getPointerTy();
14702 MachineRegisterInfo &MRI = MF.getRegInfo();
14705 // The 64 bit implementation of segmented stacks needs to clobber both r10
14706 // r11. This makes it impossible to use it along with nested parameters.
14707 const Function *F = MF.getFunction();
14709 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14711 if (I->hasNestAttr())
14712 report_fatal_error("Cannot use segmented stacks with functions that "
14713 "have nested arguments.");
14716 const TargetRegisterClass *AddrRegClass =
14717 getRegClassFor(getPointerTy());
14718 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14719 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14720 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14721 DAG.getRegister(Vreg, SPTy));
14722 SDValue Ops1[2] = { Value, Chain };
14723 return DAG.getMergeValues(Ops1, dl);
14726 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14728 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14729 Flag = Chain.getValue(1);
14730 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14732 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14734 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14735 unsigned SPReg = RegInfo->getStackRegister();
14736 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14737 Chain = SP.getValue(1);
14740 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14741 DAG.getConstant(-(uint64_t)Align, dl, VT));
14742 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14745 SDValue Ops1[2] = { SP, Chain };
14746 return DAG.getMergeValues(Ops1, dl);
14750 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14751 MachineFunction &MF = DAG.getMachineFunction();
14752 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14754 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14757 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14758 // vastart just stores the address of the VarArgsFrameIndex slot into the
14759 // memory location argument.
14760 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14762 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14763 MachinePointerInfo(SV), false, false, 0);
14767 // gp_offset (0 - 6 * 8)
14768 // fp_offset (48 - 48 + 8 * 16)
14769 // overflow_arg_area (point to parameters coming in memory).
14771 SmallVector<SDValue, 8> MemOps;
14772 SDValue FIN = Op.getOperand(1);
14774 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14775 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14777 FIN, MachinePointerInfo(SV), false, false, 0);
14778 MemOps.push_back(Store);
14781 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14782 FIN, DAG.getIntPtrConstant(4, DL));
14783 Store = DAG.getStore(Op.getOperand(0), DL,
14784 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
14786 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14787 MemOps.push_back(Store);
14789 // Store ptr to overflow_arg_area
14790 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14791 FIN, DAG.getIntPtrConstant(4, DL));
14792 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14794 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14795 MachinePointerInfo(SV, 8),
14797 MemOps.push_back(Store);
14799 // Store ptr to reg_save_area.
14800 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14801 FIN, DAG.getIntPtrConstant(8, DL));
14802 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14804 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14805 MachinePointerInfo(SV, 16), false, false, 0);
14806 MemOps.push_back(Store);
14807 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14810 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14811 assert(Subtarget->is64Bit() &&
14812 "LowerVAARG only handles 64-bit va_arg!");
14813 assert((Subtarget->isTargetLinux() ||
14814 Subtarget->isTargetDarwin()) &&
14815 "Unhandled target in LowerVAARG");
14816 assert(Op.getNode()->getNumOperands() == 4);
14817 SDValue Chain = Op.getOperand(0);
14818 SDValue SrcPtr = Op.getOperand(1);
14819 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14820 unsigned Align = Op.getConstantOperandVal(3);
14823 EVT ArgVT = Op.getNode()->getValueType(0);
14824 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14825 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14828 // Decide which area this value should be read from.
14829 // TODO: Implement the AMD64 ABI in its entirety. This simple
14830 // selection mechanism works only for the basic types.
14831 if (ArgVT == MVT::f80) {
14832 llvm_unreachable("va_arg for f80 not yet implemented");
14833 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14834 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14835 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14836 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14838 llvm_unreachable("Unhandled argument type in LowerVAARG");
14841 if (ArgMode == 2) {
14842 // Sanity Check: Make sure using fp_offset makes sense.
14843 assert(!Subtarget->useSoftFloat() &&
14844 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14845 Attribute::NoImplicitFloat)) &&
14846 Subtarget->hasSSE1());
14849 // Insert VAARG_64 node into the DAG
14850 // VAARG_64 returns two values: Variable Argument Address, Chain
14851 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
14852 DAG.getConstant(ArgMode, dl, MVT::i8),
14853 DAG.getConstant(Align, dl, MVT::i32)};
14854 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14855 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14856 VTs, InstOps, MVT::i64,
14857 MachinePointerInfo(SV),
14859 /*Volatile=*/false,
14861 /*WriteMem=*/true);
14862 Chain = VAARG.getValue(1);
14864 // Load the next argument and return it
14865 return DAG.getLoad(ArgVT, dl,
14868 MachinePointerInfo(),
14869 false, false, false, 0);
14872 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14873 SelectionDAG &DAG) {
14874 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14875 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14876 SDValue Chain = Op.getOperand(0);
14877 SDValue DstPtr = Op.getOperand(1);
14878 SDValue SrcPtr = Op.getOperand(2);
14879 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14880 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14883 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14884 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
14886 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14889 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14890 // amount is a constant. Takes immediate version of shift as input.
14891 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14892 SDValue SrcOp, uint64_t ShiftAmt,
14893 SelectionDAG &DAG) {
14894 MVT ElementType = VT.getVectorElementType();
14896 // Fold this packed shift into its first operand if ShiftAmt is 0.
14900 // Check for ShiftAmt >= element width
14901 if (ShiftAmt >= ElementType.getSizeInBits()) {
14902 if (Opc == X86ISD::VSRAI)
14903 ShiftAmt = ElementType.getSizeInBits() - 1;
14905 return DAG.getConstant(0, dl, VT);
14908 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14909 && "Unknown target vector shift-by-constant node");
14911 // Fold this packed vector shift into a build vector if SrcOp is a
14912 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14913 if (VT == SrcOp.getSimpleValueType() &&
14914 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14915 SmallVector<SDValue, 8> Elts;
14916 unsigned NumElts = SrcOp->getNumOperands();
14917 ConstantSDNode *ND;
14920 default: llvm_unreachable(nullptr);
14921 case X86ISD::VSHLI:
14922 for (unsigned i=0; i!=NumElts; ++i) {
14923 SDValue CurrentOp = SrcOp->getOperand(i);
14924 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14925 Elts.push_back(CurrentOp);
14928 ND = cast<ConstantSDNode>(CurrentOp);
14929 const APInt &C = ND->getAPIntValue();
14930 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
14933 case X86ISD::VSRLI:
14934 for (unsigned i=0; i!=NumElts; ++i) {
14935 SDValue CurrentOp = SrcOp->getOperand(i);
14936 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14937 Elts.push_back(CurrentOp);
14940 ND = cast<ConstantSDNode>(CurrentOp);
14941 const APInt &C = ND->getAPIntValue();
14942 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
14945 case X86ISD::VSRAI:
14946 for (unsigned i=0; i!=NumElts; ++i) {
14947 SDValue CurrentOp = SrcOp->getOperand(i);
14948 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14949 Elts.push_back(CurrentOp);
14952 ND = cast<ConstantSDNode>(CurrentOp);
14953 const APInt &C = ND->getAPIntValue();
14954 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
14959 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14962 return DAG.getNode(Opc, dl, VT, SrcOp,
14963 DAG.getConstant(ShiftAmt, dl, MVT::i8));
14966 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14967 // may or may not be a constant. Takes immediate version of shift as input.
14968 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14969 SDValue SrcOp, SDValue ShAmt,
14970 SelectionDAG &DAG) {
14971 MVT SVT = ShAmt.getSimpleValueType();
14972 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
14974 // Catch shift-by-constant.
14975 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14976 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14977 CShAmt->getZExtValue(), DAG);
14979 // Change opcode to non-immediate version
14981 default: llvm_unreachable("Unknown target vector shift node");
14982 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14983 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14984 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14987 const X86Subtarget &Subtarget =
14988 static_cast<const X86Subtarget &>(DAG.getSubtarget());
14989 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
14990 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
14991 // Let the shuffle legalizer expand this shift amount node.
14992 SDValue Op0 = ShAmt.getOperand(0);
14993 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
14994 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
14996 // Need to build a vector containing shift amount.
14997 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
14998 SmallVector<SDValue, 4> ShOps;
14999 ShOps.push_back(ShAmt);
15000 if (SVT == MVT::i32) {
15001 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15002 ShOps.push_back(DAG.getUNDEF(SVT));
15004 ShOps.push_back(DAG.getUNDEF(SVT));
15006 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15007 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15010 // The return type has to be a 128-bit type with the same element
15011 // type as the input type.
15012 MVT EltVT = VT.getVectorElementType();
15013 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15015 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15016 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15019 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15020 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15021 /// necessary casting for \p Mask when lowering masking intrinsics.
15022 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15023 SDValue PreservedSrc,
15024 const X86Subtarget *Subtarget,
15025 SelectionDAG &DAG) {
15026 EVT VT = Op.getValueType();
15027 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15028 MVT::i1, VT.getVectorNumElements());
15029 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15030 Mask.getValueType().getSizeInBits());
15033 assert(MaskVT.isSimple() && "invalid mask type");
15035 if (isAllOnes(Mask))
15038 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15039 // are extracted by EXTRACT_SUBVECTOR.
15040 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15041 DAG.getBitcast(BitcastVT, Mask),
15042 DAG.getIntPtrConstant(0, dl));
15044 switch (Op.getOpcode()) {
15046 case X86ISD::PCMPEQM:
15047 case X86ISD::PCMPGTM:
15049 case X86ISD::CMPMU:
15050 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15052 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15053 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15054 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
15057 /// \brief Creates an SDNode for a predicated scalar operation.
15058 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15059 /// The mask is comming as MVT::i8 and it should be truncated
15060 /// to MVT::i1 while lowering masking intrinsics.
15061 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15062 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
15063 /// a scalar instruction.
15064 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15065 SDValue PreservedSrc,
15066 const X86Subtarget *Subtarget,
15067 SelectionDAG &DAG) {
15068 if (isAllOnes(Mask))
15071 EVT VT = Op.getValueType();
15073 // The mask should be of type MVT::i1
15074 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15076 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15077 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15078 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15081 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15082 SelectionDAG &DAG) {
15084 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15085 EVT VT = Op.getValueType();
15086 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15088 switch(IntrData->Type) {
15089 case INTR_TYPE_1OP:
15090 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15091 case INTR_TYPE_2OP:
15092 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15094 case INTR_TYPE_3OP:
15095 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15096 Op.getOperand(2), Op.getOperand(3));
15097 case INTR_TYPE_1OP_MASK_RM: {
15098 SDValue Src = Op.getOperand(1);
15099 SDValue PassThru = Op.getOperand(2);
15100 SDValue Mask = Op.getOperand(3);
15101 SDValue RoundingMode;
15102 if (Op.getNumOperands() == 4)
15103 RoundingMode = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15105 RoundingMode = Op.getOperand(4);
15106 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15107 if (IntrWithRoundingModeOpcode != 0) {
15108 unsigned Round = cast<ConstantSDNode>(RoundingMode)->getZExtValue();
15109 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION)
15110 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15111 dl, Op.getValueType(), Src, RoundingMode),
15112 Mask, PassThru, Subtarget, DAG);
15114 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15116 Mask, PassThru, Subtarget, DAG);
15118 case INTR_TYPE_1OP_MASK: {
15119 SDValue Src = Op.getOperand(1);
15120 SDValue Passthru = Op.getOperand(2);
15121 SDValue Mask = Op.getOperand(3);
15122 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
15123 Mask, Passthru, Subtarget, DAG);
15125 case INTR_TYPE_SCALAR_MASK_RM: {
15126 SDValue Src1 = Op.getOperand(1);
15127 SDValue Src2 = Op.getOperand(2);
15128 SDValue Src0 = Op.getOperand(3);
15129 SDValue Mask = Op.getOperand(4);
15130 // There are 2 kinds of intrinsics in this group:
15131 // (1) With supress-all-exceptions (sae) or rounding mode- 6 operands
15132 // (2) With rounding mode and sae - 7 operands.
15133 if (Op.getNumOperands() == 6) {
15134 SDValue Sae = Op.getOperand(5);
15135 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
15136 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
15138 Mask, Src0, Subtarget, DAG);
15140 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
15141 SDValue RoundingMode = Op.getOperand(5);
15142 SDValue Sae = Op.getOperand(6);
15143 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
15144 RoundingMode, Sae),
15145 Mask, Src0, Subtarget, DAG);
15147 case INTR_TYPE_2OP_MASK: {
15148 SDValue Src1 = Op.getOperand(1);
15149 SDValue Src2 = Op.getOperand(2);
15150 SDValue PassThru = Op.getOperand(3);
15151 SDValue Mask = Op.getOperand(4);
15152 // We specify 2 possible opcodes for intrinsics with rounding modes.
15153 // First, we check if the intrinsic may have non-default rounding mode,
15154 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15155 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15156 if (IntrWithRoundingModeOpcode != 0) {
15157 SDValue Rnd = Op.getOperand(5);
15158 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15159 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15160 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15161 dl, Op.getValueType(),
15163 Mask, PassThru, Subtarget, DAG);
15166 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15168 Mask, PassThru, Subtarget, DAG);
15170 case FMA_OP_MASK: {
15171 SDValue Src1 = Op.getOperand(1);
15172 SDValue Src2 = Op.getOperand(2);
15173 SDValue Src3 = Op.getOperand(3);
15174 SDValue Mask = Op.getOperand(4);
15175 // We specify 2 possible opcodes for intrinsics with rounding modes.
15176 // First, we check if the intrinsic may have non-default rounding mode,
15177 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15178 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15179 if (IntrWithRoundingModeOpcode != 0) {
15180 SDValue Rnd = Op.getOperand(5);
15181 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15182 X86::STATIC_ROUNDING::CUR_DIRECTION)
15183 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15184 dl, Op.getValueType(),
15185 Src1, Src2, Src3, Rnd),
15186 Mask, Src1, Subtarget, DAG);
15188 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
15189 dl, Op.getValueType(),
15191 Mask, Src1, Subtarget, DAG);
15194 case CMP_MASK_CC: {
15195 // Comparison intrinsics with masks.
15196 // Example of transformation:
15197 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
15198 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
15200 // (v8i1 (insert_subvector undef,
15201 // (v2i1 (and (PCMPEQM %a, %b),
15202 // (extract_subvector
15203 // (v8i1 (bitcast %mask)), 0))), 0))))
15204 EVT VT = Op.getOperand(1).getValueType();
15205 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15206 VT.getVectorNumElements());
15207 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
15208 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15209 Mask.getValueType().getSizeInBits());
15211 if (IntrData->Type == CMP_MASK_CC) {
15212 SDValue CC = Op.getOperand(3);
15213 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
15214 // We specify 2 possible opcodes for intrinsics with rounding modes.
15215 // First, we check if the intrinsic may have non-default rounding mode,
15216 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15217 if (IntrData->Opc1 != 0) {
15218 SDValue Rnd = Op.getOperand(5);
15219 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15220 X86::STATIC_ROUNDING::CUR_DIRECTION)
15221 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
15222 Op.getOperand(2), CC, Rnd);
15224 //default rounding mode
15226 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15227 Op.getOperand(2), CC);
15230 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
15231 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15234 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
15235 DAG.getTargetConstant(0, dl,
15238 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
15239 DAG.getUNDEF(BitcastVT), CmpMask,
15240 DAG.getIntPtrConstant(0, dl));
15241 return DAG.getBitcast(Op.getValueType(), Res);
15243 case COMI: { // Comparison intrinsics
15244 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15245 SDValue LHS = Op.getOperand(1);
15246 SDValue RHS = Op.getOperand(2);
15247 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
15248 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15249 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15250 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15251 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
15252 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15255 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15256 Op.getOperand(1), Op.getOperand(2), DAG);
15258 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
15259 Op.getSimpleValueType(),
15261 Op.getOperand(2), DAG),
15262 Op.getOperand(4), Op.getOperand(3), Subtarget,
15264 case COMPRESS_EXPAND_IN_REG: {
15265 SDValue Mask = Op.getOperand(3);
15266 SDValue DataToCompress = Op.getOperand(1);
15267 SDValue PassThru = Op.getOperand(2);
15268 if (isAllOnes(Mask)) // return data as is
15269 return Op.getOperand(1);
15270 EVT VT = Op.getValueType();
15271 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15272 VT.getVectorNumElements());
15273 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15274 Mask.getValueType().getSizeInBits());
15276 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15277 DAG.getBitcast(BitcastVT, Mask),
15278 DAG.getIntPtrConstant(0, dl));
15280 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
15284 SDValue Mask = Op.getOperand(3);
15285 EVT VT = Op.getValueType();
15286 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15287 VT.getVectorNumElements());
15288 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15289 Mask.getValueType().getSizeInBits());
15291 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15292 DAG.getBitcast(BitcastVT, Mask),
15293 DAG.getIntPtrConstant(0, dl));
15294 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
15303 default: return SDValue(); // Don't custom lower most intrinsics.
15305 case Intrinsic::x86_avx2_permd:
15306 case Intrinsic::x86_avx2_permps:
15307 // Operands intentionally swapped. Mask is last operand to intrinsic,
15308 // but second operand for node/instruction.
15309 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15310 Op.getOperand(2), Op.getOperand(1));
15312 case Intrinsic::x86_avx512_mask_valign_q_512:
15313 case Intrinsic::x86_avx512_mask_valign_d_512:
15314 // Vector source operands are swapped.
15315 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15316 Op.getValueType(), Op.getOperand(2),
15319 Op.getOperand(5), Op.getOperand(4),
15322 // ptest and testp intrinsics. The intrinsic these come from are designed to
15323 // return an integer value, not just an instruction so lower it to the ptest
15324 // or testp pattern and a setcc for the result.
15325 case Intrinsic::x86_sse41_ptestz:
15326 case Intrinsic::x86_sse41_ptestc:
15327 case Intrinsic::x86_sse41_ptestnzc:
15328 case Intrinsic::x86_avx_ptestz_256:
15329 case Intrinsic::x86_avx_ptestc_256:
15330 case Intrinsic::x86_avx_ptestnzc_256:
15331 case Intrinsic::x86_avx_vtestz_ps:
15332 case Intrinsic::x86_avx_vtestc_ps:
15333 case Intrinsic::x86_avx_vtestnzc_ps:
15334 case Intrinsic::x86_avx_vtestz_pd:
15335 case Intrinsic::x86_avx_vtestc_pd:
15336 case Intrinsic::x86_avx_vtestnzc_pd:
15337 case Intrinsic::x86_avx_vtestz_ps_256:
15338 case Intrinsic::x86_avx_vtestc_ps_256:
15339 case Intrinsic::x86_avx_vtestnzc_ps_256:
15340 case Intrinsic::x86_avx_vtestz_pd_256:
15341 case Intrinsic::x86_avx_vtestc_pd_256:
15342 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15343 bool IsTestPacked = false;
15346 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15347 case Intrinsic::x86_avx_vtestz_ps:
15348 case Intrinsic::x86_avx_vtestz_pd:
15349 case Intrinsic::x86_avx_vtestz_ps_256:
15350 case Intrinsic::x86_avx_vtestz_pd_256:
15351 IsTestPacked = true; // Fallthrough
15352 case Intrinsic::x86_sse41_ptestz:
15353 case Intrinsic::x86_avx_ptestz_256:
15355 X86CC = X86::COND_E;
15357 case Intrinsic::x86_avx_vtestc_ps:
15358 case Intrinsic::x86_avx_vtestc_pd:
15359 case Intrinsic::x86_avx_vtestc_ps_256:
15360 case Intrinsic::x86_avx_vtestc_pd_256:
15361 IsTestPacked = true; // Fallthrough
15362 case Intrinsic::x86_sse41_ptestc:
15363 case Intrinsic::x86_avx_ptestc_256:
15365 X86CC = X86::COND_B;
15367 case Intrinsic::x86_avx_vtestnzc_ps:
15368 case Intrinsic::x86_avx_vtestnzc_pd:
15369 case Intrinsic::x86_avx_vtestnzc_ps_256:
15370 case Intrinsic::x86_avx_vtestnzc_pd_256:
15371 IsTestPacked = true; // Fallthrough
15372 case Intrinsic::x86_sse41_ptestnzc:
15373 case Intrinsic::x86_avx_ptestnzc_256:
15375 X86CC = X86::COND_A;
15379 SDValue LHS = Op.getOperand(1);
15380 SDValue RHS = Op.getOperand(2);
15381 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15382 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15383 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15384 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15385 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15387 case Intrinsic::x86_avx512_kortestz_w:
15388 case Intrinsic::x86_avx512_kortestc_w: {
15389 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15390 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
15391 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
15392 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15393 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15394 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15395 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15398 case Intrinsic::x86_sse42_pcmpistria128:
15399 case Intrinsic::x86_sse42_pcmpestria128:
15400 case Intrinsic::x86_sse42_pcmpistric128:
15401 case Intrinsic::x86_sse42_pcmpestric128:
15402 case Intrinsic::x86_sse42_pcmpistrio128:
15403 case Intrinsic::x86_sse42_pcmpestrio128:
15404 case Intrinsic::x86_sse42_pcmpistris128:
15405 case Intrinsic::x86_sse42_pcmpestris128:
15406 case Intrinsic::x86_sse42_pcmpistriz128:
15407 case Intrinsic::x86_sse42_pcmpestriz128: {
15411 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15412 case Intrinsic::x86_sse42_pcmpistria128:
15413 Opcode = X86ISD::PCMPISTRI;
15414 X86CC = X86::COND_A;
15416 case Intrinsic::x86_sse42_pcmpestria128:
15417 Opcode = X86ISD::PCMPESTRI;
15418 X86CC = X86::COND_A;
15420 case Intrinsic::x86_sse42_pcmpistric128:
15421 Opcode = X86ISD::PCMPISTRI;
15422 X86CC = X86::COND_B;
15424 case Intrinsic::x86_sse42_pcmpestric128:
15425 Opcode = X86ISD::PCMPESTRI;
15426 X86CC = X86::COND_B;
15428 case Intrinsic::x86_sse42_pcmpistrio128:
15429 Opcode = X86ISD::PCMPISTRI;
15430 X86CC = X86::COND_O;
15432 case Intrinsic::x86_sse42_pcmpestrio128:
15433 Opcode = X86ISD::PCMPESTRI;
15434 X86CC = X86::COND_O;
15436 case Intrinsic::x86_sse42_pcmpistris128:
15437 Opcode = X86ISD::PCMPISTRI;
15438 X86CC = X86::COND_S;
15440 case Intrinsic::x86_sse42_pcmpestris128:
15441 Opcode = X86ISD::PCMPESTRI;
15442 X86CC = X86::COND_S;
15444 case Intrinsic::x86_sse42_pcmpistriz128:
15445 Opcode = X86ISD::PCMPISTRI;
15446 X86CC = X86::COND_E;
15448 case Intrinsic::x86_sse42_pcmpestriz128:
15449 Opcode = X86ISD::PCMPESTRI;
15450 X86CC = X86::COND_E;
15453 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15454 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15455 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15456 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15457 DAG.getConstant(X86CC, dl, MVT::i8),
15458 SDValue(PCMP.getNode(), 1));
15459 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15462 case Intrinsic::x86_sse42_pcmpistri128:
15463 case Intrinsic::x86_sse42_pcmpestri128: {
15465 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15466 Opcode = X86ISD::PCMPISTRI;
15468 Opcode = X86ISD::PCMPESTRI;
15470 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15471 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15472 return DAG.getNode(Opcode, dl, VTs, NewOps);
15475 case Intrinsic::x86_seh_lsda: {
15476 // Compute the symbol for the LSDA. We know it'll get emitted later.
15477 MachineFunction &MF = DAG.getMachineFunction();
15478 SDValue Op1 = Op.getOperand(1);
15479 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
15480 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
15481 GlobalValue::getRealLinkageName(Fn->getName()));
15482 StringRef Name = LSDASym->getName();
15483 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
15485 // Generate a simple absolute symbol reference. This intrinsic is only
15486 // supported on 32-bit Windows, which isn't PIC.
15488 DAG.getTargetExternalSymbol(Name.data(), VT, X86II::MO_NOPREFIX);
15489 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
15494 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15495 SDValue Src, SDValue Mask, SDValue Base,
15496 SDValue Index, SDValue ScaleOp, SDValue Chain,
15497 const X86Subtarget * Subtarget) {
15499 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15500 assert(C && "Invalid scale type");
15501 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15502 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15503 Index.getSimpleValueType().getVectorNumElements());
15505 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15507 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15509 MaskInReg = DAG.getBitcast(MaskVT, Mask);
15510 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15511 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15512 SDValue Segment = DAG.getRegister(0, MVT::i32);
15513 if (Src.getOpcode() == ISD::UNDEF)
15514 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15515 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15516 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15517 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15518 return DAG.getMergeValues(RetOps, dl);
15521 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15522 SDValue Src, SDValue Mask, SDValue Base,
15523 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15525 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15526 assert(C && "Invalid scale type");
15527 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15528 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15529 SDValue Segment = DAG.getRegister(0, MVT::i32);
15530 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15531 Index.getSimpleValueType().getVectorNumElements());
15533 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15535 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15537 MaskInReg = DAG.getBitcast(MaskVT, Mask);
15538 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15539 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15540 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15541 return SDValue(Res, 1);
15544 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15545 SDValue Mask, SDValue Base, SDValue Index,
15546 SDValue ScaleOp, SDValue Chain) {
15548 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15549 assert(C && "Invalid scale type");
15550 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15551 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15552 SDValue Segment = DAG.getRegister(0, MVT::i32);
15554 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15556 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15558 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15560 MaskInReg = DAG.getBitcast(MaskVT, Mask);
15561 //SDVTList VTs = DAG.getVTList(MVT::Other);
15562 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15563 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15564 return SDValue(Res, 0);
15567 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15568 // read performance monitor counters (x86_rdpmc).
15569 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15570 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15571 SmallVectorImpl<SDValue> &Results) {
15572 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15573 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15576 // The ECX register is used to select the index of the performance counter
15578 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15580 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15582 // Reads the content of a 64-bit performance counter and returns it in the
15583 // registers EDX:EAX.
15584 if (Subtarget->is64Bit()) {
15585 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15586 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15589 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15590 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15593 Chain = HI.getValue(1);
15595 if (Subtarget->is64Bit()) {
15596 // The EAX register is loaded with the low-order 32 bits. The EDX register
15597 // is loaded with the supported high-order bits of the counter.
15598 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15599 DAG.getConstant(32, DL, MVT::i8));
15600 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15601 Results.push_back(Chain);
15605 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15606 SDValue Ops[] = { LO, HI };
15607 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15608 Results.push_back(Pair);
15609 Results.push_back(Chain);
15612 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15613 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15614 // also used to custom lower READCYCLECOUNTER nodes.
15615 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15616 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15617 SmallVectorImpl<SDValue> &Results) {
15618 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15619 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15622 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15623 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15624 // and the EAX register is loaded with the low-order 32 bits.
15625 if (Subtarget->is64Bit()) {
15626 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15627 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15630 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15631 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15634 SDValue Chain = HI.getValue(1);
15636 if (Opcode == X86ISD::RDTSCP_DAG) {
15637 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15639 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15640 // the ECX register. Add 'ecx' explicitly to the chain.
15641 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15643 // Explicitly store the content of ECX at the location passed in input
15644 // to the 'rdtscp' intrinsic.
15645 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15646 MachinePointerInfo(), false, false, 0);
15649 if (Subtarget->is64Bit()) {
15650 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15651 // the EAX register is loaded with the low-order 32 bits.
15652 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15653 DAG.getConstant(32, DL, MVT::i8));
15654 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15655 Results.push_back(Chain);
15659 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15660 SDValue Ops[] = { LO, HI };
15661 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15662 Results.push_back(Pair);
15663 Results.push_back(Chain);
15666 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15667 SelectionDAG &DAG) {
15668 SmallVector<SDValue, 2> Results;
15670 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15672 return DAG.getMergeValues(Results, DL);
15676 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15677 SelectionDAG &DAG) {
15678 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15680 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15685 switch(IntrData->Type) {
15687 llvm_unreachable("Unknown Intrinsic Type");
15691 // Emit the node with the right value type.
15692 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15693 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15695 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15696 // Otherwise return the value from Rand, which is always 0, casted to i32.
15697 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15698 DAG.getConstant(1, dl, Op->getValueType(1)),
15699 DAG.getConstant(X86::COND_B, dl, MVT::i32),
15700 SDValue(Result.getNode(), 1) };
15701 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15702 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15705 // Return { result, isValid, chain }.
15706 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15707 SDValue(Result.getNode(), 2));
15710 //gather(v1, mask, index, base, scale);
15711 SDValue Chain = Op.getOperand(0);
15712 SDValue Src = Op.getOperand(2);
15713 SDValue Base = Op.getOperand(3);
15714 SDValue Index = Op.getOperand(4);
15715 SDValue Mask = Op.getOperand(5);
15716 SDValue Scale = Op.getOperand(6);
15717 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
15721 //scatter(base, mask, index, v1, scale);
15722 SDValue Chain = Op.getOperand(0);
15723 SDValue Base = Op.getOperand(2);
15724 SDValue Mask = Op.getOperand(3);
15725 SDValue Index = Op.getOperand(4);
15726 SDValue Src = Op.getOperand(5);
15727 SDValue Scale = Op.getOperand(6);
15728 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
15732 SDValue Hint = Op.getOperand(6);
15733 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
15734 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
15735 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15736 SDValue Chain = Op.getOperand(0);
15737 SDValue Mask = Op.getOperand(2);
15738 SDValue Index = Op.getOperand(3);
15739 SDValue Base = Op.getOperand(4);
15740 SDValue Scale = Op.getOperand(5);
15741 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15743 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15745 SmallVector<SDValue, 2> Results;
15746 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
15748 return DAG.getMergeValues(Results, dl);
15750 // Read Performance Monitoring Counters.
15752 SmallVector<SDValue, 2> Results;
15753 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15754 return DAG.getMergeValues(Results, dl);
15756 // XTEST intrinsics.
15758 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15759 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15760 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15761 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
15763 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15764 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15765 Ret, SDValue(InTrans.getNode(), 1));
15769 SmallVector<SDValue, 2> Results;
15770 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15771 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15772 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15773 DAG.getConstant(-1, dl, MVT::i8));
15774 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15775 Op.getOperand(4), GenCF.getValue(1));
15776 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15777 Op.getOperand(5), MachinePointerInfo(),
15779 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15780 DAG.getConstant(X86::COND_B, dl, MVT::i8),
15782 Results.push_back(SetCC);
15783 Results.push_back(Store);
15784 return DAG.getMergeValues(Results, dl);
15786 case COMPRESS_TO_MEM: {
15788 SDValue Mask = Op.getOperand(4);
15789 SDValue DataToCompress = Op.getOperand(3);
15790 SDValue Addr = Op.getOperand(2);
15791 SDValue Chain = Op.getOperand(0);
15793 EVT VT = DataToCompress.getValueType();
15794 if (isAllOnes(Mask)) // return just a store
15795 return DAG.getStore(Chain, dl, DataToCompress, Addr,
15796 MachinePointerInfo(), false, false,
15797 VT.getScalarSizeInBits()/8);
15799 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15800 VT.getVectorNumElements());
15801 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15802 Mask.getValueType().getSizeInBits());
15803 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15804 DAG.getBitcast(BitcastVT, Mask),
15805 DAG.getIntPtrConstant(0, dl));
15807 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
15808 DataToCompress, DAG.getUNDEF(VT));
15809 return DAG.getStore(Chain, dl, Compressed, Addr,
15810 MachinePointerInfo(), false, false,
15811 VT.getScalarSizeInBits()/8);
15813 case EXPAND_FROM_MEM: {
15815 SDValue Mask = Op.getOperand(4);
15816 SDValue PathThru = Op.getOperand(3);
15817 SDValue Addr = Op.getOperand(2);
15818 SDValue Chain = Op.getOperand(0);
15819 EVT VT = Op.getValueType();
15821 if (isAllOnes(Mask)) // return just a load
15822 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
15823 false, VT.getScalarSizeInBits()/8);
15824 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15825 VT.getVectorNumElements());
15826 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15827 Mask.getValueType().getSizeInBits());
15828 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15829 DAG.getBitcast(BitcastVT, Mask),
15830 DAG.getIntPtrConstant(0, dl));
15832 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
15833 false, false, false,
15834 VT.getScalarSizeInBits()/8);
15836 SDValue Results[] = {
15837 DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand, PathThru),
15839 return DAG.getMergeValues(Results, dl);
15844 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15845 SelectionDAG &DAG) const {
15846 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15847 MFI->setReturnAddressIsTaken(true);
15849 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15852 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15854 EVT PtrVT = getPointerTy();
15857 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15858 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15859 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
15860 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15861 DAG.getNode(ISD::ADD, dl, PtrVT,
15862 FrameAddr, Offset),
15863 MachinePointerInfo(), false, false, false, 0);
15866 // Just load the return address.
15867 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15868 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15869 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15872 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15873 MachineFunction &MF = DAG.getMachineFunction();
15874 MachineFrameInfo *MFI = MF.getFrameInfo();
15875 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15876 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15877 EVT VT = Op.getValueType();
15879 MFI->setFrameAddressIsTaken(true);
15881 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
15882 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
15883 // is not possible to crawl up the stack without looking at the unwind codes
15885 int FrameAddrIndex = FuncInfo->getFAIndex();
15886 if (!FrameAddrIndex) {
15887 // Set up a frame object for the return address.
15888 unsigned SlotSize = RegInfo->getSlotSize();
15889 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
15890 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
15891 FuncInfo->setFAIndex(FrameAddrIndex);
15893 return DAG.getFrameIndex(FrameAddrIndex, VT);
15896 unsigned FrameReg =
15897 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15898 SDLoc dl(Op); // FIXME probably not meaningful
15899 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15900 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15901 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15902 "Invalid Frame Register!");
15903 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15905 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15906 MachinePointerInfo(),
15907 false, false, false, 0);
15911 // FIXME? Maybe this could be a TableGen attribute on some registers and
15912 // this table could be generated automatically from RegInfo.
15913 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15915 unsigned Reg = StringSwitch<unsigned>(RegName)
15916 .Case("esp", X86::ESP)
15917 .Case("rsp", X86::RSP)
15921 report_fatal_error("Invalid register name global variable");
15924 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15925 SelectionDAG &DAG) const {
15926 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15927 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
15930 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15931 SDValue Chain = Op.getOperand(0);
15932 SDValue Offset = Op.getOperand(1);
15933 SDValue Handler = Op.getOperand(2);
15936 EVT PtrVT = getPointerTy();
15937 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15938 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15939 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15940 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15941 "Invalid Frame Register!");
15942 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15943 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15945 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15946 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
15948 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15949 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15951 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15953 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15954 DAG.getRegister(StoreAddrReg, PtrVT));
15957 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15958 SelectionDAG &DAG) const {
15960 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15961 DAG.getVTList(MVT::i32, MVT::Other),
15962 Op.getOperand(0), Op.getOperand(1));
15965 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15966 SelectionDAG &DAG) const {
15968 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15969 Op.getOperand(0), Op.getOperand(1));
15972 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15973 return Op.getOperand(0);
15976 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15977 SelectionDAG &DAG) const {
15978 SDValue Root = Op.getOperand(0);
15979 SDValue Trmp = Op.getOperand(1); // trampoline
15980 SDValue FPtr = Op.getOperand(2); // nested function
15981 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15984 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15985 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
15987 if (Subtarget->is64Bit()) {
15988 SDValue OutChains[6];
15990 // Large code-model.
15991 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15992 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15994 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15995 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15997 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15999 // Load the pointer to the nested function into R11.
16000 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16001 SDValue Addr = Trmp;
16002 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16003 Addr, MachinePointerInfo(TrmpAddr),
16006 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16007 DAG.getConstant(2, dl, MVT::i64));
16008 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16009 MachinePointerInfo(TrmpAddr, 2),
16012 // Load the 'nest' parameter value into R10.
16013 // R10 is specified in X86CallingConv.td
16014 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16015 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16016 DAG.getConstant(10, dl, MVT::i64));
16017 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16018 Addr, MachinePointerInfo(TrmpAddr, 10),
16021 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16022 DAG.getConstant(12, dl, MVT::i64));
16023 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16024 MachinePointerInfo(TrmpAddr, 12),
16027 // Jump to the nested function.
16028 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16029 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16030 DAG.getConstant(20, dl, MVT::i64));
16031 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16032 Addr, MachinePointerInfo(TrmpAddr, 20),
16035 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16036 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16037 DAG.getConstant(22, dl, MVT::i64));
16038 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
16039 Addr, MachinePointerInfo(TrmpAddr, 22),
16042 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16044 const Function *Func =
16045 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16046 CallingConv::ID CC = Func->getCallingConv();
16051 llvm_unreachable("Unsupported calling convention");
16052 case CallingConv::C:
16053 case CallingConv::X86_StdCall: {
16054 // Pass 'nest' parameter in ECX.
16055 // Must be kept in sync with X86CallingConv.td
16056 NestReg = X86::ECX;
16058 // Check that ECX wasn't needed by an 'inreg' parameter.
16059 FunctionType *FTy = Func->getFunctionType();
16060 const AttributeSet &Attrs = Func->getAttributes();
16062 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16063 unsigned InRegCount = 0;
16066 for (FunctionType::param_iterator I = FTy->param_begin(),
16067 E = FTy->param_end(); I != E; ++I, ++Idx)
16068 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16069 // FIXME: should only count parameters that are lowered to integers.
16070 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16072 if (InRegCount > 2) {
16073 report_fatal_error("Nest register in use - reduce number of inreg"
16079 case CallingConv::X86_FastCall:
16080 case CallingConv::X86_ThisCall:
16081 case CallingConv::Fast:
16082 // Pass 'nest' parameter in EAX.
16083 // Must be kept in sync with X86CallingConv.td
16084 NestReg = X86::EAX;
16088 SDValue OutChains[4];
16089 SDValue Addr, Disp;
16091 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16092 DAG.getConstant(10, dl, MVT::i32));
16093 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16095 // This is storing the opcode for MOV32ri.
16096 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16097 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16098 OutChains[0] = DAG.getStore(Root, dl,
16099 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
16100 Trmp, MachinePointerInfo(TrmpAddr),
16103 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16104 DAG.getConstant(1, dl, MVT::i32));
16105 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16106 MachinePointerInfo(TrmpAddr, 1),
16109 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16110 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16111 DAG.getConstant(5, dl, MVT::i32));
16112 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
16113 Addr, MachinePointerInfo(TrmpAddr, 5),
16116 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16117 DAG.getConstant(6, dl, MVT::i32));
16118 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16119 MachinePointerInfo(TrmpAddr, 6),
16122 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16126 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16127 SelectionDAG &DAG) const {
16129 The rounding mode is in bits 11:10 of FPSR, and has the following
16131 00 Round to nearest
16136 FLT_ROUNDS, on the other hand, expects the following:
16143 To perform the conversion, we do:
16144 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16147 MachineFunction &MF = DAG.getMachineFunction();
16148 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
16149 unsigned StackAlignment = TFI.getStackAlignment();
16150 MVT VT = Op.getSimpleValueType();
16153 // Save FP Control Word to stack slot
16154 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16155 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16157 MachineMemOperand *MMO =
16158 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16159 MachineMemOperand::MOStore, 2, 2);
16161 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16162 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16163 DAG.getVTList(MVT::Other),
16164 Ops, MVT::i16, MMO);
16166 // Load FP Control Word from stack slot
16167 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16168 MachinePointerInfo(), false, false, false, 0);
16170 // Transform as necessary
16172 DAG.getNode(ISD::SRL, DL, MVT::i16,
16173 DAG.getNode(ISD::AND, DL, MVT::i16,
16174 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
16175 DAG.getConstant(11, DL, MVT::i8));
16177 DAG.getNode(ISD::SRL, DL, MVT::i16,
16178 DAG.getNode(ISD::AND, DL, MVT::i16,
16179 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
16180 DAG.getConstant(9, DL, MVT::i8));
16183 DAG.getNode(ISD::AND, DL, MVT::i16,
16184 DAG.getNode(ISD::ADD, DL, MVT::i16,
16185 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16186 DAG.getConstant(1, DL, MVT::i16)),
16187 DAG.getConstant(3, DL, MVT::i16));
16189 return DAG.getNode((VT.getSizeInBits() < 16 ?
16190 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16193 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16194 MVT VT = Op.getSimpleValueType();
16196 unsigned NumBits = VT.getSizeInBits();
16199 Op = Op.getOperand(0);
16200 if (VT == MVT::i8) {
16201 // Zero extend to i32 since there is not an i8 bsr.
16203 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16206 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16207 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16208 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16210 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16213 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
16214 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16217 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16219 // Finally xor with NumBits-1.
16220 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16221 DAG.getConstant(NumBits - 1, dl, OpVT));
16224 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16228 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16229 MVT VT = Op.getSimpleValueType();
16231 unsigned NumBits = VT.getSizeInBits();
16234 Op = Op.getOperand(0);
16235 if (VT == MVT::i8) {
16236 // Zero extend to i32 since there is not an i8 bsr.
16238 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16241 // Issue a bsr (scan bits in reverse).
16242 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16243 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16245 // And xor with NumBits-1.
16246 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16247 DAG.getConstant(NumBits - 1, dl, OpVT));
16250 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16254 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16255 MVT VT = Op.getSimpleValueType();
16256 unsigned NumBits = VT.getSizeInBits();
16258 Op = Op.getOperand(0);
16260 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16261 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16262 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16264 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16267 DAG.getConstant(NumBits, dl, VT),
16268 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16271 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16274 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16275 // ones, and then concatenate the result back.
16276 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16277 MVT VT = Op.getSimpleValueType();
16279 assert(VT.is256BitVector() && VT.isInteger() &&
16280 "Unsupported value type for operation");
16282 unsigned NumElems = VT.getVectorNumElements();
16285 // Extract the LHS vectors
16286 SDValue LHS = Op.getOperand(0);
16287 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16288 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16290 // Extract the RHS vectors
16291 SDValue RHS = Op.getOperand(1);
16292 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16293 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16295 MVT EltVT = VT.getVectorElementType();
16296 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16298 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16299 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16300 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16303 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16304 if (Op.getValueType() == MVT::i1)
16305 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16306 Op.getOperand(0), Op.getOperand(1));
16307 assert(Op.getSimpleValueType().is256BitVector() &&
16308 Op.getSimpleValueType().isInteger() &&
16309 "Only handle AVX 256-bit vector integer operation");
16310 return Lower256IntArith(Op, DAG);
16313 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16314 if (Op.getValueType() == MVT::i1)
16315 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16316 Op.getOperand(0), Op.getOperand(1));
16317 assert(Op.getSimpleValueType().is256BitVector() &&
16318 Op.getSimpleValueType().isInteger() &&
16319 "Only handle AVX 256-bit vector integer operation");
16320 return Lower256IntArith(Op, DAG);
16323 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16324 SelectionDAG &DAG) {
16326 MVT VT = Op.getSimpleValueType();
16329 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
16331 // Decompose 256-bit ops into smaller 128-bit ops.
16332 if (VT.is256BitVector() && !Subtarget->hasInt256())
16333 return Lower256IntArith(Op, DAG);
16335 SDValue A = Op.getOperand(0);
16336 SDValue B = Op.getOperand(1);
16338 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
16339 // pairs, multiply and truncate.
16340 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
16341 if (Subtarget->hasInt256()) {
16342 if (VT == MVT::v32i8) {
16343 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
16344 SDValue Lo = DAG.getIntPtrConstant(0, dl);
16345 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
16346 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
16347 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
16348 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
16349 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
16350 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16351 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
16352 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
16355 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
16356 return DAG.getNode(
16357 ISD::TRUNCATE, dl, VT,
16358 DAG.getNode(ISD::MUL, dl, ExVT,
16359 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
16360 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
16363 assert(VT == MVT::v16i8 &&
16364 "Pre-AVX2 support only supports v16i8 multiplication");
16365 MVT ExVT = MVT::v8i16;
16367 // Extract the lo parts and sign extend to i16
16369 if (Subtarget->hasSSE41()) {
16370 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
16371 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
16373 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
16374 -1, 4, -1, 5, -1, 6, -1, 7};
16375 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16376 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16377 ALo = DAG.getBitcast(ExVT, ALo);
16378 BLo = DAG.getBitcast(ExVT, BLo);
16379 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
16380 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
16383 // Extract the hi parts and sign extend to i16
16385 if (Subtarget->hasSSE41()) {
16386 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
16387 -1, -1, -1, -1, -1, -1, -1, -1};
16388 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16389 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16390 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
16391 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
16393 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
16394 -1, 12, -1, 13, -1, 14, -1, 15};
16395 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16396 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16397 AHi = DAG.getBitcast(ExVT, AHi);
16398 BHi = DAG.getBitcast(ExVT, BHi);
16399 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
16400 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
16403 // Multiply, mask the lower 8bits of the lo/hi results and pack
16404 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
16405 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
16406 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
16407 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
16408 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
16411 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16412 if (VT == MVT::v4i32) {
16413 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16414 "Should not custom lower when pmuldq is available!");
16416 // Extract the odd parts.
16417 static const int UnpackMask[] = { 1, -1, 3, -1 };
16418 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16419 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16421 // Multiply the even parts.
16422 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16423 // Now multiply odd parts.
16424 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16426 Evens = DAG.getBitcast(VT, Evens);
16427 Odds = DAG.getBitcast(VT, Odds);
16429 // Merge the two vectors back together with a shuffle. This expands into 2
16431 static const int ShufMask[] = { 0, 4, 2, 6 };
16432 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16435 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16436 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16438 // Ahi = psrlqi(a, 32);
16439 // Bhi = psrlqi(b, 32);
16441 // AloBlo = pmuludq(a, b);
16442 // AloBhi = pmuludq(a, Bhi);
16443 // AhiBlo = pmuludq(Ahi, b);
16445 // AloBhi = psllqi(AloBhi, 32);
16446 // AhiBlo = psllqi(AhiBlo, 32);
16447 // return AloBlo + AloBhi + AhiBlo;
16449 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16450 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16452 // Bit cast to 32-bit vectors for MULUDQ
16453 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16454 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16455 A = DAG.getBitcast(MulVT, A);
16456 B = DAG.getBitcast(MulVT, B);
16457 Ahi = DAG.getBitcast(MulVT, Ahi);
16458 Bhi = DAG.getBitcast(MulVT, Bhi);
16460 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16461 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16462 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16464 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16465 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16467 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16468 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16471 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16472 assert(Subtarget->isTargetWin64() && "Unexpected target");
16473 EVT VT = Op.getValueType();
16474 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16475 "Unexpected return type for lowering");
16479 switch (Op->getOpcode()) {
16480 default: llvm_unreachable("Unexpected request for libcall!");
16481 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16482 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16483 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16484 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16485 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16486 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16490 SDValue InChain = DAG.getEntryNode();
16492 TargetLowering::ArgListTy Args;
16493 TargetLowering::ArgListEntry Entry;
16494 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16495 EVT ArgVT = Op->getOperand(i).getValueType();
16496 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16497 "Unexpected argument type for lowering");
16498 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16499 Entry.Node = StackPtr;
16500 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16502 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16503 Entry.Ty = PointerType::get(ArgTy,0);
16504 Entry.isSExt = false;
16505 Entry.isZExt = false;
16506 Args.push_back(Entry);
16509 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16512 TargetLowering::CallLoweringInfo CLI(DAG);
16513 CLI.setDebugLoc(dl).setChain(InChain)
16514 .setCallee(getLibcallCallingConv(LC),
16515 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16516 Callee, std::move(Args), 0)
16517 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16519 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16520 return DAG.getBitcast(VT, CallInfo.first);
16523 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16524 SelectionDAG &DAG) {
16525 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16526 EVT VT = Op0.getValueType();
16529 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16530 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16532 // PMULxD operations multiply each even value (starting at 0) of LHS with
16533 // the related value of RHS and produce a widen result.
16534 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16535 // => <2 x i64> <ae|cg>
16537 // In other word, to have all the results, we need to perform two PMULxD:
16538 // 1. one with the even values.
16539 // 2. one with the odd values.
16540 // To achieve #2, with need to place the odd values at an even position.
16542 // Place the odd value at an even position (basically, shift all values 1
16543 // step to the left):
16544 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16545 // <a|b|c|d> => <b|undef|d|undef>
16546 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16547 // <e|f|g|h> => <f|undef|h|undef>
16548 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16550 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16552 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16553 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16555 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16556 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16557 // => <2 x i64> <ae|cg>
16558 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16559 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16560 // => <2 x i64> <bf|dh>
16561 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16563 // Shuffle it back into the right order.
16564 SDValue Highs, Lows;
16565 if (VT == MVT::v8i32) {
16566 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16567 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16568 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16569 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16571 const int HighMask[] = {1, 5, 3, 7};
16572 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16573 const int LowMask[] = {0, 4, 2, 6};
16574 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16577 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16578 // unsigned multiply.
16579 if (IsSigned && !Subtarget->hasSSE41()) {
16581 DAG.getConstant(31, dl,
16582 DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16583 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16584 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16585 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16586 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16588 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16589 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16592 // The first result of MUL_LOHI is actually the low value, followed by the
16594 SDValue Ops[] = {Lows, Highs};
16595 return DAG.getMergeValues(Ops, dl);
16598 // Return true if the requred (according to Opcode) shift-imm form is natively
16599 // supported by the Subtarget
16600 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
16602 if (VT.getScalarSizeInBits() < 16)
16605 if (VT.is512BitVector() &&
16606 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
16609 bool LShift = VT.is128BitVector() ||
16610 (VT.is256BitVector() && Subtarget->hasInt256());
16612 bool AShift = LShift && (Subtarget->hasVLX() ||
16613 (VT != MVT::v2i64 && VT != MVT::v4i64));
16614 return (Opcode == ISD::SRA) ? AShift : LShift;
16617 // The shift amount is a variable, but it is the same for all vector lanes.
16618 // These instrcutions are defined together with shift-immediate.
16620 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
16622 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
16625 // Return true if the requred (according to Opcode) variable-shift form is
16626 // natively supported by the Subtarget
16627 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
16630 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
16633 // vXi16 supported only on AVX-512, BWI
16634 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
16637 if (VT.is512BitVector() || Subtarget->hasVLX())
16640 bool LShift = VT.is128BitVector() || VT.is256BitVector();
16641 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
16642 return (Opcode == ISD::SRA) ? AShift : LShift;
16645 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16646 const X86Subtarget *Subtarget) {
16647 MVT VT = Op.getSimpleValueType();
16649 SDValue R = Op.getOperand(0);
16650 SDValue Amt = Op.getOperand(1);
16652 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16653 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16655 // Optimize shl/srl/sra with constant shift amount.
16656 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16657 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16658 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16660 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
16661 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16663 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
16664 unsigned NumElts = VT.getVectorNumElements();
16665 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
16667 if (Op.getOpcode() == ISD::SHL) {
16668 // Simple i8 add case
16670 return DAG.getNode(ISD::ADD, dl, VT, R, R);
16672 // Make a large shift.
16673 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
16675 SHL = DAG.getBitcast(VT, SHL);
16676 // Zero out the rightmost bits.
16677 SmallVector<SDValue, 32> V(
16678 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
16679 return DAG.getNode(ISD::AND, dl, VT, SHL,
16680 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16682 if (Op.getOpcode() == ISD::SRL) {
16683 // Make a large shift.
16684 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
16686 SRL = DAG.getBitcast(VT, SRL);
16687 // Zero out the leftmost bits.
16688 SmallVector<SDValue, 32> V(
16689 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
16690 return DAG.getNode(ISD::AND, dl, VT, SRL,
16691 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16693 if (Op.getOpcode() == ISD::SRA) {
16694 if (ShiftAmt == 7) {
16695 // R s>> 7 === R s< 0
16696 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16697 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16700 // R s>> a === ((R u>> a) ^ m) - m
16701 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16702 SmallVector<SDValue, 32> V(NumElts,
16703 DAG.getConstant(128 >> ShiftAmt, dl,
16705 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16706 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16707 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16710 llvm_unreachable("Unknown shift opcode.");
16715 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16716 if (!Subtarget->is64Bit() &&
16717 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16718 Amt.getOpcode() == ISD::BITCAST &&
16719 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16720 Amt = Amt.getOperand(0);
16721 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16722 VT.getVectorNumElements();
16723 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16724 uint64_t ShiftAmt = 0;
16725 for (unsigned i = 0; i != Ratio; ++i) {
16726 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16730 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16732 // Check remaining shift amounts.
16733 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16734 uint64_t ShAmt = 0;
16735 for (unsigned j = 0; j != Ratio; ++j) {
16736 ConstantSDNode *C =
16737 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16741 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16743 if (ShAmt != ShiftAmt)
16746 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16752 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16753 const X86Subtarget* Subtarget) {
16754 MVT VT = Op.getSimpleValueType();
16756 SDValue R = Op.getOperand(0);
16757 SDValue Amt = Op.getOperand(1);
16759 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16760 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16762 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
16763 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
16765 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
16767 EVT EltVT = VT.getVectorElementType();
16769 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
16770 // Check if this build_vector node is doing a splat.
16771 // If so, then set BaseShAmt equal to the splat value.
16772 BaseShAmt = BV->getSplatValue();
16773 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
16774 BaseShAmt = SDValue();
16776 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16777 Amt = Amt.getOperand(0);
16779 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
16780 if (SVN && SVN->isSplat()) {
16781 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
16782 SDValue InVec = Amt.getOperand(0);
16783 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16784 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
16785 "Unexpected shuffle index found!");
16786 BaseShAmt = InVec.getOperand(SplatIdx);
16787 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16788 if (ConstantSDNode *C =
16789 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16790 if (C->getZExtValue() == SplatIdx)
16791 BaseShAmt = InVec.getOperand(1);
16796 // Avoid introducing an extract element from a shuffle.
16797 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
16798 DAG.getIntPtrConstant(SplatIdx, dl));
16802 if (BaseShAmt.getNode()) {
16803 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
16804 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
16805 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
16806 else if (EltVT.bitsLT(MVT::i32))
16807 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16809 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
16813 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16814 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
16815 Amt.getOpcode() == ISD::BITCAST &&
16816 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16817 Amt = Amt.getOperand(0);
16818 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16819 VT.getVectorNumElements();
16820 std::vector<SDValue> Vals(Ratio);
16821 for (unsigned i = 0; i != Ratio; ++i)
16822 Vals[i] = Amt.getOperand(i);
16823 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16824 for (unsigned j = 0; j != Ratio; ++j)
16825 if (Vals[j] != Amt.getOperand(i + j))
16828 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
16833 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16834 SelectionDAG &DAG) {
16835 MVT VT = Op.getSimpleValueType();
16837 SDValue R = Op.getOperand(0);
16838 SDValue Amt = Op.getOperand(1);
16840 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16841 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16843 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
16846 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
16849 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
16852 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
16853 // shifts per-lane and then shuffle the partial results back together.
16854 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
16855 // Splat the shift amounts so the scalar shifts above will catch it.
16856 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
16857 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
16858 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
16859 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
16860 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
16863 // If possible, lower this packed shift into a vector multiply instead of
16864 // expanding it into a sequence of scalar shifts.
16865 // Do this only if the vector shift count is a constant build_vector.
16866 if (Op.getOpcode() == ISD::SHL &&
16867 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16868 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16869 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16870 SmallVector<SDValue, 8> Elts;
16871 EVT SVT = VT.getScalarType();
16872 unsigned SVTBits = SVT.getSizeInBits();
16873 const APInt &One = APInt(SVTBits, 1);
16874 unsigned NumElems = VT.getVectorNumElements();
16876 for (unsigned i=0; i !=NumElems; ++i) {
16877 SDValue Op = Amt->getOperand(i);
16878 if (Op->getOpcode() == ISD::UNDEF) {
16879 Elts.push_back(Op);
16883 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16884 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16885 uint64_t ShAmt = C.getZExtValue();
16886 if (ShAmt >= SVTBits) {
16887 Elts.push_back(DAG.getUNDEF(SVT));
16890 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
16892 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16893 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16896 // Lower SHL with variable shift amount.
16897 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16898 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
16900 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
16901 DAG.getConstant(0x3f800000U, dl, VT));
16902 Op = DAG.getBitcast(MVT::v4f32, Op);
16903 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16904 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16907 // If possible, lower this shift as a sequence of two shifts by
16908 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16910 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16912 // Could be rewritten as:
16913 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16915 // The advantage is that the two shifts from the example would be
16916 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16917 // the vector shift into four scalar shifts plus four pairs of vector
16919 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16920 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16921 unsigned TargetOpcode = X86ISD::MOVSS;
16922 bool CanBeSimplified;
16923 // The splat value for the first packed shift (the 'X' from the example).
16924 SDValue Amt1 = Amt->getOperand(0);
16925 // The splat value for the second packed shift (the 'Y' from the example).
16926 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16927 Amt->getOperand(2);
16929 // See if it is possible to replace this node with a sequence of
16930 // two shifts followed by a MOVSS/MOVSD
16931 if (VT == MVT::v4i32) {
16932 // Check if it is legal to use a MOVSS.
16933 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16934 Amt2 == Amt->getOperand(3);
16935 if (!CanBeSimplified) {
16936 // Otherwise, check if we can still simplify this node using a MOVSD.
16937 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16938 Amt->getOperand(2) == Amt->getOperand(3);
16939 TargetOpcode = X86ISD::MOVSD;
16940 Amt2 = Amt->getOperand(2);
16943 // Do similar checks for the case where the machine value type
16945 CanBeSimplified = Amt1 == Amt->getOperand(1);
16946 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16947 CanBeSimplified = Amt2 == Amt->getOperand(i);
16949 if (!CanBeSimplified) {
16950 TargetOpcode = X86ISD::MOVSD;
16951 CanBeSimplified = true;
16952 Amt2 = Amt->getOperand(4);
16953 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16954 CanBeSimplified = Amt1 == Amt->getOperand(i);
16955 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16956 CanBeSimplified = Amt2 == Amt->getOperand(j);
16960 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16961 isa<ConstantSDNode>(Amt2)) {
16962 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16963 EVT CastVT = MVT::v4i32;
16965 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
16966 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16968 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
16969 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16970 if (TargetOpcode == X86ISD::MOVSD)
16971 CastVT = MVT::v2i64;
16972 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
16973 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
16974 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16976 return DAG.getBitcast(VT, Result);
16980 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16981 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
16982 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, dl, VT));
16984 SDValue VSelM = DAG.getConstant(0x80, dl, VT);
16985 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16986 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16988 // r = VSELECT(r, shl(r, 4), a);
16989 SDValue M = DAG.getNode(ISD::SHL, dl, VT, R, DAG.getConstant(4, dl, VT));
16990 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16993 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16994 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16995 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16997 // r = VSELECT(r, shl(r, 2), a);
16998 M = DAG.getNode(ISD::SHL, dl, VT, R, DAG.getConstant(2, dl, VT));
16999 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17002 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17003 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17004 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17006 // return VSELECT(r, r+r, a);
17007 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17008 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17012 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17013 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17014 // solution better.
17015 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17016 MVT ExtVT = MVT::v8i32;
17018 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17019 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
17020 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
17021 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17022 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
17025 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
17026 MVT ExtVT = MVT::v8i32;
17027 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
17028 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
17029 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
17030 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
17031 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
17032 ALo = DAG.getBitcast(ExtVT, ALo);
17033 AHi = DAG.getBitcast(ExtVT, AHi);
17034 RLo = DAG.getBitcast(ExtVT, RLo);
17035 RHi = DAG.getBitcast(ExtVT, RHi);
17036 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
17037 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
17038 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
17039 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
17040 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
17043 // Decompose 256-bit shifts into smaller 128-bit shifts.
17044 if (VT.is256BitVector()) {
17045 unsigned NumElems = VT.getVectorNumElements();
17046 MVT EltVT = VT.getVectorElementType();
17047 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17049 // Extract the two vectors
17050 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17051 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17053 // Recreate the shift amount vectors
17054 SDValue Amt1, Amt2;
17055 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17056 // Constant shift amount
17057 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
17058 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
17059 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
17061 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17062 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17064 // Variable shift amount
17065 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17066 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17069 // Issue new vector shifts for the smaller types
17070 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17071 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17073 // Concatenate the result back
17074 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17080 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17081 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17082 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17083 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17084 // has only one use.
17085 SDNode *N = Op.getNode();
17086 SDValue LHS = N->getOperand(0);
17087 SDValue RHS = N->getOperand(1);
17088 unsigned BaseOp = 0;
17091 switch (Op.getOpcode()) {
17092 default: llvm_unreachable("Unknown ovf instruction!");
17094 // A subtract of one will be selected as a INC. Note that INC doesn't
17095 // set CF, so we can't do this for UADDO.
17096 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17098 BaseOp = X86ISD::INC;
17099 Cond = X86::COND_O;
17102 BaseOp = X86ISD::ADD;
17103 Cond = X86::COND_O;
17106 BaseOp = X86ISD::ADD;
17107 Cond = X86::COND_B;
17110 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17111 // set CF, so we can't do this for USUBO.
17112 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17114 BaseOp = X86ISD::DEC;
17115 Cond = X86::COND_O;
17118 BaseOp = X86ISD::SUB;
17119 Cond = X86::COND_O;
17122 BaseOp = X86ISD::SUB;
17123 Cond = X86::COND_B;
17126 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
17127 Cond = X86::COND_O;
17129 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17130 if (N->getValueType(0) == MVT::i8) {
17131 BaseOp = X86ISD::UMUL8;
17132 Cond = X86::COND_O;
17135 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17137 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17140 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17141 DAG.getConstant(X86::COND_O, DL, MVT::i32),
17142 SDValue(Sum.getNode(), 2));
17144 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17148 // Also sets EFLAGS.
17149 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17150 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17153 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17154 DAG.getConstant(Cond, DL, MVT::i32),
17155 SDValue(Sum.getNode(), 1));
17157 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17160 /// Returns true if the operand type is exactly twice the native width, and
17161 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17162 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17163 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17164 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17165 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17168 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17169 else if (OpWidth == 128)
17170 return Subtarget->hasCmpxchg16b();
17175 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17176 return needsCmpXchgNb(SI->getValueOperand()->getType());
17179 // Note: this turns large loads into lock cmpxchg8b/16b.
17180 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17181 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17182 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17183 return needsCmpXchgNb(PTy->getElementType());
17186 TargetLoweringBase::AtomicRMWExpansionKind
17187 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17188 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17189 const Type *MemType = AI->getType();
17191 // If the operand is too big, we must see if cmpxchg8/16b is available
17192 // and default to library calls otherwise.
17193 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
17194 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
17195 : AtomicRMWExpansionKind::None;
17198 AtomicRMWInst::BinOp Op = AI->getOperation();
17201 llvm_unreachable("Unknown atomic operation");
17202 case AtomicRMWInst::Xchg:
17203 case AtomicRMWInst::Add:
17204 case AtomicRMWInst::Sub:
17205 // It's better to use xadd, xsub or xchg for these in all cases.
17206 return AtomicRMWExpansionKind::None;
17207 case AtomicRMWInst::Or:
17208 case AtomicRMWInst::And:
17209 case AtomicRMWInst::Xor:
17210 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17211 // prefix to a normal instruction for these operations.
17212 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
17213 : AtomicRMWExpansionKind::None;
17214 case AtomicRMWInst::Nand:
17215 case AtomicRMWInst::Max:
17216 case AtomicRMWInst::Min:
17217 case AtomicRMWInst::UMax:
17218 case AtomicRMWInst::UMin:
17219 // These always require a non-trivial set of data operations on x86. We must
17220 // use a cmpxchg loop.
17221 return AtomicRMWExpansionKind::CmpXChg;
17225 static bool hasMFENCE(const X86Subtarget& Subtarget) {
17226 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17227 // no-sse2). There isn't any reason to disable it if the target processor
17229 return Subtarget.hasSSE2() || Subtarget.is64Bit();
17233 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
17234 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17235 const Type *MemType = AI->getType();
17236 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
17237 // there is no benefit in turning such RMWs into loads, and it is actually
17238 // harmful as it introduces a mfence.
17239 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17242 auto Builder = IRBuilder<>(AI);
17243 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
17244 auto SynchScope = AI->getSynchScope();
17245 // We must restrict the ordering to avoid generating loads with Release or
17246 // ReleaseAcquire orderings.
17247 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
17248 auto Ptr = AI->getPointerOperand();
17250 // Before the load we need a fence. Here is an example lifted from
17251 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
17254 // x.store(1, relaxed);
17255 // r1 = y.fetch_add(0, release);
17257 // y.fetch_add(42, acquire);
17258 // r2 = x.load(relaxed);
17259 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
17260 // lowered to just a load without a fence. A mfence flushes the store buffer,
17261 // making the optimization clearly correct.
17262 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
17263 // otherwise, we might be able to be more agressive on relaxed idempotent
17264 // rmw. In practice, they do not look useful, so we don't try to be
17265 // especially clever.
17266 if (SynchScope == SingleThread)
17267 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
17268 // the IR level, so we must wrap it in an intrinsic.
17271 if (!hasMFENCE(*Subtarget))
17272 // FIXME: it might make sense to use a locked operation here but on a
17273 // different cache-line to prevent cache-line bouncing. In practice it
17274 // is probably a small win, and x86 processors without mfence are rare
17275 // enough that we do not bother.
17279 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
17280 Builder.CreateCall(MFence, {});
17282 // Finally we can emit the atomic load.
17283 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
17284 AI->getType()->getPrimitiveSizeInBits());
17285 Loaded->setAtomic(Order, SynchScope);
17286 AI->replaceAllUsesWith(Loaded);
17287 AI->eraseFromParent();
17291 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17292 SelectionDAG &DAG) {
17294 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17295 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17296 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17297 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17299 // The only fence that needs an instruction is a sequentially-consistent
17300 // cross-thread fence.
17301 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17302 if (hasMFENCE(*Subtarget))
17303 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17305 SDValue Chain = Op.getOperand(0);
17306 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
17308 DAG.getRegister(X86::ESP, MVT::i32), // Base
17309 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
17310 DAG.getRegister(0, MVT::i32), // Index
17311 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
17312 DAG.getRegister(0, MVT::i32), // Segment.
17316 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17317 return SDValue(Res, 0);
17320 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17321 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17324 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17325 SelectionDAG &DAG) {
17326 MVT T = Op.getSimpleValueType();
17330 switch(T.SimpleTy) {
17331 default: llvm_unreachable("Invalid value type!");
17332 case MVT::i8: Reg = X86::AL; size = 1; break;
17333 case MVT::i16: Reg = X86::AX; size = 2; break;
17334 case MVT::i32: Reg = X86::EAX; size = 4; break;
17336 assert(Subtarget->is64Bit() && "Node not type legal!");
17337 Reg = X86::RAX; size = 8;
17340 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17341 Op.getOperand(2), SDValue());
17342 SDValue Ops[] = { cpIn.getValue(0),
17345 DAG.getTargetConstant(size, DL, MVT::i8),
17346 cpIn.getValue(1) };
17347 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17348 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17349 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17353 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17354 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17355 MVT::i32, cpOut.getValue(2));
17356 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17357 DAG.getConstant(X86::COND_E, DL, MVT::i8),
17360 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17361 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17362 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17366 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17367 SelectionDAG &DAG) {
17368 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17369 MVT DstVT = Op.getSimpleValueType();
17371 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17372 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17373 if (DstVT != MVT::f64)
17374 // This conversion needs to be expanded.
17377 SDValue InVec = Op->getOperand(0);
17379 unsigned NumElts = SrcVT.getVectorNumElements();
17380 EVT SVT = SrcVT.getVectorElementType();
17382 // Widen the vector in input in the case of MVT::v2i32.
17383 // Example: from MVT::v2i32 to MVT::v4i32.
17384 SmallVector<SDValue, 16> Elts;
17385 for (unsigned i = 0, e = NumElts; i != e; ++i)
17386 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17387 DAG.getIntPtrConstant(i, dl)));
17389 // Explicitly mark the extra elements as Undef.
17390 Elts.append(NumElts, DAG.getUNDEF(SVT));
17392 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17393 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17394 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
17395 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17396 DAG.getIntPtrConstant(0, dl));
17399 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17400 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17401 assert((DstVT == MVT::i64 ||
17402 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17403 "Unexpected custom BITCAST");
17404 // i64 <=> MMX conversions are Legal.
17405 if (SrcVT==MVT::i64 && DstVT.isVector())
17407 if (DstVT==MVT::i64 && SrcVT.isVector())
17409 // MMX <=> MMX conversions are Legal.
17410 if (SrcVT.isVector() && DstVT.isVector())
17412 // All other conversions need to be expanded.
17416 /// Compute the horizontal sum of bytes in V for the elements of VT.
17418 /// Requires V to be a byte vector and VT to be an integer vector type with
17419 /// wider elements than V's type. The width of the elements of VT determines
17420 /// how many bytes of V are summed horizontally to produce each element of the
17422 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
17423 const X86Subtarget *Subtarget,
17424 SelectionDAG &DAG) {
17426 MVT ByteVecVT = V.getSimpleValueType();
17427 MVT EltVT = VT.getVectorElementType();
17428 int NumElts = VT.getVectorNumElements();
17429 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
17430 "Expected value to have byte element type.");
17431 assert(EltVT != MVT::i8 &&
17432 "Horizontal byte sum only makes sense for wider elements!");
17433 unsigned VecSize = VT.getSizeInBits();
17434 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
17436 // PSADBW instruction horizontally add all bytes and leave the result in i64
17437 // chunks, thus directly computes the pop count for v2i64 and v4i64.
17438 if (EltVT == MVT::i64) {
17439 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17440 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
17441 return DAG.getBitcast(VT, V);
17444 if (EltVT == MVT::i32) {
17445 // We unpack the low half and high half into i32s interleaved with zeros so
17446 // that we can use PSADBW to horizontally sum them. The most useful part of
17447 // this is that it lines up the results of two PSADBW instructions to be
17448 // two v2i64 vectors which concatenated are the 4 population counts. We can
17449 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
17450 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
17451 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
17452 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
17454 // Do the horizontal sums into two v2i64s.
17455 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17456 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17457 DAG.getBitcast(ByteVecVT, Low), Zeros);
17458 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17459 DAG.getBitcast(ByteVecVT, High), Zeros);
17461 // Merge them together.
17462 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
17463 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
17464 DAG.getBitcast(ShortVecVT, Low),
17465 DAG.getBitcast(ShortVecVT, High));
17467 return DAG.getBitcast(VT, V);
17470 // The only element type left is i16.
17471 assert(EltVT == MVT::i16 && "Unknown how to handle type");
17473 // To obtain pop count for each i16 element starting from the pop count for
17474 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
17475 // right by 8. It is important to shift as i16s as i8 vector shift isn't
17476 // directly supported.
17477 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
17478 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
17479 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
17480 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
17481 DAG.getBitcast(ByteVecVT, V));
17482 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
17485 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
17486 const X86Subtarget *Subtarget,
17487 SelectionDAG &DAG) {
17488 MVT VT = Op.getSimpleValueType();
17489 MVT EltVT = VT.getVectorElementType();
17490 unsigned VecSize = VT.getSizeInBits();
17492 // Implement a lookup table in register by using an algorithm based on:
17493 // http://wm.ite.pl/articles/sse-popcount.html
17495 // The general idea is that every lower byte nibble in the input vector is an
17496 // index into a in-register pre-computed pop count table. We then split up the
17497 // input vector in two new ones: (1) a vector with only the shifted-right
17498 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
17499 // masked out higher ones) for each byte. PSHUB is used separately with both
17500 // to index the in-register table. Next, both are added and the result is a
17501 // i8 vector where each element contains the pop count for input byte.
17503 // To obtain the pop count for elements != i8, we follow up with the same
17504 // approach and use additional tricks as described below.
17506 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
17507 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
17508 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
17509 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
17511 int NumByteElts = VecSize / 8;
17512 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
17513 SDValue In = DAG.getBitcast(ByteVecVT, Op);
17514 SmallVector<SDValue, 16> LUTVec;
17515 for (int i = 0; i < NumByteElts; ++i)
17516 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
17517 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
17518 SmallVector<SDValue, 16> Mask0F(NumByteElts,
17519 DAG.getConstant(0x0F, DL, MVT::i8));
17520 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
17523 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
17524 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
17525 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
17528 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
17530 // The input vector is used as the shuffle mask that index elements into the
17531 // LUT. After counting low and high nibbles, add the vector to obtain the
17532 // final pop count per i8 element.
17533 SDValue HighPopCnt =
17534 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
17535 SDValue LowPopCnt =
17536 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
17537 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
17539 if (EltVT == MVT::i8)
17542 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
17545 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
17546 const X86Subtarget *Subtarget,
17547 SelectionDAG &DAG) {
17548 MVT VT = Op.getSimpleValueType();
17549 assert(VT.is128BitVector() &&
17550 "Only 128-bit vector bitmath lowering supported.");
17552 int VecSize = VT.getSizeInBits();
17553 MVT EltVT = VT.getVectorElementType();
17554 int Len = EltVT.getSizeInBits();
17556 // This is the vectorized version of the "best" algorithm from
17557 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
17558 // with a minor tweak to use a series of adds + shifts instead of vector
17559 // multiplications. Implemented for all integer vector types. We only use
17560 // this when we don't have SSSE3 which allows a LUT-based lowering that is
17561 // much faster, even faster than using native popcnt instructions.
17563 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
17564 MVT VT = V.getSimpleValueType();
17565 SmallVector<SDValue, 32> Shifters(
17566 VT.getVectorNumElements(),
17567 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
17568 return DAG.getNode(OpCode, DL, VT, V,
17569 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
17571 auto GetMask = [&](SDValue V, APInt Mask) {
17572 MVT VT = V.getSimpleValueType();
17573 SmallVector<SDValue, 32> Masks(
17574 VT.getVectorNumElements(),
17575 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
17576 return DAG.getNode(ISD::AND, DL, VT, V,
17577 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
17580 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
17581 // x86, so set the SRL type to have elements at least i16 wide. This is
17582 // correct because all of our SRLs are followed immediately by a mask anyways
17583 // that handles any bits that sneak into the high bits of the byte elements.
17584 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
17588 // v = v - ((v >> 1) & 0x55555555...)
17590 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
17591 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
17592 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
17594 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
17595 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
17596 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
17597 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
17598 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
17600 // v = (v + (v >> 4)) & 0x0F0F0F0F...
17601 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
17602 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
17603 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
17605 // At this point, V contains the byte-wise population count, and we are
17606 // merely doing a horizontal sum if necessary to get the wider element
17608 if (EltVT == MVT::i8)
17611 return LowerHorizontalByteSum(
17612 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
17616 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17617 SelectionDAG &DAG) {
17618 MVT VT = Op.getSimpleValueType();
17619 // FIXME: Need to add AVX-512 support here!
17620 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17621 "Unknown CTPOP type to handle");
17622 SDLoc DL(Op.getNode());
17623 SDValue Op0 = Op.getOperand(0);
17625 if (!Subtarget->hasSSSE3()) {
17626 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
17627 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
17628 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
17631 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
17632 unsigned NumElems = VT.getVectorNumElements();
17634 // Extract each 128-bit vector, compute pop count and concat the result.
17635 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
17636 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
17638 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
17639 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
17640 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
17643 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
17646 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17647 SelectionDAG &DAG) {
17648 assert(Op.getValueType().isVector() &&
17649 "We only do custom lowering for vector population count.");
17650 return LowerVectorCTPOP(Op, Subtarget, DAG);
17653 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17654 SDNode *Node = Op.getNode();
17656 EVT T = Node->getValueType(0);
17657 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17658 DAG.getConstant(0, dl, T), Node->getOperand(2));
17659 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17660 cast<AtomicSDNode>(Node)->getMemoryVT(),
17661 Node->getOperand(0),
17662 Node->getOperand(1), negOp,
17663 cast<AtomicSDNode>(Node)->getMemOperand(),
17664 cast<AtomicSDNode>(Node)->getOrdering(),
17665 cast<AtomicSDNode>(Node)->getSynchScope());
17668 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17669 SDNode *Node = Op.getNode();
17671 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17673 // Convert seq_cst store -> xchg
17674 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17675 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17676 // (The only way to get a 16-byte store is cmpxchg16b)
17677 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17678 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17679 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17680 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17681 cast<AtomicSDNode>(Node)->getMemoryVT(),
17682 Node->getOperand(0),
17683 Node->getOperand(1), Node->getOperand(2),
17684 cast<AtomicSDNode>(Node)->getMemOperand(),
17685 cast<AtomicSDNode>(Node)->getOrdering(),
17686 cast<AtomicSDNode>(Node)->getSynchScope());
17687 return Swap.getValue(1);
17689 // Other atomic stores have a simple pattern.
17693 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17694 EVT VT = Op.getNode()->getSimpleValueType(0);
17696 // Let legalize expand this if it isn't a legal type yet.
17697 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17700 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17703 bool ExtraOp = false;
17704 switch (Op.getOpcode()) {
17705 default: llvm_unreachable("Invalid code");
17706 case ISD::ADDC: Opc = X86ISD::ADD; break;
17707 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17708 case ISD::SUBC: Opc = X86ISD::SUB; break;
17709 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17713 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17715 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17716 Op.getOperand(1), Op.getOperand(2));
17719 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17720 SelectionDAG &DAG) {
17721 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17723 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17724 // which returns the values as { float, float } (in XMM0) or
17725 // { double, double } (which is returned in XMM0, XMM1).
17727 SDValue Arg = Op.getOperand(0);
17728 EVT ArgVT = Arg.getValueType();
17729 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17731 TargetLowering::ArgListTy Args;
17732 TargetLowering::ArgListEntry Entry;
17736 Entry.isSExt = false;
17737 Entry.isZExt = false;
17738 Args.push_back(Entry);
17740 bool isF64 = ArgVT == MVT::f64;
17741 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17742 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17743 // the results are returned via SRet in memory.
17744 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17745 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17746 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17748 Type *RetTy = isF64
17749 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
17750 : (Type*)VectorType::get(ArgTy, 4);
17752 TargetLowering::CallLoweringInfo CLI(DAG);
17753 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17754 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17756 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17759 // Returned in xmm0 and xmm1.
17760 return CallResult.first;
17762 // Returned in bits 0:31 and 32:64 xmm0.
17763 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17764 CallResult.first, DAG.getIntPtrConstant(0, dl));
17765 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17766 CallResult.first, DAG.getIntPtrConstant(1, dl));
17767 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17768 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17771 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
17772 SelectionDAG &DAG) {
17773 assert(Subtarget->hasAVX512() &&
17774 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17776 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
17777 EVT VT = N->getValue().getValueType();
17778 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
17781 // X86 scatter kills mask register, so its type should be added to
17782 // the list of return values
17783 if (N->getNumValues() == 1) {
17784 SDValue Index = N->getIndex();
17785 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
17786 !Index.getValueType().is512BitVector())
17787 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
17789 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
17790 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
17791 N->getOperand(3), Index };
17793 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
17794 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
17795 return SDValue(NewScatter.getNode(), 0);
17800 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
17801 SelectionDAG &DAG) {
17802 assert(Subtarget->hasAVX512() &&
17803 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17805 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
17806 EVT VT = Op.getValueType();
17807 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
17810 SDValue Index = N->getIndex();
17811 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
17812 !Index.getValueType().is512BitVector()) {
17813 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
17814 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
17815 N->getOperand(3), Index };
17816 DAG.UpdateNodeOperands(N, Ops);
17821 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
17822 SelectionDAG &DAG) const {
17823 // TODO: Eventually, the lowering of these nodes should be informed by or
17824 // deferred to the GC strategy for the function in which they appear. For
17825 // now, however, they must be lowered to something. Since they are logically
17826 // no-ops in the case of a null GC strategy (or a GC strategy which does not
17827 // require special handling for these nodes), lower them as literal NOOPs for
17829 SmallVector<SDValue, 2> Ops;
17831 Ops.push_back(Op.getOperand(0));
17832 if (Op->getGluedNode())
17833 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
17836 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
17837 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
17842 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
17843 SelectionDAG &DAG) const {
17844 // TODO: Eventually, the lowering of these nodes should be informed by or
17845 // deferred to the GC strategy for the function in which they appear. For
17846 // now, however, they must be lowered to something. Since they are logically
17847 // no-ops in the case of a null GC strategy (or a GC strategy which does not
17848 // require special handling for these nodes), lower them as literal NOOPs for
17850 SmallVector<SDValue, 2> Ops;
17852 Ops.push_back(Op.getOperand(0));
17853 if (Op->getGluedNode())
17854 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
17857 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
17858 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
17863 /// LowerOperation - Provide custom lowering hooks for some operations.
17865 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17866 switch (Op.getOpcode()) {
17867 default: llvm_unreachable("Should not custom lower this!");
17868 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17869 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17870 return LowerCMP_SWAP(Op, Subtarget, DAG);
17871 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
17872 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17873 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17874 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17875 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
17876 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
17877 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17878 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17879 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17880 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17881 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17882 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17883 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17884 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17885 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17886 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17887 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17888 case ISD::SHL_PARTS:
17889 case ISD::SRA_PARTS:
17890 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17891 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17892 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17893 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17894 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17895 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17896 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17897 case ISD::SIGN_EXTEND_VECTOR_INREG:
17898 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
17899 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17900 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17901 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17902 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17904 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17905 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17906 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17907 case ISD::SETCC: return LowerSETCC(Op, DAG);
17908 case ISD::SELECT: return LowerSELECT(Op, DAG);
17909 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17910 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17911 case ISD::VASTART: return LowerVASTART(Op, DAG);
17912 case ISD::VAARG: return LowerVAARG(Op, DAG);
17913 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17914 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
17915 case ISD::INTRINSIC_VOID:
17916 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17917 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17918 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17919 case ISD::FRAME_TO_ARGS_OFFSET:
17920 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17921 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17922 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17923 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17924 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17925 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17926 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17927 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17928 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17929 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17930 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17931 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17932 case ISD::UMUL_LOHI:
17933 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17936 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17942 case ISD::UMULO: return LowerXALUO(Op, DAG);
17943 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17944 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17948 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17949 case ISD::ADD: return LowerADD(Op, DAG);
17950 case ISD::SUB: return LowerSUB(Op, DAG);
17951 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17952 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
17953 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
17954 case ISD::GC_TRANSITION_START:
17955 return LowerGC_TRANSITION_START(Op, DAG);
17956 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
17960 /// ReplaceNodeResults - Replace a node with an illegal result type
17961 /// with a new node built out of custom code.
17962 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17963 SmallVectorImpl<SDValue>&Results,
17964 SelectionDAG &DAG) const {
17966 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17967 switch (N->getOpcode()) {
17969 llvm_unreachable("Do not know how to custom type legalize this operation!");
17970 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
17971 case X86ISD::FMINC:
17973 case X86ISD::FMAXC:
17974 case X86ISD::FMAX: {
17975 EVT VT = N->getValueType(0);
17976 if (VT != MVT::v2f32)
17977 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
17978 SDValue UNDEF = DAG.getUNDEF(VT);
17979 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17980 N->getOperand(0), UNDEF);
17981 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17982 N->getOperand(1), UNDEF);
17983 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
17986 case ISD::SIGN_EXTEND_INREG:
17991 // We don't want to expand or promote these.
17998 case ISD::UDIVREM: {
17999 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18000 Results.push_back(V);
18003 case ISD::FP_TO_SINT:
18004 // FP_TO_INT*_IN_MEM is not legal for f16 inputs. Do not convert
18005 // (FP_TO_SINT (load f16)) to FP_TO_INT*.
18006 if (N->getOperand(0).getValueType() == MVT::f16)
18009 case ISD::FP_TO_UINT: {
18010 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18012 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18015 std::pair<SDValue,SDValue> Vals =
18016 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18017 SDValue FIST = Vals.first, StackSlot = Vals.second;
18018 if (FIST.getNode()) {
18019 EVT VT = N->getValueType(0);
18020 // Return a load from the stack slot.
18021 if (StackSlot.getNode())
18022 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18023 MachinePointerInfo(),
18024 false, false, false, 0));
18026 Results.push_back(FIST);
18030 case ISD::UINT_TO_FP: {
18031 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18032 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18033 N->getValueType(0) != MVT::v2f32)
18035 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18037 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
18039 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18040 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18041 DAG.getBitcast(MVT::v2i64, VBias));
18042 Or = DAG.getBitcast(MVT::v2f64, Or);
18043 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18044 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18047 case ISD::FP_ROUND: {
18048 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18050 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18051 Results.push_back(V);
18054 case ISD::FP_EXTEND: {
18055 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
18056 // No other ValueType for FP_EXTEND should reach this point.
18057 assert(N->getValueType(0) == MVT::v2f32 &&
18058 "Do not know how to legalize this Node");
18061 case ISD::INTRINSIC_W_CHAIN: {
18062 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18064 default : llvm_unreachable("Do not know how to custom type "
18065 "legalize this intrinsic operation!");
18066 case Intrinsic::x86_rdtsc:
18067 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18069 case Intrinsic::x86_rdtscp:
18070 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18072 case Intrinsic::x86_rdpmc:
18073 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18076 case ISD::READCYCLECOUNTER: {
18077 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18080 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18081 EVT T = N->getValueType(0);
18082 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18083 bool Regs64bit = T == MVT::i128;
18084 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18085 SDValue cpInL, cpInH;
18086 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18087 DAG.getConstant(0, dl, HalfT));
18088 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18089 DAG.getConstant(1, dl, HalfT));
18090 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18091 Regs64bit ? X86::RAX : X86::EAX,
18093 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18094 Regs64bit ? X86::RDX : X86::EDX,
18095 cpInH, cpInL.getValue(1));
18096 SDValue swapInL, swapInH;
18097 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18098 DAG.getConstant(0, dl, HalfT));
18099 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18100 DAG.getConstant(1, dl, HalfT));
18101 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18102 Regs64bit ? X86::RBX : X86::EBX,
18103 swapInL, cpInH.getValue(1));
18104 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18105 Regs64bit ? X86::RCX : X86::ECX,
18106 swapInH, swapInL.getValue(1));
18107 SDValue Ops[] = { swapInH.getValue(0),
18109 swapInH.getValue(1) };
18110 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18111 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18112 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18113 X86ISD::LCMPXCHG8_DAG;
18114 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18115 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18116 Regs64bit ? X86::RAX : X86::EAX,
18117 HalfT, Result.getValue(1));
18118 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18119 Regs64bit ? X86::RDX : X86::EDX,
18120 HalfT, cpOutL.getValue(2));
18121 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18123 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18124 MVT::i32, cpOutH.getValue(2));
18126 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18127 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
18128 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18130 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18131 Results.push_back(Success);
18132 Results.push_back(EFLAGS.getValue(1));
18135 case ISD::ATOMIC_SWAP:
18136 case ISD::ATOMIC_LOAD_ADD:
18137 case ISD::ATOMIC_LOAD_SUB:
18138 case ISD::ATOMIC_LOAD_AND:
18139 case ISD::ATOMIC_LOAD_OR:
18140 case ISD::ATOMIC_LOAD_XOR:
18141 case ISD::ATOMIC_LOAD_NAND:
18142 case ISD::ATOMIC_LOAD_MIN:
18143 case ISD::ATOMIC_LOAD_MAX:
18144 case ISD::ATOMIC_LOAD_UMIN:
18145 case ISD::ATOMIC_LOAD_UMAX:
18146 case ISD::ATOMIC_LOAD: {
18147 // Delegate to generic TypeLegalization. Situations we can really handle
18148 // should have already been dealt with by AtomicExpandPass.cpp.
18151 case ISD::BITCAST: {
18152 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18153 EVT DstVT = N->getValueType(0);
18154 EVT SrcVT = N->getOperand(0)->getValueType(0);
18156 if (SrcVT != MVT::f64 ||
18157 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18160 unsigned NumElts = DstVT.getVectorNumElements();
18161 EVT SVT = DstVT.getVectorElementType();
18162 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18163 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18164 MVT::v2f64, N->getOperand(0));
18165 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
18167 if (ExperimentalVectorWideningLegalization) {
18168 // If we are legalizing vectors by widening, we already have the desired
18169 // legal vector type, just return it.
18170 Results.push_back(ToVecInt);
18174 SmallVector<SDValue, 8> Elts;
18175 for (unsigned i = 0, e = NumElts; i != e; ++i)
18176 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18177 ToVecInt, DAG.getIntPtrConstant(i, dl)));
18179 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18184 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18185 switch ((X86ISD::NodeType)Opcode) {
18186 case X86ISD::FIRST_NUMBER: break;
18187 case X86ISD::BSF: return "X86ISD::BSF";
18188 case X86ISD::BSR: return "X86ISD::BSR";
18189 case X86ISD::SHLD: return "X86ISD::SHLD";
18190 case X86ISD::SHRD: return "X86ISD::SHRD";
18191 case X86ISD::FAND: return "X86ISD::FAND";
18192 case X86ISD::FANDN: return "X86ISD::FANDN";
18193 case X86ISD::FOR: return "X86ISD::FOR";
18194 case X86ISD::FXOR: return "X86ISD::FXOR";
18195 case X86ISD::FILD: return "X86ISD::FILD";
18196 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18197 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18198 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18199 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18200 case X86ISD::FLD: return "X86ISD::FLD";
18201 case X86ISD::FST: return "X86ISD::FST";
18202 case X86ISD::CALL: return "X86ISD::CALL";
18203 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18204 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18205 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18206 case X86ISD::BT: return "X86ISD::BT";
18207 case X86ISD::CMP: return "X86ISD::CMP";
18208 case X86ISD::COMI: return "X86ISD::COMI";
18209 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18210 case X86ISD::CMPM: return "X86ISD::CMPM";
18211 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18212 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
18213 case X86ISD::SETCC: return "X86ISD::SETCC";
18214 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18215 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18216 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
18217 case X86ISD::CMOV: return "X86ISD::CMOV";
18218 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18219 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18220 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18221 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18222 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18223 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18224 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18225 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
18226 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
18227 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
18228 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18229 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18230 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18231 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18232 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18233 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
18234 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18235 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18236 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18237 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18238 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
18239 case X86ISD::ADDUS: return "X86ISD::ADDUS";
18240 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18241 case X86ISD::HADD: return "X86ISD::HADD";
18242 case X86ISD::HSUB: return "X86ISD::HSUB";
18243 case X86ISD::FHADD: return "X86ISD::FHADD";
18244 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18245 case X86ISD::UMAX: return "X86ISD::UMAX";
18246 case X86ISD::UMIN: return "X86ISD::UMIN";
18247 case X86ISD::SMAX: return "X86ISD::SMAX";
18248 case X86ISD::SMIN: return "X86ISD::SMIN";
18249 case X86ISD::FMAX: return "X86ISD::FMAX";
18250 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
18251 case X86ISD::FMIN: return "X86ISD::FMIN";
18252 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
18253 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18254 case X86ISD::FMINC: return "X86ISD::FMINC";
18255 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18256 case X86ISD::FRCP: return "X86ISD::FRCP";
18257 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18258 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18259 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18260 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18261 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18262 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18263 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18264 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18265 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18266 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18267 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18268 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18269 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18270 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18271 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18272 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18273 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18274 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18275 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18276 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18277 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18278 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18279 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18280 case X86ISD::VSHL: return "X86ISD::VSHL";
18281 case X86ISD::VSRL: return "X86ISD::VSRL";
18282 case X86ISD::VSRA: return "X86ISD::VSRA";
18283 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18284 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18285 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18286 case X86ISD::CMPP: return "X86ISD::CMPP";
18287 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18288 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18289 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18290 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18291 case X86ISD::ADD: return "X86ISD::ADD";
18292 case X86ISD::SUB: return "X86ISD::SUB";
18293 case X86ISD::ADC: return "X86ISD::ADC";
18294 case X86ISD::SBB: return "X86ISD::SBB";
18295 case X86ISD::SMUL: return "X86ISD::SMUL";
18296 case X86ISD::UMUL: return "X86ISD::UMUL";
18297 case X86ISD::SMUL8: return "X86ISD::SMUL8";
18298 case X86ISD::UMUL8: return "X86ISD::UMUL8";
18299 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
18300 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
18301 case X86ISD::INC: return "X86ISD::INC";
18302 case X86ISD::DEC: return "X86ISD::DEC";
18303 case X86ISD::OR: return "X86ISD::OR";
18304 case X86ISD::XOR: return "X86ISD::XOR";
18305 case X86ISD::AND: return "X86ISD::AND";
18306 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18307 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18308 case X86ISD::PTEST: return "X86ISD::PTEST";
18309 case X86ISD::TESTP: return "X86ISD::TESTP";
18310 case X86ISD::TESTM: return "X86ISD::TESTM";
18311 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18312 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18313 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18314 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18315 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18316 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18317 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18318 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18319 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18320 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18321 case X86ISD::SHUF128: return "X86ISD::SHUF128";
18322 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18323 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18324 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18325 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18326 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18327 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18328 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18329 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18330 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18331 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18332 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18333 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18334 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18335 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
18336 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18337 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
18338 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18339 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18340 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18341 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18342 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18343 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18344 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
18345 case X86ISD::VRANGE: return "X86ISD::VRANGE";
18346 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18347 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18348 case X86ISD::PSADBW: return "X86ISD::PSADBW";
18349 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18350 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18351 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18352 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18353 case X86ISD::MFENCE: return "X86ISD::MFENCE";
18354 case X86ISD::SFENCE: return "X86ISD::SFENCE";
18355 case X86ISD::LFENCE: return "X86ISD::LFENCE";
18356 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18357 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18358 case X86ISD::SAHF: return "X86ISD::SAHF";
18359 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18360 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18361 case X86ISD::FMADD: return "X86ISD::FMADD";
18362 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18363 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18364 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18365 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18366 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18367 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
18368 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
18369 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
18370 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
18371 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
18372 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
18373 case X86ISD::RNDSCALE: return "X86ISD::RNDSCALE";
18374 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18375 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18376 case X86ISD::XTEST: return "X86ISD::XTEST";
18377 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
18378 case X86ISD::EXPAND: return "X86ISD::EXPAND";
18379 case X86ISD::SELECT: return "X86ISD::SELECT";
18380 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
18381 case X86ISD::RCP28: return "X86ISD::RCP28";
18382 case X86ISD::EXP2: return "X86ISD::EXP2";
18383 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
18384 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
18385 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
18386 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
18387 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
18388 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
18389 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
18390 case X86ISD::ADDS: return "X86ISD::ADDS";
18391 case X86ISD::SUBS: return "X86ISD::SUBS";
18396 // isLegalAddressingMode - Return true if the addressing mode represented
18397 // by AM is legal for this target, for a load/store of the specified type.
18398 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18400 unsigned AS) const {
18401 // X86 supports extremely general addressing modes.
18402 CodeModel::Model M = getTargetMachine().getCodeModel();
18403 Reloc::Model R = getTargetMachine().getRelocationModel();
18405 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18406 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18411 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18413 // If a reference to this global requires an extra load, we can't fold it.
18414 if (isGlobalStubReference(GVFlags))
18417 // If BaseGV requires a register for the PIC base, we cannot also have a
18418 // BaseReg specified.
18419 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18422 // If lower 4G is not available, then we must use rip-relative addressing.
18423 if ((M != CodeModel::Small || R != Reloc::Static) &&
18424 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18428 switch (AM.Scale) {
18434 // These scales always work.
18439 // These scales are formed with basereg+scalereg. Only accept if there is
18444 default: // Other stuff never works.
18451 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18452 unsigned Bits = Ty->getScalarSizeInBits();
18454 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18455 // particularly cheaper than those without.
18459 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18460 // variable shifts just as cheap as scalar ones.
18461 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18464 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18465 // fully general vector.
18469 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18470 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18472 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18473 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18474 return NumBits1 > NumBits2;
18477 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18478 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18481 if (!isTypeLegal(EVT::getEVT(Ty1)))
18484 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18486 // Assuming the caller doesn't have a zeroext or signext return parameter,
18487 // truncation all the way down to i1 is valid.
18491 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18492 return isInt<32>(Imm);
18495 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18496 // Can also use sub to handle negated immediates.
18497 return isInt<32>(Imm);
18500 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18501 if (!VT1.isInteger() || !VT2.isInteger())
18503 unsigned NumBits1 = VT1.getSizeInBits();
18504 unsigned NumBits2 = VT2.getSizeInBits();
18505 return NumBits1 > NumBits2;
18508 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18509 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18510 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18513 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18514 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18515 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18518 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18519 EVT VT1 = Val.getValueType();
18520 if (isZExtFree(VT1, VT2))
18523 if (Val.getOpcode() != ISD::LOAD)
18526 if (!VT1.isSimple() || !VT1.isInteger() ||
18527 !VT2.isSimple() || !VT2.isInteger())
18530 switch (VT1.getSimpleVT().SimpleTy) {
18535 // X86 has 8, 16, and 32-bit zero-extending loads.
18542 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
18545 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18546 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18549 VT = VT.getScalarType();
18551 if (!VT.isSimple())
18554 switch (VT.getSimpleVT().SimpleTy) {
18565 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18566 // i16 instructions are longer (0x66 prefix) and potentially slower.
18567 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18570 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18571 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18572 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18573 /// are assumed to be legal.
18575 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18577 if (!VT.isSimple())
18580 // Not for i1 vectors
18581 if (VT.getScalarType() == MVT::i1)
18584 // Very little shuffling can be done for 64-bit vectors right now.
18585 if (VT.getSizeInBits() == 64)
18588 // We only care that the types being shuffled are legal. The lowering can
18589 // handle any possible shuffle mask that results.
18590 return isTypeLegal(VT.getSimpleVT());
18594 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18596 // Just delegate to the generic legality, clear masks aren't special.
18597 return isShuffleMaskLegal(Mask, VT);
18600 //===----------------------------------------------------------------------===//
18601 // X86 Scheduler Hooks
18602 //===----------------------------------------------------------------------===//
18604 /// Utility function to emit xbegin specifying the start of an RTM region.
18605 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18606 const TargetInstrInfo *TII) {
18607 DebugLoc DL = MI->getDebugLoc();
18609 const BasicBlock *BB = MBB->getBasicBlock();
18610 MachineFunction::iterator I = MBB;
18613 // For the v = xbegin(), we generate
18624 MachineBasicBlock *thisMBB = MBB;
18625 MachineFunction *MF = MBB->getParent();
18626 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18627 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18628 MF->insert(I, mainMBB);
18629 MF->insert(I, sinkMBB);
18631 // Transfer the remainder of BB and its successor edges to sinkMBB.
18632 sinkMBB->splice(sinkMBB->begin(), MBB,
18633 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18634 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18638 // # fallthrough to mainMBB
18639 // # abortion to sinkMBB
18640 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18641 thisMBB->addSuccessor(mainMBB);
18642 thisMBB->addSuccessor(sinkMBB);
18646 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18647 mainMBB->addSuccessor(sinkMBB);
18650 // EAX is live into the sinkMBB
18651 sinkMBB->addLiveIn(X86::EAX);
18652 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18653 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18656 MI->eraseFromParent();
18660 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18661 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18662 // in the .td file.
18663 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18664 const TargetInstrInfo *TII) {
18666 switch (MI->getOpcode()) {
18667 default: llvm_unreachable("illegal opcode!");
18668 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18669 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18670 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18671 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18672 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18673 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18674 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18675 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18678 DebugLoc dl = MI->getDebugLoc();
18679 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18681 unsigned NumArgs = MI->getNumOperands();
18682 for (unsigned i = 1; i < NumArgs; ++i) {
18683 MachineOperand &Op = MI->getOperand(i);
18684 if (!(Op.isReg() && Op.isImplicit()))
18685 MIB.addOperand(Op);
18687 if (MI->hasOneMemOperand())
18688 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18690 BuildMI(*BB, MI, dl,
18691 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18692 .addReg(X86::XMM0);
18694 MI->eraseFromParent();
18698 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18699 // defs in an instruction pattern
18700 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18701 const TargetInstrInfo *TII) {
18703 switch (MI->getOpcode()) {
18704 default: llvm_unreachable("illegal opcode!");
18705 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18706 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18707 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18708 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18709 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18710 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18711 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18712 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18715 DebugLoc dl = MI->getDebugLoc();
18716 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18718 unsigned NumArgs = MI->getNumOperands(); // remove the results
18719 for (unsigned i = 1; i < NumArgs; ++i) {
18720 MachineOperand &Op = MI->getOperand(i);
18721 if (!(Op.isReg() && Op.isImplicit()))
18722 MIB.addOperand(Op);
18724 if (MI->hasOneMemOperand())
18725 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18727 BuildMI(*BB, MI, dl,
18728 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18731 MI->eraseFromParent();
18735 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18736 const X86Subtarget *Subtarget) {
18737 DebugLoc dl = MI->getDebugLoc();
18738 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18739 // Address into RAX/EAX, other two args into ECX, EDX.
18740 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18741 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18742 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18743 for (int i = 0; i < X86::AddrNumOperands; ++i)
18744 MIB.addOperand(MI->getOperand(i));
18746 unsigned ValOps = X86::AddrNumOperands;
18747 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18748 .addReg(MI->getOperand(ValOps).getReg());
18749 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18750 .addReg(MI->getOperand(ValOps+1).getReg());
18752 // The instruction doesn't actually take any operands though.
18753 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18755 MI->eraseFromParent(); // The pseudo is gone now.
18759 MachineBasicBlock *
18760 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
18761 MachineBasicBlock *MBB) const {
18762 // Emit va_arg instruction on X86-64.
18764 // Operands to this pseudo-instruction:
18765 // 0 ) Output : destination address (reg)
18766 // 1-5) Input : va_list address (addr, i64mem)
18767 // 6 ) ArgSize : Size (in bytes) of vararg type
18768 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18769 // 8 ) Align : Alignment of type
18770 // 9 ) EFLAGS (implicit-def)
18772 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18773 static_assert(X86::AddrNumOperands == 5,
18774 "VAARG_64 assumes 5 address operands");
18776 unsigned DestReg = MI->getOperand(0).getReg();
18777 MachineOperand &Base = MI->getOperand(1);
18778 MachineOperand &Scale = MI->getOperand(2);
18779 MachineOperand &Index = MI->getOperand(3);
18780 MachineOperand &Disp = MI->getOperand(4);
18781 MachineOperand &Segment = MI->getOperand(5);
18782 unsigned ArgSize = MI->getOperand(6).getImm();
18783 unsigned ArgMode = MI->getOperand(7).getImm();
18784 unsigned Align = MI->getOperand(8).getImm();
18786 // Memory Reference
18787 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18788 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18789 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18791 // Machine Information
18792 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18793 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18794 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18795 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18796 DebugLoc DL = MI->getDebugLoc();
18798 // struct va_list {
18801 // i64 overflow_area (address)
18802 // i64 reg_save_area (address)
18804 // sizeof(va_list) = 24
18805 // alignment(va_list) = 8
18807 unsigned TotalNumIntRegs = 6;
18808 unsigned TotalNumXMMRegs = 8;
18809 bool UseGPOffset = (ArgMode == 1);
18810 bool UseFPOffset = (ArgMode == 2);
18811 unsigned MaxOffset = TotalNumIntRegs * 8 +
18812 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18814 /* Align ArgSize to a multiple of 8 */
18815 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18816 bool NeedsAlign = (Align > 8);
18818 MachineBasicBlock *thisMBB = MBB;
18819 MachineBasicBlock *overflowMBB;
18820 MachineBasicBlock *offsetMBB;
18821 MachineBasicBlock *endMBB;
18823 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18824 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18825 unsigned OffsetReg = 0;
18827 if (!UseGPOffset && !UseFPOffset) {
18828 // If we only pull from the overflow region, we don't create a branch.
18829 // We don't need to alter control flow.
18830 OffsetDestReg = 0; // unused
18831 OverflowDestReg = DestReg;
18833 offsetMBB = nullptr;
18834 overflowMBB = thisMBB;
18837 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18838 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18839 // If not, pull from overflow_area. (branch to overflowMBB)
18844 // offsetMBB overflowMBB
18849 // Registers for the PHI in endMBB
18850 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18851 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18853 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18854 MachineFunction *MF = MBB->getParent();
18855 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18856 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18857 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18859 MachineFunction::iterator MBBIter = MBB;
18862 // Insert the new basic blocks
18863 MF->insert(MBBIter, offsetMBB);
18864 MF->insert(MBBIter, overflowMBB);
18865 MF->insert(MBBIter, endMBB);
18867 // Transfer the remainder of MBB and its successor edges to endMBB.
18868 endMBB->splice(endMBB->begin(), thisMBB,
18869 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18870 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18872 // Make offsetMBB and overflowMBB successors of thisMBB
18873 thisMBB->addSuccessor(offsetMBB);
18874 thisMBB->addSuccessor(overflowMBB);
18876 // endMBB is a successor of both offsetMBB and overflowMBB
18877 offsetMBB->addSuccessor(endMBB);
18878 overflowMBB->addSuccessor(endMBB);
18880 // Load the offset value into a register
18881 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18882 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18886 .addDisp(Disp, UseFPOffset ? 4 : 0)
18887 .addOperand(Segment)
18888 .setMemRefs(MMOBegin, MMOEnd);
18890 // Check if there is enough room left to pull this argument.
18891 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18893 .addImm(MaxOffset + 8 - ArgSizeA8);
18895 // Branch to "overflowMBB" if offset >= max
18896 // Fall through to "offsetMBB" otherwise
18897 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18898 .addMBB(overflowMBB);
18901 // In offsetMBB, emit code to use the reg_save_area.
18903 assert(OffsetReg != 0);
18905 // Read the reg_save_area address.
18906 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18907 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18912 .addOperand(Segment)
18913 .setMemRefs(MMOBegin, MMOEnd);
18915 // Zero-extend the offset
18916 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18917 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18920 .addImm(X86::sub_32bit);
18922 // Add the offset to the reg_save_area to get the final address.
18923 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18924 .addReg(OffsetReg64)
18925 .addReg(RegSaveReg);
18927 // Compute the offset for the next argument
18928 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18929 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18931 .addImm(UseFPOffset ? 16 : 8);
18933 // Store it back into the va_list.
18934 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18938 .addDisp(Disp, UseFPOffset ? 4 : 0)
18939 .addOperand(Segment)
18940 .addReg(NextOffsetReg)
18941 .setMemRefs(MMOBegin, MMOEnd);
18944 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
18949 // Emit code to use overflow area
18952 // Load the overflow_area address into a register.
18953 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18954 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18959 .addOperand(Segment)
18960 .setMemRefs(MMOBegin, MMOEnd);
18962 // If we need to align it, do so. Otherwise, just copy the address
18963 // to OverflowDestReg.
18965 // Align the overflow address
18966 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18967 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18969 // aligned_addr = (addr + (align-1)) & ~(align-1)
18970 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18971 .addReg(OverflowAddrReg)
18974 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18976 .addImm(~(uint64_t)(Align-1));
18978 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18979 .addReg(OverflowAddrReg);
18982 // Compute the next overflow address after this argument.
18983 // (the overflow address should be kept 8-byte aligned)
18984 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18985 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18986 .addReg(OverflowDestReg)
18987 .addImm(ArgSizeA8);
18989 // Store the new overflow address.
18990 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18995 .addOperand(Segment)
18996 .addReg(NextAddrReg)
18997 .setMemRefs(MMOBegin, MMOEnd);
18999 // If we branched, emit the PHI to the front of endMBB.
19001 BuildMI(*endMBB, endMBB->begin(), DL,
19002 TII->get(X86::PHI), DestReg)
19003 .addReg(OffsetDestReg).addMBB(offsetMBB)
19004 .addReg(OverflowDestReg).addMBB(overflowMBB);
19007 // Erase the pseudo instruction
19008 MI->eraseFromParent();
19013 MachineBasicBlock *
19014 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19016 MachineBasicBlock *MBB) const {
19017 // Emit code to save XMM registers to the stack. The ABI says that the
19018 // number of registers to save is given in %al, so it's theoretically
19019 // possible to do an indirect jump trick to avoid saving all of them,
19020 // however this code takes a simpler approach and just executes all
19021 // of the stores if %al is non-zero. It's less code, and it's probably
19022 // easier on the hardware branch predictor, and stores aren't all that
19023 // expensive anyway.
19025 // Create the new basic blocks. One block contains all the XMM stores,
19026 // and one block is the final destination regardless of whether any
19027 // stores were performed.
19028 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19029 MachineFunction *F = MBB->getParent();
19030 MachineFunction::iterator MBBIter = MBB;
19032 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19033 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19034 F->insert(MBBIter, XMMSaveMBB);
19035 F->insert(MBBIter, EndMBB);
19037 // Transfer the remainder of MBB and its successor edges to EndMBB.
19038 EndMBB->splice(EndMBB->begin(), MBB,
19039 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19040 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19042 // The original block will now fall through to the XMM save block.
19043 MBB->addSuccessor(XMMSaveMBB);
19044 // The XMMSaveMBB will fall through to the end block.
19045 XMMSaveMBB->addSuccessor(EndMBB);
19047 // Now add the instructions.
19048 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19049 DebugLoc DL = MI->getDebugLoc();
19051 unsigned CountReg = MI->getOperand(0).getReg();
19052 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19053 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19055 if (!Subtarget->isTargetWin64()) {
19056 // If %al is 0, branch around the XMM save block.
19057 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19058 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
19059 MBB->addSuccessor(EndMBB);
19062 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19063 // that was just emitted, but clearly shouldn't be "saved".
19064 assert((MI->getNumOperands() <= 3 ||
19065 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19066 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19067 && "Expected last argument to be EFLAGS");
19068 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19069 // In the XMM save block, save all the XMM argument registers.
19070 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19071 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19072 MachineMemOperand *MMO =
19073 F->getMachineMemOperand(
19074 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19075 MachineMemOperand::MOStore,
19076 /*Size=*/16, /*Align=*/16);
19077 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19078 .addFrameIndex(RegSaveFrameIndex)
19079 .addImm(/*Scale=*/1)
19080 .addReg(/*IndexReg=*/0)
19081 .addImm(/*Disp=*/Offset)
19082 .addReg(/*Segment=*/0)
19083 .addReg(MI->getOperand(i).getReg())
19084 .addMemOperand(MMO);
19087 MI->eraseFromParent(); // The pseudo instruction is gone now.
19092 // The EFLAGS operand of SelectItr might be missing a kill marker
19093 // because there were multiple uses of EFLAGS, and ISel didn't know
19094 // which to mark. Figure out whether SelectItr should have had a
19095 // kill marker, and set it if it should. Returns the correct kill
19097 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19098 MachineBasicBlock* BB,
19099 const TargetRegisterInfo* TRI) {
19100 // Scan forward through BB for a use/def of EFLAGS.
19101 MachineBasicBlock::iterator miI(std::next(SelectItr));
19102 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19103 const MachineInstr& mi = *miI;
19104 if (mi.readsRegister(X86::EFLAGS))
19106 if (mi.definesRegister(X86::EFLAGS))
19107 break; // Should have kill-flag - update below.
19110 // If we hit the end of the block, check whether EFLAGS is live into a
19112 if (miI == BB->end()) {
19113 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19114 sEnd = BB->succ_end();
19115 sItr != sEnd; ++sItr) {
19116 MachineBasicBlock* succ = *sItr;
19117 if (succ->isLiveIn(X86::EFLAGS))
19122 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19123 // out. SelectMI should have a kill flag on EFLAGS.
19124 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19128 MachineBasicBlock *
19129 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19130 MachineBasicBlock *BB) const {
19131 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19132 DebugLoc DL = MI->getDebugLoc();
19134 // To "insert" a SELECT_CC instruction, we actually have to insert the
19135 // diamond control-flow pattern. The incoming instruction knows the
19136 // destination vreg to set, the condition code register to branch on, the
19137 // true/false values to select between, and a branch opcode to use.
19138 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19139 MachineFunction::iterator It = BB;
19145 // cmpTY ccX, r1, r2
19147 // fallthrough --> copy0MBB
19148 MachineBasicBlock *thisMBB = BB;
19149 MachineFunction *F = BB->getParent();
19151 // We also lower double CMOVs:
19152 // (CMOV (CMOV F, T, cc1), T, cc2)
19153 // to two successives branches. For that, we look for another CMOV as the
19154 // following instruction.
19156 // Without this, we would add a PHI between the two jumps, which ends up
19157 // creating a few copies all around. For instance, for
19159 // (sitofp (zext (fcmp une)))
19161 // we would generate:
19163 // ucomiss %xmm1, %xmm0
19164 // movss <1.0f>, %xmm0
19165 // movaps %xmm0, %xmm1
19167 // xorps %xmm1, %xmm1
19170 // movaps %xmm1, %xmm0
19174 // because this custom-inserter would have generated:
19186 // A: X = ...; Y = ...
19188 // C: Z = PHI [X, A], [Y, B]
19190 // E: PHI [X, C], [Z, D]
19192 // If we lower both CMOVs in a single step, we can instead generate:
19204 // A: X = ...; Y = ...
19206 // E: PHI [X, A], [X, C], [Y, D]
19208 // Which, in our sitofp/fcmp example, gives us something like:
19210 // ucomiss %xmm1, %xmm0
19211 // movss <1.0f>, %xmm0
19214 // xorps %xmm0, %xmm0
19218 MachineInstr *NextCMOV = nullptr;
19219 MachineBasicBlock::iterator NextMIIt =
19220 std::next(MachineBasicBlock::iterator(MI));
19221 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
19222 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
19223 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
19224 NextCMOV = &*NextMIIt;
19226 MachineBasicBlock *jcc1MBB = nullptr;
19228 // If we have a double CMOV, we lower it to two successive branches to
19229 // the same block. EFLAGS is used by both, so mark it as live in the second.
19231 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
19232 F->insert(It, jcc1MBB);
19233 jcc1MBB->addLiveIn(X86::EFLAGS);
19236 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19237 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19238 F->insert(It, copy0MBB);
19239 F->insert(It, sinkMBB);
19241 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19242 // live into the sink and copy blocks.
19243 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
19245 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
19246 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
19247 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
19248 copy0MBB->addLiveIn(X86::EFLAGS);
19249 sinkMBB->addLiveIn(X86::EFLAGS);
19252 // Transfer the remainder of BB and its successor edges to sinkMBB.
19253 sinkMBB->splice(sinkMBB->begin(), BB,
19254 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19255 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19257 // Add the true and fallthrough blocks as its successors.
19259 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
19260 BB->addSuccessor(jcc1MBB);
19262 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
19263 // jump to the sinkMBB.
19264 jcc1MBB->addSuccessor(copy0MBB);
19265 jcc1MBB->addSuccessor(sinkMBB);
19267 BB->addSuccessor(copy0MBB);
19270 // The true block target of the first (or only) branch is always sinkMBB.
19271 BB->addSuccessor(sinkMBB);
19273 // Create the conditional branch instruction.
19275 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19276 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19279 unsigned Opc2 = X86::GetCondBranchFromCond(
19280 (X86::CondCode)NextCMOV->getOperand(3).getImm());
19281 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
19285 // %FalseValue = ...
19286 // # fallthrough to sinkMBB
19287 copy0MBB->addSuccessor(sinkMBB);
19290 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19292 MachineInstrBuilder MIB =
19293 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
19294 MI->getOperand(0).getReg())
19295 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19296 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19298 // If we have a double CMOV, the second Jcc provides the same incoming
19299 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
19301 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
19302 // Copy the PHI result to the register defined by the second CMOV.
19303 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
19304 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
19305 .addReg(MI->getOperand(0).getReg());
19306 NextCMOV->eraseFromParent();
19309 MI->eraseFromParent(); // The pseudo instruction is gone now.
19313 MachineBasicBlock *
19314 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19315 MachineBasicBlock *BB) const {
19316 MachineFunction *MF = BB->getParent();
19317 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19318 DebugLoc DL = MI->getDebugLoc();
19319 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19321 assert(MF->shouldSplitStack());
19323 const bool Is64Bit = Subtarget->is64Bit();
19324 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19326 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19327 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19330 // ... [Till the alloca]
19331 // If stacklet is not large enough, jump to mallocMBB
19334 // Allocate by subtracting from RSP
19335 // Jump to continueMBB
19338 // Allocate by call to runtime
19342 // [rest of original BB]
19345 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19346 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19347 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19349 MachineRegisterInfo &MRI = MF->getRegInfo();
19350 const TargetRegisterClass *AddrRegClass =
19351 getRegClassFor(getPointerTy());
19353 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19354 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19355 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19356 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19357 sizeVReg = MI->getOperand(1).getReg(),
19358 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19360 MachineFunction::iterator MBBIter = BB;
19363 MF->insert(MBBIter, bumpMBB);
19364 MF->insert(MBBIter, mallocMBB);
19365 MF->insert(MBBIter, continueMBB);
19367 continueMBB->splice(continueMBB->begin(), BB,
19368 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19369 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19371 // Add code to the main basic block to check if the stack limit has been hit,
19372 // and if so, jump to mallocMBB otherwise to bumpMBB.
19373 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19374 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19375 .addReg(tmpSPVReg).addReg(sizeVReg);
19376 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19377 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19378 .addReg(SPLimitVReg);
19379 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
19381 // bumpMBB simply decreases the stack pointer, since we know the current
19382 // stacklet has enough space.
19383 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19384 .addReg(SPLimitVReg);
19385 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19386 .addReg(SPLimitVReg);
19387 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19389 // Calls into a routine in libgcc to allocate more space from the heap.
19390 const uint32_t *RegMask =
19391 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
19393 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19395 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19396 .addExternalSymbol("__morestack_allocate_stack_space")
19397 .addRegMask(RegMask)
19398 .addReg(X86::RDI, RegState::Implicit)
19399 .addReg(X86::RAX, RegState::ImplicitDefine);
19400 } else if (Is64Bit) {
19401 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19403 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19404 .addExternalSymbol("__morestack_allocate_stack_space")
19405 .addRegMask(RegMask)
19406 .addReg(X86::EDI, RegState::Implicit)
19407 .addReg(X86::EAX, RegState::ImplicitDefine);
19409 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19411 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19412 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19413 .addExternalSymbol("__morestack_allocate_stack_space")
19414 .addRegMask(RegMask)
19415 .addReg(X86::EAX, RegState::ImplicitDefine);
19419 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19422 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19423 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19424 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19426 // Set up the CFG correctly.
19427 BB->addSuccessor(bumpMBB);
19428 BB->addSuccessor(mallocMBB);
19429 mallocMBB->addSuccessor(continueMBB);
19430 bumpMBB->addSuccessor(continueMBB);
19432 // Take care of the PHI nodes.
19433 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19434 MI->getOperand(0).getReg())
19435 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19436 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19438 // Delete the original pseudo instruction.
19439 MI->eraseFromParent();
19442 return continueMBB;
19445 MachineBasicBlock *
19446 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19447 MachineBasicBlock *BB) const {
19448 DebugLoc DL = MI->getDebugLoc();
19450 assert(!Subtarget->isTargetMachO());
19452 X86FrameLowering::emitStackProbeCall(*BB->getParent(), *BB, MI, DL);
19454 MI->eraseFromParent(); // The pseudo instruction is gone now.
19458 MachineBasicBlock *
19459 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19460 MachineBasicBlock *BB) const {
19461 // This is pretty easy. We're taking the value that we received from
19462 // our load from the relocation, sticking it in either RDI (x86-64)
19463 // or EAX and doing an indirect call. The return value will then
19464 // be in the normal return register.
19465 MachineFunction *F = BB->getParent();
19466 const X86InstrInfo *TII = Subtarget->getInstrInfo();
19467 DebugLoc DL = MI->getDebugLoc();
19469 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19470 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19472 // Get a register mask for the lowered call.
19473 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19474 // proper register mask.
19475 const uint32_t *RegMask =
19476 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
19477 if (Subtarget->is64Bit()) {
19478 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19479 TII->get(X86::MOV64rm), X86::RDI)
19481 .addImm(0).addReg(0)
19482 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19483 MI->getOperand(3).getTargetFlags())
19485 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19486 addDirectMem(MIB, X86::RDI);
19487 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19488 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19489 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19490 TII->get(X86::MOV32rm), X86::EAX)
19492 .addImm(0).addReg(0)
19493 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19494 MI->getOperand(3).getTargetFlags())
19496 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19497 addDirectMem(MIB, X86::EAX);
19498 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19500 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19501 TII->get(X86::MOV32rm), X86::EAX)
19502 .addReg(TII->getGlobalBaseReg(F))
19503 .addImm(0).addReg(0)
19504 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19505 MI->getOperand(3).getTargetFlags())
19507 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19508 addDirectMem(MIB, X86::EAX);
19509 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19512 MI->eraseFromParent(); // The pseudo instruction is gone now.
19516 MachineBasicBlock *
19517 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19518 MachineBasicBlock *MBB) const {
19519 DebugLoc DL = MI->getDebugLoc();
19520 MachineFunction *MF = MBB->getParent();
19521 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19522 MachineRegisterInfo &MRI = MF->getRegInfo();
19524 const BasicBlock *BB = MBB->getBasicBlock();
19525 MachineFunction::iterator I = MBB;
19528 // Memory Reference
19529 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19530 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19533 unsigned MemOpndSlot = 0;
19535 unsigned CurOp = 0;
19537 DstReg = MI->getOperand(CurOp++).getReg();
19538 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19539 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19540 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19541 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19543 MemOpndSlot = CurOp;
19545 MVT PVT = getPointerTy();
19546 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19547 "Invalid Pointer Size!");
19549 // For v = setjmp(buf), we generate
19552 // buf[LabelOffset] = restoreMBB
19553 // SjLjSetup restoreMBB
19559 // v = phi(main, restore)
19562 // if base pointer being used, load it from frame
19565 MachineBasicBlock *thisMBB = MBB;
19566 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19567 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19568 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19569 MF->insert(I, mainMBB);
19570 MF->insert(I, sinkMBB);
19571 MF->push_back(restoreMBB);
19573 MachineInstrBuilder MIB;
19575 // Transfer the remainder of BB and its successor edges to sinkMBB.
19576 sinkMBB->splice(sinkMBB->begin(), MBB,
19577 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19578 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19581 unsigned PtrStoreOpc = 0;
19582 unsigned LabelReg = 0;
19583 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19584 Reloc::Model RM = MF->getTarget().getRelocationModel();
19585 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19586 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19588 // Prepare IP either in reg or imm.
19589 if (!UseImmLabel) {
19590 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19591 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19592 LabelReg = MRI.createVirtualRegister(PtrRC);
19593 if (Subtarget->is64Bit()) {
19594 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19598 .addMBB(restoreMBB)
19601 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19602 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19603 .addReg(XII->getGlobalBaseReg(MF))
19606 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19610 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19612 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19613 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19614 if (i == X86::AddrDisp)
19615 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19617 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19620 MIB.addReg(LabelReg);
19622 MIB.addMBB(restoreMBB);
19623 MIB.setMemRefs(MMOBegin, MMOEnd);
19625 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19626 .addMBB(restoreMBB);
19628 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19629 MIB.addRegMask(RegInfo->getNoPreservedMask());
19630 thisMBB->addSuccessor(mainMBB);
19631 thisMBB->addSuccessor(restoreMBB);
19635 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19636 mainMBB->addSuccessor(sinkMBB);
19639 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19640 TII->get(X86::PHI), DstReg)
19641 .addReg(mainDstReg).addMBB(mainMBB)
19642 .addReg(restoreDstReg).addMBB(restoreMBB);
19645 if (RegInfo->hasBasePointer(*MF)) {
19646 const bool Uses64BitFramePtr =
19647 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
19648 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
19649 X86FI->setRestoreBasePointer(MF);
19650 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
19651 unsigned BasePtr = RegInfo->getBaseRegister();
19652 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
19653 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
19654 FramePtr, true, X86FI->getRestoreBasePointerOffset())
19655 .setMIFlag(MachineInstr::FrameSetup);
19657 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19658 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
19659 restoreMBB->addSuccessor(sinkMBB);
19661 MI->eraseFromParent();
19665 MachineBasicBlock *
19666 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19667 MachineBasicBlock *MBB) const {
19668 DebugLoc DL = MI->getDebugLoc();
19669 MachineFunction *MF = MBB->getParent();
19670 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19671 MachineRegisterInfo &MRI = MF->getRegInfo();
19673 // Memory Reference
19674 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19675 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19677 MVT PVT = getPointerTy();
19678 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19679 "Invalid Pointer Size!");
19681 const TargetRegisterClass *RC =
19682 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19683 unsigned Tmp = MRI.createVirtualRegister(RC);
19684 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19685 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19686 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19687 unsigned SP = RegInfo->getStackRegister();
19689 MachineInstrBuilder MIB;
19691 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19692 const int64_t SPOffset = 2 * PVT.getStoreSize();
19694 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19695 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19698 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19699 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19700 MIB.addOperand(MI->getOperand(i));
19701 MIB.setMemRefs(MMOBegin, MMOEnd);
19703 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19704 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19705 if (i == X86::AddrDisp)
19706 MIB.addDisp(MI->getOperand(i), LabelOffset);
19708 MIB.addOperand(MI->getOperand(i));
19710 MIB.setMemRefs(MMOBegin, MMOEnd);
19712 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19713 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19714 if (i == X86::AddrDisp)
19715 MIB.addDisp(MI->getOperand(i), SPOffset);
19717 MIB.addOperand(MI->getOperand(i));
19719 MIB.setMemRefs(MMOBegin, MMOEnd);
19721 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19723 MI->eraseFromParent();
19727 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19728 // accumulator loops. Writing back to the accumulator allows the coalescer
19729 // to remove extra copies in the loop.
19730 MachineBasicBlock *
19731 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19732 MachineBasicBlock *MBB) const {
19733 MachineOperand &AddendOp = MI->getOperand(3);
19735 // Bail out early if the addend isn't a register - we can't switch these.
19736 if (!AddendOp.isReg())
19739 MachineFunction &MF = *MBB->getParent();
19740 MachineRegisterInfo &MRI = MF.getRegInfo();
19742 // Check whether the addend is defined by a PHI:
19743 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19744 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19745 if (!AddendDef.isPHI())
19748 // Look for the following pattern:
19750 // %addend = phi [%entry, 0], [%loop, %result]
19752 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19756 // %addend = phi [%entry, 0], [%loop, %result]
19758 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19760 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19761 assert(AddendDef.getOperand(i).isReg());
19762 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19763 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19764 if (&PHISrcInst == MI) {
19765 // Found a matching instruction.
19766 unsigned NewFMAOpc = 0;
19767 switch (MI->getOpcode()) {
19768 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19769 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19770 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19771 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19772 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19773 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19774 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19775 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19776 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19777 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19778 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19779 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19780 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19781 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19782 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19783 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19784 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
19785 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
19786 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
19787 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
19789 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19790 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19791 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19792 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19793 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19794 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19795 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19796 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19797 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
19798 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
19799 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
19800 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
19801 default: llvm_unreachable("Unrecognized FMA variant.");
19804 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
19805 MachineInstrBuilder MIB =
19806 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19807 .addOperand(MI->getOperand(0))
19808 .addOperand(MI->getOperand(3))
19809 .addOperand(MI->getOperand(2))
19810 .addOperand(MI->getOperand(1));
19811 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19812 MI->eraseFromParent();
19819 MachineBasicBlock *
19820 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19821 MachineBasicBlock *BB) const {
19822 switch (MI->getOpcode()) {
19823 default: llvm_unreachable("Unexpected instr type to insert");
19824 case X86::TAILJMPd64:
19825 case X86::TAILJMPr64:
19826 case X86::TAILJMPm64:
19827 case X86::TAILJMPd64_REX:
19828 case X86::TAILJMPr64_REX:
19829 case X86::TAILJMPm64_REX:
19830 llvm_unreachable("TAILJMP64 would not be touched here.");
19831 case X86::TCRETURNdi64:
19832 case X86::TCRETURNri64:
19833 case X86::TCRETURNmi64:
19835 case X86::WIN_ALLOCA:
19836 return EmitLoweredWinAlloca(MI, BB);
19837 case X86::SEG_ALLOCA_32:
19838 case X86::SEG_ALLOCA_64:
19839 return EmitLoweredSegAlloca(MI, BB);
19840 case X86::TLSCall_32:
19841 case X86::TLSCall_64:
19842 return EmitLoweredTLSCall(MI, BB);
19843 case X86::CMOV_GR8:
19844 case X86::CMOV_FR32:
19845 case X86::CMOV_FR64:
19846 case X86::CMOV_V4F32:
19847 case X86::CMOV_V2F64:
19848 case X86::CMOV_V2I64:
19849 case X86::CMOV_V8F32:
19850 case X86::CMOV_V4F64:
19851 case X86::CMOV_V4I64:
19852 case X86::CMOV_V16F32:
19853 case X86::CMOV_V8F64:
19854 case X86::CMOV_V8I64:
19855 case X86::CMOV_GR16:
19856 case X86::CMOV_GR32:
19857 case X86::CMOV_RFP32:
19858 case X86::CMOV_RFP64:
19859 case X86::CMOV_RFP80:
19860 case X86::CMOV_V8I1:
19861 case X86::CMOV_V16I1:
19862 case X86::CMOV_V32I1:
19863 case X86::CMOV_V64I1:
19864 return EmitLoweredSelect(MI, BB);
19866 case X86::FP32_TO_INT16_IN_MEM:
19867 case X86::FP32_TO_INT32_IN_MEM:
19868 case X86::FP32_TO_INT64_IN_MEM:
19869 case X86::FP64_TO_INT16_IN_MEM:
19870 case X86::FP64_TO_INT32_IN_MEM:
19871 case X86::FP64_TO_INT64_IN_MEM:
19872 case X86::FP80_TO_INT16_IN_MEM:
19873 case X86::FP80_TO_INT32_IN_MEM:
19874 case X86::FP80_TO_INT64_IN_MEM: {
19875 MachineFunction *F = BB->getParent();
19876 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19877 DebugLoc DL = MI->getDebugLoc();
19879 // Change the floating point control register to use "round towards zero"
19880 // mode when truncating to an integer value.
19881 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19882 addFrameReference(BuildMI(*BB, MI, DL,
19883 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19885 // Load the old value of the high byte of the control word...
19887 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19888 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19891 // Set the high part to be round to zero...
19892 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19895 // Reload the modified control word now...
19896 addFrameReference(BuildMI(*BB, MI, DL,
19897 TII->get(X86::FLDCW16m)), CWFrameIdx);
19899 // Restore the memory image of control word to original value
19900 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19903 // Get the X86 opcode to use.
19905 switch (MI->getOpcode()) {
19906 default: llvm_unreachable("illegal opcode!");
19907 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19908 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19909 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19910 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19911 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19912 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19913 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19914 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19915 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19919 MachineOperand &Op = MI->getOperand(0);
19921 AM.BaseType = X86AddressMode::RegBase;
19922 AM.Base.Reg = Op.getReg();
19924 AM.BaseType = X86AddressMode::FrameIndexBase;
19925 AM.Base.FrameIndex = Op.getIndex();
19927 Op = MI->getOperand(1);
19929 AM.Scale = Op.getImm();
19930 Op = MI->getOperand(2);
19932 AM.IndexReg = Op.getImm();
19933 Op = MI->getOperand(3);
19934 if (Op.isGlobal()) {
19935 AM.GV = Op.getGlobal();
19937 AM.Disp = Op.getImm();
19939 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19940 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19942 // Reload the original control word now.
19943 addFrameReference(BuildMI(*BB, MI, DL,
19944 TII->get(X86::FLDCW16m)), CWFrameIdx);
19946 MI->eraseFromParent(); // The pseudo instruction is gone now.
19949 // String/text processing lowering.
19950 case X86::PCMPISTRM128REG:
19951 case X86::VPCMPISTRM128REG:
19952 case X86::PCMPISTRM128MEM:
19953 case X86::VPCMPISTRM128MEM:
19954 case X86::PCMPESTRM128REG:
19955 case X86::VPCMPESTRM128REG:
19956 case X86::PCMPESTRM128MEM:
19957 case X86::VPCMPESTRM128MEM:
19958 assert(Subtarget->hasSSE42() &&
19959 "Target must have SSE4.2 or AVX features enabled");
19960 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
19962 // String/text processing lowering.
19963 case X86::PCMPISTRIREG:
19964 case X86::VPCMPISTRIREG:
19965 case X86::PCMPISTRIMEM:
19966 case X86::VPCMPISTRIMEM:
19967 case X86::PCMPESTRIREG:
19968 case X86::VPCMPESTRIREG:
19969 case X86::PCMPESTRIMEM:
19970 case X86::VPCMPESTRIMEM:
19971 assert(Subtarget->hasSSE42() &&
19972 "Target must have SSE4.2 or AVX features enabled");
19973 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
19975 // Thread synchronization.
19977 return EmitMonitor(MI, BB, Subtarget);
19981 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
19983 case X86::VASTART_SAVE_XMM_REGS:
19984 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19986 case X86::VAARG_64:
19987 return EmitVAARG64WithCustomInserter(MI, BB);
19989 case X86::EH_SjLj_SetJmp32:
19990 case X86::EH_SjLj_SetJmp64:
19991 return emitEHSjLjSetJmp(MI, BB);
19993 case X86::EH_SjLj_LongJmp32:
19994 case X86::EH_SjLj_LongJmp64:
19995 return emitEHSjLjLongJmp(MI, BB);
19997 case TargetOpcode::STATEPOINT:
19998 // As an implementation detail, STATEPOINT shares the STACKMAP format at
19999 // this point in the process. We diverge later.
20000 return emitPatchPoint(MI, BB);
20002 case TargetOpcode::STACKMAP:
20003 case TargetOpcode::PATCHPOINT:
20004 return emitPatchPoint(MI, BB);
20006 case X86::VFMADDPDr213r:
20007 case X86::VFMADDPSr213r:
20008 case X86::VFMADDSDr213r:
20009 case X86::VFMADDSSr213r:
20010 case X86::VFMSUBPDr213r:
20011 case X86::VFMSUBPSr213r:
20012 case X86::VFMSUBSDr213r:
20013 case X86::VFMSUBSSr213r:
20014 case X86::VFNMADDPDr213r:
20015 case X86::VFNMADDPSr213r:
20016 case X86::VFNMADDSDr213r:
20017 case X86::VFNMADDSSr213r:
20018 case X86::VFNMSUBPDr213r:
20019 case X86::VFNMSUBPSr213r:
20020 case X86::VFNMSUBSDr213r:
20021 case X86::VFNMSUBSSr213r:
20022 case X86::VFMADDSUBPDr213r:
20023 case X86::VFMADDSUBPSr213r:
20024 case X86::VFMSUBADDPDr213r:
20025 case X86::VFMSUBADDPSr213r:
20026 case X86::VFMADDPDr213rY:
20027 case X86::VFMADDPSr213rY:
20028 case X86::VFMSUBPDr213rY:
20029 case X86::VFMSUBPSr213rY:
20030 case X86::VFNMADDPDr213rY:
20031 case X86::VFNMADDPSr213rY:
20032 case X86::VFNMSUBPDr213rY:
20033 case X86::VFNMSUBPSr213rY:
20034 case X86::VFMADDSUBPDr213rY:
20035 case X86::VFMADDSUBPSr213rY:
20036 case X86::VFMSUBADDPDr213rY:
20037 case X86::VFMSUBADDPSr213rY:
20038 return emitFMA3Instr(MI, BB);
20042 //===----------------------------------------------------------------------===//
20043 // X86 Optimization Hooks
20044 //===----------------------------------------------------------------------===//
20046 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20049 const SelectionDAG &DAG,
20050 unsigned Depth) const {
20051 unsigned BitWidth = KnownZero.getBitWidth();
20052 unsigned Opc = Op.getOpcode();
20053 assert((Opc >= ISD::BUILTIN_OP_END ||
20054 Opc == ISD::INTRINSIC_WO_CHAIN ||
20055 Opc == ISD::INTRINSIC_W_CHAIN ||
20056 Opc == ISD::INTRINSIC_VOID) &&
20057 "Should use MaskedValueIsZero if you don't know whether Op"
20058 " is a target node!");
20060 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20074 // These nodes' second result is a boolean.
20075 if (Op.getResNo() == 0)
20078 case X86ISD::SETCC:
20079 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20081 case ISD::INTRINSIC_WO_CHAIN: {
20082 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20083 unsigned NumLoBits = 0;
20086 case Intrinsic::x86_sse_movmsk_ps:
20087 case Intrinsic::x86_avx_movmsk_ps_256:
20088 case Intrinsic::x86_sse2_movmsk_pd:
20089 case Intrinsic::x86_avx_movmsk_pd_256:
20090 case Intrinsic::x86_mmx_pmovmskb:
20091 case Intrinsic::x86_sse2_pmovmskb_128:
20092 case Intrinsic::x86_avx2_pmovmskb: {
20093 // High bits of movmskp{s|d}, pmovmskb are known zero.
20095 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20096 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20097 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20098 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20099 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20100 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20101 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20102 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20104 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20113 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20115 const SelectionDAG &,
20116 unsigned Depth) const {
20117 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20118 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20119 return Op.getValueType().getScalarType().getSizeInBits();
20125 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20126 /// node is a GlobalAddress + offset.
20127 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20128 const GlobalValue* &GA,
20129 int64_t &Offset) const {
20130 if (N->getOpcode() == X86ISD::Wrapper) {
20131 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20132 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20133 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20137 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20140 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20141 /// same as extracting the high 128-bit part of 256-bit vector and then
20142 /// inserting the result into the low part of a new 256-bit vector
20143 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20144 EVT VT = SVOp->getValueType(0);
20145 unsigned NumElems = VT.getVectorNumElements();
20147 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20148 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20149 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20150 SVOp->getMaskElt(j) >= 0)
20156 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20157 /// same as extracting the low 128-bit part of 256-bit vector and then
20158 /// inserting the result into the high part of a new 256-bit vector
20159 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20160 EVT VT = SVOp->getValueType(0);
20161 unsigned NumElems = VT.getVectorNumElements();
20163 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20164 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20165 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20166 SVOp->getMaskElt(j) >= 0)
20172 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20173 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20174 TargetLowering::DAGCombinerInfo &DCI,
20175 const X86Subtarget* Subtarget) {
20177 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20178 SDValue V1 = SVOp->getOperand(0);
20179 SDValue V2 = SVOp->getOperand(1);
20180 EVT VT = SVOp->getValueType(0);
20181 unsigned NumElems = VT.getVectorNumElements();
20183 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20184 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20188 // V UNDEF BUILD_VECTOR UNDEF
20190 // CONCAT_VECTOR CONCAT_VECTOR
20193 // RESULT: V + zero extended
20195 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20196 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20197 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20200 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20203 // To match the shuffle mask, the first half of the mask should
20204 // be exactly the first vector, and all the rest a splat with the
20205 // first element of the second one.
20206 for (unsigned i = 0; i != NumElems/2; ++i)
20207 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20208 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20211 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20212 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20213 if (Ld->hasNUsesOfValue(1, 0)) {
20214 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20215 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20217 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20219 Ld->getPointerInfo(),
20220 Ld->getAlignment(),
20221 false/*isVolatile*/, true/*ReadMem*/,
20222 false/*WriteMem*/);
20224 // Make sure the newly-created LOAD is in the same position as Ld in
20225 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20226 // and update uses of Ld's output chain to use the TokenFactor.
20227 if (Ld->hasAnyUseOfValue(1)) {
20228 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20229 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20230 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20231 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20232 SDValue(ResNode.getNode(), 1));
20235 return DAG.getBitcast(VT, ResNode);
20239 // Emit a zeroed vector and insert the desired subvector on its
20241 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20242 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20243 return DCI.CombineTo(N, InsV);
20246 //===--------------------------------------------------------------------===//
20247 // Combine some shuffles into subvector extracts and inserts:
20250 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20251 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20252 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20253 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20254 return DCI.CombineTo(N, InsV);
20257 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20258 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20259 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20260 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20261 return DCI.CombineTo(N, InsV);
20267 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20270 /// This is the leaf of the recursive combinine below. When we have found some
20271 /// chain of single-use x86 shuffle instructions and accumulated the combined
20272 /// shuffle mask represented by them, this will try to pattern match that mask
20273 /// into either a single instruction if there is a special purpose instruction
20274 /// for this operation, or into a PSHUFB instruction which is a fully general
20275 /// instruction but should only be used to replace chains over a certain depth.
20276 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20277 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20278 TargetLowering::DAGCombinerInfo &DCI,
20279 const X86Subtarget *Subtarget) {
20280 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20282 // Find the operand that enters the chain. Note that multiple uses are OK
20283 // here, we're not going to remove the operand we find.
20284 SDValue Input = Op.getOperand(0);
20285 while (Input.getOpcode() == ISD::BITCAST)
20286 Input = Input.getOperand(0);
20288 MVT VT = Input.getSimpleValueType();
20289 MVT RootVT = Root.getSimpleValueType();
20292 // Just remove no-op shuffle masks.
20293 if (Mask.size() == 1) {
20294 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
20299 // Use the float domain if the operand type is a floating point type.
20300 bool FloatDomain = VT.isFloatingPoint();
20302 // For floating point shuffles, we don't have free copies in the shuffle
20303 // instructions or the ability to load as part of the instruction, so
20304 // canonicalize their shuffles to UNPCK or MOV variants.
20306 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20307 // vectors because it can have a load folded into it that UNPCK cannot. This
20308 // doesn't preclude something switching to the shorter encoding post-RA.
20310 // FIXME: Should teach these routines about AVX vector widths.
20311 if (FloatDomain && VT.getSizeInBits() == 128) {
20312 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
20313 bool Lo = Mask.equals({0, 0});
20316 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20317 // is no slower than UNPCKLPD but has the option to fold the input operand
20318 // into even an unaligned memory load.
20319 if (Lo && Subtarget->hasSSE3()) {
20320 Shuffle = X86ISD::MOVDDUP;
20321 ShuffleVT = MVT::v2f64;
20323 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20324 // than the UNPCK variants.
20325 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20326 ShuffleVT = MVT::v4f32;
20328 if (Depth == 1 && Root->getOpcode() == Shuffle)
20329 return false; // Nothing to do!
20330 Op = DAG.getBitcast(ShuffleVT, Input);
20331 DCI.AddToWorklist(Op.getNode());
20332 if (Shuffle == X86ISD::MOVDDUP)
20333 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20335 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20336 DCI.AddToWorklist(Op.getNode());
20337 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20341 if (Subtarget->hasSSE3() &&
20342 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
20343 bool Lo = Mask.equals({0, 0, 2, 2});
20344 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20345 MVT ShuffleVT = MVT::v4f32;
20346 if (Depth == 1 && Root->getOpcode() == Shuffle)
20347 return false; // Nothing to do!
20348 Op = DAG.getBitcast(ShuffleVT, Input);
20349 DCI.AddToWorklist(Op.getNode());
20350 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20351 DCI.AddToWorklist(Op.getNode());
20352 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20356 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
20357 bool Lo = Mask.equals({0, 0, 1, 1});
20358 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20359 MVT ShuffleVT = MVT::v4f32;
20360 if (Depth == 1 && Root->getOpcode() == Shuffle)
20361 return false; // Nothing to do!
20362 Op = DAG.getBitcast(ShuffleVT, Input);
20363 DCI.AddToWorklist(Op.getNode());
20364 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20365 DCI.AddToWorklist(Op.getNode());
20366 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20372 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20373 // variants as none of these have single-instruction variants that are
20374 // superior to the UNPCK formulation.
20375 if (!FloatDomain && VT.getSizeInBits() == 128 &&
20376 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20377 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
20378 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
20380 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
20381 bool Lo = Mask[0] == 0;
20382 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20383 if (Depth == 1 && Root->getOpcode() == Shuffle)
20384 return false; // Nothing to do!
20386 switch (Mask.size()) {
20388 ShuffleVT = MVT::v8i16;
20391 ShuffleVT = MVT::v16i8;
20394 llvm_unreachable("Impossible mask size!");
20396 Op = DAG.getBitcast(ShuffleVT, Input);
20397 DCI.AddToWorklist(Op.getNode());
20398 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20399 DCI.AddToWorklist(Op.getNode());
20400 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20405 // Don't try to re-form single instruction chains under any circumstances now
20406 // that we've done encoding canonicalization for them.
20410 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20411 // can replace them with a single PSHUFB instruction profitably. Intel's
20412 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20413 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20414 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20415 SmallVector<SDValue, 16> PSHUFBMask;
20416 int NumBytes = VT.getSizeInBits() / 8;
20417 int Ratio = NumBytes / Mask.size();
20418 for (int i = 0; i < NumBytes; ++i) {
20419 if (Mask[i / Ratio] == SM_SentinelUndef) {
20420 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20423 int M = Mask[i / Ratio] != SM_SentinelZero
20424 ? Ratio * Mask[i / Ratio] + i % Ratio
20426 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
20428 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
20429 Op = DAG.getBitcast(ByteVT, Input);
20430 DCI.AddToWorklist(Op.getNode());
20431 SDValue PSHUFBMaskOp =
20432 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
20433 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20434 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
20435 DCI.AddToWorklist(Op.getNode());
20436 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20441 // Failed to find any combines.
20445 /// \brief Fully generic combining of x86 shuffle instructions.
20447 /// This should be the last combine run over the x86 shuffle instructions. Once
20448 /// they have been fully optimized, this will recursively consider all chains
20449 /// of single-use shuffle instructions, build a generic model of the cumulative
20450 /// shuffle operation, and check for simpler instructions which implement this
20451 /// operation. We use this primarily for two purposes:
20453 /// 1) Collapse generic shuffles to specialized single instructions when
20454 /// equivalent. In most cases, this is just an encoding size win, but
20455 /// sometimes we will collapse multiple generic shuffles into a single
20456 /// special-purpose shuffle.
20457 /// 2) Look for sequences of shuffle instructions with 3 or more total
20458 /// instructions, and replace them with the slightly more expensive SSSE3
20459 /// PSHUFB instruction if available. We do this as the last combining step
20460 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20461 /// a suitable short sequence of other instructions. The PHUFB will either
20462 /// use a register or have to read from memory and so is slightly (but only
20463 /// slightly) more expensive than the other shuffle instructions.
20465 /// Because this is inherently a quadratic operation (for each shuffle in
20466 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20467 /// This should never be an issue in practice as the shuffle lowering doesn't
20468 /// produce sequences of more than 8 instructions.
20470 /// FIXME: We will currently miss some cases where the redundant shuffling
20471 /// would simplify under the threshold for PSHUFB formation because of
20472 /// combine-ordering. To fix this, we should do the redundant instruction
20473 /// combining in this recursive walk.
20474 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20475 ArrayRef<int> RootMask,
20476 int Depth, bool HasPSHUFB,
20478 TargetLowering::DAGCombinerInfo &DCI,
20479 const X86Subtarget *Subtarget) {
20480 // Bound the depth of our recursive combine because this is ultimately
20481 // quadratic in nature.
20485 // Directly rip through bitcasts to find the underlying operand.
20486 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20487 Op = Op.getOperand(0);
20489 MVT VT = Op.getSimpleValueType();
20490 if (!VT.isVector())
20491 return false; // Bail if we hit a non-vector.
20493 assert(Root.getSimpleValueType().isVector() &&
20494 "Shuffles operate on vector types!");
20495 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20496 "Can only combine shuffles of the same vector register size.");
20498 if (!isTargetShuffle(Op.getOpcode()))
20500 SmallVector<int, 16> OpMask;
20502 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20503 // We only can combine unary shuffles which we can decode the mask for.
20504 if (!HaveMask || !IsUnary)
20507 assert(VT.getVectorNumElements() == OpMask.size() &&
20508 "Different mask size from vector size!");
20509 assert(((RootMask.size() > OpMask.size() &&
20510 RootMask.size() % OpMask.size() == 0) ||
20511 (OpMask.size() > RootMask.size() &&
20512 OpMask.size() % RootMask.size() == 0) ||
20513 OpMask.size() == RootMask.size()) &&
20514 "The smaller number of elements must divide the larger.");
20515 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20516 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20517 assert(((RootRatio == 1 && OpRatio == 1) ||
20518 (RootRatio == 1) != (OpRatio == 1)) &&
20519 "Must not have a ratio for both incoming and op masks!");
20521 SmallVector<int, 16> Mask;
20522 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20524 // Merge this shuffle operation's mask into our accumulated mask. Note that
20525 // this shuffle's mask will be the first applied to the input, followed by the
20526 // root mask to get us all the way to the root value arrangement. The reason
20527 // for this order is that we are recursing up the operation chain.
20528 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20529 int RootIdx = i / RootRatio;
20530 if (RootMask[RootIdx] < 0) {
20531 // This is a zero or undef lane, we're done.
20532 Mask.push_back(RootMask[RootIdx]);
20536 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20537 int OpIdx = RootMaskedIdx / OpRatio;
20538 if (OpMask[OpIdx] < 0) {
20539 // The incoming lanes are zero or undef, it doesn't matter which ones we
20541 Mask.push_back(OpMask[OpIdx]);
20545 // Ok, we have non-zero lanes, map them through.
20546 Mask.push_back(OpMask[OpIdx] * OpRatio +
20547 RootMaskedIdx % OpRatio);
20550 // See if we can recurse into the operand to combine more things.
20551 switch (Op.getOpcode()) {
20552 case X86ISD::PSHUFB:
20554 case X86ISD::PSHUFD:
20555 case X86ISD::PSHUFHW:
20556 case X86ISD::PSHUFLW:
20557 if (Op.getOperand(0).hasOneUse() &&
20558 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20559 HasPSHUFB, DAG, DCI, Subtarget))
20563 case X86ISD::UNPCKL:
20564 case X86ISD::UNPCKH:
20565 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20566 // We can't check for single use, we have to check that this shuffle is the only user.
20567 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20568 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20569 HasPSHUFB, DAG, DCI, Subtarget))
20574 // Minor canonicalization of the accumulated shuffle mask to make it easier
20575 // to match below. All this does is detect masks with squential pairs of
20576 // elements, and shrink them to the half-width mask. It does this in a loop
20577 // so it will reduce the size of the mask to the minimal width mask which
20578 // performs an equivalent shuffle.
20579 SmallVector<int, 16> WidenedMask;
20580 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
20581 Mask = std::move(WidenedMask);
20582 WidenedMask.clear();
20585 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20589 /// \brief Get the PSHUF-style mask from PSHUF node.
20591 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20592 /// PSHUF-style masks that can be reused with such instructions.
20593 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20594 MVT VT = N.getSimpleValueType();
20595 SmallVector<int, 4> Mask;
20597 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
20601 // If we have more than 128-bits, only the low 128-bits of shuffle mask
20602 // matter. Check that the upper masks are repeats and remove them.
20603 if (VT.getSizeInBits() > 128) {
20604 int LaneElts = 128 / VT.getScalarSizeInBits();
20606 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
20607 for (int j = 0; j < LaneElts; ++j)
20608 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
20609 "Mask doesn't repeat in high 128-bit lanes!");
20611 Mask.resize(LaneElts);
20614 switch (N.getOpcode()) {
20615 case X86ISD::PSHUFD:
20617 case X86ISD::PSHUFLW:
20620 case X86ISD::PSHUFHW:
20621 Mask.erase(Mask.begin(), Mask.begin() + 4);
20622 for (int &M : Mask)
20626 llvm_unreachable("No valid shuffle instruction found!");
20630 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20632 /// We walk up the chain and look for a combinable shuffle, skipping over
20633 /// shuffles that we could hoist this shuffle's transformation past without
20634 /// altering anything.
20636 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20638 TargetLowering::DAGCombinerInfo &DCI) {
20639 assert(N.getOpcode() == X86ISD::PSHUFD &&
20640 "Called with something other than an x86 128-bit half shuffle!");
20643 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20644 // of the shuffles in the chain so that we can form a fresh chain to replace
20646 SmallVector<SDValue, 8> Chain;
20647 SDValue V = N.getOperand(0);
20648 for (; V.hasOneUse(); V = V.getOperand(0)) {
20649 switch (V.getOpcode()) {
20651 return SDValue(); // Nothing combined!
20654 // Skip bitcasts as we always know the type for the target specific
20658 case X86ISD::PSHUFD:
20659 // Found another dword shuffle.
20662 case X86ISD::PSHUFLW:
20663 // Check that the low words (being shuffled) are the identity in the
20664 // dword shuffle, and the high words are self-contained.
20665 if (Mask[0] != 0 || Mask[1] != 1 ||
20666 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20669 Chain.push_back(V);
20672 case X86ISD::PSHUFHW:
20673 // Check that the high words (being shuffled) are the identity in the
20674 // dword shuffle, and the low words are self-contained.
20675 if (Mask[2] != 2 || Mask[3] != 3 ||
20676 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20679 Chain.push_back(V);
20682 case X86ISD::UNPCKL:
20683 case X86ISD::UNPCKH:
20684 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20685 // shuffle into a preceding word shuffle.
20686 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
20687 V.getSimpleValueType().getScalarType() != MVT::i16)
20690 // Search for a half-shuffle which we can combine with.
20691 unsigned CombineOp =
20692 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20693 if (V.getOperand(0) != V.getOperand(1) ||
20694 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20696 Chain.push_back(V);
20697 V = V.getOperand(0);
20699 switch (V.getOpcode()) {
20701 return SDValue(); // Nothing to combine.
20703 case X86ISD::PSHUFLW:
20704 case X86ISD::PSHUFHW:
20705 if (V.getOpcode() == CombineOp)
20708 Chain.push_back(V);
20712 V = V.getOperand(0);
20716 } while (V.hasOneUse());
20719 // Break out of the loop if we break out of the switch.
20723 if (!V.hasOneUse())
20724 // We fell out of the loop without finding a viable combining instruction.
20727 // Merge this node's mask and our incoming mask.
20728 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20729 for (int &M : Mask)
20731 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20732 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20734 // Rebuild the chain around this new shuffle.
20735 while (!Chain.empty()) {
20736 SDValue W = Chain.pop_back_val();
20738 if (V.getValueType() != W.getOperand(0).getValueType())
20739 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
20741 switch (W.getOpcode()) {
20743 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20745 case X86ISD::UNPCKL:
20746 case X86ISD::UNPCKH:
20747 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20750 case X86ISD::PSHUFD:
20751 case X86ISD::PSHUFLW:
20752 case X86ISD::PSHUFHW:
20753 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20757 if (V.getValueType() != N.getValueType())
20758 V = DAG.getBitcast(N.getValueType(), V);
20760 // Return the new chain to replace N.
20764 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20766 /// We walk up the chain, skipping shuffles of the other half and looking
20767 /// through shuffles which switch halves trying to find a shuffle of the same
20768 /// pair of dwords.
20769 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20771 TargetLowering::DAGCombinerInfo &DCI) {
20773 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20774 "Called with something other than an x86 128-bit half shuffle!");
20776 unsigned CombineOpcode = N.getOpcode();
20778 // Walk up a single-use chain looking for a combinable shuffle.
20779 SDValue V = N.getOperand(0);
20780 for (; V.hasOneUse(); V = V.getOperand(0)) {
20781 switch (V.getOpcode()) {
20783 return false; // Nothing combined!
20786 // Skip bitcasts as we always know the type for the target specific
20790 case X86ISD::PSHUFLW:
20791 case X86ISD::PSHUFHW:
20792 if (V.getOpcode() == CombineOpcode)
20795 // Other-half shuffles are no-ops.
20798 // Break out of the loop if we break out of the switch.
20802 if (!V.hasOneUse())
20803 // We fell out of the loop without finding a viable combining instruction.
20806 // Combine away the bottom node as its shuffle will be accumulated into
20807 // a preceding shuffle.
20808 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20810 // Record the old value.
20813 // Merge this node's mask and our incoming mask (adjusted to account for all
20814 // the pshufd instructions encountered).
20815 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20816 for (int &M : Mask)
20818 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20819 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20821 // Check that the shuffles didn't cancel each other out. If not, we need to
20822 // combine to the new one.
20824 // Replace the combinable shuffle with the combined one, updating all users
20825 // so that we re-evaluate the chain here.
20826 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20831 /// \brief Try to combine x86 target specific shuffles.
20832 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20833 TargetLowering::DAGCombinerInfo &DCI,
20834 const X86Subtarget *Subtarget) {
20836 MVT VT = N.getSimpleValueType();
20837 SmallVector<int, 4> Mask;
20839 switch (N.getOpcode()) {
20840 case X86ISD::PSHUFD:
20841 case X86ISD::PSHUFLW:
20842 case X86ISD::PSHUFHW:
20843 Mask = getPSHUFShuffleMask(N);
20844 assert(Mask.size() == 4);
20850 // Nuke no-op shuffles that show up after combining.
20851 if (isNoopShuffleMask(Mask))
20852 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20854 // Look for simplifications involving one or two shuffle instructions.
20855 SDValue V = N.getOperand(0);
20856 switch (N.getOpcode()) {
20859 case X86ISD::PSHUFLW:
20860 case X86ISD::PSHUFHW:
20861 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
20863 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20864 return SDValue(); // We combined away this shuffle, so we're done.
20866 // See if this reduces to a PSHUFD which is no more expensive and can
20867 // combine with more operations. Note that it has to at least flip the
20868 // dwords as otherwise it would have been removed as a no-op.
20869 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
20870 int DMask[] = {0, 1, 2, 3};
20871 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20872 DMask[DOffset + 0] = DOffset + 1;
20873 DMask[DOffset + 1] = DOffset + 0;
20874 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
20875 V = DAG.getBitcast(DVT, V);
20876 DCI.AddToWorklist(V.getNode());
20877 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
20878 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
20879 DCI.AddToWorklist(V.getNode());
20880 return DAG.getBitcast(VT, V);
20883 // Look for shuffle patterns which can be implemented as a single unpack.
20884 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20885 // only works when we have a PSHUFD followed by two half-shuffles.
20886 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20887 (V.getOpcode() == X86ISD::PSHUFLW ||
20888 V.getOpcode() == X86ISD::PSHUFHW) &&
20889 V.getOpcode() != N.getOpcode() &&
20891 SDValue D = V.getOperand(0);
20892 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20893 D = D.getOperand(0);
20894 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20895 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20896 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20897 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20898 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20900 for (int i = 0; i < 4; ++i) {
20901 WordMask[i + NOffset] = Mask[i] + NOffset;
20902 WordMask[i + VOffset] = VMask[i] + VOffset;
20904 // Map the word mask through the DWord mask.
20906 for (int i = 0; i < 8; ++i)
20907 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20908 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20909 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
20910 // We can replace all three shuffles with an unpack.
20911 V = DAG.getBitcast(VT, D.getOperand(0));
20912 DCI.AddToWorklist(V.getNode());
20913 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20922 case X86ISD::PSHUFD:
20923 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20932 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20934 /// We combine this directly on the abstract vector shuffle nodes so it is
20935 /// easier to generically match. We also insert dummy vector shuffle nodes for
20936 /// the operands which explicitly discard the lanes which are unused by this
20937 /// operation to try to flow through the rest of the combiner the fact that
20938 /// they're unused.
20939 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20941 EVT VT = N->getValueType(0);
20943 // We only handle target-independent shuffles.
20944 // FIXME: It would be easy and harmless to use the target shuffle mask
20945 // extraction tool to support more.
20946 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20949 auto *SVN = cast<ShuffleVectorSDNode>(N);
20950 ArrayRef<int> Mask = SVN->getMask();
20951 SDValue V1 = N->getOperand(0);
20952 SDValue V2 = N->getOperand(1);
20954 // We require the first shuffle operand to be the SUB node, and the second to
20955 // be the ADD node.
20956 // FIXME: We should support the commuted patterns.
20957 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20960 // If there are other uses of these operations we can't fold them.
20961 if (!V1->hasOneUse() || !V2->hasOneUse())
20964 // Ensure that both operations have the same operands. Note that we can
20965 // commute the FADD operands.
20966 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20967 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20968 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20971 // We're looking for blends between FADD and FSUB nodes. We insist on these
20972 // nodes being lined up in a specific expected pattern.
20973 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
20974 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
20975 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
20978 // Only specific types are legal at this point, assert so we notice if and
20979 // when these change.
20980 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20981 VT == MVT::v4f64) &&
20982 "Unknown vector type encountered!");
20984 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20987 /// PerformShuffleCombine - Performs several different shuffle combines.
20988 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20989 TargetLowering::DAGCombinerInfo &DCI,
20990 const X86Subtarget *Subtarget) {
20992 SDValue N0 = N->getOperand(0);
20993 SDValue N1 = N->getOperand(1);
20994 EVT VT = N->getValueType(0);
20996 // Don't create instructions with illegal types after legalize types has run.
20997 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20998 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21001 // If we have legalized the vector types, look for blends of FADD and FSUB
21002 // nodes that we can fuse into an ADDSUB node.
21003 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21004 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21007 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21008 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21009 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21010 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21012 // During Type Legalization, when promoting illegal vector types,
21013 // the backend might introduce new shuffle dag nodes and bitcasts.
21015 // This code performs the following transformation:
21016 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21017 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21019 // We do this only if both the bitcast and the BINOP dag nodes have
21020 // one use. Also, perform this transformation only if the new binary
21021 // operation is legal. This is to avoid introducing dag nodes that
21022 // potentially need to be further expanded (or custom lowered) into a
21023 // less optimal sequence of dag nodes.
21024 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21025 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21026 N0.getOpcode() == ISD::BITCAST) {
21027 SDValue BC0 = N0.getOperand(0);
21028 EVT SVT = BC0.getValueType();
21029 unsigned Opcode = BC0.getOpcode();
21030 unsigned NumElts = VT.getVectorNumElements();
21032 if (BC0.hasOneUse() && SVT.isVector() &&
21033 SVT.getVectorNumElements() * 2 == NumElts &&
21034 TLI.isOperationLegal(Opcode, VT)) {
21035 bool CanFold = false;
21047 unsigned SVTNumElts = SVT.getVectorNumElements();
21048 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21049 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21050 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21051 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21052 CanFold = SVOp->getMaskElt(i) < 0;
21055 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
21056 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
21057 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21058 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21063 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21064 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21065 // consecutive, non-overlapping, and in the right order.
21066 SmallVector<SDValue, 16> Elts;
21067 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21068 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21070 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21074 if (isTargetShuffle(N->getOpcode())) {
21076 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21077 if (Shuffle.getNode())
21080 // Try recursively combining arbitrary sequences of x86 shuffle
21081 // instructions into higher-order shuffles. We do this after combining
21082 // specific PSHUF instruction sequences into their minimal form so that we
21083 // can evaluate how many specialized shuffle instructions are involved in
21084 // a particular chain.
21085 SmallVector<int, 1> NonceMask; // Just a placeholder.
21086 NonceMask.push_back(0);
21087 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21088 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21090 return SDValue(); // This routine will use CombineTo to replace N.
21096 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21097 /// specific shuffle of a load can be folded into a single element load.
21098 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21099 /// shuffles have been custom lowered so we need to handle those here.
21100 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21101 TargetLowering::DAGCombinerInfo &DCI) {
21102 if (DCI.isBeforeLegalizeOps())
21105 SDValue InVec = N->getOperand(0);
21106 SDValue EltNo = N->getOperand(1);
21108 if (!isa<ConstantSDNode>(EltNo))
21111 EVT OriginalVT = InVec.getValueType();
21113 if (InVec.getOpcode() == ISD::BITCAST) {
21114 // Don't duplicate a load with other uses.
21115 if (!InVec.hasOneUse())
21117 EVT BCVT = InVec.getOperand(0).getValueType();
21118 if (!BCVT.isVector() ||
21119 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
21121 InVec = InVec.getOperand(0);
21124 EVT CurrentVT = InVec.getValueType();
21126 if (!isTargetShuffle(InVec.getOpcode()))
21129 // Don't duplicate a load with other uses.
21130 if (!InVec.hasOneUse())
21133 SmallVector<int, 16> ShuffleMask;
21135 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
21136 ShuffleMask, UnaryShuffle))
21139 // Select the input vector, guarding against out of range extract vector.
21140 unsigned NumElems = CurrentVT.getVectorNumElements();
21141 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21142 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21143 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21144 : InVec.getOperand(1);
21146 // If inputs to shuffle are the same for both ops, then allow 2 uses
21147 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
21148 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21150 if (LdNode.getOpcode() == ISD::BITCAST) {
21151 // Don't duplicate a load with other uses.
21152 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21155 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21156 LdNode = LdNode.getOperand(0);
21159 if (!ISD::isNormalLoad(LdNode.getNode()))
21162 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21164 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21167 EVT EltVT = N->getValueType(0);
21168 // If there's a bitcast before the shuffle, check if the load type and
21169 // alignment is valid.
21170 unsigned Align = LN0->getAlignment();
21171 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21172 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21173 EltVT.getTypeForEVT(*DAG.getContext()));
21175 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21178 // All checks match so transform back to vector_shuffle so that DAG combiner
21179 // can finish the job
21182 // Create shuffle node taking into account the case that its a unary shuffle
21183 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
21184 : InVec.getOperand(1);
21185 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
21186 InVec.getOperand(0), Shuffle,
21188 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
21189 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21193 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
21194 /// special and don't usually play with other vector types, it's better to
21195 /// handle them early to be sure we emit efficient code by avoiding
21196 /// store-load conversions.
21197 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
21198 if (N->getValueType(0) != MVT::x86mmx ||
21199 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
21200 N->getOperand(0)->getValueType(0) != MVT::v2i32)
21203 SDValue V = N->getOperand(0);
21204 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
21205 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
21206 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
21207 N->getValueType(0), V.getOperand(0));
21212 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21213 /// generation and convert it from being a bunch of shuffles and extracts
21214 /// into a somewhat faster sequence. For i686, the best sequence is apparently
21215 /// storing the value and loading scalars back, while for x64 we should
21216 /// use 64-bit extracts and shifts.
21217 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21218 TargetLowering::DAGCombinerInfo &DCI) {
21219 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21220 if (NewOp.getNode())
21223 SDValue InputVector = N->getOperand(0);
21224 SDLoc dl(InputVector);
21225 // Detect mmx to i32 conversion through a v2i32 elt extract.
21226 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
21227 N->getValueType(0) == MVT::i32 &&
21228 InputVector.getValueType() == MVT::v2i32) {
21230 // The bitcast source is a direct mmx result.
21231 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
21232 if (MMXSrc.getValueType() == MVT::x86mmx)
21233 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21234 N->getValueType(0),
21235 InputVector.getNode()->getOperand(0));
21237 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
21238 SDValue MMXSrcOp = MMXSrc.getOperand(0);
21239 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
21240 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
21241 MMXSrcOp.getOpcode() == ISD::BITCAST &&
21242 MMXSrcOp.getValueType() == MVT::v1i64 &&
21243 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
21244 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21245 N->getValueType(0),
21246 MMXSrcOp.getOperand(0));
21249 EVT VT = N->getValueType(0);
21251 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
21252 InputVector.getOpcode() == ISD::BITCAST &&
21253 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
21254 uint64_t ExtractedElt =
21255 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
21256 uint64_t InputValue =
21257 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
21258 uint64_t Res = (InputValue >> ExtractedElt) & 1;
21259 return DAG.getConstant(Res, dl, MVT::i1);
21261 // Only operate on vectors of 4 elements, where the alternative shuffling
21262 // gets to be more expensive.
21263 if (InputVector.getValueType() != MVT::v4i32)
21266 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21267 // single use which is a sign-extend or zero-extend, and all elements are
21269 SmallVector<SDNode *, 4> Uses;
21270 unsigned ExtractedElements = 0;
21271 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21272 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21273 if (UI.getUse().getResNo() != InputVector.getResNo())
21276 SDNode *Extract = *UI;
21277 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21280 if (Extract->getValueType(0) != MVT::i32)
21282 if (!Extract->hasOneUse())
21284 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21285 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21287 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21290 // Record which element was extracted.
21291 ExtractedElements |=
21292 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21294 Uses.push_back(Extract);
21297 // If not all the elements were used, this may not be worthwhile.
21298 if (ExtractedElements != 15)
21301 // Ok, we've now decided to do the transformation.
21302 // If 64-bit shifts are legal, use the extract-shift sequence,
21303 // otherwise bounce the vector off the cache.
21304 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21307 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
21308 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
21309 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
21310 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21311 DAG.getConstant(0, dl, VecIdxTy));
21312 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21313 DAG.getConstant(1, dl, VecIdxTy));
21315 SDValue ShAmt = DAG.getConstant(32, dl,
21316 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
21317 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
21318 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21319 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
21320 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
21321 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21322 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
21324 // Store the value to a temporary stack slot.
21325 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21326 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21327 MachinePointerInfo(), false, false, 0);
21329 EVT ElementType = InputVector.getValueType().getVectorElementType();
21330 unsigned EltSize = ElementType.getSizeInBits() / 8;
21332 // Replace each use (extract) with a load of the appropriate element.
21333 for (unsigned i = 0; i < 4; ++i) {
21334 uint64_t Offset = EltSize * i;
21335 SDValue OffsetVal = DAG.getConstant(Offset, dl, TLI.getPointerTy());
21337 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21338 StackPtr, OffsetVal);
21340 // Load the scalar.
21341 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
21342 ScalarAddr, MachinePointerInfo(),
21343 false, false, false, 0);
21348 // Replace the extracts
21349 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21350 UE = Uses.end(); UI != UE; ++UI) {
21351 SDNode *Extract = *UI;
21353 SDValue Idx = Extract->getOperand(1);
21354 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
21355 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
21358 // The replacement was made in place; don't return anything.
21362 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21363 static std::pair<unsigned, bool>
21364 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21365 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21366 if (!VT.isVector())
21367 return std::make_pair(0, false);
21369 bool NeedSplit = false;
21370 switch (VT.getSimpleVT().SimpleTy) {
21371 default: return std::make_pair(0, false);
21374 if (!Subtarget->hasVLX())
21375 return std::make_pair(0, false);
21379 if (!Subtarget->hasBWI())
21380 return std::make_pair(0, false);
21384 if (!Subtarget->hasAVX512())
21385 return std::make_pair(0, false);
21390 if (!Subtarget->hasAVX2())
21392 if (!Subtarget->hasAVX())
21393 return std::make_pair(0, false);
21398 if (!Subtarget->hasSSE2())
21399 return std::make_pair(0, false);
21402 // SSE2 has only a small subset of the operations.
21403 bool hasUnsigned = Subtarget->hasSSE41() ||
21404 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21405 bool hasSigned = Subtarget->hasSSE41() ||
21406 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21408 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21411 // Check for x CC y ? x : y.
21412 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21413 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21418 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21421 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21424 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21427 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21429 // Check for x CC y ? y : x -- a min/max with reversed arms.
21430 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21431 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21436 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21439 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21442 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21445 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21449 return std::make_pair(Opc, NeedSplit);
21453 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21454 const X86Subtarget *Subtarget) {
21456 SDValue Cond = N->getOperand(0);
21457 SDValue LHS = N->getOperand(1);
21458 SDValue RHS = N->getOperand(2);
21460 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21461 SDValue CondSrc = Cond->getOperand(0);
21462 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21463 Cond = CondSrc->getOperand(0);
21466 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21469 // A vselect where all conditions and data are constants can be optimized into
21470 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21471 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21472 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21475 unsigned MaskValue = 0;
21476 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21479 MVT VT = N->getSimpleValueType(0);
21480 unsigned NumElems = VT.getVectorNumElements();
21481 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21482 for (unsigned i = 0; i < NumElems; ++i) {
21483 // Be sure we emit undef where we can.
21484 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21485 ShuffleMask[i] = -1;
21487 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21490 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21491 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
21493 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21496 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21498 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21499 TargetLowering::DAGCombinerInfo &DCI,
21500 const X86Subtarget *Subtarget) {
21502 SDValue Cond = N->getOperand(0);
21503 // Get the LHS/RHS of the select.
21504 SDValue LHS = N->getOperand(1);
21505 SDValue RHS = N->getOperand(2);
21506 EVT VT = LHS.getValueType();
21507 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21509 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21510 // instructions match the semantics of the common C idiom x<y?x:y but not
21511 // x<=y?x:y, because of how they handle negative zero (which can be
21512 // ignored in unsafe-math mode).
21513 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
21514 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21515 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
21516 (Subtarget->hasSSE2() ||
21517 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21518 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21520 unsigned Opcode = 0;
21521 // Check for x CC y ? x : y.
21522 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21523 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21527 // Converting this to a min would handle NaNs incorrectly, and swapping
21528 // the operands would cause it to handle comparisons between positive
21529 // and negative zero incorrectly.
21530 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21531 if (!DAG.getTarget().Options.UnsafeFPMath &&
21532 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21534 std::swap(LHS, RHS);
21536 Opcode = X86ISD::FMIN;
21539 // Converting this to a min would handle comparisons between positive
21540 // and negative zero incorrectly.
21541 if (!DAG.getTarget().Options.UnsafeFPMath &&
21542 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21544 Opcode = X86ISD::FMIN;
21547 // Converting this to a min would handle both negative zeros and NaNs
21548 // incorrectly, but we can swap the operands to fix both.
21549 std::swap(LHS, RHS);
21553 Opcode = X86ISD::FMIN;
21557 // Converting this to a max would handle comparisons between positive
21558 // and negative zero incorrectly.
21559 if (!DAG.getTarget().Options.UnsafeFPMath &&
21560 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21562 Opcode = X86ISD::FMAX;
21565 // Converting this to a max would handle NaNs incorrectly, and swapping
21566 // the operands would cause it to handle comparisons between positive
21567 // and negative zero incorrectly.
21568 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21569 if (!DAG.getTarget().Options.UnsafeFPMath &&
21570 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21572 std::swap(LHS, RHS);
21574 Opcode = X86ISD::FMAX;
21577 // Converting this to a max would handle both negative zeros and NaNs
21578 // incorrectly, but we can swap the operands to fix both.
21579 std::swap(LHS, RHS);
21583 Opcode = X86ISD::FMAX;
21586 // Check for x CC y ? y : x -- a min/max with reversed arms.
21587 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21588 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21592 // Converting this to a min would handle comparisons between positive
21593 // and negative zero incorrectly, and swapping the operands would
21594 // cause it to handle NaNs incorrectly.
21595 if (!DAG.getTarget().Options.UnsafeFPMath &&
21596 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21597 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21599 std::swap(LHS, RHS);
21601 Opcode = X86ISD::FMIN;
21604 // Converting this to a min would handle NaNs incorrectly.
21605 if (!DAG.getTarget().Options.UnsafeFPMath &&
21606 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21608 Opcode = X86ISD::FMIN;
21611 // Converting this to a min would handle both negative zeros and NaNs
21612 // incorrectly, but we can swap the operands to fix both.
21613 std::swap(LHS, RHS);
21617 Opcode = X86ISD::FMIN;
21621 // Converting this to a max would handle NaNs incorrectly.
21622 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21624 Opcode = X86ISD::FMAX;
21627 // Converting this to a max would handle comparisons between positive
21628 // and negative zero incorrectly, and swapping the operands would
21629 // cause it to handle NaNs incorrectly.
21630 if (!DAG.getTarget().Options.UnsafeFPMath &&
21631 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21632 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21634 std::swap(LHS, RHS);
21636 Opcode = X86ISD::FMAX;
21639 // Converting this to a max would handle both negative zeros and NaNs
21640 // incorrectly, but we can swap the operands to fix both.
21641 std::swap(LHS, RHS);
21645 Opcode = X86ISD::FMAX;
21651 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21654 EVT CondVT = Cond.getValueType();
21655 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21656 CondVT.getVectorElementType() == MVT::i1) {
21657 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21658 // lowering on KNL. In this case we convert it to
21659 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21660 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21661 // Since SKX these selects have a proper lowering.
21662 EVT OpVT = LHS.getValueType();
21663 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21664 (OpVT.getVectorElementType() == MVT::i8 ||
21665 OpVT.getVectorElementType() == MVT::i16) &&
21666 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21667 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21668 DCI.AddToWorklist(Cond.getNode());
21669 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21672 // If this is a select between two integer constants, try to do some
21674 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21675 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21676 // Don't do this for crazy integer types.
21677 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21678 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21679 // so that TrueC (the true value) is larger than FalseC.
21680 bool NeedsCondInvert = false;
21682 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21683 // Efficiently invertible.
21684 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21685 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21686 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21687 NeedsCondInvert = true;
21688 std::swap(TrueC, FalseC);
21691 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21692 if (FalseC->getAPIntValue() == 0 &&
21693 TrueC->getAPIntValue().isPowerOf2()) {
21694 if (NeedsCondInvert) // Invert the condition if needed.
21695 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21696 DAG.getConstant(1, DL, Cond.getValueType()));
21698 // Zero extend the condition if needed.
21699 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21701 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21702 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21703 DAG.getConstant(ShAmt, DL, MVT::i8));
21706 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21707 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21708 if (NeedsCondInvert) // Invert the condition if needed.
21709 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21710 DAG.getConstant(1, DL, Cond.getValueType()));
21712 // Zero extend the condition if needed.
21713 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21714 FalseC->getValueType(0), Cond);
21715 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21716 SDValue(FalseC, 0));
21719 // Optimize cases that will turn into an LEA instruction. This requires
21720 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21721 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21722 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21723 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21725 bool isFastMultiplier = false;
21727 switch ((unsigned char)Diff) {
21729 case 1: // result = add base, cond
21730 case 2: // result = lea base( , cond*2)
21731 case 3: // result = lea base(cond, cond*2)
21732 case 4: // result = lea base( , cond*4)
21733 case 5: // result = lea base(cond, cond*4)
21734 case 8: // result = lea base( , cond*8)
21735 case 9: // result = lea base(cond, cond*8)
21736 isFastMultiplier = true;
21741 if (isFastMultiplier) {
21742 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21743 if (NeedsCondInvert) // Invert the condition if needed.
21744 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21745 DAG.getConstant(1, DL, Cond.getValueType()));
21747 // Zero extend the condition if needed.
21748 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21750 // Scale the condition by the difference.
21752 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21753 DAG.getConstant(Diff, DL,
21754 Cond.getValueType()));
21756 // Add the base if non-zero.
21757 if (FalseC->getAPIntValue() != 0)
21758 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21759 SDValue(FalseC, 0));
21766 // Canonicalize max and min:
21767 // (x > y) ? x : y -> (x >= y) ? x : y
21768 // (x < y) ? x : y -> (x <= y) ? x : y
21769 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21770 // the need for an extra compare
21771 // against zero. e.g.
21772 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21774 // testl %edi, %edi
21776 // cmovgl %edi, %eax
21780 // cmovsl %eax, %edi
21781 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21782 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21783 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21784 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21789 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21790 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21791 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21792 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21797 // Early exit check
21798 if (!TLI.isTypeLegal(VT))
21801 // Match VSELECTs into subs with unsigned saturation.
21802 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21803 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21804 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21805 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21806 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21808 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21809 // left side invert the predicate to simplify logic below.
21811 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21813 CC = ISD::getSetCCInverse(CC, true);
21814 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21818 if (Other.getNode() && Other->getNumOperands() == 2 &&
21819 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21820 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21821 SDValue CondRHS = Cond->getOperand(1);
21823 // Look for a general sub with unsigned saturation first.
21824 // x >= y ? x-y : 0 --> subus x, y
21825 // x > y ? x-y : 0 --> subus x, y
21826 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21827 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21828 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21830 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21831 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21832 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21833 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21834 // If the RHS is a constant we have to reverse the const
21835 // canonicalization.
21836 // x > C-1 ? x+-C : 0 --> subus x, C
21837 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21838 CondRHSConst->getAPIntValue() ==
21839 (-OpRHSConst->getAPIntValue() - 1))
21840 return DAG.getNode(
21841 X86ISD::SUBUS, DL, VT, OpLHS,
21842 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
21844 // Another special case: If C was a sign bit, the sub has been
21845 // canonicalized into a xor.
21846 // FIXME: Would it be better to use computeKnownBits to determine
21847 // whether it's safe to decanonicalize the xor?
21848 // x s< 0 ? x^C : 0 --> subus x, C
21849 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21850 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21851 OpRHSConst->getAPIntValue().isSignBit())
21852 // Note that we have to rebuild the RHS constant here to ensure we
21853 // don't rely on particular values of undef lanes.
21854 return DAG.getNode(
21855 X86ISD::SUBUS, DL, VT, OpLHS,
21856 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
21861 // Try to match a min/max vector operation.
21862 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21863 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21864 unsigned Opc = ret.first;
21865 bool NeedSplit = ret.second;
21867 if (Opc && NeedSplit) {
21868 unsigned NumElems = VT.getVectorNumElements();
21869 // Extract the LHS vectors
21870 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21871 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21873 // Extract the RHS vectors
21874 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21875 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21877 // Create min/max for each subvector
21878 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21879 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21881 // Merge the result
21882 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21884 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21887 // Simplify vector selection if condition value type matches vselect
21889 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
21890 assert(Cond.getValueType().isVector() &&
21891 "vector select expects a vector selector!");
21893 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21894 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21896 // Try invert the condition if true value is not all 1s and false value
21898 if (!TValIsAllOnes && !FValIsAllZeros &&
21899 // Check if the selector will be produced by CMPP*/PCMP*
21900 Cond.getOpcode() == ISD::SETCC &&
21901 // Check if SETCC has already been promoted
21902 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
21903 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21904 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21906 if (TValIsAllZeros || FValIsAllOnes) {
21907 SDValue CC = Cond.getOperand(2);
21908 ISD::CondCode NewCC =
21909 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21910 Cond.getOperand(0).getValueType().isInteger());
21911 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21912 std::swap(LHS, RHS);
21913 TValIsAllOnes = FValIsAllOnes;
21914 FValIsAllZeros = TValIsAllZeros;
21918 if (TValIsAllOnes || FValIsAllZeros) {
21921 if (TValIsAllOnes && FValIsAllZeros)
21923 else if (TValIsAllOnes)
21925 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
21926 else if (FValIsAllZeros)
21927 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21928 DAG.getBitcast(CondVT, LHS));
21930 return DAG.getBitcast(VT, Ret);
21934 // We should generate an X86ISD::BLENDI from a vselect if its argument
21935 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21936 // constants. This specific pattern gets generated when we split a
21937 // selector for a 512 bit vector in a machine without AVX512 (but with
21938 // 256-bit vectors), during legalization:
21940 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21942 // Iff we find this pattern and the build_vectors are built from
21943 // constants, we translate the vselect into a shuffle_vector that we
21944 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21945 if ((N->getOpcode() == ISD::VSELECT ||
21946 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
21947 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
21948 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21949 if (Shuffle.getNode())
21953 // If this is a *dynamic* select (non-constant condition) and we can match
21954 // this node with one of the variable blend instructions, restructure the
21955 // condition so that the blends can use the high bit of each element and use
21956 // SimplifyDemandedBits to simplify the condition operand.
21957 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21958 !DCI.isBeforeLegalize() &&
21959 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
21960 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21962 // Don't optimize vector selects that map to mask-registers.
21966 // We can only handle the cases where VSELECT is directly legal on the
21967 // subtarget. We custom lower VSELECT nodes with constant conditions and
21968 // this makes it hard to see whether a dynamic VSELECT will correctly
21969 // lower, so we both check the operation's status and explicitly handle the
21970 // cases where a *dynamic* blend will fail even though a constant-condition
21971 // blend could be custom lowered.
21972 // FIXME: We should find a better way to handle this class of problems.
21973 // Potentially, we should combine constant-condition vselect nodes
21974 // pre-legalization into shuffles and not mark as many types as custom
21976 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
21978 // FIXME: We don't support i16-element blends currently. We could and
21979 // should support them by making *all* the bits in the condition be set
21980 // rather than just the high bit and using an i8-element blend.
21981 if (VT.getScalarType() == MVT::i16)
21983 // Dynamic blending was only available from SSE4.1 onward.
21984 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
21986 // Byte blends are only available in AVX2
21987 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
21988 !Subtarget->hasAVX2())
21991 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21992 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21994 APInt KnownZero, KnownOne;
21995 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21996 DCI.isBeforeLegalizeOps());
21997 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21998 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
22000 // If we changed the computation somewhere in the DAG, this change
22001 // will affect all users of Cond.
22002 // Make sure it is fine and update all the nodes so that we do not
22003 // use the generic VSELECT anymore. Otherwise, we may perform
22004 // wrong optimizations as we messed up with the actual expectation
22005 // for the vector boolean values.
22006 if (Cond != TLO.Old) {
22007 // Check all uses of that condition operand to check whether it will be
22008 // consumed by non-BLEND instructions, which may depend on all bits are
22010 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22012 if (I->getOpcode() != ISD::VSELECT)
22013 // TODO: Add other opcodes eventually lowered into BLEND.
22016 // Update all the users of the condition, before committing the change,
22017 // so that the VSELECT optimizations that expect the correct vector
22018 // boolean value will not be triggered.
22019 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22021 DAG.ReplaceAllUsesOfValueWith(
22023 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
22024 Cond, I->getOperand(1), I->getOperand(2)));
22025 DCI.CommitTargetLoweringOpt(TLO);
22028 // At this point, only Cond is changed. Change the condition
22029 // just for N to keep the opportunity to optimize all other
22030 // users their own way.
22031 DAG.ReplaceAllUsesOfValueWith(
22033 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
22034 TLO.New, N->getOperand(1), N->getOperand(2)));
22042 // Check whether a boolean test is testing a boolean value generated by
22043 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22046 // Simplify the following patterns:
22047 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22048 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22049 // to (Op EFLAGS Cond)
22051 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22052 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22053 // to (Op EFLAGS !Cond)
22055 // where Op could be BRCOND or CMOV.
22057 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22058 // Quit if not CMP and SUB with its value result used.
22059 if (Cmp.getOpcode() != X86ISD::CMP &&
22060 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22063 // Quit if not used as a boolean value.
22064 if (CC != X86::COND_E && CC != X86::COND_NE)
22067 // Check CMP operands. One of them should be 0 or 1 and the other should be
22068 // an SetCC or extended from it.
22069 SDValue Op1 = Cmp.getOperand(0);
22070 SDValue Op2 = Cmp.getOperand(1);
22073 const ConstantSDNode* C = nullptr;
22074 bool needOppositeCond = (CC == X86::COND_E);
22075 bool checkAgainstTrue = false; // Is it a comparison against 1?
22077 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22079 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22081 else // Quit if all operands are not constants.
22084 if (C->getZExtValue() == 1) {
22085 needOppositeCond = !needOppositeCond;
22086 checkAgainstTrue = true;
22087 } else if (C->getZExtValue() != 0)
22088 // Quit if the constant is neither 0 or 1.
22091 bool truncatedToBoolWithAnd = false;
22092 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22093 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22094 SetCC.getOpcode() == ISD::TRUNCATE ||
22095 SetCC.getOpcode() == ISD::AND) {
22096 if (SetCC.getOpcode() == ISD::AND) {
22098 ConstantSDNode *CS;
22099 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22100 CS->getZExtValue() == 1)
22102 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22103 CS->getZExtValue() == 1)
22107 SetCC = SetCC.getOperand(OpIdx);
22108 truncatedToBoolWithAnd = true;
22110 SetCC = SetCC.getOperand(0);
22113 switch (SetCC.getOpcode()) {
22114 case X86ISD::SETCC_CARRY:
22115 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22116 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22117 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22118 // truncated to i1 using 'and'.
22119 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22121 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22122 "Invalid use of SETCC_CARRY!");
22124 case X86ISD::SETCC:
22125 // Set the condition code or opposite one if necessary.
22126 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22127 if (needOppositeCond)
22128 CC = X86::GetOppositeBranchCondition(CC);
22129 return SetCC.getOperand(1);
22130 case X86ISD::CMOV: {
22131 // Check whether false/true value has canonical one, i.e. 0 or 1.
22132 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22133 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22134 // Quit if true value is not a constant.
22137 // Quit if false value is not a constant.
22139 SDValue Op = SetCC.getOperand(0);
22140 // Skip 'zext' or 'trunc' node.
22141 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22142 Op.getOpcode() == ISD::TRUNCATE)
22143 Op = Op.getOperand(0);
22144 // A special case for rdrand/rdseed, where 0 is set if false cond is
22146 if ((Op.getOpcode() != X86ISD::RDRAND &&
22147 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22150 // Quit if false value is not the constant 0 or 1.
22151 bool FValIsFalse = true;
22152 if (FVal && FVal->getZExtValue() != 0) {
22153 if (FVal->getZExtValue() != 1)
22155 // If FVal is 1, opposite cond is needed.
22156 needOppositeCond = !needOppositeCond;
22157 FValIsFalse = false;
22159 // Quit if TVal is not the constant opposite of FVal.
22160 if (FValIsFalse && TVal->getZExtValue() != 1)
22162 if (!FValIsFalse && TVal->getZExtValue() != 0)
22164 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22165 if (needOppositeCond)
22166 CC = X86::GetOppositeBranchCondition(CC);
22167 return SetCC.getOperand(3);
22174 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
22176 /// (X86or (X86setcc) (X86setcc))
22177 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
22178 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
22179 X86::CondCode &CC1, SDValue &Flags,
22181 if (Cond->getOpcode() == X86ISD::CMP) {
22182 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
22183 if (!CondOp1C || !CondOp1C->isNullValue())
22186 Cond = Cond->getOperand(0);
22191 SDValue SetCC0, SetCC1;
22192 switch (Cond->getOpcode()) {
22193 default: return false;
22200 SetCC0 = Cond->getOperand(0);
22201 SetCC1 = Cond->getOperand(1);
22205 // Make sure we have SETCC nodes, using the same flags value.
22206 if (SetCC0.getOpcode() != X86ISD::SETCC ||
22207 SetCC1.getOpcode() != X86ISD::SETCC ||
22208 SetCC0->getOperand(1) != SetCC1->getOperand(1))
22211 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
22212 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
22213 Flags = SetCC0->getOperand(1);
22217 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22218 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22219 TargetLowering::DAGCombinerInfo &DCI,
22220 const X86Subtarget *Subtarget) {
22223 // If the flag operand isn't dead, don't touch this CMOV.
22224 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22227 SDValue FalseOp = N->getOperand(0);
22228 SDValue TrueOp = N->getOperand(1);
22229 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22230 SDValue Cond = N->getOperand(3);
22232 if (CC == X86::COND_E || CC == X86::COND_NE) {
22233 switch (Cond.getOpcode()) {
22237 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22238 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22239 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22245 Flags = checkBoolTestSetCCCombine(Cond, CC);
22246 if (Flags.getNode() &&
22247 // Extra check as FCMOV only supports a subset of X86 cond.
22248 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22249 SDValue Ops[] = { FalseOp, TrueOp,
22250 DAG.getConstant(CC, DL, MVT::i8), Flags };
22251 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22254 // If this is a select between two integer constants, try to do some
22255 // optimizations. Note that the operands are ordered the opposite of SELECT
22257 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22258 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22259 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22260 // larger than FalseC (the false value).
22261 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22262 CC = X86::GetOppositeBranchCondition(CC);
22263 std::swap(TrueC, FalseC);
22264 std::swap(TrueOp, FalseOp);
22267 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22268 // This is efficient for any integer data type (including i8/i16) and
22270 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22271 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22272 DAG.getConstant(CC, DL, MVT::i8), Cond);
22274 // Zero extend the condition if needed.
22275 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22277 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22278 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22279 DAG.getConstant(ShAmt, DL, MVT::i8));
22280 if (N->getNumValues() == 2) // Dead flag value?
22281 return DCI.CombineTo(N, Cond, SDValue());
22285 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22286 // for any integer data type, including i8/i16.
22287 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22288 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22289 DAG.getConstant(CC, DL, MVT::i8), Cond);
22291 // Zero extend the condition if needed.
22292 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22293 FalseC->getValueType(0), Cond);
22294 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22295 SDValue(FalseC, 0));
22297 if (N->getNumValues() == 2) // Dead flag value?
22298 return DCI.CombineTo(N, Cond, SDValue());
22302 // Optimize cases that will turn into an LEA instruction. This requires
22303 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22304 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22305 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22306 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22308 bool isFastMultiplier = false;
22310 switch ((unsigned char)Diff) {
22312 case 1: // result = add base, cond
22313 case 2: // result = lea base( , cond*2)
22314 case 3: // result = lea base(cond, cond*2)
22315 case 4: // result = lea base( , cond*4)
22316 case 5: // result = lea base(cond, cond*4)
22317 case 8: // result = lea base( , cond*8)
22318 case 9: // result = lea base(cond, cond*8)
22319 isFastMultiplier = true;
22324 if (isFastMultiplier) {
22325 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22326 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22327 DAG.getConstant(CC, DL, MVT::i8), Cond);
22328 // Zero extend the condition if needed.
22329 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22331 // Scale the condition by the difference.
22333 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22334 DAG.getConstant(Diff, DL, Cond.getValueType()));
22336 // Add the base if non-zero.
22337 if (FalseC->getAPIntValue() != 0)
22338 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22339 SDValue(FalseC, 0));
22340 if (N->getNumValues() == 2) // Dead flag value?
22341 return DCI.CombineTo(N, Cond, SDValue());
22348 // Handle these cases:
22349 // (select (x != c), e, c) -> select (x != c), e, x),
22350 // (select (x == c), c, e) -> select (x == c), x, e)
22351 // where the c is an integer constant, and the "select" is the combination
22352 // of CMOV and CMP.
22354 // The rationale for this change is that the conditional-move from a constant
22355 // needs two instructions, however, conditional-move from a register needs
22356 // only one instruction.
22358 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22359 // some instruction-combining opportunities. This opt needs to be
22360 // postponed as late as possible.
22362 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22363 // the DCI.xxxx conditions are provided to postpone the optimization as
22364 // late as possible.
22366 ConstantSDNode *CmpAgainst = nullptr;
22367 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22368 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22369 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22371 if (CC == X86::COND_NE &&
22372 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22373 CC = X86::GetOppositeBranchCondition(CC);
22374 std::swap(TrueOp, FalseOp);
22377 if (CC == X86::COND_E &&
22378 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22379 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22380 DAG.getConstant(CC, DL, MVT::i8), Cond };
22381 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22386 // Fold and/or of setcc's to double CMOV:
22387 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
22388 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
22390 // This combine lets us generate:
22391 // cmovcc1 (jcc1 if we don't have CMOV)
22397 // cmovne (jne if we don't have CMOV)
22398 // When we can't use the CMOV instruction, it might increase branch
22400 // When we can use CMOV, or when there is no mispredict, this improves
22401 // throughput and reduces register pressure.
22403 if (CC == X86::COND_NE) {
22405 X86::CondCode CC0, CC1;
22407 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
22409 std::swap(FalseOp, TrueOp);
22410 CC0 = X86::GetOppositeBranchCondition(CC0);
22411 CC1 = X86::GetOppositeBranchCondition(CC1);
22414 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
22416 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
22417 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
22418 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22419 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
22427 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22428 const X86Subtarget *Subtarget) {
22429 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22431 default: return SDValue();
22432 // SSE/AVX/AVX2 blend intrinsics.
22433 case Intrinsic::x86_avx2_pblendvb:
22434 // Don't try to simplify this intrinsic if we don't have AVX2.
22435 if (!Subtarget->hasAVX2())
22438 case Intrinsic::x86_avx_blendv_pd_256:
22439 case Intrinsic::x86_avx_blendv_ps_256:
22440 // Don't try to simplify this intrinsic if we don't have AVX.
22441 if (!Subtarget->hasAVX())
22444 case Intrinsic::x86_sse41_blendvps:
22445 case Intrinsic::x86_sse41_blendvpd:
22446 case Intrinsic::x86_sse41_pblendvb: {
22447 SDValue Op0 = N->getOperand(1);
22448 SDValue Op1 = N->getOperand(2);
22449 SDValue Mask = N->getOperand(3);
22451 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22452 if (!Subtarget->hasSSE41())
22455 // fold (blend A, A, Mask) -> A
22458 // fold (blend A, B, allZeros) -> A
22459 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22461 // fold (blend A, B, allOnes) -> B
22462 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22465 // Simplify the case where the mask is a constant i32 value.
22466 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22467 if (C->isNullValue())
22469 if (C->isAllOnesValue())
22476 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22477 case Intrinsic::x86_sse2_psrai_w:
22478 case Intrinsic::x86_sse2_psrai_d:
22479 case Intrinsic::x86_avx2_psrai_w:
22480 case Intrinsic::x86_avx2_psrai_d:
22481 case Intrinsic::x86_sse2_psra_w:
22482 case Intrinsic::x86_sse2_psra_d:
22483 case Intrinsic::x86_avx2_psra_w:
22484 case Intrinsic::x86_avx2_psra_d: {
22485 SDValue Op0 = N->getOperand(1);
22486 SDValue Op1 = N->getOperand(2);
22487 EVT VT = Op0.getValueType();
22488 assert(VT.isVector() && "Expected a vector type!");
22490 if (isa<BuildVectorSDNode>(Op1))
22491 Op1 = Op1.getOperand(0);
22493 if (!isa<ConstantSDNode>(Op1))
22496 EVT SVT = VT.getVectorElementType();
22497 unsigned SVTBits = SVT.getSizeInBits();
22499 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22500 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22501 uint64_t ShAmt = C.getZExtValue();
22503 // Don't try to convert this shift into a ISD::SRA if the shift
22504 // count is bigger than or equal to the element size.
22505 if (ShAmt >= SVTBits)
22508 // Trivial case: if the shift count is zero, then fold this
22509 // into the first operand.
22513 // Replace this packed shift intrinsic with a target independent
22516 SDValue Splat = DAG.getConstant(C, DL, VT);
22517 return DAG.getNode(ISD::SRA, DL, VT, Op0, Splat);
22522 /// PerformMulCombine - Optimize a single multiply with constant into two
22523 /// in order to implement it with two cheaper instructions, e.g.
22524 /// LEA + SHL, LEA + LEA.
22525 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22526 TargetLowering::DAGCombinerInfo &DCI) {
22527 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22530 EVT VT = N->getValueType(0);
22531 if (VT != MVT::i64 && VT != MVT::i32)
22534 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22537 uint64_t MulAmt = C->getZExtValue();
22538 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22541 uint64_t MulAmt1 = 0;
22542 uint64_t MulAmt2 = 0;
22543 if ((MulAmt % 9) == 0) {
22545 MulAmt2 = MulAmt / 9;
22546 } else if ((MulAmt % 5) == 0) {
22548 MulAmt2 = MulAmt / 5;
22549 } else if ((MulAmt % 3) == 0) {
22551 MulAmt2 = MulAmt / 3;
22554 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22557 if (isPowerOf2_64(MulAmt2) &&
22558 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22559 // If second multiplifer is pow2, issue it first. We want the multiply by
22560 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22562 std::swap(MulAmt1, MulAmt2);
22565 if (isPowerOf2_64(MulAmt1))
22566 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22567 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
22569 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22570 DAG.getConstant(MulAmt1, DL, VT));
22572 if (isPowerOf2_64(MulAmt2))
22573 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22574 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
22576 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22577 DAG.getConstant(MulAmt2, DL, VT));
22579 // Do not add new nodes to DAG combiner worklist.
22580 DCI.CombineTo(N, NewMul, false);
22585 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22586 SDValue N0 = N->getOperand(0);
22587 SDValue N1 = N->getOperand(1);
22588 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22589 EVT VT = N0.getValueType();
22591 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22592 // since the result of setcc_c is all zero's or all ones.
22593 if (VT.isInteger() && !VT.isVector() &&
22594 N1C && N0.getOpcode() == ISD::AND &&
22595 N0.getOperand(1).getOpcode() == ISD::Constant) {
22596 SDValue N00 = N0.getOperand(0);
22597 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22598 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22599 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22600 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22601 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22602 APInt ShAmt = N1C->getAPIntValue();
22603 Mask = Mask.shl(ShAmt);
22606 return DAG.getNode(ISD::AND, DL, VT,
22607 N00, DAG.getConstant(Mask, DL, VT));
22612 // Hardware support for vector shifts is sparse which makes us scalarize the
22613 // vector operations in many cases. Also, on sandybridge ADD is faster than
22615 // (shl V, 1) -> add V,V
22616 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22617 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22618 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22619 // We shift all of the values by one. In many cases we do not have
22620 // hardware support for this operation. This is better expressed as an ADD
22622 if (N1SplatC->getZExtValue() == 1)
22623 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22629 /// \brief Returns a vector of 0s if the node in input is a vector logical
22630 /// shift by a constant amount which is known to be bigger than or equal
22631 /// to the vector element size in bits.
22632 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22633 const X86Subtarget *Subtarget) {
22634 EVT VT = N->getValueType(0);
22636 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22637 (!Subtarget->hasInt256() ||
22638 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22641 SDValue Amt = N->getOperand(1);
22643 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22644 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22645 APInt ShiftAmt = AmtSplat->getAPIntValue();
22646 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22648 // SSE2/AVX2 logical shifts always return a vector of 0s
22649 // if the shift amount is bigger than or equal to
22650 // the element size. The constant shift amount will be
22651 // encoded as a 8-bit immediate.
22652 if (ShiftAmt.trunc(8).uge(MaxAmount))
22653 return getZeroVector(VT, Subtarget, DAG, DL);
22659 /// PerformShiftCombine - Combine shifts.
22660 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22661 TargetLowering::DAGCombinerInfo &DCI,
22662 const X86Subtarget *Subtarget) {
22663 if (N->getOpcode() == ISD::SHL) {
22664 SDValue V = PerformSHLCombine(N, DAG);
22665 if (V.getNode()) return V;
22668 if (N->getOpcode() != ISD::SRA) {
22669 // Try to fold this logical shift into a zero vector.
22670 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22671 if (V.getNode()) return V;
22677 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22678 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22679 // and friends. Likewise for OR -> CMPNEQSS.
22680 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22681 TargetLowering::DAGCombinerInfo &DCI,
22682 const X86Subtarget *Subtarget) {
22685 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22686 // we're requiring SSE2 for both.
22687 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22688 SDValue N0 = N->getOperand(0);
22689 SDValue N1 = N->getOperand(1);
22690 SDValue CMP0 = N0->getOperand(1);
22691 SDValue CMP1 = N1->getOperand(1);
22694 // The SETCCs should both refer to the same CMP.
22695 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22698 SDValue CMP00 = CMP0->getOperand(0);
22699 SDValue CMP01 = CMP0->getOperand(1);
22700 EVT VT = CMP00.getValueType();
22702 if (VT == MVT::f32 || VT == MVT::f64) {
22703 bool ExpectingFlags = false;
22704 // Check for any users that want flags:
22705 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22706 !ExpectingFlags && UI != UE; ++UI)
22707 switch (UI->getOpcode()) {
22712 ExpectingFlags = true;
22714 case ISD::CopyToReg:
22715 case ISD::SIGN_EXTEND:
22716 case ISD::ZERO_EXTEND:
22717 case ISD::ANY_EXTEND:
22721 if (!ExpectingFlags) {
22722 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22723 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22725 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22726 X86::CondCode tmp = cc0;
22731 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22732 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22733 // FIXME: need symbolic constants for these magic numbers.
22734 // See X86ATTInstPrinter.cpp:printSSECC().
22735 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22736 if (Subtarget->hasAVX512()) {
22737 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22739 DAG.getConstant(x86cc, DL, MVT::i8));
22740 if (N->getValueType(0) != MVT::i1)
22741 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22745 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22746 CMP00.getValueType(), CMP00, CMP01,
22747 DAG.getConstant(x86cc, DL,
22750 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22751 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22753 if (is64BitFP && !Subtarget->is64Bit()) {
22754 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22755 // 64-bit integer, since that's not a legal type. Since
22756 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22757 // bits, but can do this little dance to extract the lowest 32 bits
22758 // and work with those going forward.
22759 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22761 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
22762 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22763 Vector32, DAG.getIntPtrConstant(0, DL));
22767 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
22768 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22769 DAG.getConstant(1, DL, IntVT));
22770 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
22772 return OneBitOfTruth;
22780 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22781 /// so it can be folded inside ANDNP.
22782 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22783 EVT VT = N->getValueType(0);
22785 // Match direct AllOnes for 128 and 256-bit vectors
22786 if (ISD::isBuildVectorAllOnes(N))
22789 // Look through a bit convert.
22790 if (N->getOpcode() == ISD::BITCAST)
22791 N = N->getOperand(0).getNode();
22793 // Sometimes the operand may come from a insert_subvector building a 256-bit
22795 if (VT.is256BitVector() &&
22796 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22797 SDValue V1 = N->getOperand(0);
22798 SDValue V2 = N->getOperand(1);
22800 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22801 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22802 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22803 ISD::isBuildVectorAllOnes(V2.getNode()))
22810 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22811 // register. In most cases we actually compare or select YMM-sized registers
22812 // and mixing the two types creates horrible code. This method optimizes
22813 // some of the transition sequences.
22814 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22815 TargetLowering::DAGCombinerInfo &DCI,
22816 const X86Subtarget *Subtarget) {
22817 EVT VT = N->getValueType(0);
22818 if (!VT.is256BitVector())
22821 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22822 N->getOpcode() == ISD::ZERO_EXTEND ||
22823 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22825 SDValue Narrow = N->getOperand(0);
22826 EVT NarrowVT = Narrow->getValueType(0);
22827 if (!NarrowVT.is128BitVector())
22830 if (Narrow->getOpcode() != ISD::XOR &&
22831 Narrow->getOpcode() != ISD::AND &&
22832 Narrow->getOpcode() != ISD::OR)
22835 SDValue N0 = Narrow->getOperand(0);
22836 SDValue N1 = Narrow->getOperand(1);
22839 // The Left side has to be a trunc.
22840 if (N0.getOpcode() != ISD::TRUNCATE)
22843 // The type of the truncated inputs.
22844 EVT WideVT = N0->getOperand(0)->getValueType(0);
22848 // The right side has to be a 'trunc' or a constant vector.
22849 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22850 ConstantSDNode *RHSConstSplat = nullptr;
22851 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22852 RHSConstSplat = RHSBV->getConstantSplatNode();
22853 if (!RHSTrunc && !RHSConstSplat)
22856 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22858 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22861 // Set N0 and N1 to hold the inputs to the new wide operation.
22862 N0 = N0->getOperand(0);
22863 if (RHSConstSplat) {
22864 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22865 SDValue(RHSConstSplat, 0));
22866 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22867 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22868 } else if (RHSTrunc) {
22869 N1 = N1->getOperand(0);
22872 // Generate the wide operation.
22873 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22874 unsigned Opcode = N->getOpcode();
22876 case ISD::ANY_EXTEND:
22878 case ISD::ZERO_EXTEND: {
22879 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22880 APInt Mask = APInt::getAllOnesValue(InBits);
22881 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22882 return DAG.getNode(ISD::AND, DL, VT,
22883 Op, DAG.getConstant(Mask, DL, VT));
22885 case ISD::SIGN_EXTEND:
22886 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22887 Op, DAG.getValueType(NarrowVT));
22889 llvm_unreachable("Unexpected opcode");
22893 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
22894 TargetLowering::DAGCombinerInfo &DCI,
22895 const X86Subtarget *Subtarget) {
22896 SDValue N0 = N->getOperand(0);
22897 SDValue N1 = N->getOperand(1);
22900 // A vector zext_in_reg may be represented as a shuffle,
22901 // feeding into a bitcast (this represents anyext) feeding into
22902 // an and with a mask.
22903 // We'd like to try to combine that into a shuffle with zero
22904 // plus a bitcast, removing the and.
22905 if (N0.getOpcode() != ISD::BITCAST ||
22906 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
22909 // The other side of the AND should be a splat of 2^C, where C
22910 // is the number of bits in the source type.
22911 if (N1.getOpcode() == ISD::BITCAST)
22912 N1 = N1.getOperand(0);
22913 if (N1.getOpcode() != ISD::BUILD_VECTOR)
22915 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
22917 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
22918 EVT SrcType = Shuffle->getValueType(0);
22920 // We expect a single-source shuffle
22921 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
22924 unsigned SrcSize = SrcType.getScalarSizeInBits();
22926 APInt SplatValue, SplatUndef;
22927 unsigned SplatBitSize;
22929 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
22930 SplatBitSize, HasAnyUndefs))
22933 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
22934 // Make sure the splat matches the mask we expect
22935 if (SplatBitSize > ResSize ||
22936 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
22939 // Make sure the input and output size make sense
22940 if (SrcSize >= ResSize || ResSize % SrcSize)
22943 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
22944 // The number of u's between each two values depends on the ratio between
22945 // the source and dest type.
22946 unsigned ZextRatio = ResSize / SrcSize;
22947 bool IsZext = true;
22948 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
22949 if (i % ZextRatio) {
22950 if (Shuffle->getMaskElt(i) > 0) {
22956 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
22957 // Expected element number
22967 // Ok, perform the transformation - replace the shuffle with
22968 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
22969 // (instead of undef) where the k elements come from the zero vector.
22970 SmallVector<int, 8> Mask;
22971 unsigned NumElems = SrcType.getVectorNumElements();
22972 for (unsigned i = 0; i < NumElems; ++i)
22974 Mask.push_back(NumElems);
22976 Mask.push_back(i / ZextRatio);
22978 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
22979 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
22980 return DAG.getBitcast(N0.getValueType(), NewShuffle);
22983 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22984 TargetLowering::DAGCombinerInfo &DCI,
22985 const X86Subtarget *Subtarget) {
22986 if (DCI.isBeforeLegalizeOps())
22989 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
22992 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
22995 EVT VT = N->getValueType(0);
22996 SDValue N0 = N->getOperand(0);
22997 SDValue N1 = N->getOperand(1);
23000 // Create BEXTR instructions
23001 // BEXTR is ((X >> imm) & (2**size-1))
23002 if (VT == MVT::i32 || VT == MVT::i64) {
23003 // Check for BEXTR.
23004 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23005 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23006 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23007 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23008 if (MaskNode && ShiftNode) {
23009 uint64_t Mask = MaskNode->getZExtValue();
23010 uint64_t Shift = ShiftNode->getZExtValue();
23011 if (isMask_64(Mask)) {
23012 uint64_t MaskSize = countPopulation(Mask);
23013 if (Shift + MaskSize <= VT.getSizeInBits())
23014 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23015 DAG.getConstant(Shift | (MaskSize << 8), DL,
23024 // Want to form ANDNP nodes:
23025 // 1) In the hopes of then easily combining them with OR and AND nodes
23026 // to form PBLEND/PSIGN.
23027 // 2) To match ANDN packed intrinsics
23028 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23031 // Check LHS for vnot
23032 if (N0.getOpcode() == ISD::XOR &&
23033 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23034 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23035 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23037 // Check RHS for vnot
23038 if (N1.getOpcode() == ISD::XOR &&
23039 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23040 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23041 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23046 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23047 TargetLowering::DAGCombinerInfo &DCI,
23048 const X86Subtarget *Subtarget) {
23049 if (DCI.isBeforeLegalizeOps())
23052 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23056 SDValue N0 = N->getOperand(0);
23057 SDValue N1 = N->getOperand(1);
23058 EVT VT = N->getValueType(0);
23060 // look for psign/blend
23061 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23062 if (!Subtarget->hasSSSE3() ||
23063 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23066 // Canonicalize pandn to RHS
23067 if (N0.getOpcode() == X86ISD::ANDNP)
23069 // or (and (m, y), (pandn m, x))
23070 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23071 SDValue Mask = N1.getOperand(0);
23072 SDValue X = N1.getOperand(1);
23074 if (N0.getOperand(0) == Mask)
23075 Y = N0.getOperand(1);
23076 if (N0.getOperand(1) == Mask)
23077 Y = N0.getOperand(0);
23079 // Check to see if the mask appeared in both the AND and ANDNP and
23083 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23084 // Look through mask bitcast.
23085 if (Mask.getOpcode() == ISD::BITCAST)
23086 Mask = Mask.getOperand(0);
23087 if (X.getOpcode() == ISD::BITCAST)
23088 X = X.getOperand(0);
23089 if (Y.getOpcode() == ISD::BITCAST)
23090 Y = Y.getOperand(0);
23092 EVT MaskVT = Mask.getValueType();
23094 // Validate that the Mask operand is a vector sra node.
23095 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23096 // there is no psrai.b
23097 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23098 unsigned SraAmt = ~0;
23099 if (Mask.getOpcode() == ISD::SRA) {
23100 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23101 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23102 SraAmt = AmtConst->getZExtValue();
23103 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23104 SDValue SraC = Mask.getOperand(1);
23105 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23107 if ((SraAmt + 1) != EltBits)
23112 // Now we know we at least have a plendvb with the mask val. See if
23113 // we can form a psignb/w/d.
23114 // psign = x.type == y.type == mask.type && y = sub(0, x);
23115 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23116 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23117 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23118 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23119 "Unsupported VT for PSIGN");
23120 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23121 return DAG.getBitcast(VT, Mask);
23123 // PBLENDVB only available on SSE 4.1
23124 if (!Subtarget->hasSSE41())
23127 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23129 X = DAG.getBitcast(BlendVT, X);
23130 Y = DAG.getBitcast(BlendVT, Y);
23131 Mask = DAG.getBitcast(BlendVT, Mask);
23132 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23133 return DAG.getBitcast(VT, Mask);
23137 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23140 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23141 MachineFunction &MF = DAG.getMachineFunction();
23143 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
23145 // SHLD/SHRD instructions have lower register pressure, but on some
23146 // platforms they have higher latency than the equivalent
23147 // series of shifts/or that would otherwise be generated.
23148 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23149 // have higher latencies and we are not optimizing for size.
23150 if (!OptForSize && Subtarget->isSHLDSlow())
23153 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23155 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23157 if (!N0.hasOneUse() || !N1.hasOneUse())
23160 SDValue ShAmt0 = N0.getOperand(1);
23161 if (ShAmt0.getValueType() != MVT::i8)
23163 SDValue ShAmt1 = N1.getOperand(1);
23164 if (ShAmt1.getValueType() != MVT::i8)
23166 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23167 ShAmt0 = ShAmt0.getOperand(0);
23168 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23169 ShAmt1 = ShAmt1.getOperand(0);
23172 unsigned Opc = X86ISD::SHLD;
23173 SDValue Op0 = N0.getOperand(0);
23174 SDValue Op1 = N1.getOperand(0);
23175 if (ShAmt0.getOpcode() == ISD::SUB) {
23176 Opc = X86ISD::SHRD;
23177 std::swap(Op0, Op1);
23178 std::swap(ShAmt0, ShAmt1);
23181 unsigned Bits = VT.getSizeInBits();
23182 if (ShAmt1.getOpcode() == ISD::SUB) {
23183 SDValue Sum = ShAmt1.getOperand(0);
23184 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23185 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23186 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23187 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23188 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23189 return DAG.getNode(Opc, DL, VT,
23191 DAG.getNode(ISD::TRUNCATE, DL,
23194 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23195 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23197 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23198 return DAG.getNode(Opc, DL, VT,
23199 N0.getOperand(0), N1.getOperand(0),
23200 DAG.getNode(ISD::TRUNCATE, DL,
23207 // Generate NEG and CMOV for integer abs.
23208 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23209 EVT VT = N->getValueType(0);
23211 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23212 // 8-bit integer abs to NEG and CMOV.
23213 if (VT.isInteger() && VT.getSizeInBits() == 8)
23216 SDValue N0 = N->getOperand(0);
23217 SDValue N1 = N->getOperand(1);
23220 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23221 // and change it to SUB and CMOV.
23222 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23223 N0.getOpcode() == ISD::ADD &&
23224 N0.getOperand(1) == N1 &&
23225 N1.getOpcode() == ISD::SRA &&
23226 N1.getOperand(0) == N0.getOperand(0))
23227 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23228 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23229 // Generate SUB & CMOV.
23230 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23231 DAG.getConstant(0, DL, VT), N0.getOperand(0));
23233 SDValue Ops[] = { N0.getOperand(0), Neg,
23234 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
23235 SDValue(Neg.getNode(), 1) };
23236 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23241 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23242 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23243 TargetLowering::DAGCombinerInfo &DCI,
23244 const X86Subtarget *Subtarget) {
23245 if (DCI.isBeforeLegalizeOps())
23248 if (Subtarget->hasCMov()) {
23249 SDValue RV = performIntegerAbsCombine(N, DAG);
23257 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23258 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23259 TargetLowering::DAGCombinerInfo &DCI,
23260 const X86Subtarget *Subtarget) {
23261 LoadSDNode *Ld = cast<LoadSDNode>(N);
23262 EVT RegVT = Ld->getValueType(0);
23263 EVT MemVT = Ld->getMemoryVT();
23265 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23267 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
23268 // into two 16-byte operations.
23269 ISD::LoadExtType Ext = Ld->getExtensionType();
23270 unsigned Alignment = Ld->getAlignment();
23271 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23272 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23273 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23274 unsigned NumElems = RegVT.getVectorNumElements();
23278 SDValue Ptr = Ld->getBasePtr();
23279 SDValue Increment = DAG.getConstant(16, dl, TLI.getPointerTy());
23281 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23283 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23284 Ld->getPointerInfo(), Ld->isVolatile(),
23285 Ld->isNonTemporal(), Ld->isInvariant(),
23287 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23288 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23289 Ld->getPointerInfo(), Ld->isVolatile(),
23290 Ld->isNonTemporal(), Ld->isInvariant(),
23291 std::min(16U, Alignment));
23292 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23294 Load2.getValue(1));
23296 SDValue NewVec = DAG.getUNDEF(RegVT);
23297 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23298 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23299 return DCI.CombineTo(N, NewVec, TF, true);
23305 /// PerformMLOADCombine - Resolve extending loads
23306 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
23307 TargetLowering::DAGCombinerInfo &DCI,
23308 const X86Subtarget *Subtarget) {
23309 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
23310 if (Mld->getExtensionType() != ISD::SEXTLOAD)
23313 EVT VT = Mld->getValueType(0);
23314 unsigned NumElems = VT.getVectorNumElements();
23315 EVT LdVT = Mld->getMemoryVT();
23318 assert(LdVT != VT && "Cannot extend to the same type");
23319 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
23320 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
23321 // From, To sizes and ElemCount must be pow of two
23322 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23323 "Unexpected size for extending masked load");
23325 unsigned SizeRatio = ToSz / FromSz;
23326 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
23328 // Create a type on which we perform the shuffle
23329 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23330 LdVT.getScalarType(), NumElems*SizeRatio);
23331 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23333 // Convert Src0 value
23334 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
23335 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
23336 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23337 for (unsigned i = 0; i != NumElems; ++i)
23338 ShuffleVec[i] = i * SizeRatio;
23340 // Can't shuffle using an illegal type.
23341 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23342 && "WideVecVT should be legal");
23343 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
23344 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
23346 // Prepare the new mask
23348 SDValue Mask = Mld->getMask();
23349 if (Mask.getValueType() == VT) {
23350 // Mask and original value have the same type
23351 NewMask = DAG.getBitcast(WideVecVT, Mask);
23352 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23353 for (unsigned i = 0; i != NumElems; ++i)
23354 ShuffleVec[i] = i * SizeRatio;
23355 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23356 ShuffleVec[i] = NumElems*SizeRatio;
23357 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23358 DAG.getConstant(0, dl, WideVecVT),
23362 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23363 unsigned WidenNumElts = NumElems*SizeRatio;
23364 unsigned MaskNumElts = VT.getVectorNumElements();
23365 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23368 unsigned NumConcat = WidenNumElts / MaskNumElts;
23369 SmallVector<SDValue, 16> Ops(NumConcat);
23370 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23372 for (unsigned i = 1; i != NumConcat; ++i)
23375 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23378 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
23379 Mld->getBasePtr(), NewMask, WideSrc0,
23380 Mld->getMemoryVT(), Mld->getMemOperand(),
23382 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
23383 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
23386 /// PerformMSTORECombine - Resolve truncating stores
23387 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
23388 const X86Subtarget *Subtarget) {
23389 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
23390 if (!Mst->isTruncatingStore())
23393 EVT VT = Mst->getValue().getValueType();
23394 unsigned NumElems = VT.getVectorNumElements();
23395 EVT StVT = Mst->getMemoryVT();
23398 assert(StVT != VT && "Cannot truncate to the same type");
23399 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23400 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23402 // From, To sizes and ElemCount must be pow of two
23403 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23404 "Unexpected size for truncating masked store");
23405 // We are going to use the original vector elt for storing.
23406 // Accumulated smaller vector elements must be a multiple of the store size.
23407 assert (((NumElems * FromSz) % ToSz) == 0 &&
23408 "Unexpected ratio for truncating masked store");
23410 unsigned SizeRatio = FromSz / ToSz;
23411 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23413 // Create a type on which we perform the shuffle
23414 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23415 StVT.getScalarType(), NumElems*SizeRatio);
23417 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23419 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
23420 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23421 for (unsigned i = 0; i != NumElems; ++i)
23422 ShuffleVec[i] = i * SizeRatio;
23424 // Can't shuffle using an illegal type.
23425 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23426 && "WideVecVT should be legal");
23428 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23429 DAG.getUNDEF(WideVecVT),
23433 SDValue Mask = Mst->getMask();
23434 if (Mask.getValueType() == VT) {
23435 // Mask and original value have the same type
23436 NewMask = DAG.getBitcast(WideVecVT, Mask);
23437 for (unsigned i = 0; i != NumElems; ++i)
23438 ShuffleVec[i] = i * SizeRatio;
23439 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23440 ShuffleVec[i] = NumElems*SizeRatio;
23441 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23442 DAG.getConstant(0, dl, WideVecVT),
23446 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23447 unsigned WidenNumElts = NumElems*SizeRatio;
23448 unsigned MaskNumElts = VT.getVectorNumElements();
23449 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23452 unsigned NumConcat = WidenNumElts / MaskNumElts;
23453 SmallVector<SDValue, 16> Ops(NumConcat);
23454 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23456 for (unsigned i = 1; i != NumConcat; ++i)
23459 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23462 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
23463 NewMask, StVT, Mst->getMemOperand(), false);
23465 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23466 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23467 const X86Subtarget *Subtarget) {
23468 StoreSDNode *St = cast<StoreSDNode>(N);
23469 EVT VT = St->getValue().getValueType();
23470 EVT StVT = St->getMemoryVT();
23472 SDValue StoredVal = St->getOperand(1);
23473 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23475 // If we are saving a concatenation of two XMM registers and 32-byte stores
23476 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
23477 unsigned Alignment = St->getAlignment();
23478 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23479 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23480 StVT == VT && !IsAligned) {
23481 unsigned NumElems = VT.getVectorNumElements();
23485 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23486 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23488 SDValue Stride = DAG.getConstant(16, dl, TLI.getPointerTy());
23489 SDValue Ptr0 = St->getBasePtr();
23490 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23492 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23493 St->getPointerInfo(), St->isVolatile(),
23494 St->isNonTemporal(), Alignment);
23495 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23496 St->getPointerInfo(), St->isVolatile(),
23497 St->isNonTemporal(),
23498 std::min(16U, Alignment));
23499 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23502 // Optimize trunc store (of multiple scalars) to shuffle and store.
23503 // First, pack all of the elements in one place. Next, store to memory
23504 // in fewer chunks.
23505 if (St->isTruncatingStore() && VT.isVector()) {
23506 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23507 unsigned NumElems = VT.getVectorNumElements();
23508 assert(StVT != VT && "Cannot truncate to the same type");
23509 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23510 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23512 // From, To sizes and ElemCount must be pow of two
23513 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23514 // We are going to use the original vector elt for storing.
23515 // Accumulated smaller vector elements must be a multiple of the store size.
23516 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23518 unsigned SizeRatio = FromSz / ToSz;
23520 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23522 // Create a type on which we perform the shuffle
23523 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23524 StVT.getScalarType(), NumElems*SizeRatio);
23526 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23528 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
23529 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23530 for (unsigned i = 0; i != NumElems; ++i)
23531 ShuffleVec[i] = i * SizeRatio;
23533 // Can't shuffle using an illegal type.
23534 if (!TLI.isTypeLegal(WideVecVT))
23537 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23538 DAG.getUNDEF(WideVecVT),
23540 // At this point all of the data is stored at the bottom of the
23541 // register. We now need to save it to mem.
23543 // Find the largest store unit
23544 MVT StoreType = MVT::i8;
23545 for (MVT Tp : MVT::integer_valuetypes()) {
23546 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23550 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23551 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23552 (64 <= NumElems * ToSz))
23553 StoreType = MVT::f64;
23555 // Bitcast the original vector into a vector of store-size units
23556 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23557 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23558 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23559 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
23560 SmallVector<SDValue, 8> Chains;
23561 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, dl,
23562 TLI.getPointerTy());
23563 SDValue Ptr = St->getBasePtr();
23565 // Perform one or more big stores into memory.
23566 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23567 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23568 StoreType, ShuffWide,
23569 DAG.getIntPtrConstant(i, dl));
23570 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23571 St->getPointerInfo(), St->isVolatile(),
23572 St->isNonTemporal(), St->getAlignment());
23573 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23574 Chains.push_back(Ch);
23577 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23580 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23581 // the FP state in cases where an emms may be missing.
23582 // A preferable solution to the general problem is to figure out the right
23583 // places to insert EMMS. This qualifies as a quick hack.
23585 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23586 if (VT.getSizeInBits() != 64)
23589 const Function *F = DAG.getMachineFunction().getFunction();
23590 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
23592 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
23593 if ((VT.isVector() ||
23594 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23595 isa<LoadSDNode>(St->getValue()) &&
23596 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23597 St->getChain().hasOneUse() && !St->isVolatile()) {
23598 SDNode* LdVal = St->getValue().getNode();
23599 LoadSDNode *Ld = nullptr;
23600 int TokenFactorIndex = -1;
23601 SmallVector<SDValue, 8> Ops;
23602 SDNode* ChainVal = St->getChain().getNode();
23603 // Must be a store of a load. We currently handle two cases: the load
23604 // is a direct child, and it's under an intervening TokenFactor. It is
23605 // possible to dig deeper under nested TokenFactors.
23606 if (ChainVal == LdVal)
23607 Ld = cast<LoadSDNode>(St->getChain());
23608 else if (St->getValue().hasOneUse() &&
23609 ChainVal->getOpcode() == ISD::TokenFactor) {
23610 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23611 if (ChainVal->getOperand(i).getNode() == LdVal) {
23612 TokenFactorIndex = i;
23613 Ld = cast<LoadSDNode>(St->getValue());
23615 Ops.push_back(ChainVal->getOperand(i));
23619 if (!Ld || !ISD::isNormalLoad(Ld))
23622 // If this is not the MMX case, i.e. we are just turning i64 load/store
23623 // into f64 load/store, avoid the transformation if there are multiple
23624 // uses of the loaded value.
23625 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23630 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23631 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23633 if (Subtarget->is64Bit() || F64IsLegal) {
23634 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23635 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23636 Ld->getPointerInfo(), Ld->isVolatile(),
23637 Ld->isNonTemporal(), Ld->isInvariant(),
23638 Ld->getAlignment());
23639 SDValue NewChain = NewLd.getValue(1);
23640 if (TokenFactorIndex != -1) {
23641 Ops.push_back(NewChain);
23642 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23644 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23645 St->getPointerInfo(),
23646 St->isVolatile(), St->isNonTemporal(),
23647 St->getAlignment());
23650 // Otherwise, lower to two pairs of 32-bit loads / stores.
23651 SDValue LoAddr = Ld->getBasePtr();
23652 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23653 DAG.getConstant(4, LdDL, MVT::i32));
23655 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23656 Ld->getPointerInfo(),
23657 Ld->isVolatile(), Ld->isNonTemporal(),
23658 Ld->isInvariant(), Ld->getAlignment());
23659 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23660 Ld->getPointerInfo().getWithOffset(4),
23661 Ld->isVolatile(), Ld->isNonTemporal(),
23663 MinAlign(Ld->getAlignment(), 4));
23665 SDValue NewChain = LoLd.getValue(1);
23666 if (TokenFactorIndex != -1) {
23667 Ops.push_back(LoLd);
23668 Ops.push_back(HiLd);
23669 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23672 LoAddr = St->getBasePtr();
23673 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23674 DAG.getConstant(4, StDL, MVT::i32));
23676 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23677 St->getPointerInfo(),
23678 St->isVolatile(), St->isNonTemporal(),
23679 St->getAlignment());
23680 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23681 St->getPointerInfo().getWithOffset(4),
23683 St->isNonTemporal(),
23684 MinAlign(St->getAlignment(), 4));
23685 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23688 // This is similar to the above case, but here we handle a scalar 64-bit
23689 // integer store that is extracted from a vector on a 32-bit target.
23690 // If we have SSE2, then we can treat it like a floating-point double
23691 // to get past legalization. The execution dependencies fixup pass will
23692 // choose the optimal machine instruction for the store if this really is
23693 // an integer or v2f32 rather than an f64.
23694 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
23695 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
23696 SDValue OldExtract = St->getOperand(1);
23697 SDValue ExtOp0 = OldExtract.getOperand(0);
23698 unsigned VecSize = ExtOp0.getValueSizeInBits();
23699 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
23700 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
23701 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
23702 BitCast, OldExtract.getOperand(1));
23703 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
23704 St->getPointerInfo(), St->isVolatile(),
23705 St->isNonTemporal(), St->getAlignment());
23711 /// Return 'true' if this vector operation is "horizontal"
23712 /// and return the operands for the horizontal operation in LHS and RHS. A
23713 /// horizontal operation performs the binary operation on successive elements
23714 /// of its first operand, then on successive elements of its second operand,
23715 /// returning the resulting values in a vector. For example, if
23716 /// A = < float a0, float a1, float a2, float a3 >
23718 /// B = < float b0, float b1, float b2, float b3 >
23719 /// then the result of doing a horizontal operation on A and B is
23720 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23721 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23722 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23723 /// set to A, RHS to B, and the routine returns 'true'.
23724 /// Note that the binary operation should have the property that if one of the
23725 /// operands is UNDEF then the result is UNDEF.
23726 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23727 // Look for the following pattern: if
23728 // A = < float a0, float a1, float a2, float a3 >
23729 // B = < float b0, float b1, float b2, float b3 >
23731 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23732 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23733 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23734 // which is A horizontal-op B.
23736 // At least one of the operands should be a vector shuffle.
23737 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23738 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23741 MVT VT = LHS.getSimpleValueType();
23743 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23744 "Unsupported vector type for horizontal add/sub");
23746 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23747 // operate independently on 128-bit lanes.
23748 unsigned NumElts = VT.getVectorNumElements();
23749 unsigned NumLanes = VT.getSizeInBits()/128;
23750 unsigned NumLaneElts = NumElts / NumLanes;
23751 assert((NumLaneElts % 2 == 0) &&
23752 "Vector type should have an even number of elements in each lane");
23753 unsigned HalfLaneElts = NumLaneElts/2;
23755 // View LHS in the form
23756 // LHS = VECTOR_SHUFFLE A, B, LMask
23757 // If LHS is not a shuffle then pretend it is the shuffle
23758 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23759 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23762 SmallVector<int, 16> LMask(NumElts);
23763 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23764 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23765 A = LHS.getOperand(0);
23766 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23767 B = LHS.getOperand(1);
23768 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23769 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23771 if (LHS.getOpcode() != ISD::UNDEF)
23773 for (unsigned i = 0; i != NumElts; ++i)
23777 // Likewise, view RHS in the form
23778 // RHS = VECTOR_SHUFFLE C, D, RMask
23780 SmallVector<int, 16> RMask(NumElts);
23781 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23782 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23783 C = RHS.getOperand(0);
23784 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23785 D = RHS.getOperand(1);
23786 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23787 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23789 if (RHS.getOpcode() != ISD::UNDEF)
23791 for (unsigned i = 0; i != NumElts; ++i)
23795 // Check that the shuffles are both shuffling the same vectors.
23796 if (!(A == C && B == D) && !(A == D && B == C))
23799 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23800 if (!A.getNode() && !B.getNode())
23803 // If A and B occur in reverse order in RHS, then "swap" them (which means
23804 // rewriting the mask).
23806 ShuffleVectorSDNode::commuteMask(RMask);
23808 // At this point LHS and RHS are equivalent to
23809 // LHS = VECTOR_SHUFFLE A, B, LMask
23810 // RHS = VECTOR_SHUFFLE A, B, RMask
23811 // Check that the masks correspond to performing a horizontal operation.
23812 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23813 for (unsigned i = 0; i != NumLaneElts; ++i) {
23814 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23816 // Ignore any UNDEF components.
23817 if (LIdx < 0 || RIdx < 0 ||
23818 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23819 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23822 // Check that successive elements are being operated on. If not, this is
23823 // not a horizontal operation.
23824 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23825 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23826 if (!(LIdx == Index && RIdx == Index + 1) &&
23827 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23832 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23833 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23837 /// Do target-specific dag combines on floating point adds.
23838 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23839 const X86Subtarget *Subtarget) {
23840 EVT VT = N->getValueType(0);
23841 SDValue LHS = N->getOperand(0);
23842 SDValue RHS = N->getOperand(1);
23844 // Try to synthesize horizontal adds from adds of shuffles.
23845 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23846 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23847 isHorizontalBinOp(LHS, RHS, true))
23848 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23852 /// Do target-specific dag combines on floating point subs.
23853 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23854 const X86Subtarget *Subtarget) {
23855 EVT VT = N->getValueType(0);
23856 SDValue LHS = N->getOperand(0);
23857 SDValue RHS = N->getOperand(1);
23859 // Try to synthesize horizontal subs from subs of shuffles.
23860 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23861 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23862 isHorizontalBinOp(LHS, RHS, false))
23863 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23867 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
23868 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23869 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23871 // F[X]OR(0.0, x) -> x
23872 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23873 if (C->getValueAPF().isPosZero())
23874 return N->getOperand(1);
23876 // F[X]OR(x, 0.0) -> x
23877 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23878 if (C->getValueAPF().isPosZero())
23879 return N->getOperand(0);
23883 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
23884 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23885 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23887 // Only perform optimizations if UnsafeMath is used.
23888 if (!DAG.getTarget().Options.UnsafeFPMath)
23891 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23892 // into FMINC and FMAXC, which are Commutative operations.
23893 unsigned NewOp = 0;
23894 switch (N->getOpcode()) {
23895 default: llvm_unreachable("unknown opcode");
23896 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23897 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23900 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23901 N->getOperand(0), N->getOperand(1));
23904 /// Do target-specific dag combines on X86ISD::FAND nodes.
23905 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23906 // FAND(0.0, x) -> 0.0
23907 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23908 if (C->getValueAPF().isPosZero())
23909 return N->getOperand(0);
23911 // FAND(x, 0.0) -> 0.0
23912 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23913 if (C->getValueAPF().isPosZero())
23914 return N->getOperand(1);
23919 /// Do target-specific dag combines on X86ISD::FANDN nodes
23920 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23921 // FANDN(0.0, x) -> x
23922 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23923 if (C->getValueAPF().isPosZero())
23924 return N->getOperand(1);
23926 // FANDN(x, 0.0) -> 0.0
23927 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23928 if (C->getValueAPF().isPosZero())
23929 return N->getOperand(1);
23934 static SDValue PerformBTCombine(SDNode *N,
23936 TargetLowering::DAGCombinerInfo &DCI) {
23937 // BT ignores high bits in the bit index operand.
23938 SDValue Op1 = N->getOperand(1);
23939 if (Op1.hasOneUse()) {
23940 unsigned BitWidth = Op1.getValueSizeInBits();
23941 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23942 APInt KnownZero, KnownOne;
23943 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23944 !DCI.isBeforeLegalizeOps());
23945 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23946 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23947 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23948 DCI.CommitTargetLoweringOpt(TLO);
23953 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23954 SDValue Op = N->getOperand(0);
23955 if (Op.getOpcode() == ISD::BITCAST)
23956 Op = Op.getOperand(0);
23957 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23958 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23959 VT.getVectorElementType().getSizeInBits() ==
23960 OpVT.getVectorElementType().getSizeInBits()) {
23961 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23966 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23967 const X86Subtarget *Subtarget) {
23968 EVT VT = N->getValueType(0);
23969 if (!VT.isVector())
23972 SDValue N0 = N->getOperand(0);
23973 SDValue N1 = N->getOperand(1);
23974 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23977 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23978 // both SSE and AVX2 since there is no sign-extended shift right
23979 // operation on a vector with 64-bit elements.
23980 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23981 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23982 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23983 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23984 SDValue N00 = N0.getOperand(0);
23986 // EXTLOAD has a better solution on AVX2,
23987 // it may be replaced with X86ISD::VSEXT node.
23988 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23989 if (!ISD::isNormalLoad(N00.getNode()))
23992 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23993 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23995 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24001 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24002 TargetLowering::DAGCombinerInfo &DCI,
24003 const X86Subtarget *Subtarget) {
24004 SDValue N0 = N->getOperand(0);
24005 EVT VT = N->getValueType(0);
24006 EVT SVT = VT.getScalarType();
24007 EVT InVT = N0->getValueType(0);
24008 EVT InSVT = InVT.getScalarType();
24011 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24012 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24013 // This exposes the sext to the sdivrem lowering, so that it directly extends
24014 // from AH (which we otherwise need to do contortions to access).
24015 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24016 InVT == MVT::i8 && VT == MVT::i32) {
24017 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24018 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
24019 N0.getOperand(0), N0.getOperand(1));
24020 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24021 return R.getValue(1);
24024 if (!DCI.isBeforeLegalizeOps()) {
24025 if (N0.getValueType() == MVT::i1) {
24026 SDValue Zero = DAG.getConstant(0, DL, VT);
24028 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
24029 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
24034 if (VT.isVector()) {
24035 auto ExtendToVec128 = [&DAG](SDLoc DL, SDValue N) {
24036 EVT InVT = N->getValueType(0);
24037 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
24038 128 / InVT.getScalarSizeInBits());
24039 SmallVector<SDValue, 8> Opnds(128 / InVT.getSizeInBits(),
24040 DAG.getUNDEF(InVT));
24042 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
24045 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
24046 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
24047 if (VT.getSizeInBits() == 128 &&
24048 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24049 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24050 SDValue ExOp = ExtendToVec128(DL, N0);
24051 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
24054 // On pre-AVX2 targets, split into 128-bit nodes of
24055 // ISD::SIGN_EXTEND_VECTOR_INREG.
24056 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
24057 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24058 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24059 unsigned NumVecs = VT.getSizeInBits() / 128;
24060 unsigned NumSubElts = 128 / SVT.getSizeInBits();
24061 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
24062 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
24064 SmallVector<SDValue, 8> Opnds;
24065 for (unsigned i = 0, Offset = 0; i != NumVecs;
24066 ++i, Offset += NumSubElts) {
24067 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
24068 DAG.getIntPtrConstant(Offset, DL));
24069 SrcVec = ExtendToVec128(DL, SrcVec);
24070 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
24071 Opnds.push_back(SrcVec);
24073 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
24077 if (!Subtarget->hasFp256())
24080 if (VT.isVector() && VT.getSizeInBits() == 256) {
24081 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24089 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24090 const X86Subtarget* Subtarget) {
24092 EVT VT = N->getValueType(0);
24094 // Let legalize expand this if it isn't a legal type yet.
24095 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24098 EVT ScalarVT = VT.getScalarType();
24099 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24100 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24103 SDValue A = N->getOperand(0);
24104 SDValue B = N->getOperand(1);
24105 SDValue C = N->getOperand(2);
24107 bool NegA = (A.getOpcode() == ISD::FNEG);
24108 bool NegB = (B.getOpcode() == ISD::FNEG);
24109 bool NegC = (C.getOpcode() == ISD::FNEG);
24111 // Negative multiplication when NegA xor NegB
24112 bool NegMul = (NegA != NegB);
24114 A = A.getOperand(0);
24116 B = B.getOperand(0);
24118 C = C.getOperand(0);
24122 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24124 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24126 return DAG.getNode(Opcode, dl, VT, A, B, C);
24129 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24130 TargetLowering::DAGCombinerInfo &DCI,
24131 const X86Subtarget *Subtarget) {
24132 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24133 // (and (i32 x86isd::setcc_carry), 1)
24134 // This eliminates the zext. This transformation is necessary because
24135 // ISD::SETCC is always legalized to i8.
24137 SDValue N0 = N->getOperand(0);
24138 EVT VT = N->getValueType(0);
24140 if (N0.getOpcode() == ISD::AND &&
24142 N0.getOperand(0).hasOneUse()) {
24143 SDValue N00 = N0.getOperand(0);
24144 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24145 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24146 if (!C || C->getZExtValue() != 1)
24148 return DAG.getNode(ISD::AND, dl, VT,
24149 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24150 N00.getOperand(0), N00.getOperand(1)),
24151 DAG.getConstant(1, dl, VT));
24155 if (N0.getOpcode() == ISD::TRUNCATE &&
24157 N0.getOperand(0).hasOneUse()) {
24158 SDValue N00 = N0.getOperand(0);
24159 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24160 return DAG.getNode(ISD::AND, dl, VT,
24161 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24162 N00.getOperand(0), N00.getOperand(1)),
24163 DAG.getConstant(1, dl, VT));
24166 if (VT.is256BitVector()) {
24167 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24172 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24173 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24174 // This exposes the zext to the udivrem lowering, so that it directly extends
24175 // from AH (which we otherwise need to do contortions to access).
24176 if (N0.getOpcode() == ISD::UDIVREM &&
24177 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24178 (VT == MVT::i32 || VT == MVT::i64)) {
24179 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24180 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24181 N0.getOperand(0), N0.getOperand(1));
24182 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24183 return R.getValue(1);
24189 // Optimize x == -y --> x+y == 0
24190 // x != -y --> x+y != 0
24191 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24192 const X86Subtarget* Subtarget) {
24193 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24194 SDValue LHS = N->getOperand(0);
24195 SDValue RHS = N->getOperand(1);
24196 EVT VT = N->getValueType(0);
24199 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24200 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24201 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24202 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
24203 LHS.getOperand(1));
24204 return DAG.getSetCC(DL, N->getValueType(0), addV,
24205 DAG.getConstant(0, DL, addV.getValueType()), CC);
24207 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24208 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24209 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24210 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
24211 RHS.getOperand(1));
24212 return DAG.getSetCC(DL, N->getValueType(0), addV,
24213 DAG.getConstant(0, DL, addV.getValueType()), CC);
24216 if (VT.getScalarType() == MVT::i1 &&
24217 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
24219 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24220 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24221 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24223 if (!IsSEXT0 || !IsVZero1) {
24224 // Swap the operands and update the condition code.
24225 std::swap(LHS, RHS);
24226 CC = ISD::getSetCCSwappedOperands(CC);
24228 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24229 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24230 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24233 if (IsSEXT0 && IsVZero1) {
24234 assert(VT == LHS.getOperand(0).getValueType() &&
24235 "Uexpected operand type");
24236 if (CC == ISD::SETGT)
24237 return DAG.getConstant(0, DL, VT);
24238 if (CC == ISD::SETLE)
24239 return DAG.getConstant(1, DL, VT);
24240 if (CC == ISD::SETEQ || CC == ISD::SETGE)
24241 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24243 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
24244 "Unexpected condition code!");
24245 return LHS.getOperand(0);
24252 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
24253 SelectionDAG &DAG) {
24255 MVT VT = Load->getSimpleValueType(0);
24256 MVT EVT = VT.getVectorElementType();
24257 SDValue Addr = Load->getOperand(1);
24258 SDValue NewAddr = DAG.getNode(
24259 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
24260 DAG.getConstant(Index * EVT.getStoreSize(), dl,
24261 Addr.getSimpleValueType()));
24264 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
24265 DAG.getMachineFunction().getMachineMemOperand(
24266 Load->getMemOperand(), 0, EVT.getStoreSize()));
24270 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24271 const X86Subtarget *Subtarget) {
24273 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24274 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24275 "X86insertps is only defined for v4x32");
24277 SDValue Ld = N->getOperand(1);
24278 if (MayFoldLoad(Ld)) {
24279 // Extract the countS bits from the immediate so we can get the proper
24280 // address when narrowing the vector load to a specific element.
24281 // When the second source op is a memory address, insertps doesn't use
24282 // countS and just gets an f32 from that address.
24283 unsigned DestIndex =
24284 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24286 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24288 // Create this as a scalar to vector to match the instruction pattern.
24289 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24290 // countS bits are ignored when loading from memory on insertps, which
24291 // means we don't need to explicitly set them to 0.
24292 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24293 LoadScalarToVector, N->getOperand(2));
24298 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
24299 SDValue V0 = N->getOperand(0);
24300 SDValue V1 = N->getOperand(1);
24302 EVT VT = N->getValueType(0);
24304 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
24305 // operands and changing the mask to 1. This saves us a bunch of
24306 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
24307 // x86InstrInfo knows how to commute this back after instruction selection
24308 // if it would help register allocation.
24310 // TODO: If optimizing for size or a processor that doesn't suffer from
24311 // partial register update stalls, this should be transformed into a MOVSD
24312 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
24314 if (VT == MVT::v2f64)
24315 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
24316 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
24317 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
24318 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
24324 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24325 // as "sbb reg,reg", since it can be extended without zext and produces
24326 // an all-ones bit which is more useful than 0/1 in some cases.
24327 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24330 return DAG.getNode(ISD::AND, DL, VT,
24331 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24332 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24334 DAG.getConstant(1, DL, VT));
24335 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24336 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24337 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24338 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24342 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24343 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24344 TargetLowering::DAGCombinerInfo &DCI,
24345 const X86Subtarget *Subtarget) {
24347 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24348 SDValue EFLAGS = N->getOperand(1);
24350 if (CC == X86::COND_A) {
24351 // Try to convert COND_A into COND_B in an attempt to facilitate
24352 // materializing "setb reg".
24354 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24355 // cannot take an immediate as its first operand.
24357 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24358 EFLAGS.getValueType().isInteger() &&
24359 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24360 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24361 EFLAGS.getNode()->getVTList(),
24362 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24363 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24364 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24368 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24369 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24371 if (CC == X86::COND_B)
24372 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24376 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24377 if (Flags.getNode()) {
24378 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24379 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24385 // Optimize branch condition evaluation.
24387 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24388 TargetLowering::DAGCombinerInfo &DCI,
24389 const X86Subtarget *Subtarget) {
24391 SDValue Chain = N->getOperand(0);
24392 SDValue Dest = N->getOperand(1);
24393 SDValue EFLAGS = N->getOperand(3);
24394 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24398 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24399 if (Flags.getNode()) {
24400 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24401 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24408 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24409 SelectionDAG &DAG) {
24410 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24411 // optimize away operation when it's from a constant.
24413 // The general transformation is:
24414 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24415 // AND(VECTOR_CMP(x,y), constant2)
24416 // constant2 = UNARYOP(constant)
24418 // Early exit if this isn't a vector operation, the operand of the
24419 // unary operation isn't a bitwise AND, or if the sizes of the operations
24420 // aren't the same.
24421 EVT VT = N->getValueType(0);
24422 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24423 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24424 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24427 // Now check that the other operand of the AND is a constant. We could
24428 // make the transformation for non-constant splats as well, but it's unclear
24429 // that would be a benefit as it would not eliminate any operations, just
24430 // perform one more step in scalar code before moving to the vector unit.
24431 if (BuildVectorSDNode *BV =
24432 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24433 // Bail out if the vector isn't a constant.
24434 if (!BV->isConstant())
24437 // Everything checks out. Build up the new and improved node.
24439 EVT IntVT = BV->getValueType(0);
24440 // Create a new constant of the appropriate type for the transformed
24442 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24443 // The AND node needs bitcasts to/from an integer vector type around it.
24444 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
24445 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24446 N->getOperand(0)->getOperand(0), MaskConst);
24447 SDValue Res = DAG.getBitcast(VT, NewAnd);
24454 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24455 const X86Subtarget *Subtarget) {
24456 // First try to optimize away the conversion entirely when it's
24457 // conditionally from a constant. Vectors only.
24458 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24459 if (Res != SDValue())
24462 // Now move on to more general possibilities.
24463 SDValue Op0 = N->getOperand(0);
24464 EVT InVT = Op0->getValueType(0);
24466 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24467 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24469 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24470 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24471 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24474 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24475 // a 32-bit target where SSE doesn't support i64->FP operations.
24476 if (Op0.getOpcode() == ISD::LOAD) {
24477 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24478 EVT VT = Ld->getValueType(0);
24480 // This transformation is not supported if the result type is f16
24481 if (N->getValueType(0) == MVT::f16)
24484 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24485 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24486 !Subtarget->is64Bit() && VT == MVT::i64) {
24487 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
24488 SDValue(N, 0), Ld->getValueType(0), Ld->getChain(), Op0, DAG);
24489 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24496 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24497 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24498 X86TargetLowering::DAGCombinerInfo &DCI) {
24499 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24500 // the result is either zero or one (depending on the input carry bit).
24501 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24502 if (X86::isZeroNode(N->getOperand(0)) &&
24503 X86::isZeroNode(N->getOperand(1)) &&
24504 // We don't have a good way to replace an EFLAGS use, so only do this when
24506 SDValue(N, 1).use_empty()) {
24508 EVT VT = N->getValueType(0);
24509 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
24510 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24511 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24512 DAG.getConstant(X86::COND_B, DL,
24515 DAG.getConstant(1, DL, VT));
24516 return DCI.CombineTo(N, Res1, CarryOut);
24522 // fold (add Y, (sete X, 0)) -> adc 0, Y
24523 // (add Y, (setne X, 0)) -> sbb -1, Y
24524 // (sub (sete X, 0), Y) -> sbb 0, Y
24525 // (sub (setne X, 0), Y) -> adc -1, Y
24526 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24529 // Look through ZExts.
24530 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24531 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24534 SDValue SetCC = Ext.getOperand(0);
24535 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24538 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24539 if (CC != X86::COND_E && CC != X86::COND_NE)
24542 SDValue Cmp = SetCC.getOperand(1);
24543 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24544 !X86::isZeroNode(Cmp.getOperand(1)) ||
24545 !Cmp.getOperand(0).getValueType().isInteger())
24548 SDValue CmpOp0 = Cmp.getOperand(0);
24549 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24550 DAG.getConstant(1, DL, CmpOp0.getValueType()));
24552 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24553 if (CC == X86::COND_NE)
24554 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24555 DL, OtherVal.getValueType(), OtherVal,
24556 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
24558 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24559 DL, OtherVal.getValueType(), OtherVal,
24560 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
24563 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24564 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24565 const X86Subtarget *Subtarget) {
24566 EVT VT = N->getValueType(0);
24567 SDValue Op0 = N->getOperand(0);
24568 SDValue Op1 = N->getOperand(1);
24570 // Try to synthesize horizontal adds from adds of shuffles.
24571 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24572 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24573 isHorizontalBinOp(Op0, Op1, true))
24574 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24576 return OptimizeConditionalInDecrement(N, DAG);
24579 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24580 const X86Subtarget *Subtarget) {
24581 SDValue Op0 = N->getOperand(0);
24582 SDValue Op1 = N->getOperand(1);
24584 // X86 can't encode an immediate LHS of a sub. See if we can push the
24585 // negation into a preceding instruction.
24586 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24587 // If the RHS of the sub is a XOR with one use and a constant, invert the
24588 // immediate. Then add one to the LHS of the sub so we can turn
24589 // X-Y -> X+~Y+1, saving one register.
24590 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24591 isa<ConstantSDNode>(Op1.getOperand(1))) {
24592 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24593 EVT VT = Op0.getValueType();
24594 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24596 DAG.getConstant(~XorC, SDLoc(Op1), VT));
24597 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24598 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
24602 // Try to synthesize horizontal adds from adds of shuffles.
24603 EVT VT = N->getValueType(0);
24604 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24605 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24606 isHorizontalBinOp(Op0, Op1, true))
24607 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24609 return OptimizeConditionalInDecrement(N, DAG);
24612 /// performVZEXTCombine - Performs build vector combines
24613 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24614 TargetLowering::DAGCombinerInfo &DCI,
24615 const X86Subtarget *Subtarget) {
24617 MVT VT = N->getSimpleValueType(0);
24618 SDValue Op = N->getOperand(0);
24619 MVT OpVT = Op.getSimpleValueType();
24620 MVT OpEltVT = OpVT.getVectorElementType();
24621 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
24623 // (vzext (bitcast (vzext (x)) -> (vzext x)
24625 while (V.getOpcode() == ISD::BITCAST)
24626 V = V.getOperand(0);
24628 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
24629 MVT InnerVT = V.getSimpleValueType();
24630 MVT InnerEltVT = InnerVT.getVectorElementType();
24632 // If the element sizes match exactly, we can just do one larger vzext. This
24633 // is always an exact type match as vzext operates on integer types.
24634 if (OpEltVT == InnerEltVT) {
24635 assert(OpVT == InnerVT && "Types must match for vzext!");
24636 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
24639 // The only other way we can combine them is if only a single element of the
24640 // inner vzext is used in the input to the outer vzext.
24641 if (InnerEltVT.getSizeInBits() < InputBits)
24644 // In this case, the inner vzext is completely dead because we're going to
24645 // only look at bits inside of the low element. Just do the outer vzext on
24646 // a bitcast of the input to the inner.
24647 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
24650 // Check if we can bypass extracting and re-inserting an element of an input
24651 // vector. Essentialy:
24652 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
24653 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
24654 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
24655 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
24656 SDValue ExtractedV = V.getOperand(0);
24657 SDValue OrigV = ExtractedV.getOperand(0);
24658 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
24659 if (ExtractIdx->getZExtValue() == 0) {
24660 MVT OrigVT = OrigV.getSimpleValueType();
24661 // Extract a subvector if necessary...
24662 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
24663 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
24664 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
24665 OrigVT.getVectorNumElements() / Ratio);
24666 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
24667 DAG.getIntPtrConstant(0, DL));
24669 Op = DAG.getBitcast(OpVT, OrigV);
24670 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
24677 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24678 DAGCombinerInfo &DCI) const {
24679 SelectionDAG &DAG = DCI.DAG;
24680 switch (N->getOpcode()) {
24682 case ISD::EXTRACT_VECTOR_ELT:
24683 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24686 case X86ISD::SHRUNKBLEND:
24687 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24688 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
24689 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24690 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24691 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24692 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24693 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24696 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24697 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24698 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24699 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24700 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24701 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
24702 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24703 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
24704 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
24705 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24706 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24708 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24710 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24711 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24712 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24713 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24714 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24715 case ISD::ANY_EXTEND:
24716 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24717 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24718 case ISD::SIGN_EXTEND_INREG:
24719 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24720 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24721 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24722 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24723 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24724 case X86ISD::SHUFP: // Handle all target specific shuffles
24725 case X86ISD::PALIGNR:
24726 case X86ISD::UNPCKH:
24727 case X86ISD::UNPCKL:
24728 case X86ISD::MOVHLPS:
24729 case X86ISD::MOVLHPS:
24730 case X86ISD::PSHUFB:
24731 case X86ISD::PSHUFD:
24732 case X86ISD::PSHUFHW:
24733 case X86ISD::PSHUFLW:
24734 case X86ISD::MOVSS:
24735 case X86ISD::MOVSD:
24736 case X86ISD::VPERMILPI:
24737 case X86ISD::VPERM2X128:
24738 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24739 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24740 case ISD::INTRINSIC_WO_CHAIN:
24741 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24742 case X86ISD::INSERTPS: {
24743 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
24744 return PerformINSERTPSCombine(N, DAG, Subtarget);
24747 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
24753 /// isTypeDesirableForOp - Return true if the target has native support for
24754 /// the specified value type and it is 'desirable' to use the type for the
24755 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24756 /// instruction encodings are longer and some i16 instructions are slow.
24757 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24758 if (!isTypeLegal(VT))
24760 if (VT != MVT::i16)
24767 case ISD::SIGN_EXTEND:
24768 case ISD::ZERO_EXTEND:
24769 case ISD::ANY_EXTEND:
24782 /// IsDesirableToPromoteOp - This method query the target whether it is
24783 /// beneficial for dag combiner to promote the specified node. If true, it
24784 /// should return the desired promotion type by reference.
24785 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24786 EVT VT = Op.getValueType();
24787 if (VT != MVT::i16)
24790 bool Promote = false;
24791 bool Commute = false;
24792 switch (Op.getOpcode()) {
24795 LoadSDNode *LD = cast<LoadSDNode>(Op);
24796 // If the non-extending load has a single use and it's not live out, then it
24797 // might be folded.
24798 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24799 Op.hasOneUse()*/) {
24800 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24801 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24802 // The only case where we'd want to promote LOAD (rather then it being
24803 // promoted as an operand is when it's only use is liveout.
24804 if (UI->getOpcode() != ISD::CopyToReg)
24811 case ISD::SIGN_EXTEND:
24812 case ISD::ZERO_EXTEND:
24813 case ISD::ANY_EXTEND:
24818 SDValue N0 = Op.getOperand(0);
24819 // Look out for (store (shl (load), x)).
24820 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24833 SDValue N0 = Op.getOperand(0);
24834 SDValue N1 = Op.getOperand(1);
24835 if (!Commute && MayFoldLoad(N1))
24837 // Avoid disabling potential load folding opportunities.
24838 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24840 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24850 //===----------------------------------------------------------------------===//
24851 // X86 Inline Assembly Support
24852 //===----------------------------------------------------------------------===//
24854 // Helper to match a string separated by whitespace.
24855 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
24856 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
24858 for (StringRef Piece : Pieces) {
24859 if (!S.startswith(Piece)) // Check if the piece matches.
24862 S = S.substr(Piece.size());
24863 StringRef::size_type Pos = S.find_first_not_of(" \t");
24864 if (Pos == 0) // We matched a prefix.
24873 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24875 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24876 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24877 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24878 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24880 if (AsmPieces.size() == 3)
24882 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24889 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24890 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24892 std::string AsmStr = IA->getAsmString();
24894 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24895 if (!Ty || Ty->getBitWidth() % 16 != 0)
24898 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24899 SmallVector<StringRef, 4> AsmPieces;
24900 SplitString(AsmStr, AsmPieces, ";\n");
24902 switch (AsmPieces.size()) {
24903 default: return false;
24905 // FIXME: this should verify that we are targeting a 486 or better. If not,
24906 // we will turn this bswap into something that will be lowered to logical
24907 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24908 // lower so don't worry about this.
24910 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
24911 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
24912 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
24913 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
24914 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
24915 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
24916 // No need to check constraints, nothing other than the equivalent of
24917 // "=r,0" would be valid here.
24918 return IntrinsicLowering::LowerToByteSwap(CI);
24921 // rorw $$8, ${0:w} --> llvm.bswap.i16
24922 if (CI->getType()->isIntegerTy(16) &&
24923 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24924 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
24925 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
24927 const std::string &ConstraintsStr = IA->getConstraintString();
24928 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24929 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24930 if (clobbersFlagRegisters(AsmPieces))
24931 return IntrinsicLowering::LowerToByteSwap(CI);
24935 if (CI->getType()->isIntegerTy(32) &&
24936 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24937 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
24938 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
24939 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
24941 const std::string &ConstraintsStr = IA->getConstraintString();
24942 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24943 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24944 if (clobbersFlagRegisters(AsmPieces))
24945 return IntrinsicLowering::LowerToByteSwap(CI);
24948 if (CI->getType()->isIntegerTy(64)) {
24949 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24950 if (Constraints.size() >= 2 &&
24951 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24952 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24953 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24954 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
24955 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
24956 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
24957 return IntrinsicLowering::LowerToByteSwap(CI);
24965 /// getConstraintType - Given a constraint letter, return the type of
24966 /// constraint it is for this target.
24967 X86TargetLowering::ConstraintType
24968 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24969 if (Constraint.size() == 1) {
24970 switch (Constraint[0]) {
24981 return C_RegisterClass;
25005 return TargetLowering::getConstraintType(Constraint);
25008 /// Examine constraint type and operand type and determine a weight value.
25009 /// This object must already have been set up with the operand type
25010 /// and the current alternative constraint selected.
25011 TargetLowering::ConstraintWeight
25012 X86TargetLowering::getSingleConstraintMatchWeight(
25013 AsmOperandInfo &info, const char *constraint) const {
25014 ConstraintWeight weight = CW_Invalid;
25015 Value *CallOperandVal = info.CallOperandVal;
25016 // If we don't have a value, we can't do a match,
25017 // but allow it at the lowest weight.
25018 if (!CallOperandVal)
25020 Type *type = CallOperandVal->getType();
25021 // Look at the constraint type.
25022 switch (*constraint) {
25024 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25035 if (CallOperandVal->getType()->isIntegerTy())
25036 weight = CW_SpecificReg;
25041 if (type->isFloatingPointTy())
25042 weight = CW_SpecificReg;
25045 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25046 weight = CW_SpecificReg;
25050 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25051 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25052 weight = CW_Register;
25055 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25056 if (C->getZExtValue() <= 31)
25057 weight = CW_Constant;
25061 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25062 if (C->getZExtValue() <= 63)
25063 weight = CW_Constant;
25067 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25068 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25069 weight = CW_Constant;
25073 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25074 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25075 weight = CW_Constant;
25079 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25080 if (C->getZExtValue() <= 3)
25081 weight = CW_Constant;
25085 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25086 if (C->getZExtValue() <= 0xff)
25087 weight = CW_Constant;
25092 if (isa<ConstantFP>(CallOperandVal)) {
25093 weight = CW_Constant;
25097 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25098 if ((C->getSExtValue() >= -0x80000000LL) &&
25099 (C->getSExtValue() <= 0x7fffffffLL))
25100 weight = CW_Constant;
25104 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25105 if (C->getZExtValue() <= 0xffffffff)
25106 weight = CW_Constant;
25113 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25114 /// with another that has more specific requirements based on the type of the
25115 /// corresponding operand.
25116 const char *X86TargetLowering::
25117 LowerXConstraint(EVT ConstraintVT) const {
25118 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25119 // 'f' like normal targets.
25120 if (ConstraintVT.isFloatingPoint()) {
25121 if (Subtarget->hasSSE2())
25123 if (Subtarget->hasSSE1())
25127 return TargetLowering::LowerXConstraint(ConstraintVT);
25130 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25131 /// vector. If it is invalid, don't add anything to Ops.
25132 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25133 std::string &Constraint,
25134 std::vector<SDValue>&Ops,
25135 SelectionDAG &DAG) const {
25138 // Only support length 1 constraints for now.
25139 if (Constraint.length() > 1) return;
25141 char ConstraintLetter = Constraint[0];
25142 switch (ConstraintLetter) {
25145 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25146 if (C->getZExtValue() <= 31) {
25147 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25148 Op.getValueType());
25154 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25155 if (C->getZExtValue() <= 63) {
25156 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25157 Op.getValueType());
25163 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25164 if (isInt<8>(C->getSExtValue())) {
25165 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25166 Op.getValueType());
25172 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25173 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
25174 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
25175 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
25176 Op.getValueType());
25182 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25183 if (C->getZExtValue() <= 3) {
25184 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25185 Op.getValueType());
25191 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25192 if (C->getZExtValue() <= 255) {
25193 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25194 Op.getValueType());
25200 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25201 if (C->getZExtValue() <= 127) {
25202 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25203 Op.getValueType());
25209 // 32-bit signed value
25210 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25211 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25212 C->getSExtValue())) {
25213 // Widen to 64 bits here to get it sign extended.
25214 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
25217 // FIXME gcc accepts some relocatable values here too, but only in certain
25218 // memory models; it's complicated.
25223 // 32-bit unsigned value
25224 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25225 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25226 C->getZExtValue())) {
25227 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25228 Op.getValueType());
25232 // FIXME gcc accepts some relocatable values here too, but only in certain
25233 // memory models; it's complicated.
25237 // Literal immediates are always ok.
25238 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25239 // Widen to 64 bits here to get it sign extended.
25240 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
25244 // In any sort of PIC mode addresses need to be computed at runtime by
25245 // adding in a register or some sort of table lookup. These can't
25246 // be used as immediates.
25247 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25250 // If we are in non-pic codegen mode, we allow the address of a global (with
25251 // an optional displacement) to be used with 'i'.
25252 GlobalAddressSDNode *GA = nullptr;
25253 int64_t Offset = 0;
25255 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25257 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25258 Offset += GA->getOffset();
25260 } else if (Op.getOpcode() == ISD::ADD) {
25261 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25262 Offset += C->getZExtValue();
25263 Op = Op.getOperand(0);
25266 } else if (Op.getOpcode() == ISD::SUB) {
25267 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25268 Offset += -C->getZExtValue();
25269 Op = Op.getOperand(0);
25274 // Otherwise, this isn't something we can handle, reject it.
25278 const GlobalValue *GV = GA->getGlobal();
25279 // If we require an extra load to get this address, as in PIC mode, we
25280 // can't accept it.
25281 if (isGlobalStubReference(
25282 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25285 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25286 GA->getValueType(0), Offset);
25291 if (Result.getNode()) {
25292 Ops.push_back(Result);
25295 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25298 std::pair<unsigned, const TargetRegisterClass *>
25299 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
25300 const std::string &Constraint,
25302 // First, see if this is a constraint that directly corresponds to an LLVM
25304 if (Constraint.size() == 1) {
25305 // GCC Constraint Letters
25306 switch (Constraint[0]) {
25308 // TODO: Slight differences here in allocation order and leaving
25309 // RIP in the class. Do they matter any more here than they do
25310 // in the normal allocation?
25311 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25312 if (Subtarget->is64Bit()) {
25313 if (VT == MVT::i32 || VT == MVT::f32)
25314 return std::make_pair(0U, &X86::GR32RegClass);
25315 if (VT == MVT::i16)
25316 return std::make_pair(0U, &X86::GR16RegClass);
25317 if (VT == MVT::i8 || VT == MVT::i1)
25318 return std::make_pair(0U, &X86::GR8RegClass);
25319 if (VT == MVT::i64 || VT == MVT::f64)
25320 return std::make_pair(0U, &X86::GR64RegClass);
25323 // 32-bit fallthrough
25324 case 'Q': // Q_REGS
25325 if (VT == MVT::i32 || VT == MVT::f32)
25326 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25327 if (VT == MVT::i16)
25328 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25329 if (VT == MVT::i8 || VT == MVT::i1)
25330 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25331 if (VT == MVT::i64)
25332 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25334 case 'r': // GENERAL_REGS
25335 case 'l': // INDEX_REGS
25336 if (VT == MVT::i8 || VT == MVT::i1)
25337 return std::make_pair(0U, &X86::GR8RegClass);
25338 if (VT == MVT::i16)
25339 return std::make_pair(0U, &X86::GR16RegClass);
25340 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25341 return std::make_pair(0U, &X86::GR32RegClass);
25342 return std::make_pair(0U, &X86::GR64RegClass);
25343 case 'R': // LEGACY_REGS
25344 if (VT == MVT::i8 || VT == MVT::i1)
25345 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25346 if (VT == MVT::i16)
25347 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25348 if (VT == MVT::i32 || !Subtarget->is64Bit())
25349 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25350 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25351 case 'f': // FP Stack registers.
25352 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25353 // value to the correct fpstack register class.
25354 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25355 return std::make_pair(0U, &X86::RFP32RegClass);
25356 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25357 return std::make_pair(0U, &X86::RFP64RegClass);
25358 return std::make_pair(0U, &X86::RFP80RegClass);
25359 case 'y': // MMX_REGS if MMX allowed.
25360 if (!Subtarget->hasMMX()) break;
25361 return std::make_pair(0U, &X86::VR64RegClass);
25362 case 'Y': // SSE_REGS if SSE2 allowed
25363 if (!Subtarget->hasSSE2()) break;
25365 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25366 if (!Subtarget->hasSSE1()) break;
25368 switch (VT.SimpleTy) {
25370 // Scalar SSE types.
25373 return std::make_pair(0U, &X86::FR32RegClass);
25376 return std::make_pair(0U, &X86::FR64RegClass);
25384 return std::make_pair(0U, &X86::VR128RegClass);
25392 return std::make_pair(0U, &X86::VR256RegClass);
25397 return std::make_pair(0U, &X86::VR512RegClass);
25403 // Use the default implementation in TargetLowering to convert the register
25404 // constraint into a member of a register class.
25405 std::pair<unsigned, const TargetRegisterClass*> Res;
25406 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
25408 // Not found as a standard register?
25410 // Map st(0) -> st(7) -> ST0
25411 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25412 tolower(Constraint[1]) == 's' &&
25413 tolower(Constraint[2]) == 't' &&
25414 Constraint[3] == '(' &&
25415 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25416 Constraint[5] == ')' &&
25417 Constraint[6] == '}') {
25419 Res.first = X86::FP0+Constraint[4]-'0';
25420 Res.second = &X86::RFP80RegClass;
25424 // GCC allows "st(0)" to be called just plain "st".
25425 if (StringRef("{st}").equals_lower(Constraint)) {
25426 Res.first = X86::FP0;
25427 Res.second = &X86::RFP80RegClass;
25432 if (StringRef("{flags}").equals_lower(Constraint)) {
25433 Res.first = X86::EFLAGS;
25434 Res.second = &X86::CCRRegClass;
25438 // 'A' means EAX + EDX.
25439 if (Constraint == "A") {
25440 Res.first = X86::EAX;
25441 Res.second = &X86::GR32_ADRegClass;
25447 // Otherwise, check to see if this is a register class of the wrong value
25448 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25449 // turn into {ax},{dx}.
25450 if (Res.second->hasType(VT))
25451 return Res; // Correct type already, nothing to do.
25453 // All of the single-register GCC register classes map their values onto
25454 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25455 // really want an 8-bit or 32-bit register, map to the appropriate register
25456 // class and return the appropriate register.
25457 if (Res.second == &X86::GR16RegClass) {
25458 if (VT == MVT::i8 || VT == MVT::i1) {
25459 unsigned DestReg = 0;
25460 switch (Res.first) {
25462 case X86::AX: DestReg = X86::AL; break;
25463 case X86::DX: DestReg = X86::DL; break;
25464 case X86::CX: DestReg = X86::CL; break;
25465 case X86::BX: DestReg = X86::BL; break;
25468 Res.first = DestReg;
25469 Res.second = &X86::GR8RegClass;
25471 } else if (VT == MVT::i32 || VT == MVT::f32) {
25472 unsigned DestReg = 0;
25473 switch (Res.first) {
25475 case X86::AX: DestReg = X86::EAX; break;
25476 case X86::DX: DestReg = X86::EDX; break;
25477 case X86::CX: DestReg = X86::ECX; break;
25478 case X86::BX: DestReg = X86::EBX; break;
25479 case X86::SI: DestReg = X86::ESI; break;
25480 case X86::DI: DestReg = X86::EDI; break;
25481 case X86::BP: DestReg = X86::EBP; break;
25482 case X86::SP: DestReg = X86::ESP; break;
25485 Res.first = DestReg;
25486 Res.second = &X86::GR32RegClass;
25488 } else if (VT == MVT::i64 || VT == MVT::f64) {
25489 unsigned DestReg = 0;
25490 switch (Res.first) {
25492 case X86::AX: DestReg = X86::RAX; break;
25493 case X86::DX: DestReg = X86::RDX; break;
25494 case X86::CX: DestReg = X86::RCX; break;
25495 case X86::BX: DestReg = X86::RBX; break;
25496 case X86::SI: DestReg = X86::RSI; break;
25497 case X86::DI: DestReg = X86::RDI; break;
25498 case X86::BP: DestReg = X86::RBP; break;
25499 case X86::SP: DestReg = X86::RSP; break;
25502 Res.first = DestReg;
25503 Res.second = &X86::GR64RegClass;
25506 } else if (Res.second == &X86::FR32RegClass ||
25507 Res.second == &X86::FR64RegClass ||
25508 Res.second == &X86::VR128RegClass ||
25509 Res.second == &X86::VR256RegClass ||
25510 Res.second == &X86::FR32XRegClass ||
25511 Res.second == &X86::FR64XRegClass ||
25512 Res.second == &X86::VR128XRegClass ||
25513 Res.second == &X86::VR256XRegClass ||
25514 Res.second == &X86::VR512RegClass) {
25515 // Handle references to XMM physical registers that got mapped into the
25516 // wrong class. This can happen with constraints like {xmm0} where the
25517 // target independent register mapper will just pick the first match it can
25518 // find, ignoring the required type.
25520 if (VT == MVT::f32 || VT == MVT::i32)
25521 Res.second = &X86::FR32RegClass;
25522 else if (VT == MVT::f64 || VT == MVT::i64)
25523 Res.second = &X86::FR64RegClass;
25524 else if (X86::VR128RegClass.hasType(VT))
25525 Res.second = &X86::VR128RegClass;
25526 else if (X86::VR256RegClass.hasType(VT))
25527 Res.second = &X86::VR256RegClass;
25528 else if (X86::VR512RegClass.hasType(VT))
25529 Res.second = &X86::VR512RegClass;
25535 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25537 unsigned AS) const {
25538 // Scaling factors are not free at all.
25539 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25540 // will take 2 allocations in the out of order engine instead of 1
25541 // for plain addressing mode, i.e. inst (reg1).
25543 // vaddps (%rsi,%drx), %ymm0, %ymm1
25544 // Requires two allocations (one for the load, one for the computation)
25546 // vaddps (%rsi), %ymm0, %ymm1
25547 // Requires just 1 allocation, i.e., freeing allocations for other operations
25548 // and having less micro operations to execute.
25550 // For some X86 architectures, this is even worse because for instance for
25551 // stores, the complex addressing mode forces the instruction to use the
25552 // "load" ports instead of the dedicated "store" port.
25553 // E.g., on Haswell:
25554 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25555 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25556 if (isLegalAddressingMode(AM, Ty, AS))
25557 // Scale represents reg2 * scale, thus account for 1
25558 // as soon as we use a second register.
25559 return AM.Scale != 0;
25563 bool X86TargetLowering::isTargetFTOL() const {
25564 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();