1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VariadicFunction.h"
47 #include "llvm/Support/CallSite.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetOptions.h"
56 using namespace dwarf;
58 STATISTIC(NumTailCalls, "Number of tail calls");
60 static cl::opt<bool> UseRegMask("x86-use-regmask",
61 cl::desc("Use register masks for x86 calls"));
63 // Forward declarations.
64 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
67 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
68 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
69 /// simple subregister reference. Idx is an index in the 128 bits we
70 /// want. It need not be aligned to a 128-bit bounday. That makes
71 /// lowering EXTRACT_VECTOR_ELT operations easier.
72 static SDValue Extract128BitVector(SDValue Vec,
76 EVT VT = Vec.getValueType();
77 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
78 EVT ElVT = VT.getVectorElementType();
79 int Factor = VT.getSizeInBits()/128;
80 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
81 VT.getVectorNumElements()/Factor);
83 // Extract from UNDEF is UNDEF.
84 if (Vec.getOpcode() == ISD::UNDEF)
85 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
87 if (isa<ConstantSDNode>(Idx)) {
88 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
90 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
91 // we can match to VEXTRACTF128.
92 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
94 // This is the index of the first element of the 128-bit chunk
96 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
99 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
100 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
109 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
110 /// sets things up to match to an AVX VINSERTF128 instruction or a
111 /// simple superregister reference. Idx is an index in the 128 bits
112 /// we want. It need not be aligned to a 128-bit bounday. That makes
113 /// lowering INSERT_VECTOR_ELT operations easier.
114 static SDValue Insert128BitVector(SDValue Result,
119 if (isa<ConstantSDNode>(Idx)) {
120 EVT VT = Vec.getValueType();
121 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
123 EVT ElVT = VT.getVectorElementType();
124 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
125 EVT ResultVT = Result.getValueType();
127 // Insert the relevant 128 bits.
128 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
130 // This is the index of the first element of the 128-bit chunk
132 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
135 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
136 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
144 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
145 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
146 bool is64Bit = Subtarget->is64Bit();
148 if (Subtarget->isTargetEnvMacho()) {
150 return new X8664_MachoTargetObjectFile();
151 return new TargetLoweringObjectFileMachO();
154 if (Subtarget->isTargetELF())
155 return new TargetLoweringObjectFileELF();
156 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
157 return new TargetLoweringObjectFileCOFF();
158 llvm_unreachable("unknown subtarget type");
161 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
162 : TargetLowering(TM, createTLOF(TM)) {
163 Subtarget = &TM.getSubtarget<X86Subtarget>();
164 X86ScalarSSEf64 = Subtarget->hasSSE2();
165 X86ScalarSSEf32 = Subtarget->hasSSE1();
166 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
168 RegInfo = TM.getRegisterInfo();
169 TD = getTargetData();
171 // Set up the TargetLowering object.
172 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
174 // X86 is weird, it always uses i8 for shift amounts and setcc results.
175 setBooleanContents(ZeroOrOneBooleanContent);
176 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
177 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
179 // For 64-bit since we have so many registers use the ILP scheduler, for
180 // 32-bit code use the register pressure specific scheduling.
181 if (Subtarget->is64Bit())
182 setSchedulingPreference(Sched::ILP);
184 setSchedulingPreference(Sched::RegPressure);
185 setStackPointerRegisterToSaveRestore(X86StackPtr);
187 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
188 // Setup Windows compiler runtime calls.
189 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
190 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
191 setLibcallName(RTLIB::SREM_I64, "_allrem");
192 setLibcallName(RTLIB::UREM_I64, "_aullrem");
193 setLibcallName(RTLIB::MUL_I64, "_allmul");
194 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
195 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
196 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
197 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
198 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
199 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
200 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
201 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
202 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
205 if (Subtarget->isTargetDarwin()) {
206 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
207 setUseUnderscoreSetJmp(false);
208 setUseUnderscoreLongJmp(false);
209 } else if (Subtarget->isTargetMingw()) {
210 // MS runtime is weird: it exports _setjmp, but longjmp!
211 setUseUnderscoreSetJmp(true);
212 setUseUnderscoreLongJmp(false);
214 setUseUnderscoreSetJmp(true);
215 setUseUnderscoreLongJmp(true);
218 // Set up the register classes.
219 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
220 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
221 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
222 if (Subtarget->is64Bit())
223 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
225 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
227 // We don't accept any truncstore of integer registers.
228 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
229 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
230 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
231 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
232 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
233 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
235 // SETOEQ and SETUNE require checking two conditions.
236 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
237 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
238 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
239 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
240 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
241 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
243 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
245 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
246 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
247 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
249 if (Subtarget->is64Bit()) {
250 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
252 } else if (!TM.Options.UseSoftFloat) {
253 // We have an algorithm for SSE2->double, and we turn this into a
254 // 64-bit FILD followed by conditional FADD for other targets.
255 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
256 // We have an algorithm for SSE2, and we turn this into a 64-bit
257 // FILD for other targets.
258 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
261 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
263 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
264 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
266 if (!TM.Options.UseSoftFloat) {
267 // SSE has no i16 to fp conversion, only i32
268 if (X86ScalarSSEf32) {
269 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
270 // f32 and f64 cases are Legal, f80 case is not
271 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
274 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
281 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
282 // are Legal, f80 is custom lowered.
283 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
284 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
286 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
288 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
289 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
291 if (X86ScalarSSEf32) {
292 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
293 // f32 and f64 cases are Legal, f80 case is not
294 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
296 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
297 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
300 // Handle FP_TO_UINT by promoting the destination to a larger signed
302 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
303 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
304 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
306 if (Subtarget->is64Bit()) {
307 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
309 } else if (!TM.Options.UseSoftFloat) {
310 // Since AVX is a superset of SSE3, only check for SSE here.
311 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
312 // Expand FP_TO_UINT into a select.
313 // FIXME: We would like to use a Custom expander here eventually to do
314 // the optimal thing for SSE vs. the default expansion in the legalizer.
315 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
317 // With SSE3 we can use fisttpll to convert to a signed i64; without
318 // SSE, we're stuck with a fistpll.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
322 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
323 if (!X86ScalarSSEf64) {
324 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
325 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
326 if (Subtarget->is64Bit()) {
327 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
328 // Without SSE, i64->f64 goes through memory.
329 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
333 // Scalar integer divide and remainder are lowered to use operations that
334 // produce two results, to match the available instructions. This exposes
335 // the two-result form to trivial CSE, which is able to combine x/y and x%y
336 // into a single instruction.
338 // Scalar integer multiply-high is also lowered to use two-result
339 // operations, to match the available instructions. However, plain multiply
340 // (low) operations are left as Legal, as there are single-result
341 // instructions for this in x86. Using the two-result multiply instructions
342 // when both high and low results are needed must be arranged by dagcombine.
343 for (unsigned i = 0, e = 4; i != e; ++i) {
345 setOperationAction(ISD::MULHS, VT, Expand);
346 setOperationAction(ISD::MULHU, VT, Expand);
347 setOperationAction(ISD::SDIV, VT, Expand);
348 setOperationAction(ISD::UDIV, VT, Expand);
349 setOperationAction(ISD::SREM, VT, Expand);
350 setOperationAction(ISD::UREM, VT, Expand);
352 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
353 setOperationAction(ISD::ADDC, VT, Custom);
354 setOperationAction(ISD::ADDE, VT, Custom);
355 setOperationAction(ISD::SUBC, VT, Custom);
356 setOperationAction(ISD::SUBE, VT, Custom);
359 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
360 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
361 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
362 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
363 if (Subtarget->is64Bit())
364 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
365 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
366 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
367 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
368 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
369 setOperationAction(ISD::FREM , MVT::f32 , Expand);
370 setOperationAction(ISD::FREM , MVT::f64 , Expand);
371 setOperationAction(ISD::FREM , MVT::f80 , Expand);
372 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
374 // Promote the i8 variants and force them on up to i32 which has a shorter
376 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
377 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
378 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
379 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
380 if (Subtarget->hasBMI()) {
381 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
382 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
383 if (Subtarget->is64Bit())
384 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
386 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
387 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
388 if (Subtarget->is64Bit())
389 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
392 if (Subtarget->hasLZCNT()) {
393 // When promoting the i8 variants, force them to i32 for a shorter
395 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
396 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
397 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
398 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
399 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
400 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
401 if (Subtarget->is64Bit())
402 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
404 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
405 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
406 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
410 if (Subtarget->is64Bit()) {
411 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
416 if (Subtarget->hasPOPCNT()) {
417 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
419 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
420 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
421 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
422 if (Subtarget->is64Bit())
423 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
426 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
427 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
429 // These should be promoted to a larger select which is supported.
430 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
431 // X86 wants to expand cmov itself.
432 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
433 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
434 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
435 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
436 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
437 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
438 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
439 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
440 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
441 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
442 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
443 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
444 if (Subtarget->is64Bit()) {
445 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
446 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
448 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
451 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
452 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
453 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
454 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
455 if (Subtarget->is64Bit())
456 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
457 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
458 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
459 if (Subtarget->is64Bit()) {
460 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
461 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
462 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
463 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
464 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
466 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
467 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
468 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
469 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
470 if (Subtarget->is64Bit()) {
471 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
472 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
473 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
476 if (Subtarget->hasSSE1())
477 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
479 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
480 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
482 // On X86 and X86-64, atomic operations are lowered to locked instructions.
483 // Locked instructions, in turn, have implicit fence semantics (all memory
484 // operations are flushed before issuing the locked instruction, and they
485 // are not buffered), so we can fold away the common pattern of
486 // fence-atomic-fence.
487 setShouldFoldAtomicFences(true);
489 // Expand certain atomics
490 for (unsigned i = 0, e = 4; i != e; ++i) {
492 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
493 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
494 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
497 if (!Subtarget->is64Bit()) {
498 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
499 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
500 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
501 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
502 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
503 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
508 if (Subtarget->hasCmpxchg16b()) {
509 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
512 // FIXME - use subtarget debug flags
513 if (!Subtarget->isTargetDarwin() &&
514 !Subtarget->isTargetELF() &&
515 !Subtarget->isTargetCygMing()) {
516 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
519 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
520 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
521 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
522 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
523 if (Subtarget->is64Bit()) {
524 setExceptionPointerRegister(X86::RAX);
525 setExceptionSelectorRegister(X86::RDX);
527 setExceptionPointerRegister(X86::EAX);
528 setExceptionSelectorRegister(X86::EDX);
530 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
531 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
533 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
534 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
536 setOperationAction(ISD::TRAP, MVT::Other, Legal);
538 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
539 setOperationAction(ISD::VASTART , MVT::Other, Custom);
540 setOperationAction(ISD::VAEND , MVT::Other, Expand);
541 if (Subtarget->is64Bit()) {
542 setOperationAction(ISD::VAARG , MVT::Other, Custom);
543 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
545 setOperationAction(ISD::VAARG , MVT::Other, Expand);
546 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
549 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
550 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
552 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
553 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
554 MVT::i64 : MVT::i32, Custom);
555 else if (TM.Options.EnableSegmentedStacks)
556 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
557 MVT::i64 : MVT::i32, Custom);
559 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
560 MVT::i64 : MVT::i32, Expand);
562 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
563 // f32 and f64 use SSE.
564 // Set up the FP register classes.
565 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
566 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
568 // Use ANDPD to simulate FABS.
569 setOperationAction(ISD::FABS , MVT::f64, Custom);
570 setOperationAction(ISD::FABS , MVT::f32, Custom);
572 // Use XORP to simulate FNEG.
573 setOperationAction(ISD::FNEG , MVT::f64, Custom);
574 setOperationAction(ISD::FNEG , MVT::f32, Custom);
576 // Use ANDPD and ORPD to simulate FCOPYSIGN.
577 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
578 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
580 // Lower this to FGETSIGNx86 plus an AND.
581 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
582 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
584 // We don't support sin/cos/fmod
585 setOperationAction(ISD::FSIN , MVT::f64, Expand);
586 setOperationAction(ISD::FCOS , MVT::f64, Expand);
587 setOperationAction(ISD::FSIN , MVT::f32, Expand);
588 setOperationAction(ISD::FCOS , MVT::f32, Expand);
590 // Expand FP immediates into loads from the stack, except for the special
592 addLegalFPImmediate(APFloat(+0.0)); // xorpd
593 addLegalFPImmediate(APFloat(+0.0f)); // xorps
594 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
595 // Use SSE for f32, x87 for f64.
596 // Set up the FP register classes.
597 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
598 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
600 // Use ANDPS to simulate FABS.
601 setOperationAction(ISD::FABS , MVT::f32, Custom);
603 // Use XORP to simulate FNEG.
604 setOperationAction(ISD::FNEG , MVT::f32, Custom);
606 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
608 // Use ANDPS and ORPS to simulate FCOPYSIGN.
609 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
610 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
612 // We don't support sin/cos/fmod
613 setOperationAction(ISD::FSIN , MVT::f32, Expand);
614 setOperationAction(ISD::FCOS , MVT::f32, Expand);
616 // Special cases we handle for FP constants.
617 addLegalFPImmediate(APFloat(+0.0f)); // xorps
618 addLegalFPImmediate(APFloat(+0.0)); // FLD0
619 addLegalFPImmediate(APFloat(+1.0)); // FLD1
620 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
621 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
623 if (!TM.Options.UnsafeFPMath) {
624 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
625 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
627 } else if (!TM.Options.UseSoftFloat) {
628 // f32 and f64 in x87.
629 // Set up the FP register classes.
630 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
631 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
633 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
634 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
635 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
636 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
638 if (!TM.Options.UnsafeFPMath) {
639 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
640 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
642 addLegalFPImmediate(APFloat(+0.0)); // FLD0
643 addLegalFPImmediate(APFloat(+1.0)); // FLD1
644 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
645 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
646 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
647 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
648 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
649 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
652 // We don't support FMA.
653 setOperationAction(ISD::FMA, MVT::f64, Expand);
654 setOperationAction(ISD::FMA, MVT::f32, Expand);
656 // Long double always uses X87.
657 if (!TM.Options.UseSoftFloat) {
658 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
659 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
660 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
662 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
663 addLegalFPImmediate(TmpFlt); // FLD0
665 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
668 APFloat TmpFlt2(+1.0);
669 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
671 addLegalFPImmediate(TmpFlt2); // FLD1
672 TmpFlt2.changeSign();
673 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
676 if (!TM.Options.UnsafeFPMath) {
677 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
678 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
681 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
682 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
683 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
684 setOperationAction(ISD::FRINT, MVT::f80, Expand);
685 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
686 setOperationAction(ISD::FMA, MVT::f80, Expand);
689 // Always use a library call for pow.
690 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
691 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
692 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
694 setOperationAction(ISD::FLOG, MVT::f80, Expand);
695 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
696 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
697 setOperationAction(ISD::FEXP, MVT::f80, Expand);
698 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
700 // First set operation action for all vector types to either promote
701 // (for widening) or expand (for scalarization). Then we will selectively
702 // turn on ones that can be effectively codegen'd.
703 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
704 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
705 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
720 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
722 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
723 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
757 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
762 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
763 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
764 setTruncStoreAction((MVT::SimpleValueType)VT,
765 (MVT::SimpleValueType)InnerVT, Expand);
766 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
767 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
768 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
771 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
772 // with -msoft-float, disable use of MMX as well.
773 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
774 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
775 // No operations on x86mmx supported, everything uses intrinsics.
778 // MMX-sized vectors (other than x86mmx) are expected to be expanded
779 // into smaller operations.
780 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
781 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
782 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
783 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
784 setOperationAction(ISD::AND, MVT::v8i8, Expand);
785 setOperationAction(ISD::AND, MVT::v4i16, Expand);
786 setOperationAction(ISD::AND, MVT::v2i32, Expand);
787 setOperationAction(ISD::AND, MVT::v1i64, Expand);
788 setOperationAction(ISD::OR, MVT::v8i8, Expand);
789 setOperationAction(ISD::OR, MVT::v4i16, Expand);
790 setOperationAction(ISD::OR, MVT::v2i32, Expand);
791 setOperationAction(ISD::OR, MVT::v1i64, Expand);
792 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
793 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
794 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
795 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
796 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
797 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
798 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
799 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
800 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
801 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
802 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
803 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
804 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
805 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
806 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
807 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
808 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
810 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
811 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
813 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
814 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
815 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
816 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
817 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
818 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
819 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
820 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
821 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
822 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
823 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
824 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
827 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
828 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
830 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
831 // registers cannot be used even for integer operations.
832 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
833 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
834 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
835 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
837 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
838 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
839 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
840 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
841 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
842 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
843 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
844 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
845 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
846 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
847 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
848 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
849 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
850 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
851 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
852 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
854 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
855 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
856 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
857 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
859 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
860 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
861 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
862 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
863 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
865 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
866 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
867 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
868 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
869 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
871 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
872 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
873 EVT VT = (MVT::SimpleValueType)i;
874 // Do not attempt to custom lower non-power-of-2 vectors
875 if (!isPowerOf2_32(VT.getVectorNumElements()))
877 // Do not attempt to custom lower non-128-bit vectors
878 if (!VT.is128BitVector())
880 setOperationAction(ISD::BUILD_VECTOR,
881 VT.getSimpleVT().SimpleTy, Custom);
882 setOperationAction(ISD::VECTOR_SHUFFLE,
883 VT.getSimpleVT().SimpleTy, Custom);
884 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
885 VT.getSimpleVT().SimpleTy, Custom);
888 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
890 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
892 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
893 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
895 if (Subtarget->is64Bit()) {
896 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
897 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
900 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
901 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
902 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
905 // Do not attempt to promote non-128-bit vectors
906 if (!VT.is128BitVector())
909 setOperationAction(ISD::AND, SVT, Promote);
910 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
911 setOperationAction(ISD::OR, SVT, Promote);
912 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
913 setOperationAction(ISD::XOR, SVT, Promote);
914 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
915 setOperationAction(ISD::LOAD, SVT, Promote);
916 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
917 setOperationAction(ISD::SELECT, SVT, Promote);
918 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
921 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
923 // Custom lower v2i64 and v2f64 selects.
924 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
925 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
926 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
927 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
929 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
930 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
933 if (Subtarget->hasSSE41()) {
934 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
935 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
936 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
937 setOperationAction(ISD::FRINT, MVT::f32, Legal);
938 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
939 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
940 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
941 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
942 setOperationAction(ISD::FRINT, MVT::f64, Legal);
943 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
945 // FIXME: Do we need to handle scalar-to-vector here?
946 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
948 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
949 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
950 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
951 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
952 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
954 // i8 and i16 vectors are custom , because the source register and source
955 // source memory operand types are not the same width. f32 vectors are
956 // custom since the immediate controlling the insert encodes additional
958 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
959 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
960 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
961 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
963 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
964 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
965 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
966 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
968 // FIXME: these should be Legal but thats only for the case where
969 // the index is constant. For now custom expand to deal with that.
970 if (Subtarget->is64Bit()) {
971 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
972 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
976 if (Subtarget->hasSSE2()) {
977 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
978 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
980 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
981 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
983 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
984 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
986 if (Subtarget->hasAVX2()) {
987 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
988 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
990 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
991 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
993 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
995 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
996 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
998 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
999 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1001 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1005 if (Subtarget->hasSSE42())
1006 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1008 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1009 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
1010 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
1011 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
1012 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
1013 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
1014 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
1016 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1017 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1018 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1020 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1021 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1022 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1023 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1024 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1025 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1027 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1028 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1029 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1030 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1031 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1032 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1034 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1035 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1036 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1038 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1039 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1040 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1041 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1042 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1045 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1046 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1048 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1049 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1051 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1052 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1054 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1055 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1056 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1057 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1059 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1060 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1061 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1063 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1068 if (Subtarget->hasAVX2()) {
1069 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1070 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1071 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1072 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1074 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1075 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1076 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1077 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1079 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1080 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1081 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1082 // Don't lower v32i8 because there is no 128-bit byte mul
1084 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1086 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1087 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1089 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1090 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1092 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1094 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1095 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1096 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1097 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1099 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1100 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1101 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1102 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1104 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1105 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1106 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1107 // Don't lower v32i8 because there is no 128-bit byte mul
1109 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1110 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1112 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1113 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1115 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1118 // Custom lower several nodes for 256-bit types.
1119 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1120 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1121 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1124 // Extract subvector is special because the value type
1125 // (result) is 128-bit but the source is 256-bit wide.
1126 if (VT.is128BitVector())
1127 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1129 // Do not attempt to custom lower other non-256-bit vectors
1130 if (!VT.is256BitVector())
1133 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1134 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1136 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1137 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1138 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1141 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1142 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1143 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1146 // Do not attempt to promote non-256-bit vectors
1147 if (!VT.is256BitVector())
1150 setOperationAction(ISD::AND, SVT, Promote);
1151 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1152 setOperationAction(ISD::OR, SVT, Promote);
1153 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1154 setOperationAction(ISD::XOR, SVT, Promote);
1155 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1156 setOperationAction(ISD::LOAD, SVT, Promote);
1157 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1158 setOperationAction(ISD::SELECT, SVT, Promote);
1159 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1163 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1164 // of this type with custom code.
1165 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1166 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1167 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1171 // We want to custom lower some of our intrinsics.
1172 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1175 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1176 // handle type legalization for these operations here.
1178 // FIXME: We really should do custom legalization for addition and
1179 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1180 // than generic legalization for 64-bit multiplication-with-overflow, though.
1181 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1182 // Add/Sub/Mul with overflow operations are custom lowered.
1184 setOperationAction(ISD::SADDO, VT, Custom);
1185 setOperationAction(ISD::UADDO, VT, Custom);
1186 setOperationAction(ISD::SSUBO, VT, Custom);
1187 setOperationAction(ISD::USUBO, VT, Custom);
1188 setOperationAction(ISD::SMULO, VT, Custom);
1189 setOperationAction(ISD::UMULO, VT, Custom);
1192 // There are no 8-bit 3-address imul/mul instructions
1193 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1194 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1196 if (!Subtarget->is64Bit()) {
1197 // These libcalls are not available in 32-bit.
1198 setLibcallName(RTLIB::SHL_I128, 0);
1199 setLibcallName(RTLIB::SRL_I128, 0);
1200 setLibcallName(RTLIB::SRA_I128, 0);
1203 // We have target-specific dag combine patterns for the following nodes:
1204 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1205 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1206 setTargetDAGCombine(ISD::VSELECT);
1207 setTargetDAGCombine(ISD::SELECT);
1208 setTargetDAGCombine(ISD::SHL);
1209 setTargetDAGCombine(ISD::SRA);
1210 setTargetDAGCombine(ISD::SRL);
1211 setTargetDAGCombine(ISD::OR);
1212 setTargetDAGCombine(ISD::AND);
1213 setTargetDAGCombine(ISD::ADD);
1214 setTargetDAGCombine(ISD::FADD);
1215 setTargetDAGCombine(ISD::FSUB);
1216 setTargetDAGCombine(ISD::SUB);
1217 setTargetDAGCombine(ISD::LOAD);
1218 setTargetDAGCombine(ISD::STORE);
1219 setTargetDAGCombine(ISD::ZERO_EXTEND);
1220 setTargetDAGCombine(ISD::SINT_TO_FP);
1221 if (Subtarget->is64Bit())
1222 setTargetDAGCombine(ISD::MUL);
1223 if (Subtarget->hasBMI())
1224 setTargetDAGCombine(ISD::XOR);
1226 computeRegisterProperties();
1228 // On Darwin, -Os means optimize for size without hurting performance,
1229 // do not reduce the limit.
1230 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1231 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1232 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1233 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1234 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1235 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1236 setPrefLoopAlignment(4); // 2^4 bytes.
1237 benefitFromCodePlacementOpt = true;
1239 setPrefFunctionAlignment(4); // 2^4 bytes.
1243 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1244 if (!VT.isVector()) return MVT::i8;
1245 return VT.changeVectorElementTypeToInteger();
1249 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1250 /// the desired ByVal argument alignment.
1251 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1254 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1255 if (VTy->getBitWidth() == 128)
1257 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1258 unsigned EltAlign = 0;
1259 getMaxByValAlign(ATy->getElementType(), EltAlign);
1260 if (EltAlign > MaxAlign)
1261 MaxAlign = EltAlign;
1262 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1263 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1264 unsigned EltAlign = 0;
1265 getMaxByValAlign(STy->getElementType(i), EltAlign);
1266 if (EltAlign > MaxAlign)
1267 MaxAlign = EltAlign;
1275 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1276 /// function arguments in the caller parameter area. For X86, aggregates
1277 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1278 /// are at 4-byte boundaries.
1279 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1280 if (Subtarget->is64Bit()) {
1281 // Max of 8 and alignment of type.
1282 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1289 if (Subtarget->hasSSE1())
1290 getMaxByValAlign(Ty, Align);
1294 /// getOptimalMemOpType - Returns the target specific optimal type for load
1295 /// and store operations as a result of memset, memcpy, and memmove
1296 /// lowering. If DstAlign is zero that means it's safe to destination
1297 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1298 /// means there isn't a need to check it against alignment requirement,
1299 /// probably because the source does not need to be loaded. If
1300 /// 'IsZeroVal' is true, that means it's safe to return a
1301 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1302 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1303 /// constant so it does not need to be loaded.
1304 /// It returns EVT::Other if the type should be determined using generic
1305 /// target-independent logic.
1307 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1308 unsigned DstAlign, unsigned SrcAlign,
1311 MachineFunction &MF) const {
1312 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1313 // linux. This is because the stack realignment code can't handle certain
1314 // cases like PR2962. This should be removed when PR2962 is fixed.
1315 const Function *F = MF.getFunction();
1317 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1319 (Subtarget->isUnalignedMemAccessFast() ||
1320 ((DstAlign == 0 || DstAlign >= 16) &&
1321 (SrcAlign == 0 || SrcAlign >= 16))) &&
1322 Subtarget->getStackAlignment() >= 16) {
1323 if (Subtarget->getStackAlignment() >= 32) {
1324 if (Subtarget->hasAVX2())
1326 if (Subtarget->hasAVX())
1329 if (Subtarget->hasSSE2())
1331 if (Subtarget->hasSSE1())
1333 } else if (!MemcpyStrSrc && Size >= 8 &&
1334 !Subtarget->is64Bit() &&
1335 Subtarget->getStackAlignment() >= 8 &&
1336 Subtarget->hasSSE2()) {
1337 // Do not use f64 to lower memcpy if source is string constant. It's
1338 // better to use i32 to avoid the loads.
1342 if (Subtarget->is64Bit() && Size >= 8)
1347 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1348 /// current function. The returned value is a member of the
1349 /// MachineJumpTableInfo::JTEntryKind enum.
1350 unsigned X86TargetLowering::getJumpTableEncoding() const {
1351 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1353 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1354 Subtarget->isPICStyleGOT())
1355 return MachineJumpTableInfo::EK_Custom32;
1357 // Otherwise, use the normal jump table encoding heuristics.
1358 return TargetLowering::getJumpTableEncoding();
1362 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1363 const MachineBasicBlock *MBB,
1364 unsigned uid,MCContext &Ctx) const{
1365 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1366 Subtarget->isPICStyleGOT());
1367 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1369 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1370 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1373 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1375 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1376 SelectionDAG &DAG) const {
1377 if (!Subtarget->is64Bit())
1378 // This doesn't have DebugLoc associated with it, but is not really the
1379 // same as a Register.
1380 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1384 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1385 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1387 const MCExpr *X86TargetLowering::
1388 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1389 MCContext &Ctx) const {
1390 // X86-64 uses RIP relative addressing based on the jump table label.
1391 if (Subtarget->isPICStyleRIPRel())
1392 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1394 // Otherwise, the reference is relative to the PIC base.
1395 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1398 // FIXME: Why this routine is here? Move to RegInfo!
1399 std::pair<const TargetRegisterClass*, uint8_t>
1400 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1401 const TargetRegisterClass *RRC = 0;
1403 switch (VT.getSimpleVT().SimpleTy) {
1405 return TargetLowering::findRepresentativeClass(VT);
1406 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1407 RRC = (Subtarget->is64Bit()
1408 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1411 RRC = X86::VR64RegisterClass;
1413 case MVT::f32: case MVT::f64:
1414 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1415 case MVT::v4f32: case MVT::v2f64:
1416 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1418 RRC = X86::VR128RegisterClass;
1421 return std::make_pair(RRC, Cost);
1424 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1425 unsigned &Offset) const {
1426 if (!Subtarget->isTargetLinux())
1429 if (Subtarget->is64Bit()) {
1430 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1432 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1445 //===----------------------------------------------------------------------===//
1446 // Return Value Calling Convention Implementation
1447 //===----------------------------------------------------------------------===//
1449 #include "X86GenCallingConv.inc"
1452 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1453 MachineFunction &MF, bool isVarArg,
1454 const SmallVectorImpl<ISD::OutputArg> &Outs,
1455 LLVMContext &Context) const {
1456 SmallVector<CCValAssign, 16> RVLocs;
1457 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1459 return CCInfo.CheckReturn(Outs, RetCC_X86);
1463 X86TargetLowering::LowerReturn(SDValue Chain,
1464 CallingConv::ID CallConv, bool isVarArg,
1465 const SmallVectorImpl<ISD::OutputArg> &Outs,
1466 const SmallVectorImpl<SDValue> &OutVals,
1467 DebugLoc dl, SelectionDAG &DAG) const {
1468 MachineFunction &MF = DAG.getMachineFunction();
1469 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1471 SmallVector<CCValAssign, 16> RVLocs;
1472 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1473 RVLocs, *DAG.getContext());
1474 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1476 // Add the regs to the liveout set for the function.
1477 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1478 for (unsigned i = 0; i != RVLocs.size(); ++i)
1479 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1480 MRI.addLiveOut(RVLocs[i].getLocReg());
1484 SmallVector<SDValue, 6> RetOps;
1485 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1486 // Operand #1 = Bytes To Pop
1487 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1490 // Copy the result values into the output registers.
1491 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1492 CCValAssign &VA = RVLocs[i];
1493 assert(VA.isRegLoc() && "Can only return in registers!");
1494 SDValue ValToCopy = OutVals[i];
1495 EVT ValVT = ValToCopy.getValueType();
1497 // If this is x86-64, and we disabled SSE, we can't return FP values,
1498 // or SSE or MMX vectors.
1499 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1500 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1501 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1502 report_fatal_error("SSE register return with SSE disabled");
1504 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1505 // llvm-gcc has never done it right and no one has noticed, so this
1506 // should be OK for now.
1507 if (ValVT == MVT::f64 &&
1508 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1509 report_fatal_error("SSE2 register return with SSE2 disabled");
1511 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1512 // the RET instruction and handled by the FP Stackifier.
1513 if (VA.getLocReg() == X86::ST0 ||
1514 VA.getLocReg() == X86::ST1) {
1515 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1516 // change the value to the FP stack register class.
1517 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1518 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1519 RetOps.push_back(ValToCopy);
1520 // Don't emit a copytoreg.
1524 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1525 // which is returned in RAX / RDX.
1526 if (Subtarget->is64Bit()) {
1527 if (ValVT == MVT::x86mmx) {
1528 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1529 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1530 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1532 // If we don't have SSE2 available, convert to v4f32 so the generated
1533 // register is legal.
1534 if (!Subtarget->hasSSE2())
1535 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1540 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1541 Flag = Chain.getValue(1);
1544 // The x86-64 ABI for returning structs by value requires that we copy
1545 // the sret argument into %rax for the return. We saved the argument into
1546 // a virtual register in the entry block, so now we copy the value out
1548 if (Subtarget->is64Bit() &&
1549 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1550 MachineFunction &MF = DAG.getMachineFunction();
1551 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1552 unsigned Reg = FuncInfo->getSRetReturnReg();
1554 "SRetReturnReg should have been set in LowerFormalArguments().");
1555 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1557 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1558 Flag = Chain.getValue(1);
1560 // RAX now acts like a return value.
1561 MRI.addLiveOut(X86::RAX);
1564 RetOps[0] = Chain; // Update chain.
1566 // Add the flag if we have it.
1568 RetOps.push_back(Flag);
1570 return DAG.getNode(X86ISD::RET_FLAG, dl,
1571 MVT::Other, &RetOps[0], RetOps.size());
1574 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1575 if (N->getNumValues() != 1)
1577 if (!N->hasNUsesOfValue(1, 0))
1580 SDNode *Copy = *N->use_begin();
1581 if (Copy->getOpcode() != ISD::CopyToReg &&
1582 Copy->getOpcode() != ISD::FP_EXTEND)
1585 bool HasRet = false;
1586 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1588 if (UI->getOpcode() != X86ISD::RET_FLAG)
1597 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1598 ISD::NodeType ExtendKind) const {
1600 // TODO: Is this also valid on 32-bit?
1601 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1602 ReturnMVT = MVT::i8;
1604 ReturnMVT = MVT::i32;
1606 EVT MinVT = getRegisterType(Context, ReturnMVT);
1607 return VT.bitsLT(MinVT) ? MinVT : VT;
1610 /// LowerCallResult - Lower the result values of a call into the
1611 /// appropriate copies out of appropriate physical registers.
1614 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1615 CallingConv::ID CallConv, bool isVarArg,
1616 const SmallVectorImpl<ISD::InputArg> &Ins,
1617 DebugLoc dl, SelectionDAG &DAG,
1618 SmallVectorImpl<SDValue> &InVals) const {
1620 // Assign locations to each value returned by this call.
1621 SmallVector<CCValAssign, 16> RVLocs;
1622 bool Is64Bit = Subtarget->is64Bit();
1623 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1624 getTargetMachine(), RVLocs, *DAG.getContext());
1625 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1627 // Copy all of the result registers out of their specified physreg.
1628 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1629 CCValAssign &VA = RVLocs[i];
1630 EVT CopyVT = VA.getValVT();
1632 // If this is x86-64, and we disabled SSE, we can't return FP values
1633 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1634 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1635 report_fatal_error("SSE register return with SSE disabled");
1640 // If this is a call to a function that returns an fp value on the floating
1641 // point stack, we must guarantee the the value is popped from the stack, so
1642 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1643 // if the return value is not used. We use the FpPOP_RETVAL instruction
1645 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1646 // If we prefer to use the value in xmm registers, copy it out as f80 and
1647 // use a truncate to move it from fp stack reg to xmm reg.
1648 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1649 SDValue Ops[] = { Chain, InFlag };
1650 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1651 MVT::Other, MVT::Glue, Ops, 2), 1);
1652 Val = Chain.getValue(0);
1654 // Round the f80 to the right size, which also moves it to the appropriate
1656 if (CopyVT != VA.getValVT())
1657 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1658 // This truncation won't change the value.
1659 DAG.getIntPtrConstant(1));
1661 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1662 CopyVT, InFlag).getValue(1);
1663 Val = Chain.getValue(0);
1665 InFlag = Chain.getValue(2);
1666 InVals.push_back(Val);
1673 //===----------------------------------------------------------------------===//
1674 // C & StdCall & Fast Calling Convention implementation
1675 //===----------------------------------------------------------------------===//
1676 // StdCall calling convention seems to be standard for many Windows' API
1677 // routines and around. It differs from C calling convention just a little:
1678 // callee should clean up the stack, not caller. Symbols should be also
1679 // decorated in some fancy way :) It doesn't support any vector arguments.
1680 // For info on fast calling convention see Fast Calling Convention (tail call)
1681 // implementation LowerX86_32FastCCCallTo.
1683 /// CallIsStructReturn - Determines whether a call uses struct return
1685 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1689 return Outs[0].Flags.isSRet();
1692 /// ArgsAreStructReturn - Determines whether a function uses struct
1693 /// return semantics.
1695 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1699 return Ins[0].Flags.isSRet();
1702 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1703 /// by "Src" to address "Dst" with size and alignment information specified by
1704 /// the specific parameter attribute. The copy will be passed as a byval
1705 /// function parameter.
1707 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1708 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1710 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1712 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1713 /*isVolatile*/false, /*AlwaysInline=*/true,
1714 MachinePointerInfo(), MachinePointerInfo());
1717 /// IsTailCallConvention - Return true if the calling convention is one that
1718 /// supports tail call optimization.
1719 static bool IsTailCallConvention(CallingConv::ID CC) {
1720 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1723 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1724 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1728 CallingConv::ID CalleeCC = CS.getCallingConv();
1729 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1735 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1736 /// a tailcall target by changing its ABI.
1737 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1738 bool GuaranteedTailCallOpt) {
1739 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1743 X86TargetLowering::LowerMemArgument(SDValue Chain,
1744 CallingConv::ID CallConv,
1745 const SmallVectorImpl<ISD::InputArg> &Ins,
1746 DebugLoc dl, SelectionDAG &DAG,
1747 const CCValAssign &VA,
1748 MachineFrameInfo *MFI,
1750 // Create the nodes corresponding to a load from this parameter slot.
1751 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1752 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1753 getTargetMachine().Options.GuaranteedTailCallOpt);
1754 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1757 // If value is passed by pointer we have address passed instead of the value
1759 if (VA.getLocInfo() == CCValAssign::Indirect)
1760 ValVT = VA.getLocVT();
1762 ValVT = VA.getValVT();
1764 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1765 // changed with more analysis.
1766 // In case of tail call optimization mark all arguments mutable. Since they
1767 // could be overwritten by lowering of arguments in case of a tail call.
1768 if (Flags.isByVal()) {
1769 unsigned Bytes = Flags.getByValSize();
1770 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1771 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1772 return DAG.getFrameIndex(FI, getPointerTy());
1774 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1775 VA.getLocMemOffset(), isImmutable);
1776 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1777 return DAG.getLoad(ValVT, dl, Chain, FIN,
1778 MachinePointerInfo::getFixedStack(FI),
1779 false, false, false, 0);
1784 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1785 CallingConv::ID CallConv,
1787 const SmallVectorImpl<ISD::InputArg> &Ins,
1790 SmallVectorImpl<SDValue> &InVals)
1792 MachineFunction &MF = DAG.getMachineFunction();
1793 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1795 const Function* Fn = MF.getFunction();
1796 if (Fn->hasExternalLinkage() &&
1797 Subtarget->isTargetCygMing() &&
1798 Fn->getName() == "main")
1799 FuncInfo->setForceFramePointer(true);
1801 MachineFrameInfo *MFI = MF.getFrameInfo();
1802 bool Is64Bit = Subtarget->is64Bit();
1803 bool IsWindows = Subtarget->isTargetWindows();
1804 bool IsWin64 = Subtarget->isTargetWin64();
1806 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1807 "Var args not supported with calling convention fastcc or ghc");
1809 // Assign locations to all of the incoming arguments.
1810 SmallVector<CCValAssign, 16> ArgLocs;
1811 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1812 ArgLocs, *DAG.getContext());
1814 // Allocate shadow area for Win64
1816 CCInfo.AllocateStack(32, 8);
1819 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1821 unsigned LastVal = ~0U;
1823 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1824 CCValAssign &VA = ArgLocs[i];
1825 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1827 assert(VA.getValNo() != LastVal &&
1828 "Don't support value assigned to multiple locs yet");
1830 LastVal = VA.getValNo();
1832 if (VA.isRegLoc()) {
1833 EVT RegVT = VA.getLocVT();
1834 TargetRegisterClass *RC = NULL;
1835 if (RegVT == MVT::i32)
1836 RC = X86::GR32RegisterClass;
1837 else if (Is64Bit && RegVT == MVT::i64)
1838 RC = X86::GR64RegisterClass;
1839 else if (RegVT == MVT::f32)
1840 RC = X86::FR32RegisterClass;
1841 else if (RegVT == MVT::f64)
1842 RC = X86::FR64RegisterClass;
1843 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1844 RC = X86::VR256RegisterClass;
1845 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1846 RC = X86::VR128RegisterClass;
1847 else if (RegVT == MVT::x86mmx)
1848 RC = X86::VR64RegisterClass;
1850 llvm_unreachable("Unknown argument type!");
1852 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1853 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1855 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1856 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1858 if (VA.getLocInfo() == CCValAssign::SExt)
1859 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1860 DAG.getValueType(VA.getValVT()));
1861 else if (VA.getLocInfo() == CCValAssign::ZExt)
1862 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1863 DAG.getValueType(VA.getValVT()));
1864 else if (VA.getLocInfo() == CCValAssign::BCvt)
1865 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1867 if (VA.isExtInLoc()) {
1868 // Handle MMX values passed in XMM regs.
1869 if (RegVT.isVector()) {
1870 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1873 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1876 assert(VA.isMemLoc());
1877 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1880 // If value is passed via pointer - do a load.
1881 if (VA.getLocInfo() == CCValAssign::Indirect)
1882 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1883 MachinePointerInfo(), false, false, false, 0);
1885 InVals.push_back(ArgValue);
1888 // The x86-64 ABI for returning structs by value requires that we copy
1889 // the sret argument into %rax for the return. Save the argument into
1890 // a virtual register so that we can access it from the return points.
1891 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1892 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1893 unsigned Reg = FuncInfo->getSRetReturnReg();
1895 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1896 FuncInfo->setSRetReturnReg(Reg);
1898 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1899 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1902 unsigned StackSize = CCInfo.getNextStackOffset();
1903 // Align stack specially for tail calls.
1904 if (FuncIsMadeTailCallSafe(CallConv,
1905 MF.getTarget().Options.GuaranteedTailCallOpt))
1906 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1908 // If the function takes variable number of arguments, make a frame index for
1909 // the start of the first vararg value... for expansion of llvm.va_start.
1911 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1912 CallConv != CallingConv::X86_ThisCall)) {
1913 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1916 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1918 // FIXME: We should really autogenerate these arrays
1919 static const unsigned GPR64ArgRegsWin64[] = {
1920 X86::RCX, X86::RDX, X86::R8, X86::R9
1922 static const unsigned GPR64ArgRegs64Bit[] = {
1923 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1925 static const unsigned XMMArgRegs64Bit[] = {
1926 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1927 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1929 const unsigned *GPR64ArgRegs;
1930 unsigned NumXMMRegs = 0;
1933 // The XMM registers which might contain var arg parameters are shadowed
1934 // in their paired GPR. So we only need to save the GPR to their home
1936 TotalNumIntRegs = 4;
1937 GPR64ArgRegs = GPR64ArgRegsWin64;
1939 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1940 GPR64ArgRegs = GPR64ArgRegs64Bit;
1942 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1945 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1948 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1949 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1950 "SSE register cannot be used when SSE is disabled!");
1951 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1952 NoImplicitFloatOps) &&
1953 "SSE register cannot be used when SSE is disabled!");
1954 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1955 !Subtarget->hasSSE1())
1956 // Kernel mode asks for SSE to be disabled, so don't push them
1958 TotalNumXMMRegs = 0;
1961 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1962 // Get to the caller-allocated home save location. Add 8 to account
1963 // for the return address.
1964 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1965 FuncInfo->setRegSaveFrameIndex(
1966 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1967 // Fixup to set vararg frame on shadow area (4 x i64).
1969 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1971 // For X86-64, if there are vararg parameters that are passed via
1972 // registers, then we must store them to their spots on the stack so
1973 // they may be loaded by deferencing the result of va_next.
1974 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1975 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1976 FuncInfo->setRegSaveFrameIndex(
1977 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1981 // Store the integer parameter registers.
1982 SmallVector<SDValue, 8> MemOps;
1983 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1985 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1986 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1987 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1988 DAG.getIntPtrConstant(Offset));
1989 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1990 X86::GR64RegisterClass);
1991 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1993 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1994 MachinePointerInfo::getFixedStack(
1995 FuncInfo->getRegSaveFrameIndex(), Offset),
1997 MemOps.push_back(Store);
2001 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2002 // Now store the XMM (fp + vector) parameter registers.
2003 SmallVector<SDValue, 11> SaveXMMOps;
2004 SaveXMMOps.push_back(Chain);
2006 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
2007 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2008 SaveXMMOps.push_back(ALVal);
2010 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2011 FuncInfo->getRegSaveFrameIndex()));
2012 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2013 FuncInfo->getVarArgsFPOffset()));
2015 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2016 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2017 X86::VR128RegisterClass);
2018 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2019 SaveXMMOps.push_back(Val);
2021 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2023 &SaveXMMOps[0], SaveXMMOps.size()));
2026 if (!MemOps.empty())
2027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2028 &MemOps[0], MemOps.size());
2032 // Some CCs need callee pop.
2033 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2034 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2035 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2037 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2038 // If this is an sret function, the return should pop the hidden pointer.
2039 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2040 ArgsAreStructReturn(Ins))
2041 FuncInfo->setBytesToPopOnReturn(4);
2045 // RegSaveFrameIndex is X86-64 only.
2046 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2047 if (CallConv == CallingConv::X86_FastCall ||
2048 CallConv == CallingConv::X86_ThisCall)
2049 // fastcc functions can't have varargs.
2050 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2053 FuncInfo->setArgumentStackSize(StackSize);
2059 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2060 SDValue StackPtr, SDValue Arg,
2061 DebugLoc dl, SelectionDAG &DAG,
2062 const CCValAssign &VA,
2063 ISD::ArgFlagsTy Flags) const {
2064 unsigned LocMemOffset = VA.getLocMemOffset();
2065 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2066 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2067 if (Flags.isByVal())
2068 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2070 return DAG.getStore(Chain, dl, Arg, PtrOff,
2071 MachinePointerInfo::getStack(LocMemOffset),
2075 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2076 /// optimization is performed and it is required.
2078 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2079 SDValue &OutRetAddr, SDValue Chain,
2080 bool IsTailCall, bool Is64Bit,
2081 int FPDiff, DebugLoc dl) const {
2082 // Adjust the Return address stack slot.
2083 EVT VT = getPointerTy();
2084 OutRetAddr = getReturnAddressFrameIndex(DAG);
2086 // Load the "old" Return address.
2087 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2088 false, false, false, 0);
2089 return SDValue(OutRetAddr.getNode(), 1);
2092 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2093 /// optimization is performed and it is required (FPDiff!=0).
2095 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2096 SDValue Chain, SDValue RetAddrFrIdx,
2097 bool Is64Bit, int FPDiff, DebugLoc dl) {
2098 // Store the return address to the appropriate stack slot.
2099 if (!FPDiff) return Chain;
2100 // Calculate the new stack slot for the return address.
2101 int SlotSize = Is64Bit ? 8 : 4;
2102 int NewReturnAddrFI =
2103 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2104 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2105 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2106 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2107 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2113 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2114 CallingConv::ID CallConv, bool isVarArg,
2116 const SmallVectorImpl<ISD::OutputArg> &Outs,
2117 const SmallVectorImpl<SDValue> &OutVals,
2118 const SmallVectorImpl<ISD::InputArg> &Ins,
2119 DebugLoc dl, SelectionDAG &DAG,
2120 SmallVectorImpl<SDValue> &InVals) const {
2121 MachineFunction &MF = DAG.getMachineFunction();
2122 bool Is64Bit = Subtarget->is64Bit();
2123 bool IsWin64 = Subtarget->isTargetWin64();
2124 bool IsWindows = Subtarget->isTargetWindows();
2125 bool IsStructRet = CallIsStructReturn(Outs);
2126 bool IsSibcall = false;
2128 if (MF.getTarget().Options.DisableTailCalls)
2132 // Check if it's really possible to do a tail call.
2133 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2134 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2135 Outs, OutVals, Ins, DAG);
2137 // Sibcalls are automatically detected tailcalls which do not require
2139 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2146 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2147 "Var args not supported with calling convention fastcc or ghc");
2149 // Analyze operands of the call, assigning locations to each operand.
2150 SmallVector<CCValAssign, 16> ArgLocs;
2151 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2152 ArgLocs, *DAG.getContext());
2154 // Allocate shadow area for Win64
2156 CCInfo.AllocateStack(32, 8);
2159 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2161 // Get a count of how many bytes are to be pushed on the stack.
2162 unsigned NumBytes = CCInfo.getNextStackOffset();
2164 // This is a sibcall. The memory operands are available in caller's
2165 // own caller's stack.
2167 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2168 IsTailCallConvention(CallConv))
2169 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2172 if (isTailCall && !IsSibcall) {
2173 // Lower arguments at fp - stackoffset + fpdiff.
2174 unsigned NumBytesCallerPushed =
2175 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2176 FPDiff = NumBytesCallerPushed - NumBytes;
2178 // Set the delta of movement of the returnaddr stackslot.
2179 // But only set if delta is greater than previous delta.
2180 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2181 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2185 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2187 SDValue RetAddrFrIdx;
2188 // Load return address for tail calls.
2189 if (isTailCall && FPDiff)
2190 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2191 Is64Bit, FPDiff, dl);
2193 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2194 SmallVector<SDValue, 8> MemOpChains;
2197 // Walk the register/memloc assignments, inserting copies/loads. In the case
2198 // of tail call optimization arguments are handle later.
2199 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2200 CCValAssign &VA = ArgLocs[i];
2201 EVT RegVT = VA.getLocVT();
2202 SDValue Arg = OutVals[i];
2203 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2204 bool isByVal = Flags.isByVal();
2206 // Promote the value if needed.
2207 switch (VA.getLocInfo()) {
2208 default: llvm_unreachable("Unknown loc info!");
2209 case CCValAssign::Full: break;
2210 case CCValAssign::SExt:
2211 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2213 case CCValAssign::ZExt:
2214 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2216 case CCValAssign::AExt:
2217 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2218 // Special case: passing MMX values in XMM registers.
2219 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2220 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2221 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2223 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2225 case CCValAssign::BCvt:
2226 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2228 case CCValAssign::Indirect: {
2229 // Store the argument.
2230 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2231 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2232 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2233 MachinePointerInfo::getFixedStack(FI),
2240 if (VA.isRegLoc()) {
2241 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2242 if (isVarArg && IsWin64) {
2243 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2244 // shadow reg if callee is a varargs function.
2245 unsigned ShadowReg = 0;
2246 switch (VA.getLocReg()) {
2247 case X86::XMM0: ShadowReg = X86::RCX; break;
2248 case X86::XMM1: ShadowReg = X86::RDX; break;
2249 case X86::XMM2: ShadowReg = X86::R8; break;
2250 case X86::XMM3: ShadowReg = X86::R9; break;
2253 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2255 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2256 assert(VA.isMemLoc());
2257 if (StackPtr.getNode() == 0)
2258 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2259 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2260 dl, DAG, VA, Flags));
2264 if (!MemOpChains.empty())
2265 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2266 &MemOpChains[0], MemOpChains.size());
2268 // Build a sequence of copy-to-reg nodes chained together with token chain
2269 // and flag operands which copy the outgoing args into registers.
2271 // Tail call byval lowering might overwrite argument registers so in case of
2272 // tail call optimization the copies to registers are lowered later.
2274 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2275 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2276 RegsToPass[i].second, InFlag);
2277 InFlag = Chain.getValue(1);
2280 if (Subtarget->isPICStyleGOT()) {
2281 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2284 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2285 DAG.getNode(X86ISD::GlobalBaseReg,
2286 DebugLoc(), getPointerTy()),
2288 InFlag = Chain.getValue(1);
2290 // If we are tail calling and generating PIC/GOT style code load the
2291 // address of the callee into ECX. The value in ecx is used as target of
2292 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2293 // for tail calls on PIC/GOT architectures. Normally we would just put the
2294 // address of GOT into ebx and then call target@PLT. But for tail calls
2295 // ebx would be restored (since ebx is callee saved) before jumping to the
2298 // Note: The actual moving to ECX is done further down.
2299 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2300 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2301 !G->getGlobal()->hasProtectedVisibility())
2302 Callee = LowerGlobalAddress(Callee, DAG);
2303 else if (isa<ExternalSymbolSDNode>(Callee))
2304 Callee = LowerExternalSymbol(Callee, DAG);
2308 if (Is64Bit && isVarArg && !IsWin64) {
2309 // From AMD64 ABI document:
2310 // For calls that may call functions that use varargs or stdargs
2311 // (prototype-less calls or calls to functions containing ellipsis (...) in
2312 // the declaration) %al is used as hidden argument to specify the number
2313 // of SSE registers used. The contents of %al do not need to match exactly
2314 // the number of registers, but must be an ubound on the number of SSE
2315 // registers used and is in the range 0 - 8 inclusive.
2317 // Count the number of XMM registers allocated.
2318 static const unsigned XMMArgRegs[] = {
2319 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2320 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2322 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2323 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2324 && "SSE registers cannot be used when SSE is disabled");
2326 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2327 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2328 InFlag = Chain.getValue(1);
2332 // For tail calls lower the arguments to the 'real' stack slot.
2334 // Force all the incoming stack arguments to be loaded from the stack
2335 // before any new outgoing arguments are stored to the stack, because the
2336 // outgoing stack slots may alias the incoming argument stack slots, and
2337 // the alias isn't otherwise explicit. This is slightly more conservative
2338 // than necessary, because it means that each store effectively depends
2339 // on every argument instead of just those arguments it would clobber.
2340 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2342 SmallVector<SDValue, 8> MemOpChains2;
2345 // Do not flag preceding copytoreg stuff together with the following stuff.
2347 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2348 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2349 CCValAssign &VA = ArgLocs[i];
2352 assert(VA.isMemLoc());
2353 SDValue Arg = OutVals[i];
2354 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2355 // Create frame index.
2356 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2357 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2358 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2359 FIN = DAG.getFrameIndex(FI, getPointerTy());
2361 if (Flags.isByVal()) {
2362 // Copy relative to framepointer.
2363 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2364 if (StackPtr.getNode() == 0)
2365 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2367 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2369 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2373 // Store relative to framepointer.
2374 MemOpChains2.push_back(
2375 DAG.getStore(ArgChain, dl, Arg, FIN,
2376 MachinePointerInfo::getFixedStack(FI),
2382 if (!MemOpChains2.empty())
2383 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2384 &MemOpChains2[0], MemOpChains2.size());
2386 // Copy arguments to their registers.
2387 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2388 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2389 RegsToPass[i].second, InFlag);
2390 InFlag = Chain.getValue(1);
2394 // Store the return address to the appropriate stack slot.
2395 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2399 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2400 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2401 // In the 64-bit large code model, we have to make all calls
2402 // through a register, since the call instruction's 32-bit
2403 // pc-relative offset may not be large enough to hold the whole
2405 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2406 // If the callee is a GlobalAddress node (quite common, every direct call
2407 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2410 // We should use extra load for direct calls to dllimported functions in
2412 const GlobalValue *GV = G->getGlobal();
2413 if (!GV->hasDLLImportLinkage()) {
2414 unsigned char OpFlags = 0;
2415 bool ExtraLoad = false;
2416 unsigned WrapperKind = ISD::DELETED_NODE;
2418 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2419 // external symbols most go through the PLT in PIC mode. If the symbol
2420 // has hidden or protected visibility, or if it is static or local, then
2421 // we don't need to use the PLT - we can directly call it.
2422 if (Subtarget->isTargetELF() &&
2423 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2424 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2425 OpFlags = X86II::MO_PLT;
2426 } else if (Subtarget->isPICStyleStubAny() &&
2427 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2428 (!Subtarget->getTargetTriple().isMacOSX() ||
2429 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2430 // PC-relative references to external symbols should go through $stub,
2431 // unless we're building with the leopard linker or later, which
2432 // automatically synthesizes these stubs.
2433 OpFlags = X86II::MO_DARWIN_STUB;
2434 } else if (Subtarget->isPICStyleRIPRel() &&
2435 isa<Function>(GV) &&
2436 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2437 // If the function is marked as non-lazy, generate an indirect call
2438 // which loads from the GOT directly. This avoids runtime overhead
2439 // at the cost of eager binding (and one extra byte of encoding).
2440 OpFlags = X86II::MO_GOTPCREL;
2441 WrapperKind = X86ISD::WrapperRIP;
2445 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2446 G->getOffset(), OpFlags);
2448 // Add a wrapper if needed.
2449 if (WrapperKind != ISD::DELETED_NODE)
2450 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2451 // Add extra indirection if needed.
2453 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2454 MachinePointerInfo::getGOT(),
2455 false, false, false, 0);
2457 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2458 unsigned char OpFlags = 0;
2460 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2461 // external symbols should go through the PLT.
2462 if (Subtarget->isTargetELF() &&
2463 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2464 OpFlags = X86II::MO_PLT;
2465 } else if (Subtarget->isPICStyleStubAny() &&
2466 (!Subtarget->getTargetTriple().isMacOSX() ||
2467 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2468 // PC-relative references to external symbols should go through $stub,
2469 // unless we're building with the leopard linker or later, which
2470 // automatically synthesizes these stubs.
2471 OpFlags = X86II::MO_DARWIN_STUB;
2474 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2478 // Returns a chain & a flag for retval copy to use.
2479 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2480 SmallVector<SDValue, 8> Ops;
2482 if (!IsSibcall && isTailCall) {
2483 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2484 DAG.getIntPtrConstant(0, true), InFlag);
2485 InFlag = Chain.getValue(1);
2488 Ops.push_back(Chain);
2489 Ops.push_back(Callee);
2492 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2494 // Add argument registers to the end of the list so that they are known live
2496 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2497 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2498 RegsToPass[i].second.getValueType()));
2500 // Add an implicit use GOT pointer in EBX.
2501 if (!isTailCall && Subtarget->isPICStyleGOT())
2502 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2504 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2505 if (Is64Bit && isVarArg && !IsWin64)
2506 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2508 // Experimental: Add a register mask operand representing the call-preserved
2511 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2512 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2513 Ops.push_back(DAG.getRegisterMask(Mask));
2516 if (InFlag.getNode())
2517 Ops.push_back(InFlag);
2521 //// If this is the first return lowered for this function, add the regs
2522 //// to the liveout set for the function.
2523 // This isn't right, although it's probably harmless on x86; liveouts
2524 // should be computed from returns not tail calls. Consider a void
2525 // function making a tail call to a function returning int.
2526 return DAG.getNode(X86ISD::TC_RETURN, dl,
2527 NodeTys, &Ops[0], Ops.size());
2530 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2531 InFlag = Chain.getValue(1);
2533 // Create the CALLSEQ_END node.
2534 unsigned NumBytesForCalleeToPush;
2535 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2536 getTargetMachine().Options.GuaranteedTailCallOpt))
2537 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2538 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2540 // If this is a call to a struct-return function, the callee
2541 // pops the hidden struct pointer, so we have to push it back.
2542 // This is common for Darwin/X86, Linux & Mingw32 targets.
2543 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2544 NumBytesForCalleeToPush = 4;
2546 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2548 // Returns a flag for retval copy to use.
2550 Chain = DAG.getCALLSEQ_END(Chain,
2551 DAG.getIntPtrConstant(NumBytes, true),
2552 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2555 InFlag = Chain.getValue(1);
2558 // Handle result values, copying them out of physregs into vregs that we
2560 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2561 Ins, dl, DAG, InVals);
2565 //===----------------------------------------------------------------------===//
2566 // Fast Calling Convention (tail call) implementation
2567 //===----------------------------------------------------------------------===//
2569 // Like std call, callee cleans arguments, convention except that ECX is
2570 // reserved for storing the tail called function address. Only 2 registers are
2571 // free for argument passing (inreg). Tail call optimization is performed
2573 // * tailcallopt is enabled
2574 // * caller/callee are fastcc
2575 // On X86_64 architecture with GOT-style position independent code only local
2576 // (within module) calls are supported at the moment.
2577 // To keep the stack aligned according to platform abi the function
2578 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2579 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2580 // If a tail called function callee has more arguments than the caller the
2581 // caller needs to make sure that there is room to move the RETADDR to. This is
2582 // achieved by reserving an area the size of the argument delta right after the
2583 // original REtADDR, but before the saved framepointer or the spilled registers
2584 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2596 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2597 /// for a 16 byte align requirement.
2599 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2600 SelectionDAG& DAG) const {
2601 MachineFunction &MF = DAG.getMachineFunction();
2602 const TargetMachine &TM = MF.getTarget();
2603 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2604 unsigned StackAlignment = TFI.getStackAlignment();
2605 uint64_t AlignMask = StackAlignment - 1;
2606 int64_t Offset = StackSize;
2607 uint64_t SlotSize = TD->getPointerSize();
2608 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2609 // Number smaller than 12 so just add the difference.
2610 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2612 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2613 Offset = ((~AlignMask) & Offset) + StackAlignment +
2614 (StackAlignment-SlotSize);
2619 /// MatchingStackOffset - Return true if the given stack call argument is
2620 /// already available in the same position (relatively) of the caller's
2621 /// incoming argument stack.
2623 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2624 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2625 const X86InstrInfo *TII) {
2626 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2628 if (Arg.getOpcode() == ISD::CopyFromReg) {
2629 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2630 if (!TargetRegisterInfo::isVirtualRegister(VR))
2632 MachineInstr *Def = MRI->getVRegDef(VR);
2635 if (!Flags.isByVal()) {
2636 if (!TII->isLoadFromStackSlot(Def, FI))
2639 unsigned Opcode = Def->getOpcode();
2640 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2641 Def->getOperand(1).isFI()) {
2642 FI = Def->getOperand(1).getIndex();
2643 Bytes = Flags.getByValSize();
2647 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2648 if (Flags.isByVal())
2649 // ByVal argument is passed in as a pointer but it's now being
2650 // dereferenced. e.g.
2651 // define @foo(%struct.X* %A) {
2652 // tail call @bar(%struct.X* byval %A)
2655 SDValue Ptr = Ld->getBasePtr();
2656 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2659 FI = FINode->getIndex();
2660 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2661 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2662 FI = FINode->getIndex();
2663 Bytes = Flags.getByValSize();
2667 assert(FI != INT_MAX);
2668 if (!MFI->isFixedObjectIndex(FI))
2670 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2673 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2674 /// for tail call optimization. Targets which want to do tail call
2675 /// optimization should implement this function.
2677 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2678 CallingConv::ID CalleeCC,
2680 bool isCalleeStructRet,
2681 bool isCallerStructRet,
2682 const SmallVectorImpl<ISD::OutputArg> &Outs,
2683 const SmallVectorImpl<SDValue> &OutVals,
2684 const SmallVectorImpl<ISD::InputArg> &Ins,
2685 SelectionDAG& DAG) const {
2686 if (!IsTailCallConvention(CalleeCC) &&
2687 CalleeCC != CallingConv::C)
2690 // If -tailcallopt is specified, make fastcc functions tail-callable.
2691 const MachineFunction &MF = DAG.getMachineFunction();
2692 const Function *CallerF = DAG.getMachineFunction().getFunction();
2693 CallingConv::ID CallerCC = CallerF->getCallingConv();
2694 bool CCMatch = CallerCC == CalleeCC;
2696 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2697 if (IsTailCallConvention(CalleeCC) && CCMatch)
2702 // Look for obvious safe cases to perform tail call optimization that do not
2703 // require ABI changes. This is what gcc calls sibcall.
2705 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2706 // emit a special epilogue.
2707 if (RegInfo->needsStackRealignment(MF))
2710 // Also avoid sibcall optimization if either caller or callee uses struct
2711 // return semantics.
2712 if (isCalleeStructRet || isCallerStructRet)
2715 // An stdcall caller is expected to clean up its arguments; the callee
2716 // isn't going to do that.
2717 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2720 // Do not sibcall optimize vararg calls unless all arguments are passed via
2722 if (isVarArg && !Outs.empty()) {
2724 // Optimizing for varargs on Win64 is unlikely to be safe without
2725 // additional testing.
2726 if (Subtarget->isTargetWin64())
2729 SmallVector<CCValAssign, 16> ArgLocs;
2730 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2731 getTargetMachine(), ArgLocs, *DAG.getContext());
2733 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2734 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2735 if (!ArgLocs[i].isRegLoc())
2739 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2740 // stack. Therefore, if it's not used by the call it is not safe to optimize
2741 // this into a sibcall.
2742 bool Unused = false;
2743 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2750 SmallVector<CCValAssign, 16> RVLocs;
2751 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2752 getTargetMachine(), RVLocs, *DAG.getContext());
2753 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2754 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2755 CCValAssign &VA = RVLocs[i];
2756 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2761 // If the calling conventions do not match, then we'd better make sure the
2762 // results are returned in the same way as what the caller expects.
2764 SmallVector<CCValAssign, 16> RVLocs1;
2765 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2766 getTargetMachine(), RVLocs1, *DAG.getContext());
2767 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2769 SmallVector<CCValAssign, 16> RVLocs2;
2770 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2771 getTargetMachine(), RVLocs2, *DAG.getContext());
2772 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2774 if (RVLocs1.size() != RVLocs2.size())
2776 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2777 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2779 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2781 if (RVLocs1[i].isRegLoc()) {
2782 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2785 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2791 // If the callee takes no arguments then go on to check the results of the
2793 if (!Outs.empty()) {
2794 // Check if stack adjustment is needed. For now, do not do this if any
2795 // argument is passed on the stack.
2796 SmallVector<CCValAssign, 16> ArgLocs;
2797 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2798 getTargetMachine(), ArgLocs, *DAG.getContext());
2800 // Allocate shadow area for Win64
2801 if (Subtarget->isTargetWin64()) {
2802 CCInfo.AllocateStack(32, 8);
2805 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2806 if (CCInfo.getNextStackOffset()) {
2807 MachineFunction &MF = DAG.getMachineFunction();
2808 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2811 // Check if the arguments are already laid out in the right way as
2812 // the caller's fixed stack objects.
2813 MachineFrameInfo *MFI = MF.getFrameInfo();
2814 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2815 const X86InstrInfo *TII =
2816 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2817 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2818 CCValAssign &VA = ArgLocs[i];
2819 SDValue Arg = OutVals[i];
2820 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2821 if (VA.getLocInfo() == CCValAssign::Indirect)
2823 if (!VA.isRegLoc()) {
2824 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2831 // If the tailcall address may be in a register, then make sure it's
2832 // possible to register allocate for it. In 32-bit, the call address can
2833 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2834 // callee-saved registers are restored. These happen to be the same
2835 // registers used to pass 'inreg' arguments so watch out for those.
2836 if (!Subtarget->is64Bit() &&
2837 !isa<GlobalAddressSDNode>(Callee) &&
2838 !isa<ExternalSymbolSDNode>(Callee)) {
2839 unsigned NumInRegs = 0;
2840 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2841 CCValAssign &VA = ArgLocs[i];
2844 unsigned Reg = VA.getLocReg();
2847 case X86::EAX: case X86::EDX: case X86::ECX:
2848 if (++NumInRegs == 3)
2860 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2861 return X86::createFastISel(funcInfo);
2865 //===----------------------------------------------------------------------===//
2866 // Other Lowering Hooks
2867 //===----------------------------------------------------------------------===//
2869 static bool MayFoldLoad(SDValue Op) {
2870 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2873 static bool MayFoldIntoStore(SDValue Op) {
2874 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2877 static bool isTargetShuffle(unsigned Opcode) {
2879 default: return false;
2880 case X86ISD::PSHUFD:
2881 case X86ISD::PSHUFHW:
2882 case X86ISD::PSHUFLW:
2884 case X86ISD::PALIGN:
2885 case X86ISD::MOVLHPS:
2886 case X86ISD::MOVLHPD:
2887 case X86ISD::MOVHLPS:
2888 case X86ISD::MOVLPS:
2889 case X86ISD::MOVLPD:
2890 case X86ISD::MOVSHDUP:
2891 case X86ISD::MOVSLDUP:
2892 case X86ISD::MOVDDUP:
2895 case X86ISD::UNPCKL:
2896 case X86ISD::UNPCKH:
2897 case X86ISD::VPERMILP:
2898 case X86ISD::VPERM2X128:
2903 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2904 SDValue V1, SelectionDAG &DAG) {
2906 default: llvm_unreachable("Unknown x86 shuffle node");
2907 case X86ISD::MOVSHDUP:
2908 case X86ISD::MOVSLDUP:
2909 case X86ISD::MOVDDUP:
2910 return DAG.getNode(Opc, dl, VT, V1);
2914 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2915 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2917 default: llvm_unreachable("Unknown x86 shuffle node");
2918 case X86ISD::PSHUFD:
2919 case X86ISD::PSHUFHW:
2920 case X86ISD::PSHUFLW:
2921 case X86ISD::VPERMILP:
2922 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2926 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2927 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2929 default: llvm_unreachable("Unknown x86 shuffle node");
2930 case X86ISD::PALIGN:
2932 case X86ISD::VPERM2X128:
2933 return DAG.getNode(Opc, dl, VT, V1, V2,
2934 DAG.getConstant(TargetMask, MVT::i8));
2938 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2939 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2941 default: llvm_unreachable("Unknown x86 shuffle node");
2942 case X86ISD::MOVLHPS:
2943 case X86ISD::MOVLHPD:
2944 case X86ISD::MOVHLPS:
2945 case X86ISD::MOVLPS:
2946 case X86ISD::MOVLPD:
2949 case X86ISD::UNPCKL:
2950 case X86ISD::UNPCKH:
2951 return DAG.getNode(Opc, dl, VT, V1, V2);
2955 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2956 MachineFunction &MF = DAG.getMachineFunction();
2957 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2958 int ReturnAddrIndex = FuncInfo->getRAIndex();
2960 if (ReturnAddrIndex == 0) {
2961 // Set up a frame object for the return address.
2962 uint64_t SlotSize = TD->getPointerSize();
2963 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2965 FuncInfo->setRAIndex(ReturnAddrIndex);
2968 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2972 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2973 bool hasSymbolicDisplacement) {
2974 // Offset should fit into 32 bit immediate field.
2975 if (!isInt<32>(Offset))
2978 // If we don't have a symbolic displacement - we don't have any extra
2980 if (!hasSymbolicDisplacement)
2983 // FIXME: Some tweaks might be needed for medium code model.
2984 if (M != CodeModel::Small && M != CodeModel::Kernel)
2987 // For small code model we assume that latest object is 16MB before end of 31
2988 // bits boundary. We may also accept pretty large negative constants knowing
2989 // that all objects are in the positive half of address space.
2990 if (M == CodeModel::Small && Offset < 16*1024*1024)
2993 // For kernel code model we know that all object resist in the negative half
2994 // of 32bits address space. We may not accept negative offsets, since they may
2995 // be just off and we may accept pretty large positive ones.
2996 if (M == CodeModel::Kernel && Offset > 0)
3002 /// isCalleePop - Determines whether the callee is required to pop its
3003 /// own arguments. Callee pop is necessary to support tail calls.
3004 bool X86::isCalleePop(CallingConv::ID CallingConv,
3005 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3009 switch (CallingConv) {
3012 case CallingConv::X86_StdCall:
3014 case CallingConv::X86_FastCall:
3016 case CallingConv::X86_ThisCall:
3018 case CallingConv::Fast:
3020 case CallingConv::GHC:
3025 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3026 /// specific condition code, returning the condition code and the LHS/RHS of the
3027 /// comparison to make.
3028 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3029 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3031 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3032 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3033 // X > -1 -> X == 0, jump !sign.
3034 RHS = DAG.getConstant(0, RHS.getValueType());
3035 return X86::COND_NS;
3036 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3037 // X < 0 -> X == 0, jump on sign.
3039 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3041 RHS = DAG.getConstant(0, RHS.getValueType());
3042 return X86::COND_LE;
3046 switch (SetCCOpcode) {
3047 default: llvm_unreachable("Invalid integer condition!");
3048 case ISD::SETEQ: return X86::COND_E;
3049 case ISD::SETGT: return X86::COND_G;
3050 case ISD::SETGE: return X86::COND_GE;
3051 case ISD::SETLT: return X86::COND_L;
3052 case ISD::SETLE: return X86::COND_LE;
3053 case ISD::SETNE: return X86::COND_NE;
3054 case ISD::SETULT: return X86::COND_B;
3055 case ISD::SETUGT: return X86::COND_A;
3056 case ISD::SETULE: return X86::COND_BE;
3057 case ISD::SETUGE: return X86::COND_AE;
3061 // First determine if it is required or is profitable to flip the operands.
3063 // If LHS is a foldable load, but RHS is not, flip the condition.
3064 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3065 !ISD::isNON_EXTLoad(RHS.getNode())) {
3066 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3067 std::swap(LHS, RHS);
3070 switch (SetCCOpcode) {
3076 std::swap(LHS, RHS);
3080 // On a floating point condition, the flags are set as follows:
3082 // 0 | 0 | 0 | X > Y
3083 // 0 | 0 | 1 | X < Y
3084 // 1 | 0 | 0 | X == Y
3085 // 1 | 1 | 1 | unordered
3086 switch (SetCCOpcode) {
3087 default: llvm_unreachable("Condcode should be pre-legalized away");
3089 case ISD::SETEQ: return X86::COND_E;
3090 case ISD::SETOLT: // flipped
3092 case ISD::SETGT: return X86::COND_A;
3093 case ISD::SETOLE: // flipped
3095 case ISD::SETGE: return X86::COND_AE;
3096 case ISD::SETUGT: // flipped
3098 case ISD::SETLT: return X86::COND_B;
3099 case ISD::SETUGE: // flipped
3101 case ISD::SETLE: return X86::COND_BE;
3103 case ISD::SETNE: return X86::COND_NE;
3104 case ISD::SETUO: return X86::COND_P;
3105 case ISD::SETO: return X86::COND_NP;
3107 case ISD::SETUNE: return X86::COND_INVALID;
3111 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3112 /// code. Current x86 isa includes the following FP cmov instructions:
3113 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3114 static bool hasFPCMov(unsigned X86CC) {
3130 /// isFPImmLegal - Returns true if the target can instruction select the
3131 /// specified FP immediate natively. If false, the legalizer will
3132 /// materialize the FP immediate as a load from a constant pool.
3133 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3134 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3135 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3141 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3142 /// the specified range (L, H].
3143 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3144 return (Val < 0) || (Val >= Low && Val < Hi);
3147 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3148 /// specified value.
3149 static bool isUndefOrEqual(int Val, int CmpVal) {
3150 if (Val < 0 || Val == CmpVal)
3155 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3156 /// from position Pos and ending in Pos+Size, falls within the specified
3157 /// sequential range (L, L+Pos]. or is undef.
3158 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3159 int Pos, int Size, int Low) {
3160 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3161 if (!isUndefOrEqual(Mask[i], Low))
3166 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3167 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3168 /// the second operand.
3169 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3170 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3171 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3172 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3173 return (Mask[0] < 2 && Mask[1] < 2);
3177 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3178 return ::isPSHUFDMask(N->getMask(), N->getValueType(0));
3181 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3182 /// is suitable for input to PSHUFHW.
3183 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3184 if (VT != MVT::v8i16)
3187 // Lower quadword copied in order or undef.
3188 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3191 // Upper quadword shuffled.
3192 for (unsigned i = 4; i != 8; ++i)
3193 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3199 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3200 return ::isPSHUFHWMask(N->getMask(), N->getValueType(0));
3203 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3204 /// is suitable for input to PSHUFLW.
3205 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3206 if (VT != MVT::v8i16)
3209 // Upper quadword copied in order.
3210 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3213 // Lower quadword shuffled.
3214 for (unsigned i = 0; i != 4; ++i)
3221 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3222 return ::isPSHUFLWMask(N->getMask(), N->getValueType(0));
3225 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3226 /// is suitable for input to PALIGNR.
3227 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3228 const X86Subtarget *Subtarget) {
3229 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3230 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3233 unsigned NumElts = VT.getVectorNumElements();
3234 unsigned NumLanes = VT.getSizeInBits()/128;
3235 unsigned NumLaneElts = NumElts/NumLanes;
3237 // Do not handle 64-bit element shuffles with palignr.
3238 if (NumLaneElts == 2)
3241 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3243 for (i = 0; i != NumLaneElts; ++i) {
3248 // Lane is all undef, go to next lane
3249 if (i == NumLaneElts)
3252 int Start = Mask[i+l];
3254 // Make sure its in this lane in one of the sources
3255 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3256 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3259 // If not lane 0, then we must match lane 0
3260 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3263 // Correct second source to be contiguous with first source
3264 if (Start >= (int)NumElts)
3265 Start -= NumElts - NumLaneElts;
3267 // Make sure we're shifting in the right direction.
3268 if (Start <= (int)(i+l))
3273 // Check the rest of the elements to see if they are consecutive.
3274 for (++i; i != NumLaneElts; ++i) {
3275 int Idx = Mask[i+l];
3277 // Make sure its in this lane
3278 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3279 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3282 // If not lane 0, then we must match lane 0
3283 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3286 if (Idx >= (int)NumElts)
3287 Idx -= NumElts - NumLaneElts;
3289 if (!isUndefOrEqual(Idx, Start+i))
3298 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3299 /// the two vector operands have swapped position.
3300 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3301 unsigned NumElems) {
3302 for (unsigned i = 0; i != NumElems; ++i) {
3306 else if (idx < (int)NumElems)
3307 Mask[i] = idx + NumElems;
3309 Mask[i] = idx - NumElems;
3313 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3314 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3315 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3316 /// reverse of what x86 shuffles want.
3317 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3318 bool Commuted = false) {
3319 if (!HasAVX && VT.getSizeInBits() == 256)
3322 unsigned NumElems = VT.getVectorNumElements();
3323 unsigned NumLanes = VT.getSizeInBits()/128;
3324 unsigned NumLaneElems = NumElems/NumLanes;
3326 if (NumLaneElems != 2 && NumLaneElems != 4)
3329 // VSHUFPSY divides the resulting vector into 4 chunks.
3330 // The sources are also splitted into 4 chunks, and each destination
3331 // chunk must come from a different source chunk.
3333 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3334 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3336 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3337 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3339 // VSHUFPDY divides the resulting vector into 4 chunks.
3340 // The sources are also splitted into 4 chunks, and each destination
3341 // chunk must come from a different source chunk.
3343 // SRC1 => X3 X2 X1 X0
3344 // SRC2 => Y3 Y2 Y1 Y0
3346 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3348 unsigned HalfLaneElems = NumLaneElems/2;
3349 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3350 for (unsigned i = 0; i != NumLaneElems; ++i) {
3351 int Idx = Mask[i+l];
3352 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3353 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3355 // For VSHUFPSY, the mask of the second half must be the same as the
3356 // first but with the appropriate offsets. This works in the same way as
3357 // VPERMILPS works with masks.
3358 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3360 if (!isUndefOrEqual(Idx, Mask[i]+l))
3368 bool X86::isSHUFPMask(ShuffleVectorSDNode *N, bool HasAVX) {
3369 return ::isSHUFPMask(N->getMask(), N->getValueType(0), HasAVX);
3372 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3373 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3374 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3375 EVT VT = N->getValueType(0);
3376 unsigned NumElems = VT.getVectorNumElements();
3378 if (VT.getSizeInBits() != 128)
3384 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3385 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3386 isUndefOrEqual(N->getMaskElt(1), 7) &&
3387 isUndefOrEqual(N->getMaskElt(2), 2) &&
3388 isUndefOrEqual(N->getMaskElt(3), 3);
3391 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3392 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3394 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3395 EVT VT = N->getValueType(0);
3396 unsigned NumElems = VT.getVectorNumElements();
3398 if (VT.getSizeInBits() != 128)
3404 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3405 isUndefOrEqual(N->getMaskElt(1), 3) &&
3406 isUndefOrEqual(N->getMaskElt(2), 2) &&
3407 isUndefOrEqual(N->getMaskElt(3), 3);
3410 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3411 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3412 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3413 EVT VT = N->getValueType(0);
3415 if (VT.getSizeInBits() != 128)
3418 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3420 if (NumElems != 2 && NumElems != 4)
3423 for (unsigned i = 0; i < NumElems/2; ++i)
3424 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3427 for (unsigned i = NumElems/2; i < NumElems; ++i)
3428 if (!isUndefOrEqual(N->getMaskElt(i), i))
3434 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3435 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3436 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3437 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3439 if ((NumElems != 2 && NumElems != 4)
3440 || N->getValueType(0).getSizeInBits() > 128)
3443 for (unsigned i = 0; i < NumElems/2; ++i)
3444 if (!isUndefOrEqual(N->getMaskElt(i), i))
3447 for (unsigned i = 0; i < NumElems/2; ++i)
3448 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3454 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3455 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3456 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3457 bool HasAVX2, bool V2IsSplat = false) {
3458 unsigned NumElts = VT.getVectorNumElements();
3460 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3461 "Unsupported vector type for unpckh");
3463 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3464 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3467 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3468 // independently on 128-bit lanes.
3469 unsigned NumLanes = VT.getSizeInBits()/128;
3470 unsigned NumLaneElts = NumElts/NumLanes;
3472 for (unsigned l = 0; l != NumLanes; ++l) {
3473 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3474 i != (l+1)*NumLaneElts;
3477 int BitI1 = Mask[i+1];
3478 if (!isUndefOrEqual(BitI, j))
3481 if (!isUndefOrEqual(BitI1, NumElts))
3484 if (!isUndefOrEqual(BitI1, j + NumElts))
3493 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3494 return ::isUNPCKLMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat);
3497 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3498 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3499 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3500 bool HasAVX2, bool V2IsSplat = false) {
3501 unsigned NumElts = VT.getVectorNumElements();
3503 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3504 "Unsupported vector type for unpckh");
3506 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3507 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3510 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3511 // independently on 128-bit lanes.
3512 unsigned NumLanes = VT.getSizeInBits()/128;
3513 unsigned NumLaneElts = NumElts/NumLanes;
3515 for (unsigned l = 0; l != NumLanes; ++l) {
3516 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3517 i != (l+1)*NumLaneElts; i += 2, ++j) {
3519 int BitI1 = Mask[i+1];
3520 if (!isUndefOrEqual(BitI, j))
3523 if (isUndefOrEqual(BitI1, NumElts))
3526 if (!isUndefOrEqual(BitI1, j+NumElts))
3534 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3535 return ::isUNPCKHMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat);
3538 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3539 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3541 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3543 unsigned NumElts = VT.getVectorNumElements();
3545 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3546 "Unsupported vector type for unpckh");
3548 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3549 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3552 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3553 // FIXME: Need a better way to get rid of this, there's no latency difference
3554 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3555 // the former later. We should also remove the "_undef" special mask.
3556 if (NumElts == 4 && VT.getSizeInBits() == 256)
3559 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3560 // independently on 128-bit lanes.
3561 unsigned NumLanes = VT.getSizeInBits()/128;
3562 unsigned NumLaneElts = NumElts/NumLanes;
3564 for (unsigned l = 0; l != NumLanes; ++l) {
3565 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3566 i != (l+1)*NumLaneElts;
3569 int BitI1 = Mask[i+1];
3571 if (!isUndefOrEqual(BitI, j))
3573 if (!isUndefOrEqual(BitI1, j))
3581 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3582 return ::isUNPCKL_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2);
3585 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3586 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3588 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3589 unsigned NumElts = VT.getVectorNumElements();
3591 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3592 "Unsupported vector type for unpckh");
3594 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3595 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3598 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3599 // independently on 128-bit lanes.
3600 unsigned NumLanes = VT.getSizeInBits()/128;
3601 unsigned NumLaneElts = NumElts/NumLanes;
3603 for (unsigned l = 0; l != NumLanes; ++l) {
3604 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3605 i != (l+1)*NumLaneElts; i += 2, ++j) {
3607 int BitI1 = Mask[i+1];
3608 if (!isUndefOrEqual(BitI, j))
3610 if (!isUndefOrEqual(BitI1, j))
3617 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3618 return ::isUNPCKH_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2);
3621 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3622 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3623 /// MOVSD, and MOVD, i.e. setting the lowest element.
3624 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3625 if (VT.getVectorElementType().getSizeInBits() < 32)
3627 if (VT.getSizeInBits() == 256)
3630 unsigned NumElts = VT.getVectorNumElements();
3632 if (!isUndefOrEqual(Mask[0], NumElts))
3635 for (unsigned i = 1; i != NumElts; ++i)
3636 if (!isUndefOrEqual(Mask[i], i))
3642 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3643 return ::isMOVLMask(N->getMask(), N->getValueType(0));
3646 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3647 /// as permutations between 128-bit chunks or halves. As an example: this
3649 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3650 /// The first half comes from the second half of V1 and the second half from the
3651 /// the second half of V2.
3652 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3653 if (!HasAVX || VT.getSizeInBits() != 256)
3656 // The shuffle result is divided into half A and half B. In total the two
3657 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3658 // B must come from C, D, E or F.
3659 unsigned HalfSize = VT.getVectorNumElements()/2;
3660 bool MatchA = false, MatchB = false;
3662 // Check if A comes from one of C, D, E, F.
3663 for (unsigned Half = 0; Half != 4; ++Half) {
3664 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3670 // Check if B comes from one of C, D, E, F.
3671 for (unsigned Half = 0; Half != 4; ++Half) {
3672 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3678 return MatchA && MatchB;
3681 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3682 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3683 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3684 EVT VT = SVOp->getValueType(0);
3686 unsigned HalfSize = VT.getVectorNumElements()/2;
3688 unsigned FstHalf = 0, SndHalf = 0;
3689 for (unsigned i = 0; i < HalfSize; ++i) {
3690 if (SVOp->getMaskElt(i) > 0) {
3691 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3695 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3696 if (SVOp->getMaskElt(i) > 0) {
3697 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3702 return (FstHalf | (SndHalf << 4));
3705 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3706 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3707 /// Note that VPERMIL mask matching is different depending whether theunderlying
3708 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3709 /// to the same elements of the low, but to the higher half of the source.
3710 /// In VPERMILPD the two lanes could be shuffled independently of each other
3711 /// with the same restriction that lanes can't be crossed.
3712 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3716 unsigned NumElts = VT.getVectorNumElements();
3717 // Only match 256-bit with 32/64-bit types
3718 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3721 unsigned NumLanes = VT.getSizeInBits()/128;
3722 unsigned LaneSize = NumElts/NumLanes;
3723 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3724 for (unsigned i = 0; i != LaneSize; ++i) {
3725 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3727 if (NumElts != 8 || l == 0)
3729 // VPERMILPS handling
3732 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3740 /// getShuffleVPERMILPImmediate - Return the appropriate immediate to shuffle
3741 /// the specified VECTOR_MASK mask with VPERMILPS/D* instructions.
3742 static unsigned getShuffleVPERMILPImmediate(ShuffleVectorSDNode *SVOp) {
3743 EVT VT = SVOp->getValueType(0);
3745 unsigned NumElts = VT.getVectorNumElements();
3746 unsigned NumLanes = VT.getSizeInBits()/128;
3747 unsigned LaneSize = NumElts/NumLanes;
3749 // Although the mask is equal for both lanes do it twice to get the cases
3750 // where a mask will match because the same mask element is undef on the
3751 // first half but valid on the second. This would get pathological cases
3752 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3753 unsigned Shift = (LaneSize == 4) ? 2 : 1;
3755 for (unsigned i = 0; i != NumElts; ++i) {
3756 int MaskElt = SVOp->getMaskElt(i);
3759 MaskElt %= LaneSize;
3761 // VPERMILPSY, the mask of the first half must be equal to the second one
3762 if (NumElts == 8) Shamt %= LaneSize;
3763 Mask |= MaskElt << (Shamt*Shift);
3769 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3770 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3771 /// element of vector 2 and the other elements to come from vector 1 in order.
3772 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3773 bool V2IsSplat = false, bool V2IsUndef = false) {
3774 unsigned NumOps = VT.getVectorNumElements();
3775 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3778 if (!isUndefOrEqual(Mask[0], 0))
3781 for (unsigned i = 1; i != NumOps; ++i)
3782 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3783 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3784 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3790 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3791 bool V2IsUndef = false) {
3792 return isCommutedMOVLMask(N->getMask(), N->getValueType(0),
3793 V2IsSplat, V2IsUndef);
3796 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3797 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3798 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3799 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3800 const X86Subtarget *Subtarget) {
3801 if (!Subtarget->hasSSE3())
3804 // The second vector must be undef
3805 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3808 EVT VT = N->getValueType(0);
3809 unsigned NumElems = VT.getVectorNumElements();
3811 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3812 (VT.getSizeInBits() == 256 && NumElems != 8))
3815 // "i+1" is the value the indexed mask element must have
3816 for (unsigned i = 0; i < NumElems; i += 2)
3817 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3818 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3824 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3825 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3826 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3827 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3828 const X86Subtarget *Subtarget) {
3829 if (!Subtarget->hasSSE3())
3832 // The second vector must be undef
3833 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3836 EVT VT = N->getValueType(0);
3837 unsigned NumElems = VT.getVectorNumElements();
3839 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3840 (VT.getSizeInBits() == 256 && NumElems != 8))
3843 // "i" is the value the indexed mask element must have
3844 for (unsigned i = 0; i != NumElems; i += 2)
3845 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3846 !isUndefOrEqual(N->getMaskElt(i+1), i))
3852 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3853 /// specifies a shuffle of elements that is suitable for input to 256-bit
3854 /// version of MOVDDUP.
3855 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3856 unsigned NumElts = VT.getVectorNumElements();
3858 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3861 for (unsigned i = 0; i != NumElts/2; ++i)
3862 if (!isUndefOrEqual(Mask[i], 0))
3864 for (unsigned i = NumElts/2; i != NumElts; ++i)
3865 if (!isUndefOrEqual(Mask[i], NumElts/2))
3870 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3871 /// specifies a shuffle of elements that is suitable for input to 128-bit
3872 /// version of MOVDDUP.
3873 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3874 EVT VT = N->getValueType(0);
3876 if (VT.getSizeInBits() != 128)
3879 unsigned e = VT.getVectorNumElements() / 2;
3880 for (unsigned i = 0; i != e; ++i)
3881 if (!isUndefOrEqual(N->getMaskElt(i), i))
3883 for (unsigned i = 0; i != e; ++i)
3884 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3889 /// isVEXTRACTF128Index - Return true if the specified
3890 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3891 /// suitable for input to VEXTRACTF128.
3892 bool X86::isVEXTRACTF128Index(SDNode *N) {
3893 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3896 // The index should be aligned on a 128-bit boundary.
3898 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3900 unsigned VL = N->getValueType(0).getVectorNumElements();
3901 unsigned VBits = N->getValueType(0).getSizeInBits();
3902 unsigned ElSize = VBits / VL;
3903 bool Result = (Index * ElSize) % 128 == 0;
3908 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3909 /// operand specifies a subvector insert that is suitable for input to
3911 bool X86::isVINSERTF128Index(SDNode *N) {
3912 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3915 // The index should be aligned on a 128-bit boundary.
3917 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3919 unsigned VL = N->getValueType(0).getVectorNumElements();
3920 unsigned VBits = N->getValueType(0).getSizeInBits();
3921 unsigned ElSize = VBits / VL;
3922 bool Result = (Index * ElSize) % 128 == 0;
3927 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3928 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3929 /// Handles 128-bit and 256-bit.
3930 unsigned X86::getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3931 EVT VT = N->getValueType(0);
3933 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3934 "Unsupported vector type for PSHUF/SHUFP");
3936 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3937 // independently on 128-bit lanes.
3938 unsigned NumElts = VT.getVectorNumElements();
3939 unsigned NumLanes = VT.getSizeInBits()/128;
3940 unsigned NumLaneElts = NumElts/NumLanes;
3942 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3943 "Only supports 2 or 4 elements per lane");
3945 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3947 for (unsigned i = 0; i != NumElts; ++i) {
3948 int Elt = N->getMaskElt(i);
3949 if (Elt < 0) continue;
3951 unsigned ShAmt = i << Shift;
3952 if (ShAmt >= 8) ShAmt -= 8;
3953 Mask |= Elt << ShAmt;
3959 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3960 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3961 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3962 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3964 // 8 nodes, but we only care about the last 4.
3965 for (unsigned i = 7; i >= 4; --i) {
3966 int Val = SVOp->getMaskElt(i);
3975 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3976 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3977 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3978 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3980 // 8 nodes, but we only care about the first 4.
3981 for (int i = 3; i >= 0; --i) {
3982 int Val = SVOp->getMaskElt(i);
3991 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3992 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3993 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3994 EVT VT = SVOp->getValueType(0);
3995 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
3997 unsigned NumElts = VT.getVectorNumElements();
3998 unsigned NumLanes = VT.getSizeInBits()/128;
3999 unsigned NumLaneElts = NumElts/NumLanes;
4003 for (i = 0; i != NumElts; ++i) {
4004 Val = SVOp->getMaskElt(i);
4008 if (Val >= (int)NumElts)
4009 Val -= NumElts - NumLaneElts;
4011 assert(Val - i > 0 && "PALIGNR imm should be positive");
4012 return (Val - i) * EltSize;
4015 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4016 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4018 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4019 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4020 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4023 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4025 EVT VecVT = N->getOperand(0).getValueType();
4026 EVT ElVT = VecVT.getVectorElementType();
4028 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4029 return Index / NumElemsPerChunk;
4032 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4033 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4035 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4036 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4037 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4040 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4042 EVT VecVT = N->getValueType(0);
4043 EVT ElVT = VecVT.getVectorElementType();
4045 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4046 return Index / NumElemsPerChunk;
4049 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4051 bool X86::isZeroNode(SDValue Elt) {
4052 return ((isa<ConstantSDNode>(Elt) &&
4053 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4054 (isa<ConstantFPSDNode>(Elt) &&
4055 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4058 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4059 /// their permute mask.
4060 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4061 SelectionDAG &DAG) {
4062 EVT VT = SVOp->getValueType(0);
4063 unsigned NumElems = VT.getVectorNumElements();
4064 SmallVector<int, 8> MaskVec;
4066 for (unsigned i = 0; i != NumElems; ++i) {
4067 int idx = SVOp->getMaskElt(i);
4069 MaskVec.push_back(idx);
4070 else if (idx < (int)NumElems)
4071 MaskVec.push_back(idx + NumElems);
4073 MaskVec.push_back(idx - NumElems);
4075 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4076 SVOp->getOperand(0), &MaskVec[0]);
4079 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4080 /// match movhlps. The lower half elements should come from upper half of
4081 /// V1 (and in order), and the upper half elements should come from the upper
4082 /// half of V2 (and in order).
4083 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4084 EVT VT = Op->getValueType(0);
4085 if (VT.getSizeInBits() != 128)
4087 if (VT.getVectorNumElements() != 4)
4089 for (unsigned i = 0, e = 2; i != e; ++i)
4090 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4092 for (unsigned i = 2; i != 4; ++i)
4093 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4098 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4099 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4101 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4102 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4104 N = N->getOperand(0).getNode();
4105 if (!ISD::isNON_EXTLoad(N))
4108 *LD = cast<LoadSDNode>(N);
4112 // Test whether the given value is a vector value which will be legalized
4114 static bool WillBeConstantPoolLoad(SDNode *N) {
4115 if (N->getOpcode() != ISD::BUILD_VECTOR)
4118 // Check for any non-constant elements.
4119 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4120 switch (N->getOperand(i).getNode()->getOpcode()) {
4122 case ISD::ConstantFP:
4129 // Vectors of all-zeros and all-ones are materialized with special
4130 // instructions rather than being loaded.
4131 return !ISD::isBuildVectorAllZeros(N) &&
4132 !ISD::isBuildVectorAllOnes(N);
4135 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4136 /// match movlp{s|d}. The lower half elements should come from lower half of
4137 /// V1 (and in order), and the upper half elements should come from the upper
4138 /// half of V2 (and in order). And since V1 will become the source of the
4139 /// MOVLP, it must be either a vector load or a scalar load to vector.
4140 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4141 ShuffleVectorSDNode *Op) {
4142 EVT VT = Op->getValueType(0);
4143 if (VT.getSizeInBits() != 128)
4146 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4148 // Is V2 is a vector load, don't do this transformation. We will try to use
4149 // load folding shufps op.
4150 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4153 unsigned NumElems = VT.getVectorNumElements();
4155 if (NumElems != 2 && NumElems != 4)
4157 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4158 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4160 for (unsigned i = NumElems/2; i != NumElems; ++i)
4161 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4166 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4168 static bool isSplatVector(SDNode *N) {
4169 if (N->getOpcode() != ISD::BUILD_VECTOR)
4172 SDValue SplatValue = N->getOperand(0);
4173 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4174 if (N->getOperand(i) != SplatValue)
4179 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4180 /// to an zero vector.
4181 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4182 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4183 SDValue V1 = N->getOperand(0);
4184 SDValue V2 = N->getOperand(1);
4185 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4186 for (unsigned i = 0; i != NumElems; ++i) {
4187 int Idx = N->getMaskElt(i);
4188 if (Idx >= (int)NumElems) {
4189 unsigned Opc = V2.getOpcode();
4190 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4192 if (Opc != ISD::BUILD_VECTOR ||
4193 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4195 } else if (Idx >= 0) {
4196 unsigned Opc = V1.getOpcode();
4197 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4199 if (Opc != ISD::BUILD_VECTOR ||
4200 !X86::isZeroNode(V1.getOperand(Idx)))
4207 /// getZeroVector - Returns a vector of specified type with all zero elements.
4209 static SDValue getZeroVector(EVT VT, bool HasSSE2, bool HasAVX2,
4210 SelectionDAG &DAG, DebugLoc dl) {
4211 assert(VT.isVector() && "Expected a vector type");
4213 // Always build SSE zero vectors as <4 x i32> bitcasted
4214 // to their dest type. This ensures they get CSE'd.
4216 if (VT.getSizeInBits() == 128) { // SSE
4217 if (HasSSE2) { // SSE2
4218 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4219 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4221 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4222 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4224 } else if (VT.getSizeInBits() == 256) { // AVX
4225 if (HasAVX2) { // AVX2
4226 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4227 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4228 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4230 // 256-bit logic and arithmetic instructions in AVX are all
4231 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4232 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4233 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4234 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4237 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4240 /// getOnesVector - Returns a vector of specified type with all bits set.
4241 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4242 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4243 /// Then bitcast to their original type, ensuring they get CSE'd.
4244 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4246 assert(VT.isVector() && "Expected a vector type");
4247 assert((VT.is128BitVector() || VT.is256BitVector())
4248 && "Expected a 128-bit or 256-bit vector type");
4250 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4252 if (VT.getSizeInBits() == 256) {
4253 if (HasAVX2) { // AVX2
4254 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4255 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4257 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4258 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4259 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4260 Vec = Insert128BitVector(InsV, Vec,
4261 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4264 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4267 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4270 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4271 /// that point to V2 points to its first element.
4272 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4273 EVT VT = SVOp->getValueType(0);
4274 unsigned NumElems = VT.getVectorNumElements();
4276 bool Changed = false;
4277 SmallVector<int, 8> MaskVec(SVOp->getMask().begin(), SVOp->getMask().end());
4279 for (unsigned i = 0; i != NumElems; ++i) {
4280 if (MaskVec[i] > (int)NumElems) {
4281 MaskVec[i] = NumElems;
4286 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4287 SVOp->getOperand(1), &MaskVec[0]);
4288 return SDValue(SVOp, 0);
4291 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4292 /// operation of specified width.
4293 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4295 unsigned NumElems = VT.getVectorNumElements();
4296 SmallVector<int, 8> Mask;
4297 Mask.push_back(NumElems);
4298 for (unsigned i = 1; i != NumElems; ++i)
4300 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4303 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4304 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4306 unsigned NumElems = VT.getVectorNumElements();
4307 SmallVector<int, 8> Mask;
4308 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4310 Mask.push_back(i + NumElems);
4312 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4315 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4316 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4318 unsigned NumElems = VT.getVectorNumElements();
4319 unsigned Half = NumElems/2;
4320 SmallVector<int, 8> Mask;
4321 for (unsigned i = 0; i != Half; ++i) {
4322 Mask.push_back(i + Half);
4323 Mask.push_back(i + NumElems + Half);
4325 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4328 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4329 // a generic shuffle instruction because the target has no such instructions.
4330 // Generate shuffles which repeat i16 and i8 several times until they can be
4331 // represented by v4f32 and then be manipulated by target suported shuffles.
4332 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4333 EVT VT = V.getValueType();
4334 int NumElems = VT.getVectorNumElements();
4335 DebugLoc dl = V.getDebugLoc();
4337 while (NumElems > 4) {
4338 if (EltNo < NumElems/2) {
4339 V = getUnpackl(DAG, dl, VT, V, V);
4341 V = getUnpackh(DAG, dl, VT, V, V);
4342 EltNo -= NumElems/2;
4349 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4350 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4351 EVT VT = V.getValueType();
4352 DebugLoc dl = V.getDebugLoc();
4353 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4354 && "Vector size not supported");
4356 if (VT.getSizeInBits() == 128) {
4357 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4358 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4359 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4362 // To use VPERMILPS to splat scalars, the second half of indicies must
4363 // refer to the higher part, which is a duplication of the lower one,
4364 // because VPERMILPS can only handle in-lane permutations.
4365 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4366 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4368 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4369 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4373 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4376 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4377 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4378 EVT SrcVT = SV->getValueType(0);
4379 SDValue V1 = SV->getOperand(0);
4380 DebugLoc dl = SV->getDebugLoc();
4382 int EltNo = SV->getSplatIndex();
4383 int NumElems = SrcVT.getVectorNumElements();
4384 unsigned Size = SrcVT.getSizeInBits();
4386 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4387 "Unknown how to promote splat for type");
4389 // Extract the 128-bit part containing the splat element and update
4390 // the splat element index when it refers to the higher register.
4392 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0;
4393 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4395 EltNo -= NumElems/2;
4398 // All i16 and i8 vector types can't be used directly by a generic shuffle
4399 // instruction because the target has no such instruction. Generate shuffles
4400 // which repeat i16 and i8 several times until they fit in i32, and then can
4401 // be manipulated by target suported shuffles.
4402 EVT EltVT = SrcVT.getVectorElementType();
4403 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4404 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4406 // Recreate the 256-bit vector and place the same 128-bit vector
4407 // into the low and high part. This is necessary because we want
4408 // to use VPERM* to shuffle the vectors
4410 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4411 DAG.getConstant(0, MVT::i32), DAG, dl);
4412 V1 = Insert128BitVector(InsV, V1,
4413 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4416 return getLegalSplat(DAG, V1, EltNo);
4419 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4420 /// vector of zero or undef vector. This produces a shuffle where the low
4421 /// element of V2 is swizzled into the zero/undef vector, landing at element
4422 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4423 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4425 const X86Subtarget *Subtarget,
4426 SelectionDAG &DAG) {
4427 EVT VT = V2.getValueType();
4429 ? getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(), DAG,
4430 V2.getDebugLoc()) : DAG.getUNDEF(VT);
4431 unsigned NumElems = VT.getVectorNumElements();
4432 SmallVector<int, 16> MaskVec;
4433 for (unsigned i = 0; i != NumElems; ++i)
4434 // If this is the insertion idx, put the low elt of V2 here.
4435 MaskVec.push_back(i == Idx ? NumElems : i);
4436 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4439 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4440 /// element of the result of the vector shuffle.
4441 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4444 return SDValue(); // Limit search depth.
4446 SDValue V = SDValue(N, 0);
4447 EVT VT = V.getValueType();
4448 unsigned Opcode = V.getOpcode();
4450 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4451 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4452 Index = SV->getMaskElt(Index);
4455 return DAG.getUNDEF(VT.getVectorElementType());
4457 int NumElems = VT.getVectorNumElements();
4458 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4459 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4462 // Recurse into target specific vector shuffles to find scalars.
4463 if (isTargetShuffle(Opcode)) {
4464 int NumElems = VT.getVectorNumElements();
4465 SmallVector<unsigned, 16> ShuffleMask;
4470 ImmN = N->getOperand(N->getNumOperands()-1);
4471 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4474 case X86ISD::UNPCKH:
4475 DecodeUNPCKHMask(VT, ShuffleMask);
4477 case X86ISD::UNPCKL:
4478 DecodeUNPCKLMask(VT, ShuffleMask);
4480 case X86ISD::MOVHLPS:
4481 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4483 case X86ISD::MOVLHPS:
4484 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4486 case X86ISD::PSHUFD:
4487 ImmN = N->getOperand(N->getNumOperands()-1);
4488 DecodePSHUFMask(NumElems,
4489 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4492 case X86ISD::PSHUFHW:
4493 ImmN = N->getOperand(N->getNumOperands()-1);
4494 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4497 case X86ISD::PSHUFLW:
4498 ImmN = N->getOperand(N->getNumOperands()-1);
4499 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4503 case X86ISD::MOVSD: {
4504 // The index 0 always comes from the first element of the second source,
4505 // this is why MOVSS and MOVSD are used in the first place. The other
4506 // elements come from the other positions of the first source vector.
4507 unsigned OpNum = (Index == 0) ? 1 : 0;
4508 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4511 case X86ISD::VPERMILP:
4512 ImmN = N->getOperand(N->getNumOperands()-1);
4513 DecodeVPERMILPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4516 case X86ISD::VPERM2X128:
4517 ImmN = N->getOperand(N->getNumOperands()-1);
4518 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4521 case X86ISD::MOVDDUP:
4522 case X86ISD::MOVLHPD:
4523 case X86ISD::MOVLPD:
4524 case X86ISD::MOVLPS:
4525 case X86ISD::MOVSHDUP:
4526 case X86ISD::MOVSLDUP:
4527 case X86ISD::PALIGN:
4528 return SDValue(); // Not yet implemented.
4530 assert(0 && "unknown target shuffle node");
4534 Index = ShuffleMask[Index];
4536 return DAG.getUNDEF(VT.getVectorElementType());
4538 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4539 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4543 // Actual nodes that may contain scalar elements
4544 if (Opcode == ISD::BITCAST) {
4545 V = V.getOperand(0);
4546 EVT SrcVT = V.getValueType();
4547 unsigned NumElems = VT.getVectorNumElements();
4549 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4553 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4554 return (Index == 0) ? V.getOperand(0)
4555 : DAG.getUNDEF(VT.getVectorElementType());
4557 if (V.getOpcode() == ISD::BUILD_VECTOR)
4558 return V.getOperand(Index);
4563 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4564 /// shuffle operation which come from a consecutively from a zero. The
4565 /// search can start in two different directions, from left or right.
4567 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4568 bool ZerosFromLeft, SelectionDAG &DAG) {
4571 while (i < NumElems) {
4572 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4573 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4574 if (!(Elt.getNode() &&
4575 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4583 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4584 /// MaskE correspond consecutively to elements from one of the vector operands,
4585 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4587 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4588 int OpIdx, int NumElems, unsigned &OpNum) {
4589 bool SeenV1 = false;
4590 bool SeenV2 = false;
4592 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4593 int Idx = SVOp->getMaskElt(i);
4594 // Ignore undef indicies
4603 // Only accept consecutive elements from the same vector
4604 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4608 OpNum = SeenV1 ? 0 : 1;
4612 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4613 /// logical left shift of a vector.
4614 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4615 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4616 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4617 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4618 false /* check zeros from right */, DAG);
4624 // Considering the elements in the mask that are not consecutive zeros,
4625 // check if they consecutively come from only one of the source vectors.
4627 // V1 = {X, A, B, C} 0
4629 // vector_shuffle V1, V2 <1, 2, 3, X>
4631 if (!isShuffleMaskConsecutive(SVOp,
4632 0, // Mask Start Index
4633 NumElems-NumZeros-1, // Mask End Index
4634 NumZeros, // Where to start looking in the src vector
4635 NumElems, // Number of elements in vector
4636 OpSrc)) // Which source operand ?
4641 ShVal = SVOp->getOperand(OpSrc);
4645 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4646 /// logical left shift of a vector.
4647 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4648 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4649 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4650 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4651 true /* check zeros from left */, DAG);
4657 // Considering the elements in the mask that are not consecutive zeros,
4658 // check if they consecutively come from only one of the source vectors.
4660 // 0 { A, B, X, X } = V2
4662 // vector_shuffle V1, V2 <X, X, 4, 5>
4664 if (!isShuffleMaskConsecutive(SVOp,
4665 NumZeros, // Mask Start Index
4666 NumElems-1, // Mask End Index
4667 0, // Where to start looking in the src vector
4668 NumElems, // Number of elements in vector
4669 OpSrc)) // Which source operand ?
4674 ShVal = SVOp->getOperand(OpSrc);
4678 /// isVectorShift - Returns true if the shuffle can be implemented as a
4679 /// logical left or right shift of a vector.
4680 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4681 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4682 // Although the logic below support any bitwidth size, there are no
4683 // shift instructions which handle more than 128-bit vectors.
4684 if (SVOp->getValueType(0).getSizeInBits() > 128)
4687 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4688 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4694 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4696 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4697 unsigned NumNonZero, unsigned NumZero,
4699 const TargetLowering &TLI) {
4703 DebugLoc dl = Op.getDebugLoc();
4706 for (unsigned i = 0; i < 16; ++i) {
4707 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4708 if (ThisIsNonZero && First) {
4710 V = getZeroVector(MVT::v8i16, /*HasSSE2*/ true, /*HasAVX2*/ false,
4713 V = DAG.getUNDEF(MVT::v8i16);
4718 SDValue ThisElt(0, 0), LastElt(0, 0);
4719 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4720 if (LastIsNonZero) {
4721 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4722 MVT::i16, Op.getOperand(i-1));
4724 if (ThisIsNonZero) {
4725 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4726 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4727 ThisElt, DAG.getConstant(8, MVT::i8));
4729 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4733 if (ThisElt.getNode())
4734 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4735 DAG.getIntPtrConstant(i/2));
4739 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4742 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4744 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4745 unsigned NumNonZero, unsigned NumZero,
4747 const TargetLowering &TLI) {
4751 DebugLoc dl = Op.getDebugLoc();
4754 for (unsigned i = 0; i < 8; ++i) {
4755 bool isNonZero = (NonZeros & (1 << i)) != 0;
4759 V = getZeroVector(MVT::v8i16, /*HasSSE2*/ true, /*HasAVX2*/ false,
4762 V = DAG.getUNDEF(MVT::v8i16);
4765 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4766 MVT::v8i16, V, Op.getOperand(i),
4767 DAG.getIntPtrConstant(i));
4774 /// getVShift - Return a vector logical shift node.
4776 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4777 unsigned NumBits, SelectionDAG &DAG,
4778 const TargetLowering &TLI, DebugLoc dl) {
4779 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4780 EVT ShVT = MVT::v2i64;
4781 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4782 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4783 return DAG.getNode(ISD::BITCAST, dl, VT,
4784 DAG.getNode(Opc, dl, ShVT, SrcOp,
4785 DAG.getConstant(NumBits,
4786 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4790 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4791 SelectionDAG &DAG) const {
4793 // Check if the scalar load can be widened into a vector load. And if
4794 // the address is "base + cst" see if the cst can be "absorbed" into
4795 // the shuffle mask.
4796 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4797 SDValue Ptr = LD->getBasePtr();
4798 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4800 EVT PVT = LD->getValueType(0);
4801 if (PVT != MVT::i32 && PVT != MVT::f32)
4806 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4807 FI = FINode->getIndex();
4809 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4810 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4811 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4812 Offset = Ptr.getConstantOperandVal(1);
4813 Ptr = Ptr.getOperand(0);
4818 // FIXME: 256-bit vector instructions don't require a strict alignment,
4819 // improve this code to support it better.
4820 unsigned RequiredAlign = VT.getSizeInBits()/8;
4821 SDValue Chain = LD->getChain();
4822 // Make sure the stack object alignment is at least 16 or 32.
4823 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4824 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4825 if (MFI->isFixedObjectIndex(FI)) {
4826 // Can't change the alignment. FIXME: It's possible to compute
4827 // the exact stack offset and reference FI + adjust offset instead.
4828 // If someone *really* cares about this. That's the way to implement it.
4831 MFI->setObjectAlignment(FI, RequiredAlign);
4835 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4836 // Ptr + (Offset & ~15).
4839 if ((Offset % RequiredAlign) & 3)
4841 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4843 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4844 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4846 int EltNo = (Offset - StartOffset) >> 2;
4847 int NumElems = VT.getVectorNumElements();
4849 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4850 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4851 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4852 LD->getPointerInfo().getWithOffset(StartOffset),
4853 false, false, false, 0);
4855 // Canonicalize it to a v4i32 or v8i32 shuffle.
4856 SmallVector<int, 8> Mask;
4857 for (int i = 0; i < NumElems; ++i)
4858 Mask.push_back(EltNo);
4860 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4861 return DAG.getNode(ISD::BITCAST, dl, NVT,
4862 DAG.getVectorShuffle(CanonVT, dl, V1,
4863 DAG.getUNDEF(CanonVT),&Mask[0]));
4869 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4870 /// vector of type 'VT', see if the elements can be replaced by a single large
4871 /// load which has the same value as a build_vector whose operands are 'elts'.
4873 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4875 /// FIXME: we'd also like to handle the case where the last elements are zero
4876 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4877 /// There's even a handy isZeroNode for that purpose.
4878 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4879 DebugLoc &DL, SelectionDAG &DAG) {
4880 EVT EltVT = VT.getVectorElementType();
4881 unsigned NumElems = Elts.size();
4883 LoadSDNode *LDBase = NULL;
4884 unsigned LastLoadedElt = -1U;
4886 // For each element in the initializer, see if we've found a load or an undef.
4887 // If we don't find an initial load element, or later load elements are
4888 // non-consecutive, bail out.
4889 for (unsigned i = 0; i < NumElems; ++i) {
4890 SDValue Elt = Elts[i];
4892 if (!Elt.getNode() ||
4893 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4896 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4898 LDBase = cast<LoadSDNode>(Elt.getNode());
4902 if (Elt.getOpcode() == ISD::UNDEF)
4905 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4906 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4911 // If we have found an entire vector of loads and undefs, then return a large
4912 // load of the entire vector width starting at the base pointer. If we found
4913 // consecutive loads for the low half, generate a vzext_load node.
4914 if (LastLoadedElt == NumElems - 1) {
4915 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4916 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4917 LDBase->getPointerInfo(),
4918 LDBase->isVolatile(), LDBase->isNonTemporal(),
4919 LDBase->isInvariant(), 0);
4920 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4921 LDBase->getPointerInfo(),
4922 LDBase->isVolatile(), LDBase->isNonTemporal(),
4923 LDBase->isInvariant(), LDBase->getAlignment());
4924 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4925 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4926 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4927 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4929 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4930 LDBase->getPointerInfo(),
4931 LDBase->getAlignment(),
4932 false/*isVolatile*/, true/*ReadMem*/,
4934 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4939 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
4940 /// a vbroadcast node. We support two patterns:
4941 /// 1. A splat BUILD_VECTOR which uses a single scalar load.
4942 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4944 /// The scalar load node is returned when a pattern is found,
4945 /// or SDValue() otherwise.
4946 static SDValue isVectorBroadcast(SDValue &Op, const X86Subtarget *Subtarget) {
4947 if (!Subtarget->hasAVX())
4950 EVT VT = Op.getValueType();
4953 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
4954 V = V.getOperand(0);
4956 //A suspected load to be broadcasted.
4959 switch (V.getOpcode()) {
4961 // Unknown pattern found.
4964 case ISD::BUILD_VECTOR: {
4965 // The BUILD_VECTOR node must be a splat.
4966 if (!isSplatVector(V.getNode()))
4969 Ld = V.getOperand(0);
4971 // The suspected load node has several users. Make sure that all
4972 // of its users are from the BUILD_VECTOR node.
4973 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4978 case ISD::VECTOR_SHUFFLE: {
4979 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4981 // Shuffles must have a splat mask where the first element is
4983 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4986 SDValue Sc = Op.getOperand(0);
4987 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4990 Ld = Sc.getOperand(0);
4992 // The scalar_to_vector node and the suspected
4993 // load node must have exactly one user.
4994 if (!Sc.hasOneUse() || !Ld.hasOneUse())
5000 // The scalar source must be a normal load.
5001 if (!ISD::isNormalLoad(Ld.getNode()))
5004 bool Is256 = VT.getSizeInBits() == 256;
5005 bool Is128 = VT.getSizeInBits() == 128;
5006 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5008 // VBroadcast to YMM
5009 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
5012 // VBroadcast to XMM
5013 if (Is128 && (ScalarSize == 32))
5016 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5017 // double since there is vbroadcastsd xmm
5018 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5019 // VBroadcast to YMM
5020 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
5023 // VBroadcast to XMM
5024 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
5028 // Unsupported broadcast.
5033 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5034 DebugLoc dl = Op.getDebugLoc();
5036 EVT VT = Op.getValueType();
5037 EVT ExtVT = VT.getVectorElementType();
5038 unsigned NumElems = Op.getNumOperands();
5040 // Vectors containing all zeros can be matched by pxor and xorps later
5041 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5042 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5043 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5044 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5047 return getZeroVector(VT, Subtarget->hasSSE2(),
5048 Subtarget->hasAVX2(), DAG, dl);
5051 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5052 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5053 // vpcmpeqd on 256-bit vectors.
5054 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5055 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5058 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5061 SDValue LD = isVectorBroadcast(Op, Subtarget);
5063 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
5065 unsigned EVTBits = ExtVT.getSizeInBits();
5067 unsigned NumZero = 0;
5068 unsigned NumNonZero = 0;
5069 unsigned NonZeros = 0;
5070 bool IsAllConstants = true;
5071 SmallSet<SDValue, 8> Values;
5072 for (unsigned i = 0; i < NumElems; ++i) {
5073 SDValue Elt = Op.getOperand(i);
5074 if (Elt.getOpcode() == ISD::UNDEF)
5077 if (Elt.getOpcode() != ISD::Constant &&
5078 Elt.getOpcode() != ISD::ConstantFP)
5079 IsAllConstants = false;
5080 if (X86::isZeroNode(Elt))
5083 NonZeros |= (1 << i);
5088 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5089 if (NumNonZero == 0)
5090 return DAG.getUNDEF(VT);
5092 // Special case for single non-zero, non-undef, element.
5093 if (NumNonZero == 1) {
5094 unsigned Idx = CountTrailingZeros_32(NonZeros);
5095 SDValue Item = Op.getOperand(Idx);
5097 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5098 // the value are obviously zero, truncate the value to i32 and do the
5099 // insertion that way. Only do this if the value is non-constant or if the
5100 // value is a constant being inserted into element 0. It is cheaper to do
5101 // a constant pool load than it is to do a movd + shuffle.
5102 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5103 (!IsAllConstants || Idx == 0)) {
5104 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5106 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5107 EVT VecVT = MVT::v4i32;
5108 unsigned VecElts = 4;
5110 // Truncate the value (which may itself be a constant) to i32, and
5111 // convert it to a vector with movd (S2V+shuffle to zero extend).
5112 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5113 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5114 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5116 // Now we have our 32-bit value zero extended in the low element of
5117 // a vector. If Idx != 0, swizzle it into place.
5119 SmallVector<int, 4> Mask;
5120 Mask.push_back(Idx);
5121 for (unsigned i = 1; i != VecElts; ++i)
5123 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5124 DAG.getUNDEF(Item.getValueType()),
5127 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5131 // If we have a constant or non-constant insertion into the low element of
5132 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5133 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5134 // depending on what the source datatype is.
5137 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5139 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5140 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5141 if (VT.getSizeInBits() == 256) {
5142 SDValue ZeroVec = getZeroVector(VT, Subtarget->hasSSE2(),
5143 Subtarget->hasAVX2(), DAG, dl);
5144 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5145 Item, DAG.getIntPtrConstant(0));
5147 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5148 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5149 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5150 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5153 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5154 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5155 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5156 if (VT.getSizeInBits() == 256) {
5157 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget->hasSSE2(),
5158 Subtarget->hasAVX2(), DAG, dl);
5159 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
5162 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5163 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5165 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5169 // Is it a vector logical left shift?
5170 if (NumElems == 2 && Idx == 1 &&
5171 X86::isZeroNode(Op.getOperand(0)) &&
5172 !X86::isZeroNode(Op.getOperand(1))) {
5173 unsigned NumBits = VT.getSizeInBits();
5174 return getVShift(true, VT,
5175 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5176 VT, Op.getOperand(1)),
5177 NumBits/2, DAG, *this, dl);
5180 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5183 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5184 // is a non-constant being inserted into an element other than the low one,
5185 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5186 // movd/movss) to move this into the low element, then shuffle it into
5188 if (EVTBits == 32) {
5189 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5191 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5192 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5193 SmallVector<int, 8> MaskVec;
5194 for (unsigned i = 0; i < NumElems; i++)
5195 MaskVec.push_back(i == Idx ? 0 : 1);
5196 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5200 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5201 if (Values.size() == 1) {
5202 if (EVTBits == 32) {
5203 // Instead of a shuffle like this:
5204 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5205 // Check if it's possible to issue this instead.
5206 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5207 unsigned Idx = CountTrailingZeros_32(NonZeros);
5208 SDValue Item = Op.getOperand(Idx);
5209 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5210 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5215 // A vector full of immediates; various special cases are already
5216 // handled, so this is best done with a single constant-pool load.
5220 // For AVX-length vectors, build the individual 128-bit pieces and use
5221 // shuffles to put them in place.
5222 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5223 SmallVector<SDValue, 32> V;
5224 for (unsigned i = 0; i < NumElems; ++i)
5225 V.push_back(Op.getOperand(i));
5227 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5229 // Build both the lower and upper subvector.
5230 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5231 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5234 // Recreate the wider vector with the lower and upper part.
5235 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5236 DAG.getConstant(0, MVT::i32), DAG, dl);
5237 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5241 // Let legalizer expand 2-wide build_vectors.
5242 if (EVTBits == 64) {
5243 if (NumNonZero == 1) {
5244 // One half is zero or undef.
5245 unsigned Idx = CountTrailingZeros_32(NonZeros);
5246 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5247 Op.getOperand(Idx));
5248 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5253 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5254 if (EVTBits == 8 && NumElems == 16) {
5255 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5257 if (V.getNode()) return V;
5260 if (EVTBits == 16 && NumElems == 8) {
5261 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5263 if (V.getNode()) return V;
5266 // If element VT is == 32 bits, turn it into a number of shuffles.
5267 SmallVector<SDValue, 8> V;
5269 if (NumElems == 4 && NumZero > 0) {
5270 for (unsigned i = 0; i < 4; ++i) {
5271 bool isZero = !(NonZeros & (1 << i));
5273 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(),
5276 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5279 for (unsigned i = 0; i < 2; ++i) {
5280 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5283 V[i] = V[i*2]; // Must be a zero vector.
5286 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5289 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5292 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5297 SmallVector<int, 8> MaskVec;
5298 bool Reverse = (NonZeros & 0x3) == 2;
5299 for (unsigned i = 0; i < 2; ++i)
5300 MaskVec.push_back(Reverse ? 1-i : i);
5301 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5302 for (unsigned i = 0; i < 2; ++i)
5303 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5304 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5307 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5308 // Check for a build vector of consecutive loads.
5309 for (unsigned i = 0; i < NumElems; ++i)
5310 V[i] = Op.getOperand(i);
5312 // Check for elements which are consecutive loads.
5313 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5317 // For SSE 4.1, use insertps to put the high elements into the low element.
5318 if (getSubtarget()->hasSSE41()) {
5320 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5321 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5323 Result = DAG.getUNDEF(VT);
5325 for (unsigned i = 1; i < NumElems; ++i) {
5326 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5327 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5328 Op.getOperand(i), DAG.getIntPtrConstant(i));
5333 // Otherwise, expand into a number of unpckl*, start by extending each of
5334 // our (non-undef) elements to the full vector width with the element in the
5335 // bottom slot of the vector (which generates no code for SSE).
5336 for (unsigned i = 0; i < NumElems; ++i) {
5337 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5338 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5340 V[i] = DAG.getUNDEF(VT);
5343 // Next, we iteratively mix elements, e.g. for v4f32:
5344 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5345 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5346 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5347 unsigned EltStride = NumElems >> 1;
5348 while (EltStride != 0) {
5349 for (unsigned i = 0; i < EltStride; ++i) {
5350 // If V[i+EltStride] is undef and this is the first round of mixing,
5351 // then it is safe to just drop this shuffle: V[i] is already in the
5352 // right place, the one element (since it's the first round) being
5353 // inserted as undef can be dropped. This isn't safe for successive
5354 // rounds because they will permute elements within both vectors.
5355 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5356 EltStride == NumElems/2)
5359 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5368 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5369 // them in a MMX register. This is better than doing a stack convert.
5370 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5371 DebugLoc dl = Op.getDebugLoc();
5372 EVT ResVT = Op.getValueType();
5374 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5375 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5377 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5378 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5379 InVec = Op.getOperand(1);
5380 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5381 unsigned NumElts = ResVT.getVectorNumElements();
5382 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5383 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5384 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5386 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5387 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5388 Mask[0] = 0; Mask[1] = 2;
5389 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5391 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5394 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5395 // to create 256-bit vectors from two other 128-bit ones.
5396 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5397 DebugLoc dl = Op.getDebugLoc();
5398 EVT ResVT = Op.getValueType();
5400 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5402 SDValue V1 = Op.getOperand(0);
5403 SDValue V2 = Op.getOperand(1);
5404 unsigned NumElems = ResVT.getVectorNumElements();
5406 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5407 DAG.getConstant(0, MVT::i32), DAG, dl);
5408 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5413 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5414 EVT ResVT = Op.getValueType();
5416 assert(Op.getNumOperands() == 2);
5417 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5418 "Unsupported CONCAT_VECTORS for value type");
5420 // We support concatenate two MMX registers and place them in a MMX register.
5421 // This is better than doing a stack convert.
5422 if (ResVT.is128BitVector())
5423 return LowerMMXCONCAT_VECTORS(Op, DAG);
5425 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5426 // from two other 128-bit ones.
5427 return LowerAVXCONCAT_VECTORS(Op, DAG);
5430 // v8i16 shuffles - Prefer shuffles in the following order:
5431 // 1. [all] pshuflw, pshufhw, optional move
5432 // 2. [ssse3] 1 x pshufb
5433 // 3. [ssse3] 2 x pshufb + 1 x por
5434 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5436 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5437 SelectionDAG &DAG) const {
5438 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5439 SDValue V1 = SVOp->getOperand(0);
5440 SDValue V2 = SVOp->getOperand(1);
5441 DebugLoc dl = SVOp->getDebugLoc();
5442 SmallVector<int, 8> MaskVals;
5444 // Determine if more than 1 of the words in each of the low and high quadwords
5445 // of the result come from the same quadword of one of the two inputs. Undef
5446 // mask values count as coming from any quadword, for better codegen.
5447 unsigned LoQuad[] = { 0, 0, 0, 0 };
5448 unsigned HiQuad[] = { 0, 0, 0, 0 };
5449 BitVector InputQuads(4);
5450 for (unsigned i = 0; i < 8; ++i) {
5451 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5452 int EltIdx = SVOp->getMaskElt(i);
5453 MaskVals.push_back(EltIdx);
5462 InputQuads.set(EltIdx / 4);
5465 int BestLoQuad = -1;
5466 unsigned MaxQuad = 1;
5467 for (unsigned i = 0; i < 4; ++i) {
5468 if (LoQuad[i] > MaxQuad) {
5470 MaxQuad = LoQuad[i];
5474 int BestHiQuad = -1;
5476 for (unsigned i = 0; i < 4; ++i) {
5477 if (HiQuad[i] > MaxQuad) {
5479 MaxQuad = HiQuad[i];
5483 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5484 // of the two input vectors, shuffle them into one input vector so only a
5485 // single pshufb instruction is necessary. If There are more than 2 input
5486 // quads, disable the next transformation since it does not help SSSE3.
5487 bool V1Used = InputQuads[0] || InputQuads[1];
5488 bool V2Used = InputQuads[2] || InputQuads[3];
5489 if (Subtarget->hasSSSE3()) {
5490 if (InputQuads.count() == 2 && V1Used && V2Used) {
5491 BestLoQuad = InputQuads.find_first();
5492 BestHiQuad = InputQuads.find_next(BestLoQuad);
5494 if (InputQuads.count() > 2) {
5500 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5501 // the shuffle mask. If a quad is scored as -1, that means that it contains
5502 // words from all 4 input quadwords.
5504 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5505 SmallVector<int, 8> MaskV;
5506 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5507 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5508 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5509 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5510 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5511 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5513 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5514 // source words for the shuffle, to aid later transformations.
5515 bool AllWordsInNewV = true;
5516 bool InOrder[2] = { true, true };
5517 for (unsigned i = 0; i != 8; ++i) {
5518 int idx = MaskVals[i];
5520 InOrder[i/4] = false;
5521 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5523 AllWordsInNewV = false;
5527 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5528 if (AllWordsInNewV) {
5529 for (int i = 0; i != 8; ++i) {
5530 int idx = MaskVals[i];
5533 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5534 if ((idx != i) && idx < 4)
5536 if ((idx != i) && idx > 3)
5545 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5546 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5547 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5548 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5549 unsigned TargetMask = 0;
5550 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5551 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5552 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5553 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5554 V1 = NewV.getOperand(0);
5555 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5559 // If we have SSSE3, and all words of the result are from 1 input vector,
5560 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5561 // is present, fall back to case 4.
5562 if (Subtarget->hasSSSE3()) {
5563 SmallVector<SDValue,16> pshufbMask;
5565 // If we have elements from both input vectors, set the high bit of the
5566 // shuffle mask element to zero out elements that come from V2 in the V1
5567 // mask, and elements that come from V1 in the V2 mask, so that the two
5568 // results can be OR'd together.
5569 bool TwoInputs = V1Used && V2Used;
5570 for (unsigned i = 0; i != 8; ++i) {
5571 int EltIdx = MaskVals[i] * 2;
5572 if (TwoInputs && (EltIdx >= 16)) {
5573 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5574 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5577 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5578 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5580 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5581 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5582 DAG.getNode(ISD::BUILD_VECTOR, dl,
5583 MVT::v16i8, &pshufbMask[0], 16));
5585 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5587 // Calculate the shuffle mask for the second input, shuffle it, and
5588 // OR it with the first shuffled input.
5590 for (unsigned i = 0; i != 8; ++i) {
5591 int EltIdx = MaskVals[i] * 2;
5593 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5594 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5597 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5598 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5600 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5601 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5602 DAG.getNode(ISD::BUILD_VECTOR, dl,
5603 MVT::v16i8, &pshufbMask[0], 16));
5604 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5605 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5608 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5609 // and update MaskVals with new element order.
5610 BitVector InOrder(8);
5611 if (BestLoQuad >= 0) {
5612 SmallVector<int, 8> MaskV;
5613 for (int i = 0; i != 4; ++i) {
5614 int idx = MaskVals[i];
5616 MaskV.push_back(-1);
5618 } else if ((idx / 4) == BestLoQuad) {
5619 MaskV.push_back(idx & 3);
5622 MaskV.push_back(-1);
5625 for (unsigned i = 4; i != 8; ++i)
5627 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5630 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5631 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5633 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5637 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5638 // and update MaskVals with the new element order.
5639 if (BestHiQuad >= 0) {
5640 SmallVector<int, 8> MaskV;
5641 for (unsigned i = 0; i != 4; ++i)
5643 for (unsigned i = 4; i != 8; ++i) {
5644 int idx = MaskVals[i];
5646 MaskV.push_back(-1);
5648 } else if ((idx / 4) == BestHiQuad) {
5649 MaskV.push_back((idx & 3) + 4);
5652 MaskV.push_back(-1);
5655 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5658 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5659 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5661 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5665 // In case BestHi & BestLo were both -1, which means each quadword has a word
5666 // from each of the four input quadwords, calculate the InOrder bitvector now
5667 // before falling through to the insert/extract cleanup.
5668 if (BestLoQuad == -1 && BestHiQuad == -1) {
5670 for (int i = 0; i != 8; ++i)
5671 if (MaskVals[i] < 0 || MaskVals[i] == i)
5675 // The other elements are put in the right place using pextrw and pinsrw.
5676 for (unsigned i = 0; i != 8; ++i) {
5679 int EltIdx = MaskVals[i];
5682 SDValue ExtOp = (EltIdx < 8)
5683 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5684 DAG.getIntPtrConstant(EltIdx))
5685 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5686 DAG.getIntPtrConstant(EltIdx - 8));
5687 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5688 DAG.getIntPtrConstant(i));
5693 // v16i8 shuffles - Prefer shuffles in the following order:
5694 // 1. [ssse3] 1 x pshufb
5695 // 2. [ssse3] 2 x pshufb + 1 x por
5696 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5698 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5700 const X86TargetLowering &TLI) {
5701 SDValue V1 = SVOp->getOperand(0);
5702 SDValue V2 = SVOp->getOperand(1);
5703 DebugLoc dl = SVOp->getDebugLoc();
5704 ArrayRef<int> MaskVals = SVOp->getMask();
5706 // If we have SSSE3, case 1 is generated when all result bytes come from
5707 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5708 // present, fall back to case 3.
5709 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5712 for (unsigned i = 0; i < 16; ++i) {
5713 int EltIdx = MaskVals[i];
5722 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5723 if (TLI.getSubtarget()->hasSSSE3()) {
5724 SmallVector<SDValue,16> pshufbMask;
5726 // If all result elements are from one input vector, then only translate
5727 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5729 // Otherwise, we have elements from both input vectors, and must zero out
5730 // elements that come from V2 in the first mask, and V1 in the second mask
5731 // so that we can OR them together.
5732 bool TwoInputs = !(V1Only || V2Only);
5733 for (unsigned i = 0; i != 16; ++i) {
5734 int EltIdx = MaskVals[i];
5735 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5736 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5739 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5741 // If all the elements are from V2, assign it to V1 and return after
5742 // building the first pshufb.
5745 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5746 DAG.getNode(ISD::BUILD_VECTOR, dl,
5747 MVT::v16i8, &pshufbMask[0], 16));
5751 // Calculate the shuffle mask for the second input, shuffle it, and
5752 // OR it with the first shuffled input.
5754 for (unsigned i = 0; i != 16; ++i) {
5755 int EltIdx = MaskVals[i];
5757 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5760 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5762 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5763 DAG.getNode(ISD::BUILD_VECTOR, dl,
5764 MVT::v16i8, &pshufbMask[0], 16));
5765 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5768 // No SSSE3 - Calculate in place words and then fix all out of place words
5769 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5770 // the 16 different words that comprise the two doublequadword input vectors.
5771 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5772 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5773 SDValue NewV = V2Only ? V2 : V1;
5774 for (int i = 0; i != 8; ++i) {
5775 int Elt0 = MaskVals[i*2];
5776 int Elt1 = MaskVals[i*2+1];
5778 // This word of the result is all undef, skip it.
5779 if (Elt0 < 0 && Elt1 < 0)
5782 // This word of the result is already in the correct place, skip it.
5783 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5785 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5788 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5789 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5792 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5793 // using a single extract together, load it and store it.
5794 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5795 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5796 DAG.getIntPtrConstant(Elt1 / 2));
5797 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5798 DAG.getIntPtrConstant(i));
5802 // If Elt1 is defined, extract it from the appropriate source. If the
5803 // source byte is not also odd, shift the extracted word left 8 bits
5804 // otherwise clear the bottom 8 bits if we need to do an or.
5806 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5807 DAG.getIntPtrConstant(Elt1 / 2));
5808 if ((Elt1 & 1) == 0)
5809 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5811 TLI.getShiftAmountTy(InsElt.getValueType())));
5813 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5814 DAG.getConstant(0xFF00, MVT::i16));
5816 // If Elt0 is defined, extract it from the appropriate source. If the
5817 // source byte is not also even, shift the extracted word right 8 bits. If
5818 // Elt1 was also defined, OR the extracted values together before
5819 // inserting them in the result.
5821 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5822 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5823 if ((Elt0 & 1) != 0)
5824 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5826 TLI.getShiftAmountTy(InsElt0.getValueType())));
5828 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5829 DAG.getConstant(0x00FF, MVT::i16));
5830 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5833 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5834 DAG.getIntPtrConstant(i));
5836 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5839 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5840 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5841 /// done when every pair / quad of shuffle mask elements point to elements in
5842 /// the right sequence. e.g.
5843 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5845 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5846 SelectionDAG &DAG, DebugLoc dl) {
5847 EVT VT = SVOp->getValueType(0);
5848 SDValue V1 = SVOp->getOperand(0);
5849 SDValue V2 = SVOp->getOperand(1);
5850 unsigned NumElems = VT.getVectorNumElements();
5851 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5853 switch (VT.getSimpleVT().SimpleTy) {
5854 default: assert(false && "Unexpected!");
5855 case MVT::v4f32: NewVT = MVT::v2f64; break;
5856 case MVT::v4i32: NewVT = MVT::v2i64; break;
5857 case MVT::v8i16: NewVT = MVT::v4i32; break;
5858 case MVT::v16i8: NewVT = MVT::v4i32; break;
5861 int Scale = NumElems / NewWidth;
5862 SmallVector<int, 8> MaskVec;
5863 for (unsigned i = 0; i < NumElems; i += Scale) {
5865 for (int j = 0; j < Scale; ++j) {
5866 int EltIdx = SVOp->getMaskElt(i+j);
5870 StartIdx = EltIdx - (EltIdx % Scale);
5871 if (EltIdx != StartIdx + j)
5875 MaskVec.push_back(-1);
5877 MaskVec.push_back(StartIdx / Scale);
5880 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5881 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5882 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5885 /// getVZextMovL - Return a zero-extending vector move low node.
5887 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5888 SDValue SrcOp, SelectionDAG &DAG,
5889 const X86Subtarget *Subtarget, DebugLoc dl) {
5890 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5891 LoadSDNode *LD = NULL;
5892 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5893 LD = dyn_cast<LoadSDNode>(SrcOp);
5895 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5897 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5898 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5899 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5900 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5901 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5903 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5904 return DAG.getNode(ISD::BITCAST, dl, VT,
5905 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5906 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5914 return DAG.getNode(ISD::BITCAST, dl, VT,
5915 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5916 DAG.getNode(ISD::BITCAST, dl,
5920 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5921 /// which could not be matched by any known target speficic shuffle
5923 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5924 EVT VT = SVOp->getValueType(0);
5926 unsigned NumElems = VT.getVectorNumElements();
5927 unsigned NumLaneElems = NumElems / 2;
5929 int MinRange[2][2] = { { static_cast<int>(NumElems),
5930 static_cast<int>(NumElems) },
5931 { static_cast<int>(NumElems),
5932 static_cast<int>(NumElems) } };
5933 int MaxRange[2][2] = { { -1, -1 }, { -1, -1 } };
5935 // Collect used ranges for each source in each lane
5936 for (unsigned l = 0; l < 2; ++l) {
5937 unsigned LaneStart = l*NumLaneElems;
5938 for (unsigned i = 0; i != NumLaneElems; ++i) {
5939 int Idx = SVOp->getMaskElt(i+LaneStart);
5944 if (Idx >= (int)NumElems) {
5949 if (Idx > MaxRange[l][Input])
5950 MaxRange[l][Input] = Idx;
5951 if (Idx < MinRange[l][Input])
5952 MinRange[l][Input] = Idx;
5956 // Make sure each range is 128-bits
5957 int ExtractIdx[2][2] = { { -1, -1 }, { -1, -1 } };
5958 for (unsigned l = 0; l < 2; ++l) {
5959 for (unsigned Input = 0; Input < 2; ++Input) {
5960 if (MinRange[l][Input] == (int)NumElems && MaxRange[l][Input] < 0)
5963 if (MinRange[l][Input] >= 0 && MaxRange[l][Input] < (int)NumLaneElems)
5964 ExtractIdx[l][Input] = 0;
5965 else if (MinRange[l][Input] >= (int)NumLaneElems &&
5966 MaxRange[l][Input] < (int)NumElems)
5967 ExtractIdx[l][Input] = NumLaneElems;
5973 DebugLoc dl = SVOp->getDebugLoc();
5974 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5975 EVT NVT = MVT::getVectorVT(EltVT, NumElems/2);
5978 for (unsigned l = 0; l < 2; ++l) {
5979 for (unsigned Input = 0; Input < 2; ++Input) {
5980 if (ExtractIdx[l][Input] >= 0)
5981 Ops[l][Input] = Extract128BitVector(SVOp->getOperand(Input),
5982 DAG.getConstant(ExtractIdx[l][Input], MVT::i32),
5985 Ops[l][Input] = DAG.getUNDEF(NVT);
5989 // Generate 128-bit shuffles
5990 SmallVector<int, 16> Mask1, Mask2;
5991 for (unsigned i = 0; i != NumLaneElems; ++i) {
5992 int Elt = SVOp->getMaskElt(i);
5993 if (Elt >= (int)NumElems) {
5994 Elt %= NumLaneElems;
5995 Elt += NumLaneElems;
5996 } else if (Elt >= 0) {
5997 Elt %= NumLaneElems;
5999 Mask1.push_back(Elt);
6001 for (unsigned i = NumLaneElems; i != NumElems; ++i) {
6002 int Elt = SVOp->getMaskElt(i);
6003 if (Elt >= (int)NumElems) {
6004 Elt %= NumLaneElems;
6005 Elt += NumLaneElems;
6006 } else if (Elt >= 0) {
6007 Elt %= NumLaneElems;
6009 Mask2.push_back(Elt);
6012 SDValue Shuf1 = DAG.getVectorShuffle(NVT, dl, Ops[0][0], Ops[0][1], &Mask1[0]);
6013 SDValue Shuf2 = DAG.getVectorShuffle(NVT, dl, Ops[1][0], Ops[1][1], &Mask2[0]);
6015 // Concatenate the result back
6016 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shuf1,
6017 DAG.getConstant(0, MVT::i32), DAG, dl);
6018 return Insert128BitVector(V, Shuf2, DAG.getConstant(NumElems/2, MVT::i32),
6022 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6023 /// 4 elements, and match them with several different shuffle types.
6025 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6026 SDValue V1 = SVOp->getOperand(0);
6027 SDValue V2 = SVOp->getOperand(1);
6028 DebugLoc dl = SVOp->getDebugLoc();
6029 EVT VT = SVOp->getValueType(0);
6031 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6033 SmallVector<std::pair<int, int>, 8> Locs;
6035 SmallVector<int, 8> Mask1(4U, -1);
6036 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6040 for (unsigned i = 0; i != 4; ++i) {
6041 int Idx = PermMask[i];
6043 Locs[i] = std::make_pair(-1, -1);
6045 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6047 Locs[i] = std::make_pair(0, NumLo);
6051 Locs[i] = std::make_pair(1, NumHi);
6053 Mask1[2+NumHi] = Idx;
6059 if (NumLo <= 2 && NumHi <= 2) {
6060 // If no more than two elements come from either vector. This can be
6061 // implemented with two shuffles. First shuffle gather the elements.
6062 // The second shuffle, which takes the first shuffle as both of its
6063 // vector operands, put the elements into the right order.
6064 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6066 SmallVector<int, 8> Mask2(4U, -1);
6068 for (unsigned i = 0; i != 4; ++i) {
6069 if (Locs[i].first == -1)
6072 unsigned Idx = (i < 2) ? 0 : 4;
6073 Idx += Locs[i].first * 2 + Locs[i].second;
6078 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6079 } else if (NumLo == 3 || NumHi == 3) {
6080 // Otherwise, we must have three elements from one vector, call it X, and
6081 // one element from the other, call it Y. First, use a shufps to build an
6082 // intermediate vector with the one element from Y and the element from X
6083 // that will be in the same half in the final destination (the indexes don't
6084 // matter). Then, use a shufps to build the final vector, taking the half
6085 // containing the element from Y from the intermediate, and the other half
6088 // Normalize it so the 3 elements come from V1.
6089 CommuteVectorShuffleMask(PermMask, 4);
6093 // Find the element from V2.
6095 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6096 int Val = PermMask[HiIndex];
6103 Mask1[0] = PermMask[HiIndex];
6105 Mask1[2] = PermMask[HiIndex^1];
6107 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6110 Mask1[0] = PermMask[0];
6111 Mask1[1] = PermMask[1];
6112 Mask1[2] = HiIndex & 1 ? 6 : 4;
6113 Mask1[3] = HiIndex & 1 ? 4 : 6;
6114 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6116 Mask1[0] = HiIndex & 1 ? 2 : 0;
6117 Mask1[1] = HiIndex & 1 ? 0 : 2;
6118 Mask1[2] = PermMask[2];
6119 Mask1[3] = PermMask[3];
6124 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6128 // Break it into (shuffle shuffle_hi, shuffle_lo).
6131 SmallVector<int,8> LoMask(4U, -1);
6132 SmallVector<int,8> HiMask(4U, -1);
6134 SmallVector<int,8> *MaskPtr = &LoMask;
6135 unsigned MaskIdx = 0;
6138 for (unsigned i = 0; i != 4; ++i) {
6145 int Idx = PermMask[i];
6147 Locs[i] = std::make_pair(-1, -1);
6148 } else if (Idx < 4) {
6149 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6150 (*MaskPtr)[LoIdx] = Idx;
6153 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6154 (*MaskPtr)[HiIdx] = Idx;
6159 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6160 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6161 SmallVector<int, 8> MaskOps;
6162 for (unsigned i = 0; i != 4; ++i) {
6163 if (Locs[i].first == -1) {
6164 MaskOps.push_back(-1);
6166 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
6167 MaskOps.push_back(Idx);
6170 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6173 static bool MayFoldVectorLoad(SDValue V) {
6174 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6175 V = V.getOperand(0);
6176 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6177 V = V.getOperand(0);
6178 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6179 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6180 // BUILD_VECTOR (load), undef
6181 V = V.getOperand(0);
6187 // FIXME: the version above should always be used. Since there's
6188 // a bug where several vector shuffles can't be folded because the
6189 // DAG is not updated during lowering and a node claims to have two
6190 // uses while it only has one, use this version, and let isel match
6191 // another instruction if the load really happens to have more than
6192 // one use. Remove this version after this bug get fixed.
6193 // rdar://8434668, PR8156
6194 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6195 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6196 V = V.getOperand(0);
6197 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6198 V = V.getOperand(0);
6199 if (ISD::isNormalLoad(V.getNode()))
6204 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6205 /// a vector extract, and if both can be later optimized into a single load.
6206 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6207 /// here because otherwise a target specific shuffle node is going to be
6208 /// emitted for this shuffle, and the optimization not done.
6209 /// FIXME: This is probably not the best approach, but fix the problem
6210 /// until the right path is decided.
6212 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6213 const TargetLowering &TLI) {
6214 EVT VT = V.getValueType();
6215 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6217 // Be sure that the vector shuffle is present in a pattern like this:
6218 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6222 SDNode *N = *V.getNode()->use_begin();
6223 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6226 SDValue EltNo = N->getOperand(1);
6227 if (!isa<ConstantSDNode>(EltNo))
6230 // If the bit convert changed the number of elements, it is unsafe
6231 // to examine the mask.
6232 bool HasShuffleIntoBitcast = false;
6233 if (V.getOpcode() == ISD::BITCAST) {
6234 EVT SrcVT = V.getOperand(0).getValueType();
6235 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6237 V = V.getOperand(0);
6238 HasShuffleIntoBitcast = true;
6241 // Select the input vector, guarding against out of range extract vector.
6242 unsigned NumElems = VT.getVectorNumElements();
6243 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6244 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6245 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6247 // If we are accessing the upper part of a YMM register
6248 // then the EXTRACT_VECTOR_ELT is likely to be legalized to a sequence of
6249 // EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which are not detected at this point
6250 // because the legalization of N did not happen yet.
6251 if (Idx >= (int)NumElems/2 && VT.getSizeInBits() == 256)
6254 // Skip one more bit_convert if necessary
6255 if (V.getOpcode() == ISD::BITCAST)
6256 V = V.getOperand(0);
6258 if (!ISD::isNormalLoad(V.getNode()))
6261 // Is the original load suitable?
6262 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6264 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
6267 if (!HasShuffleIntoBitcast)
6270 // If there's a bitcast before the shuffle, check if the load type and
6271 // alignment is valid.
6272 unsigned Align = LN0->getAlignment();
6274 TLI.getTargetData()->getABITypeAlignment(
6275 VT.getTypeForEVT(*DAG.getContext()));
6277 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6284 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6285 EVT VT = Op.getValueType();
6287 // Canonizalize to v2f64.
6288 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6289 return DAG.getNode(ISD::BITCAST, dl, VT,
6290 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6295 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6297 SDValue V1 = Op.getOperand(0);
6298 SDValue V2 = Op.getOperand(1);
6299 EVT VT = Op.getValueType();
6301 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6303 if (HasSSE2 && VT == MVT::v2f64)
6304 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6306 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6307 return DAG.getNode(ISD::BITCAST, dl, VT,
6308 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6309 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6310 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6314 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6315 SDValue V1 = Op.getOperand(0);
6316 SDValue V2 = Op.getOperand(1);
6317 EVT VT = Op.getValueType();
6319 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6320 "unsupported shuffle type");
6322 if (V2.getOpcode() == ISD::UNDEF)
6326 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6330 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6331 SDValue V1 = Op.getOperand(0);
6332 SDValue V2 = Op.getOperand(1);
6333 EVT VT = Op.getValueType();
6334 unsigned NumElems = VT.getVectorNumElements();
6336 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6337 // operand of these instructions is only memory, so check if there's a
6338 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6340 bool CanFoldLoad = false;
6342 // Trivial case, when V2 comes from a load.
6343 if (MayFoldVectorLoad(V2))
6346 // When V1 is a load, it can be folded later into a store in isel, example:
6347 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6349 // (MOVLPSmr addr:$src1, VR128:$src2)
6350 // So, recognize this potential and also use MOVLPS or MOVLPD
6351 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6354 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6356 if (HasSSE2 && NumElems == 2)
6357 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6360 // If we don't care about the second element, procede to use movss.
6361 if (SVOp->getMaskElt(1) != -1)
6362 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6365 // movl and movlp will both match v2i64, but v2i64 is never matched by
6366 // movl earlier because we make it strict to avoid messing with the movlp load
6367 // folding logic (see the code above getMOVLP call). Match it here then,
6368 // this is horrible, but will stay like this until we move all shuffle
6369 // matching to x86 specific nodes. Note that for the 1st condition all
6370 // types are matched with movsd.
6372 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6373 // as to remove this logic from here, as much as possible
6374 if (NumElems == 2 || !X86::isMOVLMask(SVOp))
6375 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6376 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6379 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6381 // Invert the operand order and use SHUFPS to match it.
6382 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6383 X86::getShuffleSHUFImmediate(SVOp), DAG);
6387 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6388 const TargetLowering &TLI,
6389 const X86Subtarget *Subtarget) {
6390 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6391 EVT VT = Op.getValueType();
6392 DebugLoc dl = Op.getDebugLoc();
6393 SDValue V1 = Op.getOperand(0);
6394 SDValue V2 = Op.getOperand(1);
6396 if (isZeroShuffle(SVOp))
6397 return getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(),
6400 // Handle splat operations
6401 if (SVOp->isSplat()) {
6402 unsigned NumElem = VT.getVectorNumElements();
6403 int Size = VT.getSizeInBits();
6404 // Special case, this is the only place now where it's allowed to return
6405 // a vector_shuffle operation without using a target specific node, because
6406 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6407 // this be moved to DAGCombine instead?
6408 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6411 // Use vbroadcast whenever the splat comes from a foldable load
6412 SDValue LD = isVectorBroadcast(Op, Subtarget);
6414 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
6416 // Handle splats by matching through known shuffle masks
6417 if ((Size == 128 && NumElem <= 4) ||
6418 (Size == 256 && NumElem < 8))
6421 // All remaning splats are promoted to target supported vector shuffles.
6422 return PromoteSplat(SVOp, DAG);
6425 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6427 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6428 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6429 if (NewOp.getNode())
6430 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6431 } else if ((VT == MVT::v4i32 ||
6432 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6433 // FIXME: Figure out a cleaner way to do this.
6434 // Try to make use of movq to zero out the top part.
6435 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6436 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6437 if (NewOp.getNode()) {
6438 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6439 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6440 DAG, Subtarget, dl);
6442 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6443 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6444 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6445 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6446 DAG, Subtarget, dl);
6453 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6454 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6455 SDValue V1 = Op.getOperand(0);
6456 SDValue V2 = Op.getOperand(1);
6457 EVT VT = Op.getValueType();
6458 DebugLoc dl = Op.getDebugLoc();
6459 unsigned NumElems = VT.getVectorNumElements();
6460 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6461 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6462 bool V1IsSplat = false;
6463 bool V2IsSplat = false;
6464 bool HasSSE2 = Subtarget->hasSSE2();
6465 bool HasAVX = Subtarget->hasAVX();
6466 bool HasAVX2 = Subtarget->hasAVX2();
6467 MachineFunction &MF = DAG.getMachineFunction();
6468 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6470 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6472 if (V1IsUndef && V2IsUndef)
6473 return DAG.getUNDEF(VT);
6475 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6477 // Vector shuffle lowering takes 3 steps:
6479 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6480 // narrowing and commutation of operands should be handled.
6481 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6483 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6484 // so the shuffle can be broken into other shuffles and the legalizer can
6485 // try the lowering again.
6487 // The general idea is that no vector_shuffle operation should be left to
6488 // be matched during isel, all of them must be converted to a target specific
6491 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6492 // narrowing and commutation of operands should be handled. The actual code
6493 // doesn't include all of those, work in progress...
6494 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6495 if (NewOp.getNode())
6498 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6499 // unpckh_undef). Only use pshufd if speed is more important than size.
6500 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp, HasAVX2))
6501 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6502 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp, HasAVX2))
6503 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6505 if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3() &&
6506 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6507 return getMOVDDup(Op, dl, V1, DAG);
6509 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6510 return getMOVHighToLow(Op, dl, DAG);
6512 // Use to match splats
6513 if (HasSSE2 && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef &&
6514 (VT == MVT::v2f64 || VT == MVT::v2i64))
6515 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6517 if (X86::isPSHUFDMask(SVOp)) {
6518 // The actual implementation will match the mask in the if above and then
6519 // during isel it can match several different instructions, not only pshufd
6520 // as its name says, sad but true, emulate the behavior for now...
6521 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6522 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6524 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6526 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6527 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6529 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6533 // Check if this can be converted into a logical shift.
6534 bool isLeft = false;
6537 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6538 if (isShift && ShVal.hasOneUse()) {
6539 // If the shifted value has multiple uses, it may be cheaper to use
6540 // v_set0 + movlhps or movhlps, etc.
6541 EVT EltVT = VT.getVectorElementType();
6542 ShAmt *= EltVT.getSizeInBits();
6543 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6546 if (X86::isMOVLMask(SVOp)) {
6547 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6548 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6549 if (!X86::isMOVLPMask(SVOp)) {
6550 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6551 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6553 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6554 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6558 // FIXME: fold these into legal mask.
6559 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp, HasAVX2))
6560 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6562 if (X86::isMOVHLPSMask(SVOp))
6563 return getMOVHighToLow(Op, dl, DAG);
6565 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6566 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6568 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6569 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6571 if (X86::isMOVLPMask(SVOp))
6572 return getMOVLP(Op, dl, DAG, HasSSE2);
6574 if (ShouldXformToMOVHLPS(SVOp) ||
6575 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6576 return CommuteVectorShuffle(SVOp, DAG);
6579 // No better options. Use a vshldq / vsrldq.
6580 EVT EltVT = VT.getVectorElementType();
6581 ShAmt *= EltVT.getSizeInBits();
6582 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6585 bool Commuted = false;
6586 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6587 // 1,1,1,1 -> v8i16 though.
6588 V1IsSplat = isSplatVector(V1.getNode());
6589 V2IsSplat = isSplatVector(V2.getNode());
6591 // Canonicalize the splat or undef, if present, to be on the RHS.
6592 if (V1IsSplat && !V2IsSplat) {
6593 Op = CommuteVectorShuffle(SVOp, DAG);
6594 SVOp = cast<ShuffleVectorSDNode>(Op);
6595 V1 = SVOp->getOperand(0);
6596 V2 = SVOp->getOperand(1);
6597 std::swap(V1IsSplat, V2IsSplat);
6601 ArrayRef<int> M = SVOp->getMask();
6603 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6604 // Shuffling low element of v1 into undef, just return v1.
6607 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6608 // the instruction selector will not match, so get a canonical MOVL with
6609 // swapped operands to undo the commute.
6610 return getMOVL(DAG, dl, VT, V2, V1);
6613 if (isUNPCKLMask(M, VT, HasAVX2))
6614 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6616 if (isUNPCKHMask(M, VT, HasAVX2))
6617 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6620 // Normalize mask so all entries that point to V2 points to its first
6621 // element then try to match unpck{h|l} again. If match, return a
6622 // new vector_shuffle with the corrected mask.
6623 SDValue NewMask = NormalizeMask(SVOp, DAG);
6624 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6625 if (NSVOp != SVOp) {
6626 if (X86::isUNPCKLMask(NSVOp, HasAVX2, true)) {
6628 } else if (X86::isUNPCKHMask(NSVOp, HasAVX2, true)) {
6635 // Commute is back and try unpck* again.
6636 // FIXME: this seems wrong.
6637 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6638 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6640 if (X86::isUNPCKLMask(NewSVOp, HasAVX2))
6641 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V2, V1, DAG);
6643 if (X86::isUNPCKHMask(NewSVOp, HasAVX2))
6644 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V2, V1, DAG);
6647 // Normalize the node to match x86 shuffle ops if needed
6648 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6649 return CommuteVectorShuffle(SVOp, DAG);
6651 // The checks below are all present in isShuffleMaskLegal, but they are
6652 // inlined here right now to enable us to directly emit target specific
6653 // nodes, and remove one by one until they don't return Op anymore.
6655 if (isPALIGNRMask(M, VT, Subtarget))
6656 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6657 getShufflePALIGNRImmediate(SVOp),
6660 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6661 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6662 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6663 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6666 if (isPSHUFHWMask(M, VT))
6667 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6668 X86::getShufflePSHUFHWImmediate(SVOp),
6671 if (isPSHUFLWMask(M, VT))
6672 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6673 X86::getShufflePSHUFLWImmediate(SVOp),
6676 if (isSHUFPMask(M, VT, HasAVX))
6677 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6678 X86::getShuffleSHUFImmediate(SVOp), DAG);
6680 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6681 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6682 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6683 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6685 //===--------------------------------------------------------------------===//
6686 // Generate target specific nodes for 128 or 256-bit shuffles only
6687 // supported in the AVX instruction set.
6690 // Handle VMOVDDUPY permutations
6691 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6692 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6694 // Handle VPERMILPS/D* permutations
6695 if (isVPERMILPMask(M, VT, HasAVX))
6696 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6697 getShuffleVPERMILPImmediate(SVOp), DAG);
6699 // Handle VPERM2F128/VPERM2I128 permutations
6700 if (isVPERM2X128Mask(M, VT, HasAVX))
6701 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6702 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6704 //===--------------------------------------------------------------------===//
6705 // Since no target specific shuffle was selected for this generic one,
6706 // lower it into other known shuffles. FIXME: this isn't true yet, but
6707 // this is the plan.
6710 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6711 if (VT == MVT::v8i16) {
6712 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6713 if (NewOp.getNode())
6717 if (VT == MVT::v16i8) {
6718 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6719 if (NewOp.getNode())
6723 // Handle all 128-bit wide vectors with 4 elements, and match them with
6724 // several different shuffle types.
6725 if (NumElems == 4 && VT.getSizeInBits() == 128)
6726 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6728 // Handle general 256-bit shuffles
6729 if (VT.is256BitVector())
6730 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6736 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6737 SelectionDAG &DAG) const {
6738 EVT VT = Op.getValueType();
6739 DebugLoc dl = Op.getDebugLoc();
6741 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6744 if (VT.getSizeInBits() == 8) {
6745 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6746 Op.getOperand(0), Op.getOperand(1));
6747 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6748 DAG.getValueType(VT));
6749 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6750 } else if (VT.getSizeInBits() == 16) {
6751 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6752 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6754 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6755 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6756 DAG.getNode(ISD::BITCAST, dl,
6760 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6761 Op.getOperand(0), Op.getOperand(1));
6762 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6763 DAG.getValueType(VT));
6764 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6765 } else if (VT == MVT::f32) {
6766 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6767 // the result back to FR32 register. It's only worth matching if the
6768 // result has a single use which is a store or a bitcast to i32. And in
6769 // the case of a store, it's not worth it if the index is a constant 0,
6770 // because a MOVSSmr can be used instead, which is smaller and faster.
6771 if (!Op.hasOneUse())
6773 SDNode *User = *Op.getNode()->use_begin();
6774 if ((User->getOpcode() != ISD::STORE ||
6775 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6776 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6777 (User->getOpcode() != ISD::BITCAST ||
6778 User->getValueType(0) != MVT::i32))
6780 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6781 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6784 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6785 } else if (VT == MVT::i32 || VT == MVT::i64) {
6786 // ExtractPS/pextrq works with constant index.
6787 if (isa<ConstantSDNode>(Op.getOperand(1)))
6795 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6796 SelectionDAG &DAG) const {
6797 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6800 SDValue Vec = Op.getOperand(0);
6801 EVT VecVT = Vec.getValueType();
6803 // If this is a 256-bit vector result, first extract the 128-bit vector and
6804 // then extract the element from the 128-bit vector.
6805 if (VecVT.getSizeInBits() == 256) {
6806 DebugLoc dl = Op.getNode()->getDebugLoc();
6807 unsigned NumElems = VecVT.getVectorNumElements();
6808 SDValue Idx = Op.getOperand(1);
6809 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6811 // Get the 128-bit vector.
6812 bool Upper = IdxVal >= NumElems/2;
6813 Vec = Extract128BitVector(Vec,
6814 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6816 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6817 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6820 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6822 if (Subtarget->hasSSE41()) {
6823 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6828 EVT VT = Op.getValueType();
6829 DebugLoc dl = Op.getDebugLoc();
6830 // TODO: handle v16i8.
6831 if (VT.getSizeInBits() == 16) {
6832 SDValue Vec = Op.getOperand(0);
6833 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6835 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6836 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6837 DAG.getNode(ISD::BITCAST, dl,
6840 // Transform it so it match pextrw which produces a 32-bit result.
6841 EVT EltVT = MVT::i32;
6842 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6843 Op.getOperand(0), Op.getOperand(1));
6844 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6845 DAG.getValueType(VT));
6846 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6847 } else if (VT.getSizeInBits() == 32) {
6848 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6852 // SHUFPS the element to the lowest double word, then movss.
6853 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6854 EVT VVT = Op.getOperand(0).getValueType();
6855 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6856 DAG.getUNDEF(VVT), Mask);
6857 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6858 DAG.getIntPtrConstant(0));
6859 } else if (VT.getSizeInBits() == 64) {
6860 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6861 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6862 // to match extract_elt for f64.
6863 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6867 // UNPCKHPD the element to the lowest double word, then movsd.
6868 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6869 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6870 int Mask[2] = { 1, -1 };
6871 EVT VVT = Op.getOperand(0).getValueType();
6872 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6873 DAG.getUNDEF(VVT), Mask);
6874 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6875 DAG.getIntPtrConstant(0));
6882 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6883 SelectionDAG &DAG) const {
6884 EVT VT = Op.getValueType();
6885 EVT EltVT = VT.getVectorElementType();
6886 DebugLoc dl = Op.getDebugLoc();
6888 SDValue N0 = Op.getOperand(0);
6889 SDValue N1 = Op.getOperand(1);
6890 SDValue N2 = Op.getOperand(2);
6892 if (VT.getSizeInBits() == 256)
6895 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6896 isa<ConstantSDNode>(N2)) {
6898 if (VT == MVT::v8i16)
6899 Opc = X86ISD::PINSRW;
6900 else if (VT == MVT::v16i8)
6901 Opc = X86ISD::PINSRB;
6903 Opc = X86ISD::PINSRB;
6905 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6907 if (N1.getValueType() != MVT::i32)
6908 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6909 if (N2.getValueType() != MVT::i32)
6910 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6911 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6912 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6913 // Bits [7:6] of the constant are the source select. This will always be
6914 // zero here. The DAG Combiner may combine an extract_elt index into these
6915 // bits. For example (insert (extract, 3), 2) could be matched by putting
6916 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6917 // Bits [5:4] of the constant are the destination select. This is the
6918 // value of the incoming immediate.
6919 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6920 // combine either bitwise AND or insert of float 0.0 to set these bits.
6921 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6922 // Create this as a scalar to vector..
6923 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6924 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6925 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6926 isa<ConstantSDNode>(N2)) {
6927 // PINSR* works with constant index.
6934 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6935 EVT VT = Op.getValueType();
6936 EVT EltVT = VT.getVectorElementType();
6938 DebugLoc dl = Op.getDebugLoc();
6939 SDValue N0 = Op.getOperand(0);
6940 SDValue N1 = Op.getOperand(1);
6941 SDValue N2 = Op.getOperand(2);
6943 // If this is a 256-bit vector result, first extract the 128-bit vector,
6944 // insert the element into the extracted half and then place it back.
6945 if (VT.getSizeInBits() == 256) {
6946 if (!isa<ConstantSDNode>(N2))
6949 // Get the desired 128-bit vector half.
6950 unsigned NumElems = VT.getVectorNumElements();
6951 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6952 bool Upper = IdxVal >= NumElems/2;
6953 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6954 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6956 // Insert the element into the desired half.
6957 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6958 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6960 // Insert the changed part back to the 256-bit vector
6961 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6964 if (Subtarget->hasSSE41())
6965 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6967 if (EltVT == MVT::i8)
6970 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6971 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6972 // as its second argument.
6973 if (N1.getValueType() != MVT::i32)
6974 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6975 if (N2.getValueType() != MVT::i32)
6976 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6977 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6983 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6984 LLVMContext *Context = DAG.getContext();
6985 DebugLoc dl = Op.getDebugLoc();
6986 EVT OpVT = Op.getValueType();
6988 // If this is a 256-bit vector result, first insert into a 128-bit
6989 // vector and then insert into the 256-bit vector.
6990 if (OpVT.getSizeInBits() > 128) {
6991 // Insert into a 128-bit vector.
6992 EVT VT128 = EVT::getVectorVT(*Context,
6993 OpVT.getVectorElementType(),
6994 OpVT.getVectorNumElements() / 2);
6996 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6998 // Insert the 128-bit vector.
6999 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
7000 DAG.getConstant(0, MVT::i32),
7004 if (Op.getValueType() == MVT::v1i64 &&
7005 Op.getOperand(0).getValueType() == MVT::i64)
7006 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7008 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7009 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
7010 "Expected an SSE type!");
7011 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
7012 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7015 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7016 // a simple subregister reference or explicit instructions to grab
7017 // upper bits of a vector.
7019 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7020 if (Subtarget->hasAVX()) {
7021 DebugLoc dl = Op.getNode()->getDebugLoc();
7022 SDValue Vec = Op.getNode()->getOperand(0);
7023 SDValue Idx = Op.getNode()->getOperand(1);
7025 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7026 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7027 return Extract128BitVector(Vec, Idx, DAG, dl);
7033 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7034 // simple superregister reference or explicit instructions to insert
7035 // the upper bits of a vector.
7037 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7038 if (Subtarget->hasAVX()) {
7039 DebugLoc dl = Op.getNode()->getDebugLoc();
7040 SDValue Vec = Op.getNode()->getOperand(0);
7041 SDValue SubVec = Op.getNode()->getOperand(1);
7042 SDValue Idx = Op.getNode()->getOperand(2);
7044 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7045 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7046 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7052 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7053 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7054 // one of the above mentioned nodes. It has to be wrapped because otherwise
7055 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7056 // be used to form addressing mode. These wrapped nodes will be selected
7059 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7060 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7062 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7064 unsigned char OpFlag = 0;
7065 unsigned WrapperKind = X86ISD::Wrapper;
7066 CodeModel::Model M = getTargetMachine().getCodeModel();
7068 if (Subtarget->isPICStyleRIPRel() &&
7069 (M == CodeModel::Small || M == CodeModel::Kernel))
7070 WrapperKind = X86ISD::WrapperRIP;
7071 else if (Subtarget->isPICStyleGOT())
7072 OpFlag = X86II::MO_GOTOFF;
7073 else if (Subtarget->isPICStyleStubPIC())
7074 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7076 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7078 CP->getOffset(), OpFlag);
7079 DebugLoc DL = CP->getDebugLoc();
7080 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7081 // With PIC, the address is actually $g + Offset.
7083 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7084 DAG.getNode(X86ISD::GlobalBaseReg,
7085 DebugLoc(), getPointerTy()),
7092 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7093 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7095 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7097 unsigned char OpFlag = 0;
7098 unsigned WrapperKind = X86ISD::Wrapper;
7099 CodeModel::Model M = getTargetMachine().getCodeModel();
7101 if (Subtarget->isPICStyleRIPRel() &&
7102 (M == CodeModel::Small || M == CodeModel::Kernel))
7103 WrapperKind = X86ISD::WrapperRIP;
7104 else if (Subtarget->isPICStyleGOT())
7105 OpFlag = X86II::MO_GOTOFF;
7106 else if (Subtarget->isPICStyleStubPIC())
7107 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7109 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7111 DebugLoc DL = JT->getDebugLoc();
7112 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7114 // With PIC, the address is actually $g + Offset.
7116 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7117 DAG.getNode(X86ISD::GlobalBaseReg,
7118 DebugLoc(), getPointerTy()),
7125 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7126 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7128 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7130 unsigned char OpFlag = 0;
7131 unsigned WrapperKind = X86ISD::Wrapper;
7132 CodeModel::Model M = getTargetMachine().getCodeModel();
7134 if (Subtarget->isPICStyleRIPRel() &&
7135 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7136 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7137 OpFlag = X86II::MO_GOTPCREL;
7138 WrapperKind = X86ISD::WrapperRIP;
7139 } else if (Subtarget->isPICStyleGOT()) {
7140 OpFlag = X86II::MO_GOT;
7141 } else if (Subtarget->isPICStyleStubPIC()) {
7142 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7143 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7144 OpFlag = X86II::MO_DARWIN_NONLAZY;
7147 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7149 DebugLoc DL = Op.getDebugLoc();
7150 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7153 // With PIC, the address is actually $g + Offset.
7154 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7155 !Subtarget->is64Bit()) {
7156 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7157 DAG.getNode(X86ISD::GlobalBaseReg,
7158 DebugLoc(), getPointerTy()),
7162 // For symbols that require a load from a stub to get the address, emit the
7164 if (isGlobalStubReference(OpFlag))
7165 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7166 MachinePointerInfo::getGOT(), false, false, false, 0);
7172 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7173 // Create the TargetBlockAddressAddress node.
7174 unsigned char OpFlags =
7175 Subtarget->ClassifyBlockAddressReference();
7176 CodeModel::Model M = getTargetMachine().getCodeModel();
7177 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7178 DebugLoc dl = Op.getDebugLoc();
7179 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7180 /*isTarget=*/true, OpFlags);
7182 if (Subtarget->isPICStyleRIPRel() &&
7183 (M == CodeModel::Small || M == CodeModel::Kernel))
7184 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7186 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7188 // With PIC, the address is actually $g + Offset.
7189 if (isGlobalRelativeToPICBase(OpFlags)) {
7190 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7191 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7199 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7201 SelectionDAG &DAG) const {
7202 // Create the TargetGlobalAddress node, folding in the constant
7203 // offset if it is legal.
7204 unsigned char OpFlags =
7205 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7206 CodeModel::Model M = getTargetMachine().getCodeModel();
7208 if (OpFlags == X86II::MO_NO_FLAG &&
7209 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7210 // A direct static reference to a global.
7211 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7214 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7217 if (Subtarget->isPICStyleRIPRel() &&
7218 (M == CodeModel::Small || M == CodeModel::Kernel))
7219 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7221 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7223 // With PIC, the address is actually $g + Offset.
7224 if (isGlobalRelativeToPICBase(OpFlags)) {
7225 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7226 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7230 // For globals that require a load from a stub to get the address, emit the
7232 if (isGlobalStubReference(OpFlags))
7233 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7234 MachinePointerInfo::getGOT(), false, false, false, 0);
7236 // If there was a non-zero offset that we didn't fold, create an explicit
7239 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7240 DAG.getConstant(Offset, getPointerTy()));
7246 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7247 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7248 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7249 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7253 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7254 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7255 unsigned char OperandFlags) {
7256 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7257 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7258 DebugLoc dl = GA->getDebugLoc();
7259 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7260 GA->getValueType(0),
7264 SDValue Ops[] = { Chain, TGA, *InFlag };
7265 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7267 SDValue Ops[] = { Chain, TGA };
7268 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7271 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7272 MFI->setAdjustsStack(true);
7274 SDValue Flag = Chain.getValue(1);
7275 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7278 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7280 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7283 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7284 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7285 DAG.getNode(X86ISD::GlobalBaseReg,
7286 DebugLoc(), PtrVT), InFlag);
7287 InFlag = Chain.getValue(1);
7289 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7292 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7294 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7296 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7297 X86::RAX, X86II::MO_TLSGD);
7300 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7301 // "local exec" model.
7302 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7303 const EVT PtrVT, TLSModel::Model model,
7305 DebugLoc dl = GA->getDebugLoc();
7307 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7308 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7309 is64Bit ? 257 : 256));
7311 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7312 DAG.getIntPtrConstant(0),
7313 MachinePointerInfo(Ptr),
7314 false, false, false, 0);
7316 unsigned char OperandFlags = 0;
7317 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7319 unsigned WrapperKind = X86ISD::Wrapper;
7320 if (model == TLSModel::LocalExec) {
7321 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7322 } else if (is64Bit) {
7323 assert(model == TLSModel::InitialExec);
7324 OperandFlags = X86II::MO_GOTTPOFF;
7325 WrapperKind = X86ISD::WrapperRIP;
7327 assert(model == TLSModel::InitialExec);
7328 OperandFlags = X86II::MO_INDNTPOFF;
7331 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7333 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7334 GA->getValueType(0),
7335 GA->getOffset(), OperandFlags);
7336 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7338 if (model == TLSModel::InitialExec)
7339 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7340 MachinePointerInfo::getGOT(), false, false, false, 0);
7342 // The address of the thread local variable is the add of the thread
7343 // pointer with the offset of the variable.
7344 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7348 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7350 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7351 const GlobalValue *GV = GA->getGlobal();
7353 if (Subtarget->isTargetELF()) {
7354 // TODO: implement the "local dynamic" model
7355 // TODO: implement the "initial exec"model for pic executables
7357 // If GV is an alias then use the aliasee for determining
7358 // thread-localness.
7359 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7360 GV = GA->resolveAliasedGlobal(false);
7362 TLSModel::Model model
7363 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7366 case TLSModel::GeneralDynamic:
7367 case TLSModel::LocalDynamic: // not implemented
7368 if (Subtarget->is64Bit())
7369 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7370 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7372 case TLSModel::InitialExec:
7373 case TLSModel::LocalExec:
7374 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7375 Subtarget->is64Bit());
7377 } else if (Subtarget->isTargetDarwin()) {
7378 // Darwin only has one model of TLS. Lower to that.
7379 unsigned char OpFlag = 0;
7380 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7381 X86ISD::WrapperRIP : X86ISD::Wrapper;
7383 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7385 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7386 !Subtarget->is64Bit();
7388 OpFlag = X86II::MO_TLVP_PIC_BASE;
7390 OpFlag = X86II::MO_TLVP;
7391 DebugLoc DL = Op.getDebugLoc();
7392 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7393 GA->getValueType(0),
7394 GA->getOffset(), OpFlag);
7395 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7397 // With PIC32, the address is actually $g + Offset.
7399 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7400 DAG.getNode(X86ISD::GlobalBaseReg,
7401 DebugLoc(), getPointerTy()),
7404 // Lowering the machine isd will make sure everything is in the right
7406 SDValue Chain = DAG.getEntryNode();
7407 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7408 SDValue Args[] = { Chain, Offset };
7409 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7411 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7412 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7413 MFI->setAdjustsStack(true);
7415 // And our return value (tls address) is in the standard call return value
7417 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7418 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7422 llvm_unreachable("TLS not implemented for this target.");
7426 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7427 /// and take a 2 x i32 value to shift plus a shift amount.
7428 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7429 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7430 EVT VT = Op.getValueType();
7431 unsigned VTBits = VT.getSizeInBits();
7432 DebugLoc dl = Op.getDebugLoc();
7433 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7434 SDValue ShOpLo = Op.getOperand(0);
7435 SDValue ShOpHi = Op.getOperand(1);
7436 SDValue ShAmt = Op.getOperand(2);
7437 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7438 DAG.getConstant(VTBits - 1, MVT::i8))
7439 : DAG.getConstant(0, VT);
7442 if (Op.getOpcode() == ISD::SHL_PARTS) {
7443 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7444 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7446 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7447 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7450 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7451 DAG.getConstant(VTBits, MVT::i8));
7452 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7453 AndNode, DAG.getConstant(0, MVT::i8));
7456 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7457 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7458 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7460 if (Op.getOpcode() == ISD::SHL_PARTS) {
7461 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7462 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7464 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7465 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7468 SDValue Ops[2] = { Lo, Hi };
7469 return DAG.getMergeValues(Ops, 2, dl);
7472 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7473 SelectionDAG &DAG) const {
7474 EVT SrcVT = Op.getOperand(0).getValueType();
7476 if (SrcVT.isVector())
7479 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7480 "Unknown SINT_TO_FP to lower!");
7482 // These are really Legal; return the operand so the caller accepts it as
7484 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7486 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7487 Subtarget->is64Bit()) {
7491 DebugLoc dl = Op.getDebugLoc();
7492 unsigned Size = SrcVT.getSizeInBits()/8;
7493 MachineFunction &MF = DAG.getMachineFunction();
7494 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7495 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7496 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7498 MachinePointerInfo::getFixedStack(SSFI),
7500 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7503 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7505 SelectionDAG &DAG) const {
7507 DebugLoc DL = Op.getDebugLoc();
7509 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7511 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7513 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7515 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7517 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7518 MachineMemOperand *MMO;
7520 int SSFI = FI->getIndex();
7522 DAG.getMachineFunction()
7523 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7524 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7526 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7527 StackSlot = StackSlot.getOperand(1);
7529 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7530 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7532 Tys, Ops, array_lengthof(Ops),
7536 Chain = Result.getValue(1);
7537 SDValue InFlag = Result.getValue(2);
7539 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7540 // shouldn't be necessary except that RFP cannot be live across
7541 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7542 MachineFunction &MF = DAG.getMachineFunction();
7543 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7544 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7545 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7546 Tys = DAG.getVTList(MVT::Other);
7548 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7550 MachineMemOperand *MMO =
7551 DAG.getMachineFunction()
7552 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7553 MachineMemOperand::MOStore, SSFISize, SSFISize);
7555 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7556 Ops, array_lengthof(Ops),
7557 Op.getValueType(), MMO);
7558 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7559 MachinePointerInfo::getFixedStack(SSFI),
7560 false, false, false, 0);
7566 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7567 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7568 SelectionDAG &DAG) const {
7569 // This algorithm is not obvious. Here it is what we're trying to output:
7572 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7573 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7577 pshufd $0x4e, %xmm0, %xmm1
7582 DebugLoc dl = Op.getDebugLoc();
7583 LLVMContext *Context = DAG.getContext();
7585 // Build some magic constants.
7586 SmallVector<Constant*,4> CV0;
7587 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7588 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7589 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7590 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7591 Constant *C0 = ConstantVector::get(CV0);
7592 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7594 SmallVector<Constant*,2> CV1;
7596 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7598 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7599 Constant *C1 = ConstantVector::get(CV1);
7600 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7602 // Load the 64-bit value into an XMM register.
7603 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7605 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7606 MachinePointerInfo::getConstantPool(),
7607 false, false, false, 16);
7608 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7609 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7612 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7613 MachinePointerInfo::getConstantPool(),
7614 false, false, false, 16);
7615 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7616 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7619 if (Subtarget->hasSSE3()) {
7620 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7621 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7623 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7624 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7626 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7627 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7631 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7632 DAG.getIntPtrConstant(0));
7635 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7636 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7637 SelectionDAG &DAG) const {
7638 DebugLoc dl = Op.getDebugLoc();
7639 // FP constant to bias correct the final result.
7640 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7643 // Load the 32-bit value into an XMM register.
7644 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7647 // Zero out the upper parts of the register.
7648 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7650 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7651 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7652 DAG.getIntPtrConstant(0));
7654 // Or the load with the bias.
7655 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7656 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7657 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7659 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7660 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7661 MVT::v2f64, Bias)));
7662 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7663 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7664 DAG.getIntPtrConstant(0));
7666 // Subtract the bias.
7667 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7669 // Handle final rounding.
7670 EVT DestVT = Op.getValueType();
7672 if (DestVT.bitsLT(MVT::f64)) {
7673 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7674 DAG.getIntPtrConstant(0));
7675 } else if (DestVT.bitsGT(MVT::f64)) {
7676 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7679 // Handle final rounding.
7683 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7684 SelectionDAG &DAG) const {
7685 SDValue N0 = Op.getOperand(0);
7686 DebugLoc dl = Op.getDebugLoc();
7688 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7689 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7690 // the optimization here.
7691 if (DAG.SignBitIsZero(N0))
7692 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7694 EVT SrcVT = N0.getValueType();
7695 EVT DstVT = Op.getValueType();
7696 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7697 return LowerUINT_TO_FP_i64(Op, DAG);
7698 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7699 return LowerUINT_TO_FP_i32(Op, DAG);
7700 else if (Subtarget->is64Bit() &&
7701 SrcVT == MVT::i64 && DstVT == MVT::f32)
7704 // Make a 64-bit buffer, and use it to build an FILD.
7705 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7706 if (SrcVT == MVT::i32) {
7707 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7708 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7709 getPointerTy(), StackSlot, WordOff);
7710 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7711 StackSlot, MachinePointerInfo(),
7713 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7714 OffsetSlot, MachinePointerInfo(),
7716 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7720 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7721 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7722 StackSlot, MachinePointerInfo(),
7724 // For i64 source, we need to add the appropriate power of 2 if the input
7725 // was negative. This is the same as the optimization in
7726 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7727 // we must be careful to do the computation in x87 extended precision, not
7728 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7729 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7730 MachineMemOperand *MMO =
7731 DAG.getMachineFunction()
7732 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7733 MachineMemOperand::MOLoad, 8, 8);
7735 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7736 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7737 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7740 APInt FF(32, 0x5F800000ULL);
7742 // Check whether the sign bit is set.
7743 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7744 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7747 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7748 SDValue FudgePtr = DAG.getConstantPool(
7749 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7752 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7753 SDValue Zero = DAG.getIntPtrConstant(0);
7754 SDValue Four = DAG.getIntPtrConstant(4);
7755 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7757 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7759 // Load the value out, extending it from f32 to f80.
7760 // FIXME: Avoid the extend by constructing the right constant pool?
7761 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7762 FudgePtr, MachinePointerInfo::getConstantPool(),
7763 MVT::f32, false, false, 4);
7764 // Extend everything to 80 bits to force it to be done on x87.
7765 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7766 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7769 std::pair<SDValue,SDValue> X86TargetLowering::
7770 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7771 DebugLoc DL = Op.getDebugLoc();
7773 EVT DstTy = Op.getValueType();
7776 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7780 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7781 DstTy.getSimpleVT() >= MVT::i16 &&
7782 "Unknown FP_TO_SINT to lower!");
7784 // These are really Legal.
7785 if (DstTy == MVT::i32 &&
7786 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7787 return std::make_pair(SDValue(), SDValue());
7788 if (Subtarget->is64Bit() &&
7789 DstTy == MVT::i64 &&
7790 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7791 return std::make_pair(SDValue(), SDValue());
7793 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7795 MachineFunction &MF = DAG.getMachineFunction();
7796 unsigned MemSize = DstTy.getSizeInBits()/8;
7797 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7798 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7803 switch (DstTy.getSimpleVT().SimpleTy) {
7804 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7805 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7806 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7807 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7810 SDValue Chain = DAG.getEntryNode();
7811 SDValue Value = Op.getOperand(0);
7812 EVT TheVT = Op.getOperand(0).getValueType();
7813 if (isScalarFPTypeInSSEReg(TheVT)) {
7814 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7815 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7816 MachinePointerInfo::getFixedStack(SSFI),
7818 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7820 Chain, StackSlot, DAG.getValueType(TheVT)
7823 MachineMemOperand *MMO =
7824 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7825 MachineMemOperand::MOLoad, MemSize, MemSize);
7826 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7828 Chain = Value.getValue(1);
7829 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7830 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7833 MachineMemOperand *MMO =
7834 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7835 MachineMemOperand::MOStore, MemSize, MemSize);
7837 // Build the FP_TO_INT*_IN_MEM
7838 SDValue Ops[] = { Chain, Value, StackSlot };
7839 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7840 Ops, 3, DstTy, MMO);
7842 return std::make_pair(FIST, StackSlot);
7845 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7846 SelectionDAG &DAG) const {
7847 if (Op.getValueType().isVector())
7850 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7851 SDValue FIST = Vals.first, StackSlot = Vals.second;
7852 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7853 if (FIST.getNode() == 0) return Op;
7856 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7857 FIST, StackSlot, MachinePointerInfo(),
7858 false, false, false, 0);
7861 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7862 SelectionDAG &DAG) const {
7863 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7864 SDValue FIST = Vals.first, StackSlot = Vals.second;
7865 assert(FIST.getNode() && "Unexpected failure");
7868 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7869 FIST, StackSlot, MachinePointerInfo(),
7870 false, false, false, 0);
7873 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7874 SelectionDAG &DAG) const {
7875 LLVMContext *Context = DAG.getContext();
7876 DebugLoc dl = Op.getDebugLoc();
7877 EVT VT = Op.getValueType();
7880 EltVT = VT.getVectorElementType();
7882 if (EltVT == MVT::f64) {
7883 C = ConstantVector::getSplat(2,
7884 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7886 C = ConstantVector::getSplat(4,
7887 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7889 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7890 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7891 MachinePointerInfo::getConstantPool(),
7892 false, false, false, 16);
7893 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7896 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7897 LLVMContext *Context = DAG.getContext();
7898 DebugLoc dl = Op.getDebugLoc();
7899 EVT VT = Op.getValueType();
7901 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7902 if (VT.isVector()) {
7903 EltVT = VT.getVectorElementType();
7904 NumElts = VT.getVectorNumElements();
7907 if (EltVT == MVT::f64)
7908 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7910 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7911 C = ConstantVector::getSplat(NumElts, C);
7912 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7913 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7914 MachinePointerInfo::getConstantPool(),
7915 false, false, false, 16);
7916 if (VT.isVector()) {
7917 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7918 return DAG.getNode(ISD::BITCAST, dl, VT,
7919 DAG.getNode(ISD::XOR, dl, XORVT,
7920 DAG.getNode(ISD::BITCAST, dl, XORVT,
7922 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7924 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7928 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7929 LLVMContext *Context = DAG.getContext();
7930 SDValue Op0 = Op.getOperand(0);
7931 SDValue Op1 = Op.getOperand(1);
7932 DebugLoc dl = Op.getDebugLoc();
7933 EVT VT = Op.getValueType();
7934 EVT SrcVT = Op1.getValueType();
7936 // If second operand is smaller, extend it first.
7937 if (SrcVT.bitsLT(VT)) {
7938 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7941 // And if it is bigger, shrink it first.
7942 if (SrcVT.bitsGT(VT)) {
7943 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7947 // At this point the operands and the result should have the same
7948 // type, and that won't be f80 since that is not custom lowered.
7950 // First get the sign bit of second operand.
7951 SmallVector<Constant*,4> CV;
7952 if (SrcVT == MVT::f64) {
7953 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7954 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7956 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7957 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7958 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7959 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7961 Constant *C = ConstantVector::get(CV);
7962 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7963 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7964 MachinePointerInfo::getConstantPool(),
7965 false, false, false, 16);
7966 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7968 // Shift sign bit right or left if the two operands have different types.
7969 if (SrcVT.bitsGT(VT)) {
7970 // Op0 is MVT::f32, Op1 is MVT::f64.
7971 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7972 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7973 DAG.getConstant(32, MVT::i32));
7974 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7975 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7976 DAG.getIntPtrConstant(0));
7979 // Clear first operand sign bit.
7981 if (VT == MVT::f64) {
7982 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7983 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7985 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7986 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7987 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7988 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7990 C = ConstantVector::get(CV);
7991 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7992 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7993 MachinePointerInfo::getConstantPool(),
7994 false, false, false, 16);
7995 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
7997 // Or the value with the sign bit.
7998 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8001 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8002 SDValue N0 = Op.getOperand(0);
8003 DebugLoc dl = Op.getDebugLoc();
8004 EVT VT = Op.getValueType();
8006 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8007 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8008 DAG.getConstant(1, VT));
8009 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8012 /// Emit nodes that will be selected as "test Op0,Op0", or something
8014 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8015 SelectionDAG &DAG) const {
8016 DebugLoc dl = Op.getDebugLoc();
8018 // CF and OF aren't always set the way we want. Determine which
8019 // of these we need.
8020 bool NeedCF = false;
8021 bool NeedOF = false;
8024 case X86::COND_A: case X86::COND_AE:
8025 case X86::COND_B: case X86::COND_BE:
8028 case X86::COND_G: case X86::COND_GE:
8029 case X86::COND_L: case X86::COND_LE:
8030 case X86::COND_O: case X86::COND_NO:
8035 // See if we can use the EFLAGS value from the operand instead of
8036 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8037 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8038 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8039 // Emit a CMP with 0, which is the TEST pattern.
8040 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8041 DAG.getConstant(0, Op.getValueType()));
8043 unsigned Opcode = 0;
8044 unsigned NumOperands = 0;
8045 switch (Op.getNode()->getOpcode()) {
8047 // Due to an isel shortcoming, be conservative if this add is likely to be
8048 // selected as part of a load-modify-store instruction. When the root node
8049 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8050 // uses of other nodes in the match, such as the ADD in this case. This
8051 // leads to the ADD being left around and reselected, with the result being
8052 // two adds in the output. Alas, even if none our users are stores, that
8053 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8054 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8055 // climbing the DAG back to the root, and it doesn't seem to be worth the
8057 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8058 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8059 if (UI->getOpcode() != ISD::CopyToReg &&
8060 UI->getOpcode() != ISD::SETCC &&
8061 UI->getOpcode() != ISD::STORE)
8064 if (ConstantSDNode *C =
8065 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8066 // An add of one will be selected as an INC.
8067 if (C->getAPIntValue() == 1) {
8068 Opcode = X86ISD::INC;
8073 // An add of negative one (subtract of one) will be selected as a DEC.
8074 if (C->getAPIntValue().isAllOnesValue()) {
8075 Opcode = X86ISD::DEC;
8081 // Otherwise use a regular EFLAGS-setting add.
8082 Opcode = X86ISD::ADD;
8086 // If the primary and result isn't used, don't bother using X86ISD::AND,
8087 // because a TEST instruction will be better.
8088 bool NonFlagUse = false;
8089 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8090 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8092 unsigned UOpNo = UI.getOperandNo();
8093 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8094 // Look pass truncate.
8095 UOpNo = User->use_begin().getOperandNo();
8096 User = *User->use_begin();
8099 if (User->getOpcode() != ISD::BRCOND &&
8100 User->getOpcode() != ISD::SETCC &&
8101 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8114 // Due to the ISEL shortcoming noted above, be conservative if this op is
8115 // likely to be selected as part of a load-modify-store instruction.
8116 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8117 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8118 if (UI->getOpcode() == ISD::STORE)
8121 // Otherwise use a regular EFLAGS-setting instruction.
8122 switch (Op.getNode()->getOpcode()) {
8123 default: llvm_unreachable("unexpected operator!");
8124 case ISD::SUB: Opcode = X86ISD::SUB; break;
8125 case ISD::OR: Opcode = X86ISD::OR; break;
8126 case ISD::XOR: Opcode = X86ISD::XOR; break;
8127 case ISD::AND: Opcode = X86ISD::AND; break;
8139 return SDValue(Op.getNode(), 1);
8146 // Emit a CMP with 0, which is the TEST pattern.
8147 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8148 DAG.getConstant(0, Op.getValueType()));
8150 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8151 SmallVector<SDValue, 4> Ops;
8152 for (unsigned i = 0; i != NumOperands; ++i)
8153 Ops.push_back(Op.getOperand(i));
8155 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8156 DAG.ReplaceAllUsesWith(Op, New);
8157 return SDValue(New.getNode(), 1);
8160 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8162 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8163 SelectionDAG &DAG) const {
8164 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8165 if (C->getAPIntValue() == 0)
8166 return EmitTest(Op0, X86CC, DAG);
8168 DebugLoc dl = Op0.getDebugLoc();
8169 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8172 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8173 /// if it's possible.
8174 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8175 DebugLoc dl, SelectionDAG &DAG) const {
8176 SDValue Op0 = And.getOperand(0);
8177 SDValue Op1 = And.getOperand(1);
8178 if (Op0.getOpcode() == ISD::TRUNCATE)
8179 Op0 = Op0.getOperand(0);
8180 if (Op1.getOpcode() == ISD::TRUNCATE)
8181 Op1 = Op1.getOperand(0);
8184 if (Op1.getOpcode() == ISD::SHL)
8185 std::swap(Op0, Op1);
8186 if (Op0.getOpcode() == ISD::SHL) {
8187 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8188 if (And00C->getZExtValue() == 1) {
8189 // If we looked past a truncate, check that it's only truncating away
8191 unsigned BitWidth = Op0.getValueSizeInBits();
8192 unsigned AndBitWidth = And.getValueSizeInBits();
8193 if (BitWidth > AndBitWidth) {
8194 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8195 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8196 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8200 RHS = Op0.getOperand(1);
8202 } else if (Op1.getOpcode() == ISD::Constant) {
8203 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8204 uint64_t AndRHSVal = AndRHS->getZExtValue();
8205 SDValue AndLHS = Op0;
8207 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8208 LHS = AndLHS.getOperand(0);
8209 RHS = AndLHS.getOperand(1);
8212 // Use BT if the immediate can't be encoded in a TEST instruction.
8213 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8215 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8219 if (LHS.getNode()) {
8220 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8221 // instruction. Since the shift amount is in-range-or-undefined, we know
8222 // that doing a bittest on the i32 value is ok. We extend to i32 because
8223 // the encoding for the i16 version is larger than the i32 version.
8224 // Also promote i16 to i32 for performance / code size reason.
8225 if (LHS.getValueType() == MVT::i8 ||
8226 LHS.getValueType() == MVT::i16)
8227 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8229 // If the operand types disagree, extend the shift amount to match. Since
8230 // BT ignores high bits (like shifts) we can use anyextend.
8231 if (LHS.getValueType() != RHS.getValueType())
8232 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8234 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8235 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8236 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8237 DAG.getConstant(Cond, MVT::i8), BT);
8243 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8245 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8247 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8248 SDValue Op0 = Op.getOperand(0);
8249 SDValue Op1 = Op.getOperand(1);
8250 DebugLoc dl = Op.getDebugLoc();
8251 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8253 // Optimize to BT if possible.
8254 // Lower (X & (1 << N)) == 0 to BT(X, N).
8255 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8256 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8257 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8258 Op1.getOpcode() == ISD::Constant &&
8259 cast<ConstantSDNode>(Op1)->isNullValue() &&
8260 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8261 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8262 if (NewSetCC.getNode())
8266 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8268 if (Op1.getOpcode() == ISD::Constant &&
8269 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8270 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8271 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8273 // If the input is a setcc, then reuse the input setcc or use a new one with
8274 // the inverted condition.
8275 if (Op0.getOpcode() == X86ISD::SETCC) {
8276 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8277 bool Invert = (CC == ISD::SETNE) ^
8278 cast<ConstantSDNode>(Op1)->isNullValue();
8279 if (!Invert) return Op0;
8281 CCode = X86::GetOppositeBranchCondition(CCode);
8282 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8283 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8287 bool isFP = Op1.getValueType().isFloatingPoint();
8288 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8289 if (X86CC == X86::COND_INVALID)
8292 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8293 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8294 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8297 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8298 // ones, and then concatenate the result back.
8299 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8300 EVT VT = Op.getValueType();
8302 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8303 "Unsupported value type for operation");
8305 int NumElems = VT.getVectorNumElements();
8306 DebugLoc dl = Op.getDebugLoc();
8307 SDValue CC = Op.getOperand(2);
8308 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8309 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8311 // Extract the LHS vectors
8312 SDValue LHS = Op.getOperand(0);
8313 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8314 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8316 // Extract the RHS vectors
8317 SDValue RHS = Op.getOperand(1);
8318 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8319 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8321 // Issue the operation on the smaller types and concatenate the result back
8322 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8323 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8324 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8325 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8326 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8330 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8332 SDValue Op0 = Op.getOperand(0);
8333 SDValue Op1 = Op.getOperand(1);
8334 SDValue CC = Op.getOperand(2);
8335 EVT VT = Op.getValueType();
8336 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8337 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8338 DebugLoc dl = Op.getDebugLoc();
8342 EVT EltVT = Op0.getValueType().getVectorElementType();
8343 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8347 // SSE Condition code mapping:
8356 switch (SetCCOpcode) {
8359 case ISD::SETEQ: SSECC = 0; break;
8361 case ISD::SETGT: Swap = true; // Fallthrough
8363 case ISD::SETOLT: SSECC = 1; break;
8365 case ISD::SETGE: Swap = true; // Fallthrough
8367 case ISD::SETOLE: SSECC = 2; break;
8368 case ISD::SETUO: SSECC = 3; break;
8370 case ISD::SETNE: SSECC = 4; break;
8371 case ISD::SETULE: Swap = true;
8372 case ISD::SETUGE: SSECC = 5; break;
8373 case ISD::SETULT: Swap = true;
8374 case ISD::SETUGT: SSECC = 6; break;
8375 case ISD::SETO: SSECC = 7; break;
8378 std::swap(Op0, Op1);
8380 // In the two special cases we can't handle, emit two comparisons.
8382 if (SetCCOpcode == ISD::SETUEQ) {
8384 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8385 DAG.getConstant(3, MVT::i8));
8386 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8387 DAG.getConstant(0, MVT::i8));
8388 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8389 } else if (SetCCOpcode == ISD::SETONE) {
8391 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8392 DAG.getConstant(7, MVT::i8));
8393 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8394 DAG.getConstant(4, MVT::i8));
8395 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8397 llvm_unreachable("Illegal FP comparison");
8399 // Handle all other FP comparisons here.
8400 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8401 DAG.getConstant(SSECC, MVT::i8));
8404 // Break 256-bit integer vector compare into smaller ones.
8405 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8406 return Lower256IntVSETCC(Op, DAG);
8408 // We are handling one of the integer comparisons here. Since SSE only has
8409 // GT and EQ comparisons for integer, swapping operands and multiple
8410 // operations may be required for some comparisons.
8412 bool Swap = false, Invert = false, FlipSigns = false;
8414 switch (SetCCOpcode) {
8416 case ISD::SETNE: Invert = true;
8417 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8418 case ISD::SETLT: Swap = true;
8419 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8420 case ISD::SETGE: Swap = true;
8421 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8422 case ISD::SETULT: Swap = true;
8423 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8424 case ISD::SETUGE: Swap = true;
8425 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8428 std::swap(Op0, Op1);
8430 // Check that the operation in question is available (most are plain SSE2,
8431 // but PCMPGTQ and PCMPEQQ have different requirements).
8432 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8434 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8437 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8438 // bits of the inputs before performing those operations.
8440 EVT EltVT = VT.getVectorElementType();
8441 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8443 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8444 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8446 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8447 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8450 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8452 // If the logical-not of the result is required, perform that now.
8454 Result = DAG.getNOT(dl, Result, VT);
8459 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8460 static bool isX86LogicalCmp(SDValue Op) {
8461 unsigned Opc = Op.getNode()->getOpcode();
8462 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8464 if (Op.getResNo() == 1 &&
8465 (Opc == X86ISD::ADD ||
8466 Opc == X86ISD::SUB ||
8467 Opc == X86ISD::ADC ||
8468 Opc == X86ISD::SBB ||
8469 Opc == X86ISD::SMUL ||
8470 Opc == X86ISD::UMUL ||
8471 Opc == X86ISD::INC ||
8472 Opc == X86ISD::DEC ||
8473 Opc == X86ISD::OR ||
8474 Opc == X86ISD::XOR ||
8475 Opc == X86ISD::AND))
8478 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8484 static bool isZero(SDValue V) {
8485 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8486 return C && C->isNullValue();
8489 static bool isAllOnes(SDValue V) {
8490 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8491 return C && C->isAllOnesValue();
8494 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8495 bool addTest = true;
8496 SDValue Cond = Op.getOperand(0);
8497 SDValue Op1 = Op.getOperand(1);
8498 SDValue Op2 = Op.getOperand(2);
8499 DebugLoc DL = Op.getDebugLoc();
8502 if (Cond.getOpcode() == ISD::SETCC) {
8503 SDValue NewCond = LowerSETCC(Cond, DAG);
8504 if (NewCond.getNode())
8508 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8509 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8510 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8511 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8512 if (Cond.getOpcode() == X86ISD::SETCC &&
8513 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8514 isZero(Cond.getOperand(1).getOperand(1))) {
8515 SDValue Cmp = Cond.getOperand(1);
8517 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8519 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8520 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8521 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8523 SDValue CmpOp0 = Cmp.getOperand(0);
8524 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8525 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8527 SDValue Res = // Res = 0 or -1.
8528 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8529 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8531 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8532 Res = DAG.getNOT(DL, Res, Res.getValueType());
8534 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8535 if (N2C == 0 || !N2C->isNullValue())
8536 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8541 // Look past (and (setcc_carry (cmp ...)), 1).
8542 if (Cond.getOpcode() == ISD::AND &&
8543 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8544 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8545 if (C && C->getAPIntValue() == 1)
8546 Cond = Cond.getOperand(0);
8549 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8550 // setting operand in place of the X86ISD::SETCC.
8551 unsigned CondOpcode = Cond.getOpcode();
8552 if (CondOpcode == X86ISD::SETCC ||
8553 CondOpcode == X86ISD::SETCC_CARRY) {
8554 CC = Cond.getOperand(0);
8556 SDValue Cmp = Cond.getOperand(1);
8557 unsigned Opc = Cmp.getOpcode();
8558 EVT VT = Op.getValueType();
8560 bool IllegalFPCMov = false;
8561 if (VT.isFloatingPoint() && !VT.isVector() &&
8562 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8563 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8565 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8566 Opc == X86ISD::BT) { // FIXME
8570 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8571 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8572 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8573 Cond.getOperand(0).getValueType() != MVT::i8)) {
8574 SDValue LHS = Cond.getOperand(0);
8575 SDValue RHS = Cond.getOperand(1);
8579 switch (CondOpcode) {
8580 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8581 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8582 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8583 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8584 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8585 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8586 default: llvm_unreachable("unexpected overflowing operator");
8588 if (CondOpcode == ISD::UMULO)
8589 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8592 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8594 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8596 if (CondOpcode == ISD::UMULO)
8597 Cond = X86Op.getValue(2);
8599 Cond = X86Op.getValue(1);
8601 CC = DAG.getConstant(X86Cond, MVT::i8);
8606 // Look pass the truncate.
8607 if (Cond.getOpcode() == ISD::TRUNCATE)
8608 Cond = Cond.getOperand(0);
8610 // We know the result of AND is compared against zero. Try to match
8612 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8613 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8614 if (NewSetCC.getNode()) {
8615 CC = NewSetCC.getOperand(0);
8616 Cond = NewSetCC.getOperand(1);
8623 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8624 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8627 // a < b ? -1 : 0 -> RES = ~setcc_carry
8628 // a < b ? 0 : -1 -> RES = setcc_carry
8629 // a >= b ? -1 : 0 -> RES = setcc_carry
8630 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8631 if (Cond.getOpcode() == X86ISD::CMP) {
8632 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8634 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8635 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8636 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8637 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8638 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8639 return DAG.getNOT(DL, Res, Res.getValueType());
8644 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8645 // condition is true.
8646 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8647 SDValue Ops[] = { Op2, Op1, CC, Cond };
8648 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8651 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8652 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8653 // from the AND / OR.
8654 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8655 Opc = Op.getOpcode();
8656 if (Opc != ISD::OR && Opc != ISD::AND)
8658 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8659 Op.getOperand(0).hasOneUse() &&
8660 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8661 Op.getOperand(1).hasOneUse());
8664 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8665 // 1 and that the SETCC node has a single use.
8666 static bool isXor1OfSetCC(SDValue Op) {
8667 if (Op.getOpcode() != ISD::XOR)
8669 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8670 if (N1C && N1C->getAPIntValue() == 1) {
8671 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8672 Op.getOperand(0).hasOneUse();
8677 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8678 bool addTest = true;
8679 SDValue Chain = Op.getOperand(0);
8680 SDValue Cond = Op.getOperand(1);
8681 SDValue Dest = Op.getOperand(2);
8682 DebugLoc dl = Op.getDebugLoc();
8684 bool Inverted = false;
8686 if (Cond.getOpcode() == ISD::SETCC) {
8687 // Check for setcc([su]{add,sub,mul}o == 0).
8688 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8689 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8690 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8691 Cond.getOperand(0).getResNo() == 1 &&
8692 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8693 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8694 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8695 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8696 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8697 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8699 Cond = Cond.getOperand(0);
8701 SDValue NewCond = LowerSETCC(Cond, DAG);
8702 if (NewCond.getNode())
8707 // FIXME: LowerXALUO doesn't handle these!!
8708 else if (Cond.getOpcode() == X86ISD::ADD ||
8709 Cond.getOpcode() == X86ISD::SUB ||
8710 Cond.getOpcode() == X86ISD::SMUL ||
8711 Cond.getOpcode() == X86ISD::UMUL)
8712 Cond = LowerXALUO(Cond, DAG);
8715 // Look pass (and (setcc_carry (cmp ...)), 1).
8716 if (Cond.getOpcode() == ISD::AND &&
8717 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8718 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8719 if (C && C->getAPIntValue() == 1)
8720 Cond = Cond.getOperand(0);
8723 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8724 // setting operand in place of the X86ISD::SETCC.
8725 unsigned CondOpcode = Cond.getOpcode();
8726 if (CondOpcode == X86ISD::SETCC ||
8727 CondOpcode == X86ISD::SETCC_CARRY) {
8728 CC = Cond.getOperand(0);
8730 SDValue Cmp = Cond.getOperand(1);
8731 unsigned Opc = Cmp.getOpcode();
8732 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8733 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8737 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8741 // These can only come from an arithmetic instruction with overflow,
8742 // e.g. SADDO, UADDO.
8743 Cond = Cond.getNode()->getOperand(1);
8749 CondOpcode = Cond.getOpcode();
8750 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8751 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8752 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8753 Cond.getOperand(0).getValueType() != MVT::i8)) {
8754 SDValue LHS = Cond.getOperand(0);
8755 SDValue RHS = Cond.getOperand(1);
8759 switch (CondOpcode) {
8760 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8761 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8762 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8763 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8764 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8765 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8766 default: llvm_unreachable("unexpected overflowing operator");
8769 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8770 if (CondOpcode == ISD::UMULO)
8771 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8774 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8776 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8778 if (CondOpcode == ISD::UMULO)
8779 Cond = X86Op.getValue(2);
8781 Cond = X86Op.getValue(1);
8783 CC = DAG.getConstant(X86Cond, MVT::i8);
8787 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8788 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8789 if (CondOpc == ISD::OR) {
8790 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8791 // two branches instead of an explicit OR instruction with a
8793 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8794 isX86LogicalCmp(Cmp)) {
8795 CC = Cond.getOperand(0).getOperand(0);
8796 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8797 Chain, Dest, CC, Cmp);
8798 CC = Cond.getOperand(1).getOperand(0);
8802 } else { // ISD::AND
8803 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8804 // two branches instead of an explicit AND instruction with a
8805 // separate test. However, we only do this if this block doesn't
8806 // have a fall-through edge, because this requires an explicit
8807 // jmp when the condition is false.
8808 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8809 isX86LogicalCmp(Cmp) &&
8810 Op.getNode()->hasOneUse()) {
8811 X86::CondCode CCode =
8812 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8813 CCode = X86::GetOppositeBranchCondition(CCode);
8814 CC = DAG.getConstant(CCode, MVT::i8);
8815 SDNode *User = *Op.getNode()->use_begin();
8816 // Look for an unconditional branch following this conditional branch.
8817 // We need this because we need to reverse the successors in order
8818 // to implement FCMP_OEQ.
8819 if (User->getOpcode() == ISD::BR) {
8820 SDValue FalseBB = User->getOperand(1);
8822 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8823 assert(NewBR == User);
8827 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8828 Chain, Dest, CC, Cmp);
8829 X86::CondCode CCode =
8830 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8831 CCode = X86::GetOppositeBranchCondition(CCode);
8832 CC = DAG.getConstant(CCode, MVT::i8);
8838 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8839 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8840 // It should be transformed during dag combiner except when the condition
8841 // is set by a arithmetics with overflow node.
8842 X86::CondCode CCode =
8843 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8844 CCode = X86::GetOppositeBranchCondition(CCode);
8845 CC = DAG.getConstant(CCode, MVT::i8);
8846 Cond = Cond.getOperand(0).getOperand(1);
8848 } else if (Cond.getOpcode() == ISD::SETCC &&
8849 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8850 // For FCMP_OEQ, we can emit
8851 // two branches instead of an explicit AND instruction with a
8852 // separate test. However, we only do this if this block doesn't
8853 // have a fall-through edge, because this requires an explicit
8854 // jmp when the condition is false.
8855 if (Op.getNode()->hasOneUse()) {
8856 SDNode *User = *Op.getNode()->use_begin();
8857 // Look for an unconditional branch following this conditional branch.
8858 // We need this because we need to reverse the successors in order
8859 // to implement FCMP_OEQ.
8860 if (User->getOpcode() == ISD::BR) {
8861 SDValue FalseBB = User->getOperand(1);
8863 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8864 assert(NewBR == User);
8868 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8869 Cond.getOperand(0), Cond.getOperand(1));
8870 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8871 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8872 Chain, Dest, CC, Cmp);
8873 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8878 } else if (Cond.getOpcode() == ISD::SETCC &&
8879 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8880 // For FCMP_UNE, we can emit
8881 // two branches instead of an explicit AND instruction with a
8882 // separate test. However, we only do this if this block doesn't
8883 // have a fall-through edge, because this requires an explicit
8884 // jmp when the condition is false.
8885 if (Op.getNode()->hasOneUse()) {
8886 SDNode *User = *Op.getNode()->use_begin();
8887 // Look for an unconditional branch following this conditional branch.
8888 // We need this because we need to reverse the successors in order
8889 // to implement FCMP_UNE.
8890 if (User->getOpcode() == ISD::BR) {
8891 SDValue FalseBB = User->getOperand(1);
8893 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8894 assert(NewBR == User);
8897 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8898 Cond.getOperand(0), Cond.getOperand(1));
8899 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8900 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8901 Chain, Dest, CC, Cmp);
8902 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8912 // Look pass the truncate.
8913 if (Cond.getOpcode() == ISD::TRUNCATE)
8914 Cond = Cond.getOperand(0);
8916 // We know the result of AND is compared against zero. Try to match
8918 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8919 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8920 if (NewSetCC.getNode()) {
8921 CC = NewSetCC.getOperand(0);
8922 Cond = NewSetCC.getOperand(1);
8929 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8930 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8932 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8933 Chain, Dest, CC, Cond);
8937 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8938 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8939 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8940 // that the guard pages used by the OS virtual memory manager are allocated in
8941 // correct sequence.
8943 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8944 SelectionDAG &DAG) const {
8945 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8946 getTargetMachine().Options.EnableSegmentedStacks) &&
8947 "This should be used only on Windows targets or when segmented stacks "
8949 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8950 DebugLoc dl = Op.getDebugLoc();
8953 SDValue Chain = Op.getOperand(0);
8954 SDValue Size = Op.getOperand(1);
8955 // FIXME: Ensure alignment here
8957 bool Is64Bit = Subtarget->is64Bit();
8958 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8960 if (getTargetMachine().Options.EnableSegmentedStacks) {
8961 MachineFunction &MF = DAG.getMachineFunction();
8962 MachineRegisterInfo &MRI = MF.getRegInfo();
8965 // The 64 bit implementation of segmented stacks needs to clobber both r10
8966 // r11. This makes it impossible to use it along with nested parameters.
8967 const Function *F = MF.getFunction();
8969 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8971 if (I->hasNestAttr())
8972 report_fatal_error("Cannot use segmented stacks with functions that "
8973 "have nested arguments.");
8976 const TargetRegisterClass *AddrRegClass =
8977 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
8978 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
8979 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
8980 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
8981 DAG.getRegister(Vreg, SPTy));
8982 SDValue Ops1[2] = { Value, Chain };
8983 return DAG.getMergeValues(Ops1, 2, dl);
8986 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8988 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8989 Flag = Chain.getValue(1);
8990 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8992 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8993 Flag = Chain.getValue(1);
8995 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8997 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8998 return DAG.getMergeValues(Ops1, 2, dl);
9002 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9003 MachineFunction &MF = DAG.getMachineFunction();
9004 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9006 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9007 DebugLoc DL = Op.getDebugLoc();
9009 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9010 // vastart just stores the address of the VarArgsFrameIndex slot into the
9011 // memory location argument.
9012 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9014 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9015 MachinePointerInfo(SV), false, false, 0);
9019 // gp_offset (0 - 6 * 8)
9020 // fp_offset (48 - 48 + 8 * 16)
9021 // overflow_arg_area (point to parameters coming in memory).
9023 SmallVector<SDValue, 8> MemOps;
9024 SDValue FIN = Op.getOperand(1);
9026 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9027 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9029 FIN, MachinePointerInfo(SV), false, false, 0);
9030 MemOps.push_back(Store);
9033 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9034 FIN, DAG.getIntPtrConstant(4));
9035 Store = DAG.getStore(Op.getOperand(0), DL,
9036 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9038 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9039 MemOps.push_back(Store);
9041 // Store ptr to overflow_arg_area
9042 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9043 FIN, DAG.getIntPtrConstant(4));
9044 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9046 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9047 MachinePointerInfo(SV, 8),
9049 MemOps.push_back(Store);
9051 // Store ptr to reg_save_area.
9052 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9053 FIN, DAG.getIntPtrConstant(8));
9054 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9056 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9057 MachinePointerInfo(SV, 16), false, false, 0);
9058 MemOps.push_back(Store);
9059 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9060 &MemOps[0], MemOps.size());
9063 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9064 assert(Subtarget->is64Bit() &&
9065 "LowerVAARG only handles 64-bit va_arg!");
9066 assert((Subtarget->isTargetLinux() ||
9067 Subtarget->isTargetDarwin()) &&
9068 "Unhandled target in LowerVAARG");
9069 assert(Op.getNode()->getNumOperands() == 4);
9070 SDValue Chain = Op.getOperand(0);
9071 SDValue SrcPtr = Op.getOperand(1);
9072 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9073 unsigned Align = Op.getConstantOperandVal(3);
9074 DebugLoc dl = Op.getDebugLoc();
9076 EVT ArgVT = Op.getNode()->getValueType(0);
9077 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9078 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9081 // Decide which area this value should be read from.
9082 // TODO: Implement the AMD64 ABI in its entirety. This simple
9083 // selection mechanism works only for the basic types.
9084 if (ArgVT == MVT::f80) {
9085 llvm_unreachable("va_arg for f80 not yet implemented");
9086 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9087 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9088 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9089 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9091 llvm_unreachable("Unhandled argument type in LowerVAARG");
9095 // Sanity Check: Make sure using fp_offset makes sense.
9096 assert(!getTargetMachine().Options.UseSoftFloat &&
9097 !(DAG.getMachineFunction()
9098 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9099 Subtarget->hasSSE1());
9102 // Insert VAARG_64 node into the DAG
9103 // VAARG_64 returns two values: Variable Argument Address, Chain
9104 SmallVector<SDValue, 11> InstOps;
9105 InstOps.push_back(Chain);
9106 InstOps.push_back(SrcPtr);
9107 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9108 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9109 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9110 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9111 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9112 VTs, &InstOps[0], InstOps.size(),
9114 MachinePointerInfo(SV),
9119 Chain = VAARG.getValue(1);
9121 // Load the next argument and return it
9122 return DAG.getLoad(ArgVT, dl,
9125 MachinePointerInfo(),
9126 false, false, false, 0);
9129 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9130 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9131 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9132 SDValue Chain = Op.getOperand(0);
9133 SDValue DstPtr = Op.getOperand(1);
9134 SDValue SrcPtr = Op.getOperand(2);
9135 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9136 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9137 DebugLoc DL = Op.getDebugLoc();
9139 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9140 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9142 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9145 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9146 // may or may not be a constant. Takes immediate version of shift as input.
9147 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9148 SDValue SrcOp, SDValue ShAmt,
9149 SelectionDAG &DAG) {
9150 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9152 if (isa<ConstantSDNode>(ShAmt)) {
9154 default: llvm_unreachable("Unknown target vector shift node");
9158 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9162 // Change opcode to non-immediate version
9164 default: llvm_unreachable("Unknown target vector shift node");
9165 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9166 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9167 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9170 // Need to build a vector containing shift amount
9171 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9174 ShOps[1] = DAG.getConstant(0, MVT::i32);
9175 ShOps[2] = DAG.getUNDEF(MVT::i32);
9176 ShOps[3] = DAG.getUNDEF(MVT::i32);
9177 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9178 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9179 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9183 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9184 DebugLoc dl = Op.getDebugLoc();
9185 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9187 default: return SDValue(); // Don't custom lower most intrinsics.
9188 // Comparison intrinsics.
9189 case Intrinsic::x86_sse_comieq_ss:
9190 case Intrinsic::x86_sse_comilt_ss:
9191 case Intrinsic::x86_sse_comile_ss:
9192 case Intrinsic::x86_sse_comigt_ss:
9193 case Intrinsic::x86_sse_comige_ss:
9194 case Intrinsic::x86_sse_comineq_ss:
9195 case Intrinsic::x86_sse_ucomieq_ss:
9196 case Intrinsic::x86_sse_ucomilt_ss:
9197 case Intrinsic::x86_sse_ucomile_ss:
9198 case Intrinsic::x86_sse_ucomigt_ss:
9199 case Intrinsic::x86_sse_ucomige_ss:
9200 case Intrinsic::x86_sse_ucomineq_ss:
9201 case Intrinsic::x86_sse2_comieq_sd:
9202 case Intrinsic::x86_sse2_comilt_sd:
9203 case Intrinsic::x86_sse2_comile_sd:
9204 case Intrinsic::x86_sse2_comigt_sd:
9205 case Intrinsic::x86_sse2_comige_sd:
9206 case Intrinsic::x86_sse2_comineq_sd:
9207 case Intrinsic::x86_sse2_ucomieq_sd:
9208 case Intrinsic::x86_sse2_ucomilt_sd:
9209 case Intrinsic::x86_sse2_ucomile_sd:
9210 case Intrinsic::x86_sse2_ucomigt_sd:
9211 case Intrinsic::x86_sse2_ucomige_sd:
9212 case Intrinsic::x86_sse2_ucomineq_sd: {
9214 ISD::CondCode CC = ISD::SETCC_INVALID;
9217 case Intrinsic::x86_sse_comieq_ss:
9218 case Intrinsic::x86_sse2_comieq_sd:
9222 case Intrinsic::x86_sse_comilt_ss:
9223 case Intrinsic::x86_sse2_comilt_sd:
9227 case Intrinsic::x86_sse_comile_ss:
9228 case Intrinsic::x86_sse2_comile_sd:
9232 case Intrinsic::x86_sse_comigt_ss:
9233 case Intrinsic::x86_sse2_comigt_sd:
9237 case Intrinsic::x86_sse_comige_ss:
9238 case Intrinsic::x86_sse2_comige_sd:
9242 case Intrinsic::x86_sse_comineq_ss:
9243 case Intrinsic::x86_sse2_comineq_sd:
9247 case Intrinsic::x86_sse_ucomieq_ss:
9248 case Intrinsic::x86_sse2_ucomieq_sd:
9249 Opc = X86ISD::UCOMI;
9252 case Intrinsic::x86_sse_ucomilt_ss:
9253 case Intrinsic::x86_sse2_ucomilt_sd:
9254 Opc = X86ISD::UCOMI;
9257 case Intrinsic::x86_sse_ucomile_ss:
9258 case Intrinsic::x86_sse2_ucomile_sd:
9259 Opc = X86ISD::UCOMI;
9262 case Intrinsic::x86_sse_ucomigt_ss:
9263 case Intrinsic::x86_sse2_ucomigt_sd:
9264 Opc = X86ISD::UCOMI;
9267 case Intrinsic::x86_sse_ucomige_ss:
9268 case Intrinsic::x86_sse2_ucomige_sd:
9269 Opc = X86ISD::UCOMI;
9272 case Intrinsic::x86_sse_ucomineq_ss:
9273 case Intrinsic::x86_sse2_ucomineq_sd:
9274 Opc = X86ISD::UCOMI;
9279 SDValue LHS = Op.getOperand(1);
9280 SDValue RHS = Op.getOperand(2);
9281 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9282 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9283 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9284 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9285 DAG.getConstant(X86CC, MVT::i8), Cond);
9286 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9288 // Arithmetic intrinsics.
9289 case Intrinsic::x86_sse3_hadd_ps:
9290 case Intrinsic::x86_sse3_hadd_pd:
9291 case Intrinsic::x86_avx_hadd_ps_256:
9292 case Intrinsic::x86_avx_hadd_pd_256:
9293 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9294 Op.getOperand(1), Op.getOperand(2));
9295 case Intrinsic::x86_sse3_hsub_ps:
9296 case Intrinsic::x86_sse3_hsub_pd:
9297 case Intrinsic::x86_avx_hsub_ps_256:
9298 case Intrinsic::x86_avx_hsub_pd_256:
9299 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9300 Op.getOperand(1), Op.getOperand(2));
9301 case Intrinsic::x86_ssse3_phadd_w_128:
9302 case Intrinsic::x86_ssse3_phadd_d_128:
9303 case Intrinsic::x86_avx2_phadd_w:
9304 case Intrinsic::x86_avx2_phadd_d:
9305 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9306 Op.getOperand(1), Op.getOperand(2));
9307 case Intrinsic::x86_ssse3_phsub_w_128:
9308 case Intrinsic::x86_ssse3_phsub_d_128:
9309 case Intrinsic::x86_avx2_phsub_w:
9310 case Intrinsic::x86_avx2_phsub_d:
9311 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9312 Op.getOperand(1), Op.getOperand(2));
9313 case Intrinsic::x86_avx2_psllv_d:
9314 case Intrinsic::x86_avx2_psllv_q:
9315 case Intrinsic::x86_avx2_psllv_d_256:
9316 case Intrinsic::x86_avx2_psllv_q_256:
9317 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9318 Op.getOperand(1), Op.getOperand(2));
9319 case Intrinsic::x86_avx2_psrlv_d:
9320 case Intrinsic::x86_avx2_psrlv_q:
9321 case Intrinsic::x86_avx2_psrlv_d_256:
9322 case Intrinsic::x86_avx2_psrlv_q_256:
9323 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9324 Op.getOperand(1), Op.getOperand(2));
9325 case Intrinsic::x86_avx2_psrav_d:
9326 case Intrinsic::x86_avx2_psrav_d_256:
9327 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9328 Op.getOperand(1), Op.getOperand(2));
9329 case Intrinsic::x86_sse2_pcmpeq_b:
9330 case Intrinsic::x86_sse2_pcmpeq_w:
9331 case Intrinsic::x86_sse2_pcmpeq_d:
9332 case Intrinsic::x86_sse41_pcmpeqq:
9333 case Intrinsic::x86_avx2_pcmpeq_b:
9334 case Intrinsic::x86_avx2_pcmpeq_w:
9335 case Intrinsic::x86_avx2_pcmpeq_d:
9336 case Intrinsic::x86_avx2_pcmpeq_q:
9337 return DAG.getNode(X86ISD::PCMPEQ, dl, Op.getValueType(),
9338 Op.getOperand(1), Op.getOperand(2));
9339 case Intrinsic::x86_sse2_pcmpgt_b:
9340 case Intrinsic::x86_sse2_pcmpgt_w:
9341 case Intrinsic::x86_sse2_pcmpgt_d:
9342 case Intrinsic::x86_sse42_pcmpgtq:
9343 case Intrinsic::x86_avx2_pcmpgt_b:
9344 case Intrinsic::x86_avx2_pcmpgt_w:
9345 case Intrinsic::x86_avx2_pcmpgt_d:
9346 case Intrinsic::x86_avx2_pcmpgt_q:
9347 return DAG.getNode(X86ISD::PCMPGT, dl, Op.getValueType(),
9348 Op.getOperand(1), Op.getOperand(2));
9349 case Intrinsic::x86_ssse3_pshuf_b_128:
9350 case Intrinsic::x86_avx2_pshuf_b:
9351 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9352 Op.getOperand(1), Op.getOperand(2));
9353 case Intrinsic::x86_ssse3_psign_b_128:
9354 case Intrinsic::x86_ssse3_psign_w_128:
9355 case Intrinsic::x86_ssse3_psign_d_128:
9356 case Intrinsic::x86_avx2_psign_b:
9357 case Intrinsic::x86_avx2_psign_w:
9358 case Intrinsic::x86_avx2_psign_d:
9359 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9360 Op.getOperand(1), Op.getOperand(2));
9361 case Intrinsic::x86_sse41_insertps:
9362 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9363 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9364 case Intrinsic::x86_avx_vperm2f128_ps_256:
9365 case Intrinsic::x86_avx_vperm2f128_pd_256:
9366 case Intrinsic::x86_avx_vperm2f128_si_256:
9367 case Intrinsic::x86_avx2_vperm2i128:
9368 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9369 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9371 // ptest and testp intrinsics. The intrinsic these come from are designed to
9372 // return an integer value, not just an instruction so lower it to the ptest
9373 // or testp pattern and a setcc for the result.
9374 case Intrinsic::x86_sse41_ptestz:
9375 case Intrinsic::x86_sse41_ptestc:
9376 case Intrinsic::x86_sse41_ptestnzc:
9377 case Intrinsic::x86_avx_ptestz_256:
9378 case Intrinsic::x86_avx_ptestc_256:
9379 case Intrinsic::x86_avx_ptestnzc_256:
9380 case Intrinsic::x86_avx_vtestz_ps:
9381 case Intrinsic::x86_avx_vtestc_ps:
9382 case Intrinsic::x86_avx_vtestnzc_ps:
9383 case Intrinsic::x86_avx_vtestz_pd:
9384 case Intrinsic::x86_avx_vtestc_pd:
9385 case Intrinsic::x86_avx_vtestnzc_pd:
9386 case Intrinsic::x86_avx_vtestz_ps_256:
9387 case Intrinsic::x86_avx_vtestc_ps_256:
9388 case Intrinsic::x86_avx_vtestnzc_ps_256:
9389 case Intrinsic::x86_avx_vtestz_pd_256:
9390 case Intrinsic::x86_avx_vtestc_pd_256:
9391 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9392 bool IsTestPacked = false;
9395 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9396 case Intrinsic::x86_avx_vtestz_ps:
9397 case Intrinsic::x86_avx_vtestz_pd:
9398 case Intrinsic::x86_avx_vtestz_ps_256:
9399 case Intrinsic::x86_avx_vtestz_pd_256:
9400 IsTestPacked = true; // Fallthrough
9401 case Intrinsic::x86_sse41_ptestz:
9402 case Intrinsic::x86_avx_ptestz_256:
9404 X86CC = X86::COND_E;
9406 case Intrinsic::x86_avx_vtestc_ps:
9407 case Intrinsic::x86_avx_vtestc_pd:
9408 case Intrinsic::x86_avx_vtestc_ps_256:
9409 case Intrinsic::x86_avx_vtestc_pd_256:
9410 IsTestPacked = true; // Fallthrough
9411 case Intrinsic::x86_sse41_ptestc:
9412 case Intrinsic::x86_avx_ptestc_256:
9414 X86CC = X86::COND_B;
9416 case Intrinsic::x86_avx_vtestnzc_ps:
9417 case Intrinsic::x86_avx_vtestnzc_pd:
9418 case Intrinsic::x86_avx_vtestnzc_ps_256:
9419 case Intrinsic::x86_avx_vtestnzc_pd_256:
9420 IsTestPacked = true; // Fallthrough
9421 case Intrinsic::x86_sse41_ptestnzc:
9422 case Intrinsic::x86_avx_ptestnzc_256:
9424 X86CC = X86::COND_A;
9428 SDValue LHS = Op.getOperand(1);
9429 SDValue RHS = Op.getOperand(2);
9430 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9431 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9432 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9433 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9434 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9437 // SSE/AVX shift intrinsics
9438 case Intrinsic::x86_sse2_psll_w:
9439 case Intrinsic::x86_sse2_psll_d:
9440 case Intrinsic::x86_sse2_psll_q:
9441 case Intrinsic::x86_avx2_psll_w:
9442 case Intrinsic::x86_avx2_psll_d:
9443 case Intrinsic::x86_avx2_psll_q:
9444 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9445 Op.getOperand(1), Op.getOperand(2));
9446 case Intrinsic::x86_sse2_psrl_w:
9447 case Intrinsic::x86_sse2_psrl_d:
9448 case Intrinsic::x86_sse2_psrl_q:
9449 case Intrinsic::x86_avx2_psrl_w:
9450 case Intrinsic::x86_avx2_psrl_d:
9451 case Intrinsic::x86_avx2_psrl_q:
9452 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9453 Op.getOperand(1), Op.getOperand(2));
9454 case Intrinsic::x86_sse2_psra_w:
9455 case Intrinsic::x86_sse2_psra_d:
9456 case Intrinsic::x86_avx2_psra_w:
9457 case Intrinsic::x86_avx2_psra_d:
9458 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9459 Op.getOperand(1), Op.getOperand(2));
9460 case Intrinsic::x86_sse2_pslli_w:
9461 case Intrinsic::x86_sse2_pslli_d:
9462 case Intrinsic::x86_sse2_pslli_q:
9463 case Intrinsic::x86_avx2_pslli_w:
9464 case Intrinsic::x86_avx2_pslli_d:
9465 case Intrinsic::x86_avx2_pslli_q:
9466 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9467 Op.getOperand(1), Op.getOperand(2), DAG);
9468 case Intrinsic::x86_sse2_psrli_w:
9469 case Intrinsic::x86_sse2_psrli_d:
9470 case Intrinsic::x86_sse2_psrli_q:
9471 case Intrinsic::x86_avx2_psrli_w:
9472 case Intrinsic::x86_avx2_psrli_d:
9473 case Intrinsic::x86_avx2_psrli_q:
9474 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9475 Op.getOperand(1), Op.getOperand(2), DAG);
9476 case Intrinsic::x86_sse2_psrai_w:
9477 case Intrinsic::x86_sse2_psrai_d:
9478 case Intrinsic::x86_avx2_psrai_w:
9479 case Intrinsic::x86_avx2_psrai_d:
9480 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9481 Op.getOperand(1), Op.getOperand(2), DAG);
9482 // Fix vector shift instructions where the last operand is a non-immediate
9484 case Intrinsic::x86_mmx_pslli_w:
9485 case Intrinsic::x86_mmx_pslli_d:
9486 case Intrinsic::x86_mmx_pslli_q:
9487 case Intrinsic::x86_mmx_psrli_w:
9488 case Intrinsic::x86_mmx_psrli_d:
9489 case Intrinsic::x86_mmx_psrli_q:
9490 case Intrinsic::x86_mmx_psrai_w:
9491 case Intrinsic::x86_mmx_psrai_d: {
9492 SDValue ShAmt = Op.getOperand(2);
9493 if (isa<ConstantSDNode>(ShAmt))
9496 unsigned NewIntNo = 0;
9498 case Intrinsic::x86_mmx_pslli_w:
9499 NewIntNo = Intrinsic::x86_mmx_psll_w;
9501 case Intrinsic::x86_mmx_pslli_d:
9502 NewIntNo = Intrinsic::x86_mmx_psll_d;
9504 case Intrinsic::x86_mmx_pslli_q:
9505 NewIntNo = Intrinsic::x86_mmx_psll_q;
9507 case Intrinsic::x86_mmx_psrli_w:
9508 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9510 case Intrinsic::x86_mmx_psrli_d:
9511 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9513 case Intrinsic::x86_mmx_psrli_q:
9514 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9516 case Intrinsic::x86_mmx_psrai_w:
9517 NewIntNo = Intrinsic::x86_mmx_psra_w;
9519 case Intrinsic::x86_mmx_psrai_d:
9520 NewIntNo = Intrinsic::x86_mmx_psra_d;
9522 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9525 // The vector shift intrinsics with scalars uses 32b shift amounts but
9526 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9528 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9529 DAG.getConstant(0, MVT::i32));
9530 // FIXME this must be lowered to get rid of the invalid type.
9532 EVT VT = Op.getValueType();
9533 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9534 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9535 DAG.getConstant(NewIntNo, MVT::i32),
9536 Op.getOperand(1), ShAmt);
9541 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9542 SelectionDAG &DAG) const {
9543 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9544 MFI->setReturnAddressIsTaken(true);
9546 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9547 DebugLoc dl = Op.getDebugLoc();
9550 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9552 DAG.getConstant(TD->getPointerSize(),
9553 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9554 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9555 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9557 MachinePointerInfo(), false, false, false, 0);
9560 // Just load the return address.
9561 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9562 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9563 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9566 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9567 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9568 MFI->setFrameAddressIsTaken(true);
9570 EVT VT = Op.getValueType();
9571 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9572 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9573 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9574 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9576 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9577 MachinePointerInfo(),
9578 false, false, false, 0);
9582 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9583 SelectionDAG &DAG) const {
9584 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9587 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9588 MachineFunction &MF = DAG.getMachineFunction();
9589 SDValue Chain = Op.getOperand(0);
9590 SDValue Offset = Op.getOperand(1);
9591 SDValue Handler = Op.getOperand(2);
9592 DebugLoc dl = Op.getDebugLoc();
9594 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9595 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9597 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9599 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9600 DAG.getIntPtrConstant(TD->getPointerSize()));
9601 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9602 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9604 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9605 MF.getRegInfo().addLiveOut(StoreAddrReg);
9607 return DAG.getNode(X86ISD::EH_RETURN, dl,
9609 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9612 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9613 SelectionDAG &DAG) const {
9614 return Op.getOperand(0);
9617 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9618 SelectionDAG &DAG) const {
9619 SDValue Root = Op.getOperand(0);
9620 SDValue Trmp = Op.getOperand(1); // trampoline
9621 SDValue FPtr = Op.getOperand(2); // nested function
9622 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9623 DebugLoc dl = Op.getDebugLoc();
9625 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9627 if (Subtarget->is64Bit()) {
9628 SDValue OutChains[6];
9630 // Large code-model.
9631 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9632 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9634 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9635 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9637 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9639 // Load the pointer to the nested function into R11.
9640 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9641 SDValue Addr = Trmp;
9642 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9643 Addr, MachinePointerInfo(TrmpAddr),
9646 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9647 DAG.getConstant(2, MVT::i64));
9648 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9649 MachinePointerInfo(TrmpAddr, 2),
9652 // Load the 'nest' parameter value into R10.
9653 // R10 is specified in X86CallingConv.td
9654 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9655 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9656 DAG.getConstant(10, MVT::i64));
9657 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9658 Addr, MachinePointerInfo(TrmpAddr, 10),
9661 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9662 DAG.getConstant(12, MVT::i64));
9663 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9664 MachinePointerInfo(TrmpAddr, 12),
9667 // Jump to the nested function.
9668 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9669 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9670 DAG.getConstant(20, MVT::i64));
9671 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9672 Addr, MachinePointerInfo(TrmpAddr, 20),
9675 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9676 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9677 DAG.getConstant(22, MVT::i64));
9678 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9679 MachinePointerInfo(TrmpAddr, 22),
9682 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9684 const Function *Func =
9685 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9686 CallingConv::ID CC = Func->getCallingConv();
9691 llvm_unreachable("Unsupported calling convention");
9692 case CallingConv::C:
9693 case CallingConv::X86_StdCall: {
9694 // Pass 'nest' parameter in ECX.
9695 // Must be kept in sync with X86CallingConv.td
9698 // Check that ECX wasn't needed by an 'inreg' parameter.
9699 FunctionType *FTy = Func->getFunctionType();
9700 const AttrListPtr &Attrs = Func->getAttributes();
9702 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9703 unsigned InRegCount = 0;
9706 for (FunctionType::param_iterator I = FTy->param_begin(),
9707 E = FTy->param_end(); I != E; ++I, ++Idx)
9708 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9709 // FIXME: should only count parameters that are lowered to integers.
9710 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9712 if (InRegCount > 2) {
9713 report_fatal_error("Nest register in use - reduce number of inreg"
9719 case CallingConv::X86_FastCall:
9720 case CallingConv::X86_ThisCall:
9721 case CallingConv::Fast:
9722 // Pass 'nest' parameter in EAX.
9723 // Must be kept in sync with X86CallingConv.td
9728 SDValue OutChains[4];
9731 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9732 DAG.getConstant(10, MVT::i32));
9733 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9735 // This is storing the opcode for MOV32ri.
9736 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9737 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9738 OutChains[0] = DAG.getStore(Root, dl,
9739 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9740 Trmp, MachinePointerInfo(TrmpAddr),
9743 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9744 DAG.getConstant(1, MVT::i32));
9745 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9746 MachinePointerInfo(TrmpAddr, 1),
9749 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9750 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9751 DAG.getConstant(5, MVT::i32));
9752 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9753 MachinePointerInfo(TrmpAddr, 5),
9756 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9757 DAG.getConstant(6, MVT::i32));
9758 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9759 MachinePointerInfo(TrmpAddr, 6),
9762 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9766 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9767 SelectionDAG &DAG) const {
9769 The rounding mode is in bits 11:10 of FPSR, and has the following
9776 FLT_ROUNDS, on the other hand, expects the following:
9783 To perform the conversion, we do:
9784 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9787 MachineFunction &MF = DAG.getMachineFunction();
9788 const TargetMachine &TM = MF.getTarget();
9789 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9790 unsigned StackAlignment = TFI.getStackAlignment();
9791 EVT VT = Op.getValueType();
9792 DebugLoc DL = Op.getDebugLoc();
9794 // Save FP Control Word to stack slot
9795 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9796 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9799 MachineMemOperand *MMO =
9800 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9801 MachineMemOperand::MOStore, 2, 2);
9803 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9804 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9805 DAG.getVTList(MVT::Other),
9806 Ops, 2, MVT::i16, MMO);
9808 // Load FP Control Word from stack slot
9809 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9810 MachinePointerInfo(), false, false, false, 0);
9812 // Transform as necessary
9814 DAG.getNode(ISD::SRL, DL, MVT::i16,
9815 DAG.getNode(ISD::AND, DL, MVT::i16,
9816 CWD, DAG.getConstant(0x800, MVT::i16)),
9817 DAG.getConstant(11, MVT::i8));
9819 DAG.getNode(ISD::SRL, DL, MVT::i16,
9820 DAG.getNode(ISD::AND, DL, MVT::i16,
9821 CWD, DAG.getConstant(0x400, MVT::i16)),
9822 DAG.getConstant(9, MVT::i8));
9825 DAG.getNode(ISD::AND, DL, MVT::i16,
9826 DAG.getNode(ISD::ADD, DL, MVT::i16,
9827 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9828 DAG.getConstant(1, MVT::i16)),
9829 DAG.getConstant(3, MVT::i16));
9832 return DAG.getNode((VT.getSizeInBits() < 16 ?
9833 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9836 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9837 EVT VT = Op.getValueType();
9839 unsigned NumBits = VT.getSizeInBits();
9840 DebugLoc dl = Op.getDebugLoc();
9842 Op = Op.getOperand(0);
9843 if (VT == MVT::i8) {
9844 // Zero extend to i32 since there is not an i8 bsr.
9846 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9849 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9850 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9851 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9853 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9856 DAG.getConstant(NumBits+NumBits-1, OpVT),
9857 DAG.getConstant(X86::COND_E, MVT::i8),
9860 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9862 // Finally xor with NumBits-1.
9863 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9866 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9870 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
9871 SelectionDAG &DAG) const {
9872 EVT VT = Op.getValueType();
9874 unsigned NumBits = VT.getSizeInBits();
9875 DebugLoc dl = Op.getDebugLoc();
9877 Op = Op.getOperand(0);
9878 if (VT == MVT::i8) {
9879 // Zero extend to i32 since there is not an i8 bsr.
9881 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9884 // Issue a bsr (scan bits in reverse).
9885 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9886 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9888 // And xor with NumBits-1.
9889 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9892 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9896 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9897 EVT VT = Op.getValueType();
9898 unsigned NumBits = VT.getSizeInBits();
9899 DebugLoc dl = Op.getDebugLoc();
9900 Op = Op.getOperand(0);
9902 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9903 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
9904 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9906 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9909 DAG.getConstant(NumBits, VT),
9910 DAG.getConstant(X86::COND_E, MVT::i8),
9913 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
9916 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
9917 // ones, and then concatenate the result back.
9918 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
9919 EVT VT = Op.getValueType();
9921 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
9922 "Unsupported value type for operation");
9924 int NumElems = VT.getVectorNumElements();
9925 DebugLoc dl = Op.getDebugLoc();
9926 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
9927 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
9929 // Extract the LHS vectors
9930 SDValue LHS = Op.getOperand(0);
9931 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
9932 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
9934 // Extract the RHS vectors
9935 SDValue RHS = Op.getOperand(1);
9936 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
9937 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
9939 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9940 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9942 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9943 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
9944 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
9947 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
9948 assert(Op.getValueType().getSizeInBits() == 256 &&
9949 Op.getValueType().isInteger() &&
9950 "Only handle AVX 256-bit vector integer operation");
9951 return Lower256IntArith(Op, DAG);
9954 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
9955 assert(Op.getValueType().getSizeInBits() == 256 &&
9956 Op.getValueType().isInteger() &&
9957 "Only handle AVX 256-bit vector integer operation");
9958 return Lower256IntArith(Op, DAG);
9961 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
9962 EVT VT = Op.getValueType();
9964 // Decompose 256-bit ops into smaller 128-bit ops.
9965 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
9966 return Lower256IntArith(Op, DAG);
9968 DebugLoc dl = Op.getDebugLoc();
9970 SDValue A = Op.getOperand(0);
9971 SDValue B = Op.getOperand(1);
9973 if (VT == MVT::v4i64) {
9974 assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2");
9976 // ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32);
9977 // ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32);
9978 // ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b );
9979 // ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi );
9980 // ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b );
9982 // AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 );
9983 // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 );
9984 // return AloBlo + AloBhi + AhiBlo;
9986 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A,
9987 DAG.getConstant(32, MVT::i32));
9988 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B,
9989 DAG.getConstant(32, MVT::i32));
9990 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9991 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9993 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9994 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9996 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9997 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9999 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi,
10000 DAG.getConstant(32, MVT::i32));
10001 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo,
10002 DAG.getConstant(32, MVT::i32));
10003 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10004 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10008 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
10010 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
10011 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
10012 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
10013 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
10014 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
10016 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
10017 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
10018 // return AloBlo + AloBhi + AhiBlo;
10020 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A,
10021 DAG.getConstant(32, MVT::i32));
10022 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B,
10023 DAG.getConstant(32, MVT::i32));
10024 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10025 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
10027 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10028 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
10030 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10031 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
10033 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi,
10034 DAG.getConstant(32, MVT::i32));
10035 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo,
10036 DAG.getConstant(32, MVT::i32));
10037 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10038 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10042 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10044 EVT VT = Op.getValueType();
10045 DebugLoc dl = Op.getDebugLoc();
10046 SDValue R = Op.getOperand(0);
10047 SDValue Amt = Op.getOperand(1);
10048 LLVMContext *Context = DAG.getContext();
10050 if (!Subtarget->hasSSE2())
10053 // Optimize shl/srl/sra with constant shift amount.
10054 if (isSplatVector(Amt.getNode())) {
10055 SDValue SclrAmt = Amt->getOperand(0);
10056 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10057 uint64_t ShiftAmt = C->getZExtValue();
10059 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10060 (Subtarget->hasAVX2() &&
10061 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10062 if (Op.getOpcode() == ISD::SHL)
10063 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10064 DAG.getConstant(ShiftAmt, MVT::i32));
10065 if (Op.getOpcode() == ISD::SRL)
10066 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10067 DAG.getConstant(ShiftAmt, MVT::i32));
10068 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10069 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10070 DAG.getConstant(ShiftAmt, MVT::i32));
10073 if (VT == MVT::v16i8) {
10074 if (Op.getOpcode() == ISD::SHL) {
10075 // Make a large shift.
10076 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10077 DAG.getConstant(ShiftAmt, MVT::i32));
10078 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10079 // Zero out the rightmost bits.
10080 SmallVector<SDValue, 16> V(16,
10081 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10083 return DAG.getNode(ISD::AND, dl, VT, SHL,
10084 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10086 if (Op.getOpcode() == ISD::SRL) {
10087 // Make a large shift.
10088 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10089 DAG.getConstant(ShiftAmt, MVT::i32));
10090 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10091 // Zero out the leftmost bits.
10092 SmallVector<SDValue, 16> V(16,
10093 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10095 return DAG.getNode(ISD::AND, dl, VT, SRL,
10096 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10098 if (Op.getOpcode() == ISD::SRA) {
10099 if (ShiftAmt == 7) {
10100 // R s>> 7 === R s< 0
10101 SDValue Zeros = getZeroVector(VT, /* HasSSE2 */true,
10102 /* HasAVX2 */false, DAG, dl);
10103 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10106 // R s>> a === ((R u>> a) ^ m) - m
10107 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10108 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10110 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10111 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10112 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10117 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10118 if (Op.getOpcode() == ISD::SHL) {
10119 // Make a large shift.
10120 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10121 DAG.getConstant(ShiftAmt, MVT::i32));
10122 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10123 // Zero out the rightmost bits.
10124 SmallVector<SDValue, 32> V(32,
10125 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10127 return DAG.getNode(ISD::AND, dl, VT, SHL,
10128 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10130 if (Op.getOpcode() == ISD::SRL) {
10131 // Make a large shift.
10132 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10133 DAG.getConstant(ShiftAmt, MVT::i32));
10134 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10135 // Zero out the leftmost bits.
10136 SmallVector<SDValue, 32> V(32,
10137 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10139 return DAG.getNode(ISD::AND, dl, VT, SRL,
10140 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10142 if (Op.getOpcode() == ISD::SRA) {
10143 if (ShiftAmt == 7) {
10144 // R s>> 7 === R s< 0
10145 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */,
10146 true /* HasAVX2 */, DAG, dl);
10147 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10150 // R s>> a === ((R u>> a) ^ m) - m
10151 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10152 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10154 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10155 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10156 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10163 // Lower SHL with variable shift amount.
10164 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10165 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10166 DAG.getConstant(23, MVT::i32));
10168 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
10169 Constant *C = ConstantVector::getSplat(4, CI);
10170 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10171 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10172 MachinePointerInfo::getConstantPool(),
10173 false, false, false, 16);
10175 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10176 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10177 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10178 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10180 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10181 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10184 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10185 DAG.getConstant(5, MVT::i32));
10186 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10188 // Turn 'a' into a mask suitable for VSELECT
10189 SDValue VSelM = DAG.getConstant(0x80, VT);
10190 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10191 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10193 SDValue CM1 = DAG.getConstant(0x0f, VT);
10194 SDValue CM2 = DAG.getConstant(0x3f, VT);
10196 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10197 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10198 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10199 DAG.getConstant(4, MVT::i32), DAG);
10200 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10201 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10204 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10205 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10206 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10208 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10209 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10210 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10211 DAG.getConstant(2, MVT::i32), DAG);
10212 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10213 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10216 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10217 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10218 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10220 // return VSELECT(r, r+r, a);
10221 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10222 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10226 // Decompose 256-bit shifts into smaller 128-bit shifts.
10227 if (VT.getSizeInBits() == 256) {
10228 unsigned NumElems = VT.getVectorNumElements();
10229 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10230 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10232 // Extract the two vectors
10233 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
10234 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
10237 // Recreate the shift amount vectors
10238 SDValue Amt1, Amt2;
10239 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10240 // Constant shift amount
10241 SmallVector<SDValue, 4> Amt1Csts;
10242 SmallVector<SDValue, 4> Amt2Csts;
10243 for (unsigned i = 0; i != NumElems/2; ++i)
10244 Amt1Csts.push_back(Amt->getOperand(i));
10245 for (unsigned i = NumElems/2; i != NumElems; ++i)
10246 Amt2Csts.push_back(Amt->getOperand(i));
10248 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10249 &Amt1Csts[0], NumElems/2);
10250 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10251 &Amt2Csts[0], NumElems/2);
10253 // Variable shift amount
10254 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10255 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
10259 // Issue new vector shifts for the smaller types
10260 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10261 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10263 // Concatenate the result back
10264 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10270 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10271 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10272 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10273 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10274 // has only one use.
10275 SDNode *N = Op.getNode();
10276 SDValue LHS = N->getOperand(0);
10277 SDValue RHS = N->getOperand(1);
10278 unsigned BaseOp = 0;
10280 DebugLoc DL = Op.getDebugLoc();
10281 switch (Op.getOpcode()) {
10282 default: llvm_unreachable("Unknown ovf instruction!");
10284 // A subtract of one will be selected as a INC. Note that INC doesn't
10285 // set CF, so we can't do this for UADDO.
10286 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10288 BaseOp = X86ISD::INC;
10289 Cond = X86::COND_O;
10292 BaseOp = X86ISD::ADD;
10293 Cond = X86::COND_O;
10296 BaseOp = X86ISD::ADD;
10297 Cond = X86::COND_B;
10300 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10301 // set CF, so we can't do this for USUBO.
10302 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10304 BaseOp = X86ISD::DEC;
10305 Cond = X86::COND_O;
10308 BaseOp = X86ISD::SUB;
10309 Cond = X86::COND_O;
10312 BaseOp = X86ISD::SUB;
10313 Cond = X86::COND_B;
10316 BaseOp = X86ISD::SMUL;
10317 Cond = X86::COND_O;
10319 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10320 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10322 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10325 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10326 DAG.getConstant(X86::COND_O, MVT::i32),
10327 SDValue(Sum.getNode(), 2));
10329 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10333 // Also sets EFLAGS.
10334 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10335 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10338 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10339 DAG.getConstant(Cond, MVT::i32),
10340 SDValue(Sum.getNode(), 1));
10342 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10345 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10346 SelectionDAG &DAG) const {
10347 DebugLoc dl = Op.getDebugLoc();
10348 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10349 EVT VT = Op.getValueType();
10351 if (!Subtarget->hasSSE2() || !VT.isVector())
10354 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10355 ExtraVT.getScalarType().getSizeInBits();
10356 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10358 switch (VT.getSimpleVT().SimpleTy) {
10359 default: return SDValue();
10362 if (!Subtarget->hasAVX())
10364 if (!Subtarget->hasAVX2()) {
10365 // needs to be split
10366 int NumElems = VT.getVectorNumElements();
10367 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10368 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10370 // Extract the LHS vectors
10371 SDValue LHS = Op.getOperand(0);
10372 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10373 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10375 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10376 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10378 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10379 int ExtraNumElems = ExtraVT.getVectorNumElements();
10380 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10382 SDValue Extra = DAG.getValueType(ExtraVT);
10384 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10385 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10387 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10392 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10393 Op.getOperand(0), ShAmt, DAG);
10394 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10400 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10401 DebugLoc dl = Op.getDebugLoc();
10403 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10404 // There isn't any reason to disable it if the target processor supports it.
10405 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10406 SDValue Chain = Op.getOperand(0);
10407 SDValue Zero = DAG.getConstant(0, MVT::i32);
10409 DAG.getRegister(X86::ESP, MVT::i32), // Base
10410 DAG.getTargetConstant(1, MVT::i8), // Scale
10411 DAG.getRegister(0, MVT::i32), // Index
10412 DAG.getTargetConstant(0, MVT::i32), // Disp
10413 DAG.getRegister(0, MVT::i32), // Segment.
10418 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10419 array_lengthof(Ops));
10420 return SDValue(Res, 0);
10423 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10425 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10427 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10428 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10429 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10430 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10432 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10433 if (!Op1 && !Op2 && !Op3 && Op4)
10434 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10436 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10437 if (Op1 && !Op2 && !Op3 && !Op4)
10438 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10440 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10442 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10445 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10446 SelectionDAG &DAG) const {
10447 DebugLoc dl = Op.getDebugLoc();
10448 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10449 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10450 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10451 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10453 // The only fence that needs an instruction is a sequentially-consistent
10454 // cross-thread fence.
10455 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10456 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10457 // no-sse2). There isn't any reason to disable it if the target processor
10459 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10460 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10462 SDValue Chain = Op.getOperand(0);
10463 SDValue Zero = DAG.getConstant(0, MVT::i32);
10465 DAG.getRegister(X86::ESP, MVT::i32), // Base
10466 DAG.getTargetConstant(1, MVT::i8), // Scale
10467 DAG.getRegister(0, MVT::i32), // Index
10468 DAG.getTargetConstant(0, MVT::i32), // Disp
10469 DAG.getRegister(0, MVT::i32), // Segment.
10474 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10475 array_lengthof(Ops));
10476 return SDValue(Res, 0);
10479 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10480 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10484 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10485 EVT T = Op.getValueType();
10486 DebugLoc DL = Op.getDebugLoc();
10489 switch(T.getSimpleVT().SimpleTy) {
10491 assert(false && "Invalid value type!");
10492 case MVT::i8: Reg = X86::AL; size = 1; break;
10493 case MVT::i16: Reg = X86::AX; size = 2; break;
10494 case MVT::i32: Reg = X86::EAX; size = 4; break;
10496 assert(Subtarget->is64Bit() && "Node not type legal!");
10497 Reg = X86::RAX; size = 8;
10500 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10501 Op.getOperand(2), SDValue());
10502 SDValue Ops[] = { cpIn.getValue(0),
10505 DAG.getTargetConstant(size, MVT::i8),
10506 cpIn.getValue(1) };
10507 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10508 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10509 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10512 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10516 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10517 SelectionDAG &DAG) const {
10518 assert(Subtarget->is64Bit() && "Result not type legalized?");
10519 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10520 SDValue TheChain = Op.getOperand(0);
10521 DebugLoc dl = Op.getDebugLoc();
10522 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10523 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10524 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10526 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10527 DAG.getConstant(32, MVT::i8));
10529 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10532 return DAG.getMergeValues(Ops, 2, dl);
10535 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10536 SelectionDAG &DAG) const {
10537 EVT SrcVT = Op.getOperand(0).getValueType();
10538 EVT DstVT = Op.getValueType();
10539 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10540 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10541 assert((DstVT == MVT::i64 ||
10542 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10543 "Unexpected custom BITCAST");
10544 // i64 <=> MMX conversions are Legal.
10545 if (SrcVT==MVT::i64 && DstVT.isVector())
10547 if (DstVT==MVT::i64 && SrcVT.isVector())
10549 // MMX <=> MMX conversions are Legal.
10550 if (SrcVT.isVector() && DstVT.isVector())
10552 // All other conversions need to be expanded.
10556 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10557 SDNode *Node = Op.getNode();
10558 DebugLoc dl = Node->getDebugLoc();
10559 EVT T = Node->getValueType(0);
10560 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10561 DAG.getConstant(0, T), Node->getOperand(2));
10562 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10563 cast<AtomicSDNode>(Node)->getMemoryVT(),
10564 Node->getOperand(0),
10565 Node->getOperand(1), negOp,
10566 cast<AtomicSDNode>(Node)->getSrcValue(),
10567 cast<AtomicSDNode>(Node)->getAlignment(),
10568 cast<AtomicSDNode>(Node)->getOrdering(),
10569 cast<AtomicSDNode>(Node)->getSynchScope());
10572 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10573 SDNode *Node = Op.getNode();
10574 DebugLoc dl = Node->getDebugLoc();
10575 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10577 // Convert seq_cst store -> xchg
10578 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10579 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10580 // (The only way to get a 16-byte store is cmpxchg16b)
10581 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10582 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10583 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10584 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10585 cast<AtomicSDNode>(Node)->getMemoryVT(),
10586 Node->getOperand(0),
10587 Node->getOperand(1), Node->getOperand(2),
10588 cast<AtomicSDNode>(Node)->getMemOperand(),
10589 cast<AtomicSDNode>(Node)->getOrdering(),
10590 cast<AtomicSDNode>(Node)->getSynchScope());
10591 return Swap.getValue(1);
10593 // Other atomic stores have a simple pattern.
10597 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10598 EVT VT = Op.getNode()->getValueType(0);
10600 // Let legalize expand this if it isn't a legal type yet.
10601 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10604 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10607 bool ExtraOp = false;
10608 switch (Op.getOpcode()) {
10609 default: assert(0 && "Invalid code");
10610 case ISD::ADDC: Opc = X86ISD::ADD; break;
10611 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10612 case ISD::SUBC: Opc = X86ISD::SUB; break;
10613 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10617 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10619 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10620 Op.getOperand(1), Op.getOperand(2));
10623 /// LowerOperation - Provide custom lowering hooks for some operations.
10625 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10626 switch (Op.getOpcode()) {
10627 default: llvm_unreachable("Should not custom lower this!");
10628 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10629 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10630 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10631 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10632 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10633 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10634 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10635 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10636 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10637 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10638 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10639 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10640 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10641 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10642 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10643 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10644 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10645 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10646 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10647 case ISD::SHL_PARTS:
10648 case ISD::SRA_PARTS:
10649 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10650 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10651 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10652 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10653 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10654 case ISD::FABS: return LowerFABS(Op, DAG);
10655 case ISD::FNEG: return LowerFNEG(Op, DAG);
10656 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10657 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10658 case ISD::SETCC: return LowerSETCC(Op, DAG);
10659 case ISD::SELECT: return LowerSELECT(Op, DAG);
10660 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10661 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10662 case ISD::VASTART: return LowerVASTART(Op, DAG);
10663 case ISD::VAARG: return LowerVAARG(Op, DAG);
10664 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10665 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10666 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10667 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10668 case ISD::FRAME_TO_ARGS_OFFSET:
10669 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10670 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10671 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10672 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10673 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10674 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10675 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10676 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10677 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10678 case ISD::MUL: return LowerMUL(Op, DAG);
10681 case ISD::SHL: return LowerShift(Op, DAG);
10687 case ISD::UMULO: return LowerXALUO(Op, DAG);
10688 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10689 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10693 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10694 case ISD::ADD: return LowerADD(Op, DAG);
10695 case ISD::SUB: return LowerSUB(Op, DAG);
10699 static void ReplaceATOMIC_LOAD(SDNode *Node,
10700 SmallVectorImpl<SDValue> &Results,
10701 SelectionDAG &DAG) {
10702 DebugLoc dl = Node->getDebugLoc();
10703 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10705 // Convert wide load -> cmpxchg8b/cmpxchg16b
10706 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10707 // (The only way to get a 16-byte load is cmpxchg16b)
10708 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10709 SDValue Zero = DAG.getConstant(0, VT);
10710 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10711 Node->getOperand(0),
10712 Node->getOperand(1), Zero, Zero,
10713 cast<AtomicSDNode>(Node)->getMemOperand(),
10714 cast<AtomicSDNode>(Node)->getOrdering(),
10715 cast<AtomicSDNode>(Node)->getSynchScope());
10716 Results.push_back(Swap.getValue(0));
10717 Results.push_back(Swap.getValue(1));
10720 void X86TargetLowering::
10721 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10722 SelectionDAG &DAG, unsigned NewOp) const {
10723 DebugLoc dl = Node->getDebugLoc();
10724 assert (Node->getValueType(0) == MVT::i64 &&
10725 "Only know how to expand i64 atomics");
10727 SDValue Chain = Node->getOperand(0);
10728 SDValue In1 = Node->getOperand(1);
10729 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10730 Node->getOperand(2), DAG.getIntPtrConstant(0));
10731 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10732 Node->getOperand(2), DAG.getIntPtrConstant(1));
10733 SDValue Ops[] = { Chain, In1, In2L, In2H };
10734 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10736 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10737 cast<MemSDNode>(Node)->getMemOperand());
10738 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10739 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10740 Results.push_back(Result.getValue(2));
10743 /// ReplaceNodeResults - Replace a node with an illegal result type
10744 /// with a new node built out of custom code.
10745 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10746 SmallVectorImpl<SDValue>&Results,
10747 SelectionDAG &DAG) const {
10748 DebugLoc dl = N->getDebugLoc();
10749 switch (N->getOpcode()) {
10751 assert(false && "Do not know how to custom type legalize this operation!");
10753 case ISD::SIGN_EXTEND_INREG:
10758 // We don't want to expand or promote these.
10760 case ISD::FP_TO_SINT: {
10761 std::pair<SDValue,SDValue> Vals =
10762 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10763 SDValue FIST = Vals.first, StackSlot = Vals.second;
10764 if (FIST.getNode() != 0) {
10765 EVT VT = N->getValueType(0);
10766 // Return a load from the stack slot.
10767 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10768 MachinePointerInfo(),
10769 false, false, false, 0));
10773 case ISD::READCYCLECOUNTER: {
10774 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10775 SDValue TheChain = N->getOperand(0);
10776 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10777 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10779 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10781 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10782 SDValue Ops[] = { eax, edx };
10783 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10784 Results.push_back(edx.getValue(1));
10787 case ISD::ATOMIC_CMP_SWAP: {
10788 EVT T = N->getValueType(0);
10789 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10790 bool Regs64bit = T == MVT::i128;
10791 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10792 SDValue cpInL, cpInH;
10793 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10794 DAG.getConstant(0, HalfT));
10795 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10796 DAG.getConstant(1, HalfT));
10797 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10798 Regs64bit ? X86::RAX : X86::EAX,
10800 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10801 Regs64bit ? X86::RDX : X86::EDX,
10802 cpInH, cpInL.getValue(1));
10803 SDValue swapInL, swapInH;
10804 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10805 DAG.getConstant(0, HalfT));
10806 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10807 DAG.getConstant(1, HalfT));
10808 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10809 Regs64bit ? X86::RBX : X86::EBX,
10810 swapInL, cpInH.getValue(1));
10811 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10812 Regs64bit ? X86::RCX : X86::ECX,
10813 swapInH, swapInL.getValue(1));
10814 SDValue Ops[] = { swapInH.getValue(0),
10816 swapInH.getValue(1) };
10817 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10818 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10819 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10820 X86ISD::LCMPXCHG8_DAG;
10821 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10823 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10824 Regs64bit ? X86::RAX : X86::EAX,
10825 HalfT, Result.getValue(1));
10826 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10827 Regs64bit ? X86::RDX : X86::EDX,
10828 HalfT, cpOutL.getValue(2));
10829 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10830 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10831 Results.push_back(cpOutH.getValue(1));
10834 case ISD::ATOMIC_LOAD_ADD:
10835 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10837 case ISD::ATOMIC_LOAD_AND:
10838 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10840 case ISD::ATOMIC_LOAD_NAND:
10841 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10843 case ISD::ATOMIC_LOAD_OR:
10844 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10846 case ISD::ATOMIC_LOAD_SUB:
10847 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10849 case ISD::ATOMIC_LOAD_XOR:
10850 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10852 case ISD::ATOMIC_SWAP:
10853 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10855 case ISD::ATOMIC_LOAD:
10856 ReplaceATOMIC_LOAD(N, Results, DAG);
10860 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10862 default: return NULL;
10863 case X86ISD::BSF: return "X86ISD::BSF";
10864 case X86ISD::BSR: return "X86ISD::BSR";
10865 case X86ISD::SHLD: return "X86ISD::SHLD";
10866 case X86ISD::SHRD: return "X86ISD::SHRD";
10867 case X86ISD::FAND: return "X86ISD::FAND";
10868 case X86ISD::FOR: return "X86ISD::FOR";
10869 case X86ISD::FXOR: return "X86ISD::FXOR";
10870 case X86ISD::FSRL: return "X86ISD::FSRL";
10871 case X86ISD::FILD: return "X86ISD::FILD";
10872 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10873 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10874 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10875 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10876 case X86ISD::FLD: return "X86ISD::FLD";
10877 case X86ISD::FST: return "X86ISD::FST";
10878 case X86ISD::CALL: return "X86ISD::CALL";
10879 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10880 case X86ISD::BT: return "X86ISD::BT";
10881 case X86ISD::CMP: return "X86ISD::CMP";
10882 case X86ISD::COMI: return "X86ISD::COMI";
10883 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10884 case X86ISD::SETCC: return "X86ISD::SETCC";
10885 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10886 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10887 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10888 case X86ISD::CMOV: return "X86ISD::CMOV";
10889 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10890 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10891 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10892 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10893 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10894 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10895 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10896 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10897 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10898 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10899 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10900 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10901 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10902 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10903 case X86ISD::PSIGN: return "X86ISD::PSIGN";
10904 case X86ISD::BLENDV: return "X86ISD::BLENDV";
10905 case X86ISD::HADD: return "X86ISD::HADD";
10906 case X86ISD::HSUB: return "X86ISD::HSUB";
10907 case X86ISD::FHADD: return "X86ISD::FHADD";
10908 case X86ISD::FHSUB: return "X86ISD::FHSUB";
10909 case X86ISD::FMAX: return "X86ISD::FMAX";
10910 case X86ISD::FMIN: return "X86ISD::FMIN";
10911 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10912 case X86ISD::FRCP: return "X86ISD::FRCP";
10913 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10914 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10915 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10916 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10917 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10918 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10919 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10920 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10921 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10922 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10923 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10924 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10925 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10926 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10927 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10928 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
10929 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
10930 case X86ISD::VSHL: return "X86ISD::VSHL";
10931 case X86ISD::VSRL: return "X86ISD::VSRL";
10932 case X86ISD::VSRA: return "X86ISD::VSRA";
10933 case X86ISD::VSHLI: return "X86ISD::VSHLI";
10934 case X86ISD::VSRLI: return "X86ISD::VSRLI";
10935 case X86ISD::VSRAI: return "X86ISD::VSRAI";
10936 case X86ISD::CMPP: return "X86ISD::CMPP";
10937 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
10938 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
10939 case X86ISD::ADD: return "X86ISD::ADD";
10940 case X86ISD::SUB: return "X86ISD::SUB";
10941 case X86ISD::ADC: return "X86ISD::ADC";
10942 case X86ISD::SBB: return "X86ISD::SBB";
10943 case X86ISD::SMUL: return "X86ISD::SMUL";
10944 case X86ISD::UMUL: return "X86ISD::UMUL";
10945 case X86ISD::INC: return "X86ISD::INC";
10946 case X86ISD::DEC: return "X86ISD::DEC";
10947 case X86ISD::OR: return "X86ISD::OR";
10948 case X86ISD::XOR: return "X86ISD::XOR";
10949 case X86ISD::AND: return "X86ISD::AND";
10950 case X86ISD::ANDN: return "X86ISD::ANDN";
10951 case X86ISD::BLSI: return "X86ISD::BLSI";
10952 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
10953 case X86ISD::BLSR: return "X86ISD::BLSR";
10954 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10955 case X86ISD::PTEST: return "X86ISD::PTEST";
10956 case X86ISD::TESTP: return "X86ISD::TESTP";
10957 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10958 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10959 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
10960 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
10961 case X86ISD::SHUFP: return "X86ISD::SHUFP";
10962 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
10963 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
10964 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
10965 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
10966 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
10967 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
10968 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
10969 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
10970 case X86ISD::MOVSD: return "X86ISD::MOVSD";
10971 case X86ISD::MOVSS: return "X86ISD::MOVSS";
10972 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
10973 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
10974 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
10975 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
10976 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
10977 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
10978 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
10979 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
10980 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
10981 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
10985 // isLegalAddressingMode - Return true if the addressing mode represented
10986 // by AM is legal for this target, for a load/store of the specified type.
10987 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
10989 // X86 supports extremely general addressing modes.
10990 CodeModel::Model M = getTargetMachine().getCodeModel();
10991 Reloc::Model R = getTargetMachine().getRelocationModel();
10993 // X86 allows a sign-extended 32-bit immediate field as a displacement.
10994 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
10999 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11001 // If a reference to this global requires an extra load, we can't fold it.
11002 if (isGlobalStubReference(GVFlags))
11005 // If BaseGV requires a register for the PIC base, we cannot also have a
11006 // BaseReg specified.
11007 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11010 // If lower 4G is not available, then we must use rip-relative addressing.
11011 if ((M != CodeModel::Small || R != Reloc::Static) &&
11012 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11016 switch (AM.Scale) {
11022 // These scales always work.
11027 // These scales are formed with basereg+scalereg. Only accept if there is
11032 default: // Other stuff never works.
11040 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11041 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11043 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11044 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11045 if (NumBits1 <= NumBits2)
11050 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11051 if (!VT1.isInteger() || !VT2.isInteger())
11053 unsigned NumBits1 = VT1.getSizeInBits();
11054 unsigned NumBits2 = VT2.getSizeInBits();
11055 if (NumBits1 <= NumBits2)
11060 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11061 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11062 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11065 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11066 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11067 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11070 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11071 // i16 instructions are longer (0x66 prefix) and potentially slower.
11072 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11075 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11076 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11077 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11078 /// are assumed to be legal.
11080 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11082 // Very little shuffling can be done for 64-bit vectors right now.
11083 if (VT.getSizeInBits() == 64)
11086 // FIXME: pshufb, blends, shifts.
11087 return (VT.getVectorNumElements() == 2 ||
11088 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11089 isMOVLMask(M, VT) ||
11090 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11091 isPSHUFDMask(M, VT) ||
11092 isPSHUFHWMask(M, VT) ||
11093 isPSHUFLWMask(M, VT) ||
11094 isPALIGNRMask(M, VT, Subtarget) ||
11095 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11096 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11097 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11098 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11102 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11104 unsigned NumElts = VT.getVectorNumElements();
11105 // FIXME: This collection of masks seems suspect.
11108 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11109 return (isMOVLMask(Mask, VT) ||
11110 isCommutedMOVLMask(Mask, VT, true) ||
11111 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11112 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11117 //===----------------------------------------------------------------------===//
11118 // X86 Scheduler Hooks
11119 //===----------------------------------------------------------------------===//
11121 // private utility function
11122 MachineBasicBlock *
11123 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11124 MachineBasicBlock *MBB,
11131 TargetRegisterClass *RC,
11132 bool invSrc) const {
11133 // For the atomic bitwise operator, we generate
11136 // ld t1 = [bitinstr.addr]
11137 // op t2 = t1, [bitinstr.val]
11139 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11141 // fallthrough -->nextMBB
11142 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11143 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11144 MachineFunction::iterator MBBIter = MBB;
11147 /// First build the CFG
11148 MachineFunction *F = MBB->getParent();
11149 MachineBasicBlock *thisMBB = MBB;
11150 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11151 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11152 F->insert(MBBIter, newMBB);
11153 F->insert(MBBIter, nextMBB);
11155 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11156 nextMBB->splice(nextMBB->begin(), thisMBB,
11157 llvm::next(MachineBasicBlock::iterator(bInstr)),
11159 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11161 // Update thisMBB to fall through to newMBB
11162 thisMBB->addSuccessor(newMBB);
11164 // newMBB jumps to itself and fall through to nextMBB
11165 newMBB->addSuccessor(nextMBB);
11166 newMBB->addSuccessor(newMBB);
11168 // Insert instructions into newMBB based on incoming instruction
11169 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11170 "unexpected number of operands");
11171 DebugLoc dl = bInstr->getDebugLoc();
11172 MachineOperand& destOper = bInstr->getOperand(0);
11173 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11174 int numArgs = bInstr->getNumOperands() - 1;
11175 for (int i=0; i < numArgs; ++i)
11176 argOpers[i] = &bInstr->getOperand(i+1);
11178 // x86 address has 4 operands: base, index, scale, and displacement
11179 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11180 int valArgIndx = lastAddrIndx + 1;
11182 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11183 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11184 for (int i=0; i <= lastAddrIndx; ++i)
11185 (*MIB).addOperand(*argOpers[i]);
11187 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
11189 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
11194 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11195 assert((argOpers[valArgIndx]->isReg() ||
11196 argOpers[valArgIndx]->isImm()) &&
11197 "invalid operand");
11198 if (argOpers[valArgIndx]->isReg())
11199 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11201 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11203 (*MIB).addOperand(*argOpers[valArgIndx]);
11205 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11208 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11209 for (int i=0; i <= lastAddrIndx; ++i)
11210 (*MIB).addOperand(*argOpers[i]);
11212 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11213 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11214 bInstr->memoperands_end());
11216 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11217 MIB.addReg(EAXreg);
11220 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11222 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11226 // private utility function: 64 bit atomics on 32 bit host.
11227 MachineBasicBlock *
11228 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11229 MachineBasicBlock *MBB,
11234 bool invSrc) const {
11235 // For the atomic bitwise operator, we generate
11236 // thisMBB (instructions are in pairs, except cmpxchg8b)
11237 // ld t1,t2 = [bitinstr.addr]
11239 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11240 // op t5, t6 <- out1, out2, [bitinstr.val]
11241 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11242 // mov ECX, EBX <- t5, t6
11243 // mov EAX, EDX <- t1, t2
11244 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11245 // mov t3, t4 <- EAX, EDX
11247 // result in out1, out2
11248 // fallthrough -->nextMBB
11250 const TargetRegisterClass *RC = X86::GR32RegisterClass;
11251 const unsigned LoadOpc = X86::MOV32rm;
11252 const unsigned NotOpc = X86::NOT32r;
11253 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11254 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11255 MachineFunction::iterator MBBIter = MBB;
11258 /// First build the CFG
11259 MachineFunction *F = MBB->getParent();
11260 MachineBasicBlock *thisMBB = MBB;
11261 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11262 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11263 F->insert(MBBIter, newMBB);
11264 F->insert(MBBIter, nextMBB);
11266 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11267 nextMBB->splice(nextMBB->begin(), thisMBB,
11268 llvm::next(MachineBasicBlock::iterator(bInstr)),
11270 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11272 // Update thisMBB to fall through to newMBB
11273 thisMBB->addSuccessor(newMBB);
11275 // newMBB jumps to itself and fall through to nextMBB
11276 newMBB->addSuccessor(nextMBB);
11277 newMBB->addSuccessor(newMBB);
11279 DebugLoc dl = bInstr->getDebugLoc();
11280 // Insert instructions into newMBB based on incoming instruction
11281 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11282 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11283 "unexpected number of operands");
11284 MachineOperand& dest1Oper = bInstr->getOperand(0);
11285 MachineOperand& dest2Oper = bInstr->getOperand(1);
11286 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11287 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11288 argOpers[i] = &bInstr->getOperand(i+2);
11290 // We use some of the operands multiple times, so conservatively just
11291 // clear any kill flags that might be present.
11292 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11293 argOpers[i]->setIsKill(false);
11296 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11297 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11299 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11300 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11301 for (int i=0; i <= lastAddrIndx; ++i)
11302 (*MIB).addOperand(*argOpers[i]);
11303 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11304 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11305 // add 4 to displacement.
11306 for (int i=0; i <= lastAddrIndx-2; ++i)
11307 (*MIB).addOperand(*argOpers[i]);
11308 MachineOperand newOp3 = *(argOpers[3]);
11309 if (newOp3.isImm())
11310 newOp3.setImm(newOp3.getImm()+4);
11312 newOp3.setOffset(newOp3.getOffset()+4);
11313 (*MIB).addOperand(newOp3);
11314 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11316 // t3/4 are defined later, at the bottom of the loop
11317 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11318 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11319 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11320 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11321 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11322 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11324 // The subsequent operations should be using the destination registers of
11325 //the PHI instructions.
11327 t1 = F->getRegInfo().createVirtualRegister(RC);
11328 t2 = F->getRegInfo().createVirtualRegister(RC);
11329 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11330 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11332 t1 = dest1Oper.getReg();
11333 t2 = dest2Oper.getReg();
11336 int valArgIndx = lastAddrIndx + 1;
11337 assert((argOpers[valArgIndx]->isReg() ||
11338 argOpers[valArgIndx]->isImm()) &&
11339 "invalid operand");
11340 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11341 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11342 if (argOpers[valArgIndx]->isReg())
11343 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11345 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11346 if (regOpcL != X86::MOV32rr)
11348 (*MIB).addOperand(*argOpers[valArgIndx]);
11349 assert(argOpers[valArgIndx + 1]->isReg() ==
11350 argOpers[valArgIndx]->isReg());
11351 assert(argOpers[valArgIndx + 1]->isImm() ==
11352 argOpers[valArgIndx]->isImm());
11353 if (argOpers[valArgIndx + 1]->isReg())
11354 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11356 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11357 if (regOpcH != X86::MOV32rr)
11359 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11361 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11363 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11366 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11368 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11371 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11372 for (int i=0; i <= lastAddrIndx; ++i)
11373 (*MIB).addOperand(*argOpers[i]);
11375 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11376 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11377 bInstr->memoperands_end());
11379 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11380 MIB.addReg(X86::EAX);
11381 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11382 MIB.addReg(X86::EDX);
11385 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11387 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11391 // private utility function
11392 MachineBasicBlock *
11393 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11394 MachineBasicBlock *MBB,
11395 unsigned cmovOpc) const {
11396 // For the atomic min/max operator, we generate
11399 // ld t1 = [min/max.addr]
11400 // mov t2 = [min/max.val]
11402 // cmov[cond] t2 = t1
11404 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11406 // fallthrough -->nextMBB
11408 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11409 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11410 MachineFunction::iterator MBBIter = MBB;
11413 /// First build the CFG
11414 MachineFunction *F = MBB->getParent();
11415 MachineBasicBlock *thisMBB = MBB;
11416 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11417 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11418 F->insert(MBBIter, newMBB);
11419 F->insert(MBBIter, nextMBB);
11421 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11422 nextMBB->splice(nextMBB->begin(), thisMBB,
11423 llvm::next(MachineBasicBlock::iterator(mInstr)),
11425 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11427 // Update thisMBB to fall through to newMBB
11428 thisMBB->addSuccessor(newMBB);
11430 // newMBB jumps to newMBB and fall through to nextMBB
11431 newMBB->addSuccessor(nextMBB);
11432 newMBB->addSuccessor(newMBB);
11434 DebugLoc dl = mInstr->getDebugLoc();
11435 // Insert instructions into newMBB based on incoming instruction
11436 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11437 "unexpected number of operands");
11438 MachineOperand& destOper = mInstr->getOperand(0);
11439 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11440 int numArgs = mInstr->getNumOperands() - 1;
11441 for (int i=0; i < numArgs; ++i)
11442 argOpers[i] = &mInstr->getOperand(i+1);
11444 // x86 address has 4 operands: base, index, scale, and displacement
11445 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11446 int valArgIndx = lastAddrIndx + 1;
11448 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11449 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11450 for (int i=0; i <= lastAddrIndx; ++i)
11451 (*MIB).addOperand(*argOpers[i]);
11453 // We only support register and immediate values
11454 assert((argOpers[valArgIndx]->isReg() ||
11455 argOpers[valArgIndx]->isImm()) &&
11456 "invalid operand");
11458 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11459 if (argOpers[valArgIndx]->isReg())
11460 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11462 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11463 (*MIB).addOperand(*argOpers[valArgIndx]);
11465 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11468 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11473 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11474 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11478 // Cmp and exchange if none has modified the memory location
11479 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11480 for (int i=0; i <= lastAddrIndx; ++i)
11481 (*MIB).addOperand(*argOpers[i]);
11483 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11484 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11485 mInstr->memoperands_end());
11487 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11488 MIB.addReg(X86::EAX);
11491 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11493 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11497 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11498 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11499 // in the .td file.
11500 MachineBasicBlock *
11501 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11502 unsigned numArgs, bool memArg) const {
11503 assert(Subtarget->hasSSE42() &&
11504 "Target must have SSE4.2 or AVX features enabled");
11506 DebugLoc dl = MI->getDebugLoc();
11507 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11509 if (!Subtarget->hasAVX()) {
11511 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11513 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11516 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11518 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11521 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11522 for (unsigned i = 0; i < numArgs; ++i) {
11523 MachineOperand &Op = MI->getOperand(i+1);
11524 if (!(Op.isReg() && Op.isImplicit()))
11525 MIB.addOperand(Op);
11527 BuildMI(*BB, MI, dl,
11528 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11529 MI->getOperand(0).getReg())
11530 .addReg(X86::XMM0);
11532 MI->eraseFromParent();
11536 MachineBasicBlock *
11537 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11538 DebugLoc dl = MI->getDebugLoc();
11539 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11541 // Address into RAX/EAX, other two args into ECX, EDX.
11542 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11543 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11544 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11545 for (int i = 0; i < X86::AddrNumOperands; ++i)
11546 MIB.addOperand(MI->getOperand(i));
11548 unsigned ValOps = X86::AddrNumOperands;
11549 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11550 .addReg(MI->getOperand(ValOps).getReg());
11551 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11552 .addReg(MI->getOperand(ValOps+1).getReg());
11554 // The instruction doesn't actually take any operands though.
11555 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11557 MI->eraseFromParent(); // The pseudo is gone now.
11561 MachineBasicBlock *
11562 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11563 DebugLoc dl = MI->getDebugLoc();
11564 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11566 // First arg in ECX, the second in EAX.
11567 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11568 .addReg(MI->getOperand(0).getReg());
11569 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11570 .addReg(MI->getOperand(1).getReg());
11572 // The instruction doesn't actually take any operands though.
11573 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11575 MI->eraseFromParent(); // The pseudo is gone now.
11579 MachineBasicBlock *
11580 X86TargetLowering::EmitVAARG64WithCustomInserter(
11582 MachineBasicBlock *MBB) const {
11583 // Emit va_arg instruction on X86-64.
11585 // Operands to this pseudo-instruction:
11586 // 0 ) Output : destination address (reg)
11587 // 1-5) Input : va_list address (addr, i64mem)
11588 // 6 ) ArgSize : Size (in bytes) of vararg type
11589 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11590 // 8 ) Align : Alignment of type
11591 // 9 ) EFLAGS (implicit-def)
11593 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11594 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11596 unsigned DestReg = MI->getOperand(0).getReg();
11597 MachineOperand &Base = MI->getOperand(1);
11598 MachineOperand &Scale = MI->getOperand(2);
11599 MachineOperand &Index = MI->getOperand(3);
11600 MachineOperand &Disp = MI->getOperand(4);
11601 MachineOperand &Segment = MI->getOperand(5);
11602 unsigned ArgSize = MI->getOperand(6).getImm();
11603 unsigned ArgMode = MI->getOperand(7).getImm();
11604 unsigned Align = MI->getOperand(8).getImm();
11606 // Memory Reference
11607 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11608 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11609 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11611 // Machine Information
11612 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11613 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11614 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11615 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11616 DebugLoc DL = MI->getDebugLoc();
11618 // struct va_list {
11621 // i64 overflow_area (address)
11622 // i64 reg_save_area (address)
11624 // sizeof(va_list) = 24
11625 // alignment(va_list) = 8
11627 unsigned TotalNumIntRegs = 6;
11628 unsigned TotalNumXMMRegs = 8;
11629 bool UseGPOffset = (ArgMode == 1);
11630 bool UseFPOffset = (ArgMode == 2);
11631 unsigned MaxOffset = TotalNumIntRegs * 8 +
11632 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11634 /* Align ArgSize to a multiple of 8 */
11635 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11636 bool NeedsAlign = (Align > 8);
11638 MachineBasicBlock *thisMBB = MBB;
11639 MachineBasicBlock *overflowMBB;
11640 MachineBasicBlock *offsetMBB;
11641 MachineBasicBlock *endMBB;
11643 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11644 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11645 unsigned OffsetReg = 0;
11647 if (!UseGPOffset && !UseFPOffset) {
11648 // If we only pull from the overflow region, we don't create a branch.
11649 // We don't need to alter control flow.
11650 OffsetDestReg = 0; // unused
11651 OverflowDestReg = DestReg;
11654 overflowMBB = thisMBB;
11657 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11658 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11659 // If not, pull from overflow_area. (branch to overflowMBB)
11664 // offsetMBB overflowMBB
11669 // Registers for the PHI in endMBB
11670 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11671 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11673 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11674 MachineFunction *MF = MBB->getParent();
11675 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11676 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11677 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11679 MachineFunction::iterator MBBIter = MBB;
11682 // Insert the new basic blocks
11683 MF->insert(MBBIter, offsetMBB);
11684 MF->insert(MBBIter, overflowMBB);
11685 MF->insert(MBBIter, endMBB);
11687 // Transfer the remainder of MBB and its successor edges to endMBB.
11688 endMBB->splice(endMBB->begin(), thisMBB,
11689 llvm::next(MachineBasicBlock::iterator(MI)),
11691 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11693 // Make offsetMBB and overflowMBB successors of thisMBB
11694 thisMBB->addSuccessor(offsetMBB);
11695 thisMBB->addSuccessor(overflowMBB);
11697 // endMBB is a successor of both offsetMBB and overflowMBB
11698 offsetMBB->addSuccessor(endMBB);
11699 overflowMBB->addSuccessor(endMBB);
11701 // Load the offset value into a register
11702 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11703 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11707 .addDisp(Disp, UseFPOffset ? 4 : 0)
11708 .addOperand(Segment)
11709 .setMemRefs(MMOBegin, MMOEnd);
11711 // Check if there is enough room left to pull this argument.
11712 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11714 .addImm(MaxOffset + 8 - ArgSizeA8);
11716 // Branch to "overflowMBB" if offset >= max
11717 // Fall through to "offsetMBB" otherwise
11718 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11719 .addMBB(overflowMBB);
11722 // In offsetMBB, emit code to use the reg_save_area.
11724 assert(OffsetReg != 0);
11726 // Read the reg_save_area address.
11727 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11728 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11733 .addOperand(Segment)
11734 .setMemRefs(MMOBegin, MMOEnd);
11736 // Zero-extend the offset
11737 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11738 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11741 .addImm(X86::sub_32bit);
11743 // Add the offset to the reg_save_area to get the final address.
11744 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11745 .addReg(OffsetReg64)
11746 .addReg(RegSaveReg);
11748 // Compute the offset for the next argument
11749 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11750 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11752 .addImm(UseFPOffset ? 16 : 8);
11754 // Store it back into the va_list.
11755 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11759 .addDisp(Disp, UseFPOffset ? 4 : 0)
11760 .addOperand(Segment)
11761 .addReg(NextOffsetReg)
11762 .setMemRefs(MMOBegin, MMOEnd);
11765 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11770 // Emit code to use overflow area
11773 // Load the overflow_area address into a register.
11774 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11775 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11780 .addOperand(Segment)
11781 .setMemRefs(MMOBegin, MMOEnd);
11783 // If we need to align it, do so. Otherwise, just copy the address
11784 // to OverflowDestReg.
11786 // Align the overflow address
11787 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11788 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11790 // aligned_addr = (addr + (align-1)) & ~(align-1)
11791 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11792 .addReg(OverflowAddrReg)
11795 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11797 .addImm(~(uint64_t)(Align-1));
11799 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11800 .addReg(OverflowAddrReg);
11803 // Compute the next overflow address after this argument.
11804 // (the overflow address should be kept 8-byte aligned)
11805 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11806 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11807 .addReg(OverflowDestReg)
11808 .addImm(ArgSizeA8);
11810 // Store the new overflow address.
11811 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11816 .addOperand(Segment)
11817 .addReg(NextAddrReg)
11818 .setMemRefs(MMOBegin, MMOEnd);
11820 // If we branched, emit the PHI to the front of endMBB.
11822 BuildMI(*endMBB, endMBB->begin(), DL,
11823 TII->get(X86::PHI), DestReg)
11824 .addReg(OffsetDestReg).addMBB(offsetMBB)
11825 .addReg(OverflowDestReg).addMBB(overflowMBB);
11828 // Erase the pseudo instruction
11829 MI->eraseFromParent();
11834 MachineBasicBlock *
11835 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11837 MachineBasicBlock *MBB) const {
11838 // Emit code to save XMM registers to the stack. The ABI says that the
11839 // number of registers to save is given in %al, so it's theoretically
11840 // possible to do an indirect jump trick to avoid saving all of them,
11841 // however this code takes a simpler approach and just executes all
11842 // of the stores if %al is non-zero. It's less code, and it's probably
11843 // easier on the hardware branch predictor, and stores aren't all that
11844 // expensive anyway.
11846 // Create the new basic blocks. One block contains all the XMM stores,
11847 // and one block is the final destination regardless of whether any
11848 // stores were performed.
11849 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11850 MachineFunction *F = MBB->getParent();
11851 MachineFunction::iterator MBBIter = MBB;
11853 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11854 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11855 F->insert(MBBIter, XMMSaveMBB);
11856 F->insert(MBBIter, EndMBB);
11858 // Transfer the remainder of MBB and its successor edges to EndMBB.
11859 EndMBB->splice(EndMBB->begin(), MBB,
11860 llvm::next(MachineBasicBlock::iterator(MI)),
11862 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11864 // The original block will now fall through to the XMM save block.
11865 MBB->addSuccessor(XMMSaveMBB);
11866 // The XMMSaveMBB will fall through to the end block.
11867 XMMSaveMBB->addSuccessor(EndMBB);
11869 // Now add the instructions.
11870 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11871 DebugLoc DL = MI->getDebugLoc();
11873 unsigned CountReg = MI->getOperand(0).getReg();
11874 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11875 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11877 if (!Subtarget->isTargetWin64()) {
11878 // If %al is 0, branch around the XMM save block.
11879 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11880 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11881 MBB->addSuccessor(EndMBB);
11884 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
11885 // In the XMM save block, save all the XMM argument registers.
11886 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11887 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11888 MachineMemOperand *MMO =
11889 F->getMachineMemOperand(
11890 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11891 MachineMemOperand::MOStore,
11892 /*Size=*/16, /*Align=*/16);
11893 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
11894 .addFrameIndex(RegSaveFrameIndex)
11895 .addImm(/*Scale=*/1)
11896 .addReg(/*IndexReg=*/0)
11897 .addImm(/*Disp=*/Offset)
11898 .addReg(/*Segment=*/0)
11899 .addReg(MI->getOperand(i).getReg())
11900 .addMemOperand(MMO);
11903 MI->eraseFromParent(); // The pseudo instruction is gone now.
11908 MachineBasicBlock *
11909 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11910 MachineBasicBlock *BB) const {
11911 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11912 DebugLoc DL = MI->getDebugLoc();
11914 // To "insert" a SELECT_CC instruction, we actually have to insert the
11915 // diamond control-flow pattern. The incoming instruction knows the
11916 // destination vreg to set, the condition code register to branch on, the
11917 // true/false values to select between, and a branch opcode to use.
11918 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11919 MachineFunction::iterator It = BB;
11925 // cmpTY ccX, r1, r2
11927 // fallthrough --> copy0MBB
11928 MachineBasicBlock *thisMBB = BB;
11929 MachineFunction *F = BB->getParent();
11930 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11931 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11932 F->insert(It, copy0MBB);
11933 F->insert(It, sinkMBB);
11935 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11936 // live into the sink and copy blocks.
11937 if (!MI->killsRegister(X86::EFLAGS)) {
11938 copy0MBB->addLiveIn(X86::EFLAGS);
11939 sinkMBB->addLiveIn(X86::EFLAGS);
11942 // Transfer the remainder of BB and its successor edges to sinkMBB.
11943 sinkMBB->splice(sinkMBB->begin(), BB,
11944 llvm::next(MachineBasicBlock::iterator(MI)),
11946 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11948 // Add the true and fallthrough blocks as its successors.
11949 BB->addSuccessor(copy0MBB);
11950 BB->addSuccessor(sinkMBB);
11952 // Create the conditional branch instruction.
11954 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11955 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
11958 // %FalseValue = ...
11959 // # fallthrough to sinkMBB
11960 copy0MBB->addSuccessor(sinkMBB);
11963 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
11965 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
11966 TII->get(X86::PHI), MI->getOperand(0).getReg())
11967 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
11968 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
11970 MI->eraseFromParent(); // The pseudo instruction is gone now.
11974 MachineBasicBlock *
11975 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
11976 bool Is64Bit) const {
11977 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11978 DebugLoc DL = MI->getDebugLoc();
11979 MachineFunction *MF = BB->getParent();
11980 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11982 assert(getTargetMachine().Options.EnableSegmentedStacks);
11984 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
11985 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
11988 // ... [Till the alloca]
11989 // If stacklet is not large enough, jump to mallocMBB
11992 // Allocate by subtracting from RSP
11993 // Jump to continueMBB
11996 // Allocate by call to runtime
12000 // [rest of original BB]
12003 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12004 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12005 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12007 MachineRegisterInfo &MRI = MF->getRegInfo();
12008 const TargetRegisterClass *AddrRegClass =
12009 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12011 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12012 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12013 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12014 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12015 sizeVReg = MI->getOperand(1).getReg(),
12016 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12018 MachineFunction::iterator MBBIter = BB;
12021 MF->insert(MBBIter, bumpMBB);
12022 MF->insert(MBBIter, mallocMBB);
12023 MF->insert(MBBIter, continueMBB);
12025 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12026 (MachineBasicBlock::iterator(MI)), BB->end());
12027 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12029 // Add code to the main basic block to check if the stack limit has been hit,
12030 // and if so, jump to mallocMBB otherwise to bumpMBB.
12031 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12032 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12033 .addReg(tmpSPVReg).addReg(sizeVReg);
12034 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12035 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12036 .addReg(SPLimitVReg);
12037 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12039 // bumpMBB simply decreases the stack pointer, since we know the current
12040 // stacklet has enough space.
12041 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12042 .addReg(SPLimitVReg);
12043 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12044 .addReg(SPLimitVReg);
12045 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12047 // Calls into a routine in libgcc to allocate more space from the heap.
12049 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12051 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12052 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI);
12054 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12056 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12057 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12058 .addExternalSymbol("__morestack_allocate_stack_space");
12062 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12065 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12066 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12067 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12069 // Set up the CFG correctly.
12070 BB->addSuccessor(bumpMBB);
12071 BB->addSuccessor(mallocMBB);
12072 mallocMBB->addSuccessor(continueMBB);
12073 bumpMBB->addSuccessor(continueMBB);
12075 // Take care of the PHI nodes.
12076 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12077 MI->getOperand(0).getReg())
12078 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12079 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12081 // Delete the original pseudo instruction.
12082 MI->eraseFromParent();
12085 return continueMBB;
12088 MachineBasicBlock *
12089 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12090 MachineBasicBlock *BB) const {
12091 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12092 DebugLoc DL = MI->getDebugLoc();
12094 assert(!Subtarget->isTargetEnvMacho());
12096 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12097 // non-trivial part is impdef of ESP.
12099 if (Subtarget->isTargetWin64()) {
12100 if (Subtarget->isTargetCygMing()) {
12101 // ___chkstk(Mingw64):
12102 // Clobbers R10, R11, RAX and EFLAGS.
12104 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12105 .addExternalSymbol("___chkstk")
12106 .addReg(X86::RAX, RegState::Implicit)
12107 .addReg(X86::RSP, RegState::Implicit)
12108 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12109 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12110 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12112 // __chkstk(MSVCRT): does not update stack pointer.
12113 // Clobbers R10, R11 and EFLAGS.
12114 // FIXME: RAX(allocated size) might be reused and not killed.
12115 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12116 .addExternalSymbol("__chkstk")
12117 .addReg(X86::RAX, RegState::Implicit)
12118 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12119 // RAX has the offset to subtracted from RSP.
12120 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12125 const char *StackProbeSymbol =
12126 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12128 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12129 .addExternalSymbol(StackProbeSymbol)
12130 .addReg(X86::EAX, RegState::Implicit)
12131 .addReg(X86::ESP, RegState::Implicit)
12132 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12133 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12134 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12137 MI->eraseFromParent(); // The pseudo instruction is gone now.
12141 MachineBasicBlock *
12142 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12143 MachineBasicBlock *BB) const {
12144 // This is pretty easy. We're taking the value that we received from
12145 // our load from the relocation, sticking it in either RDI (x86-64)
12146 // or EAX and doing an indirect call. The return value will then
12147 // be in the normal return register.
12148 const X86InstrInfo *TII
12149 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12150 DebugLoc DL = MI->getDebugLoc();
12151 MachineFunction *F = BB->getParent();
12153 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12154 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12156 if (Subtarget->is64Bit()) {
12157 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12158 TII->get(X86::MOV64rm), X86::RDI)
12160 .addImm(0).addReg(0)
12161 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12162 MI->getOperand(3).getTargetFlags())
12164 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12165 addDirectMem(MIB, X86::RDI);
12166 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12167 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12168 TII->get(X86::MOV32rm), X86::EAX)
12170 .addImm(0).addReg(0)
12171 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12172 MI->getOperand(3).getTargetFlags())
12174 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12175 addDirectMem(MIB, X86::EAX);
12177 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12178 TII->get(X86::MOV32rm), X86::EAX)
12179 .addReg(TII->getGlobalBaseReg(F))
12180 .addImm(0).addReg(0)
12181 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12182 MI->getOperand(3).getTargetFlags())
12184 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12185 addDirectMem(MIB, X86::EAX);
12188 MI->eraseFromParent(); // The pseudo instruction is gone now.
12192 MachineBasicBlock *
12193 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12194 MachineBasicBlock *BB) const {
12195 switch (MI->getOpcode()) {
12196 default: assert(0 && "Unexpected instr type to insert");
12197 case X86::TAILJMPd64:
12198 case X86::TAILJMPr64:
12199 case X86::TAILJMPm64:
12200 assert(0 && "TAILJMP64 would not be touched here.");
12201 case X86::TCRETURNdi64:
12202 case X86::TCRETURNri64:
12203 case X86::TCRETURNmi64:
12204 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
12205 // On AMD64, additional defs should be added before register allocation.
12206 if (!Subtarget->isTargetWin64()) {
12207 MI->addRegisterDefined(X86::RSI);
12208 MI->addRegisterDefined(X86::RDI);
12209 MI->addRegisterDefined(X86::XMM6);
12210 MI->addRegisterDefined(X86::XMM7);
12211 MI->addRegisterDefined(X86::XMM8);
12212 MI->addRegisterDefined(X86::XMM9);
12213 MI->addRegisterDefined(X86::XMM10);
12214 MI->addRegisterDefined(X86::XMM11);
12215 MI->addRegisterDefined(X86::XMM12);
12216 MI->addRegisterDefined(X86::XMM13);
12217 MI->addRegisterDefined(X86::XMM14);
12218 MI->addRegisterDefined(X86::XMM15);
12221 case X86::WIN_ALLOCA:
12222 return EmitLoweredWinAlloca(MI, BB);
12223 case X86::SEG_ALLOCA_32:
12224 return EmitLoweredSegAlloca(MI, BB, false);
12225 case X86::SEG_ALLOCA_64:
12226 return EmitLoweredSegAlloca(MI, BB, true);
12227 case X86::TLSCall_32:
12228 case X86::TLSCall_64:
12229 return EmitLoweredTLSCall(MI, BB);
12230 case X86::CMOV_GR8:
12231 case X86::CMOV_FR32:
12232 case X86::CMOV_FR64:
12233 case X86::CMOV_V4F32:
12234 case X86::CMOV_V2F64:
12235 case X86::CMOV_V2I64:
12236 case X86::CMOV_V8F32:
12237 case X86::CMOV_V4F64:
12238 case X86::CMOV_V4I64:
12239 case X86::CMOV_GR16:
12240 case X86::CMOV_GR32:
12241 case X86::CMOV_RFP32:
12242 case X86::CMOV_RFP64:
12243 case X86::CMOV_RFP80:
12244 return EmitLoweredSelect(MI, BB);
12246 case X86::FP32_TO_INT16_IN_MEM:
12247 case X86::FP32_TO_INT32_IN_MEM:
12248 case X86::FP32_TO_INT64_IN_MEM:
12249 case X86::FP64_TO_INT16_IN_MEM:
12250 case X86::FP64_TO_INT32_IN_MEM:
12251 case X86::FP64_TO_INT64_IN_MEM:
12252 case X86::FP80_TO_INT16_IN_MEM:
12253 case X86::FP80_TO_INT32_IN_MEM:
12254 case X86::FP80_TO_INT64_IN_MEM: {
12255 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12256 DebugLoc DL = MI->getDebugLoc();
12258 // Change the floating point control register to use "round towards zero"
12259 // mode when truncating to an integer value.
12260 MachineFunction *F = BB->getParent();
12261 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12262 addFrameReference(BuildMI(*BB, MI, DL,
12263 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12265 // Load the old value of the high byte of the control word...
12267 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12268 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12271 // Set the high part to be round to zero...
12272 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12275 // Reload the modified control word now...
12276 addFrameReference(BuildMI(*BB, MI, DL,
12277 TII->get(X86::FLDCW16m)), CWFrameIdx);
12279 // Restore the memory image of control word to original value
12280 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12283 // Get the X86 opcode to use.
12285 switch (MI->getOpcode()) {
12286 default: llvm_unreachable("illegal opcode!");
12287 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12288 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12289 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12290 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12291 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12292 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12293 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12294 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12295 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12299 MachineOperand &Op = MI->getOperand(0);
12301 AM.BaseType = X86AddressMode::RegBase;
12302 AM.Base.Reg = Op.getReg();
12304 AM.BaseType = X86AddressMode::FrameIndexBase;
12305 AM.Base.FrameIndex = Op.getIndex();
12307 Op = MI->getOperand(1);
12309 AM.Scale = Op.getImm();
12310 Op = MI->getOperand(2);
12312 AM.IndexReg = Op.getImm();
12313 Op = MI->getOperand(3);
12314 if (Op.isGlobal()) {
12315 AM.GV = Op.getGlobal();
12317 AM.Disp = Op.getImm();
12319 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12320 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12322 // Reload the original control word now.
12323 addFrameReference(BuildMI(*BB, MI, DL,
12324 TII->get(X86::FLDCW16m)), CWFrameIdx);
12326 MI->eraseFromParent(); // The pseudo instruction is gone now.
12329 // String/text processing lowering.
12330 case X86::PCMPISTRM128REG:
12331 case X86::VPCMPISTRM128REG:
12332 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12333 case X86::PCMPISTRM128MEM:
12334 case X86::VPCMPISTRM128MEM:
12335 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12336 case X86::PCMPESTRM128REG:
12337 case X86::VPCMPESTRM128REG:
12338 return EmitPCMP(MI, BB, 5, false /* in mem */);
12339 case X86::PCMPESTRM128MEM:
12340 case X86::VPCMPESTRM128MEM:
12341 return EmitPCMP(MI, BB, 5, true /* in mem */);
12343 // Thread synchronization.
12345 return EmitMonitor(MI, BB);
12347 return EmitMwait(MI, BB);
12349 // Atomic Lowering.
12350 case X86::ATOMAND32:
12351 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12352 X86::AND32ri, X86::MOV32rm,
12354 X86::NOT32r, X86::EAX,
12355 X86::GR32RegisterClass);
12356 case X86::ATOMOR32:
12357 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12358 X86::OR32ri, X86::MOV32rm,
12360 X86::NOT32r, X86::EAX,
12361 X86::GR32RegisterClass);
12362 case X86::ATOMXOR32:
12363 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12364 X86::XOR32ri, X86::MOV32rm,
12366 X86::NOT32r, X86::EAX,
12367 X86::GR32RegisterClass);
12368 case X86::ATOMNAND32:
12369 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12370 X86::AND32ri, X86::MOV32rm,
12372 X86::NOT32r, X86::EAX,
12373 X86::GR32RegisterClass, true);
12374 case X86::ATOMMIN32:
12375 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12376 case X86::ATOMMAX32:
12377 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12378 case X86::ATOMUMIN32:
12379 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12380 case X86::ATOMUMAX32:
12381 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12383 case X86::ATOMAND16:
12384 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12385 X86::AND16ri, X86::MOV16rm,
12387 X86::NOT16r, X86::AX,
12388 X86::GR16RegisterClass);
12389 case X86::ATOMOR16:
12390 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12391 X86::OR16ri, X86::MOV16rm,
12393 X86::NOT16r, X86::AX,
12394 X86::GR16RegisterClass);
12395 case X86::ATOMXOR16:
12396 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12397 X86::XOR16ri, X86::MOV16rm,
12399 X86::NOT16r, X86::AX,
12400 X86::GR16RegisterClass);
12401 case X86::ATOMNAND16:
12402 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12403 X86::AND16ri, X86::MOV16rm,
12405 X86::NOT16r, X86::AX,
12406 X86::GR16RegisterClass, true);
12407 case X86::ATOMMIN16:
12408 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12409 case X86::ATOMMAX16:
12410 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12411 case X86::ATOMUMIN16:
12412 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12413 case X86::ATOMUMAX16:
12414 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12416 case X86::ATOMAND8:
12417 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12418 X86::AND8ri, X86::MOV8rm,
12420 X86::NOT8r, X86::AL,
12421 X86::GR8RegisterClass);
12423 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12424 X86::OR8ri, X86::MOV8rm,
12426 X86::NOT8r, X86::AL,
12427 X86::GR8RegisterClass);
12428 case X86::ATOMXOR8:
12429 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12430 X86::XOR8ri, X86::MOV8rm,
12432 X86::NOT8r, X86::AL,
12433 X86::GR8RegisterClass);
12434 case X86::ATOMNAND8:
12435 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12436 X86::AND8ri, X86::MOV8rm,
12438 X86::NOT8r, X86::AL,
12439 X86::GR8RegisterClass, true);
12440 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12441 // This group is for 64-bit host.
12442 case X86::ATOMAND64:
12443 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12444 X86::AND64ri32, X86::MOV64rm,
12446 X86::NOT64r, X86::RAX,
12447 X86::GR64RegisterClass);
12448 case X86::ATOMOR64:
12449 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12450 X86::OR64ri32, X86::MOV64rm,
12452 X86::NOT64r, X86::RAX,
12453 X86::GR64RegisterClass);
12454 case X86::ATOMXOR64:
12455 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12456 X86::XOR64ri32, X86::MOV64rm,
12458 X86::NOT64r, X86::RAX,
12459 X86::GR64RegisterClass);
12460 case X86::ATOMNAND64:
12461 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12462 X86::AND64ri32, X86::MOV64rm,
12464 X86::NOT64r, X86::RAX,
12465 X86::GR64RegisterClass, true);
12466 case X86::ATOMMIN64:
12467 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12468 case X86::ATOMMAX64:
12469 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12470 case X86::ATOMUMIN64:
12471 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12472 case X86::ATOMUMAX64:
12473 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12475 // This group does 64-bit operations on a 32-bit host.
12476 case X86::ATOMAND6432:
12477 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12478 X86::AND32rr, X86::AND32rr,
12479 X86::AND32ri, X86::AND32ri,
12481 case X86::ATOMOR6432:
12482 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12483 X86::OR32rr, X86::OR32rr,
12484 X86::OR32ri, X86::OR32ri,
12486 case X86::ATOMXOR6432:
12487 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12488 X86::XOR32rr, X86::XOR32rr,
12489 X86::XOR32ri, X86::XOR32ri,
12491 case X86::ATOMNAND6432:
12492 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12493 X86::AND32rr, X86::AND32rr,
12494 X86::AND32ri, X86::AND32ri,
12496 case X86::ATOMADD6432:
12497 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12498 X86::ADD32rr, X86::ADC32rr,
12499 X86::ADD32ri, X86::ADC32ri,
12501 case X86::ATOMSUB6432:
12502 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12503 X86::SUB32rr, X86::SBB32rr,
12504 X86::SUB32ri, X86::SBB32ri,
12506 case X86::ATOMSWAP6432:
12507 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12508 X86::MOV32rr, X86::MOV32rr,
12509 X86::MOV32ri, X86::MOV32ri,
12511 case X86::VASTART_SAVE_XMM_REGS:
12512 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12514 case X86::VAARG_64:
12515 return EmitVAARG64WithCustomInserter(MI, BB);
12519 //===----------------------------------------------------------------------===//
12520 // X86 Optimization Hooks
12521 //===----------------------------------------------------------------------===//
12523 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12527 const SelectionDAG &DAG,
12528 unsigned Depth) const {
12529 unsigned Opc = Op.getOpcode();
12530 assert((Opc >= ISD::BUILTIN_OP_END ||
12531 Opc == ISD::INTRINSIC_WO_CHAIN ||
12532 Opc == ISD::INTRINSIC_W_CHAIN ||
12533 Opc == ISD::INTRINSIC_VOID) &&
12534 "Should use MaskedValueIsZero if you don't know whether Op"
12535 " is a target node!");
12537 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12551 // These nodes' second result is a boolean.
12552 if (Op.getResNo() == 0)
12555 case X86ISD::SETCC:
12556 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12557 Mask.getBitWidth() - 1);
12559 case ISD::INTRINSIC_WO_CHAIN: {
12560 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12561 unsigned NumLoBits = 0;
12564 case Intrinsic::x86_sse_movmsk_ps:
12565 case Intrinsic::x86_avx_movmsk_ps_256:
12566 case Intrinsic::x86_sse2_movmsk_pd:
12567 case Intrinsic::x86_avx_movmsk_pd_256:
12568 case Intrinsic::x86_mmx_pmovmskb:
12569 case Intrinsic::x86_sse2_pmovmskb_128:
12570 case Intrinsic::x86_avx2_pmovmskb: {
12571 // High bits of movmskp{s|d}, pmovmskb are known zero.
12573 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12574 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12575 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12576 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12577 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12578 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12579 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12581 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
12582 Mask.getBitWidth() - NumLoBits);
12591 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12592 unsigned Depth) const {
12593 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12594 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12595 return Op.getValueType().getScalarType().getSizeInBits();
12601 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12602 /// node is a GlobalAddress + offset.
12603 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12604 const GlobalValue* &GA,
12605 int64_t &Offset) const {
12606 if (N->getOpcode() == X86ISD::Wrapper) {
12607 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12608 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12609 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12613 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12616 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12617 /// same as extracting the high 128-bit part of 256-bit vector and then
12618 /// inserting the result into the low part of a new 256-bit vector
12619 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12620 EVT VT = SVOp->getValueType(0);
12621 int NumElems = VT.getVectorNumElements();
12623 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12624 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12625 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12626 SVOp->getMaskElt(j) >= 0)
12632 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12633 /// same as extracting the low 128-bit part of 256-bit vector and then
12634 /// inserting the result into the high part of a new 256-bit vector
12635 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12636 EVT VT = SVOp->getValueType(0);
12637 int NumElems = VT.getVectorNumElements();
12639 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12640 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12641 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12642 SVOp->getMaskElt(j) >= 0)
12648 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12649 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12650 TargetLowering::DAGCombinerInfo &DCI,
12652 DebugLoc dl = N->getDebugLoc();
12653 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12654 SDValue V1 = SVOp->getOperand(0);
12655 SDValue V2 = SVOp->getOperand(1);
12656 EVT VT = SVOp->getValueType(0);
12657 int NumElems = VT.getVectorNumElements();
12659 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12660 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12664 // V UNDEF BUILD_VECTOR UNDEF
12666 // CONCAT_VECTOR CONCAT_VECTOR
12669 // RESULT: V + zero extended
12671 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12672 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12673 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12676 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12679 // To match the shuffle mask, the first half of the mask should
12680 // be exactly the first vector, and all the rest a splat with the
12681 // first element of the second one.
12682 for (int i = 0; i < NumElems/2; ++i)
12683 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12684 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12687 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12688 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12689 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12690 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12692 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12694 Ld->getPointerInfo(),
12695 Ld->getAlignment(),
12696 false/*isVolatile*/, true/*ReadMem*/,
12697 false/*WriteMem*/);
12698 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12701 // Emit a zeroed vector and insert the desired subvector on its
12703 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, HasAVX2, DAG, dl);
12704 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12705 DAG.getConstant(0, MVT::i32), DAG, dl);
12706 return DCI.CombineTo(N, InsV);
12709 //===--------------------------------------------------------------------===//
12710 // Combine some shuffles into subvector extracts and inserts:
12713 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12714 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12715 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12717 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12718 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12719 return DCI.CombineTo(N, InsV);
12722 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12723 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12724 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12725 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12726 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12727 return DCI.CombineTo(N, InsV);
12733 /// PerformShuffleCombine - Performs several different shuffle combines.
12734 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12735 TargetLowering::DAGCombinerInfo &DCI,
12736 const X86Subtarget *Subtarget) {
12737 DebugLoc dl = N->getDebugLoc();
12738 EVT VT = N->getValueType(0);
12740 // Don't create instructions with illegal types after legalize types has run.
12741 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12742 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12745 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12746 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12747 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12748 return PerformShuffleCombine256(N, DAG, DCI, Subtarget->hasAVX2());
12750 // Only handle 128 wide vector from here on.
12751 if (VT.getSizeInBits() != 128)
12754 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12755 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12756 // consecutive, non-overlapping, and in the right order.
12757 SmallVector<SDValue, 16> Elts;
12758 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12759 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12761 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12764 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12765 /// generation and convert it from being a bunch of shuffles and extracts
12766 /// to a simple store and scalar loads to extract the elements.
12767 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12768 const TargetLowering &TLI) {
12769 SDValue InputVector = N->getOperand(0);
12771 // Only operate on vectors of 4 elements, where the alternative shuffling
12772 // gets to be more expensive.
12773 if (InputVector.getValueType() != MVT::v4i32)
12776 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
12777 // single use which is a sign-extend or zero-extend, and all elements are
12779 SmallVector<SDNode *, 4> Uses;
12780 unsigned ExtractedElements = 0;
12781 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
12782 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
12783 if (UI.getUse().getResNo() != InputVector.getResNo())
12786 SDNode *Extract = *UI;
12787 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12790 if (Extract->getValueType(0) != MVT::i32)
12792 if (!Extract->hasOneUse())
12794 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12795 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12797 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12800 // Record which element was extracted.
12801 ExtractedElements |=
12802 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12804 Uses.push_back(Extract);
12807 // If not all the elements were used, this may not be worthwhile.
12808 if (ExtractedElements != 15)
12811 // Ok, we've now decided to do the transformation.
12812 DebugLoc dl = InputVector.getDebugLoc();
12814 // Store the value to a temporary stack slot.
12815 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
12816 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
12817 MachinePointerInfo(), false, false, 0);
12819 // Replace each use (extract) with a load of the appropriate element.
12820 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
12821 UE = Uses.end(); UI != UE; ++UI) {
12822 SDNode *Extract = *UI;
12824 // cOMpute the element's address.
12825 SDValue Idx = Extract->getOperand(1);
12827 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
12828 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
12829 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
12831 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
12832 StackPtr, OffsetVal);
12834 // Load the scalar.
12835 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
12836 ScalarAddr, MachinePointerInfo(),
12837 false, false, false, 0);
12839 // Replace the exact with the load.
12840 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
12843 // The replacement was made in place; don't return anything.
12847 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
12849 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12850 TargetLowering::DAGCombinerInfo &DCI,
12851 const X86Subtarget *Subtarget) {
12852 DebugLoc DL = N->getDebugLoc();
12853 SDValue Cond = N->getOperand(0);
12854 // Get the LHS/RHS of the select.
12855 SDValue LHS = N->getOperand(1);
12856 SDValue RHS = N->getOperand(2);
12857 EVT VT = LHS.getValueType();
12859 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12860 // instructions match the semantics of the common C idiom x<y?x:y but not
12861 // x<=y?x:y, because of how they handle negative zero (which can be
12862 // ignored in unsafe-math mode).
12863 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
12864 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
12865 (Subtarget->hasSSE2() ||
12866 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
12867 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12869 unsigned Opcode = 0;
12870 // Check for x CC y ? x : y.
12871 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12872 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12876 // Converting this to a min would handle NaNs incorrectly, and swapping
12877 // the operands would cause it to handle comparisons between positive
12878 // and negative zero incorrectly.
12879 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12880 if (!DAG.getTarget().Options.UnsafeFPMath &&
12881 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12883 std::swap(LHS, RHS);
12885 Opcode = X86ISD::FMIN;
12888 // Converting this to a min would handle comparisons between positive
12889 // and negative zero incorrectly.
12890 if (!DAG.getTarget().Options.UnsafeFPMath &&
12891 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12893 Opcode = X86ISD::FMIN;
12896 // Converting this to a min would handle both negative zeros and NaNs
12897 // incorrectly, but we can swap the operands to fix both.
12898 std::swap(LHS, RHS);
12902 Opcode = X86ISD::FMIN;
12906 // Converting this to a max would handle comparisons between positive
12907 // and negative zero incorrectly.
12908 if (!DAG.getTarget().Options.UnsafeFPMath &&
12909 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12911 Opcode = X86ISD::FMAX;
12914 // Converting this to a max would handle NaNs incorrectly, and swapping
12915 // the operands would cause it to handle comparisons between positive
12916 // and negative zero incorrectly.
12917 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12918 if (!DAG.getTarget().Options.UnsafeFPMath &&
12919 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12921 std::swap(LHS, RHS);
12923 Opcode = X86ISD::FMAX;
12926 // Converting this to a max would handle both negative zeros and NaNs
12927 // incorrectly, but we can swap the operands to fix both.
12928 std::swap(LHS, RHS);
12932 Opcode = X86ISD::FMAX;
12935 // Check for x CC y ? y : x -- a min/max with reversed arms.
12936 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12937 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12941 // Converting this to a min would handle comparisons between positive
12942 // and negative zero incorrectly, and swapping the operands would
12943 // cause it to handle NaNs incorrectly.
12944 if (!DAG.getTarget().Options.UnsafeFPMath &&
12945 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12946 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12948 std::swap(LHS, RHS);
12950 Opcode = X86ISD::FMIN;
12953 // Converting this to a min would handle NaNs incorrectly.
12954 if (!DAG.getTarget().Options.UnsafeFPMath &&
12955 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
12957 Opcode = X86ISD::FMIN;
12960 // Converting this to a min would handle both negative zeros and NaNs
12961 // incorrectly, but we can swap the operands to fix both.
12962 std::swap(LHS, RHS);
12966 Opcode = X86ISD::FMIN;
12970 // Converting this to a max would handle NaNs incorrectly.
12971 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12973 Opcode = X86ISD::FMAX;
12976 // Converting this to a max would handle comparisons between positive
12977 // and negative zero incorrectly, and swapping the operands would
12978 // cause it to handle NaNs incorrectly.
12979 if (!DAG.getTarget().Options.UnsafeFPMath &&
12980 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
12981 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12983 std::swap(LHS, RHS);
12985 Opcode = X86ISD::FMAX;
12988 // Converting this to a max would handle both negative zeros and NaNs
12989 // incorrectly, but we can swap the operands to fix both.
12990 std::swap(LHS, RHS);
12994 Opcode = X86ISD::FMAX;
13000 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13003 // If this is a select between two integer constants, try to do some
13005 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13006 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13007 // Don't do this for crazy integer types.
13008 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13009 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13010 // so that TrueC (the true value) is larger than FalseC.
13011 bool NeedsCondInvert = false;
13013 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13014 // Efficiently invertible.
13015 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13016 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13017 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13018 NeedsCondInvert = true;
13019 std::swap(TrueC, FalseC);
13022 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13023 if (FalseC->getAPIntValue() == 0 &&
13024 TrueC->getAPIntValue().isPowerOf2()) {
13025 if (NeedsCondInvert) // Invert the condition if needed.
13026 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13027 DAG.getConstant(1, Cond.getValueType()));
13029 // Zero extend the condition if needed.
13030 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13032 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13033 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13034 DAG.getConstant(ShAmt, MVT::i8));
13037 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13038 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13039 if (NeedsCondInvert) // Invert the condition if needed.
13040 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13041 DAG.getConstant(1, Cond.getValueType()));
13043 // Zero extend the condition if needed.
13044 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13045 FalseC->getValueType(0), Cond);
13046 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13047 SDValue(FalseC, 0));
13050 // Optimize cases that will turn into an LEA instruction. This requires
13051 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13052 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13053 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13054 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13056 bool isFastMultiplier = false;
13058 switch ((unsigned char)Diff) {
13060 case 1: // result = add base, cond
13061 case 2: // result = lea base( , cond*2)
13062 case 3: // result = lea base(cond, cond*2)
13063 case 4: // result = lea base( , cond*4)
13064 case 5: // result = lea base(cond, cond*4)
13065 case 8: // result = lea base( , cond*8)
13066 case 9: // result = lea base(cond, cond*8)
13067 isFastMultiplier = true;
13072 if (isFastMultiplier) {
13073 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13074 if (NeedsCondInvert) // Invert the condition if needed.
13075 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13076 DAG.getConstant(1, Cond.getValueType()));
13078 // Zero extend the condition if needed.
13079 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13081 // Scale the condition by the difference.
13083 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13084 DAG.getConstant(Diff, Cond.getValueType()));
13086 // Add the base if non-zero.
13087 if (FalseC->getAPIntValue() != 0)
13088 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13089 SDValue(FalseC, 0));
13096 // Canonicalize max and min:
13097 // (x > y) ? x : y -> (x >= y) ? x : y
13098 // (x < y) ? x : y -> (x <= y) ? x : y
13099 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13100 // the need for an extra compare
13101 // against zero. e.g.
13102 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13104 // testl %edi, %edi
13106 // cmovgl %edi, %eax
13110 // cmovsl %eax, %edi
13111 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13112 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13113 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13114 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13119 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13120 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13121 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13122 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13127 // If we know that this node is legal then we know that it is going to be
13128 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13129 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13130 // to simplify previous instructions.
13131 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13132 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13133 !DCI.isBeforeLegalize() &&
13134 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13135 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13136 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13137 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13139 APInt KnownZero, KnownOne;
13140 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13141 DCI.isBeforeLegalizeOps());
13142 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13143 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13144 DCI.CommitTargetLoweringOpt(TLO);
13150 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13151 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13152 TargetLowering::DAGCombinerInfo &DCI) {
13153 DebugLoc DL = N->getDebugLoc();
13155 // If the flag operand isn't dead, don't touch this CMOV.
13156 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13159 SDValue FalseOp = N->getOperand(0);
13160 SDValue TrueOp = N->getOperand(1);
13161 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13162 SDValue Cond = N->getOperand(3);
13163 if (CC == X86::COND_E || CC == X86::COND_NE) {
13164 switch (Cond.getOpcode()) {
13168 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13169 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13170 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13174 // If this is a select between two integer constants, try to do some
13175 // optimizations. Note that the operands are ordered the opposite of SELECT
13177 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13178 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13179 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13180 // larger than FalseC (the false value).
13181 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13182 CC = X86::GetOppositeBranchCondition(CC);
13183 std::swap(TrueC, FalseC);
13186 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13187 // This is efficient for any integer data type (including i8/i16) and
13189 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13190 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13191 DAG.getConstant(CC, MVT::i8), Cond);
13193 // Zero extend the condition if needed.
13194 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13196 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13197 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13198 DAG.getConstant(ShAmt, MVT::i8));
13199 if (N->getNumValues() == 2) // Dead flag value?
13200 return DCI.CombineTo(N, Cond, SDValue());
13204 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13205 // for any integer data type, including i8/i16.
13206 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13207 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13208 DAG.getConstant(CC, MVT::i8), Cond);
13210 // Zero extend the condition if needed.
13211 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13212 FalseC->getValueType(0), Cond);
13213 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13214 SDValue(FalseC, 0));
13216 if (N->getNumValues() == 2) // Dead flag value?
13217 return DCI.CombineTo(N, Cond, SDValue());
13221 // Optimize cases that will turn into an LEA instruction. This requires
13222 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13223 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13224 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13225 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13227 bool isFastMultiplier = false;
13229 switch ((unsigned char)Diff) {
13231 case 1: // result = add base, cond
13232 case 2: // result = lea base( , cond*2)
13233 case 3: // result = lea base(cond, cond*2)
13234 case 4: // result = lea base( , cond*4)
13235 case 5: // result = lea base(cond, cond*4)
13236 case 8: // result = lea base( , cond*8)
13237 case 9: // result = lea base(cond, cond*8)
13238 isFastMultiplier = true;
13243 if (isFastMultiplier) {
13244 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13245 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13246 DAG.getConstant(CC, MVT::i8), Cond);
13247 // Zero extend the condition if needed.
13248 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13250 // Scale the condition by the difference.
13252 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13253 DAG.getConstant(Diff, Cond.getValueType()));
13255 // Add the base if non-zero.
13256 if (FalseC->getAPIntValue() != 0)
13257 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13258 SDValue(FalseC, 0));
13259 if (N->getNumValues() == 2) // Dead flag value?
13260 return DCI.CombineTo(N, Cond, SDValue());
13270 /// PerformMulCombine - Optimize a single multiply with constant into two
13271 /// in order to implement it with two cheaper instructions, e.g.
13272 /// LEA + SHL, LEA + LEA.
13273 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13274 TargetLowering::DAGCombinerInfo &DCI) {
13275 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13278 EVT VT = N->getValueType(0);
13279 if (VT != MVT::i64)
13282 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13285 uint64_t MulAmt = C->getZExtValue();
13286 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13289 uint64_t MulAmt1 = 0;
13290 uint64_t MulAmt2 = 0;
13291 if ((MulAmt % 9) == 0) {
13293 MulAmt2 = MulAmt / 9;
13294 } else if ((MulAmt % 5) == 0) {
13296 MulAmt2 = MulAmt / 5;
13297 } else if ((MulAmt % 3) == 0) {
13299 MulAmt2 = MulAmt / 3;
13302 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13303 DebugLoc DL = N->getDebugLoc();
13305 if (isPowerOf2_64(MulAmt2) &&
13306 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13307 // If second multiplifer is pow2, issue it first. We want the multiply by
13308 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13310 std::swap(MulAmt1, MulAmt2);
13313 if (isPowerOf2_64(MulAmt1))
13314 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13315 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13317 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13318 DAG.getConstant(MulAmt1, VT));
13320 if (isPowerOf2_64(MulAmt2))
13321 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13322 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13324 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13325 DAG.getConstant(MulAmt2, VT));
13327 // Do not add new nodes to DAG combiner worklist.
13328 DCI.CombineTo(N, NewMul, false);
13333 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13334 SDValue N0 = N->getOperand(0);
13335 SDValue N1 = N->getOperand(1);
13336 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13337 EVT VT = N0.getValueType();
13339 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13340 // since the result of setcc_c is all zero's or all ones.
13341 if (VT.isInteger() && !VT.isVector() &&
13342 N1C && N0.getOpcode() == ISD::AND &&
13343 N0.getOperand(1).getOpcode() == ISD::Constant) {
13344 SDValue N00 = N0.getOperand(0);
13345 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13346 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13347 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13348 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13349 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13350 APInt ShAmt = N1C->getAPIntValue();
13351 Mask = Mask.shl(ShAmt);
13353 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13354 N00, DAG.getConstant(Mask, VT));
13359 // Hardware support for vector shifts is sparse which makes us scalarize the
13360 // vector operations in many cases. Also, on sandybridge ADD is faster than
13362 // (shl V, 1) -> add V,V
13363 if (isSplatVector(N1.getNode())) {
13364 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13365 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13366 // We shift all of the values by one. In many cases we do not have
13367 // hardware support for this operation. This is better expressed as an ADD
13369 if (N1C && (1 == N1C->getZExtValue())) {
13370 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13377 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13379 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13380 const X86Subtarget *Subtarget) {
13381 EVT VT = N->getValueType(0);
13382 if (N->getOpcode() == ISD::SHL) {
13383 SDValue V = PerformSHLCombine(N, DAG);
13384 if (V.getNode()) return V;
13387 // On X86 with SSE2 support, we can transform this to a vector shift if
13388 // all elements are shifted by the same amount. We can't do this in legalize
13389 // because the a constant vector is typically transformed to a constant pool
13390 // so we have no knowledge of the shift amount.
13391 if (!Subtarget->hasSSE2())
13394 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13395 (!Subtarget->hasAVX2() ||
13396 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13399 SDValue ShAmtOp = N->getOperand(1);
13400 EVT EltVT = VT.getVectorElementType();
13401 DebugLoc DL = N->getDebugLoc();
13402 SDValue BaseShAmt = SDValue();
13403 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13404 unsigned NumElts = VT.getVectorNumElements();
13406 for (; i != NumElts; ++i) {
13407 SDValue Arg = ShAmtOp.getOperand(i);
13408 if (Arg.getOpcode() == ISD::UNDEF) continue;
13412 // Handle the case where the build_vector is all undef
13413 // FIXME: Should DAG allow this?
13417 for (; i != NumElts; ++i) {
13418 SDValue Arg = ShAmtOp.getOperand(i);
13419 if (Arg.getOpcode() == ISD::UNDEF) continue;
13420 if (Arg != BaseShAmt) {
13424 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13425 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13426 SDValue InVec = ShAmtOp.getOperand(0);
13427 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13428 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13430 for (; i != NumElts; ++i) {
13431 SDValue Arg = InVec.getOperand(i);
13432 if (Arg.getOpcode() == ISD::UNDEF) continue;
13436 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13437 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13438 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13439 if (C->getZExtValue() == SplatIdx)
13440 BaseShAmt = InVec.getOperand(1);
13443 if (BaseShAmt.getNode() == 0)
13444 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13445 DAG.getIntPtrConstant(0));
13449 // The shift amount is an i32.
13450 if (EltVT.bitsGT(MVT::i32))
13451 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13452 else if (EltVT.bitsLT(MVT::i32))
13453 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13455 // The shift amount is identical so we can do a vector shift.
13456 SDValue ValOp = N->getOperand(0);
13457 switch (N->getOpcode()) {
13459 llvm_unreachable("Unknown shift opcode!");
13461 switch (VT.getSimpleVT().SimpleTy) {
13462 default: return SDValue();
13469 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
13472 switch (VT.getSimpleVT().SimpleTy) {
13473 default: return SDValue();
13478 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
13481 switch (VT.getSimpleVT().SimpleTy) {
13482 default: return SDValue();
13489 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
13495 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13496 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13497 // and friends. Likewise for OR -> CMPNEQSS.
13498 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13499 TargetLowering::DAGCombinerInfo &DCI,
13500 const X86Subtarget *Subtarget) {
13503 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13504 // we're requiring SSE2 for both.
13505 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13506 SDValue N0 = N->getOperand(0);
13507 SDValue N1 = N->getOperand(1);
13508 SDValue CMP0 = N0->getOperand(1);
13509 SDValue CMP1 = N1->getOperand(1);
13510 DebugLoc DL = N->getDebugLoc();
13512 // The SETCCs should both refer to the same CMP.
13513 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13516 SDValue CMP00 = CMP0->getOperand(0);
13517 SDValue CMP01 = CMP0->getOperand(1);
13518 EVT VT = CMP00.getValueType();
13520 if (VT == MVT::f32 || VT == MVT::f64) {
13521 bool ExpectingFlags = false;
13522 // Check for any users that want flags:
13523 for (SDNode::use_iterator UI = N->use_begin(),
13525 !ExpectingFlags && UI != UE; ++UI)
13526 switch (UI->getOpcode()) {
13531 ExpectingFlags = true;
13533 case ISD::CopyToReg:
13534 case ISD::SIGN_EXTEND:
13535 case ISD::ZERO_EXTEND:
13536 case ISD::ANY_EXTEND:
13540 if (!ExpectingFlags) {
13541 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13542 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13544 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13545 X86::CondCode tmp = cc0;
13550 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13551 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13552 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13553 X86ISD::NodeType NTOperator = is64BitFP ?
13554 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13555 // FIXME: need symbolic constants for these magic numbers.
13556 // See X86ATTInstPrinter.cpp:printSSECC().
13557 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13558 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13559 DAG.getConstant(x86cc, MVT::i8));
13560 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13562 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13563 DAG.getConstant(1, MVT::i32));
13564 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13565 return OneBitOfTruth;
13573 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13574 /// so it can be folded inside ANDNP.
13575 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13576 EVT VT = N->getValueType(0);
13578 // Match direct AllOnes for 128 and 256-bit vectors
13579 if (ISD::isBuildVectorAllOnes(N))
13582 // Look through a bit convert.
13583 if (N->getOpcode() == ISD::BITCAST)
13584 N = N->getOperand(0).getNode();
13586 // Sometimes the operand may come from a insert_subvector building a 256-bit
13588 if (VT.getSizeInBits() == 256 &&
13589 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13590 SDValue V1 = N->getOperand(0);
13591 SDValue V2 = N->getOperand(1);
13593 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13594 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13595 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13596 ISD::isBuildVectorAllOnes(V2.getNode()))
13603 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13604 TargetLowering::DAGCombinerInfo &DCI,
13605 const X86Subtarget *Subtarget) {
13606 if (DCI.isBeforeLegalizeOps())
13609 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13613 EVT VT = N->getValueType(0);
13615 // Create ANDN, BLSI, and BLSR instructions
13616 // BLSI is X & (-X)
13617 // BLSR is X & (X-1)
13618 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
13619 SDValue N0 = N->getOperand(0);
13620 SDValue N1 = N->getOperand(1);
13621 DebugLoc DL = N->getDebugLoc();
13623 // Check LHS for not
13624 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
13625 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
13626 // Check RHS for not
13627 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
13628 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
13630 // Check LHS for neg
13631 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
13632 isZero(N0.getOperand(0)))
13633 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
13635 // Check RHS for neg
13636 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
13637 isZero(N1.getOperand(0)))
13638 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
13640 // Check LHS for X-1
13641 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13642 isAllOnes(N0.getOperand(1)))
13643 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
13645 // Check RHS for X-1
13646 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13647 isAllOnes(N1.getOperand(1)))
13648 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
13653 // Want to form ANDNP nodes:
13654 // 1) In the hopes of then easily combining them with OR and AND nodes
13655 // to form PBLEND/PSIGN.
13656 // 2) To match ANDN packed intrinsics
13657 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13660 SDValue N0 = N->getOperand(0);
13661 SDValue N1 = N->getOperand(1);
13662 DebugLoc DL = N->getDebugLoc();
13664 // Check LHS for vnot
13665 if (N0.getOpcode() == ISD::XOR &&
13666 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13667 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13668 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13670 // Check RHS for vnot
13671 if (N1.getOpcode() == ISD::XOR &&
13672 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13673 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13674 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13679 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13680 TargetLowering::DAGCombinerInfo &DCI,
13681 const X86Subtarget *Subtarget) {
13682 if (DCI.isBeforeLegalizeOps())
13685 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13689 EVT VT = N->getValueType(0);
13691 SDValue N0 = N->getOperand(0);
13692 SDValue N1 = N->getOperand(1);
13694 // look for psign/blend
13695 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
13696 if (!Subtarget->hasSSSE3() ||
13697 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
13700 // Canonicalize pandn to RHS
13701 if (N0.getOpcode() == X86ISD::ANDNP)
13703 // or (and (m, y), (pandn m, x))
13704 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13705 SDValue Mask = N1.getOperand(0);
13706 SDValue X = N1.getOperand(1);
13708 if (N0.getOperand(0) == Mask)
13709 Y = N0.getOperand(1);
13710 if (N0.getOperand(1) == Mask)
13711 Y = N0.getOperand(0);
13713 // Check to see if the mask appeared in both the AND and ANDNP and
13717 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13718 if (Mask.getOpcode() != ISD::BITCAST ||
13719 X.getOpcode() != ISD::BITCAST ||
13720 Y.getOpcode() != ISD::BITCAST)
13723 // Look through mask bitcast.
13724 Mask = Mask.getOperand(0);
13725 EVT MaskVT = Mask.getValueType();
13727 // Validate that the Mask operand is a vector sra node.
13728 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13729 // there is no psrai.b
13730 if (Mask.getOpcode() != X86ISD::VSRAI)
13733 // Check that the SRA is all signbits.
13734 SDValue SraC = Mask.getOperand(1);
13735 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13736 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13737 if ((SraAmt + 1) != EltBits)
13740 DebugLoc DL = N->getDebugLoc();
13742 // Now we know we at least have a plendvb with the mask val. See if
13743 // we can form a psignb/w/d.
13744 // psign = x.type == y.type == mask.type && y = sub(0, x);
13745 X = X.getOperand(0);
13746 Y = Y.getOperand(0);
13747 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13748 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13749 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
13750 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
13751 "Unsupported VT for PSIGN");
13752 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
13753 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
13755 // PBLENDVB only available on SSE 4.1
13756 if (!Subtarget->hasSSE41())
13759 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
13761 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
13762 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
13763 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
13764 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
13765 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
13769 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
13772 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
13773 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
13775 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
13777 if (!N0.hasOneUse() || !N1.hasOneUse())
13780 SDValue ShAmt0 = N0.getOperand(1);
13781 if (ShAmt0.getValueType() != MVT::i8)
13783 SDValue ShAmt1 = N1.getOperand(1);
13784 if (ShAmt1.getValueType() != MVT::i8)
13786 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
13787 ShAmt0 = ShAmt0.getOperand(0);
13788 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
13789 ShAmt1 = ShAmt1.getOperand(0);
13791 DebugLoc DL = N->getDebugLoc();
13792 unsigned Opc = X86ISD::SHLD;
13793 SDValue Op0 = N0.getOperand(0);
13794 SDValue Op1 = N1.getOperand(0);
13795 if (ShAmt0.getOpcode() == ISD::SUB) {
13796 Opc = X86ISD::SHRD;
13797 std::swap(Op0, Op1);
13798 std::swap(ShAmt0, ShAmt1);
13801 unsigned Bits = VT.getSizeInBits();
13802 if (ShAmt1.getOpcode() == ISD::SUB) {
13803 SDValue Sum = ShAmt1.getOperand(0);
13804 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
13805 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
13806 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
13807 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
13808 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
13809 return DAG.getNode(Opc, DL, VT,
13811 DAG.getNode(ISD::TRUNCATE, DL,
13814 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
13815 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
13817 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
13818 return DAG.getNode(Opc, DL, VT,
13819 N0.getOperand(0), N1.getOperand(0),
13820 DAG.getNode(ISD::TRUNCATE, DL,
13827 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
13828 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
13829 TargetLowering::DAGCombinerInfo &DCI,
13830 const X86Subtarget *Subtarget) {
13831 if (DCI.isBeforeLegalizeOps())
13834 EVT VT = N->getValueType(0);
13836 if (VT != MVT::i32 && VT != MVT::i64)
13839 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
13841 // Create BLSMSK instructions by finding X ^ (X-1)
13842 SDValue N0 = N->getOperand(0);
13843 SDValue N1 = N->getOperand(1);
13844 DebugLoc DL = N->getDebugLoc();
13846 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13847 isAllOnes(N0.getOperand(1)))
13848 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
13850 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13851 isAllOnes(N1.getOperand(1)))
13852 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
13857 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
13858 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
13859 const X86Subtarget *Subtarget) {
13860 LoadSDNode *Ld = cast<LoadSDNode>(N);
13861 EVT RegVT = Ld->getValueType(0);
13862 EVT MemVT = Ld->getMemoryVT();
13863 DebugLoc dl = Ld->getDebugLoc();
13864 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13866 ISD::LoadExtType Ext = Ld->getExtensionType();
13868 // If this is a vector EXT Load then attempt to optimize it using a
13869 // shuffle. We need SSE4 for the shuffles.
13870 // TODO: It is possible to support ZExt by zeroing the undef values
13871 // during the shuffle phase or after the shuffle.
13872 if (RegVT.isVector() && RegVT.isInteger() &&
13873 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
13874 assert(MemVT != RegVT && "Cannot extend to the same type");
13875 assert(MemVT.isVector() && "Must load a vector from memory");
13877 unsigned NumElems = RegVT.getVectorNumElements();
13878 unsigned RegSz = RegVT.getSizeInBits();
13879 unsigned MemSz = MemVT.getSizeInBits();
13880 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13881 // All sizes must be a power of two
13882 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
13884 // Attempt to load the original value using a single load op.
13885 // Find a scalar type which is equal to the loaded word size.
13886 MVT SclrLoadTy = MVT::i8;
13887 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13888 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13889 MVT Tp = (MVT::SimpleValueType)tp;
13890 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
13896 // Proceed if a load word is found.
13897 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
13899 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
13900 RegSz/SclrLoadTy.getSizeInBits());
13902 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13903 RegSz/MemVT.getScalarType().getSizeInBits());
13904 // Can't shuffle using an illegal type.
13905 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13907 // Perform a single load.
13908 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
13910 Ld->getPointerInfo(), Ld->isVolatile(),
13911 Ld->isNonTemporal(), Ld->isInvariant(),
13912 Ld->getAlignment());
13914 // Insert the word loaded into a vector.
13915 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13916 LoadUnitVecVT, ScalarLoad);
13918 // Bitcast the loaded value to a vector of the original element type, in
13919 // the size of the target vector type.
13920 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
13922 unsigned SizeRatio = RegSz/MemSz;
13924 // Redistribute the loaded elements into the different locations.
13925 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13926 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
13928 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13929 DAG.getUNDEF(SlicedVec.getValueType()),
13930 ShuffleVec.data());
13932 // Bitcast to the requested type.
13933 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13934 // Replace the original load with the new sequence
13935 // and return the new chain.
13936 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
13937 return SDValue(ScalarLoad.getNode(), 1);
13943 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
13944 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
13945 const X86Subtarget *Subtarget) {
13946 StoreSDNode *St = cast<StoreSDNode>(N);
13947 EVT VT = St->getValue().getValueType();
13948 EVT StVT = St->getMemoryVT();
13949 DebugLoc dl = St->getDebugLoc();
13950 SDValue StoredVal = St->getOperand(1);
13951 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13953 // If we are saving a concatenation of two XMM registers, perform two stores.
13954 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
13955 // 128-bit ones. If in the future the cost becomes only one memory access the
13956 // first version would be better.
13957 if (VT.getSizeInBits() == 256 &&
13958 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
13959 StoredVal.getNumOperands() == 2) {
13961 SDValue Value0 = StoredVal.getOperand(0);
13962 SDValue Value1 = StoredVal.getOperand(1);
13964 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
13965 SDValue Ptr0 = St->getBasePtr();
13966 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
13968 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
13969 St->getPointerInfo(), St->isVolatile(),
13970 St->isNonTemporal(), St->getAlignment());
13971 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
13972 St->getPointerInfo(), St->isVolatile(),
13973 St->isNonTemporal(), St->getAlignment());
13974 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
13977 // Optimize trunc store (of multiple scalars) to shuffle and store.
13978 // First, pack all of the elements in one place. Next, store to memory
13979 // in fewer chunks.
13980 if (St->isTruncatingStore() && VT.isVector()) {
13981 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13982 unsigned NumElems = VT.getVectorNumElements();
13983 assert(StVT != VT && "Cannot truncate to the same type");
13984 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
13985 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
13987 // From, To sizes and ElemCount must be pow of two
13988 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
13989 // We are going to use the original vector elt for storing.
13990 // Accumulated smaller vector elements must be a multiple of the store size.
13991 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
13993 unsigned SizeRatio = FromSz / ToSz;
13995 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
13997 // Create a type on which we perform the shuffle
13998 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
13999 StVT.getScalarType(), NumElems*SizeRatio);
14001 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14003 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14004 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14005 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14007 // Can't shuffle using an illegal type
14008 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14010 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14011 DAG.getUNDEF(WideVec.getValueType()),
14012 ShuffleVec.data());
14013 // At this point all of the data is stored at the bottom of the
14014 // register. We now need to save it to mem.
14016 // Find the largest store unit
14017 MVT StoreType = MVT::i8;
14018 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14019 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14020 MVT Tp = (MVT::SimpleValueType)tp;
14021 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14025 // Bitcast the original vector into a vector of store-size units
14026 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14027 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14028 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14029 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14030 SmallVector<SDValue, 8> Chains;
14031 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14032 TLI.getPointerTy());
14033 SDValue Ptr = St->getBasePtr();
14035 // Perform one or more big stores into memory.
14036 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14037 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14038 StoreType, ShuffWide,
14039 DAG.getIntPtrConstant(i));
14040 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14041 St->getPointerInfo(), St->isVolatile(),
14042 St->isNonTemporal(), St->getAlignment());
14043 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14044 Chains.push_back(Ch);
14047 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14052 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14053 // the FP state in cases where an emms may be missing.
14054 // A preferable solution to the general problem is to figure out the right
14055 // places to insert EMMS. This qualifies as a quick hack.
14057 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14058 if (VT.getSizeInBits() != 64)
14061 const Function *F = DAG.getMachineFunction().getFunction();
14062 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14063 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14064 && Subtarget->hasSSE2();
14065 if ((VT.isVector() ||
14066 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14067 isa<LoadSDNode>(St->getValue()) &&
14068 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14069 St->getChain().hasOneUse() && !St->isVolatile()) {
14070 SDNode* LdVal = St->getValue().getNode();
14071 LoadSDNode *Ld = 0;
14072 int TokenFactorIndex = -1;
14073 SmallVector<SDValue, 8> Ops;
14074 SDNode* ChainVal = St->getChain().getNode();
14075 // Must be a store of a load. We currently handle two cases: the load
14076 // is a direct child, and it's under an intervening TokenFactor. It is
14077 // possible to dig deeper under nested TokenFactors.
14078 if (ChainVal == LdVal)
14079 Ld = cast<LoadSDNode>(St->getChain());
14080 else if (St->getValue().hasOneUse() &&
14081 ChainVal->getOpcode() == ISD::TokenFactor) {
14082 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
14083 if (ChainVal->getOperand(i).getNode() == LdVal) {
14084 TokenFactorIndex = i;
14085 Ld = cast<LoadSDNode>(St->getValue());
14087 Ops.push_back(ChainVal->getOperand(i));
14091 if (!Ld || !ISD::isNormalLoad(Ld))
14094 // If this is not the MMX case, i.e. we are just turning i64 load/store
14095 // into f64 load/store, avoid the transformation if there are multiple
14096 // uses of the loaded value.
14097 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14100 DebugLoc LdDL = Ld->getDebugLoc();
14101 DebugLoc StDL = N->getDebugLoc();
14102 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14103 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14105 if (Subtarget->is64Bit() || F64IsLegal) {
14106 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14107 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14108 Ld->getPointerInfo(), Ld->isVolatile(),
14109 Ld->isNonTemporal(), Ld->isInvariant(),
14110 Ld->getAlignment());
14111 SDValue NewChain = NewLd.getValue(1);
14112 if (TokenFactorIndex != -1) {
14113 Ops.push_back(NewChain);
14114 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14117 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14118 St->getPointerInfo(),
14119 St->isVolatile(), St->isNonTemporal(),
14120 St->getAlignment());
14123 // Otherwise, lower to two pairs of 32-bit loads / stores.
14124 SDValue LoAddr = Ld->getBasePtr();
14125 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14126 DAG.getConstant(4, MVT::i32));
14128 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14129 Ld->getPointerInfo(),
14130 Ld->isVolatile(), Ld->isNonTemporal(),
14131 Ld->isInvariant(), Ld->getAlignment());
14132 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14133 Ld->getPointerInfo().getWithOffset(4),
14134 Ld->isVolatile(), Ld->isNonTemporal(),
14136 MinAlign(Ld->getAlignment(), 4));
14138 SDValue NewChain = LoLd.getValue(1);
14139 if (TokenFactorIndex != -1) {
14140 Ops.push_back(LoLd);
14141 Ops.push_back(HiLd);
14142 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14146 LoAddr = St->getBasePtr();
14147 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14148 DAG.getConstant(4, MVT::i32));
14150 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14151 St->getPointerInfo(),
14152 St->isVolatile(), St->isNonTemporal(),
14153 St->getAlignment());
14154 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14155 St->getPointerInfo().getWithOffset(4),
14157 St->isNonTemporal(),
14158 MinAlign(St->getAlignment(), 4));
14159 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14164 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14165 /// and return the operands for the horizontal operation in LHS and RHS. A
14166 /// horizontal operation performs the binary operation on successive elements
14167 /// of its first operand, then on successive elements of its second operand,
14168 /// returning the resulting values in a vector. For example, if
14169 /// A = < float a0, float a1, float a2, float a3 >
14171 /// B = < float b0, float b1, float b2, float b3 >
14172 /// then the result of doing a horizontal operation on A and B is
14173 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14174 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14175 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14176 /// set to A, RHS to B, and the routine returns 'true'.
14177 /// Note that the binary operation should have the property that if one of the
14178 /// operands is UNDEF then the result is UNDEF.
14179 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14180 // Look for the following pattern: if
14181 // A = < float a0, float a1, float a2, float a3 >
14182 // B = < float b0, float b1, float b2, float b3 >
14184 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14185 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14186 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14187 // which is A horizontal-op B.
14189 // At least one of the operands should be a vector shuffle.
14190 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14191 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14194 EVT VT = LHS.getValueType();
14196 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14197 "Unsupported vector type for horizontal add/sub");
14199 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14200 // operate independently on 128-bit lanes.
14201 unsigned NumElts = VT.getVectorNumElements();
14202 unsigned NumLanes = VT.getSizeInBits()/128;
14203 unsigned NumLaneElts = NumElts / NumLanes;
14204 assert((NumLaneElts % 2 == 0) &&
14205 "Vector type should have an even number of elements in each lane");
14206 unsigned HalfLaneElts = NumLaneElts/2;
14208 // View LHS in the form
14209 // LHS = VECTOR_SHUFFLE A, B, LMask
14210 // If LHS is not a shuffle then pretend it is the shuffle
14211 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14212 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14215 SmallVector<int, 16> LMask(NumElts);
14216 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14217 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14218 A = LHS.getOperand(0);
14219 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14220 B = LHS.getOperand(1);
14221 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14222 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14224 if (LHS.getOpcode() != ISD::UNDEF)
14226 for (unsigned i = 0; i != NumElts; ++i)
14230 // Likewise, view RHS in the form
14231 // RHS = VECTOR_SHUFFLE C, D, RMask
14233 SmallVector<int, 16> RMask(NumElts);
14234 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14235 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14236 C = RHS.getOperand(0);
14237 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14238 D = RHS.getOperand(1);
14239 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14240 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14242 if (RHS.getOpcode() != ISD::UNDEF)
14244 for (unsigned i = 0; i != NumElts; ++i)
14248 // Check that the shuffles are both shuffling the same vectors.
14249 if (!(A == C && B == D) && !(A == D && B == C))
14252 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14253 if (!A.getNode() && !B.getNode())
14256 // If A and B occur in reverse order in RHS, then "swap" them (which means
14257 // rewriting the mask).
14259 CommuteVectorShuffleMask(RMask, NumElts);
14261 // At this point LHS and RHS are equivalent to
14262 // LHS = VECTOR_SHUFFLE A, B, LMask
14263 // RHS = VECTOR_SHUFFLE A, B, RMask
14264 // Check that the masks correspond to performing a horizontal operation.
14265 for (unsigned i = 0; i != NumElts; ++i) {
14266 int LIdx = LMask[i], RIdx = RMask[i];
14268 // Ignore any UNDEF components.
14269 if (LIdx < 0 || RIdx < 0 ||
14270 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14271 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14274 // Check that successive elements are being operated on. If not, this is
14275 // not a horizontal operation.
14276 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14277 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14278 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14279 if (!(LIdx == Index && RIdx == Index + 1) &&
14280 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14284 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14285 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14289 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14290 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14291 const X86Subtarget *Subtarget) {
14292 EVT VT = N->getValueType(0);
14293 SDValue LHS = N->getOperand(0);
14294 SDValue RHS = N->getOperand(1);
14296 // Try to synthesize horizontal adds from adds of shuffles.
14297 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14298 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14299 isHorizontalBinOp(LHS, RHS, true))
14300 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14304 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14305 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14306 const X86Subtarget *Subtarget) {
14307 EVT VT = N->getValueType(0);
14308 SDValue LHS = N->getOperand(0);
14309 SDValue RHS = N->getOperand(1);
14311 // Try to synthesize horizontal subs from subs of shuffles.
14312 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14313 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14314 isHorizontalBinOp(LHS, RHS, false))
14315 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14319 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14320 /// X86ISD::FXOR nodes.
14321 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14322 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14323 // F[X]OR(0.0, x) -> x
14324 // F[X]OR(x, 0.0) -> x
14325 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14326 if (C->getValueAPF().isPosZero())
14327 return N->getOperand(1);
14328 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14329 if (C->getValueAPF().isPosZero())
14330 return N->getOperand(0);
14334 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14335 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14336 // FAND(0.0, x) -> 0.0
14337 // FAND(x, 0.0) -> 0.0
14338 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14339 if (C->getValueAPF().isPosZero())
14340 return N->getOperand(0);
14341 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14342 if (C->getValueAPF().isPosZero())
14343 return N->getOperand(1);
14347 static SDValue PerformBTCombine(SDNode *N,
14349 TargetLowering::DAGCombinerInfo &DCI) {
14350 // BT ignores high bits in the bit index operand.
14351 SDValue Op1 = N->getOperand(1);
14352 if (Op1.hasOneUse()) {
14353 unsigned BitWidth = Op1.getValueSizeInBits();
14354 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14355 APInt KnownZero, KnownOne;
14356 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14357 !DCI.isBeforeLegalizeOps());
14358 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14359 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14360 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14361 DCI.CommitTargetLoweringOpt(TLO);
14366 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14367 SDValue Op = N->getOperand(0);
14368 if (Op.getOpcode() == ISD::BITCAST)
14369 Op = Op.getOperand(0);
14370 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14371 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14372 VT.getVectorElementType().getSizeInBits() ==
14373 OpVT.getVectorElementType().getSizeInBits()) {
14374 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14379 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
14380 const X86Subtarget *Subtarget) {
14381 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14382 // (and (i32 x86isd::setcc_carry), 1)
14383 // This eliminates the zext. This transformation is necessary because
14384 // ISD::SETCC is always legalized to i8.
14385 DebugLoc dl = N->getDebugLoc();
14386 SDValue N0 = N->getOperand(0);
14387 EVT VT = N->getValueType(0);
14388 EVT OpVT = N0.getValueType();
14390 if (N0.getOpcode() == ISD::AND &&
14392 N0.getOperand(0).hasOneUse()) {
14393 SDValue N00 = N0.getOperand(0);
14394 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14396 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14397 if (!C || C->getZExtValue() != 1)
14399 return DAG.getNode(ISD::AND, dl, VT,
14400 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14401 N00.getOperand(0), N00.getOperand(1)),
14402 DAG.getConstant(1, VT));
14404 // Optimize vectors in AVX mode:
14407 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14408 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14409 // Concat upper and lower parts.
14412 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14413 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14414 // Concat upper and lower parts.
14416 if (Subtarget->hasAVX()) {
14418 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
14419 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
14421 SDValue ZeroVec = getZeroVector(OpVT, Subtarget->hasSSE2(), Subtarget->hasAVX2(),
14423 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec, DAG);
14424 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec, DAG);
14426 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
14427 VT.getVectorNumElements()/2);
14429 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14430 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14432 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14440 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14441 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14442 unsigned X86CC = N->getConstantOperandVal(0);
14443 SDValue EFLAG = N->getOperand(1);
14444 DebugLoc DL = N->getDebugLoc();
14446 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14447 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14449 if (X86CC == X86::COND_B)
14450 return DAG.getNode(ISD::AND, DL, MVT::i8,
14451 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14452 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14453 DAG.getConstant(1, MVT::i8));
14458 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14459 const X86TargetLowering *XTLI) {
14460 SDValue Op0 = N->getOperand(0);
14461 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14462 // a 32-bit target where SSE doesn't support i64->FP operations.
14463 if (Op0.getOpcode() == ISD::LOAD) {
14464 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
14465 EVT VT = Ld->getValueType(0);
14466 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
14467 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14468 !XTLI->getSubtarget()->is64Bit() &&
14469 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14470 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
14471 Ld->getChain(), Op0, DAG);
14472 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
14479 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
14480 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
14481 X86TargetLowering::DAGCombinerInfo &DCI) {
14482 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
14483 // the result is either zero or one (depending on the input carry bit).
14484 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
14485 if (X86::isZeroNode(N->getOperand(0)) &&
14486 X86::isZeroNode(N->getOperand(1)) &&
14487 // We don't have a good way to replace an EFLAGS use, so only do this when
14489 SDValue(N, 1).use_empty()) {
14490 DebugLoc DL = N->getDebugLoc();
14491 EVT VT = N->getValueType(0);
14492 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
14493 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
14494 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
14495 DAG.getConstant(X86::COND_B,MVT::i8),
14497 DAG.getConstant(1, VT));
14498 return DCI.CombineTo(N, Res1, CarryOut);
14504 // fold (add Y, (sete X, 0)) -> adc 0, Y
14505 // (add Y, (setne X, 0)) -> sbb -1, Y
14506 // (sub (sete X, 0), Y) -> sbb 0, Y
14507 // (sub (setne X, 0), Y) -> adc -1, Y
14508 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
14509 DebugLoc DL = N->getDebugLoc();
14511 // Look through ZExts.
14512 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
14513 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
14516 SDValue SetCC = Ext.getOperand(0);
14517 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
14520 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
14521 if (CC != X86::COND_E && CC != X86::COND_NE)
14524 SDValue Cmp = SetCC.getOperand(1);
14525 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
14526 !X86::isZeroNode(Cmp.getOperand(1)) ||
14527 !Cmp.getOperand(0).getValueType().isInteger())
14530 SDValue CmpOp0 = Cmp.getOperand(0);
14531 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
14532 DAG.getConstant(1, CmpOp0.getValueType()));
14534 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
14535 if (CC == X86::COND_NE)
14536 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
14537 DL, OtherVal.getValueType(), OtherVal,
14538 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
14539 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
14540 DL, OtherVal.getValueType(), OtherVal,
14541 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
14544 /// PerformADDCombine - Do target-specific dag combines on integer adds.
14545 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
14546 const X86Subtarget *Subtarget) {
14547 EVT VT = N->getValueType(0);
14548 SDValue Op0 = N->getOperand(0);
14549 SDValue Op1 = N->getOperand(1);
14551 // Try to synthesize horizontal adds from adds of shuffles.
14552 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14553 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14554 isHorizontalBinOp(Op0, Op1, true))
14555 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
14557 return OptimizeConditionalInDecrement(N, DAG);
14560 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
14561 const X86Subtarget *Subtarget) {
14562 SDValue Op0 = N->getOperand(0);
14563 SDValue Op1 = N->getOperand(1);
14565 // X86 can't encode an immediate LHS of a sub. See if we can push the
14566 // negation into a preceding instruction.
14567 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
14568 // If the RHS of the sub is a XOR with one use and a constant, invert the
14569 // immediate. Then add one to the LHS of the sub so we can turn
14570 // X-Y -> X+~Y+1, saving one register.
14571 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
14572 isa<ConstantSDNode>(Op1.getOperand(1))) {
14573 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
14574 EVT VT = Op0.getValueType();
14575 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
14577 DAG.getConstant(~XorC, VT));
14578 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
14579 DAG.getConstant(C->getAPIntValue()+1, VT));
14583 // Try to synthesize horizontal adds from adds of shuffles.
14584 EVT VT = N->getValueType(0);
14585 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14586 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14587 isHorizontalBinOp(Op0, Op1, true))
14588 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
14590 return OptimizeConditionalInDecrement(N, DAG);
14593 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
14594 DAGCombinerInfo &DCI) const {
14595 SelectionDAG &DAG = DCI.DAG;
14596 switch (N->getOpcode()) {
14598 case ISD::EXTRACT_VECTOR_ELT:
14599 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
14601 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
14602 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
14603 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
14604 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
14605 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
14606 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
14609 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
14610 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
14611 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
14612 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
14613 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
14614 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
14615 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
14616 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
14617 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
14619 case X86ISD::FOR: return PerformFORCombine(N, DAG);
14620 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
14621 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
14622 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
14623 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);
14624 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
14625 case X86ISD::SHUFP: // Handle all target specific shuffles
14626 case X86ISD::PALIGN:
14627 case X86ISD::UNPCKH:
14628 case X86ISD::UNPCKL:
14629 case X86ISD::MOVHLPS:
14630 case X86ISD::MOVLHPS:
14631 case X86ISD::PSHUFD:
14632 case X86ISD::PSHUFHW:
14633 case X86ISD::PSHUFLW:
14634 case X86ISD::MOVSS:
14635 case X86ISD::MOVSD:
14636 case X86ISD::VPERMILP:
14637 case X86ISD::VPERM2X128:
14638 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
14644 /// isTypeDesirableForOp - Return true if the target has native support for
14645 /// the specified value type and it is 'desirable' to use the type for the
14646 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
14647 /// instruction encodings are longer and some i16 instructions are slow.
14648 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
14649 if (!isTypeLegal(VT))
14651 if (VT != MVT::i16)
14658 case ISD::SIGN_EXTEND:
14659 case ISD::ZERO_EXTEND:
14660 case ISD::ANY_EXTEND:
14673 /// IsDesirableToPromoteOp - This method query the target whether it is
14674 /// beneficial for dag combiner to promote the specified node. If true, it
14675 /// should return the desired promotion type by reference.
14676 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
14677 EVT VT = Op.getValueType();
14678 if (VT != MVT::i16)
14681 bool Promote = false;
14682 bool Commute = false;
14683 switch (Op.getOpcode()) {
14686 LoadSDNode *LD = cast<LoadSDNode>(Op);
14687 // If the non-extending load has a single use and it's not live out, then it
14688 // might be folded.
14689 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
14690 Op.hasOneUse()*/) {
14691 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14692 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
14693 // The only case where we'd want to promote LOAD (rather then it being
14694 // promoted as an operand is when it's only use is liveout.
14695 if (UI->getOpcode() != ISD::CopyToReg)
14702 case ISD::SIGN_EXTEND:
14703 case ISD::ZERO_EXTEND:
14704 case ISD::ANY_EXTEND:
14709 SDValue N0 = Op.getOperand(0);
14710 // Look out for (store (shl (load), x)).
14711 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
14724 SDValue N0 = Op.getOperand(0);
14725 SDValue N1 = Op.getOperand(1);
14726 if (!Commute && MayFoldLoad(N1))
14728 // Avoid disabling potential load folding opportunities.
14729 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
14731 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
14741 //===----------------------------------------------------------------------===//
14742 // X86 Inline Assembly Support
14743 //===----------------------------------------------------------------------===//
14746 // Helper to match a string separated by whitespace.
14747 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
14748 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
14750 for (unsigned i = 0, e = args.size(); i != e; ++i) {
14751 StringRef piece(*args[i]);
14752 if (!s.startswith(piece)) // Check if the piece matches.
14755 s = s.substr(piece.size());
14756 StringRef::size_type pos = s.find_first_not_of(" \t");
14757 if (pos == 0) // We matched a prefix.
14765 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
14768 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
14769 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
14771 std::string AsmStr = IA->getAsmString();
14773 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14774 if (!Ty || Ty->getBitWidth() % 16 != 0)
14777 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
14778 SmallVector<StringRef, 4> AsmPieces;
14779 SplitString(AsmStr, AsmPieces, ";\n");
14781 switch (AsmPieces.size()) {
14782 default: return false;
14784 // FIXME: this should verify that we are targeting a 486 or better. If not,
14785 // we will turn this bswap into something that will be lowered to logical
14786 // ops instead of emitting the bswap asm. For now, we don't support 486 or
14787 // lower so don't worry about this.
14789 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
14790 matchAsm(AsmPieces[0], "bswapl", "$0") ||
14791 matchAsm(AsmPieces[0], "bswapq", "$0") ||
14792 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
14793 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
14794 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
14795 // No need to check constraints, nothing other than the equivalent of
14796 // "=r,0" would be valid here.
14797 return IntrinsicLowering::LowerToByteSwap(CI);
14800 // rorw $$8, ${0:w} --> llvm.bswap.i16
14801 if (CI->getType()->isIntegerTy(16) &&
14802 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
14803 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
14804 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
14806 const std::string &ConstraintsStr = IA->getConstraintString();
14807 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14808 std::sort(AsmPieces.begin(), AsmPieces.end());
14809 if (AsmPieces.size() == 4 &&
14810 AsmPieces[0] == "~{cc}" &&
14811 AsmPieces[1] == "~{dirflag}" &&
14812 AsmPieces[2] == "~{flags}" &&
14813 AsmPieces[3] == "~{fpsr}")
14814 return IntrinsicLowering::LowerToByteSwap(CI);
14818 if (CI->getType()->isIntegerTy(32) &&
14819 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
14820 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
14821 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
14822 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
14824 const std::string &ConstraintsStr = IA->getConstraintString();
14825 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14826 std::sort(AsmPieces.begin(), AsmPieces.end());
14827 if (AsmPieces.size() == 4 &&
14828 AsmPieces[0] == "~{cc}" &&
14829 AsmPieces[1] == "~{dirflag}" &&
14830 AsmPieces[2] == "~{flags}" &&
14831 AsmPieces[3] == "~{fpsr}")
14832 return IntrinsicLowering::LowerToByteSwap(CI);
14835 if (CI->getType()->isIntegerTy(64)) {
14836 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
14837 if (Constraints.size() >= 2 &&
14838 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
14839 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
14840 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
14841 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
14842 matchAsm(AsmPieces[1], "bswap", "%edx") &&
14843 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
14844 return IntrinsicLowering::LowerToByteSwap(CI);
14854 /// getConstraintType - Given a constraint letter, return the type of
14855 /// constraint it is for this target.
14856 X86TargetLowering::ConstraintType
14857 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
14858 if (Constraint.size() == 1) {
14859 switch (Constraint[0]) {
14870 return C_RegisterClass;
14894 return TargetLowering::getConstraintType(Constraint);
14897 /// Examine constraint type and operand type and determine a weight value.
14898 /// This object must already have been set up with the operand type
14899 /// and the current alternative constraint selected.
14900 TargetLowering::ConstraintWeight
14901 X86TargetLowering::getSingleConstraintMatchWeight(
14902 AsmOperandInfo &info, const char *constraint) const {
14903 ConstraintWeight weight = CW_Invalid;
14904 Value *CallOperandVal = info.CallOperandVal;
14905 // If we don't have a value, we can't do a match,
14906 // but allow it at the lowest weight.
14907 if (CallOperandVal == NULL)
14909 Type *type = CallOperandVal->getType();
14910 // Look at the constraint type.
14911 switch (*constraint) {
14913 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
14924 if (CallOperandVal->getType()->isIntegerTy())
14925 weight = CW_SpecificReg;
14930 if (type->isFloatingPointTy())
14931 weight = CW_SpecificReg;
14934 if (type->isX86_MMXTy() && Subtarget->hasMMX())
14935 weight = CW_SpecificReg;
14939 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
14940 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
14941 weight = CW_Register;
14944 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
14945 if (C->getZExtValue() <= 31)
14946 weight = CW_Constant;
14950 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14951 if (C->getZExtValue() <= 63)
14952 weight = CW_Constant;
14956 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14957 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
14958 weight = CW_Constant;
14962 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14963 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
14964 weight = CW_Constant;
14968 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14969 if (C->getZExtValue() <= 3)
14970 weight = CW_Constant;
14974 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14975 if (C->getZExtValue() <= 0xff)
14976 weight = CW_Constant;
14981 if (dyn_cast<ConstantFP>(CallOperandVal)) {
14982 weight = CW_Constant;
14986 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14987 if ((C->getSExtValue() >= -0x80000000LL) &&
14988 (C->getSExtValue() <= 0x7fffffffLL))
14989 weight = CW_Constant;
14993 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14994 if (C->getZExtValue() <= 0xffffffff)
14995 weight = CW_Constant;
15002 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15003 /// with another that has more specific requirements based on the type of the
15004 /// corresponding operand.
15005 const char *X86TargetLowering::
15006 LowerXConstraint(EVT ConstraintVT) const {
15007 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15008 // 'f' like normal targets.
15009 if (ConstraintVT.isFloatingPoint()) {
15010 if (Subtarget->hasSSE2())
15012 if (Subtarget->hasSSE1())
15016 return TargetLowering::LowerXConstraint(ConstraintVT);
15019 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15020 /// vector. If it is invalid, don't add anything to Ops.
15021 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15022 std::string &Constraint,
15023 std::vector<SDValue>&Ops,
15024 SelectionDAG &DAG) const {
15025 SDValue Result(0, 0);
15027 // Only support length 1 constraints for now.
15028 if (Constraint.length() > 1) return;
15030 char ConstraintLetter = Constraint[0];
15031 switch (ConstraintLetter) {
15034 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15035 if (C->getZExtValue() <= 31) {
15036 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15042 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15043 if (C->getZExtValue() <= 63) {
15044 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15050 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15051 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15052 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15058 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15059 if (C->getZExtValue() <= 255) {
15060 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15066 // 32-bit signed value
15067 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15068 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15069 C->getSExtValue())) {
15070 // Widen to 64 bits here to get it sign extended.
15071 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15074 // FIXME gcc accepts some relocatable values here too, but only in certain
15075 // memory models; it's complicated.
15080 // 32-bit unsigned value
15081 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15082 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15083 C->getZExtValue())) {
15084 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15088 // FIXME gcc accepts some relocatable values here too, but only in certain
15089 // memory models; it's complicated.
15093 // Literal immediates are always ok.
15094 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15095 // Widen to 64 bits here to get it sign extended.
15096 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15100 // In any sort of PIC mode addresses need to be computed at runtime by
15101 // adding in a register or some sort of table lookup. These can't
15102 // be used as immediates.
15103 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15106 // If we are in non-pic codegen mode, we allow the address of a global (with
15107 // an optional displacement) to be used with 'i'.
15108 GlobalAddressSDNode *GA = 0;
15109 int64_t Offset = 0;
15111 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15113 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15114 Offset += GA->getOffset();
15116 } else if (Op.getOpcode() == ISD::ADD) {
15117 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15118 Offset += C->getZExtValue();
15119 Op = Op.getOperand(0);
15122 } else if (Op.getOpcode() == ISD::SUB) {
15123 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15124 Offset += -C->getZExtValue();
15125 Op = Op.getOperand(0);
15130 // Otherwise, this isn't something we can handle, reject it.
15134 const GlobalValue *GV = GA->getGlobal();
15135 // If we require an extra load to get this address, as in PIC mode, we
15136 // can't accept it.
15137 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15138 getTargetMachine())))
15141 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15142 GA->getValueType(0), Offset);
15147 if (Result.getNode()) {
15148 Ops.push_back(Result);
15151 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15154 std::pair<unsigned, const TargetRegisterClass*>
15155 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15157 // First, see if this is a constraint that directly corresponds to an LLVM
15159 if (Constraint.size() == 1) {
15160 // GCC Constraint Letters
15161 switch (Constraint[0]) {
15163 // TODO: Slight differences here in allocation order and leaving
15164 // RIP in the class. Do they matter any more here than they do
15165 // in the normal allocation?
15166 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15167 if (Subtarget->is64Bit()) {
15168 if (VT == MVT::i32 || VT == MVT::f32)
15169 return std::make_pair(0U, X86::GR32RegisterClass);
15170 else if (VT == MVT::i16)
15171 return std::make_pair(0U, X86::GR16RegisterClass);
15172 else if (VT == MVT::i8 || VT == MVT::i1)
15173 return std::make_pair(0U, X86::GR8RegisterClass);
15174 else if (VT == MVT::i64 || VT == MVT::f64)
15175 return std::make_pair(0U, X86::GR64RegisterClass);
15178 // 32-bit fallthrough
15179 case 'Q': // Q_REGS
15180 if (VT == MVT::i32 || VT == MVT::f32)
15181 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
15182 else if (VT == MVT::i16)
15183 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
15184 else if (VT == MVT::i8 || VT == MVT::i1)
15185 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
15186 else if (VT == MVT::i64)
15187 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
15189 case 'r': // GENERAL_REGS
15190 case 'l': // INDEX_REGS
15191 if (VT == MVT::i8 || VT == MVT::i1)
15192 return std::make_pair(0U, X86::GR8RegisterClass);
15193 if (VT == MVT::i16)
15194 return std::make_pair(0U, X86::GR16RegisterClass);
15195 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15196 return std::make_pair(0U, X86::GR32RegisterClass);
15197 return std::make_pair(0U, X86::GR64RegisterClass);
15198 case 'R': // LEGACY_REGS
15199 if (VT == MVT::i8 || VT == MVT::i1)
15200 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
15201 if (VT == MVT::i16)
15202 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
15203 if (VT == MVT::i32 || !Subtarget->is64Bit())
15204 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
15205 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
15206 case 'f': // FP Stack registers.
15207 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15208 // value to the correct fpstack register class.
15209 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15210 return std::make_pair(0U, X86::RFP32RegisterClass);
15211 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15212 return std::make_pair(0U, X86::RFP64RegisterClass);
15213 return std::make_pair(0U, X86::RFP80RegisterClass);
15214 case 'y': // MMX_REGS if MMX allowed.
15215 if (!Subtarget->hasMMX()) break;
15216 return std::make_pair(0U, X86::VR64RegisterClass);
15217 case 'Y': // SSE_REGS if SSE2 allowed
15218 if (!Subtarget->hasSSE2()) break;
15220 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15221 if (!Subtarget->hasSSE1()) break;
15223 switch (VT.getSimpleVT().SimpleTy) {
15225 // Scalar SSE types.
15228 return std::make_pair(0U, X86::FR32RegisterClass);
15231 return std::make_pair(0U, X86::FR64RegisterClass);
15239 return std::make_pair(0U, X86::VR128RegisterClass);
15247 return std::make_pair(0U, X86::VR256RegisterClass);
15254 // Use the default implementation in TargetLowering to convert the register
15255 // constraint into a member of a register class.
15256 std::pair<unsigned, const TargetRegisterClass*> Res;
15257 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15259 // Not found as a standard register?
15260 if (Res.second == 0) {
15261 // Map st(0) -> st(7) -> ST0
15262 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15263 tolower(Constraint[1]) == 's' &&
15264 tolower(Constraint[2]) == 't' &&
15265 Constraint[3] == '(' &&
15266 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15267 Constraint[5] == ')' &&
15268 Constraint[6] == '}') {
15270 Res.first = X86::ST0+Constraint[4]-'0';
15271 Res.second = X86::RFP80RegisterClass;
15275 // GCC allows "st(0)" to be called just plain "st".
15276 if (StringRef("{st}").equals_lower(Constraint)) {
15277 Res.first = X86::ST0;
15278 Res.second = X86::RFP80RegisterClass;
15283 if (StringRef("{flags}").equals_lower(Constraint)) {
15284 Res.first = X86::EFLAGS;
15285 Res.second = X86::CCRRegisterClass;
15289 // 'A' means EAX + EDX.
15290 if (Constraint == "A") {
15291 Res.first = X86::EAX;
15292 Res.second = X86::GR32_ADRegisterClass;
15298 // Otherwise, check to see if this is a register class of the wrong value
15299 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15300 // turn into {ax},{dx}.
15301 if (Res.second->hasType(VT))
15302 return Res; // Correct type already, nothing to do.
15304 // All of the single-register GCC register classes map their values onto
15305 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15306 // really want an 8-bit or 32-bit register, map to the appropriate register
15307 // class and return the appropriate register.
15308 if (Res.second == X86::GR16RegisterClass) {
15309 if (VT == MVT::i8) {
15310 unsigned DestReg = 0;
15311 switch (Res.first) {
15313 case X86::AX: DestReg = X86::AL; break;
15314 case X86::DX: DestReg = X86::DL; break;
15315 case X86::CX: DestReg = X86::CL; break;
15316 case X86::BX: DestReg = X86::BL; break;
15319 Res.first = DestReg;
15320 Res.second = X86::GR8RegisterClass;
15322 } else if (VT == MVT::i32) {
15323 unsigned DestReg = 0;
15324 switch (Res.first) {
15326 case X86::AX: DestReg = X86::EAX; break;
15327 case X86::DX: DestReg = X86::EDX; break;
15328 case X86::CX: DestReg = X86::ECX; break;
15329 case X86::BX: DestReg = X86::EBX; break;
15330 case X86::SI: DestReg = X86::ESI; break;
15331 case X86::DI: DestReg = X86::EDI; break;
15332 case X86::BP: DestReg = X86::EBP; break;
15333 case X86::SP: DestReg = X86::ESP; break;
15336 Res.first = DestReg;
15337 Res.second = X86::GR32RegisterClass;
15339 } else if (VT == MVT::i64) {
15340 unsigned DestReg = 0;
15341 switch (Res.first) {
15343 case X86::AX: DestReg = X86::RAX; break;
15344 case X86::DX: DestReg = X86::RDX; break;
15345 case X86::CX: DestReg = X86::RCX; break;
15346 case X86::BX: DestReg = X86::RBX; break;
15347 case X86::SI: DestReg = X86::RSI; break;
15348 case X86::DI: DestReg = X86::RDI; break;
15349 case X86::BP: DestReg = X86::RBP; break;
15350 case X86::SP: DestReg = X86::RSP; break;
15353 Res.first = DestReg;
15354 Res.second = X86::GR64RegisterClass;
15357 } else if (Res.second == X86::FR32RegisterClass ||
15358 Res.second == X86::FR64RegisterClass ||
15359 Res.second == X86::VR128RegisterClass) {
15360 // Handle references to XMM physical registers that got mapped into the
15361 // wrong class. This can happen with constraints like {xmm0} where the
15362 // target independent register mapper will just pick the first match it can
15363 // find, ignoring the required type.
15364 if (VT == MVT::f32)
15365 Res.second = X86::FR32RegisterClass;
15366 else if (VT == MVT::f64)
15367 Res.second = X86::FR64RegisterClass;
15368 else if (X86::VR128RegisterClass->hasType(VT))
15369 Res.second = X86::VR128RegisterClass;