1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1597 // There are no 8-bit 3-address imul/mul instructions
1598 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1599 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1601 if (!Subtarget->is64Bit()) {
1602 // These libcalls are not available in 32-bit.
1603 setLibcallName(RTLIB::SHL_I128, nullptr);
1604 setLibcallName(RTLIB::SRL_I128, nullptr);
1605 setLibcallName(RTLIB::SRA_I128, nullptr);
1608 // Combine sin / cos into one node or libcall if possible.
1609 if (Subtarget->hasSinCos()) {
1610 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1611 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1612 if (Subtarget->isTargetDarwin()) {
1613 // For MacOSX, we don't want to the normal expansion of a libcall to
1614 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1616 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1617 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1621 if (Subtarget->isTargetWin64()) {
1622 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::SREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UREM, MVT::i128, Custom);
1626 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1627 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1630 // We have target-specific dag combine patterns for the following nodes:
1631 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1632 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1633 setTargetDAGCombine(ISD::VSELECT);
1634 setTargetDAGCombine(ISD::SELECT);
1635 setTargetDAGCombine(ISD::SHL);
1636 setTargetDAGCombine(ISD::SRA);
1637 setTargetDAGCombine(ISD::SRL);
1638 setTargetDAGCombine(ISD::OR);
1639 setTargetDAGCombine(ISD::AND);
1640 setTargetDAGCombine(ISD::ADD);
1641 setTargetDAGCombine(ISD::FADD);
1642 setTargetDAGCombine(ISD::FSUB);
1643 setTargetDAGCombine(ISD::FMA);
1644 setTargetDAGCombine(ISD::SUB);
1645 setTargetDAGCombine(ISD::LOAD);
1646 setTargetDAGCombine(ISD::STORE);
1647 setTargetDAGCombine(ISD::ZERO_EXTEND);
1648 setTargetDAGCombine(ISD::ANY_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1651 setTargetDAGCombine(ISD::TRUNCATE);
1652 setTargetDAGCombine(ISD::SINT_TO_FP);
1653 setTargetDAGCombine(ISD::SETCC);
1654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1655 setTargetDAGCombine(ISD::BUILD_VECTOR);
1656 if (Subtarget->is64Bit())
1657 setTargetDAGCombine(ISD::MUL);
1658 setTargetDAGCombine(ISD::XOR);
1660 computeRegisterProperties();
1662 // On Darwin, -Os means optimize for size without hurting performance,
1663 // do not reduce the limit.
1664 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1665 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1666 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1667 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1669 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1670 setPrefLoopAlignment(4); // 2^4 bytes.
1672 // Predictable cmov don't hurt on atom because it's in-order.
1673 PredictableSelectIsExpensive = !Subtarget->isAtom();
1675 setPrefFunctionAlignment(4); // 2^4 bytes.
1677 verifyIntrinsicTables();
1680 // This has so far only been implemented for 64-bit MachO.
1681 bool X86TargetLowering::useLoadStackGuardNode() const {
1682 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1683 Subtarget->is64Bit();
1686 TargetLoweringBase::LegalizeTypeAction
1687 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1688 if (ExperimentalVectorWideningLegalization &&
1689 VT.getVectorNumElements() != 1 &&
1690 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1691 return TypeWidenVector;
1693 return TargetLoweringBase::getPreferredVectorAction(VT);
1696 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1698 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1700 const unsigned NumElts = VT.getVectorNumElements();
1701 const EVT EltVT = VT.getVectorElementType();
1702 if (VT.is512BitVector()) {
1703 if (Subtarget->hasAVX512())
1704 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1705 EltVT == MVT::f32 || EltVT == MVT::f64)
1707 case 8: return MVT::v8i1;
1708 case 16: return MVT::v16i1;
1710 if (Subtarget->hasBWI())
1711 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1713 case 32: return MVT::v32i1;
1714 case 64: return MVT::v64i1;
1718 if (VT.is256BitVector() || VT.is128BitVector()) {
1719 if (Subtarget->hasVLX())
1720 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1721 EltVT == MVT::f32 || EltVT == MVT::f64)
1723 case 2: return MVT::v2i1;
1724 case 4: return MVT::v4i1;
1725 case 8: return MVT::v8i1;
1727 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1728 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1730 case 8: return MVT::v8i1;
1731 case 16: return MVT::v16i1;
1732 case 32: return MVT::v32i1;
1736 return VT.changeVectorElementTypeToInteger();
1739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1740 /// the desired ByVal argument alignment.
1741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1744 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1745 if (VTy->getBitWidth() == 128)
1747 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1748 unsigned EltAlign = 0;
1749 getMaxByValAlign(ATy->getElementType(), EltAlign);
1750 if (EltAlign > MaxAlign)
1751 MaxAlign = EltAlign;
1752 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1753 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1754 unsigned EltAlign = 0;
1755 getMaxByValAlign(STy->getElementType(i), EltAlign);
1756 if (EltAlign > MaxAlign)
1757 MaxAlign = EltAlign;
1764 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1765 /// function arguments in the caller parameter area. For X86, aggregates
1766 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1767 /// are at 4-byte boundaries.
1768 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1769 if (Subtarget->is64Bit()) {
1770 // Max of 8 and alignment of type.
1771 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1778 if (Subtarget->hasSSE1())
1779 getMaxByValAlign(Ty, Align);
1783 /// getOptimalMemOpType - Returns the target specific optimal type for load
1784 /// and store operations as a result of memset, memcpy, and memmove
1785 /// lowering. If DstAlign is zero that means it's safe to destination
1786 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1787 /// means there isn't a need to check it against alignment requirement,
1788 /// probably because the source does not need to be loaded. If 'IsMemset' is
1789 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1790 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1791 /// source is constant so it does not need to be loaded.
1792 /// It returns EVT::Other if the type should be determined using generic
1793 /// target-independent logic.
1795 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1796 unsigned DstAlign, unsigned SrcAlign,
1797 bool IsMemset, bool ZeroMemset,
1799 MachineFunction &MF) const {
1800 const Function *F = MF.getFunction();
1801 if ((!IsMemset || ZeroMemset) &&
1802 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1803 Attribute::NoImplicitFloat)) {
1805 (Subtarget->isUnalignedMemAccessFast() ||
1806 ((DstAlign == 0 || DstAlign >= 16) &&
1807 (SrcAlign == 0 || SrcAlign >= 16)))) {
1809 if (Subtarget->hasInt256())
1811 if (Subtarget->hasFp256())
1814 if (Subtarget->hasSSE2())
1816 if (Subtarget->hasSSE1())
1818 } else if (!MemcpyStrSrc && Size >= 8 &&
1819 !Subtarget->is64Bit() &&
1820 Subtarget->hasSSE2()) {
1821 // Do not use f64 to lower memcpy if source is string constant. It's
1822 // better to use i32 to avoid the loads.
1826 if (Subtarget->is64Bit() && Size >= 8)
1831 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1833 return X86ScalarSSEf32;
1834 else if (VT == MVT::f64)
1835 return X86ScalarSSEf64;
1840 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1845 *Fast = Subtarget->isUnalignedMemAccessFast();
1849 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1850 /// current function. The returned value is a member of the
1851 /// MachineJumpTableInfo::JTEntryKind enum.
1852 unsigned X86TargetLowering::getJumpTableEncoding() const {
1853 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1855 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1856 Subtarget->isPICStyleGOT())
1857 return MachineJumpTableInfo::EK_Custom32;
1859 // Otherwise, use the normal jump table encoding heuristics.
1860 return TargetLowering::getJumpTableEncoding();
1864 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1865 const MachineBasicBlock *MBB,
1866 unsigned uid,MCContext &Ctx) const{
1867 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT());
1869 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1871 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1872 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1875 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1877 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1878 SelectionDAG &DAG) const {
1879 if (!Subtarget->is64Bit())
1880 // This doesn't have SDLoc associated with it, but is not really the
1881 // same as a Register.
1882 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1886 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1887 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1889 const MCExpr *X86TargetLowering::
1890 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1891 MCContext &Ctx) const {
1892 // X86-64 uses RIP relative addressing based on the jump table label.
1893 if (Subtarget->isPICStyleRIPRel())
1894 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1896 // Otherwise, the reference is relative to the PIC base.
1897 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1900 // FIXME: Why this routine is here? Move to RegInfo!
1901 std::pair<const TargetRegisterClass*, uint8_t>
1902 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1903 const TargetRegisterClass *RRC = nullptr;
1905 switch (VT.SimpleTy) {
1907 return TargetLowering::findRepresentativeClass(VT);
1908 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1909 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1912 RRC = &X86::VR64RegClass;
1914 case MVT::f32: case MVT::f64:
1915 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1916 case MVT::v4f32: case MVT::v2f64:
1917 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1919 RRC = &X86::VR128RegClass;
1922 return std::make_pair(RRC, Cost);
1925 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1926 unsigned &Offset) const {
1927 if (!Subtarget->isTargetLinux())
1930 if (Subtarget->is64Bit()) {
1931 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1933 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1945 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1946 unsigned DestAS) const {
1947 assert(SrcAS != DestAS && "Expected different address spaces!");
1949 return SrcAS < 256 && DestAS < 256;
1952 //===----------------------------------------------------------------------===//
1953 // Return Value Calling Convention Implementation
1954 //===----------------------------------------------------------------------===//
1956 #include "X86GenCallingConv.inc"
1959 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1960 MachineFunction &MF, bool isVarArg,
1961 const SmallVectorImpl<ISD::OutputArg> &Outs,
1962 LLVMContext &Context) const {
1963 SmallVector<CCValAssign, 16> RVLocs;
1964 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1965 return CCInfo.CheckReturn(Outs, RetCC_X86);
1968 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1969 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1974 X86TargetLowering::LowerReturn(SDValue Chain,
1975 CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::OutputArg> &Outs,
1977 const SmallVectorImpl<SDValue> &OutVals,
1978 SDLoc dl, SelectionDAG &DAG) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1984 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1987 SmallVector<SDValue, 6> RetOps;
1988 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1989 // Operand #1 = Bytes To Pop
1990 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1993 // Copy the result values into the output registers.
1994 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 assert(VA.isRegLoc() && "Can only return in registers!");
1997 SDValue ValToCopy = OutVals[i];
1998 EVT ValVT = ValToCopy.getValueType();
2000 // Promote values to the appropriate types
2001 if (VA.getLocInfo() == CCValAssign::SExt)
2002 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::ZExt)
2004 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::AExt)
2006 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2007 else if (VA.getLocInfo() == CCValAssign::BCvt)
2008 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2010 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2011 "Unexpected FP-extend for return value.");
2013 // If this is x86-64, and we disabled SSE, we can't return FP values,
2014 // or SSE or MMX vectors.
2015 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2016 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2017 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2018 report_fatal_error("SSE register return with SSE disabled");
2020 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2021 // llvm-gcc has never done it right and no one has noticed, so this
2022 // should be OK for now.
2023 if (ValVT == MVT::f64 &&
2024 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2025 report_fatal_error("SSE2 register return with SSE2 disabled");
2027 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2028 // the RET instruction and handled by the FP Stackifier.
2029 if (VA.getLocReg() == X86::FP0 ||
2030 VA.getLocReg() == X86::FP1) {
2031 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2032 // change the value to the FP stack register class.
2033 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2034 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2035 RetOps.push_back(ValToCopy);
2036 // Don't emit a copytoreg.
2040 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2041 // which is returned in RAX / RDX.
2042 if (Subtarget->is64Bit()) {
2043 if (ValVT == MVT::x86mmx) {
2044 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2045 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2046 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2048 // If we don't have SSE2 available, convert to v4f32 so the generated
2049 // register is legal.
2050 if (!Subtarget->hasSSE2())
2051 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2056 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2057 Flag = Chain.getValue(1);
2058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2061 // The x86-64 ABIs require that for returning structs by value we copy
2062 // the sret argument into %rax/%eax (depending on ABI) for the return.
2063 // Win32 requires us to put the sret argument to %eax as well.
2064 // We saved the argument into a virtual register in the entry block,
2065 // so now we copy the value out and into %rax/%eax.
2066 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2067 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2070 unsigned Reg = FuncInfo->getSRetReturnReg();
2072 "SRetReturnReg should have been set in LowerFormalArguments().");
2073 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2076 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2077 X86::RAX : X86::EAX;
2078 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2079 Flag = Chain.getValue(1);
2081 // RAX/EAX now acts like a return value.
2082 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2085 RetOps[0] = Chain; // Update chain.
2087 // Add the flag if we have it.
2089 RetOps.push_back(Flag);
2091 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2094 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2095 if (N->getNumValues() != 1)
2097 if (!N->hasNUsesOfValue(1, 0))
2100 SDValue TCChain = Chain;
2101 SDNode *Copy = *N->use_begin();
2102 if (Copy->getOpcode() == ISD::CopyToReg) {
2103 // If the copy has a glue operand, we conservatively assume it isn't safe to
2104 // perform a tail call.
2105 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2107 TCChain = Copy->getOperand(0);
2108 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2111 bool HasRet = false;
2112 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2114 if (UI->getOpcode() != X86ISD::RET_FLAG)
2116 // If we are returning more than one value, we can definitely
2117 // not make a tail call see PR19530
2118 if (UI->getNumOperands() > 4)
2120 if (UI->getNumOperands() == 4 &&
2121 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2134 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2135 ISD::NodeType ExtendKind) const {
2137 // TODO: Is this also valid on 32-bit?
2138 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2139 ReturnMVT = MVT::i8;
2141 ReturnMVT = MVT::i32;
2143 EVT MinVT = getRegisterType(Context, ReturnMVT);
2144 return VT.bitsLT(MinVT) ? MinVT : VT;
2147 /// LowerCallResult - Lower the result values of a call into the
2148 /// appropriate copies out of appropriate physical registers.
2151 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2152 CallingConv::ID CallConv, bool isVarArg,
2153 const SmallVectorImpl<ISD::InputArg> &Ins,
2154 SDLoc dl, SelectionDAG &DAG,
2155 SmallVectorImpl<SDValue> &InVals) const {
2157 // Assign locations to each value returned by this call.
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 bool Is64Bit = Subtarget->is64Bit();
2160 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2162 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2164 // Copy all of the result registers out of their specified physreg.
2165 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2166 CCValAssign &VA = RVLocs[i];
2167 EVT CopyVT = VA.getValVT();
2169 // If this is x86-64, and we disabled SSE, we can't return FP values
2170 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2171 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2172 report_fatal_error("SSE register return with SSE disabled");
2175 // If we prefer to use the value in xmm registers, copy it out as f80 and
2176 // use a truncate to move it from fp stack reg to xmm reg.
2177 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2178 isScalarFPTypeInSSEReg(VA.getValVT()))
2181 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2182 CopyVT, InFlag).getValue(1);
2183 SDValue Val = Chain.getValue(0);
2185 if (CopyVT != VA.getValVT())
2186 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2187 // This truncation won't change the value.
2188 DAG.getIntPtrConstant(1));
2190 InFlag = Chain.getValue(2);
2191 InVals.push_back(Val);
2197 //===----------------------------------------------------------------------===//
2198 // C & StdCall & Fast Calling Convention implementation
2199 //===----------------------------------------------------------------------===//
2200 // StdCall calling convention seems to be standard for many Windows' API
2201 // routines and around. It differs from C calling convention just a little:
2202 // callee should clean up the stack, not caller. Symbols should be also
2203 // decorated in some fancy way :) It doesn't support any vector arguments.
2204 // For info on fast calling convention see Fast Calling Convention (tail call)
2205 // implementation LowerX86_32FastCCCallTo.
2207 /// CallIsStructReturn - Determines whether a call uses struct return
2209 enum StructReturnType {
2214 static StructReturnType
2215 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2217 return NotStructReturn;
2219 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2220 if (!Flags.isSRet())
2221 return NotStructReturn;
2222 if (Flags.isInReg())
2223 return RegStructReturn;
2224 return StackStructReturn;
2227 /// ArgsAreStructReturn - Determines whether a function uses struct
2228 /// return semantics.
2229 static StructReturnType
2230 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2232 return NotStructReturn;
2234 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2235 if (!Flags.isSRet())
2236 return NotStructReturn;
2237 if (Flags.isInReg())
2238 return RegStructReturn;
2239 return StackStructReturn;
2242 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2243 /// by "Src" to address "Dst" with size and alignment information specified by
2244 /// the specific parameter attribute. The copy will be passed as a byval
2245 /// function parameter.
2247 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2248 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2250 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2252 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2253 /*isVolatile*/false, /*AlwaysInline=*/true,
2254 MachinePointerInfo(), MachinePointerInfo());
2257 /// IsTailCallConvention - Return true if the calling convention is one that
2258 /// supports tail call optimization.
2259 static bool IsTailCallConvention(CallingConv::ID CC) {
2260 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2261 CC == CallingConv::HiPE);
2264 /// \brief Return true if the calling convention is a C calling convention.
2265 static bool IsCCallConvention(CallingConv::ID CC) {
2266 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2267 CC == CallingConv::X86_64_SysV);
2270 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2271 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2275 CallingConv::ID CalleeCC = CS.getCallingConv();
2276 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2282 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2283 /// a tailcall target by changing its ABI.
2284 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2285 bool GuaranteedTailCallOpt) {
2286 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2290 X86TargetLowering::LowerMemArgument(SDValue Chain,
2291 CallingConv::ID CallConv,
2292 const SmallVectorImpl<ISD::InputArg> &Ins,
2293 SDLoc dl, SelectionDAG &DAG,
2294 const CCValAssign &VA,
2295 MachineFrameInfo *MFI,
2297 // Create the nodes corresponding to a load from this parameter slot.
2298 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2299 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2300 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2301 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2304 // If value is passed by pointer we have address passed instead of the value
2306 if (VA.getLocInfo() == CCValAssign::Indirect)
2307 ValVT = VA.getLocVT();
2309 ValVT = VA.getValVT();
2311 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2312 // changed with more analysis.
2313 // In case of tail call optimization mark all arguments mutable. Since they
2314 // could be overwritten by lowering of arguments in case of a tail call.
2315 if (Flags.isByVal()) {
2316 unsigned Bytes = Flags.getByValSize();
2317 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2318 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2319 return DAG.getFrameIndex(FI, getPointerTy());
2321 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2322 VA.getLocMemOffset(), isImmutable);
2323 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2324 return DAG.getLoad(ValVT, dl, Chain, FIN,
2325 MachinePointerInfo::getFixedStack(FI),
2326 false, false, false, 0);
2330 // FIXME: Get this from tablegen.
2331 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2332 const X86Subtarget *Subtarget) {
2333 assert(Subtarget->is64Bit());
2335 if (Subtarget->isCallingConvWin64(CallConv)) {
2336 static const MCPhysReg GPR64ArgRegsWin64[] = {
2337 X86::RCX, X86::RDX, X86::R8, X86::R9
2339 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2342 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2343 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2345 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2348 // FIXME: Get this from tablegen.
2349 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2350 CallingConv::ID CallConv,
2351 const X86Subtarget *Subtarget) {
2352 assert(Subtarget->is64Bit());
2353 if (Subtarget->isCallingConvWin64(CallConv)) {
2354 // The XMM registers which might contain var arg parameters are shadowed
2355 // in their paired GPR. So we only need to save the GPR to their home
2357 // TODO: __vectorcall will change this.
2361 const Function *Fn = MF.getFunction();
2362 bool NoImplicitFloatOps = Fn->getAttributes().
2363 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2364 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2365 "SSE register cannot be used when SSE is disabled!");
2366 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2367 !Subtarget->hasSSE1())
2368 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2372 static const MCPhysReg XMMArgRegs64Bit[] = {
2373 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2374 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2376 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2380 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2381 CallingConv::ID CallConv,
2383 const SmallVectorImpl<ISD::InputArg> &Ins,
2386 SmallVectorImpl<SDValue> &InVals)
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 const Function* Fn = MF.getFunction();
2392 if (Fn->hasExternalLinkage() &&
2393 Subtarget->isTargetCygMing() &&
2394 Fn->getName() == "main")
2395 FuncInfo->setForceFramePointer(true);
2397 MachineFrameInfo *MFI = MF.getFrameInfo();
2398 bool Is64Bit = Subtarget->is64Bit();
2399 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2401 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2402 "Var args not supported with calling convention fastcc, ghc or hipe");
2404 // Assign locations to all of the incoming arguments.
2405 SmallVector<CCValAssign, 16> ArgLocs;
2406 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2408 // Allocate shadow area for Win64
2410 CCInfo.AllocateStack(32, 8);
2412 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2414 unsigned LastVal = ~0U;
2416 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2417 CCValAssign &VA = ArgLocs[i];
2418 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2420 assert(VA.getValNo() != LastVal &&
2421 "Don't support value assigned to multiple locs yet");
2423 LastVal = VA.getValNo();
2425 if (VA.isRegLoc()) {
2426 EVT RegVT = VA.getLocVT();
2427 const TargetRegisterClass *RC;
2428 if (RegVT == MVT::i32)
2429 RC = &X86::GR32RegClass;
2430 else if (Is64Bit && RegVT == MVT::i64)
2431 RC = &X86::GR64RegClass;
2432 else if (RegVT == MVT::f32)
2433 RC = &X86::FR32RegClass;
2434 else if (RegVT == MVT::f64)
2435 RC = &X86::FR64RegClass;
2436 else if (RegVT.is512BitVector())
2437 RC = &X86::VR512RegClass;
2438 else if (RegVT.is256BitVector())
2439 RC = &X86::VR256RegClass;
2440 else if (RegVT.is128BitVector())
2441 RC = &X86::VR128RegClass;
2442 else if (RegVT == MVT::x86mmx)
2443 RC = &X86::VR64RegClass;
2444 else if (RegVT == MVT::i1)
2445 RC = &X86::VK1RegClass;
2446 else if (RegVT == MVT::v8i1)
2447 RC = &X86::VK8RegClass;
2448 else if (RegVT == MVT::v16i1)
2449 RC = &X86::VK16RegClass;
2450 else if (RegVT == MVT::v32i1)
2451 RC = &X86::VK32RegClass;
2452 else if (RegVT == MVT::v64i1)
2453 RC = &X86::VK64RegClass;
2455 llvm_unreachable("Unknown argument type!");
2457 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2458 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2460 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2461 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2463 if (VA.getLocInfo() == CCValAssign::SExt)
2464 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::ZExt)
2467 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2468 DAG.getValueType(VA.getValVT()));
2469 else if (VA.getLocInfo() == CCValAssign::BCvt)
2470 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2472 if (VA.isExtInLoc()) {
2473 // Handle MMX values passed in XMM regs.
2474 if (RegVT.isVector())
2475 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2477 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2480 assert(VA.isMemLoc());
2481 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2484 // If value is passed via pointer - do a load.
2485 if (VA.getLocInfo() == CCValAssign::Indirect)
2486 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2487 MachinePointerInfo(), false, false, false, 0);
2489 InVals.push_back(ArgValue);
2492 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2494 // The x86-64 ABIs require that for returning structs by value we copy
2495 // the sret argument into %rax/%eax (depending on ABI) for the return.
2496 // Win32 requires us to put the sret argument to %eax as well.
2497 // Save the argument into a virtual register so that we can access it
2498 // from the return points.
2499 if (Ins[i].Flags.isSRet()) {
2500 unsigned Reg = FuncInfo->getSRetReturnReg();
2502 MVT PtrTy = getPointerTy();
2503 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2504 FuncInfo->setSRetReturnReg(Reg);
2506 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2507 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2513 unsigned StackSize = CCInfo.getNextStackOffset();
2514 // Align stack specially for tail calls.
2515 if (FuncIsMadeTailCallSafe(CallConv,
2516 MF.getTarget().Options.GuaranteedTailCallOpt))
2517 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2519 // If the function takes variable number of arguments, make a frame index for
2520 // the start of the first vararg value... for expansion of llvm.va_start. We
2521 // can skip this if there are no va_start calls.
2522 if (MFI->hasVAStart() &&
2523 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2524 CallConv != CallingConv::X86_ThisCall))) {
2525 FuncInfo->setVarArgsFrameIndex(
2526 MFI->CreateFixedObject(1, StackSize, true));
2529 // 64-bit calling conventions support varargs and register parameters, so we
2530 // have to do extra work to spill them in the prologue or forward them to
2532 if (Is64Bit && isVarArg &&
2533 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2534 // Find the first unallocated argument registers.
2535 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2536 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2537 unsigned NumIntRegs =
2538 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2539 unsigned NumXMMRegs =
2540 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2541 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2542 "SSE register cannot be used when SSE is disabled!");
2544 // Gather all the live in physical registers.
2545 SmallVector<SDValue, 6> LiveGPRs;
2546 SmallVector<SDValue, 8> LiveXMMRegs;
2548 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2549 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2551 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2553 if (!ArgXMMs.empty()) {
2554 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2555 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2556 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2557 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2558 LiveXMMRegs.push_back(
2559 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2563 // Store them to the va_list returned by va_start.
2564 if (MFI->hasVAStart()) {
2566 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2567 // Get to the caller-allocated home save location. Add 8 to account
2568 // for the return address.
2569 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2570 FuncInfo->setRegSaveFrameIndex(
2571 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2572 // Fixup to set vararg frame on shadow area (4 x i64).
2574 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2576 // For X86-64, if there are vararg parameters that are passed via
2577 // registers, then we must store them to their spots on the stack so
2578 // they may be loaded by deferencing the result of va_next.
2579 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2580 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2581 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2582 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2585 // Store the integer parameter registers.
2586 SmallVector<SDValue, 8> MemOps;
2587 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2589 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2590 for (SDValue Val : LiveGPRs) {
2591 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2592 DAG.getIntPtrConstant(Offset));
2594 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2595 MachinePointerInfo::getFixedStack(
2596 FuncInfo->getRegSaveFrameIndex(), Offset),
2598 MemOps.push_back(Store);
2602 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2603 // Now store the XMM (fp + vector) parameter registers.
2604 SmallVector<SDValue, 12> SaveXMMOps;
2605 SaveXMMOps.push_back(Chain);
2606 SaveXMMOps.push_back(ALVal);
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getRegSaveFrameIndex()));
2609 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2610 FuncInfo->getVarArgsFPOffset()));
2611 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2613 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2614 MVT::Other, SaveXMMOps));
2617 if (!MemOps.empty())
2618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2620 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2621 // to the liveout set on a musttail call.
2622 assert(MFI->hasMustTailInVarArgFunc());
2623 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2624 typedef X86MachineFunctionInfo::Forward Forward;
2626 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2628 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2629 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2630 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2633 if (!ArgXMMs.empty()) {
2635 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2636 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2637 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2639 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2641 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2642 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2644 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2650 // Some CCs need callee pop.
2651 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2652 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2653 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2655 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2656 // If this is an sret function, the return should pop the hidden pointer.
2657 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2658 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2659 argsAreStructReturn(Ins) == StackStructReturn)
2660 FuncInfo->setBytesToPopOnReturn(4);
2664 // RegSaveFrameIndex is X86-64 only.
2665 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2666 if (CallConv == CallingConv::X86_FastCall ||
2667 CallConv == CallingConv::X86_ThisCall)
2668 // fastcc functions can't have varargs.
2669 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2672 FuncInfo->setArgumentStackSize(StackSize);
2678 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2679 SDValue StackPtr, SDValue Arg,
2680 SDLoc dl, SelectionDAG &DAG,
2681 const CCValAssign &VA,
2682 ISD::ArgFlagsTy Flags) const {
2683 unsigned LocMemOffset = VA.getLocMemOffset();
2684 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2685 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2686 if (Flags.isByVal())
2687 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2689 return DAG.getStore(Chain, dl, Arg, PtrOff,
2690 MachinePointerInfo::getStack(LocMemOffset),
2694 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2695 /// optimization is performed and it is required.
2697 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2698 SDValue &OutRetAddr, SDValue Chain,
2699 bool IsTailCall, bool Is64Bit,
2700 int FPDiff, SDLoc dl) const {
2701 // Adjust the Return address stack slot.
2702 EVT VT = getPointerTy();
2703 OutRetAddr = getReturnAddressFrameIndex(DAG);
2705 // Load the "old" Return address.
2706 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2707 false, false, false, 0);
2708 return SDValue(OutRetAddr.getNode(), 1);
2711 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2712 /// optimization is performed and it is required (FPDiff!=0).
2713 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2714 SDValue Chain, SDValue RetAddrFrIdx,
2715 EVT PtrVT, unsigned SlotSize,
2716 int FPDiff, SDLoc dl) {
2717 // Store the return address to the appropriate stack slot.
2718 if (!FPDiff) return Chain;
2719 // Calculate the new stack slot for the return address.
2720 int NewReturnAddrFI =
2721 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2723 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2724 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2725 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2731 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2732 SmallVectorImpl<SDValue> &InVals) const {
2733 SelectionDAG &DAG = CLI.DAG;
2735 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2736 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2737 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2738 SDValue Chain = CLI.Chain;
2739 SDValue Callee = CLI.Callee;
2740 CallingConv::ID CallConv = CLI.CallConv;
2741 bool &isTailCall = CLI.IsTailCall;
2742 bool isVarArg = CLI.IsVarArg;
2744 MachineFunction &MF = DAG.getMachineFunction();
2745 bool Is64Bit = Subtarget->is64Bit();
2746 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2747 StructReturnType SR = callIsStructReturn(Outs);
2748 bool IsSibcall = false;
2749 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2751 if (MF.getTarget().Options.DisableTailCalls)
2754 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2756 // Force this to be a tail call. The verifier rules are enough to ensure
2757 // that we can lower this successfully without moving the return address
2760 } else if (isTailCall) {
2761 // Check if it's really possible to do a tail call.
2762 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2763 isVarArg, SR != NotStructReturn,
2764 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2765 Outs, OutVals, Ins, DAG);
2767 // Sibcalls are automatically detected tailcalls which do not require
2769 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2776 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2777 "Var args not supported with calling convention fastcc, ghc or hipe");
2779 // Analyze operands of the call, assigning locations to each operand.
2780 SmallVector<CCValAssign, 16> ArgLocs;
2781 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2783 // Allocate shadow area for Win64
2785 CCInfo.AllocateStack(32, 8);
2787 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2789 // Get a count of how many bytes are to be pushed on the stack.
2790 unsigned NumBytes = CCInfo.getNextStackOffset();
2792 // This is a sibcall. The memory operands are available in caller's
2793 // own caller's stack.
2795 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2796 IsTailCallConvention(CallConv))
2797 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2800 if (isTailCall && !IsSibcall && !IsMustTail) {
2801 // Lower arguments at fp - stackoffset + fpdiff.
2802 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2804 FPDiff = NumBytesCallerPushed - NumBytes;
2806 // Set the delta of movement of the returnaddr stackslot.
2807 // But only set if delta is greater than previous delta.
2808 if (FPDiff < X86Info->getTCReturnAddrDelta())
2809 X86Info->setTCReturnAddrDelta(FPDiff);
2812 unsigned NumBytesToPush = NumBytes;
2813 unsigned NumBytesToPop = NumBytes;
2815 // If we have an inalloca argument, all stack space has already been allocated
2816 // for us and be right at the top of the stack. We don't support multiple
2817 // arguments passed in memory when using inalloca.
2818 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2820 if (!ArgLocs.back().isMemLoc())
2821 report_fatal_error("cannot use inalloca attribute on a register "
2823 if (ArgLocs.back().getLocMemOffset() != 0)
2824 report_fatal_error("any parameter with the inalloca attribute must be "
2825 "the only memory argument");
2829 Chain = DAG.getCALLSEQ_START(
2830 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2832 SDValue RetAddrFrIdx;
2833 // Load return address for tail calls.
2834 if (isTailCall && FPDiff)
2835 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2836 Is64Bit, FPDiff, dl);
2838 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2839 SmallVector<SDValue, 8> MemOpChains;
2842 // Walk the register/memloc assignments, inserting copies/loads. In the case
2843 // of tail call optimization arguments are handle later.
2844 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2845 DAG.getSubtarget().getRegisterInfo());
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 // Skip inalloca arguments, they have already been written.
2848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2849 if (Flags.isInAlloca())
2852 CCValAssign &VA = ArgLocs[i];
2853 EVT RegVT = VA.getLocVT();
2854 SDValue Arg = OutVals[i];
2855 bool isByVal = Flags.isByVal();
2857 // Promote the value if needed.
2858 switch (VA.getLocInfo()) {
2859 default: llvm_unreachable("Unknown loc info!");
2860 case CCValAssign::Full: break;
2861 case CCValAssign::SExt:
2862 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::ZExt:
2865 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2867 case CCValAssign::AExt:
2868 if (RegVT.is128BitVector()) {
2869 // Special case: passing MMX values in XMM registers.
2870 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2871 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2872 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2874 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2876 case CCValAssign::BCvt:
2877 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2879 case CCValAssign::Indirect: {
2880 // Store the argument.
2881 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2882 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2883 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2884 MachinePointerInfo::getFixedStack(FI),
2891 if (VA.isRegLoc()) {
2892 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2893 if (isVarArg && IsWin64) {
2894 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2895 // shadow reg if callee is a varargs function.
2896 unsigned ShadowReg = 0;
2897 switch (VA.getLocReg()) {
2898 case X86::XMM0: ShadowReg = X86::RCX; break;
2899 case X86::XMM1: ShadowReg = X86::RDX; break;
2900 case X86::XMM2: ShadowReg = X86::R8; break;
2901 case X86::XMM3: ShadowReg = X86::R9; break;
2904 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2906 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2907 assert(VA.isMemLoc());
2908 if (!StackPtr.getNode())
2909 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2911 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2912 dl, DAG, VA, Flags));
2916 if (!MemOpChains.empty())
2917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2919 if (Subtarget->isPICStyleGOT()) {
2920 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2923 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2924 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2926 // If we are tail calling and generating PIC/GOT style code load the
2927 // address of the callee into ECX. The value in ecx is used as target of
2928 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2929 // for tail calls on PIC/GOT architectures. Normally we would just put the
2930 // address of GOT into ebx and then call target@PLT. But for tail calls
2931 // ebx would be restored (since ebx is callee saved) before jumping to the
2934 // Note: The actual moving to ECX is done further down.
2935 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2936 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2937 !G->getGlobal()->hasProtectedVisibility())
2938 Callee = LowerGlobalAddress(Callee, DAG);
2939 else if (isa<ExternalSymbolSDNode>(Callee))
2940 Callee = LowerExternalSymbol(Callee, DAG);
2944 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2945 // From AMD64 ABI document:
2946 // For calls that may call functions that use varargs or stdargs
2947 // (prototype-less calls or calls to functions containing ellipsis (...) in
2948 // the declaration) %al is used as hidden argument to specify the number
2949 // of SSE registers used. The contents of %al do not need to match exactly
2950 // the number of registers, but must be an ubound on the number of SSE
2951 // registers used and is in the range 0 - 8 inclusive.
2953 // Count the number of XMM registers allocated.
2954 static const MCPhysReg XMMArgRegs[] = {
2955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2956 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2958 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2959 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2960 && "SSE registers cannot be used when SSE is disabled");
2962 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2963 DAG.getConstant(NumXMMRegs, MVT::i8)));
2966 if (Is64Bit && isVarArg && IsMustTail) {
2967 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2968 for (const auto &F : Forwards) {
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2970 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2974 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2975 // don't need this because the eligibility check rejects calls that require
2976 // shuffling arguments passed in memory.
2977 if (!IsSibcall && isTailCall) {
2978 // Force all the incoming stack arguments to be loaded from the stack
2979 // before any new outgoing arguments are stored to the stack, because the
2980 // outgoing stack slots may alias the incoming argument stack slots, and
2981 // the alias isn't otherwise explicit. This is slightly more conservative
2982 // than necessary, because it means that each store effectively depends
2983 // on every argument instead of just those arguments it would clobber.
2984 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2986 SmallVector<SDValue, 8> MemOpChains2;
2989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2990 CCValAssign &VA = ArgLocs[i];
2993 assert(VA.isMemLoc());
2994 SDValue Arg = OutVals[i];
2995 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2996 // Skip inalloca arguments. They don't require any work.
2997 if (Flags.isInAlloca())
2999 // Create frame index.
3000 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3001 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3002 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3003 FIN = DAG.getFrameIndex(FI, getPointerTy());
3005 if (Flags.isByVal()) {
3006 // Copy relative to framepointer.
3007 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3008 if (!StackPtr.getNode())
3009 StackPtr = DAG.getCopyFromReg(Chain, dl,
3010 RegInfo->getStackRegister(),
3012 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3014 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3018 // Store relative to framepointer.
3019 MemOpChains2.push_back(
3020 DAG.getStore(ArgChain, dl, Arg, FIN,
3021 MachinePointerInfo::getFixedStack(FI),
3026 if (!MemOpChains2.empty())
3027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3029 // Store the return address to the appropriate stack slot.
3030 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3031 getPointerTy(), RegInfo->getSlotSize(),
3035 // Build a sequence of copy-to-reg nodes chained together with token chain
3036 // and flag operands which copy the outgoing args into registers.
3038 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3039 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3040 RegsToPass[i].second, InFlag);
3041 InFlag = Chain.getValue(1);
3044 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3045 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3046 // In the 64-bit large code model, we have to make all calls
3047 // through a register, since the call instruction's 32-bit
3048 // pc-relative offset may not be large enough to hold the whole
3050 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3051 // If the callee is a GlobalAddress node (quite common, every direct call
3052 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3055 // We should use extra load for direct calls to dllimported functions in
3057 const GlobalValue *GV = G->getGlobal();
3058 if (!GV->hasDLLImportStorageClass()) {
3059 unsigned char OpFlags = 0;
3060 bool ExtraLoad = false;
3061 unsigned WrapperKind = ISD::DELETED_NODE;
3063 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3064 // external symbols most go through the PLT in PIC mode. If the symbol
3065 // has hidden or protected visibility, or if it is static or local, then
3066 // we don't need to use the PLT - we can directly call it.
3067 if (Subtarget->isTargetELF() &&
3068 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3069 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3070 OpFlags = X86II::MO_PLT;
3071 } else if (Subtarget->isPICStyleStubAny() &&
3072 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3073 (!Subtarget->getTargetTriple().isMacOSX() ||
3074 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3075 // PC-relative references to external symbols should go through $stub,
3076 // unless we're building with the leopard linker or later, which
3077 // automatically synthesizes these stubs.
3078 OpFlags = X86II::MO_DARWIN_STUB;
3079 } else if (Subtarget->isPICStyleRIPRel() &&
3080 isa<Function>(GV) &&
3081 cast<Function>(GV)->getAttributes().
3082 hasAttribute(AttributeSet::FunctionIndex,
3083 Attribute::NonLazyBind)) {
3084 // If the function is marked as non-lazy, generate an indirect call
3085 // which loads from the GOT directly. This avoids runtime overhead
3086 // at the cost of eager binding (and one extra byte of encoding).
3087 OpFlags = X86II::MO_GOTPCREL;
3088 WrapperKind = X86ISD::WrapperRIP;
3092 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3093 G->getOffset(), OpFlags);
3095 // Add a wrapper if needed.
3096 if (WrapperKind != ISD::DELETED_NODE)
3097 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3098 // Add extra indirection if needed.
3100 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3101 MachinePointerInfo::getGOT(),
3102 false, false, false, 0);
3104 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3105 unsigned char OpFlags = 0;
3107 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3108 // external symbols should go through the PLT.
3109 if (Subtarget->isTargetELF() &&
3110 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3121 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3123 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3124 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3125 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3128 // Returns a chain & a flag for retval copy to use.
3129 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3130 SmallVector<SDValue, 8> Ops;
3132 if (!IsSibcall && isTailCall) {
3133 Chain = DAG.getCALLSEQ_END(Chain,
3134 DAG.getIntPtrConstant(NumBytesToPop, true),
3135 DAG.getIntPtrConstant(0, true), InFlag, dl);
3136 InFlag = Chain.getValue(1);
3139 Ops.push_back(Chain);
3140 Ops.push_back(Callee);
3143 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3145 // Add argument registers to the end of the list so that they are known live
3147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3148 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3149 RegsToPass[i].second.getValueType()));
3151 // Add a register mask operand representing the call-preserved registers.
3152 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3153 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3154 assert(Mask && "Missing call preserved mask for calling convention");
3155 Ops.push_back(DAG.getRegisterMask(Mask));
3157 if (InFlag.getNode())
3158 Ops.push_back(InFlag);
3162 //// If this is the first return lowered for this function, add the regs
3163 //// to the liveout set for the function.
3164 // This isn't right, although it's probably harmless on x86; liveouts
3165 // should be computed from returns not tail calls. Consider a void
3166 // function making a tail call to a function returning int.
3167 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3170 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3171 InFlag = Chain.getValue(1);
3173 // Create the CALLSEQ_END node.
3174 unsigned NumBytesForCalleeToPop;
3175 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3176 DAG.getTarget().Options.GuaranteedTailCallOpt))
3177 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3178 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3179 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3180 SR == StackStructReturn)
3181 // If this is a call to a struct-return function, the callee
3182 // pops the hidden struct pointer, so we have to push it back.
3183 // This is common for Darwin/X86, Linux & Mingw32 targets.
3184 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3185 NumBytesForCalleeToPop = 4;
3187 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3189 // Returns a flag for retval copy to use.
3191 Chain = DAG.getCALLSEQ_END(Chain,
3192 DAG.getIntPtrConstant(NumBytesToPop, true),
3193 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3196 InFlag = Chain.getValue(1);
3199 // Handle result values, copying them out of physregs into vregs that we
3201 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3202 Ins, dl, DAG, InVals);
3205 //===----------------------------------------------------------------------===//
3206 // Fast Calling Convention (tail call) implementation
3207 //===----------------------------------------------------------------------===//
3209 // Like std call, callee cleans arguments, convention except that ECX is
3210 // reserved for storing the tail called function address. Only 2 registers are
3211 // free for argument passing (inreg). Tail call optimization is performed
3213 // * tailcallopt is enabled
3214 // * caller/callee are fastcc
3215 // On X86_64 architecture with GOT-style position independent code only local
3216 // (within module) calls are supported at the moment.
3217 // To keep the stack aligned according to platform abi the function
3218 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3219 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3220 // If a tail called function callee has more arguments than the caller the
3221 // caller needs to make sure that there is room to move the RETADDR to. This is
3222 // achieved by reserving an area the size of the argument delta right after the
3223 // original RETADDR, but before the saved framepointer or the spilled registers
3224 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3236 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3237 /// for a 16 byte align requirement.
3239 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3240 SelectionDAG& DAG) const {
3241 MachineFunction &MF = DAG.getMachineFunction();
3242 const TargetMachine &TM = MF.getTarget();
3243 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3244 TM.getSubtargetImpl()->getRegisterInfo());
3245 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3246 unsigned StackAlignment = TFI.getStackAlignment();
3247 uint64_t AlignMask = StackAlignment - 1;
3248 int64_t Offset = StackSize;
3249 unsigned SlotSize = RegInfo->getSlotSize();
3250 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3251 // Number smaller than 12 so just add the difference.
3252 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3254 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3255 Offset = ((~AlignMask) & Offset) + StackAlignment +
3256 (StackAlignment-SlotSize);
3261 /// MatchingStackOffset - Return true if the given stack call argument is
3262 /// already available in the same position (relatively) of the caller's
3263 /// incoming argument stack.
3265 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3266 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3267 const X86InstrInfo *TII) {
3268 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3270 if (Arg.getOpcode() == ISD::CopyFromReg) {
3271 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3272 if (!TargetRegisterInfo::isVirtualRegister(VR))
3274 MachineInstr *Def = MRI->getVRegDef(VR);
3277 if (!Flags.isByVal()) {
3278 if (!TII->isLoadFromStackSlot(Def, FI))
3281 unsigned Opcode = Def->getOpcode();
3282 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3283 Def->getOperand(1).isFI()) {
3284 FI = Def->getOperand(1).getIndex();
3285 Bytes = Flags.getByValSize();
3289 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3290 if (Flags.isByVal())
3291 // ByVal argument is passed in as a pointer but it's now being
3292 // dereferenced. e.g.
3293 // define @foo(%struct.X* %A) {
3294 // tail call @bar(%struct.X* byval %A)
3297 SDValue Ptr = Ld->getBasePtr();
3298 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3301 FI = FINode->getIndex();
3302 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3303 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3304 FI = FINode->getIndex();
3305 Bytes = Flags.getByValSize();
3309 assert(FI != INT_MAX);
3310 if (!MFI->isFixedObjectIndex(FI))
3312 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3315 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3316 /// for tail call optimization. Targets which want to do tail call
3317 /// optimization should implement this function.
3319 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3320 CallingConv::ID CalleeCC,
3322 bool isCalleeStructRet,
3323 bool isCallerStructRet,
3325 const SmallVectorImpl<ISD::OutputArg> &Outs,
3326 const SmallVectorImpl<SDValue> &OutVals,
3327 const SmallVectorImpl<ISD::InputArg> &Ins,
3328 SelectionDAG &DAG) const {
3329 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3332 // If -tailcallopt is specified, make fastcc functions tail-callable.
3333 const MachineFunction &MF = DAG.getMachineFunction();
3334 const Function *CallerF = MF.getFunction();
3336 // If the function return type is x86_fp80 and the callee return type is not,
3337 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3338 // perform a tailcall optimization here.
3339 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3342 CallingConv::ID CallerCC = CallerF->getCallingConv();
3343 bool CCMatch = CallerCC == CalleeCC;
3344 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3345 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3347 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3348 if (IsTailCallConvention(CalleeCC) && CCMatch)
3353 // Look for obvious safe cases to perform tail call optimization that do not
3354 // require ABI changes. This is what gcc calls sibcall.
3356 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3357 // emit a special epilogue.
3358 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3359 DAG.getSubtarget().getRegisterInfo());
3360 if (RegInfo->needsStackRealignment(MF))
3363 // Also avoid sibcall optimization if either caller or callee uses struct
3364 // return semantics.
3365 if (isCalleeStructRet || isCallerStructRet)
3368 // An stdcall/thiscall caller is expected to clean up its arguments; the
3369 // callee isn't going to do that.
3370 // FIXME: this is more restrictive than needed. We could produce a tailcall
3371 // when the stack adjustment matches. For example, with a thiscall that takes
3372 // only one argument.
3373 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3374 CallerCC == CallingConv::X86_ThisCall))
3377 // Do not sibcall optimize vararg calls unless all arguments are passed via
3379 if (isVarArg && !Outs.empty()) {
3381 // Optimizing for varargs on Win64 is unlikely to be safe without
3382 // additional testing.
3383 if (IsCalleeWin64 || IsCallerWin64)
3386 SmallVector<CCValAssign, 16> ArgLocs;
3387 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3390 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3392 if (!ArgLocs[i].isRegLoc())
3396 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3397 // stack. Therefore, if it's not used by the call it is not safe to optimize
3398 // this into a sibcall.
3399 bool Unused = false;
3400 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3407 SmallVector<CCValAssign, 16> RVLocs;
3408 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3410 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3411 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3412 CCValAssign &VA = RVLocs[i];
3413 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3418 // If the calling conventions do not match, then we'd better make sure the
3419 // results are returned in the same way as what the caller expects.
3421 SmallVector<CCValAssign, 16> RVLocs1;
3422 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3424 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3426 SmallVector<CCValAssign, 16> RVLocs2;
3427 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3429 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3431 if (RVLocs1.size() != RVLocs2.size())
3433 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3434 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3436 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3438 if (RVLocs1[i].isRegLoc()) {
3439 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3442 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3448 // If the callee takes no arguments then go on to check the results of the
3450 if (!Outs.empty()) {
3451 // Check if stack adjustment is needed. For now, do not do this if any
3452 // argument is passed on the stack.
3453 SmallVector<CCValAssign, 16> ArgLocs;
3454 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3457 // Allocate shadow area for Win64
3459 CCInfo.AllocateStack(32, 8);
3461 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3462 if (CCInfo.getNextStackOffset()) {
3463 MachineFunction &MF = DAG.getMachineFunction();
3464 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3467 // Check if the arguments are already laid out in the right way as
3468 // the caller's fixed stack objects.
3469 MachineFrameInfo *MFI = MF.getFrameInfo();
3470 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3471 const X86InstrInfo *TII =
3472 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3474 CCValAssign &VA = ArgLocs[i];
3475 SDValue Arg = OutVals[i];
3476 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3477 if (VA.getLocInfo() == CCValAssign::Indirect)
3479 if (!VA.isRegLoc()) {
3480 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3487 // If the tailcall address may be in a register, then make sure it's
3488 // possible to register allocate for it. In 32-bit, the call address can
3489 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3490 // callee-saved registers are restored. These happen to be the same
3491 // registers used to pass 'inreg' arguments so watch out for those.
3492 if (!Subtarget->is64Bit() &&
3493 ((!isa<GlobalAddressSDNode>(Callee) &&
3494 !isa<ExternalSymbolSDNode>(Callee)) ||
3495 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3496 unsigned NumInRegs = 0;
3497 // In PIC we need an extra register to formulate the address computation
3499 unsigned MaxInRegs =
3500 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3503 CCValAssign &VA = ArgLocs[i];
3506 unsigned Reg = VA.getLocReg();
3509 case X86::EAX: case X86::EDX: case X86::ECX:
3510 if (++NumInRegs == MaxInRegs)
3522 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3523 const TargetLibraryInfo *libInfo) const {
3524 return X86::createFastISel(funcInfo, libInfo);
3527 //===----------------------------------------------------------------------===//
3528 // Other Lowering Hooks
3529 //===----------------------------------------------------------------------===//
3531 static bool MayFoldLoad(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3535 static bool MayFoldIntoStore(SDValue Op) {
3536 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3539 static bool isTargetShuffle(unsigned Opcode) {
3541 default: return false;
3542 case X86ISD::BLENDI:
3543 case X86ISD::PSHUFB:
3544 case X86ISD::PSHUFD:
3545 case X86ISD::PSHUFHW:
3546 case X86ISD::PSHUFLW:
3548 case X86ISD::PALIGNR:
3549 case X86ISD::MOVLHPS:
3550 case X86ISD::MOVLHPD:
3551 case X86ISD::MOVHLPS:
3552 case X86ISD::MOVLPS:
3553 case X86ISD::MOVLPD:
3554 case X86ISD::MOVSHDUP:
3555 case X86ISD::MOVSLDUP:
3556 case X86ISD::MOVDDUP:
3559 case X86ISD::UNPCKL:
3560 case X86ISD::UNPCKH:
3561 case X86ISD::VPERMILPI:
3562 case X86ISD::VPERM2X128:
3563 case X86ISD::VPERMI:
3568 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3569 SDValue V1, SelectionDAG &DAG) {
3571 default: llvm_unreachable("Unknown x86 shuffle node");
3572 case X86ISD::MOVSHDUP:
3573 case X86ISD::MOVSLDUP:
3574 case X86ISD::MOVDDUP:
3575 return DAG.getNode(Opc, dl, VT, V1);
3579 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3580 SDValue V1, unsigned TargetMask,
3581 SelectionDAG &DAG) {
3583 default: llvm_unreachable("Unknown x86 shuffle node");
3584 case X86ISD::PSHUFD:
3585 case X86ISD::PSHUFHW:
3586 case X86ISD::PSHUFLW:
3587 case X86ISD::VPERMILPI:
3588 case X86ISD::VPERMI:
3589 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3593 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3594 SDValue V1, SDValue V2, unsigned TargetMask,
3595 SelectionDAG &DAG) {
3597 default: llvm_unreachable("Unknown x86 shuffle node");
3598 case X86ISD::PALIGNR:
3599 case X86ISD::VALIGN:
3601 case X86ISD::VPERM2X128:
3602 return DAG.getNode(Opc, dl, VT, V1, V2,
3603 DAG.getConstant(TargetMask, MVT::i8));
3607 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3608 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3610 default: llvm_unreachable("Unknown x86 shuffle node");
3611 case X86ISD::MOVLHPS:
3612 case X86ISD::MOVLHPD:
3613 case X86ISD::MOVHLPS:
3614 case X86ISD::MOVLPS:
3615 case X86ISD::MOVLPD:
3618 case X86ISD::UNPCKL:
3619 case X86ISD::UNPCKH:
3620 return DAG.getNode(Opc, dl, VT, V1, V2);
3624 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3625 MachineFunction &MF = DAG.getMachineFunction();
3626 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3627 DAG.getSubtarget().getRegisterInfo());
3628 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3629 int ReturnAddrIndex = FuncInfo->getRAIndex();
3631 if (ReturnAddrIndex == 0) {
3632 // Set up a frame object for the return address.
3633 unsigned SlotSize = RegInfo->getSlotSize();
3634 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3637 FuncInfo->setRAIndex(ReturnAddrIndex);
3640 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3643 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3644 bool hasSymbolicDisplacement) {
3645 // Offset should fit into 32 bit immediate field.
3646 if (!isInt<32>(Offset))
3649 // If we don't have a symbolic displacement - we don't have any extra
3651 if (!hasSymbolicDisplacement)
3654 // FIXME: Some tweaks might be needed for medium code model.
3655 if (M != CodeModel::Small && M != CodeModel::Kernel)
3658 // For small code model we assume that latest object is 16MB before end of 31
3659 // bits boundary. We may also accept pretty large negative constants knowing
3660 // that all objects are in the positive half of address space.
3661 if (M == CodeModel::Small && Offset < 16*1024*1024)
3664 // For kernel code model we know that all object resist in the negative half
3665 // of 32bits address space. We may not accept negative offsets, since they may
3666 // be just off and we may accept pretty large positive ones.
3667 if (M == CodeModel::Kernel && Offset > 0)
3673 /// isCalleePop - Determines whether the callee is required to pop its
3674 /// own arguments. Callee pop is necessary to support tail calls.
3675 bool X86::isCalleePop(CallingConv::ID CallingConv,
3676 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3677 switch (CallingConv) {
3680 case CallingConv::X86_StdCall:
3681 case CallingConv::X86_FastCall:
3682 case CallingConv::X86_ThisCall:
3684 case CallingConv::Fast:
3685 case CallingConv::GHC:
3686 case CallingConv::HiPE:
3693 /// \brief Return true if the condition is an unsigned comparison operation.
3694 static bool isX86CCUnsigned(unsigned X86CC) {
3696 default: llvm_unreachable("Invalid integer condition!");
3697 case X86::COND_E: return true;
3698 case X86::COND_G: return false;
3699 case X86::COND_GE: return false;
3700 case X86::COND_L: return false;
3701 case X86::COND_LE: return false;
3702 case X86::COND_NE: return true;
3703 case X86::COND_B: return true;
3704 case X86::COND_A: return true;
3705 case X86::COND_BE: return true;
3706 case X86::COND_AE: return true;
3708 llvm_unreachable("covered switch fell through?!");
3711 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3712 /// specific condition code, returning the condition code and the LHS/RHS of the
3713 /// comparison to make.
3714 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3715 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3717 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3718 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3719 // X > -1 -> X == 0, jump !sign.
3720 RHS = DAG.getConstant(0, RHS.getValueType());
3721 return X86::COND_NS;
3723 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3724 // X < 0 -> X == 0, jump on sign.
3727 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3729 RHS = DAG.getConstant(0, RHS.getValueType());
3730 return X86::COND_LE;
3734 switch (SetCCOpcode) {
3735 default: llvm_unreachable("Invalid integer condition!");
3736 case ISD::SETEQ: return X86::COND_E;
3737 case ISD::SETGT: return X86::COND_G;
3738 case ISD::SETGE: return X86::COND_GE;
3739 case ISD::SETLT: return X86::COND_L;
3740 case ISD::SETLE: return X86::COND_LE;
3741 case ISD::SETNE: return X86::COND_NE;
3742 case ISD::SETULT: return X86::COND_B;
3743 case ISD::SETUGT: return X86::COND_A;
3744 case ISD::SETULE: return X86::COND_BE;
3745 case ISD::SETUGE: return X86::COND_AE;
3749 // First determine if it is required or is profitable to flip the operands.
3751 // If LHS is a foldable load, but RHS is not, flip the condition.
3752 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3753 !ISD::isNON_EXTLoad(RHS.getNode())) {
3754 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3755 std::swap(LHS, RHS);
3758 switch (SetCCOpcode) {
3764 std::swap(LHS, RHS);
3768 // On a floating point condition, the flags are set as follows:
3770 // 0 | 0 | 0 | X > Y
3771 // 0 | 0 | 1 | X < Y
3772 // 1 | 0 | 0 | X == Y
3773 // 1 | 1 | 1 | unordered
3774 switch (SetCCOpcode) {
3775 default: llvm_unreachable("Condcode should be pre-legalized away");
3777 case ISD::SETEQ: return X86::COND_E;
3778 case ISD::SETOLT: // flipped
3780 case ISD::SETGT: return X86::COND_A;
3781 case ISD::SETOLE: // flipped
3783 case ISD::SETGE: return X86::COND_AE;
3784 case ISD::SETUGT: // flipped
3786 case ISD::SETLT: return X86::COND_B;
3787 case ISD::SETUGE: // flipped
3789 case ISD::SETLE: return X86::COND_BE;
3791 case ISD::SETNE: return X86::COND_NE;
3792 case ISD::SETUO: return X86::COND_P;
3793 case ISD::SETO: return X86::COND_NP;
3795 case ISD::SETUNE: return X86::COND_INVALID;
3799 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3800 /// code. Current x86 isa includes the following FP cmov instructions:
3801 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3802 static bool hasFPCMov(unsigned X86CC) {
3818 /// isFPImmLegal - Returns true if the target can instruction select the
3819 /// specified FP immediate natively. If false, the legalizer will
3820 /// materialize the FP immediate as a load from a constant pool.
3821 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3822 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3823 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3829 /// \brief Returns true if it is beneficial to convert a load of a constant
3830 /// to just the constant itself.
3831 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3833 assert(Ty->isIntegerTy());
3835 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3836 if (BitSize == 0 || BitSize > 64)
3841 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3842 /// the specified range (L, H].
3843 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3844 return (Val < 0) || (Val >= Low && Val < Hi);
3847 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3848 /// specified value.
3849 static bool isUndefOrEqual(int Val, int CmpVal) {
3850 return (Val < 0 || Val == CmpVal);
3853 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3854 /// from position Pos and ending in Pos+Size, falls within the specified
3855 /// sequential range (L, L+Pos]. or is undef.
3856 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3857 unsigned Pos, unsigned Size, int Low) {
3858 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3859 if (!isUndefOrEqual(Mask[i], Low))
3864 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3865 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3866 /// the second operand.
3867 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3868 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3869 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3870 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3871 return (Mask[0] < 2 && Mask[1] < 2);
3875 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3876 /// is suitable for input to PSHUFHW.
3877 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3878 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3881 // Lower quadword copied in order or undef.
3882 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3885 // Upper quadword shuffled.
3886 for (unsigned i = 4; i != 8; ++i)
3887 if (!isUndefOrInRange(Mask[i], 4, 8))
3890 if (VT == MVT::v16i16) {
3891 // Lower quadword copied in order or undef.
3892 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3895 // Upper quadword shuffled.
3896 for (unsigned i = 12; i != 16; ++i)
3897 if (!isUndefOrInRange(Mask[i], 12, 16))
3904 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3905 /// is suitable for input to PSHUFLW.
3906 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3907 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3910 // Upper quadword copied in order.
3911 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3914 // Lower quadword shuffled.
3915 for (unsigned i = 0; i != 4; ++i)
3916 if (!isUndefOrInRange(Mask[i], 0, 4))
3919 if (VT == MVT::v16i16) {
3920 // Upper quadword copied in order.
3921 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3924 // Lower quadword shuffled.
3925 for (unsigned i = 8; i != 12; ++i)
3926 if (!isUndefOrInRange(Mask[i], 8, 12))
3933 /// \brief Return true if the mask specifies a shuffle of elements that is
3934 /// suitable for input to intralane (palignr) or interlane (valign) vector
3936 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3937 unsigned NumElts = VT.getVectorNumElements();
3938 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3939 unsigned NumLaneElts = NumElts/NumLanes;
3941 // Do not handle 64-bit element shuffles with palignr.
3942 if (NumLaneElts == 2)
3945 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3947 for (i = 0; i != NumLaneElts; ++i) {
3952 // Lane is all undef, go to next lane
3953 if (i == NumLaneElts)
3956 int Start = Mask[i+l];
3958 // Make sure its in this lane in one of the sources
3959 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3960 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3963 // If not lane 0, then we must match lane 0
3964 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3967 // Correct second source to be contiguous with first source
3968 if (Start >= (int)NumElts)
3969 Start -= NumElts - NumLaneElts;
3971 // Make sure we're shifting in the right direction.
3972 if (Start <= (int)(i+l))
3977 // Check the rest of the elements to see if they are consecutive.
3978 for (++i; i != NumLaneElts; ++i) {
3979 int Idx = Mask[i+l];
3981 // Make sure its in this lane
3982 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3983 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3986 // If not lane 0, then we must match lane 0
3987 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3990 if (Idx >= (int)NumElts)
3991 Idx -= NumElts - NumLaneElts;
3993 if (!isUndefOrEqual(Idx, Start+i))
4002 /// \brief Return true if the node specifies a shuffle of elements that is
4003 /// suitable for input to PALIGNR.
4004 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4005 const X86Subtarget *Subtarget) {
4006 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4007 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4008 VT.is512BitVector())
4009 // FIXME: Add AVX512BW.
4012 return isAlignrMask(Mask, VT, false);
4015 /// \brief Return true if the node specifies a shuffle of elements that is
4016 /// suitable for input to VALIGN.
4017 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4018 const X86Subtarget *Subtarget) {
4019 // FIXME: Add AVX512VL.
4020 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4022 return isAlignrMask(Mask, VT, true);
4025 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4026 /// the two vector operands have swapped position.
4027 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4028 unsigned NumElems) {
4029 for (unsigned i = 0; i != NumElems; ++i) {
4033 else if (idx < (int)NumElems)
4034 Mask[i] = idx + NumElems;
4036 Mask[i] = idx - NumElems;
4040 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4041 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4042 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4043 /// reverse of what x86 shuffles want.
4044 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4046 unsigned NumElems = VT.getVectorNumElements();
4047 unsigned NumLanes = VT.getSizeInBits()/128;
4048 unsigned NumLaneElems = NumElems/NumLanes;
4050 if (NumLaneElems != 2 && NumLaneElems != 4)
4053 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4054 bool symetricMaskRequired =
4055 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4057 // VSHUFPSY divides the resulting vector into 4 chunks.
4058 // The sources are also splitted into 4 chunks, and each destination
4059 // chunk must come from a different source chunk.
4061 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4062 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4064 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4065 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4067 // VSHUFPDY divides the resulting vector into 4 chunks.
4068 // The sources are also splitted into 4 chunks, and each destination
4069 // chunk must come from a different source chunk.
4071 // SRC1 => X3 X2 X1 X0
4072 // SRC2 => Y3 Y2 Y1 Y0
4074 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4076 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4077 unsigned HalfLaneElems = NumLaneElems/2;
4078 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4079 for (unsigned i = 0; i != NumLaneElems; ++i) {
4080 int Idx = Mask[i+l];
4081 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4082 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4084 // For VSHUFPSY, the mask of the second half must be the same as the
4085 // first but with the appropriate offsets. This works in the same way as
4086 // VPERMILPS works with masks.
4087 if (!symetricMaskRequired || Idx < 0)
4089 if (MaskVal[i] < 0) {
4090 MaskVal[i] = Idx - l;
4093 if ((signed)(Idx - l) != MaskVal[i])
4101 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4102 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4103 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4104 if (!VT.is128BitVector())
4107 unsigned NumElems = VT.getVectorNumElements();
4112 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4113 return isUndefOrEqual(Mask[0], 6) &&
4114 isUndefOrEqual(Mask[1], 7) &&
4115 isUndefOrEqual(Mask[2], 2) &&
4116 isUndefOrEqual(Mask[3], 3);
4119 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4120 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4122 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4123 if (!VT.is128BitVector())
4126 unsigned NumElems = VT.getVectorNumElements();
4131 return isUndefOrEqual(Mask[0], 2) &&
4132 isUndefOrEqual(Mask[1], 3) &&
4133 isUndefOrEqual(Mask[2], 2) &&
4134 isUndefOrEqual(Mask[3], 3);
4137 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4138 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4139 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4140 if (!VT.is128BitVector())
4143 unsigned NumElems = VT.getVectorNumElements();
4145 if (NumElems != 2 && NumElems != 4)
4148 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4149 if (!isUndefOrEqual(Mask[i], i + NumElems))
4152 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4153 if (!isUndefOrEqual(Mask[i], i))
4159 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4160 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4161 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4162 if (!VT.is128BitVector())
4165 unsigned NumElems = VT.getVectorNumElements();
4167 if (NumElems != 2 && NumElems != 4)
4170 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4171 if (!isUndefOrEqual(Mask[i], i))
4174 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4175 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4181 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4182 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4183 /// i. e: If all but one element come from the same vector.
4184 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4185 // TODO: Deal with AVX's VINSERTPS
4186 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4189 unsigned CorrectPosV1 = 0;
4190 unsigned CorrectPosV2 = 0;
4191 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4192 if (Mask[i] == -1) {
4200 else if (Mask[i] == i + 4)
4204 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4205 // We have 3 elements (undefs count as elements from any vector) from one
4206 // vector, and one from another.
4213 // Some special combinations that can be optimized.
4216 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4217 SelectionDAG &DAG) {
4218 MVT VT = SVOp->getSimpleValueType(0);
4221 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4224 ArrayRef<int> Mask = SVOp->getMask();
4226 // These are the special masks that may be optimized.
4227 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4228 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4229 bool MatchEvenMask = true;
4230 bool MatchOddMask = true;
4231 for (int i=0; i<8; ++i) {
4232 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4233 MatchEvenMask = false;
4234 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4235 MatchOddMask = false;
4238 if (!MatchEvenMask && !MatchOddMask)
4241 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4243 SDValue Op0 = SVOp->getOperand(0);
4244 SDValue Op1 = SVOp->getOperand(1);
4246 if (MatchEvenMask) {
4247 // Shift the second operand right to 32 bits.
4248 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4249 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4251 // Shift the first operand left to 32 bits.
4252 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4253 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4255 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4256 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4259 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4260 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4261 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4262 bool HasInt256, bool V2IsSplat = false) {
4264 assert(VT.getSizeInBits() >= 128 &&
4265 "Unsupported vector type for unpckl");
4267 unsigned NumElts = VT.getVectorNumElements();
4268 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4269 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4272 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4273 "Unsupported vector type for unpckh");
4275 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4276 unsigned NumLanes = VT.getSizeInBits()/128;
4277 unsigned NumLaneElts = NumElts/NumLanes;
4279 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4280 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4281 int BitI = Mask[l+i];
4282 int BitI1 = Mask[l+i+1];
4283 if (!isUndefOrEqual(BitI, j))
4286 if (!isUndefOrEqual(BitI1, NumElts))
4289 if (!isUndefOrEqual(BitI1, j + NumElts))
4298 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4299 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4300 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4301 bool HasInt256, bool V2IsSplat = false) {
4302 assert(VT.getSizeInBits() >= 128 &&
4303 "Unsupported vector type for unpckh");
4305 unsigned NumElts = VT.getVectorNumElements();
4306 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4307 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4310 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4311 "Unsupported vector type for unpckh");
4313 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4314 unsigned NumLanes = VT.getSizeInBits()/128;
4315 unsigned NumLaneElts = NumElts/NumLanes;
4317 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4318 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4319 int BitI = Mask[l+i];
4320 int BitI1 = Mask[l+i+1];
4321 if (!isUndefOrEqual(BitI, j))
4324 if (isUndefOrEqual(BitI1, NumElts))
4327 if (!isUndefOrEqual(BitI1, j+NumElts))
4335 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4336 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4338 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4339 unsigned NumElts = VT.getVectorNumElements();
4340 bool Is256BitVec = VT.is256BitVector();
4342 if (VT.is512BitVector())
4344 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4345 "Unsupported vector type for unpckh");
4347 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4348 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4351 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4352 // FIXME: Need a better way to get rid of this, there's no latency difference
4353 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4354 // the former later. We should also remove the "_undef" special mask.
4355 if (NumElts == 4 && Is256BitVec)
4358 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4359 // independently on 128-bit lanes.
4360 unsigned NumLanes = VT.getSizeInBits()/128;
4361 unsigned NumLaneElts = NumElts/NumLanes;
4363 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4364 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4365 int BitI = Mask[l+i];
4366 int BitI1 = Mask[l+i+1];
4368 if (!isUndefOrEqual(BitI, j))
4370 if (!isUndefOrEqual(BitI1, j))
4378 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4379 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4381 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4382 unsigned NumElts = VT.getVectorNumElements();
4384 if (VT.is512BitVector())
4387 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4388 "Unsupported vector type for unpckh");
4390 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4391 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4394 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4395 // independently on 128-bit lanes.
4396 unsigned NumLanes = VT.getSizeInBits()/128;
4397 unsigned NumLaneElts = NumElts/NumLanes;
4399 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4400 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4401 int BitI = Mask[l+i];
4402 int BitI1 = Mask[l+i+1];
4403 if (!isUndefOrEqual(BitI, j))
4405 if (!isUndefOrEqual(BitI1, j))
4412 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4413 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4414 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4415 if (!VT.is512BitVector())
4418 unsigned NumElts = VT.getVectorNumElements();
4419 unsigned HalfSize = NumElts/2;
4420 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4421 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4426 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4427 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4435 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4436 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4437 /// MOVSD, and MOVD, i.e. setting the lowest element.
4438 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4439 if (VT.getVectorElementType().getSizeInBits() < 32)
4441 if (!VT.is128BitVector())
4444 unsigned NumElts = VT.getVectorNumElements();
4446 if (!isUndefOrEqual(Mask[0], NumElts))
4449 for (unsigned i = 1; i != NumElts; ++i)
4450 if (!isUndefOrEqual(Mask[i], i))
4456 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4457 /// as permutations between 128-bit chunks or halves. As an example: this
4459 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4460 /// The first half comes from the second half of V1 and the second half from the
4461 /// the second half of V2.
4462 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4463 if (!HasFp256 || !VT.is256BitVector())
4466 // The shuffle result is divided into half A and half B. In total the two
4467 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4468 // B must come from C, D, E or F.
4469 unsigned HalfSize = VT.getVectorNumElements()/2;
4470 bool MatchA = false, MatchB = false;
4472 // Check if A comes from one of C, D, E, F.
4473 for (unsigned Half = 0; Half != 4; ++Half) {
4474 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4480 // Check if B comes from one of C, D, E, F.
4481 for (unsigned Half = 0; Half != 4; ++Half) {
4482 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4488 return MatchA && MatchB;
4491 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4492 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4493 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4494 MVT VT = SVOp->getSimpleValueType(0);
4496 unsigned HalfSize = VT.getVectorNumElements()/2;
4498 unsigned FstHalf = 0, SndHalf = 0;
4499 for (unsigned i = 0; i < HalfSize; ++i) {
4500 if (SVOp->getMaskElt(i) > 0) {
4501 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4505 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4506 if (SVOp->getMaskElt(i) > 0) {
4507 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4512 return (FstHalf | (SndHalf << 4));
4515 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4516 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4517 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4521 unsigned NumElts = VT.getVectorNumElements();
4523 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4524 for (unsigned i = 0; i != NumElts; ++i) {
4527 Imm8 |= Mask[i] << (i*2);
4532 unsigned LaneSize = 4;
4533 SmallVector<int, 4> MaskVal(LaneSize, -1);
4535 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4536 for (unsigned i = 0; i != LaneSize; ++i) {
4537 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4541 if (MaskVal[i] < 0) {
4542 MaskVal[i] = Mask[i+l] - l;
4543 Imm8 |= MaskVal[i] << (i*2);
4546 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4553 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4554 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4555 /// Note that VPERMIL mask matching is different depending whether theunderlying
4556 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4557 /// to the same elements of the low, but to the higher half of the source.
4558 /// In VPERMILPD the two lanes could be shuffled independently of each other
4559 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4560 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4561 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4562 if (VT.getSizeInBits() < 256 || EltSize < 32)
4564 bool symetricMaskRequired = (EltSize == 32);
4565 unsigned NumElts = VT.getVectorNumElements();
4567 unsigned NumLanes = VT.getSizeInBits()/128;
4568 unsigned LaneSize = NumElts/NumLanes;
4569 // 2 or 4 elements in one lane
4571 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4572 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4573 for (unsigned i = 0; i != LaneSize; ++i) {
4574 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4576 if (symetricMaskRequired) {
4577 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4578 ExpectedMaskVal[i] = Mask[i+l] - l;
4581 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4589 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4590 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4591 /// element of vector 2 and the other elements to come from vector 1 in order.
4592 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4593 bool V2IsSplat = false, bool V2IsUndef = false) {
4594 if (!VT.is128BitVector())
4597 unsigned NumOps = VT.getVectorNumElements();
4598 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4601 if (!isUndefOrEqual(Mask[0], 0))
4604 for (unsigned i = 1; i != NumOps; ++i)
4605 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4606 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4607 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4613 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4614 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4615 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4616 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4617 const X86Subtarget *Subtarget) {
4618 if (!Subtarget->hasSSE3())
4621 unsigned NumElems = VT.getVectorNumElements();
4623 if ((VT.is128BitVector() && NumElems != 4) ||
4624 (VT.is256BitVector() && NumElems != 8) ||
4625 (VT.is512BitVector() && NumElems != 16))
4628 // "i+1" is the value the indexed mask element must have
4629 for (unsigned i = 0; i != NumElems; i += 2)
4630 if (!isUndefOrEqual(Mask[i], i+1) ||
4631 !isUndefOrEqual(Mask[i+1], i+1))
4637 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4638 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4639 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4640 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4641 const X86Subtarget *Subtarget) {
4642 if (!Subtarget->hasSSE3())
4645 unsigned NumElems = VT.getVectorNumElements();
4647 if ((VT.is128BitVector() && NumElems != 4) ||
4648 (VT.is256BitVector() && NumElems != 8) ||
4649 (VT.is512BitVector() && NumElems != 16))
4652 // "i" is the value the indexed mask element must have
4653 for (unsigned i = 0; i != NumElems; i += 2)
4654 if (!isUndefOrEqual(Mask[i], i) ||
4655 !isUndefOrEqual(Mask[i+1], i))
4661 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4662 /// specifies a shuffle of elements that is suitable for input to 256-bit
4663 /// version of MOVDDUP.
4664 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4665 if (!HasFp256 || !VT.is256BitVector())
4668 unsigned NumElts = VT.getVectorNumElements();
4672 for (unsigned i = 0; i != NumElts/2; ++i)
4673 if (!isUndefOrEqual(Mask[i], 0))
4675 for (unsigned i = NumElts/2; i != NumElts; ++i)
4676 if (!isUndefOrEqual(Mask[i], NumElts/2))
4681 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4682 /// specifies a shuffle of elements that is suitable for input to 128-bit
4683 /// version of MOVDDUP.
4684 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4685 if (!VT.is128BitVector())
4688 unsigned e = VT.getVectorNumElements() / 2;
4689 for (unsigned i = 0; i != e; ++i)
4690 if (!isUndefOrEqual(Mask[i], i))
4692 for (unsigned i = 0; i != e; ++i)
4693 if (!isUndefOrEqual(Mask[e+i], i))
4698 /// isVEXTRACTIndex - Return true if the specified
4699 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4700 /// suitable for instruction that extract 128 or 256 bit vectors
4701 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4702 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4703 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4706 // The index should be aligned on a vecWidth-bit boundary.
4708 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4710 MVT VT = N->getSimpleValueType(0);
4711 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4712 bool Result = (Index * ElSize) % vecWidth == 0;
4717 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4718 /// operand specifies a subvector insert that is suitable for input to
4719 /// insertion of 128 or 256-bit subvectors
4720 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4721 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4722 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4724 // The index should be aligned on a vecWidth-bit boundary.
4726 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4728 MVT VT = N->getSimpleValueType(0);
4729 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4730 bool Result = (Index * ElSize) % vecWidth == 0;
4735 bool X86::isVINSERT128Index(SDNode *N) {
4736 return isVINSERTIndex(N, 128);
4739 bool X86::isVINSERT256Index(SDNode *N) {
4740 return isVINSERTIndex(N, 256);
4743 bool X86::isVEXTRACT128Index(SDNode *N) {
4744 return isVEXTRACTIndex(N, 128);
4747 bool X86::isVEXTRACT256Index(SDNode *N) {
4748 return isVEXTRACTIndex(N, 256);
4751 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4752 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4753 /// Handles 128-bit and 256-bit.
4754 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4755 MVT VT = N->getSimpleValueType(0);
4757 assert((VT.getSizeInBits() >= 128) &&
4758 "Unsupported vector type for PSHUF/SHUFP");
4760 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4761 // independently on 128-bit lanes.
4762 unsigned NumElts = VT.getVectorNumElements();
4763 unsigned NumLanes = VT.getSizeInBits()/128;
4764 unsigned NumLaneElts = NumElts/NumLanes;
4766 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4767 "Only supports 2, 4 or 8 elements per lane");
4769 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4771 for (unsigned i = 0; i != NumElts; ++i) {
4772 int Elt = N->getMaskElt(i);
4773 if (Elt < 0) continue;
4774 Elt &= NumLaneElts - 1;
4775 unsigned ShAmt = (i << Shift) % 8;
4776 Mask |= Elt << ShAmt;
4782 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4783 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4784 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4785 MVT VT = N->getSimpleValueType(0);
4787 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4788 "Unsupported vector type for PSHUFHW");
4790 unsigned NumElts = VT.getVectorNumElements();
4793 for (unsigned l = 0; l != NumElts; l += 8) {
4794 // 8 nodes per lane, but we only care about the last 4.
4795 for (unsigned i = 0; i < 4; ++i) {
4796 int Elt = N->getMaskElt(l+i+4);
4797 if (Elt < 0) continue;
4798 Elt &= 0x3; // only 2-bits.
4799 Mask |= Elt << (i * 2);
4806 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4807 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4808 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4809 MVT VT = N->getSimpleValueType(0);
4811 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4812 "Unsupported vector type for PSHUFHW");
4814 unsigned NumElts = VT.getVectorNumElements();
4817 for (unsigned l = 0; l != NumElts; l += 8) {
4818 // 8 nodes per lane, but we only care about the first 4.
4819 for (unsigned i = 0; i < 4; ++i) {
4820 int Elt = N->getMaskElt(l+i);
4821 if (Elt < 0) continue;
4822 Elt &= 0x3; // only 2-bits
4823 Mask |= Elt << (i * 2);
4830 /// \brief Return the appropriate immediate to shuffle the specified
4831 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4832 /// VALIGN (if Interlane is true) instructions.
4833 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4835 MVT VT = SVOp->getSimpleValueType(0);
4836 unsigned EltSize = InterLane ? 1 :
4837 VT.getVectorElementType().getSizeInBits() >> 3;
4839 unsigned NumElts = VT.getVectorNumElements();
4840 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4841 unsigned NumLaneElts = NumElts/NumLanes;
4845 for (i = 0; i != NumElts; ++i) {
4846 Val = SVOp->getMaskElt(i);
4850 if (Val >= (int)NumElts)
4851 Val -= NumElts - NumLaneElts;
4853 assert(Val - i > 0 && "PALIGNR imm should be positive");
4854 return (Val - i) * EltSize;
4857 /// \brief Return the appropriate immediate to shuffle the specified
4858 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4859 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4860 return getShuffleAlignrImmediate(SVOp, false);
4863 /// \brief Return the appropriate immediate to shuffle the specified
4864 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4865 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4866 return getShuffleAlignrImmediate(SVOp, true);
4870 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4871 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4872 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4873 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4876 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4878 MVT VecVT = N->getOperand(0).getSimpleValueType();
4879 MVT ElVT = VecVT.getVectorElementType();
4881 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4882 return Index / NumElemsPerChunk;
4885 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4886 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4887 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4888 llvm_unreachable("Illegal insert subvector for VINSERT");
4891 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4893 MVT VecVT = N->getSimpleValueType(0);
4894 MVT ElVT = VecVT.getVectorElementType();
4896 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4897 return Index / NumElemsPerChunk;
4900 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4901 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4902 /// and VINSERTI128 instructions.
4903 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4904 return getExtractVEXTRACTImmediate(N, 128);
4907 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4908 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4909 /// and VINSERTI64x4 instructions.
4910 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4911 return getExtractVEXTRACTImmediate(N, 256);
4914 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4915 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4916 /// and VINSERTI128 instructions.
4917 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4918 return getInsertVINSERTImmediate(N, 128);
4921 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4922 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4923 /// and VINSERTI64x4 instructions.
4924 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4925 return getInsertVINSERTImmediate(N, 256);
4928 /// isZero - Returns true if Elt is a constant integer zero
4929 static bool isZero(SDValue V) {
4930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4931 return C && C->isNullValue();
4934 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4936 bool X86::isZeroNode(SDValue Elt) {
4939 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4940 return CFP->getValueAPF().isPosZero();
4944 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4945 /// match movhlps. The lower half elements should come from upper half of
4946 /// V1 (and in order), and the upper half elements should come from the upper
4947 /// half of V2 (and in order).
4948 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4949 if (!VT.is128BitVector())
4951 if (VT.getVectorNumElements() != 4)
4953 for (unsigned i = 0, e = 2; i != e; ++i)
4954 if (!isUndefOrEqual(Mask[i], i+2))
4956 for (unsigned i = 2; i != 4; ++i)
4957 if (!isUndefOrEqual(Mask[i], i+4))
4962 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4963 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4965 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4966 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4968 N = N->getOperand(0).getNode();
4969 if (!ISD::isNON_EXTLoad(N))
4972 *LD = cast<LoadSDNode>(N);
4976 // Test whether the given value is a vector value which will be legalized
4978 static bool WillBeConstantPoolLoad(SDNode *N) {
4979 if (N->getOpcode() != ISD::BUILD_VECTOR)
4982 // Check for any non-constant elements.
4983 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4984 switch (N->getOperand(i).getNode()->getOpcode()) {
4986 case ISD::ConstantFP:
4993 // Vectors of all-zeros and all-ones are materialized with special
4994 // instructions rather than being loaded.
4995 return !ISD::isBuildVectorAllZeros(N) &&
4996 !ISD::isBuildVectorAllOnes(N);
4999 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5000 /// match movlp{s|d}. The lower half elements should come from lower half of
5001 /// V1 (and in order), and the upper half elements should come from the upper
5002 /// half of V2 (and in order). And since V1 will become the source of the
5003 /// MOVLP, it must be either a vector load or a scalar load to vector.
5004 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5005 ArrayRef<int> Mask, MVT VT) {
5006 if (!VT.is128BitVector())
5009 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5011 // Is V2 is a vector load, don't do this transformation. We will try to use
5012 // load folding shufps op.
5013 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5016 unsigned NumElems = VT.getVectorNumElements();
5018 if (NumElems != 2 && NumElems != 4)
5020 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5021 if (!isUndefOrEqual(Mask[i], i))
5023 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5024 if (!isUndefOrEqual(Mask[i], i+NumElems))
5029 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5030 /// to an zero vector.
5031 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5032 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5033 SDValue V1 = N->getOperand(0);
5034 SDValue V2 = N->getOperand(1);
5035 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5036 for (unsigned i = 0; i != NumElems; ++i) {
5037 int Idx = N->getMaskElt(i);
5038 if (Idx >= (int)NumElems) {
5039 unsigned Opc = V2.getOpcode();
5040 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5042 if (Opc != ISD::BUILD_VECTOR ||
5043 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5045 } else if (Idx >= 0) {
5046 unsigned Opc = V1.getOpcode();
5047 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5049 if (Opc != ISD::BUILD_VECTOR ||
5050 !X86::isZeroNode(V1.getOperand(Idx)))
5057 /// getZeroVector - Returns a vector of specified type with all zero elements.
5059 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5060 SelectionDAG &DAG, SDLoc dl) {
5061 assert(VT.isVector() && "Expected a vector type");
5063 // Always build SSE zero vectors as <4 x i32> bitcasted
5064 // to their dest type. This ensures they get CSE'd.
5066 if (VT.is128BitVector()) { // SSE
5067 if (Subtarget->hasSSE2()) { // SSE2
5068 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5069 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5071 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5072 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5074 } else if (VT.is256BitVector()) { // AVX
5075 if (Subtarget->hasInt256()) { // AVX2
5076 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5077 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5078 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5080 // 256-bit logic and arithmetic instructions in AVX are all
5081 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5082 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5083 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5084 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5086 } else if (VT.is512BitVector()) { // AVX-512
5087 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5088 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5089 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5090 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5091 } else if (VT.getScalarType() == MVT::i1) {
5092 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5093 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5094 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5095 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5097 llvm_unreachable("Unexpected vector type");
5099 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5102 /// getOnesVector - Returns a vector of specified type with all bits set.
5103 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5104 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5105 /// Then bitcast to their original type, ensuring they get CSE'd.
5106 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5108 assert(VT.isVector() && "Expected a vector type");
5110 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5112 if (VT.is256BitVector()) {
5113 if (HasInt256) { // AVX2
5114 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5115 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5117 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5118 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5120 } else if (VT.is128BitVector()) {
5121 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5123 llvm_unreachable("Unexpected vector type");
5125 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5128 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5129 /// that point to V2 points to its first element.
5130 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5131 for (unsigned i = 0; i != NumElems; ++i) {
5132 if (Mask[i] > (int)NumElems) {
5138 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5139 /// operation of specified width.
5140 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5142 unsigned NumElems = VT.getVectorNumElements();
5143 SmallVector<int, 8> Mask;
5144 Mask.push_back(NumElems);
5145 for (unsigned i = 1; i != NumElems; ++i)
5147 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5150 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5151 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5153 unsigned NumElems = VT.getVectorNumElements();
5154 SmallVector<int, 8> Mask;
5155 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5157 Mask.push_back(i + NumElems);
5159 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5162 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5163 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5165 unsigned NumElems = VT.getVectorNumElements();
5166 SmallVector<int, 8> Mask;
5167 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5168 Mask.push_back(i + Half);
5169 Mask.push_back(i + NumElems + Half);
5171 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5174 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5175 // a generic shuffle instruction because the target has no such instructions.
5176 // Generate shuffles which repeat i16 and i8 several times until they can be
5177 // represented by v4f32 and then be manipulated by target suported shuffles.
5178 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5179 MVT VT = V.getSimpleValueType();
5180 int NumElems = VT.getVectorNumElements();
5183 while (NumElems > 4) {
5184 if (EltNo < NumElems/2) {
5185 V = getUnpackl(DAG, dl, VT, V, V);
5187 V = getUnpackh(DAG, dl, VT, V, V);
5188 EltNo -= NumElems/2;
5195 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5196 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5197 MVT VT = V.getSimpleValueType();
5200 if (VT.is128BitVector()) {
5201 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5202 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5203 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5205 } else if (VT.is256BitVector()) {
5206 // To use VPERMILPS to splat scalars, the second half of indicies must
5207 // refer to the higher part, which is a duplication of the lower one,
5208 // because VPERMILPS can only handle in-lane permutations.
5209 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5210 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5212 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5213 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5216 llvm_unreachable("Vector size not supported");
5218 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5221 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5222 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5223 MVT SrcVT = SV->getSimpleValueType(0);
5224 SDValue V1 = SV->getOperand(0);
5227 int EltNo = SV->getSplatIndex();
5228 int NumElems = SrcVT.getVectorNumElements();
5229 bool Is256BitVec = SrcVT.is256BitVector();
5231 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5232 "Unknown how to promote splat for type");
5234 // Extract the 128-bit part containing the splat element and update
5235 // the splat element index when it refers to the higher register.
5237 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5238 if (EltNo >= NumElems/2)
5239 EltNo -= NumElems/2;
5242 // All i16 and i8 vector types can't be used directly by a generic shuffle
5243 // instruction because the target has no such instruction. Generate shuffles
5244 // which repeat i16 and i8 several times until they fit in i32, and then can
5245 // be manipulated by target suported shuffles.
5246 MVT EltVT = SrcVT.getVectorElementType();
5247 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5248 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5250 // Recreate the 256-bit vector and place the same 128-bit vector
5251 // into the low and high part. This is necessary because we want
5252 // to use VPERM* to shuffle the vectors
5254 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5257 return getLegalSplat(DAG, V1, EltNo);
5260 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5261 /// vector of zero or undef vector. This produces a shuffle where the low
5262 /// element of V2 is swizzled into the zero/undef vector, landing at element
5263 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5264 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5266 const X86Subtarget *Subtarget,
5267 SelectionDAG &DAG) {
5268 MVT VT = V2.getSimpleValueType();
5270 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5271 unsigned NumElems = VT.getVectorNumElements();
5272 SmallVector<int, 16> MaskVec;
5273 for (unsigned i = 0; i != NumElems; ++i)
5274 // If this is the insertion idx, put the low elt of V2 here.
5275 MaskVec.push_back(i == Idx ? NumElems : i);
5276 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5279 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5280 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5281 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5282 /// shuffles which use a single input multiple times, and in those cases it will
5283 /// adjust the mask to only have indices within that single input.
5284 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5285 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5286 unsigned NumElems = VT.getVectorNumElements();
5290 bool IsFakeUnary = false;
5291 switch(N->getOpcode()) {
5292 case X86ISD::BLENDI:
5293 ImmN = N->getOperand(N->getNumOperands()-1);
5294 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5297 ImmN = N->getOperand(N->getNumOperands()-1);
5298 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5299 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5301 case X86ISD::UNPCKH:
5302 DecodeUNPCKHMask(VT, Mask);
5303 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5305 case X86ISD::UNPCKL:
5306 DecodeUNPCKLMask(VT, Mask);
5307 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5309 case X86ISD::MOVHLPS:
5310 DecodeMOVHLPSMask(NumElems, Mask);
5311 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5313 case X86ISD::MOVLHPS:
5314 DecodeMOVLHPSMask(NumElems, Mask);
5315 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5317 case X86ISD::PALIGNR:
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5321 case X86ISD::PSHUFD:
5322 case X86ISD::VPERMILPI:
5323 ImmN = N->getOperand(N->getNumOperands()-1);
5324 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFHW:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5332 case X86ISD::PSHUFLW:
5333 ImmN = N->getOperand(N->getNumOperands()-1);
5334 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5337 case X86ISD::PSHUFB: {
5339 SDValue MaskNode = N->getOperand(1);
5340 while (MaskNode->getOpcode() == ISD::BITCAST)
5341 MaskNode = MaskNode->getOperand(0);
5343 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5344 // If we have a build-vector, then things are easy.
5345 EVT VT = MaskNode.getValueType();
5346 assert(VT.isVector() &&
5347 "Can't produce a non-vector with a build_vector!");
5348 if (!VT.isInteger())
5351 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5353 SmallVector<uint64_t, 32> RawMask;
5354 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5355 SDValue Op = MaskNode->getOperand(i);
5356 if (Op->getOpcode() == ISD::UNDEF) {
5357 RawMask.push_back((uint64_t)SM_SentinelUndef);
5360 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5363 APInt MaskElement = CN->getAPIntValue();
5365 // We now have to decode the element which could be any integer size and
5366 // extract each byte of it.
5367 for (int j = 0; j < NumBytesPerElement; ++j) {
5368 // Note that this is x86 and so always little endian: the low byte is
5369 // the first byte of the mask.
5370 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5371 MaskElement = MaskElement.lshr(8);
5374 DecodePSHUFBMask(RawMask, Mask);
5378 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5382 SDValue Ptr = MaskLoad->getBasePtr();
5383 if (Ptr->getOpcode() == X86ISD::Wrapper)
5384 Ptr = Ptr->getOperand(0);
5386 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5387 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5390 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5391 // FIXME: Support AVX-512 here.
5392 Type *Ty = C->getType();
5393 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5394 Ty->getVectorNumElements() != 32))
5397 DecodePSHUFBMask(C, Mask);
5403 case X86ISD::VPERMI:
5404 ImmN = N->getOperand(N->getNumOperands()-1);
5405 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5409 case X86ISD::MOVSD: {
5410 // The index 0 always comes from the first element of the second source,
5411 // this is why MOVSS and MOVSD are used in the first place. The other
5412 // elements come from the other positions of the first source vector
5413 Mask.push_back(NumElems);
5414 for (unsigned i = 1; i != NumElems; ++i) {
5419 case X86ISD::VPERM2X128:
5420 ImmN = N->getOperand(N->getNumOperands()-1);
5421 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5422 if (Mask.empty()) return false;
5424 case X86ISD::MOVSLDUP:
5425 DecodeMOVSLDUPMask(VT, Mask);
5427 case X86ISD::MOVSHDUP:
5428 DecodeMOVSHDUPMask(VT, Mask);
5430 case X86ISD::MOVDDUP:
5431 case X86ISD::MOVLHPD:
5432 case X86ISD::MOVLPD:
5433 case X86ISD::MOVLPS:
5434 // Not yet implemented
5436 default: llvm_unreachable("unknown target shuffle node");
5439 // If we have a fake unary shuffle, the shuffle mask is spread across two
5440 // inputs that are actually the same node. Re-map the mask to always point
5441 // into the first input.
5444 if (M >= (int)Mask.size())
5450 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5451 /// element of the result of the vector shuffle.
5452 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5455 return SDValue(); // Limit search depth.
5457 SDValue V = SDValue(N, 0);
5458 EVT VT = V.getValueType();
5459 unsigned Opcode = V.getOpcode();
5461 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5462 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5463 int Elt = SV->getMaskElt(Index);
5466 return DAG.getUNDEF(VT.getVectorElementType());
5468 unsigned NumElems = VT.getVectorNumElements();
5469 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5470 : SV->getOperand(1);
5471 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5474 // Recurse into target specific vector shuffles to find scalars.
5475 if (isTargetShuffle(Opcode)) {
5476 MVT ShufVT = V.getSimpleValueType();
5477 unsigned NumElems = ShufVT.getVectorNumElements();
5478 SmallVector<int, 16> ShuffleMask;
5481 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5484 int Elt = ShuffleMask[Index];
5486 return DAG.getUNDEF(ShufVT.getVectorElementType());
5488 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5490 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5494 // Actual nodes that may contain scalar elements
5495 if (Opcode == ISD::BITCAST) {
5496 V = V.getOperand(0);
5497 EVT SrcVT = V.getValueType();
5498 unsigned NumElems = VT.getVectorNumElements();
5500 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5504 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5505 return (Index == 0) ? V.getOperand(0)
5506 : DAG.getUNDEF(VT.getVectorElementType());
5508 if (V.getOpcode() == ISD::BUILD_VECTOR)
5509 return V.getOperand(Index);
5514 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5515 /// shuffle operation which come from a consecutively from a zero. The
5516 /// search can start in two different directions, from left or right.
5517 /// We count undefs as zeros until PreferredNum is reached.
5518 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5519 unsigned NumElems, bool ZerosFromLeft,
5521 unsigned PreferredNum = -1U) {
5522 unsigned NumZeros = 0;
5523 for (unsigned i = 0; i != NumElems; ++i) {
5524 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5525 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5529 if (X86::isZeroNode(Elt))
5531 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5532 NumZeros = std::min(NumZeros + 1, PreferredNum);
5540 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5541 /// correspond consecutively to elements from one of the vector operands,
5542 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5544 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5545 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5546 unsigned NumElems, unsigned &OpNum) {
5547 bool SeenV1 = false;
5548 bool SeenV2 = false;
5550 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5551 int Idx = SVOp->getMaskElt(i);
5552 // Ignore undef indicies
5556 if (Idx < (int)NumElems)
5561 // Only accept consecutive elements from the same vector
5562 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5566 OpNum = SeenV1 ? 0 : 1;
5570 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5571 /// logical left shift of a vector.
5572 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5573 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5575 SVOp->getSimpleValueType(0).getVectorNumElements();
5576 unsigned NumZeros = getNumOfConsecutiveZeros(
5577 SVOp, NumElems, false /* check zeros from right */, DAG,
5578 SVOp->getMaskElt(0));
5584 // Considering the elements in the mask that are not consecutive zeros,
5585 // check if they consecutively come from only one of the source vectors.
5587 // V1 = {X, A, B, C} 0
5589 // vector_shuffle V1, V2 <1, 2, 3, X>
5591 if (!isShuffleMaskConsecutive(SVOp,
5592 0, // Mask Start Index
5593 NumElems-NumZeros, // Mask End Index(exclusive)
5594 NumZeros, // Where to start looking in the src vector
5595 NumElems, // Number of elements in vector
5596 OpSrc)) // Which source operand ?
5601 ShVal = SVOp->getOperand(OpSrc);
5605 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5606 /// logical left shift of a vector.
5607 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5608 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5610 SVOp->getSimpleValueType(0).getVectorNumElements();
5611 unsigned NumZeros = getNumOfConsecutiveZeros(
5612 SVOp, NumElems, true /* check zeros from left */, DAG,
5613 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5619 // Considering the elements in the mask that are not consecutive zeros,
5620 // check if they consecutively come from only one of the source vectors.
5622 // 0 { A, B, X, X } = V2
5624 // vector_shuffle V1, V2 <X, X, 4, 5>
5626 if (!isShuffleMaskConsecutive(SVOp,
5627 NumZeros, // Mask Start Index
5628 NumElems, // Mask End Index(exclusive)
5629 0, // Where to start looking in the src vector
5630 NumElems, // Number of elements in vector
5631 OpSrc)) // Which source operand ?
5636 ShVal = SVOp->getOperand(OpSrc);
5640 /// isVectorShift - Returns true if the shuffle can be implemented as a
5641 /// logical left or right shift of a vector.
5642 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5643 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5644 // Although the logic below support any bitwidth size, there are no
5645 // shift instructions which handle more than 128-bit vectors.
5646 if (!SVOp->getSimpleValueType(0).is128BitVector())
5649 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5650 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5656 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5658 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5659 unsigned NumNonZero, unsigned NumZero,
5661 const X86Subtarget* Subtarget,
5662 const TargetLowering &TLI) {
5669 for (unsigned i = 0; i < 16; ++i) {
5670 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5671 if (ThisIsNonZero && First) {
5673 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5675 V = DAG.getUNDEF(MVT::v8i16);
5680 SDValue ThisElt, LastElt;
5681 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5682 if (LastIsNonZero) {
5683 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5684 MVT::i16, Op.getOperand(i-1));
5686 if (ThisIsNonZero) {
5687 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5688 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5689 ThisElt, DAG.getConstant(8, MVT::i8));
5691 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5695 if (ThisElt.getNode())
5696 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5697 DAG.getIntPtrConstant(i/2));
5701 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5704 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5706 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5707 unsigned NumNonZero, unsigned NumZero,
5709 const X86Subtarget* Subtarget,
5710 const TargetLowering &TLI) {
5717 for (unsigned i = 0; i < 8; ++i) {
5718 bool isNonZero = (NonZeros & (1 << i)) != 0;
5722 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5724 V = DAG.getUNDEF(MVT::v8i16);
5727 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5728 MVT::v8i16, V, Op.getOperand(i),
5729 DAG.getIntPtrConstant(i));
5736 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5737 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5738 unsigned NonZeros, unsigned NumNonZero,
5739 unsigned NumZero, SelectionDAG &DAG,
5740 const X86Subtarget *Subtarget,
5741 const TargetLowering &TLI) {
5742 // We know there's at least one non-zero element
5743 unsigned FirstNonZeroIdx = 0;
5744 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5745 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5746 X86::isZeroNode(FirstNonZero)) {
5748 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5751 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5752 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5755 SDValue V = FirstNonZero.getOperand(0);
5756 MVT VVT = V.getSimpleValueType();
5757 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5760 unsigned FirstNonZeroDst =
5761 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5762 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5763 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5764 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5766 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5767 SDValue Elem = Op.getOperand(Idx);
5768 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5771 // TODO: What else can be here? Deal with it.
5772 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5775 // TODO: Some optimizations are still possible here
5776 // ex: Getting one element from a vector, and the rest from another.
5777 if (Elem.getOperand(0) != V)
5780 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5783 else if (IncorrectIdx == -1U) {
5787 // There was already one element with an incorrect index.
5788 // We can't optimize this case to an insertps.
5792 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5794 EVT VT = Op.getSimpleValueType();
5795 unsigned ElementMoveMask = 0;
5796 if (IncorrectIdx == -1U)
5797 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5799 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5801 SDValue InsertpsMask =
5802 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5803 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5809 /// getVShift - Return a vector logical shift node.
5811 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5812 unsigned NumBits, SelectionDAG &DAG,
5813 const TargetLowering &TLI, SDLoc dl) {
5814 assert(VT.is128BitVector() && "Unknown type for VShift");
5815 EVT ShVT = MVT::v2i64;
5816 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5817 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5818 return DAG.getNode(ISD::BITCAST, dl, VT,
5819 DAG.getNode(Opc, dl, ShVT, SrcOp,
5820 DAG.getConstant(NumBits,
5821 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5825 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5827 // Check if the scalar load can be widened into a vector load. And if
5828 // the address is "base + cst" see if the cst can be "absorbed" into
5829 // the shuffle mask.
5830 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5831 SDValue Ptr = LD->getBasePtr();
5832 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5834 EVT PVT = LD->getValueType(0);
5835 if (PVT != MVT::i32 && PVT != MVT::f32)
5840 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5841 FI = FINode->getIndex();
5843 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5844 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5845 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5846 Offset = Ptr.getConstantOperandVal(1);
5847 Ptr = Ptr.getOperand(0);
5852 // FIXME: 256-bit vector instructions don't require a strict alignment,
5853 // improve this code to support it better.
5854 unsigned RequiredAlign = VT.getSizeInBits()/8;
5855 SDValue Chain = LD->getChain();
5856 // Make sure the stack object alignment is at least 16 or 32.
5857 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5858 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5859 if (MFI->isFixedObjectIndex(FI)) {
5860 // Can't change the alignment. FIXME: It's possible to compute
5861 // the exact stack offset and reference FI + adjust offset instead.
5862 // If someone *really* cares about this. That's the way to implement it.
5865 MFI->setObjectAlignment(FI, RequiredAlign);
5869 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5870 // Ptr + (Offset & ~15).
5873 if ((Offset % RequiredAlign) & 3)
5875 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5877 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5878 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5880 int EltNo = (Offset - StartOffset) >> 2;
5881 unsigned NumElems = VT.getVectorNumElements();
5883 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5884 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5885 LD->getPointerInfo().getWithOffset(StartOffset),
5886 false, false, false, 0);
5888 SmallVector<int, 8> Mask;
5889 for (unsigned i = 0; i != NumElems; ++i)
5890 Mask.push_back(EltNo);
5892 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5898 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5899 /// vector of type 'VT', see if the elements can be replaced by a single large
5900 /// load which has the same value as a build_vector whose operands are 'elts'.
5902 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5904 /// FIXME: we'd also like to handle the case where the last elements are zero
5905 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5906 /// There's even a handy isZeroNode for that purpose.
5907 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5908 SDLoc &DL, SelectionDAG &DAG,
5909 bool isAfterLegalize) {
5910 EVT EltVT = VT.getVectorElementType();
5911 unsigned NumElems = Elts.size();
5913 LoadSDNode *LDBase = nullptr;
5914 unsigned LastLoadedElt = -1U;
5916 // For each element in the initializer, see if we've found a load or an undef.
5917 // If we don't find an initial load element, or later load elements are
5918 // non-consecutive, bail out.
5919 for (unsigned i = 0; i < NumElems; ++i) {
5920 SDValue Elt = Elts[i];
5922 if (!Elt.getNode() ||
5923 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5926 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5928 LDBase = cast<LoadSDNode>(Elt.getNode());
5932 if (Elt.getOpcode() == ISD::UNDEF)
5935 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5936 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5941 // If we have found an entire vector of loads and undefs, then return a large
5942 // load of the entire vector width starting at the base pointer. If we found
5943 // consecutive loads for the low half, generate a vzext_load node.
5944 if (LastLoadedElt == NumElems - 1) {
5946 if (isAfterLegalize &&
5947 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5950 SDValue NewLd = SDValue();
5952 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5953 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5954 LDBase->getPointerInfo(),
5955 LDBase->isVolatile(), LDBase->isNonTemporal(),
5956 LDBase->isInvariant(), 0);
5957 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5958 LDBase->getPointerInfo(),
5959 LDBase->isVolatile(), LDBase->isNonTemporal(),
5960 LDBase->isInvariant(), LDBase->getAlignment());
5962 if (LDBase->hasAnyUseOfValue(1)) {
5963 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5965 SDValue(NewLd.getNode(), 1));
5966 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5967 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5968 SDValue(NewLd.getNode(), 1));
5973 if (NumElems == 4 && LastLoadedElt == 1 &&
5974 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5975 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5976 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5978 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5979 LDBase->getPointerInfo(),
5980 LDBase->getAlignment(),
5981 false/*isVolatile*/, true/*ReadMem*/,
5984 // Make sure the newly-created LOAD is in the same position as LDBase in
5985 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5986 // update uses of LDBase's output chain to use the TokenFactor.
5987 if (LDBase->hasAnyUseOfValue(1)) {
5988 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5989 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5990 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5991 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5992 SDValue(ResNode.getNode(), 1));
5995 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6000 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6001 /// to generate a splat value for the following cases:
6002 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6003 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6004 /// a scalar load, or a constant.
6005 /// The VBROADCAST node is returned when a pattern is found,
6006 /// or SDValue() otherwise.
6007 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6008 SelectionDAG &DAG) {
6009 // VBROADCAST requires AVX.
6010 // TODO: Splats could be generated for non-AVX CPUs using SSE
6011 // instructions, but there's less potential gain for only 128-bit vectors.
6012 if (!Subtarget->hasAVX())
6015 MVT VT = Op.getSimpleValueType();
6018 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6019 "Unsupported vector type for broadcast.");
6024 switch (Op.getOpcode()) {
6026 // Unknown pattern found.
6029 case ISD::BUILD_VECTOR: {
6030 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6031 BitVector UndefElements;
6032 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6034 // We need a splat of a single value to use broadcast, and it doesn't
6035 // make any sense if the value is only in one element of the vector.
6036 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6040 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6041 Ld.getOpcode() == ISD::ConstantFP);
6043 // Make sure that all of the users of a non-constant load are from the
6044 // BUILD_VECTOR node.
6045 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6050 case ISD::VECTOR_SHUFFLE: {
6051 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6053 // Shuffles must have a splat mask where the first element is
6055 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6058 SDValue Sc = Op.getOperand(0);
6059 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6060 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6062 if (!Subtarget->hasInt256())
6065 // Use the register form of the broadcast instruction available on AVX2.
6066 if (VT.getSizeInBits() >= 256)
6067 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6068 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6071 Ld = Sc.getOperand(0);
6072 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6073 Ld.getOpcode() == ISD::ConstantFP);
6075 // The scalar_to_vector node and the suspected
6076 // load node must have exactly one user.
6077 // Constants may have multiple users.
6079 // AVX-512 has register version of the broadcast
6080 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6081 Ld.getValueType().getSizeInBits() >= 32;
6082 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6089 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6090 bool IsGE256 = (VT.getSizeInBits() >= 256);
6092 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6093 // instruction to save 8 or more bytes of constant pool data.
6094 // TODO: If multiple splats are generated to load the same constant,
6095 // it may be detrimental to overall size. There needs to be a way to detect
6096 // that condition to know if this is truly a size win.
6097 const Function *F = DAG.getMachineFunction().getFunction();
6098 bool OptForSize = F->getAttributes().
6099 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6101 // Handle broadcasting a single constant scalar from the constant pool
6103 // On Sandybridge (no AVX2), it is still better to load a constant vector
6104 // from the constant pool and not to broadcast it from a scalar.
6105 // But override that restriction when optimizing for size.
6106 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6107 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6108 EVT CVT = Ld.getValueType();
6109 assert(!CVT.isVector() && "Must not broadcast a vector type");
6111 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6112 // For size optimization, also splat v2f64 and v2i64, and for size opt
6113 // with AVX2, also splat i8 and i16.
6114 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6115 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6116 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6117 const Constant *C = nullptr;
6118 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6119 C = CI->getConstantIntValue();
6120 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6121 C = CF->getConstantFPValue();
6123 assert(C && "Invalid constant type");
6125 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6126 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6127 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6128 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6129 MachinePointerInfo::getConstantPool(),
6130 false, false, false, Alignment);
6132 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6136 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6138 // Handle AVX2 in-register broadcasts.
6139 if (!IsLoad && Subtarget->hasInt256() &&
6140 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6141 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6143 // The scalar source must be a normal load.
6147 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6148 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6150 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6151 // double since there is no vbroadcastsd xmm
6152 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6153 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6154 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6157 // Unsupported broadcast.
6161 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6162 /// underlying vector and index.
6164 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6166 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6168 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6169 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6172 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6174 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6176 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6177 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6180 // In this case the vector is the extract_subvector expression and the index
6181 // is 2, as specified by the shuffle.
6182 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6183 SDValue ShuffleVec = SVOp->getOperand(0);
6184 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6185 assert(ShuffleVecVT.getVectorElementType() ==
6186 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6188 int ShuffleIdx = SVOp->getMaskElt(Idx);
6189 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6190 ExtractedFromVec = ShuffleVec;
6196 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6197 MVT VT = Op.getSimpleValueType();
6199 // Skip if insert_vec_elt is not supported.
6200 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6201 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6205 unsigned NumElems = Op.getNumOperands();
6209 SmallVector<unsigned, 4> InsertIndices;
6210 SmallVector<int, 8> Mask(NumElems, -1);
6212 for (unsigned i = 0; i != NumElems; ++i) {
6213 unsigned Opc = Op.getOperand(i).getOpcode();
6215 if (Opc == ISD::UNDEF)
6218 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6219 // Quit if more than 1 elements need inserting.
6220 if (InsertIndices.size() > 1)
6223 InsertIndices.push_back(i);
6227 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6228 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6229 // Quit if non-constant index.
6230 if (!isa<ConstantSDNode>(ExtIdx))
6232 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6234 // Quit if extracted from vector of different type.
6235 if (ExtractedFromVec.getValueType() != VT)
6238 if (!VecIn1.getNode())
6239 VecIn1 = ExtractedFromVec;
6240 else if (VecIn1 != ExtractedFromVec) {
6241 if (!VecIn2.getNode())
6242 VecIn2 = ExtractedFromVec;
6243 else if (VecIn2 != ExtractedFromVec)
6244 // Quit if more than 2 vectors to shuffle
6248 if (ExtractedFromVec == VecIn1)
6250 else if (ExtractedFromVec == VecIn2)
6251 Mask[i] = Idx + NumElems;
6254 if (!VecIn1.getNode())
6257 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6258 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6259 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6260 unsigned Idx = InsertIndices[i];
6261 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6262 DAG.getIntPtrConstant(Idx));
6268 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6270 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6272 MVT VT = Op.getSimpleValueType();
6273 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6274 "Unexpected type in LowerBUILD_VECTORvXi1!");
6277 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6278 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6279 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6280 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6283 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6284 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6285 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6286 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6289 bool AllContants = true;
6290 uint64_t Immediate = 0;
6291 int NonConstIdx = -1;
6292 bool IsSplat = true;
6293 unsigned NumNonConsts = 0;
6294 unsigned NumConsts = 0;
6295 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6296 SDValue In = Op.getOperand(idx);
6297 if (In.getOpcode() == ISD::UNDEF)
6299 if (!isa<ConstantSDNode>(In)) {
6300 AllContants = false;
6306 if (cast<ConstantSDNode>(In)->getZExtValue())
6307 Immediate |= (1ULL << idx);
6309 if (In != Op.getOperand(0))
6314 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6315 DAG.getConstant(Immediate, MVT::i16));
6316 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6317 DAG.getIntPtrConstant(0));
6320 if (NumNonConsts == 1 && NonConstIdx != 0) {
6323 SDValue VecAsImm = DAG.getConstant(Immediate,
6324 MVT::getIntegerVT(VT.getSizeInBits()));
6325 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6328 DstVec = DAG.getUNDEF(VT);
6329 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6330 Op.getOperand(NonConstIdx),
6331 DAG.getIntPtrConstant(NonConstIdx));
6333 if (!IsSplat && (NonConstIdx != 0))
6334 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6335 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6338 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6339 DAG.getConstant(-1, SelectVT),
6340 DAG.getConstant(0, SelectVT));
6342 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6343 DAG.getConstant((Immediate | 1), SelectVT),
6344 DAG.getConstant(Immediate, SelectVT));
6345 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6348 /// \brief Return true if \p N implements a horizontal binop and return the
6349 /// operands for the horizontal binop into V0 and V1.
6351 /// This is a helper function of PerformBUILD_VECTORCombine.
6352 /// This function checks that the build_vector \p N in input implements a
6353 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6354 /// operation to match.
6355 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6356 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6357 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6360 /// This function only analyzes elements of \p N whose indices are
6361 /// in range [BaseIdx, LastIdx).
6362 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6364 unsigned BaseIdx, unsigned LastIdx,
6365 SDValue &V0, SDValue &V1) {
6366 EVT VT = N->getValueType(0);
6368 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6369 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6370 "Invalid Vector in input!");
6372 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6373 bool CanFold = true;
6374 unsigned ExpectedVExtractIdx = BaseIdx;
6375 unsigned NumElts = LastIdx - BaseIdx;
6376 V0 = DAG.getUNDEF(VT);
6377 V1 = DAG.getUNDEF(VT);
6379 // Check if N implements a horizontal binop.
6380 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6381 SDValue Op = N->getOperand(i + BaseIdx);
6384 if (Op->getOpcode() == ISD::UNDEF) {
6385 // Update the expected vector extract index.
6386 if (i * 2 == NumElts)
6387 ExpectedVExtractIdx = BaseIdx;
6388 ExpectedVExtractIdx += 2;
6392 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6397 SDValue Op0 = Op.getOperand(0);
6398 SDValue Op1 = Op.getOperand(1);
6400 // Try to match the following pattern:
6401 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6402 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6403 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6404 Op0.getOperand(0) == Op1.getOperand(0) &&
6405 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6406 isa<ConstantSDNode>(Op1.getOperand(1)));
6410 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6411 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6413 if (i * 2 < NumElts) {
6414 if (V0.getOpcode() == ISD::UNDEF)
6415 V0 = Op0.getOperand(0);
6417 if (V1.getOpcode() == ISD::UNDEF)
6418 V1 = Op0.getOperand(0);
6419 if (i * 2 == NumElts)
6420 ExpectedVExtractIdx = BaseIdx;
6423 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6424 if (I0 == ExpectedVExtractIdx)
6425 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6426 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6427 // Try to match the following dag sequence:
6428 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6429 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6433 ExpectedVExtractIdx += 2;
6439 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6440 /// a concat_vector.
6442 /// This is a helper function of PerformBUILD_VECTORCombine.
6443 /// This function expects two 256-bit vectors called V0 and V1.
6444 /// At first, each vector is split into two separate 128-bit vectors.
6445 /// Then, the resulting 128-bit vectors are used to implement two
6446 /// horizontal binary operations.
6448 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6450 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6451 /// the two new horizontal binop.
6452 /// When Mode is set, the first horizontal binop dag node would take as input
6453 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6454 /// horizontal binop dag node would take as input the lower 128-bit of V1
6455 /// and the upper 128-bit of V1.
6457 /// HADD V0_LO, V0_HI
6458 /// HADD V1_LO, V1_HI
6460 /// Otherwise, the first horizontal binop dag node takes as input the lower
6461 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6462 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6464 /// HADD V0_LO, V1_LO
6465 /// HADD V0_HI, V1_HI
6467 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6468 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6469 /// the upper 128-bits of the result.
6470 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6471 SDLoc DL, SelectionDAG &DAG,
6472 unsigned X86Opcode, bool Mode,
6473 bool isUndefLO, bool isUndefHI) {
6474 EVT VT = V0.getValueType();
6475 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6476 "Invalid nodes in input!");
6478 unsigned NumElts = VT.getVectorNumElements();
6479 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6480 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6481 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6482 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6483 EVT NewVT = V0_LO.getValueType();
6485 SDValue LO = DAG.getUNDEF(NewVT);
6486 SDValue HI = DAG.getUNDEF(NewVT);
6489 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6490 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6491 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6492 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6493 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6495 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6496 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6497 V1_LO->getOpcode() != ISD::UNDEF))
6498 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6500 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6501 V1_HI->getOpcode() != ISD::UNDEF))
6502 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6505 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6508 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6509 /// sequence of 'vadd + vsub + blendi'.
6510 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6511 const X86Subtarget *Subtarget) {
6513 EVT VT = BV->getValueType(0);
6514 unsigned NumElts = VT.getVectorNumElements();
6515 SDValue InVec0 = DAG.getUNDEF(VT);
6516 SDValue InVec1 = DAG.getUNDEF(VT);
6518 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6519 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6521 // Odd-numbered elements in the input build vector are obtained from
6522 // adding two integer/float elements.
6523 // Even-numbered elements in the input build vector are obtained from
6524 // subtracting two integer/float elements.
6525 unsigned ExpectedOpcode = ISD::FSUB;
6526 unsigned NextExpectedOpcode = ISD::FADD;
6527 bool AddFound = false;
6528 bool SubFound = false;
6530 for (unsigned i = 0, e = NumElts; i != e; i++) {
6531 SDValue Op = BV->getOperand(i);
6533 // Skip 'undef' values.
6534 unsigned Opcode = Op.getOpcode();
6535 if (Opcode == ISD::UNDEF) {
6536 std::swap(ExpectedOpcode, NextExpectedOpcode);
6540 // Early exit if we found an unexpected opcode.
6541 if (Opcode != ExpectedOpcode)
6544 SDValue Op0 = Op.getOperand(0);
6545 SDValue Op1 = Op.getOperand(1);
6547 // Try to match the following pattern:
6548 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6549 // Early exit if we cannot match that sequence.
6550 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6551 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6552 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6553 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6554 Op0.getOperand(1) != Op1.getOperand(1))
6557 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6561 // We found a valid add/sub node. Update the information accordingly.
6567 // Update InVec0 and InVec1.
6568 if (InVec0.getOpcode() == ISD::UNDEF)
6569 InVec0 = Op0.getOperand(0);
6570 if (InVec1.getOpcode() == ISD::UNDEF)
6571 InVec1 = Op1.getOperand(0);
6573 // Make sure that operands in input to each add/sub node always
6574 // come from a same pair of vectors.
6575 if (InVec0 != Op0.getOperand(0)) {
6576 if (ExpectedOpcode == ISD::FSUB)
6579 // FADD is commutable. Try to commute the operands
6580 // and then test again.
6581 std::swap(Op0, Op1);
6582 if (InVec0 != Op0.getOperand(0))
6586 if (InVec1 != Op1.getOperand(0))
6589 // Update the pair of expected opcodes.
6590 std::swap(ExpectedOpcode, NextExpectedOpcode);
6593 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6594 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6595 InVec1.getOpcode() != ISD::UNDEF)
6596 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6601 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6602 const X86Subtarget *Subtarget) {
6604 EVT VT = N->getValueType(0);
6605 unsigned NumElts = VT.getVectorNumElements();
6606 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6607 SDValue InVec0, InVec1;
6609 // Try to match an ADDSUB.
6610 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6611 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6612 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6613 if (Value.getNode())
6617 // Try to match horizontal ADD/SUB.
6618 unsigned NumUndefsLO = 0;
6619 unsigned NumUndefsHI = 0;
6620 unsigned Half = NumElts/2;
6622 // Count the number of UNDEF operands in the build_vector in input.
6623 for (unsigned i = 0, e = Half; i != e; ++i)
6624 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6627 for (unsigned i = Half, e = NumElts; i != e; ++i)
6628 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6631 // Early exit if this is either a build_vector of all UNDEFs or all the
6632 // operands but one are UNDEF.
6633 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6636 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6637 // Try to match an SSE3 float HADD/HSUB.
6638 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6639 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6641 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6642 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6643 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6644 // Try to match an SSSE3 integer HADD/HSUB.
6645 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6646 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6648 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6649 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6652 if (!Subtarget->hasAVX())
6655 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6656 // Try to match an AVX horizontal add/sub of packed single/double
6657 // precision floating point values from 256-bit vectors.
6658 SDValue InVec2, InVec3;
6659 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6660 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6661 ((InVec0.getOpcode() == ISD::UNDEF ||
6662 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6663 ((InVec1.getOpcode() == ISD::UNDEF ||
6664 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6665 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6667 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6668 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6669 ((InVec0.getOpcode() == ISD::UNDEF ||
6670 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6671 ((InVec1.getOpcode() == ISD::UNDEF ||
6672 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6673 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6674 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6675 // Try to match an AVX2 horizontal add/sub of signed integers.
6676 SDValue InVec2, InVec3;
6678 bool CanFold = true;
6680 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6681 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6682 ((InVec0.getOpcode() == ISD::UNDEF ||
6683 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6684 ((InVec1.getOpcode() == ISD::UNDEF ||
6685 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6686 X86Opcode = X86ISD::HADD;
6687 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6688 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6689 ((InVec0.getOpcode() == ISD::UNDEF ||
6690 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6691 ((InVec1.getOpcode() == ISD::UNDEF ||
6692 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6693 X86Opcode = X86ISD::HSUB;
6698 // Fold this build_vector into a single horizontal add/sub.
6699 // Do this only if the target has AVX2.
6700 if (Subtarget->hasAVX2())
6701 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6703 // Do not try to expand this build_vector into a pair of horizontal
6704 // add/sub if we can emit a pair of scalar add/sub.
6705 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6708 // Convert this build_vector into a pair of horizontal binop followed by
6710 bool isUndefLO = NumUndefsLO == Half;
6711 bool isUndefHI = NumUndefsHI == Half;
6712 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6713 isUndefLO, isUndefHI);
6717 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6718 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6720 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6721 X86Opcode = X86ISD::HADD;
6722 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6723 X86Opcode = X86ISD::HSUB;
6724 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6725 X86Opcode = X86ISD::FHADD;
6726 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6727 X86Opcode = X86ISD::FHSUB;
6731 // Don't try to expand this build_vector into a pair of horizontal add/sub
6732 // if we can simply emit a pair of scalar add/sub.
6733 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6736 // Convert this build_vector into two horizontal add/sub followed by
6738 bool isUndefLO = NumUndefsLO == Half;
6739 bool isUndefHI = NumUndefsHI == Half;
6740 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6741 isUndefLO, isUndefHI);
6748 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6751 MVT VT = Op.getSimpleValueType();
6752 MVT ExtVT = VT.getVectorElementType();
6753 unsigned NumElems = Op.getNumOperands();
6755 // Generate vectors for predicate vectors.
6756 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6757 return LowerBUILD_VECTORvXi1(Op, DAG);
6759 // Vectors containing all zeros can be matched by pxor and xorps later
6760 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6761 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6762 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6763 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6766 return getZeroVector(VT, Subtarget, DAG, dl);
6769 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6770 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6771 // vpcmpeqd on 256-bit vectors.
6772 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6773 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6776 if (!VT.is512BitVector())
6777 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6780 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6781 if (Broadcast.getNode())
6784 unsigned EVTBits = ExtVT.getSizeInBits();
6786 unsigned NumZero = 0;
6787 unsigned NumNonZero = 0;
6788 unsigned NonZeros = 0;
6789 bool IsAllConstants = true;
6790 SmallSet<SDValue, 8> Values;
6791 for (unsigned i = 0; i < NumElems; ++i) {
6792 SDValue Elt = Op.getOperand(i);
6793 if (Elt.getOpcode() == ISD::UNDEF)
6796 if (Elt.getOpcode() != ISD::Constant &&
6797 Elt.getOpcode() != ISD::ConstantFP)
6798 IsAllConstants = false;
6799 if (X86::isZeroNode(Elt))
6802 NonZeros |= (1 << i);
6807 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6808 if (NumNonZero == 0)
6809 return DAG.getUNDEF(VT);
6811 // Special case for single non-zero, non-undef, element.
6812 if (NumNonZero == 1) {
6813 unsigned Idx = countTrailingZeros(NonZeros);
6814 SDValue Item = Op.getOperand(Idx);
6816 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6817 // the value are obviously zero, truncate the value to i32 and do the
6818 // insertion that way. Only do this if the value is non-constant or if the
6819 // value is a constant being inserted into element 0. It is cheaper to do
6820 // a constant pool load than it is to do a movd + shuffle.
6821 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6822 (!IsAllConstants || Idx == 0)) {
6823 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6825 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6826 EVT VecVT = MVT::v4i32;
6827 unsigned VecElts = 4;
6829 // Truncate the value (which may itself be a constant) to i32, and
6830 // convert it to a vector with movd (S2V+shuffle to zero extend).
6831 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6832 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6834 // If using the new shuffle lowering, just directly insert this.
6835 if (ExperimentalVectorShuffleLowering)
6837 ISD::BITCAST, dl, VT,
6838 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6840 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6842 // Now we have our 32-bit value zero extended in the low element of
6843 // a vector. If Idx != 0, swizzle it into place.
6845 SmallVector<int, 4> Mask;
6846 Mask.push_back(Idx);
6847 for (unsigned i = 1; i != VecElts; ++i)
6849 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6852 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6856 // If we have a constant or non-constant insertion into the low element of
6857 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6858 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6859 // depending on what the source datatype is.
6862 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6864 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6865 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6866 if (VT.is256BitVector() || VT.is512BitVector()) {
6867 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6868 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6869 Item, DAG.getIntPtrConstant(0));
6871 assert(VT.is128BitVector() && "Expected an SSE value type!");
6872 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6873 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6874 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6877 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6878 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6879 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6880 if (VT.is256BitVector()) {
6881 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6882 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6884 assert(VT.is128BitVector() && "Expected an SSE value type!");
6885 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6887 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6891 // Is it a vector logical left shift?
6892 if (NumElems == 2 && Idx == 1 &&
6893 X86::isZeroNode(Op.getOperand(0)) &&
6894 !X86::isZeroNode(Op.getOperand(1))) {
6895 unsigned NumBits = VT.getSizeInBits();
6896 return getVShift(true, VT,
6897 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6898 VT, Op.getOperand(1)),
6899 NumBits/2, DAG, *this, dl);
6902 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6905 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6906 // is a non-constant being inserted into an element other than the low one,
6907 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6908 // movd/movss) to move this into the low element, then shuffle it into
6910 if (EVTBits == 32) {
6911 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6913 // If using the new shuffle lowering, just directly insert this.
6914 if (ExperimentalVectorShuffleLowering)
6915 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6917 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6918 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6919 SmallVector<int, 8> MaskVec;
6920 for (unsigned i = 0; i != NumElems; ++i)
6921 MaskVec.push_back(i == Idx ? 0 : 1);
6922 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6926 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6927 if (Values.size() == 1) {
6928 if (EVTBits == 32) {
6929 // Instead of a shuffle like this:
6930 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6931 // Check if it's possible to issue this instead.
6932 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6933 unsigned Idx = countTrailingZeros(NonZeros);
6934 SDValue Item = Op.getOperand(Idx);
6935 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6936 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6941 // A vector full of immediates; various special cases are already
6942 // handled, so this is best done with a single constant-pool load.
6946 // For AVX-length vectors, build the individual 128-bit pieces and use
6947 // shuffles to put them in place.
6948 if (VT.is256BitVector() || VT.is512BitVector()) {
6949 SmallVector<SDValue, 64> V;
6950 for (unsigned i = 0; i != NumElems; ++i)
6951 V.push_back(Op.getOperand(i));
6953 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6955 // Build both the lower and upper subvector.
6956 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6957 makeArrayRef(&V[0], NumElems/2));
6958 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6959 makeArrayRef(&V[NumElems / 2], NumElems/2));
6961 // Recreate the wider vector with the lower and upper part.
6962 if (VT.is256BitVector())
6963 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6964 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6967 // Let legalizer expand 2-wide build_vectors.
6968 if (EVTBits == 64) {
6969 if (NumNonZero == 1) {
6970 // One half is zero or undef.
6971 unsigned Idx = countTrailingZeros(NonZeros);
6972 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6973 Op.getOperand(Idx));
6974 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6979 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6980 if (EVTBits == 8 && NumElems == 16) {
6981 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6983 if (V.getNode()) return V;
6986 if (EVTBits == 16 && NumElems == 8) {
6987 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6989 if (V.getNode()) return V;
6992 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6993 if (EVTBits == 32 && NumElems == 4) {
6994 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6995 NumZero, DAG, Subtarget, *this);
7000 // If element VT is == 32 bits, turn it into a number of shuffles.
7001 SmallVector<SDValue, 8> V(NumElems);
7002 if (NumElems == 4 && NumZero > 0) {
7003 for (unsigned i = 0; i < 4; ++i) {
7004 bool isZero = !(NonZeros & (1 << i));
7006 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7008 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7011 for (unsigned i = 0; i < 2; ++i) {
7012 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7015 V[i] = V[i*2]; // Must be a zero vector.
7018 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7021 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7024 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7029 bool Reverse1 = (NonZeros & 0x3) == 2;
7030 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7034 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7035 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7037 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7040 if (Values.size() > 1 && VT.is128BitVector()) {
7041 // Check for a build vector of consecutive loads.
7042 for (unsigned i = 0; i < NumElems; ++i)
7043 V[i] = Op.getOperand(i);
7045 // Check for elements which are consecutive loads.
7046 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7050 // Check for a build vector from mostly shuffle plus few inserting.
7051 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7055 // For SSE 4.1, use insertps to put the high elements into the low element.
7056 if (getSubtarget()->hasSSE41()) {
7058 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7059 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7061 Result = DAG.getUNDEF(VT);
7063 for (unsigned i = 1; i < NumElems; ++i) {
7064 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7065 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7066 Op.getOperand(i), DAG.getIntPtrConstant(i));
7071 // Otherwise, expand into a number of unpckl*, start by extending each of
7072 // our (non-undef) elements to the full vector width with the element in the
7073 // bottom slot of the vector (which generates no code for SSE).
7074 for (unsigned i = 0; i < NumElems; ++i) {
7075 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7076 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7078 V[i] = DAG.getUNDEF(VT);
7081 // Next, we iteratively mix elements, e.g. for v4f32:
7082 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7083 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7084 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7085 unsigned EltStride = NumElems >> 1;
7086 while (EltStride != 0) {
7087 for (unsigned i = 0; i < EltStride; ++i) {
7088 // If V[i+EltStride] is undef and this is the first round of mixing,
7089 // then it is safe to just drop this shuffle: V[i] is already in the
7090 // right place, the one element (since it's the first round) being
7091 // inserted as undef can be dropped. This isn't safe for successive
7092 // rounds because they will permute elements within both vectors.
7093 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7094 EltStride == NumElems/2)
7097 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7106 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7107 // to create 256-bit vectors from two other 128-bit ones.
7108 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7110 MVT ResVT = Op.getSimpleValueType();
7112 assert((ResVT.is256BitVector() ||
7113 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7115 SDValue V1 = Op.getOperand(0);
7116 SDValue V2 = Op.getOperand(1);
7117 unsigned NumElems = ResVT.getVectorNumElements();
7118 if(ResVT.is256BitVector())
7119 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7121 if (Op.getNumOperands() == 4) {
7122 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7123 ResVT.getVectorNumElements()/2);
7124 SDValue V3 = Op.getOperand(2);
7125 SDValue V4 = Op.getOperand(3);
7126 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7127 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7129 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7132 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7133 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7134 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7135 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7136 Op.getNumOperands() == 4)));
7138 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7139 // from two other 128-bit ones.
7141 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7142 return LowerAVXCONCAT_VECTORS(Op, DAG);
7146 //===----------------------------------------------------------------------===//
7147 // Vector shuffle lowering
7149 // This is an experimental code path for lowering vector shuffles on x86. It is
7150 // designed to handle arbitrary vector shuffles and blends, gracefully
7151 // degrading performance as necessary. It works hard to recognize idiomatic
7152 // shuffles and lower them to optimal instruction patterns without leaving
7153 // a framework that allows reasonably efficient handling of all vector shuffle
7155 //===----------------------------------------------------------------------===//
7157 /// \brief Tiny helper function to identify a no-op mask.
7159 /// This is a somewhat boring predicate function. It checks whether the mask
7160 /// array input, which is assumed to be a single-input shuffle mask of the kind
7161 /// used by the X86 shuffle instructions (not a fully general
7162 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7163 /// in-place shuffle are 'no-op's.
7164 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7165 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7166 if (Mask[i] != -1 && Mask[i] != i)
7171 /// \brief Helper function to classify a mask as a single-input mask.
7173 /// This isn't a generic single-input test because in the vector shuffle
7174 /// lowering we canonicalize single inputs to be the first input operand. This
7175 /// means we can more quickly test for a single input by only checking whether
7176 /// an input from the second operand exists. We also assume that the size of
7177 /// mask corresponds to the size of the input vectors which isn't true in the
7178 /// fully general case.
7179 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7181 if (M >= (int)Mask.size())
7186 /// \brief Test whether there are elements crossing 128-bit lanes in this
7189 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7190 /// and we routinely test for these.
7191 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7192 int LaneSize = 128 / VT.getScalarSizeInBits();
7193 int Size = Mask.size();
7194 for (int i = 0; i < Size; ++i)
7195 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7200 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7202 /// This checks a shuffle mask to see if it is performing the same
7203 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7204 /// that it is also not lane-crossing. It may however involve a blend from the
7205 /// same lane of a second vector.
7207 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7208 /// non-trivial to compute in the face of undef lanes. The representation is
7209 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7210 /// entries from both V1 and V2 inputs to the wider mask.
7212 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7213 SmallVectorImpl<int> &RepeatedMask) {
7214 int LaneSize = 128 / VT.getScalarSizeInBits();
7215 RepeatedMask.resize(LaneSize, -1);
7216 int Size = Mask.size();
7217 for (int i = 0; i < Size; ++i) {
7220 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7221 // This entry crosses lanes, so there is no way to model this shuffle.
7224 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7225 if (RepeatedMask[i % LaneSize] == -1)
7226 // This is the first non-undef entry in this slot of a 128-bit lane.
7227 RepeatedMask[i % LaneSize] =
7228 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7229 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7230 // Found a mismatch with the repeated mask.
7236 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7237 // 2013 will allow us to use it as a non-type template parameter.
7240 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7242 /// See its documentation for details.
7243 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7244 if (Mask.size() != Args.size())
7246 for (int i = 0, e = Mask.size(); i < e; ++i) {
7247 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7248 if (Mask[i] != -1 && Mask[i] != *Args[i])
7256 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7259 /// This is a fast way to test a shuffle mask against a fixed pattern:
7261 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7263 /// It returns true if the mask is exactly as wide as the argument list, and
7264 /// each element of the mask is either -1 (signifying undef) or the value given
7265 /// in the argument.
7266 static const VariadicFunction1<
7267 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7269 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7271 /// This helper function produces an 8-bit shuffle immediate corresponding to
7272 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7273 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7276 /// NB: We rely heavily on "undef" masks preserving the input lane.
7277 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7278 SelectionDAG &DAG) {
7279 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7280 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7281 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7282 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7283 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7286 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7287 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7288 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7289 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7290 return DAG.getConstant(Imm, MVT::i8);
7293 /// \brief Try to emit a blend instruction for a shuffle.
7295 /// This doesn't do any checks for the availability of instructions for blending
7296 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7297 /// be matched in the backend with the type given. What it does check for is
7298 /// that the shuffle mask is in fact a blend.
7299 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7300 SDValue V2, ArrayRef<int> Mask,
7301 const X86Subtarget *Subtarget,
7302 SelectionDAG &DAG) {
7304 unsigned BlendMask = 0;
7305 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7306 if (Mask[i] >= Size) {
7307 if (Mask[i] != i + Size)
7308 return SDValue(); // Shuffled V2 input!
7309 BlendMask |= 1u << i;
7312 if (Mask[i] >= 0 && Mask[i] != i)
7313 return SDValue(); // Shuffled V1 input!
7315 switch (VT.SimpleTy) {
7320 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7321 DAG.getConstant(BlendMask, MVT::i8));
7325 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7329 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7330 // that instruction.
7331 if (Subtarget->hasAVX2()) {
7332 // Scale the blend by the number of 32-bit dwords per element.
7333 int Scale = VT.getScalarSizeInBits() / 32;
7335 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7336 if (Mask[i] >= Size)
7337 for (int j = 0; j < Scale; ++j)
7338 BlendMask |= 1u << (i * Scale + j);
7340 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7341 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7342 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7343 return DAG.getNode(ISD::BITCAST, DL, VT,
7344 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7345 DAG.getConstant(BlendMask, MVT::i8)));
7349 // For integer shuffles we need to expand the mask and cast the inputs to
7350 // v8i16s prior to blending.
7351 int Scale = 8 / VT.getVectorNumElements();
7353 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7354 if (Mask[i] >= Size)
7355 for (int j = 0; j < Scale; ++j)
7356 BlendMask |= 1u << (i * Scale + j);
7358 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7359 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7360 return DAG.getNode(ISD::BITCAST, DL, VT,
7361 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7362 DAG.getConstant(BlendMask, MVT::i8)));
7366 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7367 SmallVector<int, 8> RepeatedMask;
7368 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7369 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7370 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7372 for (int i = 0; i < 8; ++i)
7373 if (RepeatedMask[i] >= 16)
7374 BlendMask |= 1u << i;
7375 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7376 DAG.getConstant(BlendMask, MVT::i8));
7381 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7382 SDValue PBLENDVMask[32];
7383 // Scale the blend by the number of bytes per element.
7384 int Scale = VT.getScalarSizeInBits() / 8;
7385 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7386 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7387 for (int j = 0; j < Scale; ++j)
7388 PBLENDVMask[Scale * i + j] =
7389 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7390 : DAG.getConstant(Mask[i] < Size ? 0 : 0x80, MVT::i8);
7392 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7393 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7395 ISD::BITCAST, DL, VT,
7396 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7397 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PBLENDVMask),
7402 llvm_unreachable("Not a supported integer vector type!");
7406 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7407 /// unblended shuffles followed by an unshuffled blend.
7409 /// This matches the extremely common pattern for handling combined
7410 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7412 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7416 SelectionDAG &DAG) {
7417 // Shuffle the input elements into the desired positions in V1 and V2 and
7418 // blend them together.
7419 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7420 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7421 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7422 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7423 if (Mask[i] >= 0 && Mask[i] < Size) {
7424 V1Mask[i] = Mask[i];
7426 } else if (Mask[i] >= Size) {
7427 V2Mask[i] = Mask[i] - Size;
7428 BlendMask[i] = i + Size;
7431 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7432 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7433 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7436 /// \brief Try to lower a vector shuffle as a byte rotation.
7438 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7439 /// byte-rotation of a the concatentation of two vectors. This routine will
7440 /// try to generically lower a vector shuffle through such an instruction. It
7441 /// does not check for the availability of PALIGNR-based lowerings, only the
7442 /// applicability of this strategy to the given mask. This matches shuffle
7443 /// vectors that look like:
7445 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7447 /// Essentially it concatenates V1 and V2, shifts right by some number of
7448 /// elements, and takes the low elements as the result. Note that while this is
7449 /// specified as a *right shift* because x86 is little-endian, it is a *left
7450 /// rotate* of the vector lanes.
7452 /// Note that this only handles 128-bit vector widths currently.
7453 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7456 SelectionDAG &DAG) {
7457 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7459 // We need to detect various ways of spelling a rotation:
7460 // [11, 12, 13, 14, 15, 0, 1, 2]
7461 // [-1, 12, 13, 14, -1, -1, 1, -1]
7462 // [-1, -1, -1, -1, -1, -1, 1, 2]
7463 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7464 // [-1, 4, 5, 6, -1, -1, 9, -1]
7465 // [-1, 4, 5, 6, -1, -1, -1, -1]
7468 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7471 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7473 // Based on the mod-Size value of this mask element determine where
7474 // a rotated vector would have started.
7475 int StartIdx = i - (Mask[i] % Size);
7477 // The identity rotation isn't interesting, stop.
7480 // If we found the tail of a vector the rotation must be the missing
7481 // front. If we found the head of a vector, it must be how much of the head.
7482 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7485 Rotation = CandidateRotation;
7486 else if (Rotation != CandidateRotation)
7487 // The rotations don't match, so we can't match this mask.
7490 // Compute which value this mask is pointing at.
7491 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7493 // Compute which of the two target values this index should be assigned to.
7494 // This reflects whether the high elements are remaining or the low elements
7496 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7498 // Either set up this value if we've not encountered it before, or check
7499 // that it remains consistent.
7502 else if (TargetV != MaskV)
7503 // This may be a rotation, but it pulls from the inputs in some
7504 // unsupported interleaving.
7508 // Check that we successfully analyzed the mask, and normalize the results.
7509 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7510 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7516 // Cast the inputs to v16i8 to match PALIGNR.
7517 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7518 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7520 assert(VT.getSizeInBits() == 128 &&
7521 "Rotate-based lowering only supports 128-bit lowering!");
7522 assert(Mask.size() <= 16 &&
7523 "Can shuffle at most 16 bytes in a 128-bit vector!");
7524 // The actual rotate instruction rotates bytes, so we need to scale the
7525 // rotation based on how many bytes are in the vector.
7526 int Scale = 16 / Mask.size();
7528 return DAG.getNode(ISD::BITCAST, DL, VT,
7529 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7530 DAG.getConstant(Rotation * Scale, MVT::i8)));
7533 /// \brief Compute whether each element of a shuffle is zeroable.
7535 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7536 /// Either it is an undef element in the shuffle mask, the element of the input
7537 /// referenced is undef, or the element of the input referenced is known to be
7538 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7539 /// as many lanes with this technique as possible to simplify the remaining
7541 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7542 SDValue V1, SDValue V2) {
7543 SmallBitVector Zeroable(Mask.size(), false);
7545 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7546 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7548 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7550 // Handle the easy cases.
7551 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7556 // If this is an index into a build_vector node, dig out the input value and
7558 SDValue V = M < Size ? V1 : V2;
7559 if (V.getOpcode() != ISD::BUILD_VECTOR)
7562 SDValue Input = V.getOperand(M % Size);
7563 // The UNDEF opcode check really should be dead code here, but not quite
7564 // worth asserting on (it isn't invalid, just unexpected).
7565 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7572 /// \brief Lower a vector shuffle as a zero or any extension.
7574 /// Given a specific number of elements, element bit width, and extension
7575 /// stride, produce either a zero or any extension based on the available
7576 /// features of the subtarget.
7577 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7578 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7579 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7580 assert(Scale > 1 && "Need a scale to extend.");
7581 int EltBits = VT.getSizeInBits() / NumElements;
7582 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7583 "Only 8, 16, and 32 bit elements can be extended.");
7584 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7586 // Found a valid zext mask! Try various lowering strategies based on the
7587 // input type and available ISA extensions.
7588 if (Subtarget->hasSSE41()) {
7589 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7590 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7591 NumElements / Scale);
7592 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7593 return DAG.getNode(ISD::BITCAST, DL, VT,
7594 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7597 // For any extends we can cheat for larger element sizes and use shuffle
7598 // instructions that can fold with a load and/or copy.
7599 if (AnyExt && EltBits == 32) {
7600 int PSHUFDMask[4] = {0, -1, 1, -1};
7602 ISD::BITCAST, DL, VT,
7603 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7604 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7605 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7607 if (AnyExt && EltBits == 16 && Scale > 2) {
7608 int PSHUFDMask[4] = {0, -1, 0, -1};
7609 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7610 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7611 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7612 int PSHUFHWMask[4] = {1, -1, -1, -1};
7614 ISD::BITCAST, DL, VT,
7615 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7616 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7617 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7620 // If this would require more than 2 unpack instructions to expand, use
7621 // pshufb when available. We can only use more than 2 unpack instructions
7622 // when zero extending i8 elements which also makes it easier to use pshufb.
7623 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7624 assert(NumElements == 16 && "Unexpected byte vector width!");
7625 SDValue PSHUFBMask[16];
7626 for (int i = 0; i < 16; ++i)
7628 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7629 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7630 return DAG.getNode(ISD::BITCAST, DL, VT,
7631 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7632 DAG.getNode(ISD::BUILD_VECTOR, DL,
7633 MVT::v16i8, PSHUFBMask)));
7636 // Otherwise emit a sequence of unpacks.
7638 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7639 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7640 : getZeroVector(InputVT, Subtarget, DAG, DL);
7641 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7642 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7646 } while (Scale > 1);
7647 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7650 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7652 /// This routine will try to do everything in its power to cleverly lower
7653 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7654 /// check for the profitability of this lowering, it tries to aggressively
7655 /// match this pattern. It will use all of the micro-architectural details it
7656 /// can to emit an efficient lowering. It handles both blends with all-zero
7657 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7658 /// masking out later).
7660 /// The reason we have dedicated lowering for zext-style shuffles is that they
7661 /// are both incredibly common and often quite performance sensitive.
7662 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7663 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7664 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7665 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7667 int Bits = VT.getSizeInBits();
7668 int NumElements = Mask.size();
7670 // Define a helper function to check a particular ext-scale and lower to it if
7672 auto Lower = [&](int Scale) -> SDValue {
7675 for (int i = 0; i < NumElements; ++i) {
7677 continue; // Valid anywhere but doesn't tell us anything.
7678 if (i % Scale != 0) {
7679 // Each of the extend elements needs to be zeroable.
7683 // We no lorger are in the anyext case.
7688 // Each of the base elements needs to be consecutive indices into the
7689 // same input vector.
7690 SDValue V = Mask[i] < NumElements ? V1 : V2;
7693 else if (InputV != V)
7694 return SDValue(); // Flip-flopping inputs.
7696 if (Mask[i] % NumElements != i / Scale)
7697 return SDValue(); // Non-consecutive strided elemenst.
7700 // If we fail to find an input, we have a zero-shuffle which should always
7701 // have already been handled.
7702 // FIXME: Maybe handle this here in case during blending we end up with one?
7706 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7707 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7710 // The widest scale possible for extending is to a 64-bit integer.
7711 assert(Bits % 64 == 0 &&
7712 "The number of bits in a vector must be divisible by 64 on x86!");
7713 int NumExtElements = Bits / 64;
7715 // Each iteration, try extending the elements half as much, but into twice as
7717 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7718 assert(NumElements % NumExtElements == 0 &&
7719 "The input vector size must be divisble by the extended size.");
7720 if (SDValue V = Lower(NumElements / NumExtElements))
7724 // No viable ext lowering found.
7728 /// \brief Try to lower insertion of a single element into a zero vector.
7730 /// This is a common pattern that we have especially efficient patterns to lower
7731 /// across all subtarget feature sets.
7732 static SDValue lowerVectorShuffleAsElementInsertion(
7733 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7734 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7735 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7737 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7738 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7740 if (Mask.size() == 2) {
7741 if (!Zeroable[V2Index ^ 1]) {
7742 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7743 // with 2 to flip from {2,3} to {0,1} and vice versa.
7744 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7745 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7746 if (Zeroable[V2Index])
7747 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7753 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7754 if (i != V2Index && !Zeroable[i])
7755 return SDValue(); // Not inserting into a zero vector.
7758 // Step over any bitcasts on either input so we can scan the actual
7759 // BUILD_VECTOR nodes.
7760 while (V1.getOpcode() == ISD::BITCAST)
7761 V1 = V1.getOperand(0);
7762 while (V2.getOpcode() == ISD::BITCAST)
7763 V2 = V2.getOperand(0);
7765 // Check for a single input from a SCALAR_TO_VECTOR node.
7766 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7767 // all the smarts here sunk into that routine. However, the current
7768 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7769 // vector shuffle lowering is dead.
7770 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7771 Mask[V2Index] == (int)Mask.size()) ||
7772 V2.getOpcode() == ISD::BUILD_VECTOR))
7775 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7777 // First, we need to zext the scalar if it is smaller than an i32.
7779 MVT EltVT = VT.getVectorElementType();
7780 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7781 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7782 // Zero-extend directly to i32.
7784 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7787 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7788 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7790 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7793 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7794 // the desired position. Otherwise it is more efficient to do a vector
7795 // shift left. We know that we can do a vector shift left because all
7796 // the inputs are zero.
7797 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7798 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7799 V2Shuffle[V2Index] = 0;
7800 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7802 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7804 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7806 V2Index * EltVT.getSizeInBits(),
7807 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7808 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7814 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7816 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7817 /// support for floating point shuffles but not integer shuffles. These
7818 /// instructions will incur a domain crossing penalty on some chips though so
7819 /// it is better to avoid lowering through this for integer vectors where
7821 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7822 const X86Subtarget *Subtarget,
7823 SelectionDAG &DAG) {
7825 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7826 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7827 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7828 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7829 ArrayRef<int> Mask = SVOp->getMask();
7830 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7832 if (isSingleInputShuffleMask(Mask)) {
7833 // Straight shuffle of a single input vector. Simulate this by using the
7834 // single input as both of the "inputs" to this instruction..
7835 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7837 if (Subtarget->hasAVX()) {
7838 // If we have AVX, we can use VPERMILPS which will allow folding a load
7839 // into the shuffle.
7840 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7841 DAG.getConstant(SHUFPDMask, MVT::i8));
7844 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7845 DAG.getConstant(SHUFPDMask, MVT::i8));
7847 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7848 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7850 // Use dedicated unpack instructions for masks that match their pattern.
7851 if (isShuffleEquivalent(Mask, 0, 2))
7852 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7853 if (isShuffleEquivalent(Mask, 1, 3))
7854 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7856 // If we have a single input, insert that into V1 if we can do so cheaply.
7857 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7858 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7859 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7862 if (Subtarget->hasSSE41())
7863 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7867 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7868 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7869 DAG.getConstant(SHUFPDMask, MVT::i8));
7872 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7874 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7875 /// the integer unit to minimize domain crossing penalties. However, for blends
7876 /// it falls back to the floating point shuffle operation with appropriate bit
7878 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7879 const X86Subtarget *Subtarget,
7880 SelectionDAG &DAG) {
7882 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7883 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7884 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7885 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7886 ArrayRef<int> Mask = SVOp->getMask();
7887 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7889 if (isSingleInputShuffleMask(Mask)) {
7890 // Straight shuffle of a single input vector. For everything from SSE2
7891 // onward this has a single fast instruction with no scary immediates.
7892 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7893 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7894 int WidenedMask[4] = {
7895 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7896 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7898 ISD::BITCAST, DL, MVT::v2i64,
7899 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7900 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7903 // Use dedicated unpack instructions for masks that match their pattern.
7904 if (isShuffleEquivalent(Mask, 0, 2))
7905 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7906 if (isShuffleEquivalent(Mask, 1, 3))
7907 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7909 // If we have a single input from V2 insert that into V1 if we can do so
7911 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7912 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7913 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7916 if (Subtarget->hasSSE41())
7917 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7921 // Try to use rotation instructions if available.
7922 if (Subtarget->hasSSSE3())
7923 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7924 DL, MVT::v2i64, V1, V2, Mask, DAG))
7927 // We implement this with SHUFPD which is pretty lame because it will likely
7928 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7929 // However, all the alternatives are still more cycles and newer chips don't
7930 // have this problem. It would be really nice if x86 had better shuffles here.
7931 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7932 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7933 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7934 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7937 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7939 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7940 /// It makes no assumptions about whether this is the *best* lowering, it simply
7942 static SDValue lowerVectorShuffleWithSHUPFS(SDLoc DL, MVT VT,
7943 ArrayRef<int> Mask, SDValue V1,
7944 SDValue V2, SelectionDAG &DAG) {
7945 SDValue LowV = V1, HighV = V2;
7946 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7949 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7951 if (NumV2Elements == 1) {
7953 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7956 // Compute the index adjacent to V2Index and in the same half by toggling
7958 int V2AdjIndex = V2Index ^ 1;
7960 if (Mask[V2AdjIndex] == -1) {
7961 // Handles all the cases where we have a single V2 element and an undef.
7962 // This will only ever happen in the high lanes because we commute the
7963 // vector otherwise.
7965 std::swap(LowV, HighV);
7966 NewMask[V2Index] -= 4;
7968 // Handle the case where the V2 element ends up adjacent to a V1 element.
7969 // To make this work, blend them together as the first step.
7970 int V1Index = V2AdjIndex;
7971 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7972 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7973 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7975 // Now proceed to reconstruct the final blend as we have the necessary
7976 // high or low half formed.
7983 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7984 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7986 } else if (NumV2Elements == 2) {
7987 if (Mask[0] < 4 && Mask[1] < 4) {
7988 // Handle the easy case where we have V1 in the low lanes and V2 in the
7989 // high lanes. We never see this reversed because we sort the shuffle.
7993 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7994 // trying to place elements directly, just blend them and set up the final
7995 // shuffle to place them.
7997 // The first two blend mask elements are for V1, the second two are for
7999 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8000 Mask[2] < 4 ? Mask[2] : Mask[3],
8001 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8002 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8003 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8004 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8006 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8009 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8010 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8011 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8012 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8015 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8016 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8019 /// \brief Lower 4-lane 32-bit floating point shuffles.
8021 /// Uses instructions exclusively from the floating point unit to minimize
8022 /// domain crossing penalties, as these are sufficient to implement all v4f32
8024 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8025 const X86Subtarget *Subtarget,
8026 SelectionDAG &DAG) {
8028 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8029 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8030 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8031 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8032 ArrayRef<int> Mask = SVOp->getMask();
8033 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8036 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8038 if (NumV2Elements == 0) {
8039 if (Subtarget->hasAVX()) {
8040 // If we have AVX, we can use VPERMILPS which will allow folding a load
8041 // into the shuffle.
8042 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8043 getV4X86ShuffleImm8ForMask(Mask, DAG));
8046 // Otherwise, use a straight shuffle of a single input vector. We pass the
8047 // input vector to both operands to simulate this with a SHUFPS.
8048 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8049 getV4X86ShuffleImm8ForMask(Mask, DAG));
8052 // Use dedicated unpack instructions for masks that match their pattern.
8053 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8054 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8055 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8056 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8058 // There are special ways we can lower some single-element blends. However, we
8059 // have custom ways we can lower more complex single-element blends below that
8060 // we defer to if both this and BLENDPS fail to match, so restrict this to
8061 // when the V2 input is targeting element 0 of the mask -- that is the fast
8063 if (NumV2Elements == 1 && Mask[0] >= 4)
8064 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8065 Mask, Subtarget, DAG))
8068 if (Subtarget->hasSSE41())
8069 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8073 // Check for whether we can use INSERTPS to perform the blend. We only use
8074 // INSERTPS when the V1 elements are already in the correct locations
8075 // because otherwise we can just always use two SHUFPS instructions which
8076 // are much smaller to encode than a SHUFPS and an INSERTPS.
8077 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8079 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8082 // When using INSERTPS we can zero any lane of the destination. Collect
8083 // the zero inputs into a mask and drop them from the lanes of V1 which
8084 // actually need to be present as inputs to the INSERTPS.
8085 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8087 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8088 bool InsertNeedsShuffle = false;
8090 for (int i = 0; i < 4; ++i)
8094 } else if (Mask[i] != i) {
8095 InsertNeedsShuffle = true;
8100 // We don't want to use INSERTPS or other insertion techniques if it will
8101 // require shuffling anyways.
8102 if (!InsertNeedsShuffle) {
8103 // If all of V1 is zeroable, replace it with undef.
8104 if ((ZMask | 1 << V2Index) == 0xF)
8105 V1 = DAG.getUNDEF(MVT::v4f32);
8107 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8108 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8110 // Insert the V2 element into the desired position.
8111 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8112 DAG.getConstant(InsertPSMask, MVT::i8));
8116 // Otherwise fall back to a SHUFPS lowering strategy.
8117 return lowerVectorShuffleWithSHUPFS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8120 /// \brief Lower 4-lane i32 vector shuffles.
8122 /// We try to handle these with integer-domain shuffles where we can, but for
8123 /// blends we use the floating point domain blend instructions.
8124 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8125 const X86Subtarget *Subtarget,
8126 SelectionDAG &DAG) {
8128 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8129 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8130 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8131 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8132 ArrayRef<int> Mask = SVOp->getMask();
8133 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8136 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8138 if (NumV2Elements == 0) {
8139 // Straight shuffle of a single input vector. For everything from SSE2
8140 // onward this has a single fast instruction with no scary immediates.
8141 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8142 // but we aren't actually going to use the UNPCK instruction because doing
8143 // so prevents folding a load into this instruction or making a copy.
8144 const int UnpackLoMask[] = {0, 0, 1, 1};
8145 const int UnpackHiMask[] = {2, 2, 3, 3};
8146 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8147 Mask = UnpackLoMask;
8148 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8149 Mask = UnpackHiMask;
8151 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8152 getV4X86ShuffleImm8ForMask(Mask, DAG));
8155 // Whenever we can lower this as a zext, that instruction is strictly faster
8156 // than any alternative.
8157 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8158 Mask, Subtarget, DAG))
8161 // Use dedicated unpack instructions for masks that match their pattern.
8162 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8163 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8164 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8165 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8167 // There are special ways we can lower some single-element blends.
8168 if (NumV2Elements == 1)
8169 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8170 Mask, Subtarget, DAG))
8173 if (Subtarget->hasSSE41())
8174 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8178 // Try to use rotation instructions if available.
8179 if (Subtarget->hasSSSE3())
8180 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8181 DL, MVT::v4i32, V1, V2, Mask, DAG))
8184 // We implement this with SHUFPS because it can blend from two vectors.
8185 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8186 // up the inputs, bypassing domain shift penalties that we would encur if we
8187 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8189 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8190 DAG.getVectorShuffle(
8192 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8193 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8196 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8197 /// shuffle lowering, and the most complex part.
8199 /// The lowering strategy is to try to form pairs of input lanes which are
8200 /// targeted at the same half of the final vector, and then use a dword shuffle
8201 /// to place them onto the right half, and finally unpack the paired lanes into
8202 /// their final position.
8204 /// The exact breakdown of how to form these dword pairs and align them on the
8205 /// correct sides is really tricky. See the comments within the function for
8206 /// more of the details.
8207 static SDValue lowerV8I16SingleInputVectorShuffle(
8208 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8209 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8210 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8211 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8212 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8214 SmallVector<int, 4> LoInputs;
8215 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8216 [](int M) { return M >= 0; });
8217 std::sort(LoInputs.begin(), LoInputs.end());
8218 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8219 SmallVector<int, 4> HiInputs;
8220 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8221 [](int M) { return M >= 0; });
8222 std::sort(HiInputs.begin(), HiInputs.end());
8223 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8225 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8226 int NumHToL = LoInputs.size() - NumLToL;
8228 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8229 int NumHToH = HiInputs.size() - NumLToH;
8230 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8231 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8232 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8233 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8235 // Use dedicated unpack instructions for masks that match their pattern.
8236 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8237 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8238 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8239 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8241 // Try to use rotation instructions if available.
8242 if (Subtarget->hasSSSE3())
8243 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8244 DL, MVT::v8i16, V, V, Mask, DAG))
8247 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8248 // such inputs we can swap two of the dwords across the half mark and end up
8249 // with <=2 inputs to each half in each half. Once there, we can fall through
8250 // to the generic code below. For example:
8252 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8253 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8255 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8256 // and an existing 2-into-2 on the other half. In this case we may have to
8257 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8258 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8259 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8260 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8261 // half than the one we target for fixing) will be fixed when we re-enter this
8262 // path. We will also combine away any sequence of PSHUFD instructions that
8263 // result into a single instruction. Here is an example of the tricky case:
8265 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8266 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8268 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8270 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8271 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8273 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8274 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8276 // The result is fine to be handled by the generic logic.
8277 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8278 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8279 int AOffset, int BOffset) {
8280 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8281 "Must call this with A having 3 or 1 inputs from the A half.");
8282 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8283 "Must call this with B having 1 or 3 inputs from the B half.");
8284 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8285 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8287 // Compute the index of dword with only one word among the three inputs in
8288 // a half by taking the sum of the half with three inputs and subtracting
8289 // the sum of the actual three inputs. The difference is the remaining
8292 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8293 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8294 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8295 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8296 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8297 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8298 int TripleNonInputIdx =
8299 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8300 TripleDWord = TripleNonInputIdx / 2;
8302 // We use xor with one to compute the adjacent DWord to whichever one the
8304 OneInputDWord = (OneInput / 2) ^ 1;
8306 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8307 // and BToA inputs. If there is also such a problem with the BToB and AToB
8308 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8309 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8310 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8311 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8312 // Compute how many inputs will be flipped by swapping these DWords. We
8314 // to balance this to ensure we don't form a 3-1 shuffle in the other
8316 int NumFlippedAToBInputs =
8317 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8318 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8319 int NumFlippedBToBInputs =
8320 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8321 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8322 if ((NumFlippedAToBInputs == 1 &&
8323 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8324 (NumFlippedBToBInputs == 1 &&
8325 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8326 // We choose whether to fix the A half or B half based on whether that
8327 // half has zero flipped inputs. At zero, we may not be able to fix it
8328 // with that half. We also bias towards fixing the B half because that
8329 // will more commonly be the high half, and we have to bias one way.
8330 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8331 ArrayRef<int> Inputs) {
8332 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8333 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8334 PinnedIdx ^ 1) != Inputs.end();
8335 // Determine whether the free index is in the flipped dword or the
8336 // unflipped dword based on where the pinned index is. We use this bit
8337 // in an xor to conditionally select the adjacent dword.
8338 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8339 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8340 FixFreeIdx) != Inputs.end();
8341 if (IsFixIdxInput == IsFixFreeIdxInput)
8343 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8344 FixFreeIdx) != Inputs.end();
8345 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8346 "We need to be changing the number of flipped inputs!");
8347 int PSHUFHalfMask[] = {0, 1, 2, 3};
8348 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8349 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8351 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8354 if (M != -1 && M == FixIdx)
8356 else if (M != -1 && M == FixFreeIdx)
8359 if (NumFlippedBToBInputs != 0) {
8361 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8362 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8364 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8366 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8367 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8372 int PSHUFDMask[] = {0, 1, 2, 3};
8373 PSHUFDMask[ADWord] = BDWord;
8374 PSHUFDMask[BDWord] = ADWord;
8375 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8376 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8377 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8378 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8380 // Adjust the mask to match the new locations of A and B.
8382 if (M != -1 && M/2 == ADWord)
8383 M = 2 * BDWord + M % 2;
8384 else if (M != -1 && M/2 == BDWord)
8385 M = 2 * ADWord + M % 2;
8387 // Recurse back into this routine to re-compute state now that this isn't
8388 // a 3 and 1 problem.
8389 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8392 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8393 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8394 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8395 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8397 // At this point there are at most two inputs to the low and high halves from
8398 // each half. That means the inputs can always be grouped into dwords and
8399 // those dwords can then be moved to the correct half with a dword shuffle.
8400 // We use at most one low and one high word shuffle to collect these paired
8401 // inputs into dwords, and finally a dword shuffle to place them.
8402 int PSHUFLMask[4] = {-1, -1, -1, -1};
8403 int PSHUFHMask[4] = {-1, -1, -1, -1};
8404 int PSHUFDMask[4] = {-1, -1, -1, -1};
8406 // First fix the masks for all the inputs that are staying in their
8407 // original halves. This will then dictate the targets of the cross-half
8409 auto fixInPlaceInputs =
8410 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8411 MutableArrayRef<int> SourceHalfMask,
8412 MutableArrayRef<int> HalfMask, int HalfOffset) {
8413 if (InPlaceInputs.empty())
8415 if (InPlaceInputs.size() == 1) {
8416 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8417 InPlaceInputs[0] - HalfOffset;
8418 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8421 if (IncomingInputs.empty()) {
8422 // Just fix all of the in place inputs.
8423 for (int Input : InPlaceInputs) {
8424 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8425 PSHUFDMask[Input / 2] = Input / 2;
8430 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8431 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8432 InPlaceInputs[0] - HalfOffset;
8433 // Put the second input next to the first so that they are packed into
8434 // a dword. We find the adjacent index by toggling the low bit.
8435 int AdjIndex = InPlaceInputs[0] ^ 1;
8436 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8437 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8438 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8440 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8441 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8443 // Now gather the cross-half inputs and place them into a free dword of
8444 // their target half.
8445 // FIXME: This operation could almost certainly be simplified dramatically to
8446 // look more like the 3-1 fixing operation.
8447 auto moveInputsToRightHalf = [&PSHUFDMask](
8448 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8449 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8450 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8452 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8453 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8455 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8457 int LowWord = Word & ~1;
8458 int HighWord = Word | 1;
8459 return isWordClobbered(SourceHalfMask, LowWord) ||
8460 isWordClobbered(SourceHalfMask, HighWord);
8463 if (IncomingInputs.empty())
8466 if (ExistingInputs.empty()) {
8467 // Map any dwords with inputs from them into the right half.
8468 for (int Input : IncomingInputs) {
8469 // If the source half mask maps over the inputs, turn those into
8470 // swaps and use the swapped lane.
8471 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8472 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8473 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8474 Input - SourceOffset;
8475 // We have to swap the uses in our half mask in one sweep.
8476 for (int &M : HalfMask)
8477 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8479 else if (M == Input)
8480 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8482 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8483 Input - SourceOffset &&
8484 "Previous placement doesn't match!");
8486 // Note that this correctly re-maps both when we do a swap and when
8487 // we observe the other side of the swap above. We rely on that to
8488 // avoid swapping the members of the input list directly.
8489 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8492 // Map the input's dword into the correct half.
8493 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8494 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8496 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8498 "Previous placement doesn't match!");
8501 // And just directly shift any other-half mask elements to be same-half
8502 // as we will have mirrored the dword containing the element into the
8503 // same position within that half.
8504 for (int &M : HalfMask)
8505 if (M >= SourceOffset && M < SourceOffset + 4) {
8506 M = M - SourceOffset + DestOffset;
8507 assert(M >= 0 && "This should never wrap below zero!");
8512 // Ensure we have the input in a viable dword of its current half. This
8513 // is particularly tricky because the original position may be clobbered
8514 // by inputs being moved and *staying* in that half.
8515 if (IncomingInputs.size() == 1) {
8516 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8517 int InputFixed = std::find(std::begin(SourceHalfMask),
8518 std::end(SourceHalfMask), -1) -
8519 std::begin(SourceHalfMask) + SourceOffset;
8520 SourceHalfMask[InputFixed - SourceOffset] =
8521 IncomingInputs[0] - SourceOffset;
8522 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8524 IncomingInputs[0] = InputFixed;
8526 } else if (IncomingInputs.size() == 2) {
8527 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8528 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8529 // We have two non-adjacent or clobbered inputs we need to extract from
8530 // the source half. To do this, we need to map them into some adjacent
8531 // dword slot in the source mask.
8532 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8533 IncomingInputs[1] - SourceOffset};
8535 // If there is a free slot in the source half mask adjacent to one of
8536 // the inputs, place the other input in it. We use (Index XOR 1) to
8537 // compute an adjacent index.
8538 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8539 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8540 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8541 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8542 InputsFixed[1] = InputsFixed[0] ^ 1;
8543 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8544 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8545 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8546 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8547 InputsFixed[0] = InputsFixed[1] ^ 1;
8548 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8549 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8550 // The two inputs are in the same DWord but it is clobbered and the
8551 // adjacent DWord isn't used at all. Move both inputs to the free
8553 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8554 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8555 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8556 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8558 // The only way we hit this point is if there is no clobbering
8559 // (because there are no off-half inputs to this half) and there is no
8560 // free slot adjacent to one of the inputs. In this case, we have to
8561 // swap an input with a non-input.
8562 for (int i = 0; i < 4; ++i)
8563 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8564 "We can't handle any clobbers here!");
8565 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8566 "Cannot have adjacent inputs here!");
8568 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8569 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8571 // We also have to update the final source mask in this case because
8572 // it may need to undo the above swap.
8573 for (int &M : FinalSourceHalfMask)
8574 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8575 M = InputsFixed[1] + SourceOffset;
8576 else if (M == InputsFixed[1] + SourceOffset)
8577 M = (InputsFixed[0] ^ 1) + SourceOffset;
8579 InputsFixed[1] = InputsFixed[0] ^ 1;
8582 // Point everything at the fixed inputs.
8583 for (int &M : HalfMask)
8584 if (M == IncomingInputs[0])
8585 M = InputsFixed[0] + SourceOffset;
8586 else if (M == IncomingInputs[1])
8587 M = InputsFixed[1] + SourceOffset;
8589 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8590 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8593 llvm_unreachable("Unhandled input size!");
8596 // Now hoist the DWord down to the right half.
8597 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8598 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8599 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8600 for (int &M : HalfMask)
8601 for (int Input : IncomingInputs)
8603 M = FreeDWord * 2 + Input % 2;
8605 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8606 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8607 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8608 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8610 // Now enact all the shuffles we've computed to move the inputs into their
8612 if (!isNoopShuffleMask(PSHUFLMask))
8613 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8614 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8615 if (!isNoopShuffleMask(PSHUFHMask))
8616 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8617 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8618 if (!isNoopShuffleMask(PSHUFDMask))
8619 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8620 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8621 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8622 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8624 // At this point, each half should contain all its inputs, and we can then
8625 // just shuffle them into their final position.
8626 assert(std::count_if(LoMask.begin(), LoMask.end(),
8627 [](int M) { return M >= 4; }) == 0 &&
8628 "Failed to lift all the high half inputs to the low mask!");
8629 assert(std::count_if(HiMask.begin(), HiMask.end(),
8630 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8631 "Failed to lift all the low half inputs to the high mask!");
8633 // Do a half shuffle for the low mask.
8634 if (!isNoopShuffleMask(LoMask))
8635 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8636 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8638 // Do a half shuffle with the high mask after shifting its values down.
8639 for (int &M : HiMask)
8642 if (!isNoopShuffleMask(HiMask))
8643 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8644 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8649 /// \brief Detect whether the mask pattern should be lowered through
8652 /// This essentially tests whether viewing the mask as an interleaving of two
8653 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8654 /// lowering it through interleaving is a significantly better strategy.
8655 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8656 int NumEvenInputs[2] = {0, 0};
8657 int NumOddInputs[2] = {0, 0};
8658 int NumLoInputs[2] = {0, 0};
8659 int NumHiInputs[2] = {0, 0};
8660 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8664 int InputIdx = Mask[i] >= Size;
8667 ++NumLoInputs[InputIdx];
8669 ++NumHiInputs[InputIdx];
8672 ++NumEvenInputs[InputIdx];
8674 ++NumOddInputs[InputIdx];
8677 // The minimum number of cross-input results for both the interleaved and
8678 // split cases. If interleaving results in fewer cross-input results, return
8680 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8681 NumEvenInputs[0] + NumOddInputs[1]);
8682 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8683 NumLoInputs[0] + NumHiInputs[1]);
8684 return InterleavedCrosses < SplitCrosses;
8687 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8689 /// This strategy only works when the inputs from each vector fit into a single
8690 /// half of that vector, and generally there are not so many inputs as to leave
8691 /// the in-place shuffles required highly constrained (and thus expensive). It
8692 /// shifts all the inputs into a single side of both input vectors and then
8693 /// uses an unpack to interleave these inputs in a single vector. At that
8694 /// point, we will fall back on the generic single input shuffle lowering.
8695 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8697 MutableArrayRef<int> Mask,
8698 const X86Subtarget *Subtarget,
8699 SelectionDAG &DAG) {
8700 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8701 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8702 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8703 for (int i = 0; i < 8; ++i)
8704 if (Mask[i] >= 0 && Mask[i] < 4)
8705 LoV1Inputs.push_back(i);
8706 else if (Mask[i] >= 4 && Mask[i] < 8)
8707 HiV1Inputs.push_back(i);
8708 else if (Mask[i] >= 8 && Mask[i] < 12)
8709 LoV2Inputs.push_back(i);
8710 else if (Mask[i] >= 12)
8711 HiV2Inputs.push_back(i);
8713 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8714 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8717 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8718 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8719 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8721 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8722 HiV1Inputs.size() + HiV2Inputs.size();
8724 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8725 ArrayRef<int> HiInputs, bool MoveToLo,
8727 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8728 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8729 if (BadInputs.empty())
8732 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8733 int MoveOffset = MoveToLo ? 0 : 4;
8735 if (GoodInputs.empty()) {
8736 for (int BadInput : BadInputs) {
8737 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8738 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8741 if (GoodInputs.size() == 2) {
8742 // If the low inputs are spread across two dwords, pack them into
8744 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8745 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8746 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8747 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8749 // Otherwise pin the good inputs.
8750 for (int GoodInput : GoodInputs)
8751 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8754 if (BadInputs.size() == 2) {
8755 // If we have two bad inputs then there may be either one or two good
8756 // inputs fixed in place. Find a fixed input, and then find the *other*
8757 // two adjacent indices by using modular arithmetic.
8759 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8760 [](int M) { return M >= 0; }) -
8761 std::begin(MoveMask);
8763 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8764 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8765 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8766 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8767 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8768 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8769 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8771 assert(BadInputs.size() == 1 && "All sizes handled");
8772 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8773 std::end(MoveMask), -1) -
8774 std::begin(MoveMask);
8775 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8776 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8780 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8783 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8785 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8788 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8789 // cross-half traffic in the final shuffle.
8791 // Munge the mask to be a single-input mask after the unpack merges the
8795 M = 2 * (M % 4) + (M / 8);
8797 return DAG.getVectorShuffle(
8798 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8799 DL, MVT::v8i16, V1, V2),
8800 DAG.getUNDEF(MVT::v8i16), Mask);
8803 /// \brief Generic lowering of 8-lane i16 shuffles.
8805 /// This handles both single-input shuffles and combined shuffle/blends with
8806 /// two inputs. The single input shuffles are immediately delegated to
8807 /// a dedicated lowering routine.
8809 /// The blends are lowered in one of three fundamental ways. If there are few
8810 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8811 /// of the input is significantly cheaper when lowered as an interleaving of
8812 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8813 /// halves of the inputs separately (making them have relatively few inputs)
8814 /// and then concatenate them.
8815 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8816 const X86Subtarget *Subtarget,
8817 SelectionDAG &DAG) {
8819 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8820 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8821 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8822 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8823 ArrayRef<int> OrigMask = SVOp->getMask();
8824 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8825 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8826 MutableArrayRef<int> Mask(MaskStorage);
8828 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8830 // Whenever we can lower this as a zext, that instruction is strictly faster
8831 // than any alternative.
8832 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8833 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8836 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8837 auto isV2 = [](int M) { return M >= 8; };
8839 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8840 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8842 if (NumV2Inputs == 0)
8843 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8845 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8846 "to be V1-input shuffles.");
8848 // There are special ways we can lower some single-element blends.
8849 if (NumV2Inputs == 1)
8850 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8851 Mask, Subtarget, DAG))
8854 if (Subtarget->hasSSE41())
8855 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8859 // Try to use rotation instructions if available.
8860 if (Subtarget->hasSSSE3())
8861 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8864 if (NumV1Inputs + NumV2Inputs <= 4)
8865 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8867 // Check whether an interleaving lowering is likely to be more efficient.
8868 // This isn't perfect but it is a strong heuristic that tends to work well on
8869 // the kinds of shuffles that show up in practice.
8871 // FIXME: Handle 1x, 2x, and 4x interleaving.
8872 if (shouldLowerAsInterleaving(Mask)) {
8873 // FIXME: Figure out whether we should pack these into the low or high
8876 int EMask[8], OMask[8];
8877 for (int i = 0; i < 4; ++i) {
8878 EMask[i] = Mask[2*i];
8879 OMask[i] = Mask[2*i + 1];
8884 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8885 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8887 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8890 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8891 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8893 for (int i = 0; i < 4; ++i) {
8894 LoBlendMask[i] = Mask[i];
8895 HiBlendMask[i] = Mask[i + 4];
8898 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8899 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8900 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8901 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8903 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8904 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8907 /// \brief Check whether a compaction lowering can be done by dropping even
8908 /// elements and compute how many times even elements must be dropped.
8910 /// This handles shuffles which take every Nth element where N is a power of
8911 /// two. Example shuffle masks:
8913 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8914 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8915 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8916 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8917 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8918 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8920 /// Any of these lanes can of course be undef.
8922 /// This routine only supports N <= 3.
8923 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8926 /// \returns N above, or the number of times even elements must be dropped if
8927 /// there is such a number. Otherwise returns zero.
8928 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8929 // Figure out whether we're looping over two inputs or just one.
8930 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8932 // The modulus for the shuffle vector entries is based on whether this is
8933 // a single input or not.
8934 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8935 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8936 "We should only be called with masks with a power-of-2 size!");
8938 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8940 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8941 // and 2^3 simultaneously. This is because we may have ambiguity with
8942 // partially undef inputs.
8943 bool ViableForN[3] = {true, true, true};
8945 for (int i = 0, e = Mask.size(); i < e; ++i) {
8946 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8951 bool IsAnyViable = false;
8952 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8953 if (ViableForN[j]) {
8956 // The shuffle mask must be equal to (i * 2^N) % M.
8957 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8960 ViableForN[j] = false;
8962 // Early exit if we exhaust the possible powers of two.
8967 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8971 // Return 0 as there is no viable power of two.
8975 /// \brief Generic lowering of v16i8 shuffles.
8977 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8978 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8979 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8980 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8982 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8983 const X86Subtarget *Subtarget,
8984 SelectionDAG &DAG) {
8986 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8987 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8988 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8989 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8990 ArrayRef<int> OrigMask = SVOp->getMask();
8991 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8993 // Try to use rotation instructions if available.
8994 if (Subtarget->hasSSSE3())
8995 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
8999 // Try to use a zext lowering.
9000 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9001 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9004 int MaskStorage[16] = {
9005 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9006 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9007 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9008 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9009 MutableArrayRef<int> Mask(MaskStorage);
9010 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9011 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9014 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9016 // For single-input shuffles, there are some nicer lowering tricks we can use.
9017 if (NumV2Elements == 0) {
9018 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9019 // Notably, this handles splat and partial-splat shuffles more efficiently.
9020 // However, it only makes sense if the pre-duplication shuffle simplifies
9021 // things significantly. Currently, this means we need to be able to
9022 // express the pre-duplication shuffle as an i16 shuffle.
9024 // FIXME: We should check for other patterns which can be widened into an
9025 // i16 shuffle as well.
9026 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9027 for (int i = 0; i < 16; i += 2)
9028 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9033 auto tryToWidenViaDuplication = [&]() -> SDValue {
9034 if (!canWidenViaDuplication(Mask))
9036 SmallVector<int, 4> LoInputs;
9037 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9038 [](int M) { return M >= 0 && M < 8; });
9039 std::sort(LoInputs.begin(), LoInputs.end());
9040 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9042 SmallVector<int, 4> HiInputs;
9043 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9044 [](int M) { return M >= 8; });
9045 std::sort(HiInputs.begin(), HiInputs.end());
9046 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9049 bool TargetLo = LoInputs.size() >= HiInputs.size();
9050 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9051 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9053 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9054 SmallDenseMap<int, int, 8> LaneMap;
9055 for (int I : InPlaceInputs) {
9056 PreDupI16Shuffle[I/2] = I/2;
9059 int j = TargetLo ? 0 : 4, je = j + 4;
9060 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9061 // Check if j is already a shuffle of this input. This happens when
9062 // there are two adjacent bytes after we move the low one.
9063 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9064 // If we haven't yet mapped the input, search for a slot into which
9066 while (j < je && PreDupI16Shuffle[j] != -1)
9070 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9073 // Map this input with the i16 shuffle.
9074 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9077 // Update the lane map based on the mapping we ended up with.
9078 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9081 ISD::BITCAST, DL, MVT::v16i8,
9082 DAG.getVectorShuffle(MVT::v8i16, DL,
9083 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9084 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9086 // Unpack the bytes to form the i16s that will be shuffled into place.
9087 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9088 MVT::v16i8, V1, V1);
9090 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9091 for (int i = 0; i < 16; i += 2) {
9093 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9094 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
9097 ISD::BITCAST, DL, MVT::v16i8,
9098 DAG.getVectorShuffle(MVT::v8i16, DL,
9099 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9100 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9102 if (SDValue V = tryToWidenViaDuplication())
9106 // Check whether an interleaving lowering is likely to be more efficient.
9107 // This isn't perfect but it is a strong heuristic that tends to work well on
9108 // the kinds of shuffles that show up in practice.
9110 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9111 if (shouldLowerAsInterleaving(Mask)) {
9112 // FIXME: Figure out whether we should pack these into the low or high
9115 int EMask[16], OMask[16];
9116 for (int i = 0; i < 8; ++i) {
9117 EMask[i] = Mask[2*i];
9118 OMask[i] = Mask[2*i + 1];
9123 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9124 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9126 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
9129 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9130 // with PSHUFB. It is important to do this before we attempt to generate any
9131 // blends but after all of the single-input lowerings. If the single input
9132 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9133 // want to preserve that and we can DAG combine any longer sequences into
9134 // a PSHUFB in the end. But once we start blending from multiple inputs,
9135 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9136 // and there are *very* few patterns that would actually be faster than the
9137 // PSHUFB approach because of its ability to zero lanes.
9139 // FIXME: The only exceptions to the above are blends which are exact
9140 // interleavings with direct instructions supporting them. We currently don't
9141 // handle those well here.
9142 if (Subtarget->hasSSSE3()) {
9145 for (int i = 0; i < 16; ++i)
9146 if (Mask[i] == -1) {
9147 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9149 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9151 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9153 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9154 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9155 if (isSingleInputShuffleMask(Mask))
9156 return V1; // Single inputs are easy.
9158 // Otherwise, blend the two.
9159 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9160 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9161 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9164 // There are special ways we can lower some single-element blends.
9165 if (NumV2Elements == 1)
9166 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9167 Mask, Subtarget, DAG))
9170 // Check whether a compaction lowering can be done. This handles shuffles
9171 // which take every Nth element for some even N. See the helper function for
9174 // We special case these as they can be particularly efficiently handled with
9175 // the PACKUSB instruction on x86 and they show up in common patterns of
9176 // rearranging bytes to truncate wide elements.
9177 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9178 // NumEvenDrops is the power of two stride of the elements. Another way of
9179 // thinking about it is that we need to drop the even elements this many
9180 // times to get the original input.
9181 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9183 // First we need to zero all the dropped bytes.
9184 assert(NumEvenDrops <= 3 &&
9185 "No support for dropping even elements more than 3 times.");
9186 // We use the mask type to pick which bytes are preserved based on how many
9187 // elements are dropped.
9188 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9189 SDValue ByteClearMask =
9190 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9191 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9192 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9194 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9196 // Now pack things back together.
9197 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9198 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9199 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9200 for (int i = 1; i < NumEvenDrops; ++i) {
9201 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9202 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9208 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9209 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9210 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9211 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9213 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9214 MutableArrayRef<int> V1HalfBlendMask,
9215 MutableArrayRef<int> V2HalfBlendMask) {
9216 for (int i = 0; i < 8; ++i)
9217 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9218 V1HalfBlendMask[i] = HalfMask[i];
9220 } else if (HalfMask[i] >= 16) {
9221 V2HalfBlendMask[i] = HalfMask[i] - 16;
9222 HalfMask[i] = i + 8;
9225 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9226 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9228 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9230 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9231 MutableArrayRef<int> HiBlendMask) {
9233 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9234 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9236 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9237 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9238 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9239 [](int M) { return M >= 0 && M % 2 == 1; })) {
9240 // Use a mask to drop the high bytes.
9241 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9242 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9243 DAG.getConstant(0x00FF, MVT::v8i16));
9245 // This will be a single vector shuffle instead of a blend so nuke V2.
9246 V2 = DAG.getUNDEF(MVT::v8i16);
9248 // Squash the masks to point directly into V1.
9249 for (int &M : LoBlendMask)
9252 for (int &M : HiBlendMask)
9256 // Otherwise just unpack the low half of V into V1 and the high half into
9257 // V2 so that we can blend them as i16s.
9258 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9259 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9260 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9261 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9264 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9265 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9266 return std::make_pair(BlendedLo, BlendedHi);
9268 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9269 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9270 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9272 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9273 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9275 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9278 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9280 /// This routine breaks down the specific type of 128-bit shuffle and
9281 /// dispatches to the lowering routines accordingly.
9282 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9283 MVT VT, const X86Subtarget *Subtarget,
9284 SelectionDAG &DAG) {
9285 switch (VT.SimpleTy) {
9287 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9289 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9291 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9293 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9295 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9297 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9300 llvm_unreachable("Unimplemented!");
9304 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
9307 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
9308 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
9309 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
9310 /// we encode the logic here for specific shuffle lowering routines to bail to
9311 /// when they exhaust the features avaible to more directly handle the shuffle.
9312 static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
9314 const X86Subtarget *Subtarget,
9315 SelectionDAG &DAG) {
9317 MVT VT = Op.getSimpleValueType();
9318 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9319 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9320 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9321 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9322 ArrayRef<int> Mask = SVOp->getMask();
9324 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
9325 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
9327 int NumElements = VT.getVectorNumElements();
9328 int SplitNumElements = NumElements / 2;
9329 MVT ScalarVT = VT.getScalarType();
9330 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9332 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9333 DAG.getIntPtrConstant(0));
9334 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9335 DAG.getIntPtrConstant(SplitNumElements));
9336 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9337 DAG.getIntPtrConstant(0));
9338 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9339 DAG.getIntPtrConstant(SplitNumElements));
9341 // Now create two 4-way blends of these half-width vectors.
9342 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9343 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
9344 for (int i = 0; i < SplitNumElements; ++i) {
9345 int M = HalfMask[i];
9346 if (M >= NumElements) {
9347 V2BlendMask.push_back(M - NumElements);
9348 V1BlendMask.push_back(-1);
9349 BlendMask.push_back(SplitNumElements + i);
9350 } else if (M >= 0) {
9351 V2BlendMask.push_back(-1);
9352 V1BlendMask.push_back(M);
9353 BlendMask.push_back(i);
9355 V2BlendMask.push_back(-1);
9356 V1BlendMask.push_back(-1);
9357 BlendMask.push_back(-1);
9360 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9361 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9362 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9364 SDValue Lo = HalfBlend(LoMask);
9365 SDValue Hi = HalfBlend(HiMask);
9366 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9369 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9371 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9372 /// isn't available.
9373 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9374 const X86Subtarget *Subtarget,
9375 SelectionDAG &DAG) {
9377 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9378 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9379 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9380 ArrayRef<int> Mask = SVOp->getMask();
9381 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9383 if (is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask))
9384 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9386 if (isSingleInputShuffleMask(Mask)) {
9387 // Non-half-crossing single input shuffles can be lowerid with an
9388 // interleaved permutation.
9389 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9390 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9391 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9392 DAG.getConstant(VPERMILPMask, MVT::i8));
9395 // X86 has dedicated unpack instructions that can handle specific blend
9396 // operations: UNPCKH and UNPCKL.
9397 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9398 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9399 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9400 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9402 // If we have a single input to the zero element, insert that into V1 if we
9403 // can do so cheaply.
9405 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9406 if (NumV2Elements == 1 && Mask[0] >= 4)
9407 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9408 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9411 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9415 // Check if the blend happens to exactly fit that of SHUFPD.
9416 if (Mask[0] < 4 && (Mask[1] == -1 || Mask[1] >= 4) &&
9417 Mask[2] < 4 && (Mask[3] == -1 || Mask[3] >= 4)) {
9418 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9419 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9420 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9421 DAG.getConstant(SHUFPDMask, MVT::i8));
9423 if ((Mask[0] == -1 || Mask[0] >= 4) && Mask[1] < 4 &&
9424 (Mask[2] == -1 || Mask[2] >= 4) && Mask[3] < 4) {
9425 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9426 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9427 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9428 DAG.getConstant(SHUFPDMask, MVT::i8));
9431 // Otherwise fall back on generic blend lowering.
9432 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9436 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9438 /// This routine is only called when we have AVX2 and thus a reasonable
9439 /// instruction set for v4i64 shuffling..
9440 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9441 const X86Subtarget *Subtarget,
9442 SelectionDAG &DAG) {
9444 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9445 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9446 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9447 ArrayRef<int> Mask = SVOp->getMask();
9448 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9449 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9451 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9455 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9456 // use lower latency instructions that will operate on both 128-bit lanes.
9457 SmallVector<int, 2> RepeatedMask;
9458 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9459 if (isSingleInputShuffleMask(Mask)) {
9460 int PSHUFDMask[] = {-1, -1, -1, -1};
9461 for (int i = 0; i < 2; ++i)
9462 if (RepeatedMask[i] >= 0) {
9463 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9464 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9467 ISD::BITCAST, DL, MVT::v4i64,
9468 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9469 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9470 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9473 // Use dedicated unpack instructions for masks that match their pattern.
9474 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9475 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9476 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9477 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9480 // AVX2 provides a direct instruction for permuting a single input across
9482 if (isSingleInputShuffleMask(Mask))
9483 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9484 getV4X86ShuffleImm8ForMask(Mask, DAG));
9486 // Otherwise fall back on generic blend lowering.
9487 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9491 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9493 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9494 /// isn't available.
9495 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9496 const X86Subtarget *Subtarget,
9497 SelectionDAG &DAG) {
9499 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9500 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9501 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9502 ArrayRef<int> Mask = SVOp->getMask();
9503 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9505 if (is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9506 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9508 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9512 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9513 // options to efficiently lower the shuffle.
9514 SmallVector<int, 2> RepeatedMask;
9515 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9516 if (isSingleInputShuffleMask(Mask))
9517 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9518 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9520 // Use dedicated unpack instructions for masks that match their pattern.
9521 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9522 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9523 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9524 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9526 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9527 // have already handled any direct blends.
9528 int SHUFPSMask[] = {Mask[0], Mask[1], Mask[2], Mask[3]};
9529 for (int &M : SHUFPSMask)
9532 return lowerVectorShuffleWithSHUPFS(DL, MVT::v8f32, SHUFPSMask, V1, V2, DAG);
9535 // If we have a single input shuffle with different shuffle patterns in the
9536 // two 128-bit lanes use the variable mask to VPERMILPS.
9537 if (isSingleInputShuffleMask(Mask)) {
9538 SDValue VPermMask[8];
9539 for (int i = 0; i < 8; ++i)
9540 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9541 : DAG.getConstant(Mask[i], MVT::i32);
9543 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9544 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9547 // Otherwise fall back on generic blend lowering.
9548 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9552 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9554 /// This routine is only called when we have AVX2 and thus a reasonable
9555 /// instruction set for v8i32 shuffling..
9556 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9557 const X86Subtarget *Subtarget,
9558 SelectionDAG &DAG) {
9560 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9561 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9562 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9563 ArrayRef<int> Mask = SVOp->getMask();
9564 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9565 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9567 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9571 // If the shuffle mask is repeated in each 128-bit lane we can use more
9572 // efficient instructions that mirror the shuffles across the two 128-bit
9574 SmallVector<int, 4> RepeatedMask;
9575 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9576 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9577 if (isSingleInputShuffleMask(Mask))
9578 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9579 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9581 // Use dedicated unpack instructions for masks that match their pattern.
9582 if (isShuffleEquivalent(Mask, 0, 8, 1, 9))
9583 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9584 if (isShuffleEquivalent(Mask, 2, 10, 3, 11))
9585 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9588 // If the shuffle patterns aren't repeated but it is a single input, directly
9589 // generate a cross-lane VPERMD instruction.
9590 if (isSingleInputShuffleMask(Mask)) {
9591 SDValue VPermMask[8];
9592 for (int i = 0; i < 8; ++i)
9593 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9594 : DAG.getConstant(Mask[i], MVT::i32);
9596 X86ISD::VPERMV, DL, MVT::v8i32,
9597 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9600 // Otherwise fall back on generic blend lowering.
9601 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9605 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9607 /// This routine is only called when we have AVX2 and thus a reasonable
9608 /// instruction set for v16i16 shuffling..
9609 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9610 const X86Subtarget *Subtarget,
9611 SelectionDAG &DAG) {
9613 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9614 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9615 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9616 ArrayRef<int> Mask = SVOp->getMask();
9617 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9618 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9620 // There are no generalized cross-lane shuffle operations available on i16
9622 // FIXME: We should teach the "split and lower" path to do something more
9623 // clever, or do it ourselves here. The optimal lowering of cross-lane
9624 // shuffles I am aware of is to swap the lanes into a copy, shuffle both the
9625 // original and the copy, and then blend to pick up the cross-lane elements.
9626 // This is four instructions with a tree height of three which is better than
9627 // the worst case for a gather-cross-scatter approach such as used in SSE2
9628 // v8i16 lowering (where we don't have blends). While for cross-lane blends it
9629 // results in a blend tree, blends are very cheap in AVX2 and newer chips. We
9630 // might also want to special case situations where we can always do a single
9631 // VPERMD to produce a non-lane-crossing shuffle.
9632 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9633 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9635 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9639 // Use dedicated unpack instructions for masks that match their pattern.
9640 if (isShuffleEquivalent(Mask,
9641 // First 128-bit lane:
9642 0, 16, 1, 17, 2, 18, 3, 19,
9643 // Second 128-bit lane:
9644 8, 24, 9, 25, 10, 26, 11, 27))
9645 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9646 if (isShuffleEquivalent(Mask,
9647 // First 128-bit lane:
9648 4, 20, 5, 21, 6, 22, 7, 23,
9649 // Second 128-bit lane:
9650 12, 28, 13, 29, 14, 30, 15, 31))
9651 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9653 if (isSingleInputShuffleMask(Mask)) {
9654 SDValue PSHUFBMask[32];
9655 for (int i = 0; i < 16; ++i) {
9656 if (Mask[i] == -1) {
9657 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9661 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9662 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9663 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
9664 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
9667 ISD::BITCAST, DL, MVT::v16i16,
9669 X86ISD::PSHUFB, DL, MVT::v32i8,
9670 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9671 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9674 // Otherwise fall back on generic blend lowering.
9675 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i16, V1, V2,
9679 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9681 /// This routine is only called when we have AVX2 and thus a reasonable
9682 /// instruction set for v32i8 shuffling..
9683 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9684 const X86Subtarget *Subtarget,
9685 SelectionDAG &DAG) {
9687 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9688 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9689 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9690 ArrayRef<int> Mask = SVOp->getMask();
9691 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9692 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9694 // There are no generalized cross-lane shuffle operations available on i16
9696 // FIXME: We should teach the "split and lower" path to do something more
9697 // clever, or do it ourselves here. The optimal lowering of cross-lane
9698 // shuffles I am aware of is to swap the lanes into a copy, shuffle both the
9699 // original and the copy, and then blend to pick up the cross-lane elements.
9700 // This is four instructions with a tree height of three which is better than
9701 // the worst case for a gather-cross-scatter approach such as used in SSE2
9702 // v8i16 lowering (where we don't have blends). While for cross-lane blends it
9703 // results in a blend tree, blends are very cheap in AVX2 and newer chips. We
9704 // might also want to special case situations where we can always do a single
9705 // VPERMD to produce a non-lane-crossing shuffle.
9706 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9707 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9709 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9713 // Use dedicated unpack instructions for masks that match their pattern.
9714 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9716 if (isShuffleEquivalent(
9718 // First 128-bit lane:
9719 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9720 // Second 128-bit lane:
9721 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
9722 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9723 if (isShuffleEquivalent(
9725 // First 128-bit lane:
9726 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9727 // Second 128-bit lane:
9728 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
9729 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9731 if (isSingleInputShuffleMask(Mask)) {
9732 SDValue PSHUFBMask[32];
9733 for (int i = 0; i < 32; ++i)
9736 ? DAG.getUNDEF(MVT::i8)
9737 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
9740 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9741 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9744 // Otherwise fall back on generic blend lowering.
9745 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v32i8, V1, V2,
9749 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9751 /// This routine either breaks down the specific type of a 256-bit x86 vector
9752 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9753 /// together based on the available instructions.
9754 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9755 MVT VT, const X86Subtarget *Subtarget,
9756 SelectionDAG &DAG) {
9758 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9759 ArrayRef<int> Mask = SVOp->getMask();
9761 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9762 // check for those subtargets here and avoid much of the subtarget querying in
9763 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9764 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9765 // floating point types there eventually, just immediately cast everything to
9766 // a float and operate entirely in that domain.
9767 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9768 int ElementBits = VT.getScalarSizeInBits();
9769 if (ElementBits < 32)
9770 // No floating point type available, decompose into 128-bit vectors.
9771 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9773 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9774 VT.getVectorNumElements());
9775 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9776 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9777 return DAG.getNode(ISD::BITCAST, DL, VT,
9778 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9781 switch (VT.SimpleTy) {
9783 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9785 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9787 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9789 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9791 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9793 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9796 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9800 /// \brief Tiny helper function to test whether a shuffle mask could be
9801 /// simplified by widening the elements being shuffled.
9802 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
9803 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9804 if ((Mask[i] != -1 && Mask[i] % 2 != 0) ||
9805 (Mask[i + 1] != -1 && (Mask[i + 1] % 2 != 1 ||
9806 (Mask[i] != -1 && Mask[i] + 1 != Mask[i + 1]))))
9812 /// \brief Top-level lowering for x86 vector shuffles.
9814 /// This handles decomposition, canonicalization, and lowering of all x86
9815 /// vector shuffles. Most of the specific lowering strategies are encapsulated
9816 /// above in helper routines. The canonicalization attempts to widen shuffles
9817 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
9818 /// s.t. only one of the two inputs needs to be tested, etc.
9819 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9820 SelectionDAG &DAG) {
9821 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9822 ArrayRef<int> Mask = SVOp->getMask();
9823 SDValue V1 = Op.getOperand(0);
9824 SDValue V2 = Op.getOperand(1);
9825 MVT VT = Op.getSimpleValueType();
9826 int NumElements = VT.getVectorNumElements();
9829 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9831 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9832 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9833 if (V1IsUndef && V2IsUndef)
9834 return DAG.getUNDEF(VT);
9836 // When we create a shuffle node we put the UNDEF node to second operand,
9837 // but in some cases the first operand may be transformed to UNDEF.
9838 // In this case we should just commute the node.
9840 return DAG.getCommutedVectorShuffle(*SVOp);
9842 // Check for non-undef masks pointing at an undef vector and make the masks
9843 // undef as well. This makes it easier to match the shuffle based solely on
9847 if (M >= NumElements) {
9848 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
9849 for (int &M : NewMask)
9850 if (M >= NumElements)
9852 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
9855 // For integer vector shuffles, try to collapse them into a shuffle of fewer
9856 // lanes but wider integers. We cap this to not form integers larger than i64
9857 // but it might be interesting to form i128 integers to handle flipping the
9858 // low and high halves of AVX 256-bit vectors.
9859 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
9860 canWidenShuffleElements(Mask)) {
9861 SmallVector<int, 8> NewMask;
9862 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9863 NewMask.push_back(Mask[i] != -1
9865 : (Mask[i + 1] != -1 ? Mask[i + 1] / 2 : -1));
9867 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
9868 VT.getVectorNumElements() / 2);
9869 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
9870 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
9871 return DAG.getNode(ISD::BITCAST, dl, VT,
9872 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
9875 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
9876 for (int M : SVOp->getMask())
9879 else if (M < NumElements)
9884 // Commute the shuffle as needed such that more elements come from V1 than
9885 // V2. This allows us to match the shuffle pattern strictly on how many
9886 // elements come from V1 without handling the symmetric cases.
9887 if (NumV2Elements > NumV1Elements)
9888 return DAG.getCommutedVectorShuffle(*SVOp);
9890 // When the number of V1 and V2 elements are the same, try to minimize the
9891 // number of uses of V2 in the low half of the vector. When that is tied,
9892 // ensure that the sum of indices for V1 is equal to or lower than the sum
9894 if (NumV1Elements == NumV2Elements) {
9895 int LowV1Elements = 0, LowV2Elements = 0;
9896 for (int M : SVOp->getMask().slice(0, NumElements / 2))
9897 if (M >= NumElements)
9901 if (LowV2Elements > LowV1Elements)
9902 return DAG.getCommutedVectorShuffle(*SVOp);
9904 int SumV1Indices = 0, SumV2Indices = 0;
9905 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
9906 if (SVOp->getMask()[i] >= NumElements)
9908 else if (SVOp->getMask()[i] >= 0)
9910 if (SumV2Indices < SumV1Indices)
9911 return DAG.getCommutedVectorShuffle(*SVOp);
9914 // For each vector width, delegate to a specialized lowering routine.
9915 if (VT.getSizeInBits() == 128)
9916 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9918 if (VT.getSizeInBits() == 256)
9919 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9921 llvm_unreachable("Unimplemented!");
9925 //===----------------------------------------------------------------------===//
9926 // Legacy vector shuffle lowering
9928 // This code is the legacy code handling vector shuffles until the above
9929 // replaces its functionality and performance.
9930 //===----------------------------------------------------------------------===//
9932 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
9933 bool hasInt256, unsigned *MaskOut = nullptr) {
9934 MVT EltVT = VT.getVectorElementType();
9936 // There is no blend with immediate in AVX-512.
9937 if (VT.is512BitVector())
9940 if (!hasSSE41 || EltVT == MVT::i8)
9942 if (!hasInt256 && VT == MVT::v16i16)
9945 unsigned MaskValue = 0;
9946 unsigned NumElems = VT.getVectorNumElements();
9947 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9948 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9949 unsigned NumElemsInLane = NumElems / NumLanes;
9951 // Blend for v16i16 should be symetric for the both lanes.
9952 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9954 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
9955 int EltIdx = MaskVals[i];
9957 if ((EltIdx < 0 || EltIdx == (int)i) &&
9958 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
9961 if (((unsigned)EltIdx == (i + NumElems)) &&
9962 (SndLaneEltIdx < 0 ||
9963 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
9964 MaskValue |= (1 << i);
9970 *MaskOut = MaskValue;
9974 // Try to lower a shuffle node into a simple blend instruction.
9975 // This function assumes isBlendMask returns true for this
9976 // SuffleVectorSDNode
9977 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
9979 const X86Subtarget *Subtarget,
9980 SelectionDAG &DAG) {
9981 MVT VT = SVOp->getSimpleValueType(0);
9982 MVT EltVT = VT.getVectorElementType();
9983 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
9984 Subtarget->hasInt256() && "Trying to lower a "
9985 "VECTOR_SHUFFLE to a Blend but "
9986 "with the wrong mask"));
9987 SDValue V1 = SVOp->getOperand(0);
9988 SDValue V2 = SVOp->getOperand(1);
9990 unsigned NumElems = VT.getVectorNumElements();
9992 // Convert i32 vectors to floating point if it is not AVX2.
9993 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9995 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9996 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9998 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
9999 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10002 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10003 DAG.getConstant(MaskValue, MVT::i32));
10004 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10007 /// In vector type \p VT, return true if the element at index \p InputIdx
10008 /// falls on a different 128-bit lane than \p OutputIdx.
10009 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10010 unsigned OutputIdx) {
10011 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10012 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10015 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10016 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10017 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10018 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10020 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10021 SelectionDAG &DAG) {
10022 MVT VT = V1.getSimpleValueType();
10023 assert(VT.is128BitVector() || VT.is256BitVector());
10025 MVT EltVT = VT.getVectorElementType();
10026 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10027 unsigned NumElts = VT.getVectorNumElements();
10029 SmallVector<SDValue, 32> PshufbMask;
10030 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10031 int InputIdx = MaskVals[OutputIdx];
10032 unsigned InputByteIdx;
10034 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10035 InputByteIdx = 0x80;
10037 // Cross lane is not allowed.
10038 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10040 InputByteIdx = InputIdx * EltSizeInBytes;
10041 // Index is an byte offset within the 128-bit lane.
10042 InputByteIdx &= 0xf;
10045 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10046 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10047 if (InputByteIdx != 0x80)
10052 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10054 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10055 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10056 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10059 // v8i16 shuffles - Prefer shuffles in the following order:
10060 // 1. [all] pshuflw, pshufhw, optional move
10061 // 2. [ssse3] 1 x pshufb
10062 // 3. [ssse3] 2 x pshufb + 1 x por
10063 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10065 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10066 SelectionDAG &DAG) {
10067 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10068 SDValue V1 = SVOp->getOperand(0);
10069 SDValue V2 = SVOp->getOperand(1);
10071 SmallVector<int, 8> MaskVals;
10073 // Determine if more than 1 of the words in each of the low and high quadwords
10074 // of the result come from the same quadword of one of the two inputs. Undef
10075 // mask values count as coming from any quadword, for better codegen.
10077 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10078 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10079 unsigned LoQuad[] = { 0, 0, 0, 0 };
10080 unsigned HiQuad[] = { 0, 0, 0, 0 };
10081 // Indices of quads used.
10082 std::bitset<4> InputQuads;
10083 for (unsigned i = 0; i < 8; ++i) {
10084 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10085 int EltIdx = SVOp->getMaskElt(i);
10086 MaskVals.push_back(EltIdx);
10094 ++Quad[EltIdx / 4];
10095 InputQuads.set(EltIdx / 4);
10098 int BestLoQuad = -1;
10099 unsigned MaxQuad = 1;
10100 for (unsigned i = 0; i < 4; ++i) {
10101 if (LoQuad[i] > MaxQuad) {
10103 MaxQuad = LoQuad[i];
10107 int BestHiQuad = -1;
10109 for (unsigned i = 0; i < 4; ++i) {
10110 if (HiQuad[i] > MaxQuad) {
10112 MaxQuad = HiQuad[i];
10116 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10117 // of the two input vectors, shuffle them into one input vector so only a
10118 // single pshufb instruction is necessary. If there are more than 2 input
10119 // quads, disable the next transformation since it does not help SSSE3.
10120 bool V1Used = InputQuads[0] || InputQuads[1];
10121 bool V2Used = InputQuads[2] || InputQuads[3];
10122 if (Subtarget->hasSSSE3()) {
10123 if (InputQuads.count() == 2 && V1Used && V2Used) {
10124 BestLoQuad = InputQuads[0] ? 0 : 1;
10125 BestHiQuad = InputQuads[2] ? 2 : 3;
10127 if (InputQuads.count() > 2) {
10133 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10134 // the shuffle mask. If a quad is scored as -1, that means that it contains
10135 // words from all 4 input quadwords.
10137 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10139 BestLoQuad < 0 ? 0 : BestLoQuad,
10140 BestHiQuad < 0 ? 1 : BestHiQuad
10142 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10143 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10144 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10145 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10147 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10148 // source words for the shuffle, to aid later transformations.
10149 bool AllWordsInNewV = true;
10150 bool InOrder[2] = { true, true };
10151 for (unsigned i = 0; i != 8; ++i) {
10152 int idx = MaskVals[i];
10154 InOrder[i/4] = false;
10155 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10157 AllWordsInNewV = false;
10161 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10162 if (AllWordsInNewV) {
10163 for (int i = 0; i != 8; ++i) {
10164 int idx = MaskVals[i];
10167 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10168 if ((idx != i) && idx < 4)
10170 if ((idx != i) && idx > 3)
10179 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10180 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10181 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10182 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10183 unsigned TargetMask = 0;
10184 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10185 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10186 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10187 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10188 getShufflePSHUFLWImmediate(SVOp);
10189 V1 = NewV.getOperand(0);
10190 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10194 // Promote splats to a larger type which usually leads to more efficient code.
10195 // FIXME: Is this true if pshufb is available?
10196 if (SVOp->isSplat())
10197 return PromoteSplat(SVOp, DAG);
10199 // If we have SSSE3, and all words of the result are from 1 input vector,
10200 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10201 // is present, fall back to case 4.
10202 if (Subtarget->hasSSSE3()) {
10203 SmallVector<SDValue,16> pshufbMask;
10205 // If we have elements from both input vectors, set the high bit of the
10206 // shuffle mask element to zero out elements that come from V2 in the V1
10207 // mask, and elements that come from V1 in the V2 mask, so that the two
10208 // results can be OR'd together.
10209 bool TwoInputs = V1Used && V2Used;
10210 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10212 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10214 // Calculate the shuffle mask for the second input, shuffle it, and
10215 // OR it with the first shuffled input.
10216 CommuteVectorShuffleMask(MaskVals, 8);
10217 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10218 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10219 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10222 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10223 // and update MaskVals with new element order.
10224 std::bitset<8> InOrder;
10225 if (BestLoQuad >= 0) {
10226 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10227 for (int i = 0; i != 4; ++i) {
10228 int idx = MaskVals[i];
10231 } else if ((idx / 4) == BestLoQuad) {
10232 MaskV[i] = idx & 3;
10236 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10239 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10240 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10241 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10242 NewV.getOperand(0),
10243 getShufflePSHUFLWImmediate(SVOp), DAG);
10247 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10248 // and update MaskVals with the new element order.
10249 if (BestHiQuad >= 0) {
10250 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10251 for (unsigned i = 4; i != 8; ++i) {
10252 int idx = MaskVals[i];
10255 } else if ((idx / 4) == BestHiQuad) {
10256 MaskV[i] = (idx & 3) + 4;
10260 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10263 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10264 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10265 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10266 NewV.getOperand(0),
10267 getShufflePSHUFHWImmediate(SVOp), DAG);
10271 // In case BestHi & BestLo were both -1, which means each quadword has a word
10272 // from each of the four input quadwords, calculate the InOrder bitvector now
10273 // before falling through to the insert/extract cleanup.
10274 if (BestLoQuad == -1 && BestHiQuad == -1) {
10276 for (int i = 0; i != 8; ++i)
10277 if (MaskVals[i] < 0 || MaskVals[i] == i)
10281 // The other elements are put in the right place using pextrw and pinsrw.
10282 for (unsigned i = 0; i != 8; ++i) {
10285 int EltIdx = MaskVals[i];
10288 SDValue ExtOp = (EltIdx < 8) ?
10289 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10290 DAG.getIntPtrConstant(EltIdx)) :
10291 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10292 DAG.getIntPtrConstant(EltIdx - 8));
10293 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10294 DAG.getIntPtrConstant(i));
10299 /// \brief v16i16 shuffles
10301 /// FIXME: We only support generation of a single pshufb currently. We can
10302 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10303 /// well (e.g 2 x pshufb + 1 x por).
10305 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10306 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10307 SDValue V1 = SVOp->getOperand(0);
10308 SDValue V2 = SVOp->getOperand(1);
10311 if (V2.getOpcode() != ISD::UNDEF)
10314 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10315 return getPSHUFB(MaskVals, V1, dl, DAG);
10318 // v16i8 shuffles - Prefer shuffles in the following order:
10319 // 1. [ssse3] 1 x pshufb
10320 // 2. [ssse3] 2 x pshufb + 1 x por
10321 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10322 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10323 const X86Subtarget* Subtarget,
10324 SelectionDAG &DAG) {
10325 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10326 SDValue V1 = SVOp->getOperand(0);
10327 SDValue V2 = SVOp->getOperand(1);
10329 ArrayRef<int> MaskVals = SVOp->getMask();
10331 // Promote splats to a larger type which usually leads to more efficient code.
10332 // FIXME: Is this true if pshufb is available?
10333 if (SVOp->isSplat())
10334 return PromoteSplat(SVOp, DAG);
10336 // If we have SSSE3, case 1 is generated when all result bytes come from
10337 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10338 // present, fall back to case 3.
10340 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10341 if (Subtarget->hasSSSE3()) {
10342 SmallVector<SDValue,16> pshufbMask;
10344 // If all result elements are from one input vector, then only translate
10345 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10347 // Otherwise, we have elements from both input vectors, and must zero out
10348 // elements that come from V2 in the first mask, and V1 in the second mask
10349 // so that we can OR them together.
10350 for (unsigned i = 0; i != 16; ++i) {
10351 int EltIdx = MaskVals[i];
10352 if (EltIdx < 0 || EltIdx >= 16)
10354 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10356 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10357 DAG.getNode(ISD::BUILD_VECTOR, dl,
10358 MVT::v16i8, pshufbMask));
10360 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10361 // the 2nd operand if it's undefined or zero.
10362 if (V2.getOpcode() == ISD::UNDEF ||
10363 ISD::isBuildVectorAllZeros(V2.getNode()))
10366 // Calculate the shuffle mask for the second input, shuffle it, and
10367 // OR it with the first shuffled input.
10368 pshufbMask.clear();
10369 for (unsigned i = 0; i != 16; ++i) {
10370 int EltIdx = MaskVals[i];
10371 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10372 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10374 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10375 DAG.getNode(ISD::BUILD_VECTOR, dl,
10376 MVT::v16i8, pshufbMask));
10377 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10380 // No SSSE3 - Calculate in place words and then fix all out of place words
10381 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10382 // the 16 different words that comprise the two doublequadword input vectors.
10383 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10384 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10386 for (int i = 0; i != 8; ++i) {
10387 int Elt0 = MaskVals[i*2];
10388 int Elt1 = MaskVals[i*2+1];
10390 // This word of the result is all undef, skip it.
10391 if (Elt0 < 0 && Elt1 < 0)
10394 // This word of the result is already in the correct place, skip it.
10395 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10398 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10399 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10402 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10403 // using a single extract together, load it and store it.
10404 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10405 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10406 DAG.getIntPtrConstant(Elt1 / 2));
10407 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10408 DAG.getIntPtrConstant(i));
10412 // If Elt1 is defined, extract it from the appropriate source. If the
10413 // source byte is not also odd, shift the extracted word left 8 bits
10414 // otherwise clear the bottom 8 bits if we need to do an or.
10416 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10417 DAG.getIntPtrConstant(Elt1 / 2));
10418 if ((Elt1 & 1) == 0)
10419 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10421 TLI.getShiftAmountTy(InsElt.getValueType())));
10422 else if (Elt0 >= 0)
10423 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10424 DAG.getConstant(0xFF00, MVT::i16));
10426 // If Elt0 is defined, extract it from the appropriate source. If the
10427 // source byte is not also even, shift the extracted word right 8 bits. If
10428 // Elt1 was also defined, OR the extracted values together before
10429 // inserting them in the result.
10431 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10432 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10433 if ((Elt0 & 1) != 0)
10434 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10436 TLI.getShiftAmountTy(InsElt0.getValueType())));
10437 else if (Elt1 >= 0)
10438 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10439 DAG.getConstant(0x00FF, MVT::i16));
10440 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10443 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10444 DAG.getIntPtrConstant(i));
10446 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10449 // v32i8 shuffles - Translate to VPSHUFB if possible.
10451 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10452 const X86Subtarget *Subtarget,
10453 SelectionDAG &DAG) {
10454 MVT VT = SVOp->getSimpleValueType(0);
10455 SDValue V1 = SVOp->getOperand(0);
10456 SDValue V2 = SVOp->getOperand(1);
10458 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10460 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10461 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10462 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10464 // VPSHUFB may be generated if
10465 // (1) one of input vector is undefined or zeroinitializer.
10466 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10467 // And (2) the mask indexes don't cross the 128-bit lane.
10468 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10469 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10472 if (V1IsAllZero && !V2IsAllZero) {
10473 CommuteVectorShuffleMask(MaskVals, 32);
10476 return getPSHUFB(MaskVals, V1, dl, DAG);
10479 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10480 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10481 /// done when every pair / quad of shuffle mask elements point to elements in
10482 /// the right sequence. e.g.
10483 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10485 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10486 SelectionDAG &DAG) {
10487 MVT VT = SVOp->getSimpleValueType(0);
10489 unsigned NumElems = VT.getVectorNumElements();
10492 switch (VT.SimpleTy) {
10493 default: llvm_unreachable("Unexpected!");
10496 return SDValue(SVOp, 0);
10497 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10498 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10499 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10500 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10501 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10502 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10505 SmallVector<int, 8> MaskVec;
10506 for (unsigned i = 0; i != NumElems; i += Scale) {
10508 for (unsigned j = 0; j != Scale; ++j) {
10509 int EltIdx = SVOp->getMaskElt(i+j);
10513 StartIdx = (EltIdx / Scale);
10514 if (EltIdx != (int)(StartIdx*Scale + j))
10517 MaskVec.push_back(StartIdx);
10520 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10521 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10522 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10525 /// getVZextMovL - Return a zero-extending vector move low node.
10527 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10528 SDValue SrcOp, SelectionDAG &DAG,
10529 const X86Subtarget *Subtarget, SDLoc dl) {
10530 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10531 LoadSDNode *LD = nullptr;
10532 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10533 LD = dyn_cast<LoadSDNode>(SrcOp);
10535 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10537 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10538 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10539 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10540 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10541 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10543 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10544 return DAG.getNode(ISD::BITCAST, dl, VT,
10545 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10546 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10548 SrcOp.getOperand(0)
10554 return DAG.getNode(ISD::BITCAST, dl, VT,
10555 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10556 DAG.getNode(ISD::BITCAST, dl,
10560 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10561 /// which could not be matched by any known target speficic shuffle
10563 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10565 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10566 if (NewOp.getNode())
10569 MVT VT = SVOp->getSimpleValueType(0);
10571 unsigned NumElems = VT.getVectorNumElements();
10572 unsigned NumLaneElems = NumElems / 2;
10575 MVT EltVT = VT.getVectorElementType();
10576 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10579 SmallVector<int, 16> Mask;
10580 for (unsigned l = 0; l < 2; ++l) {
10581 // Build a shuffle mask for the output, discovering on the fly which
10582 // input vectors to use as shuffle operands (recorded in InputUsed).
10583 // If building a suitable shuffle vector proves too hard, then bail
10584 // out with UseBuildVector set.
10585 bool UseBuildVector = false;
10586 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10587 unsigned LaneStart = l * NumLaneElems;
10588 for (unsigned i = 0; i != NumLaneElems; ++i) {
10589 // The mask element. This indexes into the input.
10590 int Idx = SVOp->getMaskElt(i+LaneStart);
10592 // the mask element does not index into any input vector.
10593 Mask.push_back(-1);
10597 // The input vector this mask element indexes into.
10598 int Input = Idx / NumLaneElems;
10600 // Turn the index into an offset from the start of the input vector.
10601 Idx -= Input * NumLaneElems;
10603 // Find or create a shuffle vector operand to hold this input.
10605 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10606 if (InputUsed[OpNo] == Input)
10607 // This input vector is already an operand.
10609 if (InputUsed[OpNo] < 0) {
10610 // Create a new operand for this input vector.
10611 InputUsed[OpNo] = Input;
10616 if (OpNo >= array_lengthof(InputUsed)) {
10617 // More than two input vectors used! Give up on trying to create a
10618 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10619 UseBuildVector = true;
10623 // Add the mask index for the new shuffle vector.
10624 Mask.push_back(Idx + OpNo * NumLaneElems);
10627 if (UseBuildVector) {
10628 SmallVector<SDValue, 16> SVOps;
10629 for (unsigned i = 0; i != NumLaneElems; ++i) {
10630 // The mask element. This indexes into the input.
10631 int Idx = SVOp->getMaskElt(i+LaneStart);
10633 SVOps.push_back(DAG.getUNDEF(EltVT));
10637 // The input vector this mask element indexes into.
10638 int Input = Idx / NumElems;
10640 // Turn the index into an offset from the start of the input vector.
10641 Idx -= Input * NumElems;
10643 // Extract the vector element by hand.
10644 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
10645 SVOp->getOperand(Input),
10646 DAG.getIntPtrConstant(Idx)));
10649 // Construct the output using a BUILD_VECTOR.
10650 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
10651 } else if (InputUsed[0] < 0) {
10652 // No input vectors were used! The result is undefined.
10653 Output[l] = DAG.getUNDEF(NVT);
10655 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
10656 (InputUsed[0] % 2) * NumLaneElems,
10658 // If only one input was used, use an undefined vector for the other.
10659 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
10660 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
10661 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
10662 // At least one input vector was used. Create a new shuffle vector.
10663 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
10669 // Concatenate the result back
10670 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
10673 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
10674 /// 4 elements, and match them with several different shuffle types.
10676 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10677 SDValue V1 = SVOp->getOperand(0);
10678 SDValue V2 = SVOp->getOperand(1);
10680 MVT VT = SVOp->getSimpleValueType(0);
10682 assert(VT.is128BitVector() && "Unsupported vector size");
10684 std::pair<int, int> Locs[4];
10685 int Mask1[] = { -1, -1, -1, -1 };
10686 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
10688 unsigned NumHi = 0;
10689 unsigned NumLo = 0;
10690 for (unsigned i = 0; i != 4; ++i) {
10691 int Idx = PermMask[i];
10693 Locs[i] = std::make_pair(-1, -1);
10695 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
10697 Locs[i] = std::make_pair(0, NumLo);
10698 Mask1[NumLo] = Idx;
10701 Locs[i] = std::make_pair(1, NumHi);
10703 Mask1[2+NumHi] = Idx;
10709 if (NumLo <= 2 && NumHi <= 2) {
10710 // If no more than two elements come from either vector. This can be
10711 // implemented with two shuffles. First shuffle gather the elements.
10712 // The second shuffle, which takes the first shuffle as both of its
10713 // vector operands, put the elements into the right order.
10714 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10716 int Mask2[] = { -1, -1, -1, -1 };
10718 for (unsigned i = 0; i != 4; ++i)
10719 if (Locs[i].first != -1) {
10720 unsigned Idx = (i < 2) ? 0 : 4;
10721 Idx += Locs[i].first * 2 + Locs[i].second;
10725 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
10728 if (NumLo == 3 || NumHi == 3) {
10729 // Otherwise, we must have three elements from one vector, call it X, and
10730 // one element from the other, call it Y. First, use a shufps to build an
10731 // intermediate vector with the one element from Y and the element from X
10732 // that will be in the same half in the final destination (the indexes don't
10733 // matter). Then, use a shufps to build the final vector, taking the half
10734 // containing the element from Y from the intermediate, and the other half
10737 // Normalize it so the 3 elements come from V1.
10738 CommuteVectorShuffleMask(PermMask, 4);
10742 // Find the element from V2.
10744 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
10745 int Val = PermMask[HiIndex];
10752 Mask1[0] = PermMask[HiIndex];
10754 Mask1[2] = PermMask[HiIndex^1];
10756 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10758 if (HiIndex >= 2) {
10759 Mask1[0] = PermMask[0];
10760 Mask1[1] = PermMask[1];
10761 Mask1[2] = HiIndex & 1 ? 6 : 4;
10762 Mask1[3] = HiIndex & 1 ? 4 : 6;
10763 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10766 Mask1[0] = HiIndex & 1 ? 2 : 0;
10767 Mask1[1] = HiIndex & 1 ? 0 : 2;
10768 Mask1[2] = PermMask[2];
10769 Mask1[3] = PermMask[3];
10774 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
10777 // Break it into (shuffle shuffle_hi, shuffle_lo).
10778 int LoMask[] = { -1, -1, -1, -1 };
10779 int HiMask[] = { -1, -1, -1, -1 };
10781 int *MaskPtr = LoMask;
10782 unsigned MaskIdx = 0;
10783 unsigned LoIdx = 0;
10784 unsigned HiIdx = 2;
10785 for (unsigned i = 0; i != 4; ++i) {
10792 int Idx = PermMask[i];
10794 Locs[i] = std::make_pair(-1, -1);
10795 } else if (Idx < 4) {
10796 Locs[i] = std::make_pair(MaskIdx, LoIdx);
10797 MaskPtr[LoIdx] = Idx;
10800 Locs[i] = std::make_pair(MaskIdx, HiIdx);
10801 MaskPtr[HiIdx] = Idx;
10806 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
10807 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
10808 int MaskOps[] = { -1, -1, -1, -1 };
10809 for (unsigned i = 0; i != 4; ++i)
10810 if (Locs[i].first != -1)
10811 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
10812 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
10815 static bool MayFoldVectorLoad(SDValue V) {
10816 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
10817 V = V.getOperand(0);
10819 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
10820 V = V.getOperand(0);
10821 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
10822 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
10823 // BUILD_VECTOR (load), undef
10824 V = V.getOperand(0);
10826 return MayFoldLoad(V);
10830 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
10831 MVT VT = Op.getSimpleValueType();
10833 // Canonizalize to v2f64.
10834 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
10835 return DAG.getNode(ISD::BITCAST, dl, VT,
10836 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
10841 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
10843 SDValue V1 = Op.getOperand(0);
10844 SDValue V2 = Op.getOperand(1);
10845 MVT VT = Op.getSimpleValueType();
10847 assert(VT != MVT::v2i64 && "unsupported shuffle type");
10849 if (HasSSE2 && VT == MVT::v2f64)
10850 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
10852 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
10853 return DAG.getNode(ISD::BITCAST, dl, VT,
10854 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
10855 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
10856 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
10860 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
10861 SDValue V1 = Op.getOperand(0);
10862 SDValue V2 = Op.getOperand(1);
10863 MVT VT = Op.getSimpleValueType();
10865 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
10866 "unsupported shuffle type");
10868 if (V2.getOpcode() == ISD::UNDEF)
10872 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
10876 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
10877 SDValue V1 = Op.getOperand(0);
10878 SDValue V2 = Op.getOperand(1);
10879 MVT VT = Op.getSimpleValueType();
10880 unsigned NumElems = VT.getVectorNumElements();
10882 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
10883 // operand of these instructions is only memory, so check if there's a
10884 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
10886 bool CanFoldLoad = false;
10888 // Trivial case, when V2 comes from a load.
10889 if (MayFoldVectorLoad(V2))
10890 CanFoldLoad = true;
10892 // When V1 is a load, it can be folded later into a store in isel, example:
10893 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
10895 // (MOVLPSmr addr:$src1, VR128:$src2)
10896 // So, recognize this potential and also use MOVLPS or MOVLPD
10897 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
10898 CanFoldLoad = true;
10900 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10902 if (HasSSE2 && NumElems == 2)
10903 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
10906 // If we don't care about the second element, proceed to use movss.
10907 if (SVOp->getMaskElt(1) != -1)
10908 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
10911 // movl and movlp will both match v2i64, but v2i64 is never matched by
10912 // movl earlier because we make it strict to avoid messing with the movlp load
10913 // folding logic (see the code above getMOVLP call). Match it here then,
10914 // this is horrible, but will stay like this until we move all shuffle
10915 // matching to x86 specific nodes. Note that for the 1st condition all
10916 // types are matched with movsd.
10918 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
10919 // as to remove this logic from here, as much as possible
10920 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
10921 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10922 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10925 assert(VT != MVT::v4i32 && "unsupported shuffle type");
10927 // Invert the operand order and use SHUFPS to match it.
10928 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
10929 getShuffleSHUFImmediate(SVOp), DAG);
10932 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
10933 SelectionDAG &DAG) {
10935 MVT VT = Load->getSimpleValueType(0);
10936 MVT EVT = VT.getVectorElementType();
10937 SDValue Addr = Load->getOperand(1);
10938 SDValue NewAddr = DAG.getNode(
10939 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
10940 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
10943 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
10944 DAG.getMachineFunction().getMachineMemOperand(
10945 Load->getMemOperand(), 0, EVT.getStoreSize()));
10949 // It is only safe to call this function if isINSERTPSMask is true for
10950 // this shufflevector mask.
10951 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
10952 SelectionDAG &DAG) {
10953 // Generate an insertps instruction when inserting an f32 from memory onto a
10954 // v4f32 or when copying a member from one v4f32 to another.
10955 // We also use it for transferring i32 from one register to another,
10956 // since it simply copies the same bits.
10957 // If we're transferring an i32 from memory to a specific element in a
10958 // register, we output a generic DAG that will match the PINSRD
10960 MVT VT = SVOp->getSimpleValueType(0);
10961 MVT EVT = VT.getVectorElementType();
10962 SDValue V1 = SVOp->getOperand(0);
10963 SDValue V2 = SVOp->getOperand(1);
10964 auto Mask = SVOp->getMask();
10965 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
10966 "unsupported vector type for insertps/pinsrd");
10968 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
10969 auto FromV2Predicate = [](const int &i) { return i >= 4; };
10970 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
10974 unsigned DestIndex;
10978 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
10981 // If we have 1 element from each vector, we have to check if we're
10982 // changing V1's element's place. If so, we're done. Otherwise, we
10983 // should assume we're changing V2's element's place and behave
10985 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
10986 assert(DestIndex <= INT32_MAX && "truncated destination index");
10987 if (FromV1 == FromV2 &&
10988 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
10992 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10995 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
10996 "More than one element from V1 and from V2, or no elements from one "
10997 "of the vectors. This case should not have returned true from "
11002 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11005 // Get an index into the source vector in the range [0,4) (the mask is
11006 // in the range [0,8) because it can address V1 and V2)
11007 unsigned SrcIndex = Mask[DestIndex] % 4;
11008 if (MayFoldLoad(From)) {
11009 // Trivial case, when From comes from a load and is only used by the
11010 // shuffle. Make it use insertps from the vector that we need from that
11013 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11014 if (!NewLoad.getNode())
11017 if (EVT == MVT::f32) {
11018 // Create this as a scalar to vector to match the instruction pattern.
11019 SDValue LoadScalarToVector =
11020 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11021 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11022 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11024 } else { // EVT == MVT::i32
11025 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11026 // instruction, to match the PINSRD instruction, which loads an i32 to a
11027 // certain vector element.
11028 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11029 DAG.getConstant(DestIndex, MVT::i32));
11033 // Vector-element-to-vector
11034 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11035 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11038 // Reduce a vector shuffle to zext.
11039 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11040 SelectionDAG &DAG) {
11041 // PMOVZX is only available from SSE41.
11042 if (!Subtarget->hasSSE41())
11045 MVT VT = Op.getSimpleValueType();
11047 // Only AVX2 support 256-bit vector integer extending.
11048 if (!Subtarget->hasInt256() && VT.is256BitVector())
11051 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11053 SDValue V1 = Op.getOperand(0);
11054 SDValue V2 = Op.getOperand(1);
11055 unsigned NumElems = VT.getVectorNumElements();
11057 // Extending is an unary operation and the element type of the source vector
11058 // won't be equal to or larger than i64.
11059 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11060 VT.getVectorElementType() == MVT::i64)
11063 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11064 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11065 while ((1U << Shift) < NumElems) {
11066 if (SVOp->getMaskElt(1U << Shift) == 1)
11069 // The maximal ratio is 8, i.e. from i8 to i64.
11074 // Check the shuffle mask.
11075 unsigned Mask = (1U << Shift) - 1;
11076 for (unsigned i = 0; i != NumElems; ++i) {
11077 int EltIdx = SVOp->getMaskElt(i);
11078 if ((i & Mask) != 0 && EltIdx != -1)
11080 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11084 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11085 MVT NeVT = MVT::getIntegerVT(NBits);
11086 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11088 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11091 // Simplify the operand as it's prepared to be fed into shuffle.
11092 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
11093 if (V1.getOpcode() == ISD::BITCAST &&
11094 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
11095 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
11096 V1.getOperand(0).getOperand(0)
11097 .getSimpleValueType().getSizeInBits() == SignificantBits) {
11098 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
11099 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
11100 ConstantSDNode *CIdx =
11101 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
11102 // If it's foldable, i.e. normal load with single use, we will let code
11103 // selection to fold it. Otherwise, we will short the conversion sequence.
11104 if (CIdx && CIdx->getZExtValue() == 0 &&
11105 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
11106 MVT FullVT = V.getSimpleValueType();
11107 MVT V1VT = V1.getSimpleValueType();
11108 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
11109 // The "ext_vec_elt" node is wider than the result node.
11110 // In this case we should extract subvector from V.
11111 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
11112 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
11113 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
11114 FullVT.getVectorNumElements()/Ratio);
11115 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
11116 DAG.getIntPtrConstant(0));
11118 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
11122 return DAG.getNode(ISD::BITCAST, DL, VT,
11123 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11126 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11127 SelectionDAG &DAG) {
11128 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11129 MVT VT = Op.getSimpleValueType();
11131 SDValue V1 = Op.getOperand(0);
11132 SDValue V2 = Op.getOperand(1);
11134 if (isZeroShuffle(SVOp))
11135 return getZeroVector(VT, Subtarget, DAG, dl);
11137 // Handle splat operations
11138 if (SVOp->isSplat()) {
11139 // Use vbroadcast whenever the splat comes from a foldable load
11140 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11141 if (Broadcast.getNode())
11145 // Check integer expanding shuffles.
11146 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11147 if (NewOp.getNode())
11150 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11152 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11153 VT == MVT::v32i8) {
11154 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11155 if (NewOp.getNode())
11156 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11157 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11158 // FIXME: Figure out a cleaner way to do this.
11159 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11160 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11161 if (NewOp.getNode()) {
11162 MVT NewVT = NewOp.getSimpleValueType();
11163 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11164 NewVT, true, false))
11165 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11168 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11169 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11170 if (NewOp.getNode()) {
11171 MVT NewVT = NewOp.getSimpleValueType();
11172 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11173 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11182 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11183 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11184 SDValue V1 = Op.getOperand(0);
11185 SDValue V2 = Op.getOperand(1);
11186 MVT VT = Op.getSimpleValueType();
11188 unsigned NumElems = VT.getVectorNumElements();
11189 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11190 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11191 bool V1IsSplat = false;
11192 bool V2IsSplat = false;
11193 bool HasSSE2 = Subtarget->hasSSE2();
11194 bool HasFp256 = Subtarget->hasFp256();
11195 bool HasInt256 = Subtarget->hasInt256();
11196 MachineFunction &MF = DAG.getMachineFunction();
11197 bool OptForSize = MF.getFunction()->getAttributes().
11198 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11200 // Check if we should use the experimental vector shuffle lowering. If so,
11201 // delegate completely to that code path.
11202 if (ExperimentalVectorShuffleLowering)
11203 return lowerVectorShuffle(Op, Subtarget, DAG);
11205 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11207 if (V1IsUndef && V2IsUndef)
11208 return DAG.getUNDEF(VT);
11210 // When we create a shuffle node we put the UNDEF node to second operand,
11211 // but in some cases the first operand may be transformed to UNDEF.
11212 // In this case we should just commute the node.
11214 return DAG.getCommutedVectorShuffle(*SVOp);
11216 // Vector shuffle lowering takes 3 steps:
11218 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11219 // narrowing and commutation of operands should be handled.
11220 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11222 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11223 // so the shuffle can be broken into other shuffles and the legalizer can
11224 // try the lowering again.
11226 // The general idea is that no vector_shuffle operation should be left to
11227 // be matched during isel, all of them must be converted to a target specific
11230 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11231 // narrowing and commutation of operands should be handled. The actual code
11232 // doesn't include all of those, work in progress...
11233 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11234 if (NewOp.getNode())
11237 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11239 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11240 // unpckh_undef). Only use pshufd if speed is more important than size.
11241 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11242 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11243 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11244 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11246 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11247 V2IsUndef && MayFoldVectorLoad(V1))
11248 return getMOVDDup(Op, dl, V1, DAG);
11250 if (isMOVHLPS_v_undef_Mask(M, VT))
11251 return getMOVHighToLow(Op, dl, DAG);
11253 // Use to match splats
11254 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11255 (VT == MVT::v2f64 || VT == MVT::v2i64))
11256 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11258 if (isPSHUFDMask(M, VT)) {
11259 // The actual implementation will match the mask in the if above and then
11260 // during isel it can match several different instructions, not only pshufd
11261 // as its name says, sad but true, emulate the behavior for now...
11262 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11263 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11265 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11267 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11268 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11270 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11271 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11274 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11278 if (isPALIGNRMask(M, VT, Subtarget))
11279 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11280 getShufflePALIGNRImmediate(SVOp),
11283 if (isVALIGNMask(M, VT, Subtarget))
11284 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11285 getShuffleVALIGNImmediate(SVOp),
11288 // Check if this can be converted into a logical shift.
11289 bool isLeft = false;
11290 unsigned ShAmt = 0;
11292 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11293 if (isShift && ShVal.hasOneUse()) {
11294 // If the shifted value has multiple uses, it may be cheaper to use
11295 // v_set0 + movlhps or movhlps, etc.
11296 MVT EltVT = VT.getVectorElementType();
11297 ShAmt *= EltVT.getSizeInBits();
11298 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11301 if (isMOVLMask(M, VT)) {
11302 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11303 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11304 if (!isMOVLPMask(M, VT)) {
11305 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11306 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11308 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11309 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11313 // FIXME: fold these into legal mask.
11314 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11315 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11317 if (isMOVHLPSMask(M, VT))
11318 return getMOVHighToLow(Op, dl, DAG);
11320 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11321 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11323 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11324 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11326 if (isMOVLPMask(M, VT))
11327 return getMOVLP(Op, dl, DAG, HasSSE2);
11329 if (ShouldXformToMOVHLPS(M, VT) ||
11330 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11331 return DAG.getCommutedVectorShuffle(*SVOp);
11334 // No better options. Use a vshldq / vsrldq.
11335 MVT EltVT = VT.getVectorElementType();
11336 ShAmt *= EltVT.getSizeInBits();
11337 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11340 bool Commuted = false;
11341 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11342 // 1,1,1,1 -> v8i16 though.
11343 BitVector UndefElements;
11344 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11345 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11347 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11348 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11351 // Canonicalize the splat or undef, if present, to be on the RHS.
11352 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11353 CommuteVectorShuffleMask(M, NumElems);
11355 std::swap(V1IsSplat, V2IsSplat);
11359 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11360 // Shuffling low element of v1 into undef, just return v1.
11363 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11364 // the instruction selector will not match, so get a canonical MOVL with
11365 // swapped operands to undo the commute.
11366 return getMOVL(DAG, dl, VT, V2, V1);
11369 if (isUNPCKLMask(M, VT, HasInt256))
11370 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11372 if (isUNPCKHMask(M, VT, HasInt256))
11373 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11376 // Normalize mask so all entries that point to V2 points to its first
11377 // element then try to match unpck{h|l} again. If match, return a
11378 // new vector_shuffle with the corrected mask.p
11379 SmallVector<int, 8> NewMask(M.begin(), M.end());
11380 NormalizeMask(NewMask, NumElems);
11381 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11382 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11383 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11384 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11388 // Commute is back and try unpck* again.
11389 // FIXME: this seems wrong.
11390 CommuteVectorShuffleMask(M, NumElems);
11392 std::swap(V1IsSplat, V2IsSplat);
11394 if (isUNPCKLMask(M, VT, HasInt256))
11395 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11397 if (isUNPCKHMask(M, VT, HasInt256))
11398 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11401 // Normalize the node to match x86 shuffle ops if needed
11402 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11403 return DAG.getCommutedVectorShuffle(*SVOp);
11405 // The checks below are all present in isShuffleMaskLegal, but they are
11406 // inlined here right now to enable us to directly emit target specific
11407 // nodes, and remove one by one until they don't return Op anymore.
11409 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11410 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11411 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11412 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11415 if (isPSHUFHWMask(M, VT, HasInt256))
11416 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11417 getShufflePSHUFHWImmediate(SVOp),
11420 if (isPSHUFLWMask(M, VT, HasInt256))
11421 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11422 getShufflePSHUFLWImmediate(SVOp),
11425 unsigned MaskValue;
11426 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11428 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11430 if (isSHUFPMask(M, VT))
11431 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11432 getShuffleSHUFImmediate(SVOp), DAG);
11434 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11435 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11436 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11437 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11439 //===--------------------------------------------------------------------===//
11440 // Generate target specific nodes for 128 or 256-bit shuffles only
11441 // supported in the AVX instruction set.
11444 // Handle VMOVDDUPY permutations
11445 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11446 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11448 // Handle VPERMILPS/D* permutations
11449 if (isVPERMILPMask(M, VT)) {
11450 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11451 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11452 getShuffleSHUFImmediate(SVOp), DAG);
11453 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11454 getShuffleSHUFImmediate(SVOp), DAG);
11458 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11459 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11460 Idx*(NumElems/2), DAG, dl);
11462 // Handle VPERM2F128/VPERM2I128 permutations
11463 if (isVPERM2X128Mask(M, VT, HasFp256))
11464 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11465 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11467 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11468 return getINSERTPS(SVOp, dl, DAG);
11471 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11472 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11474 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11475 VT.is512BitVector()) {
11476 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11477 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11478 SmallVector<SDValue, 16> permclMask;
11479 for (unsigned i = 0; i != NumElems; ++i) {
11480 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11483 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11485 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11486 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11487 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11488 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11489 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11492 //===--------------------------------------------------------------------===//
11493 // Since no target specific shuffle was selected for this generic one,
11494 // lower it into other known shuffles. FIXME: this isn't true yet, but
11495 // this is the plan.
11498 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11499 if (VT == MVT::v8i16) {
11500 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11501 if (NewOp.getNode())
11505 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11506 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11507 if (NewOp.getNode())
11511 if (VT == MVT::v16i8) {
11512 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11513 if (NewOp.getNode())
11517 if (VT == MVT::v32i8) {
11518 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11519 if (NewOp.getNode())
11523 // Handle all 128-bit wide vectors with 4 elements, and match them with
11524 // several different shuffle types.
11525 if (NumElems == 4 && VT.is128BitVector())
11526 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11528 // Handle general 256-bit shuffles
11529 if (VT.is256BitVector())
11530 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11535 // This function assumes its argument is a BUILD_VECTOR of constants or
11536 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11538 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11539 unsigned &MaskValue) {
11541 unsigned NumElems = BuildVector->getNumOperands();
11542 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11543 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11544 unsigned NumElemsInLane = NumElems / NumLanes;
11546 // Blend for v16i16 should be symetric for the both lanes.
11547 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11548 SDValue EltCond = BuildVector->getOperand(i);
11549 SDValue SndLaneEltCond =
11550 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11552 int Lane1Cond = -1, Lane2Cond = -1;
11553 if (isa<ConstantSDNode>(EltCond))
11554 Lane1Cond = !isZero(EltCond);
11555 if (isa<ConstantSDNode>(SndLaneEltCond))
11556 Lane2Cond = !isZero(SndLaneEltCond);
11558 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11559 // Lane1Cond != 0, means we want the first argument.
11560 // Lane1Cond == 0, means we want the second argument.
11561 // The encoding of this argument is 0 for the first argument, 1
11562 // for the second. Therefore, invert the condition.
11563 MaskValue |= !Lane1Cond << i;
11564 else if (Lane1Cond < 0)
11565 MaskValue |= !Lane2Cond << i;
11572 // Try to lower a vselect node into a simple blend instruction.
11573 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
11574 SelectionDAG &DAG) {
11575 SDValue Cond = Op.getOperand(0);
11576 SDValue LHS = Op.getOperand(1);
11577 SDValue RHS = Op.getOperand(2);
11579 MVT VT = Op.getSimpleValueType();
11580 MVT EltVT = VT.getVectorElementType();
11581 unsigned NumElems = VT.getVectorNumElements();
11583 // There is no blend with immediate in AVX-512.
11584 if (VT.is512BitVector())
11587 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
11589 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
11592 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11595 // Check the mask for BLEND and build the value.
11596 unsigned MaskValue = 0;
11597 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
11600 // Convert i32 vectors to floating point if it is not AVX2.
11601 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11603 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11604 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11606 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
11607 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
11610 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11611 DAG.getConstant(MaskValue, MVT::i32));
11612 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11615 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11616 // A vselect where all conditions and data are constants can be optimized into
11617 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11618 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11619 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11620 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11623 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
11624 if (BlendOp.getNode())
11627 // Some types for vselect were previously set to Expand, not Legal or
11628 // Custom. Return an empty SDValue so we fall-through to Expand, after
11629 // the Custom lowering phase.
11630 MVT VT = Op.getSimpleValueType();
11631 switch (VT.SimpleTy) {
11636 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11641 // We couldn't create a "Blend with immediate" node.
11642 // This node should still be legal, but we'll have to emit a blendv*
11647 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11648 MVT VT = Op.getSimpleValueType();
11651 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11654 if (VT.getSizeInBits() == 8) {
11655 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11656 Op.getOperand(0), Op.getOperand(1));
11657 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11658 DAG.getValueType(VT));
11659 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11662 if (VT.getSizeInBits() == 16) {
11663 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11664 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11666 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11667 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11668 DAG.getNode(ISD::BITCAST, dl,
11671 Op.getOperand(1)));
11672 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11673 Op.getOperand(0), Op.getOperand(1));
11674 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11675 DAG.getValueType(VT));
11676 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11679 if (VT == MVT::f32) {
11680 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11681 // the result back to FR32 register. It's only worth matching if the
11682 // result has a single use which is a store or a bitcast to i32. And in
11683 // the case of a store, it's not worth it if the index is a constant 0,
11684 // because a MOVSSmr can be used instead, which is smaller and faster.
11685 if (!Op.hasOneUse())
11687 SDNode *User = *Op.getNode()->use_begin();
11688 if ((User->getOpcode() != ISD::STORE ||
11689 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11690 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11691 (User->getOpcode() != ISD::BITCAST ||
11692 User->getValueType(0) != MVT::i32))
11694 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11695 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
11698 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
11701 if (VT == MVT::i32 || VT == MVT::i64) {
11702 // ExtractPS/pextrq works with constant index.
11703 if (isa<ConstantSDNode>(Op.getOperand(1)))
11709 /// Extract one bit from mask vector, like v16i1 or v8i1.
11710 /// AVX-512 feature.
11712 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11713 SDValue Vec = Op.getOperand(0);
11715 MVT VecVT = Vec.getSimpleValueType();
11716 SDValue Idx = Op.getOperand(1);
11717 MVT EltVT = Op.getSimpleValueType();
11719 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11721 // variable index can't be handled in mask registers,
11722 // extend vector to VR512
11723 if (!isa<ConstantSDNode>(Idx)) {
11724 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11725 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11726 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11727 ExtVT.getVectorElementType(), Ext, Idx);
11728 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11731 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11732 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11733 unsigned MaxSift = rc->getSize()*8 - 1;
11734 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11735 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11736 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11737 DAG.getConstant(MaxSift, MVT::i8));
11738 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11739 DAG.getIntPtrConstant(0));
11743 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11744 SelectionDAG &DAG) const {
11746 SDValue Vec = Op.getOperand(0);
11747 MVT VecVT = Vec.getSimpleValueType();
11748 SDValue Idx = Op.getOperand(1);
11750 if (Op.getSimpleValueType() == MVT::i1)
11751 return ExtractBitFromMaskVector(Op, DAG);
11753 if (!isa<ConstantSDNode>(Idx)) {
11754 if (VecVT.is512BitVector() ||
11755 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11756 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11759 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11760 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11761 MaskEltVT.getSizeInBits());
11763 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11764 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11765 getZeroVector(MaskVT, Subtarget, DAG, dl),
11766 Idx, DAG.getConstant(0, getPointerTy()));
11767 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11768 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
11769 Perm, DAG.getConstant(0, getPointerTy()));
11774 // If this is a 256-bit vector result, first extract the 128-bit vector and
11775 // then extract the element from the 128-bit vector.
11776 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11778 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11779 // Get the 128-bit vector.
11780 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11781 MVT EltVT = VecVT.getVectorElementType();
11783 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11785 //if (IdxVal >= NumElems/2)
11786 // IdxVal -= NumElems/2;
11787 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11788 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11789 DAG.getConstant(IdxVal, MVT::i32));
11792 assert(VecVT.is128BitVector() && "Unexpected vector length");
11794 if (Subtarget->hasSSE41()) {
11795 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
11800 MVT VT = Op.getSimpleValueType();
11801 // TODO: handle v16i8.
11802 if (VT.getSizeInBits() == 16) {
11803 SDValue Vec = Op.getOperand(0);
11804 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11806 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11807 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11808 DAG.getNode(ISD::BITCAST, dl,
11810 Op.getOperand(1)));
11811 // Transform it so it match pextrw which produces a 32-bit result.
11812 MVT EltVT = MVT::i32;
11813 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11814 Op.getOperand(0), Op.getOperand(1));
11815 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11816 DAG.getValueType(VT));
11817 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11820 if (VT.getSizeInBits() == 32) {
11821 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11825 // SHUFPS the element to the lowest double word, then movss.
11826 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11827 MVT VVT = Op.getOperand(0).getSimpleValueType();
11828 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11829 DAG.getUNDEF(VVT), Mask);
11830 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11831 DAG.getIntPtrConstant(0));
11834 if (VT.getSizeInBits() == 64) {
11835 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11836 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11837 // to match extract_elt for f64.
11838 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11842 // UNPCKHPD the element to the lowest double word, then movsd.
11843 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11844 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11845 int Mask[2] = { 1, -1 };
11846 MVT VVT = Op.getOperand(0).getSimpleValueType();
11847 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11848 DAG.getUNDEF(VVT), Mask);
11849 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11850 DAG.getIntPtrConstant(0));
11856 /// Insert one bit to mask vector, like v16i1 or v8i1.
11857 /// AVX-512 feature.
11859 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11861 SDValue Vec = Op.getOperand(0);
11862 SDValue Elt = Op.getOperand(1);
11863 SDValue Idx = Op.getOperand(2);
11864 MVT VecVT = Vec.getSimpleValueType();
11866 if (!isa<ConstantSDNode>(Idx)) {
11867 // Non constant index. Extend source and destination,
11868 // insert element and then truncate the result.
11869 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11870 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11871 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11872 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11873 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11874 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11877 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11878 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11879 if (Vec.getOpcode() == ISD::UNDEF)
11880 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11881 DAG.getConstant(IdxVal, MVT::i8));
11882 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11883 unsigned MaxSift = rc->getSize()*8 - 1;
11884 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11885 DAG.getConstant(MaxSift, MVT::i8));
11886 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
11887 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11888 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11891 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11892 SelectionDAG &DAG) const {
11893 MVT VT = Op.getSimpleValueType();
11894 MVT EltVT = VT.getVectorElementType();
11896 if (EltVT == MVT::i1)
11897 return InsertBitToMaskVector(Op, DAG);
11900 SDValue N0 = Op.getOperand(0);
11901 SDValue N1 = Op.getOperand(1);
11902 SDValue N2 = Op.getOperand(2);
11903 if (!isa<ConstantSDNode>(N2))
11905 auto *N2C = cast<ConstantSDNode>(N2);
11906 unsigned IdxVal = N2C->getZExtValue();
11908 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11909 // into that, and then insert the subvector back into the result.
11910 if (VT.is256BitVector() || VT.is512BitVector()) {
11911 // Get the desired 128-bit vector half.
11912 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11914 // Insert the element into the desired half.
11915 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11916 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11918 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11919 DAG.getConstant(IdxIn128, MVT::i32));
11921 // Insert the changed part back to the 256-bit vector
11922 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11924 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11926 if (Subtarget->hasSSE41()) {
11927 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11929 if (VT == MVT::v8i16) {
11930 Opc = X86ISD::PINSRW;
11932 assert(VT == MVT::v16i8);
11933 Opc = X86ISD::PINSRB;
11936 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11938 if (N1.getValueType() != MVT::i32)
11939 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11940 if (N2.getValueType() != MVT::i32)
11941 N2 = DAG.getIntPtrConstant(IdxVal);
11942 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11945 if (EltVT == MVT::f32) {
11946 // Bits [7:6] of the constant are the source select. This will always be
11947 // zero here. The DAG Combiner may combine an extract_elt index into
11949 // bits. For example (insert (extract, 3), 2) could be matched by
11951 // the '3' into bits [7:6] of X86ISD::INSERTPS.
11952 // Bits [5:4] of the constant are the destination select. This is the
11953 // value of the incoming immediate.
11954 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11955 // combine either bitwise AND or insert of float 0.0 to set these bits.
11956 N2 = DAG.getIntPtrConstant(IdxVal << 4);
11957 // Create this as a scalar to vector..
11958 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11959 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11962 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11963 // PINSR* works with constant index.
11968 if (EltVT == MVT::i8)
11971 if (EltVT.getSizeInBits() == 16) {
11972 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11973 // as its second argument.
11974 if (N1.getValueType() != MVT::i32)
11975 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11976 if (N2.getValueType() != MVT::i32)
11977 N2 = DAG.getIntPtrConstant(IdxVal);
11978 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11983 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11985 MVT OpVT = Op.getSimpleValueType();
11987 // If this is a 256-bit vector result, first insert into a 128-bit
11988 // vector and then insert into the 256-bit vector.
11989 if (!OpVT.is128BitVector()) {
11990 // Insert into a 128-bit vector.
11991 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11992 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11993 OpVT.getVectorNumElements() / SizeFactor);
11995 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11997 // Insert the 128-bit vector.
11998 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12001 if (OpVT == MVT::v1i64 &&
12002 Op.getOperand(0).getValueType() == MVT::i64)
12003 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12005 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12006 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12007 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12008 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12011 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12012 // a simple subregister reference or explicit instructions to grab
12013 // upper bits of a vector.
12014 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12015 SelectionDAG &DAG) {
12017 SDValue In = Op.getOperand(0);
12018 SDValue Idx = Op.getOperand(1);
12019 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12020 MVT ResVT = Op.getSimpleValueType();
12021 MVT InVT = In.getSimpleValueType();
12023 if (Subtarget->hasFp256()) {
12024 if (ResVT.is128BitVector() &&
12025 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12026 isa<ConstantSDNode>(Idx)) {
12027 return Extract128BitVector(In, IdxVal, DAG, dl);
12029 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12030 isa<ConstantSDNode>(Idx)) {
12031 return Extract256BitVector(In, IdxVal, DAG, dl);
12037 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12038 // simple superregister reference or explicit instructions to insert
12039 // the upper bits of a vector.
12040 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12041 SelectionDAG &DAG) {
12042 if (Subtarget->hasFp256()) {
12043 SDLoc dl(Op.getNode());
12044 SDValue Vec = Op.getNode()->getOperand(0);
12045 SDValue SubVec = Op.getNode()->getOperand(1);
12046 SDValue Idx = Op.getNode()->getOperand(2);
12048 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12049 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12050 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12051 isa<ConstantSDNode>(Idx)) {
12052 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12053 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12056 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12057 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12058 isa<ConstantSDNode>(Idx)) {
12059 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12060 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12066 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12067 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12068 // one of the above mentioned nodes. It has to be wrapped because otherwise
12069 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12070 // be used to form addressing mode. These wrapped nodes will be selected
12073 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12074 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12076 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12077 // global base reg.
12078 unsigned char OpFlag = 0;
12079 unsigned WrapperKind = X86ISD::Wrapper;
12080 CodeModel::Model M = DAG.getTarget().getCodeModel();
12082 if (Subtarget->isPICStyleRIPRel() &&
12083 (M == CodeModel::Small || M == CodeModel::Kernel))
12084 WrapperKind = X86ISD::WrapperRIP;
12085 else if (Subtarget->isPICStyleGOT())
12086 OpFlag = X86II::MO_GOTOFF;
12087 else if (Subtarget->isPICStyleStubPIC())
12088 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12090 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12091 CP->getAlignment(),
12092 CP->getOffset(), OpFlag);
12094 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12095 // With PIC, the address is actually $g + Offset.
12097 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12098 DAG.getNode(X86ISD::GlobalBaseReg,
12099 SDLoc(), getPointerTy()),
12106 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12107 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12109 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12110 // global base reg.
12111 unsigned char OpFlag = 0;
12112 unsigned WrapperKind = X86ISD::Wrapper;
12113 CodeModel::Model M = DAG.getTarget().getCodeModel();
12115 if (Subtarget->isPICStyleRIPRel() &&
12116 (M == CodeModel::Small || M == CodeModel::Kernel))
12117 WrapperKind = X86ISD::WrapperRIP;
12118 else if (Subtarget->isPICStyleGOT())
12119 OpFlag = X86II::MO_GOTOFF;
12120 else if (Subtarget->isPICStyleStubPIC())
12121 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12123 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12126 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12128 // With PIC, the address is actually $g + Offset.
12130 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12131 DAG.getNode(X86ISD::GlobalBaseReg,
12132 SDLoc(), getPointerTy()),
12139 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12140 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12142 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12143 // global base reg.
12144 unsigned char OpFlag = 0;
12145 unsigned WrapperKind = X86ISD::Wrapper;
12146 CodeModel::Model M = DAG.getTarget().getCodeModel();
12148 if (Subtarget->isPICStyleRIPRel() &&
12149 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12150 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12151 OpFlag = X86II::MO_GOTPCREL;
12152 WrapperKind = X86ISD::WrapperRIP;
12153 } else if (Subtarget->isPICStyleGOT()) {
12154 OpFlag = X86II::MO_GOT;
12155 } else if (Subtarget->isPICStyleStubPIC()) {
12156 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12157 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12158 OpFlag = X86II::MO_DARWIN_NONLAZY;
12161 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12164 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12166 // With PIC, the address is actually $g + Offset.
12167 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12168 !Subtarget->is64Bit()) {
12169 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12170 DAG.getNode(X86ISD::GlobalBaseReg,
12171 SDLoc(), getPointerTy()),
12175 // For symbols that require a load from a stub to get the address, emit the
12177 if (isGlobalStubReference(OpFlag))
12178 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12179 MachinePointerInfo::getGOT(), false, false, false, 0);
12185 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12186 // Create the TargetBlockAddressAddress node.
12187 unsigned char OpFlags =
12188 Subtarget->ClassifyBlockAddressReference();
12189 CodeModel::Model M = DAG.getTarget().getCodeModel();
12190 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12191 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12193 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12196 if (Subtarget->isPICStyleRIPRel() &&
12197 (M == CodeModel::Small || M == CodeModel::Kernel))
12198 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12200 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12202 // With PIC, the address is actually $g + Offset.
12203 if (isGlobalRelativeToPICBase(OpFlags)) {
12204 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12205 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12213 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12214 int64_t Offset, SelectionDAG &DAG) const {
12215 // Create the TargetGlobalAddress node, folding in the constant
12216 // offset if it is legal.
12217 unsigned char OpFlags =
12218 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12219 CodeModel::Model M = DAG.getTarget().getCodeModel();
12221 if (OpFlags == X86II::MO_NO_FLAG &&
12222 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12223 // A direct static reference to a global.
12224 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12227 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12230 if (Subtarget->isPICStyleRIPRel() &&
12231 (M == CodeModel::Small || M == CodeModel::Kernel))
12232 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12234 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12236 // With PIC, the address is actually $g + Offset.
12237 if (isGlobalRelativeToPICBase(OpFlags)) {
12238 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12239 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12243 // For globals that require a load from a stub to get the address, emit the
12245 if (isGlobalStubReference(OpFlags))
12246 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12247 MachinePointerInfo::getGOT(), false, false, false, 0);
12249 // If there was a non-zero offset that we didn't fold, create an explicit
12250 // addition for it.
12252 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12253 DAG.getConstant(Offset, getPointerTy()));
12259 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12260 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12261 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12262 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12266 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12267 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12268 unsigned char OperandFlags, bool LocalDynamic = false) {
12269 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12270 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12272 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12273 GA->getValueType(0),
12277 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12281 SDValue Ops[] = { Chain, TGA, *InFlag };
12282 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12284 SDValue Ops[] = { Chain, TGA };
12285 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12288 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12289 MFI->setAdjustsStack(true);
12291 SDValue Flag = Chain.getValue(1);
12292 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12295 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12297 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12300 SDLoc dl(GA); // ? function entry point might be better
12301 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12302 DAG.getNode(X86ISD::GlobalBaseReg,
12303 SDLoc(), PtrVT), InFlag);
12304 InFlag = Chain.getValue(1);
12306 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12309 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12311 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12313 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12314 X86::RAX, X86II::MO_TLSGD);
12317 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12323 // Get the start address of the TLS block for this module.
12324 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12325 .getInfo<X86MachineFunctionInfo>();
12326 MFI->incNumLocalDynamicTLSAccesses();
12330 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12331 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12334 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12335 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12336 InFlag = Chain.getValue(1);
12337 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12338 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12341 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12345 unsigned char OperandFlags = X86II::MO_DTPOFF;
12346 unsigned WrapperKind = X86ISD::Wrapper;
12347 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12348 GA->getValueType(0),
12349 GA->getOffset(), OperandFlags);
12350 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12352 // Add x@dtpoff with the base.
12353 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12356 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12357 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12358 const EVT PtrVT, TLSModel::Model model,
12359 bool is64Bit, bool isPIC) {
12362 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12363 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12364 is64Bit ? 257 : 256));
12366 SDValue ThreadPointer =
12367 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12368 MachinePointerInfo(Ptr), false, false, false, 0);
12370 unsigned char OperandFlags = 0;
12371 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12373 unsigned WrapperKind = X86ISD::Wrapper;
12374 if (model == TLSModel::LocalExec) {
12375 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12376 } else if (model == TLSModel::InitialExec) {
12378 OperandFlags = X86II::MO_GOTTPOFF;
12379 WrapperKind = X86ISD::WrapperRIP;
12381 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12384 llvm_unreachable("Unexpected model");
12387 // emit "addl x@ntpoff,%eax" (local exec)
12388 // or "addl x@indntpoff,%eax" (initial exec)
12389 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12391 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12392 GA->getOffset(), OperandFlags);
12393 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12395 if (model == TLSModel::InitialExec) {
12396 if (isPIC && !is64Bit) {
12397 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12398 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12402 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12403 MachinePointerInfo::getGOT(), false, false, false, 0);
12406 // The address of the thread local variable is the add of the thread
12407 // pointer with the offset of the variable.
12408 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12412 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12414 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12415 const GlobalValue *GV = GA->getGlobal();
12417 if (Subtarget->isTargetELF()) {
12418 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12421 case TLSModel::GeneralDynamic:
12422 if (Subtarget->is64Bit())
12423 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12424 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12425 case TLSModel::LocalDynamic:
12426 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12427 Subtarget->is64Bit());
12428 case TLSModel::InitialExec:
12429 case TLSModel::LocalExec:
12430 return LowerToTLSExecModel(
12431 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12432 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12434 llvm_unreachable("Unknown TLS model.");
12437 if (Subtarget->isTargetDarwin()) {
12438 // Darwin only has one model of TLS. Lower to that.
12439 unsigned char OpFlag = 0;
12440 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12441 X86ISD::WrapperRIP : X86ISD::Wrapper;
12443 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12444 // global base reg.
12445 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12446 !Subtarget->is64Bit();
12448 OpFlag = X86II::MO_TLVP_PIC_BASE;
12450 OpFlag = X86II::MO_TLVP;
12452 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12453 GA->getValueType(0),
12454 GA->getOffset(), OpFlag);
12455 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12457 // With PIC32, the address is actually $g + Offset.
12459 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12460 DAG.getNode(X86ISD::GlobalBaseReg,
12461 SDLoc(), getPointerTy()),
12464 // Lowering the machine isd will make sure everything is in the right
12466 SDValue Chain = DAG.getEntryNode();
12467 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12468 SDValue Args[] = { Chain, Offset };
12469 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12471 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12472 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12473 MFI->setAdjustsStack(true);
12475 // And our return value (tls address) is in the standard call return value
12477 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12478 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12479 Chain.getValue(1));
12482 if (Subtarget->isTargetKnownWindowsMSVC() ||
12483 Subtarget->isTargetWindowsGNU()) {
12484 // Just use the implicit TLS architecture
12485 // Need to generate someting similar to:
12486 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12488 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12489 // mov rcx, qword [rdx+rcx*8]
12490 // mov eax, .tls$:tlsvar
12491 // [rax+rcx] contains the address
12492 // Windows 64bit: gs:0x58
12493 // Windows 32bit: fs:__tls_array
12496 SDValue Chain = DAG.getEntryNode();
12498 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12499 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12500 // use its literal value of 0x2C.
12501 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12502 ? Type::getInt8PtrTy(*DAG.getContext(),
12504 : Type::getInt32PtrTy(*DAG.getContext(),
12508 Subtarget->is64Bit()
12509 ? DAG.getIntPtrConstant(0x58)
12510 : (Subtarget->isTargetWindowsGNU()
12511 ? DAG.getIntPtrConstant(0x2C)
12512 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12514 SDValue ThreadPointer =
12515 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12516 MachinePointerInfo(Ptr), false, false, false, 0);
12518 // Load the _tls_index variable
12519 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12520 if (Subtarget->is64Bit())
12521 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12522 IDX, MachinePointerInfo(), MVT::i32,
12523 false, false, false, 0);
12525 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12526 false, false, false, 0);
12528 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12530 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12532 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12533 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12534 false, false, false, 0);
12536 // Get the offset of start of .tls section
12537 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12538 GA->getValueType(0),
12539 GA->getOffset(), X86II::MO_SECREL);
12540 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12542 // The address of the thread local variable is the add of the thread
12543 // pointer with the offset of the variable.
12544 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12547 llvm_unreachable("TLS not implemented for this target.");
12550 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12551 /// and take a 2 x i32 value to shift plus a shift amount.
12552 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12553 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12554 MVT VT = Op.getSimpleValueType();
12555 unsigned VTBits = VT.getSizeInBits();
12557 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12558 SDValue ShOpLo = Op.getOperand(0);
12559 SDValue ShOpHi = Op.getOperand(1);
12560 SDValue ShAmt = Op.getOperand(2);
12561 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12562 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12564 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12565 DAG.getConstant(VTBits - 1, MVT::i8));
12566 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12567 DAG.getConstant(VTBits - 1, MVT::i8))
12568 : DAG.getConstant(0, VT);
12570 SDValue Tmp2, Tmp3;
12571 if (Op.getOpcode() == ISD::SHL_PARTS) {
12572 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12573 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12575 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12576 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12579 // If the shift amount is larger or equal than the width of a part we can't
12580 // rely on the results of shld/shrd. Insert a test and select the appropriate
12581 // values for large shift amounts.
12582 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12583 DAG.getConstant(VTBits, MVT::i8));
12584 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12585 AndNode, DAG.getConstant(0, MVT::i8));
12588 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12589 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12590 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12592 if (Op.getOpcode() == ISD::SHL_PARTS) {
12593 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12594 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12596 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12597 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12600 SDValue Ops[2] = { Lo, Hi };
12601 return DAG.getMergeValues(Ops, dl);
12604 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12605 SelectionDAG &DAG) const {
12606 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12608 if (SrcVT.isVector())
12611 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12612 "Unknown SINT_TO_FP to lower!");
12614 // These are really Legal; return the operand so the caller accepts it as
12616 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12618 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12619 Subtarget->is64Bit()) {
12624 unsigned Size = SrcVT.getSizeInBits()/8;
12625 MachineFunction &MF = DAG.getMachineFunction();
12626 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12627 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12628 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12630 MachinePointerInfo::getFixedStack(SSFI),
12632 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12635 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12637 SelectionDAG &DAG) const {
12641 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12643 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12645 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12647 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12649 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12650 MachineMemOperand *MMO;
12652 int SSFI = FI->getIndex();
12654 DAG.getMachineFunction()
12655 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12656 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12658 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12659 StackSlot = StackSlot.getOperand(1);
12661 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12662 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12664 Tys, Ops, SrcVT, MMO);
12667 Chain = Result.getValue(1);
12668 SDValue InFlag = Result.getValue(2);
12670 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12671 // shouldn't be necessary except that RFP cannot be live across
12672 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12673 MachineFunction &MF = DAG.getMachineFunction();
12674 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12675 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12676 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12677 Tys = DAG.getVTList(MVT::Other);
12679 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12681 MachineMemOperand *MMO =
12682 DAG.getMachineFunction()
12683 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12684 MachineMemOperand::MOStore, SSFISize, SSFISize);
12686 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12687 Ops, Op.getValueType(), MMO);
12688 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
12689 MachinePointerInfo::getFixedStack(SSFI),
12690 false, false, false, 0);
12696 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12697 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12698 SelectionDAG &DAG) const {
12699 // This algorithm is not obvious. Here it is what we're trying to output:
12702 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12703 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12705 haddpd %xmm0, %xmm0
12707 pshufd $0x4e, %xmm0, %xmm1
12713 LLVMContext *Context = DAG.getContext();
12715 // Build some magic constants.
12716 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12717 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12718 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
12720 SmallVector<Constant*,2> CV1;
12722 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12723 APInt(64, 0x4330000000000000ULL))));
12725 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12726 APInt(64, 0x4530000000000000ULL))));
12727 Constant *C1 = ConstantVector::get(CV1);
12728 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
12730 // Load the 64-bit value into an XMM register.
12731 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12733 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12734 MachinePointerInfo::getConstantPool(),
12735 false, false, false, 16);
12736 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
12737 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
12740 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12741 MachinePointerInfo::getConstantPool(),
12742 false, false, false, 16);
12743 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
12744 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12747 if (Subtarget->hasSSE3()) {
12748 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12749 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12751 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
12752 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12754 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12755 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
12759 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12760 DAG.getIntPtrConstant(0));
12763 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12764 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12765 SelectionDAG &DAG) const {
12767 // FP constant to bias correct the final result.
12768 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12771 // Load the 32-bit value into an XMM register.
12772 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12775 // Zero out the upper parts of the register.
12776 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12778 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12779 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
12780 DAG.getIntPtrConstant(0));
12782 // Or the load with the bias.
12783 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
12784 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12785 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12786 MVT::v2f64, Load)),
12787 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12788 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12789 MVT::v2f64, Bias)));
12790 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12791 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
12792 DAG.getIntPtrConstant(0));
12794 // Subtract the bias.
12795 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12797 // Handle final rounding.
12798 EVT DestVT = Op.getValueType();
12800 if (DestVT.bitsLT(MVT::f64))
12801 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12802 DAG.getIntPtrConstant(0));
12803 if (DestVT.bitsGT(MVT::f64))
12804 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12806 // Handle final rounding.
12810 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12811 SelectionDAG &DAG) const {
12812 SDValue N0 = Op.getOperand(0);
12813 MVT SVT = N0.getSimpleValueType();
12816 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
12817 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
12818 "Custom UINT_TO_FP is not supported!");
12820 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12821 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12822 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12825 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12826 SelectionDAG &DAG) const {
12827 SDValue N0 = Op.getOperand(0);
12830 if (Op.getValueType().isVector())
12831 return lowerUINT_TO_FP_vec(Op, DAG);
12833 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12834 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12835 // the optimization here.
12836 if (DAG.SignBitIsZero(N0))
12837 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12839 MVT SrcVT = N0.getSimpleValueType();
12840 MVT DstVT = Op.getSimpleValueType();
12841 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12842 return LowerUINT_TO_FP_i64(Op, DAG);
12843 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12844 return LowerUINT_TO_FP_i32(Op, DAG);
12845 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12848 // Make a 64-bit buffer, and use it to build an FILD.
12849 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12850 if (SrcVT == MVT::i32) {
12851 SDValue WordOff = DAG.getConstant(4, getPointerTy());
12852 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
12853 getPointerTy(), StackSlot, WordOff);
12854 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12855 StackSlot, MachinePointerInfo(),
12857 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
12858 OffsetSlot, MachinePointerInfo(),
12860 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12864 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12865 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12866 StackSlot, MachinePointerInfo(),
12868 // For i64 source, we need to add the appropriate power of 2 if the input
12869 // was negative. This is the same as the optimization in
12870 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12871 // we must be careful to do the computation in x87 extended precision, not
12872 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12873 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12874 MachineMemOperand *MMO =
12875 DAG.getMachineFunction()
12876 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12877 MachineMemOperand::MOLoad, 8, 8);
12879 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12880 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12881 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12884 APInt FF(32, 0x5F800000ULL);
12886 // Check whether the sign bit is set.
12887 SDValue SignSet = DAG.getSetCC(dl,
12888 getSetCCResultType(*DAG.getContext(), MVT::i64),
12889 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
12892 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12893 SDValue FudgePtr = DAG.getConstantPool(
12894 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
12897 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12898 SDValue Zero = DAG.getIntPtrConstant(0);
12899 SDValue Four = DAG.getIntPtrConstant(4);
12900 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12902 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
12904 // Load the value out, extending it from f32 to f80.
12905 // FIXME: Avoid the extend by constructing the right constant pool?
12906 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12907 FudgePtr, MachinePointerInfo::getConstantPool(),
12908 MVT::f32, false, false, false, 4);
12909 // Extend everything to 80 bits to force it to be done on x87.
12910 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12911 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
12914 std::pair<SDValue,SDValue>
12915 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12916 bool IsSigned, bool IsReplace) const {
12919 EVT DstTy = Op.getValueType();
12921 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12922 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12926 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12927 DstTy.getSimpleVT() >= MVT::i16 &&
12928 "Unknown FP_TO_INT to lower!");
12930 // These are really Legal.
12931 if (DstTy == MVT::i32 &&
12932 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12933 return std::make_pair(SDValue(), SDValue());
12934 if (Subtarget->is64Bit() &&
12935 DstTy == MVT::i64 &&
12936 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12937 return std::make_pair(SDValue(), SDValue());
12939 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12940 // stack slot, or into the FTOL runtime function.
12941 MachineFunction &MF = DAG.getMachineFunction();
12942 unsigned MemSize = DstTy.getSizeInBits()/8;
12943 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12944 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12947 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12948 Opc = X86ISD::WIN_FTOL;
12950 switch (DstTy.getSimpleVT().SimpleTy) {
12951 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12952 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12953 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12954 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12957 SDValue Chain = DAG.getEntryNode();
12958 SDValue Value = Op.getOperand(0);
12959 EVT TheVT = Op.getOperand(0).getValueType();
12960 // FIXME This causes a redundant load/store if the SSE-class value is already
12961 // in memory, such as if it is on the callstack.
12962 if (isScalarFPTypeInSSEReg(TheVT)) {
12963 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12964 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12965 MachinePointerInfo::getFixedStack(SSFI),
12967 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12969 Chain, StackSlot, DAG.getValueType(TheVT)
12972 MachineMemOperand *MMO =
12973 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12974 MachineMemOperand::MOLoad, MemSize, MemSize);
12975 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12976 Chain = Value.getValue(1);
12977 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12978 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12981 MachineMemOperand *MMO =
12982 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12983 MachineMemOperand::MOStore, MemSize, MemSize);
12985 if (Opc != X86ISD::WIN_FTOL) {
12986 // Build the FP_TO_INT*_IN_MEM
12987 SDValue Ops[] = { Chain, Value, StackSlot };
12988 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12990 return std::make_pair(FIST, StackSlot);
12992 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12993 DAG.getVTList(MVT::Other, MVT::Glue),
12995 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12996 MVT::i32, ftol.getValue(1));
12997 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12998 MVT::i32, eax.getValue(2));
12999 SDValue Ops[] = { eax, edx };
13000 SDValue pair = IsReplace
13001 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13002 : DAG.getMergeValues(Ops, DL);
13003 return std::make_pair(pair, SDValue());
13007 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13008 const X86Subtarget *Subtarget) {
13009 MVT VT = Op->getSimpleValueType(0);
13010 SDValue In = Op->getOperand(0);
13011 MVT InVT = In.getSimpleValueType();
13014 // Optimize vectors in AVX mode:
13017 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13018 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13019 // Concat upper and lower parts.
13022 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13023 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13024 // Concat upper and lower parts.
13027 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13028 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13029 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13032 if (Subtarget->hasInt256())
13033 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13035 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13036 SDValue Undef = DAG.getUNDEF(InVT);
13037 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13038 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13039 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13041 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13042 VT.getVectorNumElements()/2);
13044 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13045 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13047 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13050 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13051 SelectionDAG &DAG) {
13052 MVT VT = Op->getSimpleValueType(0);
13053 SDValue In = Op->getOperand(0);
13054 MVT InVT = In.getSimpleValueType();
13056 unsigned int NumElts = VT.getVectorNumElements();
13057 if (NumElts != 8 && NumElts != 16)
13060 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13061 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13063 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13064 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13065 // Now we have only mask extension
13066 assert(InVT.getVectorElementType() == MVT::i1);
13067 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13068 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13069 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13070 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13071 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13072 MachinePointerInfo::getConstantPool(),
13073 false, false, false, Alignment);
13075 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13076 if (VT.is512BitVector())
13078 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13081 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13082 SelectionDAG &DAG) {
13083 if (Subtarget->hasFp256()) {
13084 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13092 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13093 SelectionDAG &DAG) {
13095 MVT VT = Op.getSimpleValueType();
13096 SDValue In = Op.getOperand(0);
13097 MVT SVT = In.getSimpleValueType();
13099 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13100 return LowerZERO_EXTEND_AVX512(Op, DAG);
13102 if (Subtarget->hasFp256()) {
13103 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13108 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13109 VT.getVectorNumElements() != SVT.getVectorNumElements());
13113 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13115 MVT VT = Op.getSimpleValueType();
13116 SDValue In = Op.getOperand(0);
13117 MVT InVT = In.getSimpleValueType();
13119 if (VT == MVT::i1) {
13120 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13121 "Invalid scalar TRUNCATE operation");
13122 if (InVT.getSizeInBits() >= 32)
13124 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13125 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13127 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13128 "Invalid TRUNCATE operation");
13130 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13131 if (VT.getVectorElementType().getSizeInBits() >=8)
13132 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13134 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13135 unsigned NumElts = InVT.getVectorNumElements();
13136 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13137 if (InVT.getSizeInBits() < 512) {
13138 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13139 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13143 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13144 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13145 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13146 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13147 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13148 MachinePointerInfo::getConstantPool(),
13149 false, false, false, Alignment);
13150 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13151 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13152 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13155 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13156 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13157 if (Subtarget->hasInt256()) {
13158 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13159 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13160 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13162 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13163 DAG.getIntPtrConstant(0));
13166 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13167 DAG.getIntPtrConstant(0));
13168 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13169 DAG.getIntPtrConstant(2));
13170 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13171 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13172 static const int ShufMask[] = {0, 2, 4, 6};
13173 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13176 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13177 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13178 if (Subtarget->hasInt256()) {
13179 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13181 SmallVector<SDValue,32> pshufbMask;
13182 for (unsigned i = 0; i < 2; ++i) {
13183 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13184 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13185 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13186 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13187 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13188 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13189 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13190 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13191 for (unsigned j = 0; j < 8; ++j)
13192 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13194 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13195 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13196 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13198 static const int ShufMask[] = {0, 2, -1, -1};
13199 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13201 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13202 DAG.getIntPtrConstant(0));
13203 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13206 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13207 DAG.getIntPtrConstant(0));
13209 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13210 DAG.getIntPtrConstant(4));
13212 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13213 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13215 // The PSHUFB mask:
13216 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13217 -1, -1, -1, -1, -1, -1, -1, -1};
13219 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13220 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13221 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13223 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13224 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13226 // The MOVLHPS Mask:
13227 static const int ShufMask2[] = {0, 1, 4, 5};
13228 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13229 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13232 // Handle truncation of V256 to V128 using shuffles.
13233 if (!VT.is128BitVector() || !InVT.is256BitVector())
13236 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13238 unsigned NumElems = VT.getVectorNumElements();
13239 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13241 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13242 // Prepare truncation shuffle mask
13243 for (unsigned i = 0; i != NumElems; ++i)
13244 MaskVec[i] = i * 2;
13245 SDValue V = DAG.getVectorShuffle(NVT, DL,
13246 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13247 DAG.getUNDEF(NVT), &MaskVec[0]);
13248 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13249 DAG.getIntPtrConstant(0));
13252 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13253 SelectionDAG &DAG) const {
13254 assert(!Op.getSimpleValueType().isVector());
13256 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13257 /*IsSigned=*/ true, /*IsReplace=*/ false);
13258 SDValue FIST = Vals.first, StackSlot = Vals.second;
13259 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13260 if (!FIST.getNode()) return Op;
13262 if (StackSlot.getNode())
13263 // Load the result.
13264 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13265 FIST, StackSlot, MachinePointerInfo(),
13266 false, false, false, 0);
13268 // The node is the result.
13272 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13273 SelectionDAG &DAG) const {
13274 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13275 /*IsSigned=*/ false, /*IsReplace=*/ false);
13276 SDValue FIST = Vals.first, StackSlot = Vals.second;
13277 assert(FIST.getNode() && "Unexpected failure");
13279 if (StackSlot.getNode())
13280 // Load the result.
13281 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13282 FIST, StackSlot, MachinePointerInfo(),
13283 false, false, false, 0);
13285 // The node is the result.
13289 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13291 MVT VT = Op.getSimpleValueType();
13292 SDValue In = Op.getOperand(0);
13293 MVT SVT = In.getSimpleValueType();
13295 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13297 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13298 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13299 In, DAG.getUNDEF(SVT)));
13302 // The only differences between FABS and FNEG are the mask and the logic op.
13303 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13304 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13305 "Wrong opcode for lowering FABS or FNEG.");
13307 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13309 MVT VT = Op.getSimpleValueType();
13310 // Assume scalar op for initialization; update for vector if needed.
13311 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13312 // generate a 16-byte vector constant and logic op even for the scalar case.
13313 // Using a 16-byte mask allows folding the load of the mask with
13314 // the logic op, so it can save (~4 bytes) on code size.
13316 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13317 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13318 // decide if we should generate a 16-byte constant mask when we only need 4 or
13319 // 8 bytes for the scalar case.
13320 if (VT.isVector()) {
13321 EltVT = VT.getVectorElementType();
13322 NumElts = VT.getVectorNumElements();
13325 unsigned EltBits = EltVT.getSizeInBits();
13326 LLVMContext *Context = DAG.getContext();
13327 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13329 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13330 Constant *C = ConstantInt::get(*Context, MaskElt);
13331 C = ConstantVector::getSplat(NumElts, C);
13332 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13333 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13334 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13335 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13336 MachinePointerInfo::getConstantPool(),
13337 false, false, false, Alignment);
13339 if (VT.isVector()) {
13340 // For a vector, cast operands to a vector type, perform the logic op,
13341 // and cast the result back to the original value type.
13342 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13343 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
13344 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13345 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
13346 return DAG.getNode(ISD::BITCAST, dl, VT,
13347 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
13349 // If not vector, then scalar.
13350 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
13351 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
13354 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13355 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13356 LLVMContext *Context = DAG.getContext();
13357 SDValue Op0 = Op.getOperand(0);
13358 SDValue Op1 = Op.getOperand(1);
13360 MVT VT = Op.getSimpleValueType();
13361 MVT SrcVT = Op1.getSimpleValueType();
13363 // If second operand is smaller, extend it first.
13364 if (SrcVT.bitsLT(VT)) {
13365 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13368 // And if it is bigger, shrink it first.
13369 if (SrcVT.bitsGT(VT)) {
13370 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13374 // At this point the operands and the result should have the same
13375 // type, and that won't be f80 since that is not custom lowered.
13377 // First get the sign bit of second operand.
13378 SmallVector<Constant*,4> CV;
13379 if (SrcVT == MVT::f64) {
13380 const fltSemantics &Sem = APFloat::IEEEdouble;
13381 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13382 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13384 const fltSemantics &Sem = APFloat::IEEEsingle;
13385 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13386 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13387 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13388 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13390 Constant *C = ConstantVector::get(CV);
13391 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13392 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13393 MachinePointerInfo::getConstantPool(),
13394 false, false, false, 16);
13395 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13397 // Shift sign bit right or left if the two operands have different types.
13398 if (SrcVT.bitsGT(VT)) {
13399 // Op0 is MVT::f32, Op1 is MVT::f64.
13400 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13401 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13402 DAG.getConstant(32, MVT::i32));
13403 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13404 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13405 DAG.getIntPtrConstant(0));
13408 // Clear first operand sign bit.
13410 if (VT == MVT::f64) {
13411 const fltSemantics &Sem = APFloat::IEEEdouble;
13412 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13413 APInt(64, ~(1ULL << 63)))));
13414 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13416 const fltSemantics &Sem = APFloat::IEEEsingle;
13417 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13418 APInt(32, ~(1U << 31)))));
13419 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13420 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13421 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13423 C = ConstantVector::get(CV);
13424 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13425 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13426 MachinePointerInfo::getConstantPool(),
13427 false, false, false, 16);
13428 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13430 // Or the value with the sign bit.
13431 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13434 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13435 SDValue N0 = Op.getOperand(0);
13437 MVT VT = Op.getSimpleValueType();
13439 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13440 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13441 DAG.getConstant(1, VT));
13442 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13445 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
13447 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13448 SelectionDAG &DAG) {
13449 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13451 if (!Subtarget->hasSSE41())
13454 if (!Op->hasOneUse())
13457 SDNode *N = Op.getNode();
13460 SmallVector<SDValue, 8> Opnds;
13461 DenseMap<SDValue, unsigned> VecInMap;
13462 SmallVector<SDValue, 8> VecIns;
13463 EVT VT = MVT::Other;
13465 // Recognize a special case where a vector is casted into wide integer to
13467 Opnds.push_back(N->getOperand(0));
13468 Opnds.push_back(N->getOperand(1));
13470 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13471 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13472 // BFS traverse all OR'd operands.
13473 if (I->getOpcode() == ISD::OR) {
13474 Opnds.push_back(I->getOperand(0));
13475 Opnds.push_back(I->getOperand(1));
13476 // Re-evaluate the number of nodes to be traversed.
13477 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13481 // Quit if a non-EXTRACT_VECTOR_ELT
13482 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13485 // Quit if without a constant index.
13486 SDValue Idx = I->getOperand(1);
13487 if (!isa<ConstantSDNode>(Idx))
13490 SDValue ExtractedFromVec = I->getOperand(0);
13491 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13492 if (M == VecInMap.end()) {
13493 VT = ExtractedFromVec.getValueType();
13494 // Quit if not 128/256-bit vector.
13495 if (!VT.is128BitVector() && !VT.is256BitVector())
13497 // Quit if not the same type.
13498 if (VecInMap.begin() != VecInMap.end() &&
13499 VT != VecInMap.begin()->first.getValueType())
13501 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13502 VecIns.push_back(ExtractedFromVec);
13504 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13507 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13508 "Not extracted from 128-/256-bit vector.");
13510 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13512 for (DenseMap<SDValue, unsigned>::const_iterator
13513 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13514 // Quit if not all elements are used.
13515 if (I->second != FullMask)
13519 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13521 // Cast all vectors into TestVT for PTEST.
13522 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13523 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13525 // If more than one full vectors are evaluated, OR them first before PTEST.
13526 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13527 // Each iteration will OR 2 nodes and append the result until there is only
13528 // 1 node left, i.e. the final OR'd value of all vectors.
13529 SDValue LHS = VecIns[Slot];
13530 SDValue RHS = VecIns[Slot + 1];
13531 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13534 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13535 VecIns.back(), VecIns.back());
13538 /// \brief return true if \c Op has a use that doesn't just read flags.
13539 static bool hasNonFlagsUse(SDValue Op) {
13540 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13542 SDNode *User = *UI;
13543 unsigned UOpNo = UI.getOperandNo();
13544 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13545 // Look pass truncate.
13546 UOpNo = User->use_begin().getOperandNo();
13547 User = *User->use_begin();
13550 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13551 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13557 /// Emit nodes that will be selected as "test Op0,Op0", or something
13559 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13560 SelectionDAG &DAG) const {
13561 if (Op.getValueType() == MVT::i1)
13562 // KORTEST instruction should be selected
13563 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13564 DAG.getConstant(0, Op.getValueType()));
13566 // CF and OF aren't always set the way we want. Determine which
13567 // of these we need.
13568 bool NeedCF = false;
13569 bool NeedOF = false;
13572 case X86::COND_A: case X86::COND_AE:
13573 case X86::COND_B: case X86::COND_BE:
13576 case X86::COND_G: case X86::COND_GE:
13577 case X86::COND_L: case X86::COND_LE:
13578 case X86::COND_O: case X86::COND_NO: {
13579 // Check if we really need to set the
13580 // Overflow flag. If NoSignedWrap is present
13581 // that is not actually needed.
13582 switch (Op->getOpcode()) {
13587 const BinaryWithFlagsSDNode *BinNode =
13588 cast<BinaryWithFlagsSDNode>(Op.getNode());
13589 if (BinNode->hasNoSignedWrap())
13599 // See if we can use the EFLAGS value from the operand instead of
13600 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13601 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13602 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13603 // Emit a CMP with 0, which is the TEST pattern.
13604 //if (Op.getValueType() == MVT::i1)
13605 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13606 // DAG.getConstant(0, MVT::i1));
13607 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13608 DAG.getConstant(0, Op.getValueType()));
13610 unsigned Opcode = 0;
13611 unsigned NumOperands = 0;
13613 // Truncate operations may prevent the merge of the SETCC instruction
13614 // and the arithmetic instruction before it. Attempt to truncate the operands
13615 // of the arithmetic instruction and use a reduced bit-width instruction.
13616 bool NeedTruncation = false;
13617 SDValue ArithOp = Op;
13618 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13619 SDValue Arith = Op->getOperand(0);
13620 // Both the trunc and the arithmetic op need to have one user each.
13621 if (Arith->hasOneUse())
13622 switch (Arith.getOpcode()) {
13629 NeedTruncation = true;
13635 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13636 // which may be the result of a CAST. We use the variable 'Op', which is the
13637 // non-casted variable when we check for possible users.
13638 switch (ArithOp.getOpcode()) {
13640 // Due to an isel shortcoming, be conservative if this add is likely to be
13641 // selected as part of a load-modify-store instruction. When the root node
13642 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13643 // uses of other nodes in the match, such as the ADD in this case. This
13644 // leads to the ADD being left around and reselected, with the result being
13645 // two adds in the output. Alas, even if none our users are stores, that
13646 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13647 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13648 // climbing the DAG back to the root, and it doesn't seem to be worth the
13650 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13651 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13652 if (UI->getOpcode() != ISD::CopyToReg &&
13653 UI->getOpcode() != ISD::SETCC &&
13654 UI->getOpcode() != ISD::STORE)
13657 if (ConstantSDNode *C =
13658 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13659 // An add of one will be selected as an INC.
13660 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13661 Opcode = X86ISD::INC;
13666 // An add of negative one (subtract of one) will be selected as a DEC.
13667 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13668 Opcode = X86ISD::DEC;
13674 // Otherwise use a regular EFLAGS-setting add.
13675 Opcode = X86ISD::ADD;
13680 // If we have a constant logical shift that's only used in a comparison
13681 // against zero turn it into an equivalent AND. This allows turning it into
13682 // a TEST instruction later.
13683 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13684 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13685 EVT VT = Op.getValueType();
13686 unsigned BitWidth = VT.getSizeInBits();
13687 unsigned ShAmt = Op->getConstantOperandVal(1);
13688 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13690 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13691 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13692 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13693 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13695 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13696 DAG.getConstant(Mask, VT));
13697 DAG.ReplaceAllUsesWith(Op, New);
13703 // If the primary and result isn't used, don't bother using X86ISD::AND,
13704 // because a TEST instruction will be better.
13705 if (!hasNonFlagsUse(Op))
13711 // Due to the ISEL shortcoming noted above, be conservative if this op is
13712 // likely to be selected as part of a load-modify-store instruction.
13713 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13714 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13715 if (UI->getOpcode() == ISD::STORE)
13718 // Otherwise use a regular EFLAGS-setting instruction.
13719 switch (ArithOp.getOpcode()) {
13720 default: llvm_unreachable("unexpected operator!");
13721 case ISD::SUB: Opcode = X86ISD::SUB; break;
13722 case ISD::XOR: Opcode = X86ISD::XOR; break;
13723 case ISD::AND: Opcode = X86ISD::AND; break;
13725 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13726 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13727 if (EFLAGS.getNode())
13730 Opcode = X86ISD::OR;
13744 return SDValue(Op.getNode(), 1);
13750 // If we found that truncation is beneficial, perform the truncation and
13752 if (NeedTruncation) {
13753 EVT VT = Op.getValueType();
13754 SDValue WideVal = Op->getOperand(0);
13755 EVT WideVT = WideVal.getValueType();
13756 unsigned ConvertedOp = 0;
13757 // Use a target machine opcode to prevent further DAGCombine
13758 // optimizations that may separate the arithmetic operations
13759 // from the setcc node.
13760 switch (WideVal.getOpcode()) {
13762 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13763 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13764 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13765 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13766 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13770 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13771 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13772 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13773 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13774 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13780 // Emit a CMP with 0, which is the TEST pattern.
13781 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13782 DAG.getConstant(0, Op.getValueType()));
13784 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13785 SmallVector<SDValue, 4> Ops;
13786 for (unsigned i = 0; i != NumOperands; ++i)
13787 Ops.push_back(Op.getOperand(i));
13789 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13790 DAG.ReplaceAllUsesWith(Op, New);
13791 return SDValue(New.getNode(), 1);
13794 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13796 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13797 SDLoc dl, SelectionDAG &DAG) const {
13798 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13799 if (C->getAPIntValue() == 0)
13800 return EmitTest(Op0, X86CC, dl, DAG);
13802 if (Op0.getValueType() == MVT::i1)
13803 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13806 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13807 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13808 // Do the comparison at i32 if it's smaller, besides the Atom case.
13809 // This avoids subregister aliasing issues. Keep the smaller reference
13810 // if we're optimizing for size, however, as that'll allow better folding
13811 // of memory operations.
13812 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13813 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
13814 AttributeSet::FunctionIndex, Attribute::MinSize) &&
13815 !Subtarget->isAtom()) {
13816 unsigned ExtendOp =
13817 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13818 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13819 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13821 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13822 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13823 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13825 return SDValue(Sub.getNode(), 1);
13827 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13830 /// Convert a comparison if required by the subtarget.
13831 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13832 SelectionDAG &DAG) const {
13833 // If the subtarget does not support the FUCOMI instruction, floating-point
13834 // comparisons have to be converted.
13835 if (Subtarget->hasCMov() ||
13836 Cmp.getOpcode() != X86ISD::CMP ||
13837 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13838 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13841 // The instruction selector will select an FUCOM instruction instead of
13842 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13843 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13844 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13846 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13847 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13848 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13849 DAG.getConstant(8, MVT::i8));
13850 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13851 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13854 static bool isAllOnes(SDValue V) {
13855 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13856 return C && C->isAllOnesValue();
13859 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13860 /// if it's possible.
13861 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13862 SDLoc dl, SelectionDAG &DAG) const {
13863 SDValue Op0 = And.getOperand(0);
13864 SDValue Op1 = And.getOperand(1);
13865 if (Op0.getOpcode() == ISD::TRUNCATE)
13866 Op0 = Op0.getOperand(0);
13867 if (Op1.getOpcode() == ISD::TRUNCATE)
13868 Op1 = Op1.getOperand(0);
13871 if (Op1.getOpcode() == ISD::SHL)
13872 std::swap(Op0, Op1);
13873 if (Op0.getOpcode() == ISD::SHL) {
13874 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13875 if (And00C->getZExtValue() == 1) {
13876 // If we looked past a truncate, check that it's only truncating away
13878 unsigned BitWidth = Op0.getValueSizeInBits();
13879 unsigned AndBitWidth = And.getValueSizeInBits();
13880 if (BitWidth > AndBitWidth) {
13882 DAG.computeKnownBits(Op0, Zeros, Ones);
13883 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13887 RHS = Op0.getOperand(1);
13889 } else if (Op1.getOpcode() == ISD::Constant) {
13890 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13891 uint64_t AndRHSVal = AndRHS->getZExtValue();
13892 SDValue AndLHS = Op0;
13894 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13895 LHS = AndLHS.getOperand(0);
13896 RHS = AndLHS.getOperand(1);
13899 // Use BT if the immediate can't be encoded in a TEST instruction.
13900 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13902 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
13906 if (LHS.getNode()) {
13907 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13908 // instruction. Since the shift amount is in-range-or-undefined, we know
13909 // that doing a bittest on the i32 value is ok. We extend to i32 because
13910 // the encoding for the i16 version is larger than the i32 version.
13911 // Also promote i16 to i32 for performance / code size reason.
13912 if (LHS.getValueType() == MVT::i8 ||
13913 LHS.getValueType() == MVT::i16)
13914 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13916 // If the operand types disagree, extend the shift amount to match. Since
13917 // BT ignores high bits (like shifts) we can use anyextend.
13918 if (LHS.getValueType() != RHS.getValueType())
13919 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13921 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13922 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13923 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13924 DAG.getConstant(Cond, MVT::i8), BT);
13930 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13932 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13937 // SSE Condition code mapping:
13946 switch (SetCCOpcode) {
13947 default: llvm_unreachable("Unexpected SETCC condition");
13949 case ISD::SETEQ: SSECC = 0; break;
13951 case ISD::SETGT: Swap = true; // Fallthrough
13953 case ISD::SETOLT: SSECC = 1; break;
13955 case ISD::SETGE: Swap = true; // Fallthrough
13957 case ISD::SETOLE: SSECC = 2; break;
13958 case ISD::SETUO: SSECC = 3; break;
13960 case ISD::SETNE: SSECC = 4; break;
13961 case ISD::SETULE: Swap = true; // Fallthrough
13962 case ISD::SETUGE: SSECC = 5; break;
13963 case ISD::SETULT: Swap = true; // Fallthrough
13964 case ISD::SETUGT: SSECC = 6; break;
13965 case ISD::SETO: SSECC = 7; break;
13967 case ISD::SETONE: SSECC = 8; break;
13970 std::swap(Op0, Op1);
13975 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13976 // ones, and then concatenate the result back.
13977 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13978 MVT VT = Op.getSimpleValueType();
13980 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13981 "Unsupported value type for operation");
13983 unsigned NumElems = VT.getVectorNumElements();
13985 SDValue CC = Op.getOperand(2);
13987 // Extract the LHS vectors
13988 SDValue LHS = Op.getOperand(0);
13989 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13990 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13992 // Extract the RHS vectors
13993 SDValue RHS = Op.getOperand(1);
13994 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13995 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13997 // Issue the operation on the smaller types and concatenate the result back
13998 MVT EltVT = VT.getVectorElementType();
13999 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14000 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14001 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14002 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14005 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14006 const X86Subtarget *Subtarget) {
14007 SDValue Op0 = Op.getOperand(0);
14008 SDValue Op1 = Op.getOperand(1);
14009 SDValue CC = Op.getOperand(2);
14010 MVT VT = Op.getSimpleValueType();
14013 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14014 Op.getValueType().getScalarType() == MVT::i1 &&
14015 "Cannot set masked compare for this operation");
14017 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14019 bool Unsigned = false;
14022 switch (SetCCOpcode) {
14023 default: llvm_unreachable("Unexpected SETCC condition");
14024 case ISD::SETNE: SSECC = 4; break;
14025 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14026 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14027 case ISD::SETLT: Swap = true; //fall-through
14028 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14029 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14030 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14031 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14032 case ISD::SETULE: Unsigned = true; //fall-through
14033 case ISD::SETLE: SSECC = 2; break;
14037 std::swap(Op0, Op1);
14039 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14040 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14041 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14042 DAG.getConstant(SSECC, MVT::i8));
14045 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14046 /// operand \p Op1. If non-trivial (for example because it's not constant)
14047 /// return an empty value.
14048 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14050 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14054 MVT VT = Op1.getSimpleValueType();
14055 MVT EVT = VT.getVectorElementType();
14056 unsigned n = VT.getVectorNumElements();
14057 SmallVector<SDValue, 8> ULTOp1;
14059 for (unsigned i = 0; i < n; ++i) {
14060 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14061 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14064 // Avoid underflow.
14065 APInt Val = Elt->getAPIntValue();
14069 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14072 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14075 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14076 SelectionDAG &DAG) {
14077 SDValue Op0 = Op.getOperand(0);
14078 SDValue Op1 = Op.getOperand(1);
14079 SDValue CC = Op.getOperand(2);
14080 MVT VT = Op.getSimpleValueType();
14081 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14082 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14087 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14088 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14091 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14092 unsigned Opc = X86ISD::CMPP;
14093 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14094 assert(VT.getVectorNumElements() <= 16);
14095 Opc = X86ISD::CMPM;
14097 // In the two special cases we can't handle, emit two comparisons.
14100 unsigned CombineOpc;
14101 if (SetCCOpcode == ISD::SETUEQ) {
14102 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14104 assert(SetCCOpcode == ISD::SETONE);
14105 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14108 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14109 DAG.getConstant(CC0, MVT::i8));
14110 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14111 DAG.getConstant(CC1, MVT::i8));
14112 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14114 // Handle all other FP comparisons here.
14115 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14116 DAG.getConstant(SSECC, MVT::i8));
14119 // Break 256-bit integer vector compare into smaller ones.
14120 if (VT.is256BitVector() && !Subtarget->hasInt256())
14121 return Lower256IntVSETCC(Op, DAG);
14123 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14124 EVT OpVT = Op1.getValueType();
14125 if (Subtarget->hasAVX512()) {
14126 if (Op1.getValueType().is512BitVector() ||
14127 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14128 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14129 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14131 // In AVX-512 architecture setcc returns mask with i1 elements,
14132 // But there is no compare instruction for i8 and i16 elements in KNL.
14133 // We are not talking about 512-bit operands in this case, these
14134 // types are illegal.
14136 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14137 OpVT.getVectorElementType().getSizeInBits() >= 8))
14138 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14139 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14142 // We are handling one of the integer comparisons here. Since SSE only has
14143 // GT and EQ comparisons for integer, swapping operands and multiple
14144 // operations may be required for some comparisons.
14146 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14147 bool Subus = false;
14149 switch (SetCCOpcode) {
14150 default: llvm_unreachable("Unexpected SETCC condition");
14151 case ISD::SETNE: Invert = true;
14152 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14153 case ISD::SETLT: Swap = true;
14154 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14155 case ISD::SETGE: Swap = true;
14156 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14157 Invert = true; break;
14158 case ISD::SETULT: Swap = true;
14159 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14160 FlipSigns = true; break;
14161 case ISD::SETUGE: Swap = true;
14162 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14163 FlipSigns = true; Invert = true; break;
14166 // Special case: Use min/max operations for SETULE/SETUGE
14167 MVT VET = VT.getVectorElementType();
14169 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14170 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14173 switch (SetCCOpcode) {
14175 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14176 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14179 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14182 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14183 if (!MinMax && hasSubus) {
14184 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14186 // t = psubus Op0, Op1
14187 // pcmpeq t, <0..0>
14188 switch (SetCCOpcode) {
14190 case ISD::SETULT: {
14191 // If the comparison is against a constant we can turn this into a
14192 // setule. With psubus, setule does not require a swap. This is
14193 // beneficial because the constant in the register is no longer
14194 // destructed as the destination so it can be hoisted out of a loop.
14195 // Only do this pre-AVX since vpcmp* is no longer destructive.
14196 if (Subtarget->hasAVX())
14198 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14199 if (ULEOp1.getNode()) {
14201 Subus = true; Invert = false; Swap = false;
14205 // Psubus is better than flip-sign because it requires no inversion.
14206 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14207 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14211 Opc = X86ISD::SUBUS;
14217 std::swap(Op0, Op1);
14219 // Check that the operation in question is available (most are plain SSE2,
14220 // but PCMPGTQ and PCMPEQQ have different requirements).
14221 if (VT == MVT::v2i64) {
14222 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14223 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14225 // First cast everything to the right type.
14226 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14227 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14229 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14230 // bits of the inputs before performing those operations. The lower
14231 // compare is always unsigned.
14234 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14236 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14237 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14238 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14239 Sign, Zero, Sign, Zero);
14241 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14242 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14244 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14245 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14246 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14248 // Create masks for only the low parts/high parts of the 64 bit integers.
14249 static const int MaskHi[] = { 1, 1, 3, 3 };
14250 static const int MaskLo[] = { 0, 0, 2, 2 };
14251 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14252 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14253 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14255 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14256 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14259 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14261 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14264 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14265 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14266 // pcmpeqd + pshufd + pand.
14267 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14269 // First cast everything to the right type.
14270 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14271 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14274 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14276 // Make sure the lower and upper halves are both all-ones.
14277 static const int Mask[] = { 1, 0, 3, 2 };
14278 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14279 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14282 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14284 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14288 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14289 // bits of the inputs before performing those operations.
14291 EVT EltVT = VT.getVectorElementType();
14292 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14293 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14294 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14297 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14299 // If the logical-not of the result is required, perform that now.
14301 Result = DAG.getNOT(dl, Result, VT);
14304 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14307 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14308 getZeroVector(VT, Subtarget, DAG, dl));
14313 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14315 MVT VT = Op.getSimpleValueType();
14317 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14319 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14320 && "SetCC type must be 8-bit or 1-bit integer");
14321 SDValue Op0 = Op.getOperand(0);
14322 SDValue Op1 = Op.getOperand(1);
14324 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14326 // Optimize to BT if possible.
14327 // Lower (X & (1 << N)) == 0 to BT(X, N).
14328 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14329 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14330 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14331 Op1.getOpcode() == ISD::Constant &&
14332 cast<ConstantSDNode>(Op1)->isNullValue() &&
14333 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14334 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14335 if (NewSetCC.getNode())
14339 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14341 if (Op1.getOpcode() == ISD::Constant &&
14342 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14343 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14344 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14346 // If the input is a setcc, then reuse the input setcc or use a new one with
14347 // the inverted condition.
14348 if (Op0.getOpcode() == X86ISD::SETCC) {
14349 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14350 bool Invert = (CC == ISD::SETNE) ^
14351 cast<ConstantSDNode>(Op1)->isNullValue();
14355 CCode = X86::GetOppositeBranchCondition(CCode);
14356 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14357 DAG.getConstant(CCode, MVT::i8),
14358 Op0.getOperand(1));
14360 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14364 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14365 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14366 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14368 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14369 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14372 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14373 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14374 if (X86CC == X86::COND_INVALID)
14377 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14378 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14379 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14380 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14382 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14386 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14387 static bool isX86LogicalCmp(SDValue Op) {
14388 unsigned Opc = Op.getNode()->getOpcode();
14389 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14390 Opc == X86ISD::SAHF)
14392 if (Op.getResNo() == 1 &&
14393 (Opc == X86ISD::ADD ||
14394 Opc == X86ISD::SUB ||
14395 Opc == X86ISD::ADC ||
14396 Opc == X86ISD::SBB ||
14397 Opc == X86ISD::SMUL ||
14398 Opc == X86ISD::UMUL ||
14399 Opc == X86ISD::INC ||
14400 Opc == X86ISD::DEC ||
14401 Opc == X86ISD::OR ||
14402 Opc == X86ISD::XOR ||
14403 Opc == X86ISD::AND))
14406 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14412 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14413 if (V.getOpcode() != ISD::TRUNCATE)
14416 SDValue VOp0 = V.getOperand(0);
14417 unsigned InBits = VOp0.getValueSizeInBits();
14418 unsigned Bits = V.getValueSizeInBits();
14419 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14422 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14423 bool addTest = true;
14424 SDValue Cond = Op.getOperand(0);
14425 SDValue Op1 = Op.getOperand(1);
14426 SDValue Op2 = Op.getOperand(2);
14428 EVT VT = Op1.getValueType();
14431 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14432 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14433 // sequence later on.
14434 if (Cond.getOpcode() == ISD::SETCC &&
14435 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14436 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14437 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14438 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14439 int SSECC = translateX86FSETCC(
14440 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14443 if (Subtarget->hasAVX512()) {
14444 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14445 DAG.getConstant(SSECC, MVT::i8));
14446 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14448 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14449 DAG.getConstant(SSECC, MVT::i8));
14450 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14451 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14452 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14456 if (Cond.getOpcode() == ISD::SETCC) {
14457 SDValue NewCond = LowerSETCC(Cond, DAG);
14458 if (NewCond.getNode())
14462 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14463 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14464 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14465 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14466 if (Cond.getOpcode() == X86ISD::SETCC &&
14467 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14468 isZero(Cond.getOperand(1).getOperand(1))) {
14469 SDValue Cmp = Cond.getOperand(1);
14471 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14473 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14474 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14475 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14477 SDValue CmpOp0 = Cmp.getOperand(0);
14478 // Apply further optimizations for special cases
14479 // (select (x != 0), -1, 0) -> neg & sbb
14480 // (select (x == 0), 0, -1) -> neg & sbb
14481 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14482 if (YC->isNullValue() &&
14483 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14484 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14485 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14486 DAG.getConstant(0, CmpOp0.getValueType()),
14488 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14489 DAG.getConstant(X86::COND_B, MVT::i8),
14490 SDValue(Neg.getNode(), 1));
14494 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14495 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14496 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14498 SDValue Res = // Res = 0 or -1.
14499 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14500 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14502 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14503 Res = DAG.getNOT(DL, Res, Res.getValueType());
14505 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14506 if (!N2C || !N2C->isNullValue())
14507 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14512 // Look past (and (setcc_carry (cmp ...)), 1).
14513 if (Cond.getOpcode() == ISD::AND &&
14514 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14515 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14516 if (C && C->getAPIntValue() == 1)
14517 Cond = Cond.getOperand(0);
14520 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14521 // setting operand in place of the X86ISD::SETCC.
14522 unsigned CondOpcode = Cond.getOpcode();
14523 if (CondOpcode == X86ISD::SETCC ||
14524 CondOpcode == X86ISD::SETCC_CARRY) {
14525 CC = Cond.getOperand(0);
14527 SDValue Cmp = Cond.getOperand(1);
14528 unsigned Opc = Cmp.getOpcode();
14529 MVT VT = Op.getSimpleValueType();
14531 bool IllegalFPCMov = false;
14532 if (VT.isFloatingPoint() && !VT.isVector() &&
14533 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14534 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14536 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14537 Opc == X86ISD::BT) { // FIXME
14541 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14542 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14543 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14544 Cond.getOperand(0).getValueType() != MVT::i8)) {
14545 SDValue LHS = Cond.getOperand(0);
14546 SDValue RHS = Cond.getOperand(1);
14547 unsigned X86Opcode;
14550 switch (CondOpcode) {
14551 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14552 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14553 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14554 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14555 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14556 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14557 default: llvm_unreachable("unexpected overflowing operator");
14559 if (CondOpcode == ISD::UMULO)
14560 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14563 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14565 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14567 if (CondOpcode == ISD::UMULO)
14568 Cond = X86Op.getValue(2);
14570 Cond = X86Op.getValue(1);
14572 CC = DAG.getConstant(X86Cond, MVT::i8);
14577 // Look pass the truncate if the high bits are known zero.
14578 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14579 Cond = Cond.getOperand(0);
14581 // We know the result of AND is compared against zero. Try to match
14583 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14584 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14585 if (NewSetCC.getNode()) {
14586 CC = NewSetCC.getOperand(0);
14587 Cond = NewSetCC.getOperand(1);
14594 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14595 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14598 // a < b ? -1 : 0 -> RES = ~setcc_carry
14599 // a < b ? 0 : -1 -> RES = setcc_carry
14600 // a >= b ? -1 : 0 -> RES = setcc_carry
14601 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14602 if (Cond.getOpcode() == X86ISD::SUB) {
14603 Cond = ConvertCmpIfNecessary(Cond, DAG);
14604 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14606 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14607 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14608 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14609 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14610 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14611 return DAG.getNOT(DL, Res, Res.getValueType());
14616 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14617 // widen the cmov and push the truncate through. This avoids introducing a new
14618 // branch during isel and doesn't add any extensions.
14619 if (Op.getValueType() == MVT::i8 &&
14620 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14621 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14622 if (T1.getValueType() == T2.getValueType() &&
14623 // Blacklist CopyFromReg to avoid partial register stalls.
14624 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14625 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14626 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14627 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14631 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14632 // condition is true.
14633 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14634 SDValue Ops[] = { Op2, Op1, CC, Cond };
14635 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14638 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
14639 MVT VT = Op->getSimpleValueType(0);
14640 SDValue In = Op->getOperand(0);
14641 MVT InVT = In.getSimpleValueType();
14644 unsigned int NumElts = VT.getVectorNumElements();
14645 if (NumElts != 8 && NumElts != 16)
14648 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14649 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14651 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14652 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14654 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
14655 Constant *C = ConstantInt::get(*DAG.getContext(),
14656 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
14658 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14659 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14660 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
14661 MachinePointerInfo::getConstantPool(),
14662 false, false, false, Alignment);
14663 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
14664 if (VT.is512BitVector())
14666 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
14669 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14670 SelectionDAG &DAG) {
14671 MVT VT = Op->getSimpleValueType(0);
14672 SDValue In = Op->getOperand(0);
14673 MVT InVT = In.getSimpleValueType();
14676 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14677 return LowerSIGN_EXTEND_AVX512(Op, DAG);
14679 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14680 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14681 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14684 if (Subtarget->hasInt256())
14685 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14687 // Optimize vectors in AVX mode
14688 // Sign extend v8i16 to v8i32 and
14691 // Divide input vector into two parts
14692 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14693 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14694 // concat the vectors to original VT
14696 unsigned NumElems = InVT.getVectorNumElements();
14697 SDValue Undef = DAG.getUNDEF(InVT);
14699 SmallVector<int,8> ShufMask1(NumElems, -1);
14700 for (unsigned i = 0; i != NumElems/2; ++i)
14703 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14705 SmallVector<int,8> ShufMask2(NumElems, -1);
14706 for (unsigned i = 0; i != NumElems/2; ++i)
14707 ShufMask2[i] = i + NumElems/2;
14709 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14711 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14712 VT.getVectorNumElements()/2);
14714 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14715 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14717 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14720 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14721 // may emit an illegal shuffle but the expansion is still better than scalar
14722 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14723 // we'll emit a shuffle and a arithmetic shift.
14724 // TODO: It is possible to support ZExt by zeroing the undef values during
14725 // the shuffle phase or after the shuffle.
14726 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14727 SelectionDAG &DAG) {
14728 MVT RegVT = Op.getSimpleValueType();
14729 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14730 assert(RegVT.isInteger() &&
14731 "We only custom lower integer vector sext loads.");
14733 // Nothing useful we can do without SSE2 shuffles.
14734 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14736 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14738 EVT MemVT = Ld->getMemoryVT();
14739 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14740 unsigned RegSz = RegVT.getSizeInBits();
14742 ISD::LoadExtType Ext = Ld->getExtensionType();
14744 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14745 && "Only anyext and sext are currently implemented.");
14746 assert(MemVT != RegVT && "Cannot extend to the same type");
14747 assert(MemVT.isVector() && "Must load a vector from memory");
14749 unsigned NumElems = RegVT.getVectorNumElements();
14750 unsigned MemSz = MemVT.getSizeInBits();
14751 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14753 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14754 // The only way in which we have a legal 256-bit vector result but not the
14755 // integer 256-bit operations needed to directly lower a sextload is if we
14756 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14757 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14758 // correctly legalized. We do this late to allow the canonical form of
14759 // sextload to persist throughout the rest of the DAG combiner -- it wants
14760 // to fold together any extensions it can, and so will fuse a sign_extend
14761 // of an sextload into a sextload targeting a wider value.
14763 if (MemSz == 128) {
14764 // Just switch this to a normal load.
14765 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14766 "it must be a legal 128-bit vector "
14768 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14769 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14770 Ld->isInvariant(), Ld->getAlignment());
14772 assert(MemSz < 128 &&
14773 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14774 // Do an sext load to a 128-bit vector type. We want to use the same
14775 // number of elements, but elements half as wide. This will end up being
14776 // recursively lowered by this routine, but will succeed as we definitely
14777 // have all the necessary features if we're using AVX1.
14779 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14780 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14782 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14783 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14784 Ld->isNonTemporal(), Ld->isInvariant(),
14785 Ld->getAlignment());
14788 // Replace chain users with the new chain.
14789 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14790 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14792 // Finally, do a normal sign-extend to the desired register.
14793 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14796 // All sizes must be a power of two.
14797 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14798 "Non-power-of-two elements are not custom lowered!");
14800 // Attempt to load the original value using scalar loads.
14801 // Find the largest scalar type that divides the total loaded size.
14802 MVT SclrLoadTy = MVT::i8;
14803 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14804 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14805 MVT Tp = (MVT::SimpleValueType)tp;
14806 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14811 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14812 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14814 SclrLoadTy = MVT::f64;
14816 // Calculate the number of scalar loads that we need to perform
14817 // in order to load our vector from memory.
14818 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14820 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14821 "Can only lower sext loads with a single scalar load!");
14823 unsigned loadRegZize = RegSz;
14824 if (Ext == ISD::SEXTLOAD && RegSz == 256)
14827 // Represent our vector as a sequence of elements which are the
14828 // largest scalar that we can load.
14829 EVT LoadUnitVecVT = EVT::getVectorVT(
14830 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14832 // Represent the data using the same element type that is stored in
14833 // memory. In practice, we ''widen'' MemVT.
14835 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14836 loadRegZize / MemVT.getScalarType().getSizeInBits());
14838 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14839 "Invalid vector type");
14841 // We can't shuffle using an illegal type.
14842 assert(TLI.isTypeLegal(WideVecVT) &&
14843 "We only lower types that form legal widened vector types");
14845 SmallVector<SDValue, 8> Chains;
14846 SDValue Ptr = Ld->getBasePtr();
14847 SDValue Increment =
14848 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
14849 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14851 for (unsigned i = 0; i < NumLoads; ++i) {
14852 // Perform a single load.
14853 SDValue ScalarLoad =
14854 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14855 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14856 Ld->getAlignment());
14857 Chains.push_back(ScalarLoad.getValue(1));
14858 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14859 // another round of DAGCombining.
14861 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14863 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14864 ScalarLoad, DAG.getIntPtrConstant(i));
14866 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14869 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14871 // Bitcast the loaded value to a vector of the original element type, in
14872 // the size of the target vector type.
14873 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14874 unsigned SizeRatio = RegSz / MemSz;
14876 if (Ext == ISD::SEXTLOAD) {
14877 // If we have SSE4.1, we can directly emit a VSEXT node.
14878 if (Subtarget->hasSSE41()) {
14879 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14880 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14884 // Otherwise we'll shuffle the small elements in the high bits of the
14885 // larger type and perform an arithmetic shift. If the shift is not legal
14886 // it's better to scalarize.
14887 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14888 "We can't implement a sext load without an arithmetic right shift!");
14890 // Redistribute the loaded elements into the different locations.
14891 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14892 for (unsigned i = 0; i != NumElems; ++i)
14893 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14895 SDValue Shuff = DAG.getVectorShuffle(
14896 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14898 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14900 // Build the arithmetic shift.
14901 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14902 MemVT.getVectorElementType().getSizeInBits();
14904 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
14906 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14910 // Redistribute the loaded elements into the different locations.
14911 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14912 for (unsigned i = 0; i != NumElems; ++i)
14913 ShuffleVec[i * SizeRatio] = i;
14915 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14916 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14918 // Bitcast to the requested type.
14919 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14920 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14924 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14925 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14926 // from the AND / OR.
14927 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14928 Opc = Op.getOpcode();
14929 if (Opc != ISD::OR && Opc != ISD::AND)
14931 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14932 Op.getOperand(0).hasOneUse() &&
14933 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14934 Op.getOperand(1).hasOneUse());
14937 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14938 // 1 and that the SETCC node has a single use.
14939 static bool isXor1OfSetCC(SDValue Op) {
14940 if (Op.getOpcode() != ISD::XOR)
14942 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14943 if (N1C && N1C->getAPIntValue() == 1) {
14944 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14945 Op.getOperand(0).hasOneUse();
14950 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14951 bool addTest = true;
14952 SDValue Chain = Op.getOperand(0);
14953 SDValue Cond = Op.getOperand(1);
14954 SDValue Dest = Op.getOperand(2);
14957 bool Inverted = false;
14959 if (Cond.getOpcode() == ISD::SETCC) {
14960 // Check for setcc([su]{add,sub,mul}o == 0).
14961 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14962 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14963 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14964 Cond.getOperand(0).getResNo() == 1 &&
14965 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14966 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14967 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14968 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14969 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14970 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14972 Cond = Cond.getOperand(0);
14974 SDValue NewCond = LowerSETCC(Cond, DAG);
14975 if (NewCond.getNode())
14980 // FIXME: LowerXALUO doesn't handle these!!
14981 else if (Cond.getOpcode() == X86ISD::ADD ||
14982 Cond.getOpcode() == X86ISD::SUB ||
14983 Cond.getOpcode() == X86ISD::SMUL ||
14984 Cond.getOpcode() == X86ISD::UMUL)
14985 Cond = LowerXALUO(Cond, DAG);
14988 // Look pass (and (setcc_carry (cmp ...)), 1).
14989 if (Cond.getOpcode() == ISD::AND &&
14990 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14991 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14992 if (C && C->getAPIntValue() == 1)
14993 Cond = Cond.getOperand(0);
14996 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14997 // setting operand in place of the X86ISD::SETCC.
14998 unsigned CondOpcode = Cond.getOpcode();
14999 if (CondOpcode == X86ISD::SETCC ||
15000 CondOpcode == X86ISD::SETCC_CARRY) {
15001 CC = Cond.getOperand(0);
15003 SDValue Cmp = Cond.getOperand(1);
15004 unsigned Opc = Cmp.getOpcode();
15005 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15006 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15010 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15014 // These can only come from an arithmetic instruction with overflow,
15015 // e.g. SADDO, UADDO.
15016 Cond = Cond.getNode()->getOperand(1);
15022 CondOpcode = Cond.getOpcode();
15023 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15024 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15025 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15026 Cond.getOperand(0).getValueType() != MVT::i8)) {
15027 SDValue LHS = Cond.getOperand(0);
15028 SDValue RHS = Cond.getOperand(1);
15029 unsigned X86Opcode;
15032 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15033 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15035 switch (CondOpcode) {
15036 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15038 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15040 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15043 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15044 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15046 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15048 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15051 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15052 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15053 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15054 default: llvm_unreachable("unexpected overflowing operator");
15057 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15058 if (CondOpcode == ISD::UMULO)
15059 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15062 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15064 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15066 if (CondOpcode == ISD::UMULO)
15067 Cond = X86Op.getValue(2);
15069 Cond = X86Op.getValue(1);
15071 CC = DAG.getConstant(X86Cond, MVT::i8);
15075 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15076 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15077 if (CondOpc == ISD::OR) {
15078 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15079 // two branches instead of an explicit OR instruction with a
15081 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15082 isX86LogicalCmp(Cmp)) {
15083 CC = Cond.getOperand(0).getOperand(0);
15084 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15085 Chain, Dest, CC, Cmp);
15086 CC = Cond.getOperand(1).getOperand(0);
15090 } else { // ISD::AND
15091 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15092 // two branches instead of an explicit AND instruction with a
15093 // separate test. However, we only do this if this block doesn't
15094 // have a fall-through edge, because this requires an explicit
15095 // jmp when the condition is false.
15096 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15097 isX86LogicalCmp(Cmp) &&
15098 Op.getNode()->hasOneUse()) {
15099 X86::CondCode CCode =
15100 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15101 CCode = X86::GetOppositeBranchCondition(CCode);
15102 CC = DAG.getConstant(CCode, MVT::i8);
15103 SDNode *User = *Op.getNode()->use_begin();
15104 // Look for an unconditional branch following this conditional branch.
15105 // We need this because we need to reverse the successors in order
15106 // to implement FCMP_OEQ.
15107 if (User->getOpcode() == ISD::BR) {
15108 SDValue FalseBB = User->getOperand(1);
15110 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15111 assert(NewBR == User);
15115 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15116 Chain, Dest, CC, Cmp);
15117 X86::CondCode CCode =
15118 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15119 CCode = X86::GetOppositeBranchCondition(CCode);
15120 CC = DAG.getConstant(CCode, MVT::i8);
15126 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15127 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15128 // It should be transformed during dag combiner except when the condition
15129 // is set by a arithmetics with overflow node.
15130 X86::CondCode CCode =
15131 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15132 CCode = X86::GetOppositeBranchCondition(CCode);
15133 CC = DAG.getConstant(CCode, MVT::i8);
15134 Cond = Cond.getOperand(0).getOperand(1);
15136 } else if (Cond.getOpcode() == ISD::SETCC &&
15137 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15138 // For FCMP_OEQ, we can emit
15139 // two branches instead of an explicit AND instruction with a
15140 // separate test. However, we only do this if this block doesn't
15141 // have a fall-through edge, because this requires an explicit
15142 // jmp when the condition is false.
15143 if (Op.getNode()->hasOneUse()) {
15144 SDNode *User = *Op.getNode()->use_begin();
15145 // Look for an unconditional branch following this conditional branch.
15146 // We need this because we need to reverse the successors in order
15147 // to implement FCMP_OEQ.
15148 if (User->getOpcode() == ISD::BR) {
15149 SDValue FalseBB = User->getOperand(1);
15151 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15152 assert(NewBR == User);
15156 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15157 Cond.getOperand(0), Cond.getOperand(1));
15158 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15159 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15160 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15161 Chain, Dest, CC, Cmp);
15162 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15167 } else if (Cond.getOpcode() == ISD::SETCC &&
15168 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15169 // For FCMP_UNE, we can emit
15170 // two branches instead of an explicit AND instruction with a
15171 // separate test. However, we only do this if this block doesn't
15172 // have a fall-through edge, because this requires an explicit
15173 // jmp when the condition is false.
15174 if (Op.getNode()->hasOneUse()) {
15175 SDNode *User = *Op.getNode()->use_begin();
15176 // Look for an unconditional branch following this conditional branch.
15177 // We need this because we need to reverse the successors in order
15178 // to implement FCMP_UNE.
15179 if (User->getOpcode() == ISD::BR) {
15180 SDValue FalseBB = User->getOperand(1);
15182 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15183 assert(NewBR == User);
15186 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15187 Cond.getOperand(0), Cond.getOperand(1));
15188 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15189 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15190 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15191 Chain, Dest, CC, Cmp);
15192 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
15202 // Look pass the truncate if the high bits are known zero.
15203 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15204 Cond = Cond.getOperand(0);
15206 // We know the result of AND is compared against zero. Try to match
15208 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15209 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15210 if (NewSetCC.getNode()) {
15211 CC = NewSetCC.getOperand(0);
15212 Cond = NewSetCC.getOperand(1);
15219 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15220 CC = DAG.getConstant(X86Cond, MVT::i8);
15221 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15223 Cond = ConvertCmpIfNecessary(Cond, DAG);
15224 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15225 Chain, Dest, CC, Cond);
15228 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15229 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15230 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15231 // that the guard pages used by the OS virtual memory manager are allocated in
15232 // correct sequence.
15234 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15235 SelectionDAG &DAG) const {
15236 MachineFunction &MF = DAG.getMachineFunction();
15237 bool SplitStack = MF.shouldSplitStack();
15238 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15244 SDNode* Node = Op.getNode();
15246 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15247 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15248 " not tell us which reg is the stack pointer!");
15249 EVT VT = Node->getValueType(0);
15250 SDValue Tmp1 = SDValue(Node, 0);
15251 SDValue Tmp2 = SDValue(Node, 1);
15252 SDValue Tmp3 = Node->getOperand(2);
15253 SDValue Chain = Tmp1.getOperand(0);
15255 // Chain the dynamic stack allocation so that it doesn't modify the stack
15256 // pointer when other instructions are using the stack.
15257 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15260 SDValue Size = Tmp2.getOperand(1);
15261 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15262 Chain = SP.getValue(1);
15263 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15264 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15265 unsigned StackAlign = TFI.getStackAlignment();
15266 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15267 if (Align > StackAlign)
15268 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15269 DAG.getConstant(-(uint64_t)Align, VT));
15270 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15272 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15273 DAG.getIntPtrConstant(0, true), SDValue(),
15276 SDValue Ops[2] = { Tmp1, Tmp2 };
15277 return DAG.getMergeValues(Ops, dl);
15281 SDValue Chain = Op.getOperand(0);
15282 SDValue Size = Op.getOperand(1);
15283 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15284 EVT VT = Op.getNode()->getValueType(0);
15286 bool Is64Bit = Subtarget->is64Bit();
15287 EVT SPTy = getPointerTy();
15290 MachineRegisterInfo &MRI = MF.getRegInfo();
15293 // The 64 bit implementation of segmented stacks needs to clobber both r10
15294 // r11. This makes it impossible to use it along with nested parameters.
15295 const Function *F = MF.getFunction();
15297 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15299 if (I->hasNestAttr())
15300 report_fatal_error("Cannot use segmented stacks with functions that "
15301 "have nested arguments.");
15304 const TargetRegisterClass *AddrRegClass =
15305 getRegClassFor(getPointerTy());
15306 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15307 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15308 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15309 DAG.getRegister(Vreg, SPTy));
15310 SDValue Ops1[2] = { Value, Chain };
15311 return DAG.getMergeValues(Ops1, dl);
15314 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15316 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15317 Flag = Chain.getValue(1);
15318 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15320 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15322 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15323 DAG.getSubtarget().getRegisterInfo());
15324 unsigned SPReg = RegInfo->getStackRegister();
15325 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15326 Chain = SP.getValue(1);
15329 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15330 DAG.getConstant(-(uint64_t)Align, VT));
15331 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15334 SDValue Ops1[2] = { SP, Chain };
15335 return DAG.getMergeValues(Ops1, dl);
15339 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15340 MachineFunction &MF = DAG.getMachineFunction();
15341 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15343 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15346 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15347 // vastart just stores the address of the VarArgsFrameIndex slot into the
15348 // memory location argument.
15349 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15351 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15352 MachinePointerInfo(SV), false, false, 0);
15356 // gp_offset (0 - 6 * 8)
15357 // fp_offset (48 - 48 + 8 * 16)
15358 // overflow_arg_area (point to parameters coming in memory).
15360 SmallVector<SDValue, 8> MemOps;
15361 SDValue FIN = Op.getOperand(1);
15363 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15364 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15366 FIN, MachinePointerInfo(SV), false, false, 0);
15367 MemOps.push_back(Store);
15370 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15371 FIN, DAG.getIntPtrConstant(4));
15372 Store = DAG.getStore(Op.getOperand(0), DL,
15373 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15375 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15376 MemOps.push_back(Store);
15378 // Store ptr to overflow_arg_area
15379 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15380 FIN, DAG.getIntPtrConstant(4));
15381 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15383 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15384 MachinePointerInfo(SV, 8),
15386 MemOps.push_back(Store);
15388 // Store ptr to reg_save_area.
15389 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15390 FIN, DAG.getIntPtrConstant(8));
15391 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15393 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15394 MachinePointerInfo(SV, 16), false, false, 0);
15395 MemOps.push_back(Store);
15396 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15399 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15400 assert(Subtarget->is64Bit() &&
15401 "LowerVAARG only handles 64-bit va_arg!");
15402 assert((Subtarget->isTargetLinux() ||
15403 Subtarget->isTargetDarwin()) &&
15404 "Unhandled target in LowerVAARG");
15405 assert(Op.getNode()->getNumOperands() == 4);
15406 SDValue Chain = Op.getOperand(0);
15407 SDValue SrcPtr = Op.getOperand(1);
15408 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15409 unsigned Align = Op.getConstantOperandVal(3);
15412 EVT ArgVT = Op.getNode()->getValueType(0);
15413 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15414 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15417 // Decide which area this value should be read from.
15418 // TODO: Implement the AMD64 ABI in its entirety. This simple
15419 // selection mechanism works only for the basic types.
15420 if (ArgVT == MVT::f80) {
15421 llvm_unreachable("va_arg for f80 not yet implemented");
15422 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15423 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15424 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15425 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15427 llvm_unreachable("Unhandled argument type in LowerVAARG");
15430 if (ArgMode == 2) {
15431 // Sanity Check: Make sure using fp_offset makes sense.
15432 assert(!DAG.getTarget().Options.UseSoftFloat &&
15433 !(DAG.getMachineFunction()
15434 .getFunction()->getAttributes()
15435 .hasAttribute(AttributeSet::FunctionIndex,
15436 Attribute::NoImplicitFloat)) &&
15437 Subtarget->hasSSE1());
15440 // Insert VAARG_64 node into the DAG
15441 // VAARG_64 returns two values: Variable Argument Address, Chain
15442 SmallVector<SDValue, 11> InstOps;
15443 InstOps.push_back(Chain);
15444 InstOps.push_back(SrcPtr);
15445 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15446 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15447 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15448 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15449 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15450 VTs, InstOps, MVT::i64,
15451 MachinePointerInfo(SV),
15453 /*Volatile=*/false,
15455 /*WriteMem=*/true);
15456 Chain = VAARG.getValue(1);
15458 // Load the next argument and return it
15459 return DAG.getLoad(ArgVT, dl,
15462 MachinePointerInfo(),
15463 false, false, false, 0);
15466 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15467 SelectionDAG &DAG) {
15468 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15469 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15470 SDValue Chain = Op.getOperand(0);
15471 SDValue DstPtr = Op.getOperand(1);
15472 SDValue SrcPtr = Op.getOperand(2);
15473 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15474 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15477 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15478 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15480 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15483 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15484 // amount is a constant. Takes immediate version of shift as input.
15485 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15486 SDValue SrcOp, uint64_t ShiftAmt,
15487 SelectionDAG &DAG) {
15488 MVT ElementType = VT.getVectorElementType();
15490 // Fold this packed shift into its first operand if ShiftAmt is 0.
15494 // Check for ShiftAmt >= element width
15495 if (ShiftAmt >= ElementType.getSizeInBits()) {
15496 if (Opc == X86ISD::VSRAI)
15497 ShiftAmt = ElementType.getSizeInBits() - 1;
15499 return DAG.getConstant(0, VT);
15502 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15503 && "Unknown target vector shift-by-constant node");
15505 // Fold this packed vector shift into a build vector if SrcOp is a
15506 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15507 if (VT == SrcOp.getSimpleValueType() &&
15508 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15509 SmallVector<SDValue, 8> Elts;
15510 unsigned NumElts = SrcOp->getNumOperands();
15511 ConstantSDNode *ND;
15514 default: llvm_unreachable(nullptr);
15515 case X86ISD::VSHLI:
15516 for (unsigned i=0; i!=NumElts; ++i) {
15517 SDValue CurrentOp = SrcOp->getOperand(i);
15518 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15519 Elts.push_back(CurrentOp);
15522 ND = cast<ConstantSDNode>(CurrentOp);
15523 const APInt &C = ND->getAPIntValue();
15524 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15527 case X86ISD::VSRLI:
15528 for (unsigned i=0; i!=NumElts; ++i) {
15529 SDValue CurrentOp = SrcOp->getOperand(i);
15530 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15531 Elts.push_back(CurrentOp);
15534 ND = cast<ConstantSDNode>(CurrentOp);
15535 const APInt &C = ND->getAPIntValue();
15536 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15539 case X86ISD::VSRAI:
15540 for (unsigned i=0; i!=NumElts; ++i) {
15541 SDValue CurrentOp = SrcOp->getOperand(i);
15542 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15543 Elts.push_back(CurrentOp);
15546 ND = cast<ConstantSDNode>(CurrentOp);
15547 const APInt &C = ND->getAPIntValue();
15548 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15553 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15556 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15559 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15560 // may or may not be a constant. Takes immediate version of shift as input.
15561 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15562 SDValue SrcOp, SDValue ShAmt,
15563 SelectionDAG &DAG) {
15564 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15566 // Catch shift-by-constant.
15567 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15568 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15569 CShAmt->getZExtValue(), DAG);
15571 // Change opcode to non-immediate version
15573 default: llvm_unreachable("Unknown target vector shift node");
15574 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15575 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15576 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15579 // Need to build a vector containing shift amount
15580 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15583 ShOps[1] = DAG.getConstant(0, MVT::i32);
15584 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15585 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15587 // The return type has to be a 128-bit type with the same element
15588 // type as the input type.
15589 MVT EltVT = VT.getVectorElementType();
15590 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15592 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15593 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15596 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
15597 /// necessary casting for \p Mask when lowering masking intrinsics.
15598 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15599 SDValue PreservedSrc, SelectionDAG &DAG) {
15600 EVT VT = Op.getValueType();
15601 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15602 MVT::i1, VT.getVectorNumElements());
15605 assert(MaskVT.isSimple() && "invalid mask type");
15606 return DAG.getNode(ISD::VSELECT, dl, VT,
15607 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
15611 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
15613 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15614 case Intrinsic::x86_fma_vfmadd_ps:
15615 case Intrinsic::x86_fma_vfmadd_pd:
15616 case Intrinsic::x86_fma_vfmadd_ps_256:
15617 case Intrinsic::x86_fma_vfmadd_pd_256:
15618 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15619 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15620 return X86ISD::FMADD;
15621 case Intrinsic::x86_fma_vfmsub_ps:
15622 case Intrinsic::x86_fma_vfmsub_pd:
15623 case Intrinsic::x86_fma_vfmsub_ps_256:
15624 case Intrinsic::x86_fma_vfmsub_pd_256:
15625 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15626 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15627 return X86ISD::FMSUB;
15628 case Intrinsic::x86_fma_vfnmadd_ps:
15629 case Intrinsic::x86_fma_vfnmadd_pd:
15630 case Intrinsic::x86_fma_vfnmadd_ps_256:
15631 case Intrinsic::x86_fma_vfnmadd_pd_256:
15632 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15633 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15634 return X86ISD::FNMADD;
15635 case Intrinsic::x86_fma_vfnmsub_ps:
15636 case Intrinsic::x86_fma_vfnmsub_pd:
15637 case Intrinsic::x86_fma_vfnmsub_ps_256:
15638 case Intrinsic::x86_fma_vfnmsub_pd_256:
15639 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15640 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15641 return X86ISD::FNMSUB;
15642 case Intrinsic::x86_fma_vfmaddsub_ps:
15643 case Intrinsic::x86_fma_vfmaddsub_pd:
15644 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15645 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15646 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15647 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15648 return X86ISD::FMADDSUB;
15649 case Intrinsic::x86_fma_vfmsubadd_ps:
15650 case Intrinsic::x86_fma_vfmsubadd_pd:
15651 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15652 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15653 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15654 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
15655 return X86ISD::FMSUBADD;
15659 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
15661 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15663 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15665 switch(IntrData->Type) {
15666 case INTR_TYPE_1OP:
15667 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15668 case INTR_TYPE_2OP:
15669 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15671 case INTR_TYPE_3OP:
15672 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15673 Op.getOperand(2), Op.getOperand(3));
15674 case COMI: { // Comparison intrinsics
15675 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15676 SDValue LHS = Op.getOperand(1);
15677 SDValue RHS = Op.getOperand(2);
15678 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
15679 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15680 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15681 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15682 DAG.getConstant(X86CC, MVT::i8), Cond);
15683 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15686 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15687 Op.getOperand(1), Op.getOperand(2), DAG);
15694 default: return SDValue(); // Don't custom lower most intrinsics.
15696 // Arithmetic intrinsics.
15697 case Intrinsic::x86_sse2_pmulu_dq:
15698 case Intrinsic::x86_avx2_pmulu_dq:
15699 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
15700 Op.getOperand(1), Op.getOperand(2));
15702 case Intrinsic::x86_sse41_pmuldq:
15703 case Intrinsic::x86_avx2_pmul_dq:
15704 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
15705 Op.getOperand(1), Op.getOperand(2));
15707 case Intrinsic::x86_sse2_pmulhu_w:
15708 case Intrinsic::x86_avx2_pmulhu_w:
15709 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
15710 Op.getOperand(1), Op.getOperand(2));
15712 case Intrinsic::x86_sse2_pmulh_w:
15713 case Intrinsic::x86_avx2_pmulh_w:
15714 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
15715 Op.getOperand(1), Op.getOperand(2));
15717 // SSE/SSE2/AVX floating point max/min intrinsics.
15718 case Intrinsic::x86_sse_max_ps:
15719 case Intrinsic::x86_sse2_max_pd:
15720 case Intrinsic::x86_avx_max_ps_256:
15721 case Intrinsic::x86_avx_max_pd_256:
15722 case Intrinsic::x86_sse_min_ps:
15723 case Intrinsic::x86_sse2_min_pd:
15724 case Intrinsic::x86_avx_min_ps_256:
15725 case Intrinsic::x86_avx_min_pd_256: {
15728 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15729 case Intrinsic::x86_sse_max_ps:
15730 case Intrinsic::x86_sse2_max_pd:
15731 case Intrinsic::x86_avx_max_ps_256:
15732 case Intrinsic::x86_avx_max_pd_256:
15733 Opcode = X86ISD::FMAX;
15735 case Intrinsic::x86_sse_min_ps:
15736 case Intrinsic::x86_sse2_min_pd:
15737 case Intrinsic::x86_avx_min_ps_256:
15738 case Intrinsic::x86_avx_min_pd_256:
15739 Opcode = X86ISD::FMIN;
15742 return DAG.getNode(Opcode, dl, Op.getValueType(),
15743 Op.getOperand(1), Op.getOperand(2));
15746 // AVX2 variable shift intrinsics
15747 case Intrinsic::x86_avx2_psllv_d:
15748 case Intrinsic::x86_avx2_psllv_q:
15749 case Intrinsic::x86_avx2_psllv_d_256:
15750 case Intrinsic::x86_avx2_psllv_q_256:
15751 case Intrinsic::x86_avx2_psrlv_d:
15752 case Intrinsic::x86_avx2_psrlv_q:
15753 case Intrinsic::x86_avx2_psrlv_d_256:
15754 case Intrinsic::x86_avx2_psrlv_q_256:
15755 case Intrinsic::x86_avx2_psrav_d:
15756 case Intrinsic::x86_avx2_psrav_d_256: {
15759 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15760 case Intrinsic::x86_avx2_psllv_d:
15761 case Intrinsic::x86_avx2_psllv_q:
15762 case Intrinsic::x86_avx2_psllv_d_256:
15763 case Intrinsic::x86_avx2_psllv_q_256:
15766 case Intrinsic::x86_avx2_psrlv_d:
15767 case Intrinsic::x86_avx2_psrlv_q:
15768 case Intrinsic::x86_avx2_psrlv_d_256:
15769 case Intrinsic::x86_avx2_psrlv_q_256:
15772 case Intrinsic::x86_avx2_psrav_d:
15773 case Intrinsic::x86_avx2_psrav_d_256:
15777 return DAG.getNode(Opcode, dl, Op.getValueType(),
15778 Op.getOperand(1), Op.getOperand(2));
15781 case Intrinsic::x86_sse2_packssdw_128:
15782 case Intrinsic::x86_sse2_packsswb_128:
15783 case Intrinsic::x86_avx2_packssdw:
15784 case Intrinsic::x86_avx2_packsswb:
15785 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
15786 Op.getOperand(1), Op.getOperand(2));
15788 case Intrinsic::x86_sse2_packuswb_128:
15789 case Intrinsic::x86_sse41_packusdw:
15790 case Intrinsic::x86_avx2_packuswb:
15791 case Intrinsic::x86_avx2_packusdw:
15792 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
15793 Op.getOperand(1), Op.getOperand(2));
15795 case Intrinsic::x86_ssse3_pshuf_b_128:
15796 case Intrinsic::x86_avx2_pshuf_b:
15797 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
15798 Op.getOperand(1), Op.getOperand(2));
15800 case Intrinsic::x86_sse2_pshuf_d:
15801 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
15802 Op.getOperand(1), Op.getOperand(2));
15804 case Intrinsic::x86_sse2_pshufl_w:
15805 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
15806 Op.getOperand(1), Op.getOperand(2));
15808 case Intrinsic::x86_sse2_pshufh_w:
15809 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
15810 Op.getOperand(1), Op.getOperand(2));
15812 case Intrinsic::x86_ssse3_psign_b_128:
15813 case Intrinsic::x86_ssse3_psign_w_128:
15814 case Intrinsic::x86_ssse3_psign_d_128:
15815 case Intrinsic::x86_avx2_psign_b:
15816 case Intrinsic::x86_avx2_psign_w:
15817 case Intrinsic::x86_avx2_psign_d:
15818 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
15819 Op.getOperand(1), Op.getOperand(2));
15821 case Intrinsic::x86_avx2_permd:
15822 case Intrinsic::x86_avx2_permps:
15823 // Operands intentionally swapped. Mask is last operand to intrinsic,
15824 // but second operand for node/instruction.
15825 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15826 Op.getOperand(2), Op.getOperand(1));
15828 case Intrinsic::x86_avx512_mask_valign_q_512:
15829 case Intrinsic::x86_avx512_mask_valign_d_512:
15830 // Vector source operands are swapped.
15831 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15832 Op.getValueType(), Op.getOperand(2),
15835 Op.getOperand(5), Op.getOperand(4), DAG);
15837 // ptest and testp intrinsics. The intrinsic these come from are designed to
15838 // return an integer value, not just an instruction so lower it to the ptest
15839 // or testp pattern and a setcc for the result.
15840 case Intrinsic::x86_sse41_ptestz:
15841 case Intrinsic::x86_sse41_ptestc:
15842 case Intrinsic::x86_sse41_ptestnzc:
15843 case Intrinsic::x86_avx_ptestz_256:
15844 case Intrinsic::x86_avx_ptestc_256:
15845 case Intrinsic::x86_avx_ptestnzc_256:
15846 case Intrinsic::x86_avx_vtestz_ps:
15847 case Intrinsic::x86_avx_vtestc_ps:
15848 case Intrinsic::x86_avx_vtestnzc_ps:
15849 case Intrinsic::x86_avx_vtestz_pd:
15850 case Intrinsic::x86_avx_vtestc_pd:
15851 case Intrinsic::x86_avx_vtestnzc_pd:
15852 case Intrinsic::x86_avx_vtestz_ps_256:
15853 case Intrinsic::x86_avx_vtestc_ps_256:
15854 case Intrinsic::x86_avx_vtestnzc_ps_256:
15855 case Intrinsic::x86_avx_vtestz_pd_256:
15856 case Intrinsic::x86_avx_vtestc_pd_256:
15857 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15858 bool IsTestPacked = false;
15861 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15862 case Intrinsic::x86_avx_vtestz_ps:
15863 case Intrinsic::x86_avx_vtestz_pd:
15864 case Intrinsic::x86_avx_vtestz_ps_256:
15865 case Intrinsic::x86_avx_vtestz_pd_256:
15866 IsTestPacked = true; // Fallthrough
15867 case Intrinsic::x86_sse41_ptestz:
15868 case Intrinsic::x86_avx_ptestz_256:
15870 X86CC = X86::COND_E;
15872 case Intrinsic::x86_avx_vtestc_ps:
15873 case Intrinsic::x86_avx_vtestc_pd:
15874 case Intrinsic::x86_avx_vtestc_ps_256:
15875 case Intrinsic::x86_avx_vtestc_pd_256:
15876 IsTestPacked = true; // Fallthrough
15877 case Intrinsic::x86_sse41_ptestc:
15878 case Intrinsic::x86_avx_ptestc_256:
15880 X86CC = X86::COND_B;
15882 case Intrinsic::x86_avx_vtestnzc_ps:
15883 case Intrinsic::x86_avx_vtestnzc_pd:
15884 case Intrinsic::x86_avx_vtestnzc_ps_256:
15885 case Intrinsic::x86_avx_vtestnzc_pd_256:
15886 IsTestPacked = true; // Fallthrough
15887 case Intrinsic::x86_sse41_ptestnzc:
15888 case Intrinsic::x86_avx_ptestnzc_256:
15890 X86CC = X86::COND_A;
15894 SDValue LHS = Op.getOperand(1);
15895 SDValue RHS = Op.getOperand(2);
15896 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15897 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15898 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15899 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15900 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15902 case Intrinsic::x86_avx512_kortestz_w:
15903 case Intrinsic::x86_avx512_kortestc_w: {
15904 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15905 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15906 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15907 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15908 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15909 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15910 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15913 case Intrinsic::x86_sse42_pcmpistria128:
15914 case Intrinsic::x86_sse42_pcmpestria128:
15915 case Intrinsic::x86_sse42_pcmpistric128:
15916 case Intrinsic::x86_sse42_pcmpestric128:
15917 case Intrinsic::x86_sse42_pcmpistrio128:
15918 case Intrinsic::x86_sse42_pcmpestrio128:
15919 case Intrinsic::x86_sse42_pcmpistris128:
15920 case Intrinsic::x86_sse42_pcmpestris128:
15921 case Intrinsic::x86_sse42_pcmpistriz128:
15922 case Intrinsic::x86_sse42_pcmpestriz128: {
15926 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15927 case Intrinsic::x86_sse42_pcmpistria128:
15928 Opcode = X86ISD::PCMPISTRI;
15929 X86CC = X86::COND_A;
15931 case Intrinsic::x86_sse42_pcmpestria128:
15932 Opcode = X86ISD::PCMPESTRI;
15933 X86CC = X86::COND_A;
15935 case Intrinsic::x86_sse42_pcmpistric128:
15936 Opcode = X86ISD::PCMPISTRI;
15937 X86CC = X86::COND_B;
15939 case Intrinsic::x86_sse42_pcmpestric128:
15940 Opcode = X86ISD::PCMPESTRI;
15941 X86CC = X86::COND_B;
15943 case Intrinsic::x86_sse42_pcmpistrio128:
15944 Opcode = X86ISD::PCMPISTRI;
15945 X86CC = X86::COND_O;
15947 case Intrinsic::x86_sse42_pcmpestrio128:
15948 Opcode = X86ISD::PCMPESTRI;
15949 X86CC = X86::COND_O;
15951 case Intrinsic::x86_sse42_pcmpistris128:
15952 Opcode = X86ISD::PCMPISTRI;
15953 X86CC = X86::COND_S;
15955 case Intrinsic::x86_sse42_pcmpestris128:
15956 Opcode = X86ISD::PCMPESTRI;
15957 X86CC = X86::COND_S;
15959 case Intrinsic::x86_sse42_pcmpistriz128:
15960 Opcode = X86ISD::PCMPISTRI;
15961 X86CC = X86::COND_E;
15963 case Intrinsic::x86_sse42_pcmpestriz128:
15964 Opcode = X86ISD::PCMPESTRI;
15965 X86CC = X86::COND_E;
15968 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15969 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15970 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15971 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15972 DAG.getConstant(X86CC, MVT::i8),
15973 SDValue(PCMP.getNode(), 1));
15974 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15977 case Intrinsic::x86_sse42_pcmpistri128:
15978 case Intrinsic::x86_sse42_pcmpestri128: {
15980 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15981 Opcode = X86ISD::PCMPISTRI;
15983 Opcode = X86ISD::PCMPESTRI;
15985 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15986 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15987 return DAG.getNode(Opcode, dl, VTs, NewOps);
15990 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15991 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15992 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15993 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15994 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15995 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15996 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15997 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15998 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15999 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16000 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16001 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16002 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16003 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16004 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16005 dl, Op.getValueType(),
16009 Op.getOperand(4), Op.getOperand(1), DAG);
16014 case Intrinsic::x86_fma_vfmadd_ps:
16015 case Intrinsic::x86_fma_vfmadd_pd:
16016 case Intrinsic::x86_fma_vfmsub_ps:
16017 case Intrinsic::x86_fma_vfmsub_pd:
16018 case Intrinsic::x86_fma_vfnmadd_ps:
16019 case Intrinsic::x86_fma_vfnmadd_pd:
16020 case Intrinsic::x86_fma_vfnmsub_ps:
16021 case Intrinsic::x86_fma_vfnmsub_pd:
16022 case Intrinsic::x86_fma_vfmaddsub_ps:
16023 case Intrinsic::x86_fma_vfmaddsub_pd:
16024 case Intrinsic::x86_fma_vfmsubadd_ps:
16025 case Intrinsic::x86_fma_vfmsubadd_pd:
16026 case Intrinsic::x86_fma_vfmadd_ps_256:
16027 case Intrinsic::x86_fma_vfmadd_pd_256:
16028 case Intrinsic::x86_fma_vfmsub_ps_256:
16029 case Intrinsic::x86_fma_vfmsub_pd_256:
16030 case Intrinsic::x86_fma_vfnmadd_ps_256:
16031 case Intrinsic::x86_fma_vfnmadd_pd_256:
16032 case Intrinsic::x86_fma_vfnmsub_ps_256:
16033 case Intrinsic::x86_fma_vfnmsub_pd_256:
16034 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16035 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16036 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16037 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16038 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16039 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16043 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16044 SDValue Src, SDValue Mask, SDValue Base,
16045 SDValue Index, SDValue ScaleOp, SDValue Chain,
16046 const X86Subtarget * Subtarget) {
16048 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16049 assert(C && "Invalid scale type");
16050 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16051 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16052 Index.getSimpleValueType().getVectorNumElements());
16054 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16056 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16058 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16059 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16060 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16061 SDValue Segment = DAG.getRegister(0, MVT::i32);
16062 if (Src.getOpcode() == ISD::UNDEF)
16063 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16064 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16065 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16066 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16067 return DAG.getMergeValues(RetOps, dl);
16070 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16071 SDValue Src, SDValue Mask, SDValue Base,
16072 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16074 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16075 assert(C && "Invalid scale type");
16076 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16077 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16078 SDValue Segment = DAG.getRegister(0, MVT::i32);
16079 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16080 Index.getSimpleValueType().getVectorNumElements());
16082 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16084 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16086 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16087 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16088 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16089 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16090 return SDValue(Res, 1);
16093 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16094 SDValue Mask, SDValue Base, SDValue Index,
16095 SDValue ScaleOp, SDValue Chain) {
16097 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16098 assert(C && "Invalid scale type");
16099 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16100 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16101 SDValue Segment = DAG.getRegister(0, MVT::i32);
16103 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16105 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16107 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16109 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16110 //SDVTList VTs = DAG.getVTList(MVT::Other);
16111 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16112 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16113 return SDValue(Res, 0);
16116 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16117 // read performance monitor counters (x86_rdpmc).
16118 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16119 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16120 SmallVectorImpl<SDValue> &Results) {
16121 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16122 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16125 // The ECX register is used to select the index of the performance counter
16127 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16129 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16131 // Reads the content of a 64-bit performance counter and returns it in the
16132 // registers EDX:EAX.
16133 if (Subtarget->is64Bit()) {
16134 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16135 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16138 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16139 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16142 Chain = HI.getValue(1);
16144 if (Subtarget->is64Bit()) {
16145 // The EAX register is loaded with the low-order 32 bits. The EDX register
16146 // is loaded with the supported high-order bits of the counter.
16147 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16148 DAG.getConstant(32, MVT::i8));
16149 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16150 Results.push_back(Chain);
16154 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16155 SDValue Ops[] = { LO, HI };
16156 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16157 Results.push_back(Pair);
16158 Results.push_back(Chain);
16161 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16162 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16163 // also used to custom lower READCYCLECOUNTER nodes.
16164 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16165 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16166 SmallVectorImpl<SDValue> &Results) {
16167 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16168 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16171 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16172 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16173 // and the EAX register is loaded with the low-order 32 bits.
16174 if (Subtarget->is64Bit()) {
16175 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16176 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16179 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16180 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16183 SDValue Chain = HI.getValue(1);
16185 if (Opcode == X86ISD::RDTSCP_DAG) {
16186 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16188 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16189 // the ECX register. Add 'ecx' explicitly to the chain.
16190 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16192 // Explicitly store the content of ECX at the location passed in input
16193 // to the 'rdtscp' intrinsic.
16194 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16195 MachinePointerInfo(), false, false, 0);
16198 if (Subtarget->is64Bit()) {
16199 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16200 // the EAX register is loaded with the low-order 32 bits.
16201 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16202 DAG.getConstant(32, MVT::i8));
16203 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16204 Results.push_back(Chain);
16208 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16209 SDValue Ops[] = { LO, HI };
16210 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16211 Results.push_back(Pair);
16212 Results.push_back(Chain);
16215 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16216 SelectionDAG &DAG) {
16217 SmallVector<SDValue, 2> Results;
16219 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16221 return DAG.getMergeValues(Results, DL);
16225 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16226 SelectionDAG &DAG) {
16227 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16229 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16234 switch(IntrData->Type) {
16236 llvm_unreachable("Unknown Intrinsic Type");
16240 // Emit the node with the right value type.
16241 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16242 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16244 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16245 // Otherwise return the value from Rand, which is always 0, casted to i32.
16246 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16247 DAG.getConstant(1, Op->getValueType(1)),
16248 DAG.getConstant(X86::COND_B, MVT::i32),
16249 SDValue(Result.getNode(), 1) };
16250 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16251 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16254 // Return { result, isValid, chain }.
16255 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16256 SDValue(Result.getNode(), 2));
16259 //gather(v1, mask, index, base, scale);
16260 SDValue Chain = Op.getOperand(0);
16261 SDValue Src = Op.getOperand(2);
16262 SDValue Base = Op.getOperand(3);
16263 SDValue Index = Op.getOperand(4);
16264 SDValue Mask = Op.getOperand(5);
16265 SDValue Scale = Op.getOperand(6);
16266 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16270 //scatter(base, mask, index, v1, scale);
16271 SDValue Chain = Op.getOperand(0);
16272 SDValue Base = Op.getOperand(2);
16273 SDValue Mask = Op.getOperand(3);
16274 SDValue Index = Op.getOperand(4);
16275 SDValue Src = Op.getOperand(5);
16276 SDValue Scale = Op.getOperand(6);
16277 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16280 SDValue Hint = Op.getOperand(6);
16282 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16283 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16284 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16285 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16286 SDValue Chain = Op.getOperand(0);
16287 SDValue Mask = Op.getOperand(2);
16288 SDValue Index = Op.getOperand(3);
16289 SDValue Base = Op.getOperand(4);
16290 SDValue Scale = Op.getOperand(5);
16291 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16293 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16295 SmallVector<SDValue, 2> Results;
16296 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16297 return DAG.getMergeValues(Results, dl);
16299 // Read Performance Monitoring Counters.
16301 SmallVector<SDValue, 2> Results;
16302 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16303 return DAG.getMergeValues(Results, dl);
16305 // XTEST intrinsics.
16307 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16308 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16309 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16310 DAG.getConstant(X86::COND_NE, MVT::i8),
16312 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16313 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16314 Ret, SDValue(InTrans.getNode(), 1));
16318 SmallVector<SDValue, 2> Results;
16319 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16320 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16321 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16322 DAG.getConstant(-1, MVT::i8));
16323 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16324 Op.getOperand(4), GenCF.getValue(1));
16325 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16326 Op.getOperand(5), MachinePointerInfo(),
16328 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16329 DAG.getConstant(X86::COND_B, MVT::i8),
16331 Results.push_back(SetCC);
16332 Results.push_back(Store);
16333 return DAG.getMergeValues(Results, dl);
16338 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16339 SelectionDAG &DAG) const {
16340 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16341 MFI->setReturnAddressIsTaken(true);
16343 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16346 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16348 EVT PtrVT = getPointerTy();
16351 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16352 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16353 DAG.getSubtarget().getRegisterInfo());
16354 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16355 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16356 DAG.getNode(ISD::ADD, dl, PtrVT,
16357 FrameAddr, Offset),
16358 MachinePointerInfo(), false, false, false, 0);
16361 // Just load the return address.
16362 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16363 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16364 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16367 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16368 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16369 MFI->setFrameAddressIsTaken(true);
16371 EVT VT = Op.getValueType();
16372 SDLoc dl(Op); // FIXME probably not meaningful
16373 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16374 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16375 DAG.getSubtarget().getRegisterInfo());
16376 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16377 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16378 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16379 "Invalid Frame Register!");
16380 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16382 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16383 MachinePointerInfo(),
16384 false, false, false, 0);
16388 // FIXME? Maybe this could be a TableGen attribute on some registers and
16389 // this table could be generated automatically from RegInfo.
16390 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16392 unsigned Reg = StringSwitch<unsigned>(RegName)
16393 .Case("esp", X86::ESP)
16394 .Case("rsp", X86::RSP)
16398 report_fatal_error("Invalid register name global variable");
16401 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16402 SelectionDAG &DAG) const {
16403 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16404 DAG.getSubtarget().getRegisterInfo());
16405 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16408 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16409 SDValue Chain = Op.getOperand(0);
16410 SDValue Offset = Op.getOperand(1);
16411 SDValue Handler = Op.getOperand(2);
16414 EVT PtrVT = getPointerTy();
16415 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16416 DAG.getSubtarget().getRegisterInfo());
16417 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16418 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16419 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16420 "Invalid Frame Register!");
16421 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16422 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16424 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16425 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16426 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16427 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16429 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16431 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16432 DAG.getRegister(StoreAddrReg, PtrVT));
16435 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16436 SelectionDAG &DAG) const {
16438 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16439 DAG.getVTList(MVT::i32, MVT::Other),
16440 Op.getOperand(0), Op.getOperand(1));
16443 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16444 SelectionDAG &DAG) const {
16446 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16447 Op.getOperand(0), Op.getOperand(1));
16450 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16451 return Op.getOperand(0);
16454 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16455 SelectionDAG &DAG) const {
16456 SDValue Root = Op.getOperand(0);
16457 SDValue Trmp = Op.getOperand(1); // trampoline
16458 SDValue FPtr = Op.getOperand(2); // nested function
16459 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16462 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16463 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16465 if (Subtarget->is64Bit()) {
16466 SDValue OutChains[6];
16468 // Large code-model.
16469 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16470 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16472 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16473 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16475 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16477 // Load the pointer to the nested function into R11.
16478 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16479 SDValue Addr = Trmp;
16480 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16481 Addr, MachinePointerInfo(TrmpAddr),
16484 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16485 DAG.getConstant(2, MVT::i64));
16486 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16487 MachinePointerInfo(TrmpAddr, 2),
16490 // Load the 'nest' parameter value into R10.
16491 // R10 is specified in X86CallingConv.td
16492 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16493 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16494 DAG.getConstant(10, MVT::i64));
16495 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16496 Addr, MachinePointerInfo(TrmpAddr, 10),
16499 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16500 DAG.getConstant(12, MVT::i64));
16501 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16502 MachinePointerInfo(TrmpAddr, 12),
16505 // Jump to the nested function.
16506 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16507 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16508 DAG.getConstant(20, MVT::i64));
16509 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16510 Addr, MachinePointerInfo(TrmpAddr, 20),
16513 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16514 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16515 DAG.getConstant(22, MVT::i64));
16516 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16517 MachinePointerInfo(TrmpAddr, 22),
16520 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16522 const Function *Func =
16523 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16524 CallingConv::ID CC = Func->getCallingConv();
16529 llvm_unreachable("Unsupported calling convention");
16530 case CallingConv::C:
16531 case CallingConv::X86_StdCall: {
16532 // Pass 'nest' parameter in ECX.
16533 // Must be kept in sync with X86CallingConv.td
16534 NestReg = X86::ECX;
16536 // Check that ECX wasn't needed by an 'inreg' parameter.
16537 FunctionType *FTy = Func->getFunctionType();
16538 const AttributeSet &Attrs = Func->getAttributes();
16540 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16541 unsigned InRegCount = 0;
16544 for (FunctionType::param_iterator I = FTy->param_begin(),
16545 E = FTy->param_end(); I != E; ++I, ++Idx)
16546 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16547 // FIXME: should only count parameters that are lowered to integers.
16548 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16550 if (InRegCount > 2) {
16551 report_fatal_error("Nest register in use - reduce number of inreg"
16557 case CallingConv::X86_FastCall:
16558 case CallingConv::X86_ThisCall:
16559 case CallingConv::Fast:
16560 // Pass 'nest' parameter in EAX.
16561 // Must be kept in sync with X86CallingConv.td
16562 NestReg = X86::EAX;
16566 SDValue OutChains[4];
16567 SDValue Addr, Disp;
16569 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16570 DAG.getConstant(10, MVT::i32));
16571 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16573 // This is storing the opcode for MOV32ri.
16574 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16575 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16576 OutChains[0] = DAG.getStore(Root, dl,
16577 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16578 Trmp, MachinePointerInfo(TrmpAddr),
16581 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16582 DAG.getConstant(1, MVT::i32));
16583 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16584 MachinePointerInfo(TrmpAddr, 1),
16587 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16588 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16589 DAG.getConstant(5, MVT::i32));
16590 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
16591 MachinePointerInfo(TrmpAddr, 5),
16594 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16595 DAG.getConstant(6, MVT::i32));
16596 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16597 MachinePointerInfo(TrmpAddr, 6),
16600 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16604 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16605 SelectionDAG &DAG) const {
16607 The rounding mode is in bits 11:10 of FPSR, and has the following
16609 00 Round to nearest
16614 FLT_ROUNDS, on the other hand, expects the following:
16621 To perform the conversion, we do:
16622 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16625 MachineFunction &MF = DAG.getMachineFunction();
16626 const TargetMachine &TM = MF.getTarget();
16627 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
16628 unsigned StackAlignment = TFI.getStackAlignment();
16629 MVT VT = Op.getSimpleValueType();
16632 // Save FP Control Word to stack slot
16633 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16634 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16636 MachineMemOperand *MMO =
16637 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16638 MachineMemOperand::MOStore, 2, 2);
16640 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16641 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16642 DAG.getVTList(MVT::Other),
16643 Ops, MVT::i16, MMO);
16645 // Load FP Control Word from stack slot
16646 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16647 MachinePointerInfo(), false, false, false, 0);
16649 // Transform as necessary
16651 DAG.getNode(ISD::SRL, DL, MVT::i16,
16652 DAG.getNode(ISD::AND, DL, MVT::i16,
16653 CWD, DAG.getConstant(0x800, MVT::i16)),
16654 DAG.getConstant(11, MVT::i8));
16656 DAG.getNode(ISD::SRL, DL, MVT::i16,
16657 DAG.getNode(ISD::AND, DL, MVT::i16,
16658 CWD, DAG.getConstant(0x400, MVT::i16)),
16659 DAG.getConstant(9, MVT::i8));
16662 DAG.getNode(ISD::AND, DL, MVT::i16,
16663 DAG.getNode(ISD::ADD, DL, MVT::i16,
16664 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16665 DAG.getConstant(1, MVT::i16)),
16666 DAG.getConstant(3, MVT::i16));
16668 return DAG.getNode((VT.getSizeInBits() < 16 ?
16669 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16672 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16673 MVT VT = Op.getSimpleValueType();
16675 unsigned NumBits = VT.getSizeInBits();
16678 Op = Op.getOperand(0);
16679 if (VT == MVT::i8) {
16680 // Zero extend to i32 since there is not an i8 bsr.
16682 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16685 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16686 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16687 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16689 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16692 DAG.getConstant(NumBits+NumBits-1, OpVT),
16693 DAG.getConstant(X86::COND_E, MVT::i8),
16696 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16698 // Finally xor with NumBits-1.
16699 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16702 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16706 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16707 MVT VT = Op.getSimpleValueType();
16709 unsigned NumBits = VT.getSizeInBits();
16712 Op = Op.getOperand(0);
16713 if (VT == MVT::i8) {
16714 // Zero extend to i32 since there is not an i8 bsr.
16716 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16719 // Issue a bsr (scan bits in reverse).
16720 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16721 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16723 // And xor with NumBits-1.
16724 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16727 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16731 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16732 MVT VT = Op.getSimpleValueType();
16733 unsigned NumBits = VT.getSizeInBits();
16735 Op = Op.getOperand(0);
16737 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16738 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16739 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16741 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16744 DAG.getConstant(NumBits, VT),
16745 DAG.getConstant(X86::COND_E, MVT::i8),
16748 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16751 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16752 // ones, and then concatenate the result back.
16753 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16754 MVT VT = Op.getSimpleValueType();
16756 assert(VT.is256BitVector() && VT.isInteger() &&
16757 "Unsupported value type for operation");
16759 unsigned NumElems = VT.getVectorNumElements();
16762 // Extract the LHS vectors
16763 SDValue LHS = Op.getOperand(0);
16764 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16765 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16767 // Extract the RHS vectors
16768 SDValue RHS = Op.getOperand(1);
16769 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16770 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16772 MVT EltVT = VT.getVectorElementType();
16773 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16775 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16776 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16777 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16780 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16781 assert(Op.getSimpleValueType().is256BitVector() &&
16782 Op.getSimpleValueType().isInteger() &&
16783 "Only handle AVX 256-bit vector integer operation");
16784 return Lower256IntArith(Op, DAG);
16787 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16788 assert(Op.getSimpleValueType().is256BitVector() &&
16789 Op.getSimpleValueType().isInteger() &&
16790 "Only handle AVX 256-bit vector integer operation");
16791 return Lower256IntArith(Op, DAG);
16794 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16795 SelectionDAG &DAG) {
16797 MVT VT = Op.getSimpleValueType();
16799 // Decompose 256-bit ops into smaller 128-bit ops.
16800 if (VT.is256BitVector() && !Subtarget->hasInt256())
16801 return Lower256IntArith(Op, DAG);
16803 SDValue A = Op.getOperand(0);
16804 SDValue B = Op.getOperand(1);
16806 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16807 if (VT == MVT::v4i32) {
16808 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16809 "Should not custom lower when pmuldq is available!");
16811 // Extract the odd parts.
16812 static const int UnpackMask[] = { 1, -1, 3, -1 };
16813 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16814 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16816 // Multiply the even parts.
16817 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16818 // Now multiply odd parts.
16819 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16821 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16822 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16824 // Merge the two vectors back together with a shuffle. This expands into 2
16826 static const int ShufMask[] = { 0, 4, 2, 6 };
16827 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16830 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16831 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16833 // Ahi = psrlqi(a, 32);
16834 // Bhi = psrlqi(b, 32);
16836 // AloBlo = pmuludq(a, b);
16837 // AloBhi = pmuludq(a, Bhi);
16838 // AhiBlo = pmuludq(Ahi, b);
16840 // AloBhi = psllqi(AloBhi, 32);
16841 // AhiBlo = psllqi(AhiBlo, 32);
16842 // return AloBlo + AloBhi + AhiBlo;
16844 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16845 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16847 // Bit cast to 32-bit vectors for MULUDQ
16848 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16849 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16850 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16851 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16852 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16853 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16855 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16856 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16857 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16859 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16860 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16862 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16863 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16866 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16867 assert(Subtarget->isTargetWin64() && "Unexpected target");
16868 EVT VT = Op.getValueType();
16869 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16870 "Unexpected return type for lowering");
16874 switch (Op->getOpcode()) {
16875 default: llvm_unreachable("Unexpected request for libcall!");
16876 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16877 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16878 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16879 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16880 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16881 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16885 SDValue InChain = DAG.getEntryNode();
16887 TargetLowering::ArgListTy Args;
16888 TargetLowering::ArgListEntry Entry;
16889 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16890 EVT ArgVT = Op->getOperand(i).getValueType();
16891 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16892 "Unexpected argument type for lowering");
16893 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16894 Entry.Node = StackPtr;
16895 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16897 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16898 Entry.Ty = PointerType::get(ArgTy,0);
16899 Entry.isSExt = false;
16900 Entry.isZExt = false;
16901 Args.push_back(Entry);
16904 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16907 TargetLowering::CallLoweringInfo CLI(DAG);
16908 CLI.setDebugLoc(dl).setChain(InChain)
16909 .setCallee(getLibcallCallingConv(LC),
16910 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16911 Callee, std::move(Args), 0)
16912 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16914 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16915 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16918 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16919 SelectionDAG &DAG) {
16920 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16921 EVT VT = Op0.getValueType();
16924 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16925 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16927 // PMULxD operations multiply each even value (starting at 0) of LHS with
16928 // the related value of RHS and produce a widen result.
16929 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16930 // => <2 x i64> <ae|cg>
16932 // In other word, to have all the results, we need to perform two PMULxD:
16933 // 1. one with the even values.
16934 // 2. one with the odd values.
16935 // To achieve #2, with need to place the odd values at an even position.
16937 // Place the odd value at an even position (basically, shift all values 1
16938 // step to the left):
16939 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16940 // <a|b|c|d> => <b|undef|d|undef>
16941 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16942 // <e|f|g|h> => <f|undef|h|undef>
16943 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16945 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16947 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16948 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16950 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16951 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16952 // => <2 x i64> <ae|cg>
16953 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16954 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16955 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16956 // => <2 x i64> <bf|dh>
16957 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16958 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16960 // Shuffle it back into the right order.
16961 SDValue Highs, Lows;
16962 if (VT == MVT::v8i32) {
16963 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16964 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16965 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16966 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16968 const int HighMask[] = {1, 5, 3, 7};
16969 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16970 const int LowMask[] = {0, 4, 2, 6};
16971 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16974 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16975 // unsigned multiply.
16976 if (IsSigned && !Subtarget->hasSSE41()) {
16978 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16979 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16980 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16981 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16982 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16984 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16985 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16988 // The first result of MUL_LOHI is actually the low value, followed by the
16990 SDValue Ops[] = {Lows, Highs};
16991 return DAG.getMergeValues(Ops, dl);
16994 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16995 const X86Subtarget *Subtarget) {
16996 MVT VT = Op.getSimpleValueType();
16998 SDValue R = Op.getOperand(0);
16999 SDValue Amt = Op.getOperand(1);
17001 // Optimize shl/srl/sra with constant shift amount.
17002 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17003 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17004 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17006 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17007 (Subtarget->hasInt256() &&
17008 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17009 (Subtarget->hasAVX512() &&
17010 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17011 if (Op.getOpcode() == ISD::SHL)
17012 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17014 if (Op.getOpcode() == ISD::SRL)
17015 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17017 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17018 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17022 if (VT == MVT::v16i8) {
17023 if (Op.getOpcode() == ISD::SHL) {
17024 // Make a large shift.
17025 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17026 MVT::v8i16, R, ShiftAmt,
17028 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17029 // Zero out the rightmost bits.
17030 SmallVector<SDValue, 16> V(16,
17031 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17033 return DAG.getNode(ISD::AND, dl, VT, SHL,
17034 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17036 if (Op.getOpcode() == ISD::SRL) {
17037 // Make a large shift.
17038 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17039 MVT::v8i16, R, ShiftAmt,
17041 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17042 // Zero out the leftmost bits.
17043 SmallVector<SDValue, 16> V(16,
17044 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17046 return DAG.getNode(ISD::AND, dl, VT, SRL,
17047 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17049 if (Op.getOpcode() == ISD::SRA) {
17050 if (ShiftAmt == 7) {
17051 // R s>> 7 === R s< 0
17052 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17053 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17056 // R s>> a === ((R u>> a) ^ m) - m
17057 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17058 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17060 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17061 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17062 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17065 llvm_unreachable("Unknown shift opcode.");
17068 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17069 if (Op.getOpcode() == ISD::SHL) {
17070 // Make a large shift.
17071 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17072 MVT::v16i16, R, ShiftAmt,
17074 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17075 // Zero out the rightmost bits.
17076 SmallVector<SDValue, 32> V(32,
17077 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17079 return DAG.getNode(ISD::AND, dl, VT, SHL,
17080 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17082 if (Op.getOpcode() == ISD::SRL) {
17083 // Make a large shift.
17084 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17085 MVT::v16i16, R, ShiftAmt,
17087 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17088 // Zero out the leftmost bits.
17089 SmallVector<SDValue, 32> V(32,
17090 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17092 return DAG.getNode(ISD::AND, dl, VT, SRL,
17093 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17095 if (Op.getOpcode() == ISD::SRA) {
17096 if (ShiftAmt == 7) {
17097 // R s>> 7 === R s< 0
17098 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17099 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17102 // R s>> a === ((R u>> a) ^ m) - m
17103 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17104 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
17106 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17107 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17108 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17111 llvm_unreachable("Unknown shift opcode.");
17116 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17117 if (!Subtarget->is64Bit() &&
17118 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17119 Amt.getOpcode() == ISD::BITCAST &&
17120 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17121 Amt = Amt.getOperand(0);
17122 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17123 VT.getVectorNumElements();
17124 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17125 uint64_t ShiftAmt = 0;
17126 for (unsigned i = 0; i != Ratio; ++i) {
17127 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17131 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17133 // Check remaining shift amounts.
17134 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17135 uint64_t ShAmt = 0;
17136 for (unsigned j = 0; j != Ratio; ++j) {
17137 ConstantSDNode *C =
17138 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17142 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17144 if (ShAmt != ShiftAmt)
17147 switch (Op.getOpcode()) {
17149 llvm_unreachable("Unknown shift opcode!");
17151 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17154 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17157 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17165 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17166 const X86Subtarget* Subtarget) {
17167 MVT VT = Op.getSimpleValueType();
17169 SDValue R = Op.getOperand(0);
17170 SDValue Amt = Op.getOperand(1);
17172 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
17173 VT == MVT::v4i32 || VT == MVT::v8i16 ||
17174 (Subtarget->hasInt256() &&
17175 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
17176 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17177 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17179 EVT EltVT = VT.getVectorElementType();
17181 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17182 unsigned NumElts = VT.getVectorNumElements();
17184 for (i = 0; i != NumElts; ++i) {
17185 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
17189 for (j = i; j != NumElts; ++j) {
17190 SDValue Arg = Amt.getOperand(j);
17191 if (Arg.getOpcode() == ISD::UNDEF) continue;
17192 if (Arg != Amt.getOperand(i))
17195 if (i != NumElts && j == NumElts)
17196 BaseShAmt = Amt.getOperand(i);
17198 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17199 Amt = Amt.getOperand(0);
17200 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
17201 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
17202 SDValue InVec = Amt.getOperand(0);
17203 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17204 unsigned NumElts = InVec.getValueType().getVectorNumElements();
17206 for (; i != NumElts; ++i) {
17207 SDValue Arg = InVec.getOperand(i);
17208 if (Arg.getOpcode() == ISD::UNDEF) continue;
17212 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17213 if (ConstantSDNode *C =
17214 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17215 unsigned SplatIdx =
17216 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
17217 if (C->getZExtValue() == SplatIdx)
17218 BaseShAmt = InVec.getOperand(1);
17221 if (!BaseShAmt.getNode())
17222 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
17223 DAG.getIntPtrConstant(0));
17227 if (BaseShAmt.getNode()) {
17228 if (EltVT.bitsGT(MVT::i32))
17229 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
17230 else if (EltVT.bitsLT(MVT::i32))
17231 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17233 switch (Op.getOpcode()) {
17235 llvm_unreachable("Unknown shift opcode!");
17237 switch (VT.SimpleTy) {
17238 default: return SDValue();
17247 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17250 switch (VT.SimpleTy) {
17251 default: return SDValue();
17258 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17261 switch (VT.SimpleTy) {
17262 default: return SDValue();
17271 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17277 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17278 if (!Subtarget->is64Bit() &&
17279 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17280 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17281 Amt.getOpcode() == ISD::BITCAST &&
17282 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17283 Amt = Amt.getOperand(0);
17284 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17285 VT.getVectorNumElements();
17286 std::vector<SDValue> Vals(Ratio);
17287 for (unsigned i = 0; i != Ratio; ++i)
17288 Vals[i] = Amt.getOperand(i);
17289 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17290 for (unsigned j = 0; j != Ratio; ++j)
17291 if (Vals[j] != Amt.getOperand(i + j))
17294 switch (Op.getOpcode()) {
17296 llvm_unreachable("Unknown shift opcode!");
17298 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17300 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17302 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17309 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17310 SelectionDAG &DAG) {
17311 MVT VT = Op.getSimpleValueType();
17313 SDValue R = Op.getOperand(0);
17314 SDValue Amt = Op.getOperand(1);
17317 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17318 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17320 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17324 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17328 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17330 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17331 if (Subtarget->hasInt256()) {
17332 if (Op.getOpcode() == ISD::SRL &&
17333 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17334 VT == MVT::v4i64 || VT == MVT::v8i32))
17336 if (Op.getOpcode() == ISD::SHL &&
17337 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17338 VT == MVT::v4i64 || VT == MVT::v8i32))
17340 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17344 // If possible, lower this packed shift into a vector multiply instead of
17345 // expanding it into a sequence of scalar shifts.
17346 // Do this only if the vector shift count is a constant build_vector.
17347 if (Op.getOpcode() == ISD::SHL &&
17348 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17349 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17350 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17351 SmallVector<SDValue, 8> Elts;
17352 EVT SVT = VT.getScalarType();
17353 unsigned SVTBits = SVT.getSizeInBits();
17354 const APInt &One = APInt(SVTBits, 1);
17355 unsigned NumElems = VT.getVectorNumElements();
17357 for (unsigned i=0; i !=NumElems; ++i) {
17358 SDValue Op = Amt->getOperand(i);
17359 if (Op->getOpcode() == ISD::UNDEF) {
17360 Elts.push_back(Op);
17364 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17365 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17366 uint64_t ShAmt = C.getZExtValue();
17367 if (ShAmt >= SVTBits) {
17368 Elts.push_back(DAG.getUNDEF(SVT));
17371 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17373 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17374 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17377 // Lower SHL with variable shift amount.
17378 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17379 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17381 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17382 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17383 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17384 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17387 // If possible, lower this shift as a sequence of two shifts by
17388 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17390 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17392 // Could be rewritten as:
17393 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17395 // The advantage is that the two shifts from the example would be
17396 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17397 // the vector shift into four scalar shifts plus four pairs of vector
17399 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17400 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17401 unsigned TargetOpcode = X86ISD::MOVSS;
17402 bool CanBeSimplified;
17403 // The splat value for the first packed shift (the 'X' from the example).
17404 SDValue Amt1 = Amt->getOperand(0);
17405 // The splat value for the second packed shift (the 'Y' from the example).
17406 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17407 Amt->getOperand(2);
17409 // See if it is possible to replace this node with a sequence of
17410 // two shifts followed by a MOVSS/MOVSD
17411 if (VT == MVT::v4i32) {
17412 // Check if it is legal to use a MOVSS.
17413 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17414 Amt2 == Amt->getOperand(3);
17415 if (!CanBeSimplified) {
17416 // Otherwise, check if we can still simplify this node using a MOVSD.
17417 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17418 Amt->getOperand(2) == Amt->getOperand(3);
17419 TargetOpcode = X86ISD::MOVSD;
17420 Amt2 = Amt->getOperand(2);
17423 // Do similar checks for the case where the machine value type
17425 CanBeSimplified = Amt1 == Amt->getOperand(1);
17426 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17427 CanBeSimplified = Amt2 == Amt->getOperand(i);
17429 if (!CanBeSimplified) {
17430 TargetOpcode = X86ISD::MOVSD;
17431 CanBeSimplified = true;
17432 Amt2 = Amt->getOperand(4);
17433 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17434 CanBeSimplified = Amt1 == Amt->getOperand(i);
17435 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17436 CanBeSimplified = Amt2 == Amt->getOperand(j);
17440 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17441 isa<ConstantSDNode>(Amt2)) {
17442 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17443 EVT CastVT = MVT::v4i32;
17445 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17446 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17448 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17449 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17450 if (TargetOpcode == X86ISD::MOVSD)
17451 CastVT = MVT::v2i64;
17452 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17453 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17454 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17456 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17460 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17461 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17464 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17465 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17467 // Turn 'a' into a mask suitable for VSELECT
17468 SDValue VSelM = DAG.getConstant(0x80, VT);
17469 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17470 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17472 SDValue CM1 = DAG.getConstant(0x0f, VT);
17473 SDValue CM2 = DAG.getConstant(0x3f, VT);
17475 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17476 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17477 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17478 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17479 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17482 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17483 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17484 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17486 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17487 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17488 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17489 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17490 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17493 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17494 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17495 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17497 // return VSELECT(r, r+r, a);
17498 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17499 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17503 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17504 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17505 // solution better.
17506 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17507 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17509 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17510 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17511 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17512 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17513 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17516 // Decompose 256-bit shifts into smaller 128-bit shifts.
17517 if (VT.is256BitVector()) {
17518 unsigned NumElems = VT.getVectorNumElements();
17519 MVT EltVT = VT.getVectorElementType();
17520 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17522 // Extract the two vectors
17523 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17524 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17526 // Recreate the shift amount vectors
17527 SDValue Amt1, Amt2;
17528 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17529 // Constant shift amount
17530 SmallVector<SDValue, 4> Amt1Csts;
17531 SmallVector<SDValue, 4> Amt2Csts;
17532 for (unsigned i = 0; i != NumElems/2; ++i)
17533 Amt1Csts.push_back(Amt->getOperand(i));
17534 for (unsigned i = NumElems/2; i != NumElems; ++i)
17535 Amt2Csts.push_back(Amt->getOperand(i));
17537 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17538 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17540 // Variable shift amount
17541 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17542 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17545 // Issue new vector shifts for the smaller types
17546 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17547 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17549 // Concatenate the result back
17550 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17556 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17557 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17558 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17559 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17560 // has only one use.
17561 SDNode *N = Op.getNode();
17562 SDValue LHS = N->getOperand(0);
17563 SDValue RHS = N->getOperand(1);
17564 unsigned BaseOp = 0;
17567 switch (Op.getOpcode()) {
17568 default: llvm_unreachable("Unknown ovf instruction!");
17570 // A subtract of one will be selected as a INC. Note that INC doesn't
17571 // set CF, so we can't do this for UADDO.
17572 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17574 BaseOp = X86ISD::INC;
17575 Cond = X86::COND_O;
17578 BaseOp = X86ISD::ADD;
17579 Cond = X86::COND_O;
17582 BaseOp = X86ISD::ADD;
17583 Cond = X86::COND_B;
17586 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17587 // set CF, so we can't do this for USUBO.
17588 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17590 BaseOp = X86ISD::DEC;
17591 Cond = X86::COND_O;
17594 BaseOp = X86ISD::SUB;
17595 Cond = X86::COND_O;
17598 BaseOp = X86ISD::SUB;
17599 Cond = X86::COND_B;
17602 BaseOp = X86ISD::SMUL;
17603 Cond = X86::COND_O;
17605 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17606 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17608 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17611 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17612 DAG.getConstant(X86::COND_O, MVT::i32),
17613 SDValue(Sum.getNode(), 2));
17615 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17619 // Also sets EFLAGS.
17620 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17621 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17624 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17625 DAG.getConstant(Cond, MVT::i32),
17626 SDValue(Sum.getNode(), 1));
17628 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17631 // Sign extension of the low part of vector elements. This may be used either
17632 // when sign extend instructions are not available or if the vector element
17633 // sizes already match the sign-extended size. If the vector elements are in
17634 // their pre-extended size and sign extend instructions are available, that will
17635 // be handled by LowerSIGN_EXTEND.
17636 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
17637 SelectionDAG &DAG) const {
17639 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
17640 MVT VT = Op.getSimpleValueType();
17642 if (!Subtarget->hasSSE2() || !VT.isVector())
17645 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
17646 ExtraVT.getScalarType().getSizeInBits();
17648 switch (VT.SimpleTy) {
17649 default: return SDValue();
17652 if (!Subtarget->hasFp256())
17654 if (!Subtarget->hasInt256()) {
17655 // needs to be split
17656 unsigned NumElems = VT.getVectorNumElements();
17658 // Extract the LHS vectors
17659 SDValue LHS = Op.getOperand(0);
17660 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17661 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17663 MVT EltVT = VT.getVectorElementType();
17664 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17666 EVT ExtraEltVT = ExtraVT.getVectorElementType();
17667 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
17668 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
17670 SDValue Extra = DAG.getValueType(ExtraVT);
17672 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
17673 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
17675 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
17680 SDValue Op0 = Op.getOperand(0);
17682 // This is a sign extension of some low part of vector elements without
17683 // changing the size of the vector elements themselves:
17684 // Shift-Left + Shift-Right-Algebraic.
17685 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
17687 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
17693 /// Returns true if the operand type is exactly twice the native width, and
17694 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17695 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17696 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17697 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17698 const X86Subtarget &Subtarget =
17699 getTargetMachine().getSubtarget<X86Subtarget>();
17700 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17703 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17704 else if (OpWidth == 128)
17705 return Subtarget.hasCmpxchg16b();
17710 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17711 return needsCmpXchgNb(SI->getValueOperand()->getType());
17714 // Note: this turns large loads into lock cmpxchg8b/16b.
17715 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17716 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17717 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17718 return needsCmpXchgNb(PTy->getElementType());
17721 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17722 const X86Subtarget &Subtarget =
17723 getTargetMachine().getSubtarget<X86Subtarget>();
17724 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
17725 const Type *MemType = AI->getType();
17727 // If the operand is too big, we must see if cmpxchg8/16b is available
17728 // and default to library calls otherwise.
17729 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17730 return needsCmpXchgNb(MemType);
17732 AtomicRMWInst::BinOp Op = AI->getOperation();
17735 llvm_unreachable("Unknown atomic operation");
17736 case AtomicRMWInst::Xchg:
17737 case AtomicRMWInst::Add:
17738 case AtomicRMWInst::Sub:
17739 // It's better to use xadd, xsub or xchg for these in all cases.
17741 case AtomicRMWInst::Or:
17742 case AtomicRMWInst::And:
17743 case AtomicRMWInst::Xor:
17744 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17745 // prefix to a normal instruction for these operations.
17746 return !AI->use_empty();
17747 case AtomicRMWInst::Nand:
17748 case AtomicRMWInst::Max:
17749 case AtomicRMWInst::Min:
17750 case AtomicRMWInst::UMax:
17751 case AtomicRMWInst::UMin:
17752 // These always require a non-trivial set of data operations on x86. We must
17753 // use a cmpxchg loop.
17758 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17759 SelectionDAG &DAG) {
17761 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17762 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17763 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17764 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17766 // The only fence that needs an instruction is a sequentially-consistent
17767 // cross-thread fence.
17768 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17769 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17770 // no-sse2). There isn't any reason to disable it if the target processor
17772 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
17773 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17775 SDValue Chain = Op.getOperand(0);
17776 SDValue Zero = DAG.getConstant(0, MVT::i32);
17778 DAG.getRegister(X86::ESP, MVT::i32), // Base
17779 DAG.getTargetConstant(1, MVT::i8), // Scale
17780 DAG.getRegister(0, MVT::i32), // Index
17781 DAG.getTargetConstant(0, MVT::i32), // Disp
17782 DAG.getRegister(0, MVT::i32), // Segment.
17786 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17787 return SDValue(Res, 0);
17790 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17791 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17794 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17795 SelectionDAG &DAG) {
17796 MVT T = Op.getSimpleValueType();
17800 switch(T.SimpleTy) {
17801 default: llvm_unreachable("Invalid value type!");
17802 case MVT::i8: Reg = X86::AL; size = 1; break;
17803 case MVT::i16: Reg = X86::AX; size = 2; break;
17804 case MVT::i32: Reg = X86::EAX; size = 4; break;
17806 assert(Subtarget->is64Bit() && "Node not type legal!");
17807 Reg = X86::RAX; size = 8;
17810 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17811 Op.getOperand(2), SDValue());
17812 SDValue Ops[] = { cpIn.getValue(0),
17815 DAG.getTargetConstant(size, MVT::i8),
17816 cpIn.getValue(1) };
17817 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17818 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17819 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17823 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17824 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17825 MVT::i32, cpOut.getValue(2));
17826 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17827 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17829 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17830 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17831 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17835 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17836 SelectionDAG &DAG) {
17837 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17838 MVT DstVT = Op.getSimpleValueType();
17840 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17841 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17842 if (DstVT != MVT::f64)
17843 // This conversion needs to be expanded.
17846 SDValue InVec = Op->getOperand(0);
17848 unsigned NumElts = SrcVT.getVectorNumElements();
17849 EVT SVT = SrcVT.getVectorElementType();
17851 // Widen the vector in input in the case of MVT::v2i32.
17852 // Example: from MVT::v2i32 to MVT::v4i32.
17853 SmallVector<SDValue, 16> Elts;
17854 for (unsigned i = 0, e = NumElts; i != e; ++i)
17855 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17856 DAG.getIntPtrConstant(i)));
17858 // Explicitly mark the extra elements as Undef.
17859 SDValue Undef = DAG.getUNDEF(SVT);
17860 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
17861 Elts.push_back(Undef);
17863 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17864 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17865 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17866 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17867 DAG.getIntPtrConstant(0));
17870 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17871 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17872 assert((DstVT == MVT::i64 ||
17873 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17874 "Unexpected custom BITCAST");
17875 // i64 <=> MMX conversions are Legal.
17876 if (SrcVT==MVT::i64 && DstVT.isVector())
17878 if (DstVT==MVT::i64 && SrcVT.isVector())
17880 // MMX <=> MMX conversions are Legal.
17881 if (SrcVT.isVector() && DstVT.isVector())
17883 // All other conversions need to be expanded.
17887 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17888 SDNode *Node = Op.getNode();
17890 EVT T = Node->getValueType(0);
17891 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17892 DAG.getConstant(0, T), Node->getOperand(2));
17893 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17894 cast<AtomicSDNode>(Node)->getMemoryVT(),
17895 Node->getOperand(0),
17896 Node->getOperand(1), negOp,
17897 cast<AtomicSDNode>(Node)->getMemOperand(),
17898 cast<AtomicSDNode>(Node)->getOrdering(),
17899 cast<AtomicSDNode>(Node)->getSynchScope());
17902 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17903 SDNode *Node = Op.getNode();
17905 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17907 // Convert seq_cst store -> xchg
17908 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17909 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17910 // (The only way to get a 16-byte store is cmpxchg16b)
17911 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17912 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17913 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17914 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17915 cast<AtomicSDNode>(Node)->getMemoryVT(),
17916 Node->getOperand(0),
17917 Node->getOperand(1), Node->getOperand(2),
17918 cast<AtomicSDNode>(Node)->getMemOperand(),
17919 cast<AtomicSDNode>(Node)->getOrdering(),
17920 cast<AtomicSDNode>(Node)->getSynchScope());
17921 return Swap.getValue(1);
17923 // Other atomic stores have a simple pattern.
17927 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17928 EVT VT = Op.getNode()->getSimpleValueType(0);
17930 // Let legalize expand this if it isn't a legal type yet.
17931 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17934 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17937 bool ExtraOp = false;
17938 switch (Op.getOpcode()) {
17939 default: llvm_unreachable("Invalid code");
17940 case ISD::ADDC: Opc = X86ISD::ADD; break;
17941 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17942 case ISD::SUBC: Opc = X86ISD::SUB; break;
17943 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17947 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17949 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17950 Op.getOperand(1), Op.getOperand(2));
17953 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17954 SelectionDAG &DAG) {
17955 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17957 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17958 // which returns the values as { float, float } (in XMM0) or
17959 // { double, double } (which is returned in XMM0, XMM1).
17961 SDValue Arg = Op.getOperand(0);
17962 EVT ArgVT = Arg.getValueType();
17963 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17965 TargetLowering::ArgListTy Args;
17966 TargetLowering::ArgListEntry Entry;
17970 Entry.isSExt = false;
17971 Entry.isZExt = false;
17972 Args.push_back(Entry);
17974 bool isF64 = ArgVT == MVT::f64;
17975 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17976 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17977 // the results are returned via SRet in memory.
17978 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17979 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17980 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17982 Type *RetTy = isF64
17983 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
17984 : (Type*)VectorType::get(ArgTy, 4);
17986 TargetLowering::CallLoweringInfo CLI(DAG);
17987 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17988 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17990 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17993 // Returned in xmm0 and xmm1.
17994 return CallResult.first;
17996 // Returned in bits 0:31 and 32:64 xmm0.
17997 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17998 CallResult.first, DAG.getIntPtrConstant(0));
17999 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18000 CallResult.first, DAG.getIntPtrConstant(1));
18001 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18002 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18005 /// LowerOperation - Provide custom lowering hooks for some operations.
18007 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18008 switch (Op.getOpcode()) {
18009 default: llvm_unreachable("Should not custom lower this!");
18010 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18011 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18012 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18013 return LowerCMP_SWAP(Op, Subtarget, DAG);
18014 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18015 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18016 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18017 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18018 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18019 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18020 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18021 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18022 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18023 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18024 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18025 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18026 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18027 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18028 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18029 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18030 case ISD::SHL_PARTS:
18031 case ISD::SRA_PARTS:
18032 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18033 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18034 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18035 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18036 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18037 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18038 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18039 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18040 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18041 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18042 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18044 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18045 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18046 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18047 case ISD::SETCC: return LowerSETCC(Op, DAG);
18048 case ISD::SELECT: return LowerSELECT(Op, DAG);
18049 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18050 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18051 case ISD::VASTART: return LowerVASTART(Op, DAG);
18052 case ISD::VAARG: return LowerVAARG(Op, DAG);
18053 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18054 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
18055 case ISD::INTRINSIC_VOID:
18056 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18057 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18058 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18059 case ISD::FRAME_TO_ARGS_OFFSET:
18060 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18061 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18062 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18063 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18064 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18065 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18066 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18067 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18068 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18069 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18070 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18071 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18072 case ISD::UMUL_LOHI:
18073 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18076 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18082 case ISD::UMULO: return LowerXALUO(Op, DAG);
18083 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18084 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18088 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18089 case ISD::ADD: return LowerADD(Op, DAG);
18090 case ISD::SUB: return LowerSUB(Op, DAG);
18091 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18095 /// ReplaceNodeResults - Replace a node with an illegal result type
18096 /// with a new node built out of custom code.
18097 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18098 SmallVectorImpl<SDValue>&Results,
18099 SelectionDAG &DAG) const {
18101 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18102 switch (N->getOpcode()) {
18104 llvm_unreachable("Do not know how to custom type legalize this operation!");
18105 case ISD::SIGN_EXTEND_INREG:
18110 // We don't want to expand or promote these.
18117 case ISD::UDIVREM: {
18118 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18119 Results.push_back(V);
18122 case ISD::FP_TO_SINT:
18123 case ISD::FP_TO_UINT: {
18124 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18126 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18129 std::pair<SDValue,SDValue> Vals =
18130 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18131 SDValue FIST = Vals.first, StackSlot = Vals.second;
18132 if (FIST.getNode()) {
18133 EVT VT = N->getValueType(0);
18134 // Return a load from the stack slot.
18135 if (StackSlot.getNode())
18136 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18137 MachinePointerInfo(),
18138 false, false, false, 0));
18140 Results.push_back(FIST);
18144 case ISD::UINT_TO_FP: {
18145 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18146 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18147 N->getValueType(0) != MVT::v2f32)
18149 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18151 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
18153 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18154 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18155 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
18156 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
18157 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18158 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18161 case ISD::FP_ROUND: {
18162 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18164 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18165 Results.push_back(V);
18168 case ISD::INTRINSIC_W_CHAIN: {
18169 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18171 default : llvm_unreachable("Do not know how to custom type "
18172 "legalize this intrinsic operation!");
18173 case Intrinsic::x86_rdtsc:
18174 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18176 case Intrinsic::x86_rdtscp:
18177 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18179 case Intrinsic::x86_rdpmc:
18180 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18183 case ISD::READCYCLECOUNTER: {
18184 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18187 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18188 EVT T = N->getValueType(0);
18189 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18190 bool Regs64bit = T == MVT::i128;
18191 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18192 SDValue cpInL, cpInH;
18193 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18194 DAG.getConstant(0, HalfT));
18195 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18196 DAG.getConstant(1, HalfT));
18197 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18198 Regs64bit ? X86::RAX : X86::EAX,
18200 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18201 Regs64bit ? X86::RDX : X86::EDX,
18202 cpInH, cpInL.getValue(1));
18203 SDValue swapInL, swapInH;
18204 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18205 DAG.getConstant(0, HalfT));
18206 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18207 DAG.getConstant(1, HalfT));
18208 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18209 Regs64bit ? X86::RBX : X86::EBX,
18210 swapInL, cpInH.getValue(1));
18211 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18212 Regs64bit ? X86::RCX : X86::ECX,
18213 swapInH, swapInL.getValue(1));
18214 SDValue Ops[] = { swapInH.getValue(0),
18216 swapInH.getValue(1) };
18217 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18218 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18219 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18220 X86ISD::LCMPXCHG8_DAG;
18221 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18222 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18223 Regs64bit ? X86::RAX : X86::EAX,
18224 HalfT, Result.getValue(1));
18225 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18226 Regs64bit ? X86::RDX : X86::EDX,
18227 HalfT, cpOutL.getValue(2));
18228 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18230 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18231 MVT::i32, cpOutH.getValue(2));
18233 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18234 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18235 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18237 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18238 Results.push_back(Success);
18239 Results.push_back(EFLAGS.getValue(1));
18242 case ISD::ATOMIC_SWAP:
18243 case ISD::ATOMIC_LOAD_ADD:
18244 case ISD::ATOMIC_LOAD_SUB:
18245 case ISD::ATOMIC_LOAD_AND:
18246 case ISD::ATOMIC_LOAD_OR:
18247 case ISD::ATOMIC_LOAD_XOR:
18248 case ISD::ATOMIC_LOAD_NAND:
18249 case ISD::ATOMIC_LOAD_MIN:
18250 case ISD::ATOMIC_LOAD_MAX:
18251 case ISD::ATOMIC_LOAD_UMIN:
18252 case ISD::ATOMIC_LOAD_UMAX:
18253 case ISD::ATOMIC_LOAD: {
18254 // Delegate to generic TypeLegalization. Situations we can really handle
18255 // should have already been dealt with by AtomicExpandPass.cpp.
18258 case ISD::BITCAST: {
18259 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18260 EVT DstVT = N->getValueType(0);
18261 EVT SrcVT = N->getOperand(0)->getValueType(0);
18263 if (SrcVT != MVT::f64 ||
18264 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18267 unsigned NumElts = DstVT.getVectorNumElements();
18268 EVT SVT = DstVT.getVectorElementType();
18269 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18270 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18271 MVT::v2f64, N->getOperand(0));
18272 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18274 if (ExperimentalVectorWideningLegalization) {
18275 // If we are legalizing vectors by widening, we already have the desired
18276 // legal vector type, just return it.
18277 Results.push_back(ToVecInt);
18281 SmallVector<SDValue, 8> Elts;
18282 for (unsigned i = 0, e = NumElts; i != e; ++i)
18283 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18284 ToVecInt, DAG.getIntPtrConstant(i)));
18286 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18291 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18293 default: return nullptr;
18294 case X86ISD::BSF: return "X86ISD::BSF";
18295 case X86ISD::BSR: return "X86ISD::BSR";
18296 case X86ISD::SHLD: return "X86ISD::SHLD";
18297 case X86ISD::SHRD: return "X86ISD::SHRD";
18298 case X86ISD::FAND: return "X86ISD::FAND";
18299 case X86ISD::FANDN: return "X86ISD::FANDN";
18300 case X86ISD::FOR: return "X86ISD::FOR";
18301 case X86ISD::FXOR: return "X86ISD::FXOR";
18302 case X86ISD::FSRL: return "X86ISD::FSRL";
18303 case X86ISD::FILD: return "X86ISD::FILD";
18304 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18305 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18306 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18307 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18308 case X86ISD::FLD: return "X86ISD::FLD";
18309 case X86ISD::FST: return "X86ISD::FST";
18310 case X86ISD::CALL: return "X86ISD::CALL";
18311 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18312 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18313 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18314 case X86ISD::BT: return "X86ISD::BT";
18315 case X86ISD::CMP: return "X86ISD::CMP";
18316 case X86ISD::COMI: return "X86ISD::COMI";
18317 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18318 case X86ISD::CMPM: return "X86ISD::CMPM";
18319 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18320 case X86ISD::SETCC: return "X86ISD::SETCC";
18321 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18322 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18323 case X86ISD::CMOV: return "X86ISD::CMOV";
18324 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18325 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18326 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18327 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18328 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18329 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18330 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18331 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18332 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18333 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18334 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18335 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18336 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18337 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18338 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18339 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18340 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18341 case X86ISD::HADD: return "X86ISD::HADD";
18342 case X86ISD::HSUB: return "X86ISD::HSUB";
18343 case X86ISD::FHADD: return "X86ISD::FHADD";
18344 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18345 case X86ISD::UMAX: return "X86ISD::UMAX";
18346 case X86ISD::UMIN: return "X86ISD::UMIN";
18347 case X86ISD::SMAX: return "X86ISD::SMAX";
18348 case X86ISD::SMIN: return "X86ISD::SMIN";
18349 case X86ISD::FMAX: return "X86ISD::FMAX";
18350 case X86ISD::FMIN: return "X86ISD::FMIN";
18351 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18352 case X86ISD::FMINC: return "X86ISD::FMINC";
18353 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18354 case X86ISD::FRCP: return "X86ISD::FRCP";
18355 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18356 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18357 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18358 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18359 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18360 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18361 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18362 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18363 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18364 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18365 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18366 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18367 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18368 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18369 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18370 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18371 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18372 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18373 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18374 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18375 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18376 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18377 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18378 case X86ISD::VSHL: return "X86ISD::VSHL";
18379 case X86ISD::VSRL: return "X86ISD::VSRL";
18380 case X86ISD::VSRA: return "X86ISD::VSRA";
18381 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18382 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18383 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18384 case X86ISD::CMPP: return "X86ISD::CMPP";
18385 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18386 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18387 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18388 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18389 case X86ISD::ADD: return "X86ISD::ADD";
18390 case X86ISD::SUB: return "X86ISD::SUB";
18391 case X86ISD::ADC: return "X86ISD::ADC";
18392 case X86ISD::SBB: return "X86ISD::SBB";
18393 case X86ISD::SMUL: return "X86ISD::SMUL";
18394 case X86ISD::UMUL: return "X86ISD::UMUL";
18395 case X86ISD::INC: return "X86ISD::INC";
18396 case X86ISD::DEC: return "X86ISD::DEC";
18397 case X86ISD::OR: return "X86ISD::OR";
18398 case X86ISD::XOR: return "X86ISD::XOR";
18399 case X86ISD::AND: return "X86ISD::AND";
18400 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18401 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18402 case X86ISD::PTEST: return "X86ISD::PTEST";
18403 case X86ISD::TESTP: return "X86ISD::TESTP";
18404 case X86ISD::TESTM: return "X86ISD::TESTM";
18405 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18406 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18407 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18408 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18409 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18410 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18411 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18412 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18413 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18414 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18415 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18416 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18417 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18418 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18419 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18420 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18421 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18422 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18423 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18424 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18425 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18426 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18427 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18428 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18429 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18430 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18431 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18432 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18433 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18434 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18435 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18436 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18437 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18438 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18439 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18440 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18441 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18442 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18443 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18444 case X86ISD::SAHF: return "X86ISD::SAHF";
18445 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18446 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18447 case X86ISD::FMADD: return "X86ISD::FMADD";
18448 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18449 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18450 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18451 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18452 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18453 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18454 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18455 case X86ISD::XTEST: return "X86ISD::XTEST";
18459 // isLegalAddressingMode - Return true if the addressing mode represented
18460 // by AM is legal for this target, for a load/store of the specified type.
18461 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18463 // X86 supports extremely general addressing modes.
18464 CodeModel::Model M = getTargetMachine().getCodeModel();
18465 Reloc::Model R = getTargetMachine().getRelocationModel();
18467 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18468 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18473 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18475 // If a reference to this global requires an extra load, we can't fold it.
18476 if (isGlobalStubReference(GVFlags))
18479 // If BaseGV requires a register for the PIC base, we cannot also have a
18480 // BaseReg specified.
18481 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18484 // If lower 4G is not available, then we must use rip-relative addressing.
18485 if ((M != CodeModel::Small || R != Reloc::Static) &&
18486 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18490 switch (AM.Scale) {
18496 // These scales always work.
18501 // These scales are formed with basereg+scalereg. Only accept if there is
18506 default: // Other stuff never works.
18513 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18514 unsigned Bits = Ty->getScalarSizeInBits();
18516 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18517 // particularly cheaper than those without.
18521 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18522 // variable shifts just as cheap as scalar ones.
18523 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18526 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18527 // fully general vector.
18531 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18532 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18534 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18535 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18536 return NumBits1 > NumBits2;
18539 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18540 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18543 if (!isTypeLegal(EVT::getEVT(Ty1)))
18546 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18548 // Assuming the caller doesn't have a zeroext or signext return parameter,
18549 // truncation all the way down to i1 is valid.
18553 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18554 return isInt<32>(Imm);
18557 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18558 // Can also use sub to handle negated immediates.
18559 return isInt<32>(Imm);
18562 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18563 if (!VT1.isInteger() || !VT2.isInteger())
18565 unsigned NumBits1 = VT1.getSizeInBits();
18566 unsigned NumBits2 = VT2.getSizeInBits();
18567 return NumBits1 > NumBits2;
18570 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18571 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18572 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18575 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18576 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18577 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18580 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18581 EVT VT1 = Val.getValueType();
18582 if (isZExtFree(VT1, VT2))
18585 if (Val.getOpcode() != ISD::LOAD)
18588 if (!VT1.isSimple() || !VT1.isInteger() ||
18589 !VT2.isSimple() || !VT2.isInteger())
18592 switch (VT1.getSimpleVT().SimpleTy) {
18597 // X86 has 8, 16, and 32-bit zero-extending loads.
18605 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18606 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18609 VT = VT.getScalarType();
18611 if (!VT.isSimple())
18614 switch (VT.getSimpleVT().SimpleTy) {
18625 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18626 // i16 instructions are longer (0x66 prefix) and potentially slower.
18627 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18630 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18631 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18632 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18633 /// are assumed to be legal.
18635 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18637 if (!VT.isSimple())
18640 MVT SVT = VT.getSimpleVT();
18642 // Very little shuffling can be done for 64-bit vectors right now.
18643 if (VT.getSizeInBits() == 64)
18646 // If this is a single-input shuffle with no 128 bit lane crossings we can
18647 // lower it into pshufb.
18648 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
18649 (SVT.is256BitVector() && Subtarget->hasInt256())) {
18650 bool isLegal = true;
18651 for (unsigned I = 0, E = M.size(); I != E; ++I) {
18652 if (M[I] >= (int)SVT.getVectorNumElements() ||
18653 ShuffleCrosses128bitLane(SVT, I, M[I])) {
18662 // FIXME: blends, shifts.
18663 return (SVT.getVectorNumElements() == 2 ||
18664 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
18665 isMOVLMask(M, SVT) ||
18666 isMOVHLPSMask(M, SVT) ||
18667 isSHUFPMask(M, SVT) ||
18668 isPSHUFDMask(M, SVT) ||
18669 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
18670 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
18671 isPALIGNRMask(M, SVT, Subtarget) ||
18672 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
18673 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
18674 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18675 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18676 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
18680 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18682 if (!VT.isSimple())
18685 MVT SVT = VT.getSimpleVT();
18686 unsigned NumElts = SVT.getVectorNumElements();
18687 // FIXME: This collection of masks seems suspect.
18690 if (NumElts == 4 && SVT.is128BitVector()) {
18691 return (isMOVLMask(Mask, SVT) ||
18692 isCommutedMOVLMask(Mask, SVT, true) ||
18693 isSHUFPMask(Mask, SVT) ||
18694 isSHUFPMask(Mask, SVT, /* Commuted */ true));
18699 //===----------------------------------------------------------------------===//
18700 // X86 Scheduler Hooks
18701 //===----------------------------------------------------------------------===//
18703 /// Utility function to emit xbegin specifying the start of an RTM region.
18704 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18705 const TargetInstrInfo *TII) {
18706 DebugLoc DL = MI->getDebugLoc();
18708 const BasicBlock *BB = MBB->getBasicBlock();
18709 MachineFunction::iterator I = MBB;
18712 // For the v = xbegin(), we generate
18723 MachineBasicBlock *thisMBB = MBB;
18724 MachineFunction *MF = MBB->getParent();
18725 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18726 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18727 MF->insert(I, mainMBB);
18728 MF->insert(I, sinkMBB);
18730 // Transfer the remainder of BB and its successor edges to sinkMBB.
18731 sinkMBB->splice(sinkMBB->begin(), MBB,
18732 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18733 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18737 // # fallthrough to mainMBB
18738 // # abortion to sinkMBB
18739 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18740 thisMBB->addSuccessor(mainMBB);
18741 thisMBB->addSuccessor(sinkMBB);
18745 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18746 mainMBB->addSuccessor(sinkMBB);
18749 // EAX is live into the sinkMBB
18750 sinkMBB->addLiveIn(X86::EAX);
18751 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18752 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18755 MI->eraseFromParent();
18759 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18760 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18761 // in the .td file.
18762 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18763 const TargetInstrInfo *TII) {
18765 switch (MI->getOpcode()) {
18766 default: llvm_unreachable("illegal opcode!");
18767 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18768 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18769 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18770 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18771 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18772 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18773 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18774 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18777 DebugLoc dl = MI->getDebugLoc();
18778 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18780 unsigned NumArgs = MI->getNumOperands();
18781 for (unsigned i = 1; i < NumArgs; ++i) {
18782 MachineOperand &Op = MI->getOperand(i);
18783 if (!(Op.isReg() && Op.isImplicit()))
18784 MIB.addOperand(Op);
18786 if (MI->hasOneMemOperand())
18787 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18789 BuildMI(*BB, MI, dl,
18790 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18791 .addReg(X86::XMM0);
18793 MI->eraseFromParent();
18797 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18798 // defs in an instruction pattern
18799 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18800 const TargetInstrInfo *TII) {
18802 switch (MI->getOpcode()) {
18803 default: llvm_unreachable("illegal opcode!");
18804 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18805 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18806 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18807 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18808 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18809 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18810 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18811 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18814 DebugLoc dl = MI->getDebugLoc();
18815 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18817 unsigned NumArgs = MI->getNumOperands(); // remove the results
18818 for (unsigned i = 1; i < NumArgs; ++i) {
18819 MachineOperand &Op = MI->getOperand(i);
18820 if (!(Op.isReg() && Op.isImplicit()))
18821 MIB.addOperand(Op);
18823 if (MI->hasOneMemOperand())
18824 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18826 BuildMI(*BB, MI, dl,
18827 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18830 MI->eraseFromParent();
18834 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18835 const TargetInstrInfo *TII,
18836 const X86Subtarget* Subtarget) {
18837 DebugLoc dl = MI->getDebugLoc();
18839 // Address into RAX/EAX, other two args into ECX, EDX.
18840 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18841 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18842 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18843 for (int i = 0; i < X86::AddrNumOperands; ++i)
18844 MIB.addOperand(MI->getOperand(i));
18846 unsigned ValOps = X86::AddrNumOperands;
18847 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18848 .addReg(MI->getOperand(ValOps).getReg());
18849 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18850 .addReg(MI->getOperand(ValOps+1).getReg());
18852 // The instruction doesn't actually take any operands though.
18853 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18855 MI->eraseFromParent(); // The pseudo is gone now.
18859 MachineBasicBlock *
18860 X86TargetLowering::EmitVAARG64WithCustomInserter(
18862 MachineBasicBlock *MBB) const {
18863 // Emit va_arg instruction on X86-64.
18865 // Operands to this pseudo-instruction:
18866 // 0 ) Output : destination address (reg)
18867 // 1-5) Input : va_list address (addr, i64mem)
18868 // 6 ) ArgSize : Size (in bytes) of vararg type
18869 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18870 // 8 ) Align : Alignment of type
18871 // 9 ) EFLAGS (implicit-def)
18873 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18874 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
18876 unsigned DestReg = MI->getOperand(0).getReg();
18877 MachineOperand &Base = MI->getOperand(1);
18878 MachineOperand &Scale = MI->getOperand(2);
18879 MachineOperand &Index = MI->getOperand(3);
18880 MachineOperand &Disp = MI->getOperand(4);
18881 MachineOperand &Segment = MI->getOperand(5);
18882 unsigned ArgSize = MI->getOperand(6).getImm();
18883 unsigned ArgMode = MI->getOperand(7).getImm();
18884 unsigned Align = MI->getOperand(8).getImm();
18886 // Memory Reference
18887 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18888 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18889 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18891 // Machine Information
18892 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18893 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18894 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18895 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18896 DebugLoc DL = MI->getDebugLoc();
18898 // struct va_list {
18901 // i64 overflow_area (address)
18902 // i64 reg_save_area (address)
18904 // sizeof(va_list) = 24
18905 // alignment(va_list) = 8
18907 unsigned TotalNumIntRegs = 6;
18908 unsigned TotalNumXMMRegs = 8;
18909 bool UseGPOffset = (ArgMode == 1);
18910 bool UseFPOffset = (ArgMode == 2);
18911 unsigned MaxOffset = TotalNumIntRegs * 8 +
18912 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18914 /* Align ArgSize to a multiple of 8 */
18915 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18916 bool NeedsAlign = (Align > 8);
18918 MachineBasicBlock *thisMBB = MBB;
18919 MachineBasicBlock *overflowMBB;
18920 MachineBasicBlock *offsetMBB;
18921 MachineBasicBlock *endMBB;
18923 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18924 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18925 unsigned OffsetReg = 0;
18927 if (!UseGPOffset && !UseFPOffset) {
18928 // If we only pull from the overflow region, we don't create a branch.
18929 // We don't need to alter control flow.
18930 OffsetDestReg = 0; // unused
18931 OverflowDestReg = DestReg;
18933 offsetMBB = nullptr;
18934 overflowMBB = thisMBB;
18937 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18938 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18939 // If not, pull from overflow_area. (branch to overflowMBB)
18944 // offsetMBB overflowMBB
18949 // Registers for the PHI in endMBB
18950 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18951 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18953 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18954 MachineFunction *MF = MBB->getParent();
18955 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18956 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18957 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18959 MachineFunction::iterator MBBIter = MBB;
18962 // Insert the new basic blocks
18963 MF->insert(MBBIter, offsetMBB);
18964 MF->insert(MBBIter, overflowMBB);
18965 MF->insert(MBBIter, endMBB);
18967 // Transfer the remainder of MBB and its successor edges to endMBB.
18968 endMBB->splice(endMBB->begin(), thisMBB,
18969 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18970 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18972 // Make offsetMBB and overflowMBB successors of thisMBB
18973 thisMBB->addSuccessor(offsetMBB);
18974 thisMBB->addSuccessor(overflowMBB);
18976 // endMBB is a successor of both offsetMBB and overflowMBB
18977 offsetMBB->addSuccessor(endMBB);
18978 overflowMBB->addSuccessor(endMBB);
18980 // Load the offset value into a register
18981 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18982 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18986 .addDisp(Disp, UseFPOffset ? 4 : 0)
18987 .addOperand(Segment)
18988 .setMemRefs(MMOBegin, MMOEnd);
18990 // Check if there is enough room left to pull this argument.
18991 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18993 .addImm(MaxOffset + 8 - ArgSizeA8);
18995 // Branch to "overflowMBB" if offset >= max
18996 // Fall through to "offsetMBB" otherwise
18997 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18998 .addMBB(overflowMBB);
19001 // In offsetMBB, emit code to use the reg_save_area.
19003 assert(OffsetReg != 0);
19005 // Read the reg_save_area address.
19006 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19007 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19012 .addOperand(Segment)
19013 .setMemRefs(MMOBegin, MMOEnd);
19015 // Zero-extend the offset
19016 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19017 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19020 .addImm(X86::sub_32bit);
19022 // Add the offset to the reg_save_area to get the final address.
19023 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19024 .addReg(OffsetReg64)
19025 .addReg(RegSaveReg);
19027 // Compute the offset for the next argument
19028 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19029 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19031 .addImm(UseFPOffset ? 16 : 8);
19033 // Store it back into the va_list.
19034 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19038 .addDisp(Disp, UseFPOffset ? 4 : 0)
19039 .addOperand(Segment)
19040 .addReg(NextOffsetReg)
19041 .setMemRefs(MMOBegin, MMOEnd);
19044 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
19049 // Emit code to use overflow area
19052 // Load the overflow_area address into a register.
19053 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19054 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19059 .addOperand(Segment)
19060 .setMemRefs(MMOBegin, MMOEnd);
19062 // If we need to align it, do so. Otherwise, just copy the address
19063 // to OverflowDestReg.
19065 // Align the overflow address
19066 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19067 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19069 // aligned_addr = (addr + (align-1)) & ~(align-1)
19070 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19071 .addReg(OverflowAddrReg)
19074 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19076 .addImm(~(uint64_t)(Align-1));
19078 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19079 .addReg(OverflowAddrReg);
19082 // Compute the next overflow address after this argument.
19083 // (the overflow address should be kept 8-byte aligned)
19084 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19085 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19086 .addReg(OverflowDestReg)
19087 .addImm(ArgSizeA8);
19089 // Store the new overflow address.
19090 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19095 .addOperand(Segment)
19096 .addReg(NextAddrReg)
19097 .setMemRefs(MMOBegin, MMOEnd);
19099 // If we branched, emit the PHI to the front of endMBB.
19101 BuildMI(*endMBB, endMBB->begin(), DL,
19102 TII->get(X86::PHI), DestReg)
19103 .addReg(OffsetDestReg).addMBB(offsetMBB)
19104 .addReg(OverflowDestReg).addMBB(overflowMBB);
19107 // Erase the pseudo instruction
19108 MI->eraseFromParent();
19113 MachineBasicBlock *
19114 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19116 MachineBasicBlock *MBB) const {
19117 // Emit code to save XMM registers to the stack. The ABI says that the
19118 // number of registers to save is given in %al, so it's theoretically
19119 // possible to do an indirect jump trick to avoid saving all of them,
19120 // however this code takes a simpler approach and just executes all
19121 // of the stores if %al is non-zero. It's less code, and it's probably
19122 // easier on the hardware branch predictor, and stores aren't all that
19123 // expensive anyway.
19125 // Create the new basic blocks. One block contains all the XMM stores,
19126 // and one block is the final destination regardless of whether any
19127 // stores were performed.
19128 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19129 MachineFunction *F = MBB->getParent();
19130 MachineFunction::iterator MBBIter = MBB;
19132 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19133 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19134 F->insert(MBBIter, XMMSaveMBB);
19135 F->insert(MBBIter, EndMBB);
19137 // Transfer the remainder of MBB and its successor edges to EndMBB.
19138 EndMBB->splice(EndMBB->begin(), MBB,
19139 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19140 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19142 // The original block will now fall through to the XMM save block.
19143 MBB->addSuccessor(XMMSaveMBB);
19144 // The XMMSaveMBB will fall through to the end block.
19145 XMMSaveMBB->addSuccessor(EndMBB);
19147 // Now add the instructions.
19148 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19149 DebugLoc DL = MI->getDebugLoc();
19151 unsigned CountReg = MI->getOperand(0).getReg();
19152 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19153 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19155 if (!Subtarget->isTargetWin64()) {
19156 // If %al is 0, branch around the XMM save block.
19157 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19158 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
19159 MBB->addSuccessor(EndMBB);
19162 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19163 // that was just emitted, but clearly shouldn't be "saved".
19164 assert((MI->getNumOperands() <= 3 ||
19165 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19166 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19167 && "Expected last argument to be EFLAGS");
19168 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19169 // In the XMM save block, save all the XMM argument registers.
19170 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19171 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19172 MachineMemOperand *MMO =
19173 F->getMachineMemOperand(
19174 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19175 MachineMemOperand::MOStore,
19176 /*Size=*/16, /*Align=*/16);
19177 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19178 .addFrameIndex(RegSaveFrameIndex)
19179 .addImm(/*Scale=*/1)
19180 .addReg(/*IndexReg=*/0)
19181 .addImm(/*Disp=*/Offset)
19182 .addReg(/*Segment=*/0)
19183 .addReg(MI->getOperand(i).getReg())
19184 .addMemOperand(MMO);
19187 MI->eraseFromParent(); // The pseudo instruction is gone now.
19192 // The EFLAGS operand of SelectItr might be missing a kill marker
19193 // because there were multiple uses of EFLAGS, and ISel didn't know
19194 // which to mark. Figure out whether SelectItr should have had a
19195 // kill marker, and set it if it should. Returns the correct kill
19197 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19198 MachineBasicBlock* BB,
19199 const TargetRegisterInfo* TRI) {
19200 // Scan forward through BB for a use/def of EFLAGS.
19201 MachineBasicBlock::iterator miI(std::next(SelectItr));
19202 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19203 const MachineInstr& mi = *miI;
19204 if (mi.readsRegister(X86::EFLAGS))
19206 if (mi.definesRegister(X86::EFLAGS))
19207 break; // Should have kill-flag - update below.
19210 // If we hit the end of the block, check whether EFLAGS is live into a
19212 if (miI == BB->end()) {
19213 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19214 sEnd = BB->succ_end();
19215 sItr != sEnd; ++sItr) {
19216 MachineBasicBlock* succ = *sItr;
19217 if (succ->isLiveIn(X86::EFLAGS))
19222 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19223 // out. SelectMI should have a kill flag on EFLAGS.
19224 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19228 MachineBasicBlock *
19229 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19230 MachineBasicBlock *BB) const {
19231 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19232 DebugLoc DL = MI->getDebugLoc();
19234 // To "insert" a SELECT_CC instruction, we actually have to insert the
19235 // diamond control-flow pattern. The incoming instruction knows the
19236 // destination vreg to set, the condition code register to branch on, the
19237 // true/false values to select between, and a branch opcode to use.
19238 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19239 MachineFunction::iterator It = BB;
19245 // cmpTY ccX, r1, r2
19247 // fallthrough --> copy0MBB
19248 MachineBasicBlock *thisMBB = BB;
19249 MachineFunction *F = BB->getParent();
19250 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19251 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19252 F->insert(It, copy0MBB);
19253 F->insert(It, sinkMBB);
19255 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19256 // live into the sink and copy blocks.
19257 const TargetRegisterInfo *TRI =
19258 BB->getParent()->getSubtarget().getRegisterInfo();
19259 if (!MI->killsRegister(X86::EFLAGS) &&
19260 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19261 copy0MBB->addLiveIn(X86::EFLAGS);
19262 sinkMBB->addLiveIn(X86::EFLAGS);
19265 // Transfer the remainder of BB and its successor edges to sinkMBB.
19266 sinkMBB->splice(sinkMBB->begin(), BB,
19267 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19268 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19270 // Add the true and fallthrough blocks as its successors.
19271 BB->addSuccessor(copy0MBB);
19272 BB->addSuccessor(sinkMBB);
19274 // Create the conditional branch instruction.
19276 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19277 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19280 // %FalseValue = ...
19281 // # fallthrough to sinkMBB
19282 copy0MBB->addSuccessor(sinkMBB);
19285 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19287 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19288 TII->get(X86::PHI), MI->getOperand(0).getReg())
19289 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19290 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19292 MI->eraseFromParent(); // The pseudo instruction is gone now.
19296 MachineBasicBlock *
19297 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19298 MachineBasicBlock *BB) const {
19299 MachineFunction *MF = BB->getParent();
19300 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19301 DebugLoc DL = MI->getDebugLoc();
19302 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19304 assert(MF->shouldSplitStack());
19306 const bool Is64Bit = Subtarget->is64Bit();
19307 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19309 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19310 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19313 // ... [Till the alloca]
19314 // If stacklet is not large enough, jump to mallocMBB
19317 // Allocate by subtracting from RSP
19318 // Jump to continueMBB
19321 // Allocate by call to runtime
19325 // [rest of original BB]
19328 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19329 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19330 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19332 MachineRegisterInfo &MRI = MF->getRegInfo();
19333 const TargetRegisterClass *AddrRegClass =
19334 getRegClassFor(getPointerTy());
19336 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19337 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19338 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19339 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19340 sizeVReg = MI->getOperand(1).getReg(),
19341 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19343 MachineFunction::iterator MBBIter = BB;
19346 MF->insert(MBBIter, bumpMBB);
19347 MF->insert(MBBIter, mallocMBB);
19348 MF->insert(MBBIter, continueMBB);
19350 continueMBB->splice(continueMBB->begin(), BB,
19351 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19352 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19354 // Add code to the main basic block to check if the stack limit has been hit,
19355 // and if so, jump to mallocMBB otherwise to bumpMBB.
19356 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19357 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19358 .addReg(tmpSPVReg).addReg(sizeVReg);
19359 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19360 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19361 .addReg(SPLimitVReg);
19362 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19364 // bumpMBB simply decreases the stack pointer, since we know the current
19365 // stacklet has enough space.
19366 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19367 .addReg(SPLimitVReg);
19368 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19369 .addReg(SPLimitVReg);
19370 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19372 // Calls into a routine in libgcc to allocate more space from the heap.
19373 const uint32_t *RegMask = MF->getTarget()
19374 .getSubtargetImpl()
19375 ->getRegisterInfo()
19376 ->getCallPreservedMask(CallingConv::C);
19378 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19380 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19381 .addExternalSymbol("__morestack_allocate_stack_space")
19382 .addRegMask(RegMask)
19383 .addReg(X86::RDI, RegState::Implicit)
19384 .addReg(X86::RAX, RegState::ImplicitDefine);
19385 } else if (Is64Bit) {
19386 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19388 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19389 .addExternalSymbol("__morestack_allocate_stack_space")
19390 .addRegMask(RegMask)
19391 .addReg(X86::EDI, RegState::Implicit)
19392 .addReg(X86::EAX, RegState::ImplicitDefine);
19394 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19396 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19397 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19398 .addExternalSymbol("__morestack_allocate_stack_space")
19399 .addRegMask(RegMask)
19400 .addReg(X86::EAX, RegState::ImplicitDefine);
19404 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19407 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19408 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19409 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19411 // Set up the CFG correctly.
19412 BB->addSuccessor(bumpMBB);
19413 BB->addSuccessor(mallocMBB);
19414 mallocMBB->addSuccessor(continueMBB);
19415 bumpMBB->addSuccessor(continueMBB);
19417 // Take care of the PHI nodes.
19418 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19419 MI->getOperand(0).getReg())
19420 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19421 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19423 // Delete the original pseudo instruction.
19424 MI->eraseFromParent();
19427 return continueMBB;
19430 MachineBasicBlock *
19431 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19432 MachineBasicBlock *BB) const {
19433 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19434 DebugLoc DL = MI->getDebugLoc();
19436 assert(!Subtarget->isTargetMacho());
19438 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19439 // non-trivial part is impdef of ESP.
19441 if (Subtarget->isTargetWin64()) {
19442 if (Subtarget->isTargetCygMing()) {
19443 // ___chkstk(Mingw64):
19444 // Clobbers R10, R11, RAX and EFLAGS.
19446 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19447 .addExternalSymbol("___chkstk")
19448 .addReg(X86::RAX, RegState::Implicit)
19449 .addReg(X86::RSP, RegState::Implicit)
19450 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19451 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19452 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19454 // __chkstk(MSVCRT): does not update stack pointer.
19455 // Clobbers R10, R11 and EFLAGS.
19456 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19457 .addExternalSymbol("__chkstk")
19458 .addReg(X86::RAX, RegState::Implicit)
19459 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19460 // RAX has the offset to be subtracted from RSP.
19461 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
19466 const char *StackProbeSymbol =
19467 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
19469 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
19470 .addExternalSymbol(StackProbeSymbol)
19471 .addReg(X86::EAX, RegState::Implicit)
19472 .addReg(X86::ESP, RegState::Implicit)
19473 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
19474 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
19475 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19478 MI->eraseFromParent(); // The pseudo instruction is gone now.
19482 MachineBasicBlock *
19483 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19484 MachineBasicBlock *BB) const {
19485 // This is pretty easy. We're taking the value that we received from
19486 // our load from the relocation, sticking it in either RDI (x86-64)
19487 // or EAX and doing an indirect call. The return value will then
19488 // be in the normal return register.
19489 MachineFunction *F = BB->getParent();
19490 const X86InstrInfo *TII =
19491 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
19492 DebugLoc DL = MI->getDebugLoc();
19494 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19495 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19497 // Get a register mask for the lowered call.
19498 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19499 // proper register mask.
19500 const uint32_t *RegMask = F->getTarget()
19501 .getSubtargetImpl()
19502 ->getRegisterInfo()
19503 ->getCallPreservedMask(CallingConv::C);
19504 if (Subtarget->is64Bit()) {
19505 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19506 TII->get(X86::MOV64rm), X86::RDI)
19508 .addImm(0).addReg(0)
19509 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19510 MI->getOperand(3).getTargetFlags())
19512 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19513 addDirectMem(MIB, X86::RDI);
19514 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19515 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19516 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19517 TII->get(X86::MOV32rm), X86::EAX)
19519 .addImm(0).addReg(0)
19520 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19521 MI->getOperand(3).getTargetFlags())
19523 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19524 addDirectMem(MIB, X86::EAX);
19525 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19527 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19528 TII->get(X86::MOV32rm), X86::EAX)
19529 .addReg(TII->getGlobalBaseReg(F))
19530 .addImm(0).addReg(0)
19531 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19532 MI->getOperand(3).getTargetFlags())
19534 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19535 addDirectMem(MIB, X86::EAX);
19536 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19539 MI->eraseFromParent(); // The pseudo instruction is gone now.
19543 MachineBasicBlock *
19544 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19545 MachineBasicBlock *MBB) const {
19546 DebugLoc DL = MI->getDebugLoc();
19547 MachineFunction *MF = MBB->getParent();
19548 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19549 MachineRegisterInfo &MRI = MF->getRegInfo();
19551 const BasicBlock *BB = MBB->getBasicBlock();
19552 MachineFunction::iterator I = MBB;
19555 // Memory Reference
19556 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19557 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19560 unsigned MemOpndSlot = 0;
19562 unsigned CurOp = 0;
19564 DstReg = MI->getOperand(CurOp++).getReg();
19565 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19566 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19567 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19568 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19570 MemOpndSlot = CurOp;
19572 MVT PVT = getPointerTy();
19573 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19574 "Invalid Pointer Size!");
19576 // For v = setjmp(buf), we generate
19579 // buf[LabelOffset] = restoreMBB
19580 // SjLjSetup restoreMBB
19586 // v = phi(main, restore)
19591 MachineBasicBlock *thisMBB = MBB;
19592 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19593 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19594 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19595 MF->insert(I, mainMBB);
19596 MF->insert(I, sinkMBB);
19597 MF->push_back(restoreMBB);
19599 MachineInstrBuilder MIB;
19601 // Transfer the remainder of BB and its successor edges to sinkMBB.
19602 sinkMBB->splice(sinkMBB->begin(), MBB,
19603 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19604 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19607 unsigned PtrStoreOpc = 0;
19608 unsigned LabelReg = 0;
19609 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19610 Reloc::Model RM = MF->getTarget().getRelocationModel();
19611 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19612 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19614 // Prepare IP either in reg or imm.
19615 if (!UseImmLabel) {
19616 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19617 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19618 LabelReg = MRI.createVirtualRegister(PtrRC);
19619 if (Subtarget->is64Bit()) {
19620 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19624 .addMBB(restoreMBB)
19627 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19628 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19629 .addReg(XII->getGlobalBaseReg(MF))
19632 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19636 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19638 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19639 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19640 if (i == X86::AddrDisp)
19641 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19643 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19646 MIB.addReg(LabelReg);
19648 MIB.addMBB(restoreMBB);
19649 MIB.setMemRefs(MMOBegin, MMOEnd);
19651 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19652 .addMBB(restoreMBB);
19654 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19655 MF->getSubtarget().getRegisterInfo());
19656 MIB.addRegMask(RegInfo->getNoPreservedMask());
19657 thisMBB->addSuccessor(mainMBB);
19658 thisMBB->addSuccessor(restoreMBB);
19662 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19663 mainMBB->addSuccessor(sinkMBB);
19666 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19667 TII->get(X86::PHI), DstReg)
19668 .addReg(mainDstReg).addMBB(mainMBB)
19669 .addReg(restoreDstReg).addMBB(restoreMBB);
19672 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19673 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
19674 restoreMBB->addSuccessor(sinkMBB);
19676 MI->eraseFromParent();
19680 MachineBasicBlock *
19681 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19682 MachineBasicBlock *MBB) const {
19683 DebugLoc DL = MI->getDebugLoc();
19684 MachineFunction *MF = MBB->getParent();
19685 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19686 MachineRegisterInfo &MRI = MF->getRegInfo();
19688 // Memory Reference
19689 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19690 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19692 MVT PVT = getPointerTy();
19693 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19694 "Invalid Pointer Size!");
19696 const TargetRegisterClass *RC =
19697 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19698 unsigned Tmp = MRI.createVirtualRegister(RC);
19699 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19700 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19701 MF->getSubtarget().getRegisterInfo());
19702 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19703 unsigned SP = RegInfo->getStackRegister();
19705 MachineInstrBuilder MIB;
19707 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19708 const int64_t SPOffset = 2 * PVT.getStoreSize();
19710 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19711 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19714 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19715 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19716 MIB.addOperand(MI->getOperand(i));
19717 MIB.setMemRefs(MMOBegin, MMOEnd);
19719 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19720 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19721 if (i == X86::AddrDisp)
19722 MIB.addDisp(MI->getOperand(i), LabelOffset);
19724 MIB.addOperand(MI->getOperand(i));
19726 MIB.setMemRefs(MMOBegin, MMOEnd);
19728 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19729 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19730 if (i == X86::AddrDisp)
19731 MIB.addDisp(MI->getOperand(i), SPOffset);
19733 MIB.addOperand(MI->getOperand(i));
19735 MIB.setMemRefs(MMOBegin, MMOEnd);
19737 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19739 MI->eraseFromParent();
19743 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19744 // accumulator loops. Writing back to the accumulator allows the coalescer
19745 // to remove extra copies in the loop.
19746 MachineBasicBlock *
19747 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19748 MachineBasicBlock *MBB) const {
19749 MachineOperand &AddendOp = MI->getOperand(3);
19751 // Bail out early if the addend isn't a register - we can't switch these.
19752 if (!AddendOp.isReg())
19755 MachineFunction &MF = *MBB->getParent();
19756 MachineRegisterInfo &MRI = MF.getRegInfo();
19758 // Check whether the addend is defined by a PHI:
19759 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19760 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19761 if (!AddendDef.isPHI())
19764 // Look for the following pattern:
19766 // %addend = phi [%entry, 0], [%loop, %result]
19768 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19772 // %addend = phi [%entry, 0], [%loop, %result]
19774 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19776 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19777 assert(AddendDef.getOperand(i).isReg());
19778 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19779 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19780 if (&PHISrcInst == MI) {
19781 // Found a matching instruction.
19782 unsigned NewFMAOpc = 0;
19783 switch (MI->getOpcode()) {
19784 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19785 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19786 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19787 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19788 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19789 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19790 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19791 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19792 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19793 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19794 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19795 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19796 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19797 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19798 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19799 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19800 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19801 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19802 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19803 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19804 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19805 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19806 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19807 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19808 default: llvm_unreachable("Unrecognized FMA variant.");
19811 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
19812 MachineInstrBuilder MIB =
19813 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19814 .addOperand(MI->getOperand(0))
19815 .addOperand(MI->getOperand(3))
19816 .addOperand(MI->getOperand(2))
19817 .addOperand(MI->getOperand(1));
19818 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19819 MI->eraseFromParent();
19826 MachineBasicBlock *
19827 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19828 MachineBasicBlock *BB) const {
19829 switch (MI->getOpcode()) {
19830 default: llvm_unreachable("Unexpected instr type to insert");
19831 case X86::TAILJMPd64:
19832 case X86::TAILJMPr64:
19833 case X86::TAILJMPm64:
19834 llvm_unreachable("TAILJMP64 would not be touched here.");
19835 case X86::TCRETURNdi64:
19836 case X86::TCRETURNri64:
19837 case X86::TCRETURNmi64:
19839 case X86::WIN_ALLOCA:
19840 return EmitLoweredWinAlloca(MI, BB);
19841 case X86::SEG_ALLOCA_32:
19842 case X86::SEG_ALLOCA_64:
19843 return EmitLoweredSegAlloca(MI, BB);
19844 case X86::TLSCall_32:
19845 case X86::TLSCall_64:
19846 return EmitLoweredTLSCall(MI, BB);
19847 case X86::CMOV_GR8:
19848 case X86::CMOV_FR32:
19849 case X86::CMOV_FR64:
19850 case X86::CMOV_V4F32:
19851 case X86::CMOV_V2F64:
19852 case X86::CMOV_V2I64:
19853 case X86::CMOV_V8F32:
19854 case X86::CMOV_V4F64:
19855 case X86::CMOV_V4I64:
19856 case X86::CMOV_V16F32:
19857 case X86::CMOV_V8F64:
19858 case X86::CMOV_V8I64:
19859 case X86::CMOV_GR16:
19860 case X86::CMOV_GR32:
19861 case X86::CMOV_RFP32:
19862 case X86::CMOV_RFP64:
19863 case X86::CMOV_RFP80:
19864 return EmitLoweredSelect(MI, BB);
19866 case X86::FP32_TO_INT16_IN_MEM:
19867 case X86::FP32_TO_INT32_IN_MEM:
19868 case X86::FP32_TO_INT64_IN_MEM:
19869 case X86::FP64_TO_INT16_IN_MEM:
19870 case X86::FP64_TO_INT32_IN_MEM:
19871 case X86::FP64_TO_INT64_IN_MEM:
19872 case X86::FP80_TO_INT16_IN_MEM:
19873 case X86::FP80_TO_INT32_IN_MEM:
19874 case X86::FP80_TO_INT64_IN_MEM: {
19875 MachineFunction *F = BB->getParent();
19876 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
19877 DebugLoc DL = MI->getDebugLoc();
19879 // Change the floating point control register to use "round towards zero"
19880 // mode when truncating to an integer value.
19881 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19882 addFrameReference(BuildMI(*BB, MI, DL,
19883 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19885 // Load the old value of the high byte of the control word...
19887 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19888 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19891 // Set the high part to be round to zero...
19892 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19895 // Reload the modified control word now...
19896 addFrameReference(BuildMI(*BB, MI, DL,
19897 TII->get(X86::FLDCW16m)), CWFrameIdx);
19899 // Restore the memory image of control word to original value
19900 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19903 // Get the X86 opcode to use.
19905 switch (MI->getOpcode()) {
19906 default: llvm_unreachable("illegal opcode!");
19907 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19908 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19909 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19910 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19911 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19912 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19913 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19914 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19915 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19919 MachineOperand &Op = MI->getOperand(0);
19921 AM.BaseType = X86AddressMode::RegBase;
19922 AM.Base.Reg = Op.getReg();
19924 AM.BaseType = X86AddressMode::FrameIndexBase;
19925 AM.Base.FrameIndex = Op.getIndex();
19927 Op = MI->getOperand(1);
19929 AM.Scale = Op.getImm();
19930 Op = MI->getOperand(2);
19932 AM.IndexReg = Op.getImm();
19933 Op = MI->getOperand(3);
19934 if (Op.isGlobal()) {
19935 AM.GV = Op.getGlobal();
19937 AM.Disp = Op.getImm();
19939 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19940 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19942 // Reload the original control word now.
19943 addFrameReference(BuildMI(*BB, MI, DL,
19944 TII->get(X86::FLDCW16m)), CWFrameIdx);
19946 MI->eraseFromParent(); // The pseudo instruction is gone now.
19949 // String/text processing lowering.
19950 case X86::PCMPISTRM128REG:
19951 case X86::VPCMPISTRM128REG:
19952 case X86::PCMPISTRM128MEM:
19953 case X86::VPCMPISTRM128MEM:
19954 case X86::PCMPESTRM128REG:
19955 case X86::VPCMPESTRM128REG:
19956 case X86::PCMPESTRM128MEM:
19957 case X86::VPCMPESTRM128MEM:
19958 assert(Subtarget->hasSSE42() &&
19959 "Target must have SSE4.2 or AVX features enabled");
19960 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19962 // String/text processing lowering.
19963 case X86::PCMPISTRIREG:
19964 case X86::VPCMPISTRIREG:
19965 case X86::PCMPISTRIMEM:
19966 case X86::VPCMPISTRIMEM:
19967 case X86::PCMPESTRIREG:
19968 case X86::VPCMPESTRIREG:
19969 case X86::PCMPESTRIMEM:
19970 case X86::VPCMPESTRIMEM:
19971 assert(Subtarget->hasSSE42() &&
19972 "Target must have SSE4.2 or AVX features enabled");
19973 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19975 // Thread synchronization.
19977 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
19982 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19984 case X86::VASTART_SAVE_XMM_REGS:
19985 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19987 case X86::VAARG_64:
19988 return EmitVAARG64WithCustomInserter(MI, BB);
19990 case X86::EH_SjLj_SetJmp32:
19991 case X86::EH_SjLj_SetJmp64:
19992 return emitEHSjLjSetJmp(MI, BB);
19994 case X86::EH_SjLj_LongJmp32:
19995 case X86::EH_SjLj_LongJmp64:
19996 return emitEHSjLjLongJmp(MI, BB);
19998 case TargetOpcode::STACKMAP:
19999 case TargetOpcode::PATCHPOINT:
20000 return emitPatchPoint(MI, BB);
20002 case X86::VFMADDPDr213r:
20003 case X86::VFMADDPSr213r:
20004 case X86::VFMADDSDr213r:
20005 case X86::VFMADDSSr213r:
20006 case X86::VFMSUBPDr213r:
20007 case X86::VFMSUBPSr213r:
20008 case X86::VFMSUBSDr213r:
20009 case X86::VFMSUBSSr213r:
20010 case X86::VFNMADDPDr213r:
20011 case X86::VFNMADDPSr213r:
20012 case X86::VFNMADDSDr213r:
20013 case X86::VFNMADDSSr213r:
20014 case X86::VFNMSUBPDr213r:
20015 case X86::VFNMSUBPSr213r:
20016 case X86::VFNMSUBSDr213r:
20017 case X86::VFNMSUBSSr213r:
20018 case X86::VFMADDPDr213rY:
20019 case X86::VFMADDPSr213rY:
20020 case X86::VFMSUBPDr213rY:
20021 case X86::VFMSUBPSr213rY:
20022 case X86::VFNMADDPDr213rY:
20023 case X86::VFNMADDPSr213rY:
20024 case X86::VFNMSUBPDr213rY:
20025 case X86::VFNMSUBPSr213rY:
20026 return emitFMA3Instr(MI, BB);
20030 //===----------------------------------------------------------------------===//
20031 // X86 Optimization Hooks
20032 //===----------------------------------------------------------------------===//
20034 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20037 const SelectionDAG &DAG,
20038 unsigned Depth) const {
20039 unsigned BitWidth = KnownZero.getBitWidth();
20040 unsigned Opc = Op.getOpcode();
20041 assert((Opc >= ISD::BUILTIN_OP_END ||
20042 Opc == ISD::INTRINSIC_WO_CHAIN ||
20043 Opc == ISD::INTRINSIC_W_CHAIN ||
20044 Opc == ISD::INTRINSIC_VOID) &&
20045 "Should use MaskedValueIsZero if you don't know whether Op"
20046 " is a target node!");
20048 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20062 // These nodes' second result is a boolean.
20063 if (Op.getResNo() == 0)
20066 case X86ISD::SETCC:
20067 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20069 case ISD::INTRINSIC_WO_CHAIN: {
20070 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20071 unsigned NumLoBits = 0;
20074 case Intrinsic::x86_sse_movmsk_ps:
20075 case Intrinsic::x86_avx_movmsk_ps_256:
20076 case Intrinsic::x86_sse2_movmsk_pd:
20077 case Intrinsic::x86_avx_movmsk_pd_256:
20078 case Intrinsic::x86_mmx_pmovmskb:
20079 case Intrinsic::x86_sse2_pmovmskb_128:
20080 case Intrinsic::x86_avx2_pmovmskb: {
20081 // High bits of movmskp{s|d}, pmovmskb are known zero.
20083 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20084 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20085 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20086 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20087 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20088 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20089 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20090 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20092 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20101 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20103 const SelectionDAG &,
20104 unsigned Depth) const {
20105 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20106 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20107 return Op.getValueType().getScalarType().getSizeInBits();
20113 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20114 /// node is a GlobalAddress + offset.
20115 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20116 const GlobalValue* &GA,
20117 int64_t &Offset) const {
20118 if (N->getOpcode() == X86ISD::Wrapper) {
20119 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20120 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20121 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20125 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20128 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20129 /// same as extracting the high 128-bit part of 256-bit vector and then
20130 /// inserting the result into the low part of a new 256-bit vector
20131 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20132 EVT VT = SVOp->getValueType(0);
20133 unsigned NumElems = VT.getVectorNumElements();
20135 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20136 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20137 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20138 SVOp->getMaskElt(j) >= 0)
20144 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20145 /// same as extracting the low 128-bit part of 256-bit vector and then
20146 /// inserting the result into the high part of a new 256-bit vector
20147 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20148 EVT VT = SVOp->getValueType(0);
20149 unsigned NumElems = VT.getVectorNumElements();
20151 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20152 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20153 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20154 SVOp->getMaskElt(j) >= 0)
20160 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20161 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20162 TargetLowering::DAGCombinerInfo &DCI,
20163 const X86Subtarget* Subtarget) {
20165 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20166 SDValue V1 = SVOp->getOperand(0);
20167 SDValue V2 = SVOp->getOperand(1);
20168 EVT VT = SVOp->getValueType(0);
20169 unsigned NumElems = VT.getVectorNumElements();
20171 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20172 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20176 // V UNDEF BUILD_VECTOR UNDEF
20178 // CONCAT_VECTOR CONCAT_VECTOR
20181 // RESULT: V + zero extended
20183 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20184 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20185 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20188 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20191 // To match the shuffle mask, the first half of the mask should
20192 // be exactly the first vector, and all the rest a splat with the
20193 // first element of the second one.
20194 for (unsigned i = 0; i != NumElems/2; ++i)
20195 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20196 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20199 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20200 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20201 if (Ld->hasNUsesOfValue(1, 0)) {
20202 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20203 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20205 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20207 Ld->getPointerInfo(),
20208 Ld->getAlignment(),
20209 false/*isVolatile*/, true/*ReadMem*/,
20210 false/*WriteMem*/);
20212 // Make sure the newly-created LOAD is in the same position as Ld in
20213 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20214 // and update uses of Ld's output chain to use the TokenFactor.
20215 if (Ld->hasAnyUseOfValue(1)) {
20216 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20217 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20218 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20219 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20220 SDValue(ResNode.getNode(), 1));
20223 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20227 // Emit a zeroed vector and insert the desired subvector on its
20229 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20230 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20231 return DCI.CombineTo(N, InsV);
20234 //===--------------------------------------------------------------------===//
20235 // Combine some shuffles into subvector extracts and inserts:
20238 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20239 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20240 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20241 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20242 return DCI.CombineTo(N, InsV);
20245 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20246 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20247 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20248 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20249 return DCI.CombineTo(N, InsV);
20255 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20258 /// This is the leaf of the recursive combinine below. When we have found some
20259 /// chain of single-use x86 shuffle instructions and accumulated the combined
20260 /// shuffle mask represented by them, this will try to pattern match that mask
20261 /// into either a single instruction if there is a special purpose instruction
20262 /// for this operation, or into a PSHUFB instruction which is a fully general
20263 /// instruction but should only be used to replace chains over a certain depth.
20264 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20265 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20266 TargetLowering::DAGCombinerInfo &DCI,
20267 const X86Subtarget *Subtarget) {
20268 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20270 // Find the operand that enters the chain. Note that multiple uses are OK
20271 // here, we're not going to remove the operand we find.
20272 SDValue Input = Op.getOperand(0);
20273 while (Input.getOpcode() == ISD::BITCAST)
20274 Input = Input.getOperand(0);
20276 MVT VT = Input.getSimpleValueType();
20277 MVT RootVT = Root.getSimpleValueType();
20280 // Just remove no-op shuffle masks.
20281 if (Mask.size() == 1) {
20282 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20287 // Use the float domain if the operand type is a floating point type.
20288 bool FloatDomain = VT.isFloatingPoint();
20290 // For floating point shuffles, we don't have free copies in the shuffle
20291 // instructions or the ability to load as part of the instruction, so
20292 // canonicalize their shuffles to UNPCK or MOV variants.
20294 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20295 // vectors because it can have a load folded into it that UNPCK cannot. This
20296 // doesn't preclude something switching to the shorter encoding post-RA.
20298 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20299 bool Lo = Mask.equals(0, 0);
20302 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20303 // is no slower than UNPCKLPD but has the option to fold the input operand
20304 // into even an unaligned memory load.
20305 if (Lo && Subtarget->hasSSE3()) {
20306 Shuffle = X86ISD::MOVDDUP;
20307 ShuffleVT = MVT::v2f64;
20309 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20310 // than the UNPCK variants.
20311 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20312 ShuffleVT = MVT::v4f32;
20314 if (Depth == 1 && Root->getOpcode() == Shuffle)
20315 return false; // Nothing to do!
20316 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20317 DCI.AddToWorklist(Op.getNode());
20318 if (Shuffle == X86ISD::MOVDDUP)
20319 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20321 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20322 DCI.AddToWorklist(Op.getNode());
20323 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20327 if (Subtarget->hasSSE3() &&
20328 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20329 bool Lo = Mask.equals(0, 0, 2, 2);
20330 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20331 MVT ShuffleVT = MVT::v4f32;
20332 if (Depth == 1 && Root->getOpcode() == Shuffle)
20333 return false; // Nothing to do!
20334 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20335 DCI.AddToWorklist(Op.getNode());
20336 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20337 DCI.AddToWorklist(Op.getNode());
20338 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20342 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20343 bool Lo = Mask.equals(0, 0, 1, 1);
20344 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20345 MVT ShuffleVT = MVT::v4f32;
20346 if (Depth == 1 && Root->getOpcode() == Shuffle)
20347 return false; // Nothing to do!
20348 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20349 DCI.AddToWorklist(Op.getNode());
20350 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20351 DCI.AddToWorklist(Op.getNode());
20352 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20358 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20359 // variants as none of these have single-instruction variants that are
20360 // superior to the UNPCK formulation.
20361 if (!FloatDomain &&
20362 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20363 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20364 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20365 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20367 bool Lo = Mask[0] == 0;
20368 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20369 if (Depth == 1 && Root->getOpcode() == Shuffle)
20370 return false; // Nothing to do!
20372 switch (Mask.size()) {
20374 ShuffleVT = MVT::v8i16;
20377 ShuffleVT = MVT::v16i8;
20380 llvm_unreachable("Impossible mask size!");
20382 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20383 DCI.AddToWorklist(Op.getNode());
20384 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20385 DCI.AddToWorklist(Op.getNode());
20386 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20391 // Don't try to re-form single instruction chains under any circumstances now
20392 // that we've done encoding canonicalization for them.
20396 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20397 // can replace them with a single PSHUFB instruction profitably. Intel's
20398 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20399 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20400 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20401 SmallVector<SDValue, 16> PSHUFBMask;
20402 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
20403 int Ratio = 16 / Mask.size();
20404 for (unsigned i = 0; i < 16; ++i) {
20405 if (Mask[i / Ratio] == SM_SentinelUndef) {
20406 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20409 int M = Mask[i / Ratio] != SM_SentinelZero
20410 ? Ratio * Mask[i / Ratio] + i % Ratio
20412 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
20414 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
20415 DCI.AddToWorklist(Op.getNode());
20416 SDValue PSHUFBMaskOp =
20417 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
20418 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20419 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
20420 DCI.AddToWorklist(Op.getNode());
20421 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20426 // Failed to find any combines.
20430 /// \brief Fully generic combining of x86 shuffle instructions.
20432 /// This should be the last combine run over the x86 shuffle instructions. Once
20433 /// they have been fully optimized, this will recursively consider all chains
20434 /// of single-use shuffle instructions, build a generic model of the cumulative
20435 /// shuffle operation, and check for simpler instructions which implement this
20436 /// operation. We use this primarily for two purposes:
20438 /// 1) Collapse generic shuffles to specialized single instructions when
20439 /// equivalent. In most cases, this is just an encoding size win, but
20440 /// sometimes we will collapse multiple generic shuffles into a single
20441 /// special-purpose shuffle.
20442 /// 2) Look for sequences of shuffle instructions with 3 or more total
20443 /// instructions, and replace them with the slightly more expensive SSSE3
20444 /// PSHUFB instruction if available. We do this as the last combining step
20445 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20446 /// a suitable short sequence of other instructions. The PHUFB will either
20447 /// use a register or have to read from memory and so is slightly (but only
20448 /// slightly) more expensive than the other shuffle instructions.
20450 /// Because this is inherently a quadratic operation (for each shuffle in
20451 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20452 /// This should never be an issue in practice as the shuffle lowering doesn't
20453 /// produce sequences of more than 8 instructions.
20455 /// FIXME: We will currently miss some cases where the redundant shuffling
20456 /// would simplify under the threshold for PSHUFB formation because of
20457 /// combine-ordering. To fix this, we should do the redundant instruction
20458 /// combining in this recursive walk.
20459 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20460 ArrayRef<int> RootMask,
20461 int Depth, bool HasPSHUFB,
20463 TargetLowering::DAGCombinerInfo &DCI,
20464 const X86Subtarget *Subtarget) {
20465 // Bound the depth of our recursive combine because this is ultimately
20466 // quadratic in nature.
20470 // Directly rip through bitcasts to find the underlying operand.
20471 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20472 Op = Op.getOperand(0);
20474 MVT VT = Op.getSimpleValueType();
20475 if (!VT.isVector())
20476 return false; // Bail if we hit a non-vector.
20477 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
20478 // version should be added.
20479 if (VT.getSizeInBits() != 128)
20482 assert(Root.getSimpleValueType().isVector() &&
20483 "Shuffles operate on vector types!");
20484 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20485 "Can only combine shuffles of the same vector register size.");
20487 if (!isTargetShuffle(Op.getOpcode()))
20489 SmallVector<int, 16> OpMask;
20491 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20492 // We only can combine unary shuffles which we can decode the mask for.
20493 if (!HaveMask || !IsUnary)
20496 assert(VT.getVectorNumElements() == OpMask.size() &&
20497 "Different mask size from vector size!");
20498 assert(((RootMask.size() > OpMask.size() &&
20499 RootMask.size() % OpMask.size() == 0) ||
20500 (OpMask.size() > RootMask.size() &&
20501 OpMask.size() % RootMask.size() == 0) ||
20502 OpMask.size() == RootMask.size()) &&
20503 "The smaller number of elements must divide the larger.");
20504 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20505 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20506 assert(((RootRatio == 1 && OpRatio == 1) ||
20507 (RootRatio == 1) != (OpRatio == 1)) &&
20508 "Must not have a ratio for both incoming and op masks!");
20510 SmallVector<int, 16> Mask;
20511 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20513 // Merge this shuffle operation's mask into our accumulated mask. Note that
20514 // this shuffle's mask will be the first applied to the input, followed by the
20515 // root mask to get us all the way to the root value arrangement. The reason
20516 // for this order is that we are recursing up the operation chain.
20517 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20518 int RootIdx = i / RootRatio;
20519 if (RootMask[RootIdx] < 0) {
20520 // This is a zero or undef lane, we're done.
20521 Mask.push_back(RootMask[RootIdx]);
20525 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20526 int OpIdx = RootMaskedIdx / OpRatio;
20527 if (OpMask[OpIdx] < 0) {
20528 // The incoming lanes are zero or undef, it doesn't matter which ones we
20530 Mask.push_back(OpMask[OpIdx]);
20534 // Ok, we have non-zero lanes, map them through.
20535 Mask.push_back(OpMask[OpIdx] * OpRatio +
20536 RootMaskedIdx % OpRatio);
20539 // See if we can recurse into the operand to combine more things.
20540 switch (Op.getOpcode()) {
20541 case X86ISD::PSHUFB:
20543 case X86ISD::PSHUFD:
20544 case X86ISD::PSHUFHW:
20545 case X86ISD::PSHUFLW:
20546 if (Op.getOperand(0).hasOneUse() &&
20547 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20548 HasPSHUFB, DAG, DCI, Subtarget))
20552 case X86ISD::UNPCKL:
20553 case X86ISD::UNPCKH:
20554 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20555 // We can't check for single use, we have to check that this shuffle is the only user.
20556 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20557 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20558 HasPSHUFB, DAG, DCI, Subtarget))
20563 // Minor canonicalization of the accumulated shuffle mask to make it easier
20564 // to match below. All this does is detect masks with squential pairs of
20565 // elements, and shrink them to the half-width mask. It does this in a loop
20566 // so it will reduce the size of the mask to the minimal width mask which
20567 // performs an equivalent shuffle.
20568 while (Mask.size() > 1 && canWidenShuffleElements(Mask)) {
20569 for (int i = 0, e = Mask.size() / 2; i < e; ++i)
20570 Mask[i] = Mask[2 * i] / 2;
20571 Mask.resize(Mask.size() / 2);
20574 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20578 /// \brief Get the PSHUF-style mask from PSHUF node.
20580 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20581 /// PSHUF-style masks that can be reused with such instructions.
20582 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20583 SmallVector<int, 4> Mask;
20585 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
20589 switch (N.getOpcode()) {
20590 case X86ISD::PSHUFD:
20592 case X86ISD::PSHUFLW:
20595 case X86ISD::PSHUFHW:
20596 Mask.erase(Mask.begin(), Mask.begin() + 4);
20597 for (int &M : Mask)
20601 llvm_unreachable("No valid shuffle instruction found!");
20605 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20607 /// We walk up the chain and look for a combinable shuffle, skipping over
20608 /// shuffles that we could hoist this shuffle's transformation past without
20609 /// altering anything.
20611 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20613 TargetLowering::DAGCombinerInfo &DCI) {
20614 assert(N.getOpcode() == X86ISD::PSHUFD &&
20615 "Called with something other than an x86 128-bit half shuffle!");
20618 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20619 // of the shuffles in the chain so that we can form a fresh chain to replace
20621 SmallVector<SDValue, 8> Chain;
20622 SDValue V = N.getOperand(0);
20623 for (; V.hasOneUse(); V = V.getOperand(0)) {
20624 switch (V.getOpcode()) {
20626 return SDValue(); // Nothing combined!
20629 // Skip bitcasts as we always know the type for the target specific
20633 case X86ISD::PSHUFD:
20634 // Found another dword shuffle.
20637 case X86ISD::PSHUFLW:
20638 // Check that the low words (being shuffled) are the identity in the
20639 // dword shuffle, and the high words are self-contained.
20640 if (Mask[0] != 0 || Mask[1] != 1 ||
20641 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20644 Chain.push_back(V);
20647 case X86ISD::PSHUFHW:
20648 // Check that the high words (being shuffled) are the identity in the
20649 // dword shuffle, and the low words are self-contained.
20650 if (Mask[2] != 2 || Mask[3] != 3 ||
20651 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20654 Chain.push_back(V);
20657 case X86ISD::UNPCKL:
20658 case X86ISD::UNPCKH:
20659 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20660 // shuffle into a preceding word shuffle.
20661 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
20664 // Search for a half-shuffle which we can combine with.
20665 unsigned CombineOp =
20666 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20667 if (V.getOperand(0) != V.getOperand(1) ||
20668 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20670 Chain.push_back(V);
20671 V = V.getOperand(0);
20673 switch (V.getOpcode()) {
20675 return SDValue(); // Nothing to combine.
20677 case X86ISD::PSHUFLW:
20678 case X86ISD::PSHUFHW:
20679 if (V.getOpcode() == CombineOp)
20682 Chain.push_back(V);
20686 V = V.getOperand(0);
20690 } while (V.hasOneUse());
20693 // Break out of the loop if we break out of the switch.
20697 if (!V.hasOneUse())
20698 // We fell out of the loop without finding a viable combining instruction.
20701 // Merge this node's mask and our incoming mask.
20702 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20703 for (int &M : Mask)
20705 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20706 getV4X86ShuffleImm8ForMask(Mask, DAG));
20708 // Rebuild the chain around this new shuffle.
20709 while (!Chain.empty()) {
20710 SDValue W = Chain.pop_back_val();
20712 if (V.getValueType() != W.getOperand(0).getValueType())
20713 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20715 switch (W.getOpcode()) {
20717 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20719 case X86ISD::UNPCKL:
20720 case X86ISD::UNPCKH:
20721 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20724 case X86ISD::PSHUFD:
20725 case X86ISD::PSHUFLW:
20726 case X86ISD::PSHUFHW:
20727 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20731 if (V.getValueType() != N.getValueType())
20732 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20734 // Return the new chain to replace N.
20738 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20740 /// We walk up the chain, skipping shuffles of the other half and looking
20741 /// through shuffles which switch halves trying to find a shuffle of the same
20742 /// pair of dwords.
20743 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20745 TargetLowering::DAGCombinerInfo &DCI) {
20747 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20748 "Called with something other than an x86 128-bit half shuffle!");
20750 unsigned CombineOpcode = N.getOpcode();
20752 // Walk up a single-use chain looking for a combinable shuffle.
20753 SDValue V = N.getOperand(0);
20754 for (; V.hasOneUse(); V = V.getOperand(0)) {
20755 switch (V.getOpcode()) {
20757 return false; // Nothing combined!
20760 // Skip bitcasts as we always know the type for the target specific
20764 case X86ISD::PSHUFLW:
20765 case X86ISD::PSHUFHW:
20766 if (V.getOpcode() == CombineOpcode)
20769 // Other-half shuffles are no-ops.
20772 // Break out of the loop if we break out of the switch.
20776 if (!V.hasOneUse())
20777 // We fell out of the loop without finding a viable combining instruction.
20780 // Combine away the bottom node as its shuffle will be accumulated into
20781 // a preceding shuffle.
20782 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20784 // Record the old value.
20787 // Merge this node's mask and our incoming mask (adjusted to account for all
20788 // the pshufd instructions encountered).
20789 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20790 for (int &M : Mask)
20792 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20793 getV4X86ShuffleImm8ForMask(Mask, DAG));
20795 // Check that the shuffles didn't cancel each other out. If not, we need to
20796 // combine to the new one.
20798 // Replace the combinable shuffle with the combined one, updating all users
20799 // so that we re-evaluate the chain here.
20800 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20805 /// \brief Try to combine x86 target specific shuffles.
20806 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20807 TargetLowering::DAGCombinerInfo &DCI,
20808 const X86Subtarget *Subtarget) {
20810 MVT VT = N.getSimpleValueType();
20811 SmallVector<int, 4> Mask;
20813 switch (N.getOpcode()) {
20814 case X86ISD::PSHUFD:
20815 case X86ISD::PSHUFLW:
20816 case X86ISD::PSHUFHW:
20817 Mask = getPSHUFShuffleMask(N);
20818 assert(Mask.size() == 4);
20824 // Nuke no-op shuffles that show up after combining.
20825 if (isNoopShuffleMask(Mask))
20826 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20828 // Look for simplifications involving one or two shuffle instructions.
20829 SDValue V = N.getOperand(0);
20830 switch (N.getOpcode()) {
20833 case X86ISD::PSHUFLW:
20834 case X86ISD::PSHUFHW:
20835 assert(VT == MVT::v8i16);
20838 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20839 return SDValue(); // We combined away this shuffle, so we're done.
20841 // See if this reduces to a PSHUFD which is no more expensive and can
20842 // combine with more operations.
20843 if (canWidenShuffleElements(Mask)) {
20844 int DMask[] = {-1, -1, -1, -1};
20845 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20846 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
20847 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
20848 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
20849 DCI.AddToWorklist(V.getNode());
20850 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
20851 getV4X86ShuffleImm8ForMask(DMask, DAG));
20852 DCI.AddToWorklist(V.getNode());
20853 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
20856 // Look for shuffle patterns which can be implemented as a single unpack.
20857 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20858 // only works when we have a PSHUFD followed by two half-shuffles.
20859 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20860 (V.getOpcode() == X86ISD::PSHUFLW ||
20861 V.getOpcode() == X86ISD::PSHUFHW) &&
20862 V.getOpcode() != N.getOpcode() &&
20864 SDValue D = V.getOperand(0);
20865 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20866 D = D.getOperand(0);
20867 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20868 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20869 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20870 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20871 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20873 for (int i = 0; i < 4; ++i) {
20874 WordMask[i + NOffset] = Mask[i] + NOffset;
20875 WordMask[i + VOffset] = VMask[i] + VOffset;
20877 // Map the word mask through the DWord mask.
20879 for (int i = 0; i < 8; ++i)
20880 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20881 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
20882 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
20883 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
20884 std::begin(UnpackLoMask)) ||
20885 std::equal(std::begin(MappedMask), std::end(MappedMask),
20886 std::begin(UnpackHiMask))) {
20887 // We can replace all three shuffles with an unpack.
20888 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
20889 DCI.AddToWorklist(V.getNode());
20890 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20892 DL, MVT::v8i16, V, V);
20899 case X86ISD::PSHUFD:
20900 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20909 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20911 /// We combine this directly on the abstract vector shuffle nodes so it is
20912 /// easier to generically match. We also insert dummy vector shuffle nodes for
20913 /// the operands which explicitly discard the lanes which are unused by this
20914 /// operation to try to flow through the rest of the combiner the fact that
20915 /// they're unused.
20916 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20918 EVT VT = N->getValueType(0);
20920 // We only handle target-independent shuffles.
20921 // FIXME: It would be easy and harmless to use the target shuffle mask
20922 // extraction tool to support more.
20923 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20926 auto *SVN = cast<ShuffleVectorSDNode>(N);
20927 ArrayRef<int> Mask = SVN->getMask();
20928 SDValue V1 = N->getOperand(0);
20929 SDValue V2 = N->getOperand(1);
20931 // We require the first shuffle operand to be the SUB node, and the second to
20932 // be the ADD node.
20933 // FIXME: We should support the commuted patterns.
20934 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20937 // If there are other uses of these operations we can't fold them.
20938 if (!V1->hasOneUse() || !V2->hasOneUse())
20941 // Ensure that both operations have the same operands. Note that we can
20942 // commute the FADD operands.
20943 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20944 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20945 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20948 // We're looking for blends between FADD and FSUB nodes. We insist on these
20949 // nodes being lined up in a specific expected pattern.
20950 if (!(isShuffleEquivalent(Mask, 0, 3) ||
20951 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
20952 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
20955 // Only specific types are legal at this point, assert so we notice if and
20956 // when these change.
20957 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20958 VT == MVT::v4f64) &&
20959 "Unknown vector type encountered!");
20961 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20964 /// PerformShuffleCombine - Performs several different shuffle combines.
20965 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20966 TargetLowering::DAGCombinerInfo &DCI,
20967 const X86Subtarget *Subtarget) {
20969 SDValue N0 = N->getOperand(0);
20970 SDValue N1 = N->getOperand(1);
20971 EVT VT = N->getValueType(0);
20973 // Don't create instructions with illegal types after legalize types has run.
20974 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20975 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20978 // If we have legalized the vector types, look for blends of FADD and FSUB
20979 // nodes that we can fuse into an ADDSUB node.
20980 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20981 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20984 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20985 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20986 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20987 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20989 // During Type Legalization, when promoting illegal vector types,
20990 // the backend might introduce new shuffle dag nodes and bitcasts.
20992 // This code performs the following transformation:
20993 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20994 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20996 // We do this only if both the bitcast and the BINOP dag nodes have
20997 // one use. Also, perform this transformation only if the new binary
20998 // operation is legal. This is to avoid introducing dag nodes that
20999 // potentially need to be further expanded (or custom lowered) into a
21000 // less optimal sequence of dag nodes.
21001 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21002 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21003 N0.getOpcode() == ISD::BITCAST) {
21004 SDValue BC0 = N0.getOperand(0);
21005 EVT SVT = BC0.getValueType();
21006 unsigned Opcode = BC0.getOpcode();
21007 unsigned NumElts = VT.getVectorNumElements();
21009 if (BC0.hasOneUse() && SVT.isVector() &&
21010 SVT.getVectorNumElements() * 2 == NumElts &&
21011 TLI.isOperationLegal(Opcode, VT)) {
21012 bool CanFold = false;
21024 unsigned SVTNumElts = SVT.getVectorNumElements();
21025 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21026 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21027 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21028 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21029 CanFold = SVOp->getMaskElt(i) < 0;
21032 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
21033 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
21034 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21035 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21040 // Only handle 128 wide vector from here on.
21041 if (!VT.is128BitVector())
21044 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21045 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21046 // consecutive, non-overlapping, and in the right order.
21047 SmallVector<SDValue, 16> Elts;
21048 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21049 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21051 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21055 if (isTargetShuffle(N->getOpcode())) {
21057 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21058 if (Shuffle.getNode())
21061 // Try recursively combining arbitrary sequences of x86 shuffle
21062 // instructions into higher-order shuffles. We do this after combining
21063 // specific PSHUF instruction sequences into their minimal form so that we
21064 // can evaluate how many specialized shuffle instructions are involved in
21065 // a particular chain.
21066 SmallVector<int, 1> NonceMask; // Just a placeholder.
21067 NonceMask.push_back(0);
21068 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21069 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21071 return SDValue(); // This routine will use CombineTo to replace N.
21077 /// PerformTruncateCombine - Converts truncate operation to
21078 /// a sequence of vector shuffle operations.
21079 /// It is possible when we truncate 256-bit vector to 128-bit vector
21080 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
21081 TargetLowering::DAGCombinerInfo &DCI,
21082 const X86Subtarget *Subtarget) {
21086 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21087 /// specific shuffle of a load can be folded into a single element load.
21088 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21089 /// shuffles have been customed lowered so we need to handle those here.
21090 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21091 TargetLowering::DAGCombinerInfo &DCI) {
21092 if (DCI.isBeforeLegalizeOps())
21095 SDValue InVec = N->getOperand(0);
21096 SDValue EltNo = N->getOperand(1);
21098 if (!isa<ConstantSDNode>(EltNo))
21101 EVT VT = InVec.getValueType();
21103 if (InVec.getOpcode() == ISD::BITCAST) {
21104 // Don't duplicate a load with other uses.
21105 if (!InVec.hasOneUse())
21107 EVT BCVT = InVec.getOperand(0).getValueType();
21108 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
21110 InVec = InVec.getOperand(0);
21113 if (!isTargetShuffle(InVec.getOpcode()))
21116 // Don't duplicate a load with other uses.
21117 if (!InVec.hasOneUse())
21120 SmallVector<int, 16> ShuffleMask;
21122 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
21126 // Select the input vector, guarding against out of range extract vector.
21127 unsigned NumElems = VT.getVectorNumElements();
21128 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21129 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21130 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21131 : InVec.getOperand(1);
21133 // If inputs to shuffle are the same for both ops, then allow 2 uses
21134 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21136 if (LdNode.getOpcode() == ISD::BITCAST) {
21137 // Don't duplicate a load with other uses.
21138 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21141 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21142 LdNode = LdNode.getOperand(0);
21145 if (!ISD::isNormalLoad(LdNode.getNode()))
21148 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21150 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21153 EVT EltVT = N->getValueType(0);
21154 // If there's a bitcast before the shuffle, check if the load type and
21155 // alignment is valid.
21156 unsigned Align = LN0->getAlignment();
21157 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21158 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21159 EltVT.getTypeForEVT(*DAG.getContext()));
21161 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21164 // All checks match so transform back to vector_shuffle so that DAG combiner
21165 // can finish the job
21168 // Create shuffle node taking into account the case that its a unary shuffle
21169 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
21170 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
21171 InVec.getOperand(0), Shuffle,
21173 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
21174 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21178 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21179 /// generation and convert it from being a bunch of shuffles and extracts
21180 /// to a simple store and scalar loads to extract the elements.
21181 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21182 TargetLowering::DAGCombinerInfo &DCI) {
21183 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21184 if (NewOp.getNode())
21187 SDValue InputVector = N->getOperand(0);
21189 // Detect whether we are trying to convert from mmx to i32 and the bitcast
21190 // from mmx to v2i32 has a single usage.
21191 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
21192 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
21193 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
21194 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21195 N->getValueType(0),
21196 InputVector.getNode()->getOperand(0));
21198 // Only operate on vectors of 4 elements, where the alternative shuffling
21199 // gets to be more expensive.
21200 if (InputVector.getValueType() != MVT::v4i32)
21203 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21204 // single use which is a sign-extend or zero-extend, and all elements are
21206 SmallVector<SDNode *, 4> Uses;
21207 unsigned ExtractedElements = 0;
21208 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21209 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21210 if (UI.getUse().getResNo() != InputVector.getResNo())
21213 SDNode *Extract = *UI;
21214 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21217 if (Extract->getValueType(0) != MVT::i32)
21219 if (!Extract->hasOneUse())
21221 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21222 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21224 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21227 // Record which element was extracted.
21228 ExtractedElements |=
21229 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21231 Uses.push_back(Extract);
21234 // If not all the elements were used, this may not be worthwhile.
21235 if (ExtractedElements != 15)
21238 // Ok, we've now decided to do the transformation.
21239 SDLoc dl(InputVector);
21241 // Store the value to a temporary stack slot.
21242 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21243 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21244 MachinePointerInfo(), false, false, 0);
21246 // Replace each use (extract) with a load of the appropriate element.
21247 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21248 UE = Uses.end(); UI != UE; ++UI) {
21249 SDNode *Extract = *UI;
21251 // cOMpute the element's address.
21252 SDValue Idx = Extract->getOperand(1);
21254 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21255 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21256 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21257 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21259 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21260 StackPtr, OffsetVal);
21262 // Load the scalar.
21263 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21264 ScalarAddr, MachinePointerInfo(),
21265 false, false, false, 0);
21267 // Replace the exact with the load.
21268 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21271 // The replacement was made in place; don't return anything.
21275 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21276 static std::pair<unsigned, bool>
21277 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21278 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21279 if (!VT.isVector())
21280 return std::make_pair(0, false);
21282 bool NeedSplit = false;
21283 switch (VT.getSimpleVT().SimpleTy) {
21284 default: return std::make_pair(0, false);
21288 if (!Subtarget->hasAVX2())
21290 if (!Subtarget->hasAVX())
21291 return std::make_pair(0, false);
21296 if (!Subtarget->hasSSE2())
21297 return std::make_pair(0, false);
21300 // SSE2 has only a small subset of the operations.
21301 bool hasUnsigned = Subtarget->hasSSE41() ||
21302 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21303 bool hasSigned = Subtarget->hasSSE41() ||
21304 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21306 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21309 // Check for x CC y ? x : y.
21310 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21311 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21316 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21319 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21322 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21325 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21327 // Check for x CC y ? y : x -- a min/max with reversed arms.
21328 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21329 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21334 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21337 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21340 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21343 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21347 return std::make_pair(Opc, NeedSplit);
21351 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21352 const X86Subtarget *Subtarget) {
21354 SDValue Cond = N->getOperand(0);
21355 SDValue LHS = N->getOperand(1);
21356 SDValue RHS = N->getOperand(2);
21358 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21359 SDValue CondSrc = Cond->getOperand(0);
21360 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21361 Cond = CondSrc->getOperand(0);
21364 MVT VT = N->getSimpleValueType(0);
21365 MVT EltVT = VT.getVectorElementType();
21366 unsigned NumElems = VT.getVectorNumElements();
21367 // There is no blend with immediate in AVX-512.
21368 if (VT.is512BitVector())
21371 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21373 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21376 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21379 // A vselect where all conditions and data are constants can be optimized into
21380 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21381 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21382 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21385 unsigned MaskValue = 0;
21386 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21389 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21390 for (unsigned i = 0; i < NumElems; ++i) {
21391 // Be sure we emit undef where we can.
21392 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21393 ShuffleMask[i] = -1;
21395 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21398 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21401 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21403 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21404 TargetLowering::DAGCombinerInfo &DCI,
21405 const X86Subtarget *Subtarget) {
21407 SDValue Cond = N->getOperand(0);
21408 // Get the LHS/RHS of the select.
21409 SDValue LHS = N->getOperand(1);
21410 SDValue RHS = N->getOperand(2);
21411 EVT VT = LHS.getValueType();
21412 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21414 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21415 // instructions match the semantics of the common C idiom x<y?x:y but not
21416 // x<=y?x:y, because of how they handle negative zero (which can be
21417 // ignored in unsafe-math mode).
21418 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21419 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
21420 (Subtarget->hasSSE2() ||
21421 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21422 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21424 unsigned Opcode = 0;
21425 // Check for x CC y ? x : y.
21426 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21427 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21431 // Converting this to a min would handle NaNs incorrectly, and swapping
21432 // the operands would cause it to handle comparisons between positive
21433 // and negative zero incorrectly.
21434 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21435 if (!DAG.getTarget().Options.UnsafeFPMath &&
21436 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21438 std::swap(LHS, RHS);
21440 Opcode = X86ISD::FMIN;
21443 // Converting this to a min would handle comparisons between positive
21444 // and negative zero incorrectly.
21445 if (!DAG.getTarget().Options.UnsafeFPMath &&
21446 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21448 Opcode = X86ISD::FMIN;
21451 // Converting this to a min would handle both negative zeros and NaNs
21452 // incorrectly, but we can swap the operands to fix both.
21453 std::swap(LHS, RHS);
21457 Opcode = X86ISD::FMIN;
21461 // Converting this to a max would handle comparisons between positive
21462 // and negative zero incorrectly.
21463 if (!DAG.getTarget().Options.UnsafeFPMath &&
21464 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21466 Opcode = X86ISD::FMAX;
21469 // Converting this to a max would handle NaNs incorrectly, and swapping
21470 // the operands would cause it to handle comparisons between positive
21471 // and negative zero incorrectly.
21472 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21473 if (!DAG.getTarget().Options.UnsafeFPMath &&
21474 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21476 std::swap(LHS, RHS);
21478 Opcode = X86ISD::FMAX;
21481 // Converting this to a max would handle both negative zeros and NaNs
21482 // incorrectly, but we can swap the operands to fix both.
21483 std::swap(LHS, RHS);
21487 Opcode = X86ISD::FMAX;
21490 // Check for x CC y ? y : x -- a min/max with reversed arms.
21491 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21492 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21496 // Converting this to a min would handle comparisons between positive
21497 // and negative zero incorrectly, and swapping the operands would
21498 // cause it to handle NaNs incorrectly.
21499 if (!DAG.getTarget().Options.UnsafeFPMath &&
21500 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21501 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21503 std::swap(LHS, RHS);
21505 Opcode = X86ISD::FMIN;
21508 // Converting this to a min would handle NaNs incorrectly.
21509 if (!DAG.getTarget().Options.UnsafeFPMath &&
21510 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21512 Opcode = X86ISD::FMIN;
21515 // Converting this to a min would handle both negative zeros and NaNs
21516 // incorrectly, but we can swap the operands to fix both.
21517 std::swap(LHS, RHS);
21521 Opcode = X86ISD::FMIN;
21525 // Converting this to a max would handle NaNs incorrectly.
21526 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21528 Opcode = X86ISD::FMAX;
21531 // Converting this to a max would handle comparisons between positive
21532 // and negative zero incorrectly, and swapping the operands would
21533 // cause it to handle NaNs incorrectly.
21534 if (!DAG.getTarget().Options.UnsafeFPMath &&
21535 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21536 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21538 std::swap(LHS, RHS);
21540 Opcode = X86ISD::FMAX;
21543 // Converting this to a max would handle both negative zeros and NaNs
21544 // incorrectly, but we can swap the operands to fix both.
21545 std::swap(LHS, RHS);
21549 Opcode = X86ISD::FMAX;
21555 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21558 EVT CondVT = Cond.getValueType();
21559 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21560 CondVT.getVectorElementType() == MVT::i1) {
21561 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21562 // lowering on KNL. In this case we convert it to
21563 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21564 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21565 // Since SKX these selects have a proper lowering.
21566 EVT OpVT = LHS.getValueType();
21567 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21568 (OpVT.getVectorElementType() == MVT::i8 ||
21569 OpVT.getVectorElementType() == MVT::i16) &&
21570 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21571 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21572 DCI.AddToWorklist(Cond.getNode());
21573 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21576 // If this is a select between two integer constants, try to do some
21578 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21579 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21580 // Don't do this for crazy integer types.
21581 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21582 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21583 // so that TrueC (the true value) is larger than FalseC.
21584 bool NeedsCondInvert = false;
21586 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21587 // Efficiently invertible.
21588 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21589 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21590 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21591 NeedsCondInvert = true;
21592 std::swap(TrueC, FalseC);
21595 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21596 if (FalseC->getAPIntValue() == 0 &&
21597 TrueC->getAPIntValue().isPowerOf2()) {
21598 if (NeedsCondInvert) // Invert the condition if needed.
21599 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21600 DAG.getConstant(1, Cond.getValueType()));
21602 // Zero extend the condition if needed.
21603 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21605 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21606 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21607 DAG.getConstant(ShAmt, MVT::i8));
21610 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21611 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21612 if (NeedsCondInvert) // Invert the condition if needed.
21613 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21614 DAG.getConstant(1, Cond.getValueType()));
21616 // Zero extend the condition if needed.
21617 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21618 FalseC->getValueType(0), Cond);
21619 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21620 SDValue(FalseC, 0));
21623 // Optimize cases that will turn into an LEA instruction. This requires
21624 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21625 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21626 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21627 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21629 bool isFastMultiplier = false;
21631 switch ((unsigned char)Diff) {
21633 case 1: // result = add base, cond
21634 case 2: // result = lea base( , cond*2)
21635 case 3: // result = lea base(cond, cond*2)
21636 case 4: // result = lea base( , cond*4)
21637 case 5: // result = lea base(cond, cond*4)
21638 case 8: // result = lea base( , cond*8)
21639 case 9: // result = lea base(cond, cond*8)
21640 isFastMultiplier = true;
21645 if (isFastMultiplier) {
21646 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21647 if (NeedsCondInvert) // Invert the condition if needed.
21648 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21649 DAG.getConstant(1, Cond.getValueType()));
21651 // Zero extend the condition if needed.
21652 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21654 // Scale the condition by the difference.
21656 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21657 DAG.getConstant(Diff, Cond.getValueType()));
21659 // Add the base if non-zero.
21660 if (FalseC->getAPIntValue() != 0)
21661 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21662 SDValue(FalseC, 0));
21669 // Canonicalize max and min:
21670 // (x > y) ? x : y -> (x >= y) ? x : y
21671 // (x < y) ? x : y -> (x <= y) ? x : y
21672 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21673 // the need for an extra compare
21674 // against zero. e.g.
21675 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21677 // testl %edi, %edi
21679 // cmovgl %edi, %eax
21683 // cmovsl %eax, %edi
21684 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21685 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21686 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21687 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21692 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21693 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21694 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21695 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21700 // Early exit check
21701 if (!TLI.isTypeLegal(VT))
21704 // Match VSELECTs into subs with unsigned saturation.
21705 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21706 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21707 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21708 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21709 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21711 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21712 // left side invert the predicate to simplify logic below.
21714 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21716 CC = ISD::getSetCCInverse(CC, true);
21717 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21721 if (Other.getNode() && Other->getNumOperands() == 2 &&
21722 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21723 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21724 SDValue CondRHS = Cond->getOperand(1);
21726 // Look for a general sub with unsigned saturation first.
21727 // x >= y ? x-y : 0 --> subus x, y
21728 // x > y ? x-y : 0 --> subus x, y
21729 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21730 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21731 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21733 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21734 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21735 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21736 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21737 // If the RHS is a constant we have to reverse the const
21738 // canonicalization.
21739 // x > C-1 ? x+-C : 0 --> subus x, C
21740 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21741 CondRHSConst->getAPIntValue() ==
21742 (-OpRHSConst->getAPIntValue() - 1))
21743 return DAG.getNode(
21744 X86ISD::SUBUS, DL, VT, OpLHS,
21745 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
21747 // Another special case: If C was a sign bit, the sub has been
21748 // canonicalized into a xor.
21749 // FIXME: Would it be better to use computeKnownBits to determine
21750 // whether it's safe to decanonicalize the xor?
21751 // x s< 0 ? x^C : 0 --> subus x, C
21752 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21753 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21754 OpRHSConst->getAPIntValue().isSignBit())
21755 // Note that we have to rebuild the RHS constant here to ensure we
21756 // don't rely on particular values of undef lanes.
21757 return DAG.getNode(
21758 X86ISD::SUBUS, DL, VT, OpLHS,
21759 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
21764 // Try to match a min/max vector operation.
21765 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21766 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21767 unsigned Opc = ret.first;
21768 bool NeedSplit = ret.second;
21770 if (Opc && NeedSplit) {
21771 unsigned NumElems = VT.getVectorNumElements();
21772 // Extract the LHS vectors
21773 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21774 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21776 // Extract the RHS vectors
21777 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21778 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21780 // Create min/max for each subvector
21781 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21782 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21784 // Merge the result
21785 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21787 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21790 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
21791 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21792 // Check if SETCC has already been promoted
21793 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
21794 // Check that condition value type matches vselect operand type
21797 assert(Cond.getValueType().isVector() &&
21798 "vector select expects a vector selector!");
21800 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21801 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21803 if (!TValIsAllOnes && !FValIsAllZeros) {
21804 // Try invert the condition if true value is not all 1s and false value
21806 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21807 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21809 if (TValIsAllZeros || FValIsAllOnes) {
21810 SDValue CC = Cond.getOperand(2);
21811 ISD::CondCode NewCC =
21812 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21813 Cond.getOperand(0).getValueType().isInteger());
21814 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21815 std::swap(LHS, RHS);
21816 TValIsAllOnes = FValIsAllOnes;
21817 FValIsAllZeros = TValIsAllZeros;
21821 if (TValIsAllOnes || FValIsAllZeros) {
21824 if (TValIsAllOnes && FValIsAllZeros)
21826 else if (TValIsAllOnes)
21827 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21828 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21829 else if (FValIsAllZeros)
21830 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21831 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21833 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21837 // Try to fold this VSELECT into a MOVSS/MOVSD
21838 if (N->getOpcode() == ISD::VSELECT &&
21839 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
21840 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
21841 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
21842 bool CanFold = false;
21843 unsigned NumElems = Cond.getNumOperands();
21847 if (isZero(Cond.getOperand(0))) {
21850 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
21851 // fold (vselect <0,-1> -> (movsd A, B)
21852 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21853 CanFold = isAllOnes(Cond.getOperand(i));
21854 } else if (isAllOnes(Cond.getOperand(0))) {
21858 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
21859 // fold (vselect <-1,0> -> (movsd B, A)
21860 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21861 CanFold = isZero(Cond.getOperand(i));
21865 if (VT == MVT::v4i32 || VT == MVT::v4f32)
21866 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
21867 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
21870 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
21871 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
21872 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
21873 // (v2i64 (bitcast B)))))
21875 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
21876 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
21877 // (v2f64 (bitcast B)))))
21879 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
21880 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
21881 // (v2i64 (bitcast A)))))
21883 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
21884 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
21885 // (v2f64 (bitcast A)))))
21887 CanFold = (isZero(Cond.getOperand(0)) &&
21888 isZero(Cond.getOperand(1)) &&
21889 isAllOnes(Cond.getOperand(2)) &&
21890 isAllOnes(Cond.getOperand(3)));
21892 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
21893 isAllOnes(Cond.getOperand(1)) &&
21894 isZero(Cond.getOperand(2)) &&
21895 isZero(Cond.getOperand(3))) {
21897 std::swap(LHS, RHS);
21901 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
21902 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
21903 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
21904 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
21906 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
21912 // If we know that this node is legal then we know that it is going to be
21913 // matched by one of the SSE/AVX BLEND instructions. These instructions only
21914 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
21915 // to simplify previous instructions.
21916 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21917 !DCI.isBeforeLegalize() &&
21918 // We explicitly check against v8i16 and v16i16 because, although
21919 // they're marked as Custom, they might only be legal when Cond is a
21920 // build_vector of constants. This will be taken care in a later
21922 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
21923 VT != MVT::v8i16)) {
21924 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21926 // Don't optimize vector selects that map to mask-registers.
21930 // Check all uses of that condition operand to check whether it will be
21931 // consumed by non-BLEND instructions, which may depend on all bits are set
21933 for (SDNode::use_iterator I = Cond->use_begin(),
21934 E = Cond->use_end(); I != E; ++I)
21935 if (I->getOpcode() != ISD::VSELECT)
21936 // TODO: Add other opcodes eventually lowered into BLEND.
21939 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21940 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21942 APInt KnownZero, KnownOne;
21943 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21944 DCI.isBeforeLegalizeOps());
21945 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21946 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
21947 DCI.CommitTargetLoweringOpt(TLO);
21950 // We should generate an X86ISD::BLENDI from a vselect if its argument
21951 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21952 // constants. This specific pattern gets generated when we split a
21953 // selector for a 512 bit vector in a machine without AVX512 (but with
21954 // 256-bit vectors), during legalization:
21956 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21958 // Iff we find this pattern and the build_vectors are built from
21959 // constants, we translate the vselect into a shuffle_vector that we
21960 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21961 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
21962 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21963 if (Shuffle.getNode())
21970 // Check whether a boolean test is testing a boolean value generated by
21971 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21974 // Simplify the following patterns:
21975 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21976 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21977 // to (Op EFLAGS Cond)
21979 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21980 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21981 // to (Op EFLAGS !Cond)
21983 // where Op could be BRCOND or CMOV.
21985 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21986 // Quit if not CMP and SUB with its value result used.
21987 if (Cmp.getOpcode() != X86ISD::CMP &&
21988 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21991 // Quit if not used as a boolean value.
21992 if (CC != X86::COND_E && CC != X86::COND_NE)
21995 // Check CMP operands. One of them should be 0 or 1 and the other should be
21996 // an SetCC or extended from it.
21997 SDValue Op1 = Cmp.getOperand(0);
21998 SDValue Op2 = Cmp.getOperand(1);
22001 const ConstantSDNode* C = nullptr;
22002 bool needOppositeCond = (CC == X86::COND_E);
22003 bool checkAgainstTrue = false; // Is it a comparison against 1?
22005 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22007 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22009 else // Quit if all operands are not constants.
22012 if (C->getZExtValue() == 1) {
22013 needOppositeCond = !needOppositeCond;
22014 checkAgainstTrue = true;
22015 } else if (C->getZExtValue() != 0)
22016 // Quit if the constant is neither 0 or 1.
22019 bool truncatedToBoolWithAnd = false;
22020 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22021 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22022 SetCC.getOpcode() == ISD::TRUNCATE ||
22023 SetCC.getOpcode() == ISD::AND) {
22024 if (SetCC.getOpcode() == ISD::AND) {
22026 ConstantSDNode *CS;
22027 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22028 CS->getZExtValue() == 1)
22030 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22031 CS->getZExtValue() == 1)
22035 SetCC = SetCC.getOperand(OpIdx);
22036 truncatedToBoolWithAnd = true;
22038 SetCC = SetCC.getOperand(0);
22041 switch (SetCC.getOpcode()) {
22042 case X86ISD::SETCC_CARRY:
22043 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22044 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22045 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22046 // truncated to i1 using 'and'.
22047 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22049 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22050 "Invalid use of SETCC_CARRY!");
22052 case X86ISD::SETCC:
22053 // Set the condition code or opposite one if necessary.
22054 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22055 if (needOppositeCond)
22056 CC = X86::GetOppositeBranchCondition(CC);
22057 return SetCC.getOperand(1);
22058 case X86ISD::CMOV: {
22059 // Check whether false/true value has canonical one, i.e. 0 or 1.
22060 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22061 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22062 // Quit if true value is not a constant.
22065 // Quit if false value is not a constant.
22067 SDValue Op = SetCC.getOperand(0);
22068 // Skip 'zext' or 'trunc' node.
22069 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22070 Op.getOpcode() == ISD::TRUNCATE)
22071 Op = Op.getOperand(0);
22072 // A special case for rdrand/rdseed, where 0 is set if false cond is
22074 if ((Op.getOpcode() != X86ISD::RDRAND &&
22075 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22078 // Quit if false value is not the constant 0 or 1.
22079 bool FValIsFalse = true;
22080 if (FVal && FVal->getZExtValue() != 0) {
22081 if (FVal->getZExtValue() != 1)
22083 // If FVal is 1, opposite cond is needed.
22084 needOppositeCond = !needOppositeCond;
22085 FValIsFalse = false;
22087 // Quit if TVal is not the constant opposite of FVal.
22088 if (FValIsFalse && TVal->getZExtValue() != 1)
22090 if (!FValIsFalse && TVal->getZExtValue() != 0)
22092 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22093 if (needOppositeCond)
22094 CC = X86::GetOppositeBranchCondition(CC);
22095 return SetCC.getOperand(3);
22102 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22103 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22104 TargetLowering::DAGCombinerInfo &DCI,
22105 const X86Subtarget *Subtarget) {
22108 // If the flag operand isn't dead, don't touch this CMOV.
22109 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22112 SDValue FalseOp = N->getOperand(0);
22113 SDValue TrueOp = N->getOperand(1);
22114 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22115 SDValue Cond = N->getOperand(3);
22117 if (CC == X86::COND_E || CC == X86::COND_NE) {
22118 switch (Cond.getOpcode()) {
22122 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22123 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22124 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22130 Flags = checkBoolTestSetCCCombine(Cond, CC);
22131 if (Flags.getNode() &&
22132 // Extra check as FCMOV only supports a subset of X86 cond.
22133 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22134 SDValue Ops[] = { FalseOp, TrueOp,
22135 DAG.getConstant(CC, MVT::i8), Flags };
22136 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22139 // If this is a select between two integer constants, try to do some
22140 // optimizations. Note that the operands are ordered the opposite of SELECT
22142 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22143 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22144 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22145 // larger than FalseC (the false value).
22146 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22147 CC = X86::GetOppositeBranchCondition(CC);
22148 std::swap(TrueC, FalseC);
22149 std::swap(TrueOp, FalseOp);
22152 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22153 // This is efficient for any integer data type (including i8/i16) and
22155 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22156 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22157 DAG.getConstant(CC, MVT::i8), Cond);
22159 // Zero extend the condition if needed.
22160 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22162 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22163 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22164 DAG.getConstant(ShAmt, MVT::i8));
22165 if (N->getNumValues() == 2) // Dead flag value?
22166 return DCI.CombineTo(N, Cond, SDValue());
22170 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22171 // for any integer data type, including i8/i16.
22172 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22173 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22174 DAG.getConstant(CC, MVT::i8), Cond);
22176 // Zero extend the condition if needed.
22177 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22178 FalseC->getValueType(0), Cond);
22179 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22180 SDValue(FalseC, 0));
22182 if (N->getNumValues() == 2) // Dead flag value?
22183 return DCI.CombineTo(N, Cond, SDValue());
22187 // Optimize cases that will turn into an LEA instruction. This requires
22188 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22189 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22190 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22191 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22193 bool isFastMultiplier = false;
22195 switch ((unsigned char)Diff) {
22197 case 1: // result = add base, cond
22198 case 2: // result = lea base( , cond*2)
22199 case 3: // result = lea base(cond, cond*2)
22200 case 4: // result = lea base( , cond*4)
22201 case 5: // result = lea base(cond, cond*4)
22202 case 8: // result = lea base( , cond*8)
22203 case 9: // result = lea base(cond, cond*8)
22204 isFastMultiplier = true;
22209 if (isFastMultiplier) {
22210 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22211 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22212 DAG.getConstant(CC, MVT::i8), Cond);
22213 // Zero extend the condition if needed.
22214 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22216 // Scale the condition by the difference.
22218 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22219 DAG.getConstant(Diff, Cond.getValueType()));
22221 // Add the base if non-zero.
22222 if (FalseC->getAPIntValue() != 0)
22223 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22224 SDValue(FalseC, 0));
22225 if (N->getNumValues() == 2) // Dead flag value?
22226 return DCI.CombineTo(N, Cond, SDValue());
22233 // Handle these cases:
22234 // (select (x != c), e, c) -> select (x != c), e, x),
22235 // (select (x == c), c, e) -> select (x == c), x, e)
22236 // where the c is an integer constant, and the "select" is the combination
22237 // of CMOV and CMP.
22239 // The rationale for this change is that the conditional-move from a constant
22240 // needs two instructions, however, conditional-move from a register needs
22241 // only one instruction.
22243 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22244 // some instruction-combining opportunities. This opt needs to be
22245 // postponed as late as possible.
22247 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22248 // the DCI.xxxx conditions are provided to postpone the optimization as
22249 // late as possible.
22251 ConstantSDNode *CmpAgainst = nullptr;
22252 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22253 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22254 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22256 if (CC == X86::COND_NE &&
22257 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22258 CC = X86::GetOppositeBranchCondition(CC);
22259 std::swap(TrueOp, FalseOp);
22262 if (CC == X86::COND_E &&
22263 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22264 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22265 DAG.getConstant(CC, MVT::i8), Cond };
22266 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22274 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22275 const X86Subtarget *Subtarget) {
22276 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22278 default: return SDValue();
22279 // SSE/AVX/AVX2 blend intrinsics.
22280 case Intrinsic::x86_avx2_pblendvb:
22281 case Intrinsic::x86_avx2_pblendw:
22282 case Intrinsic::x86_avx2_pblendd_128:
22283 case Intrinsic::x86_avx2_pblendd_256:
22284 // Don't try to simplify this intrinsic if we don't have AVX2.
22285 if (!Subtarget->hasAVX2())
22288 case Intrinsic::x86_avx_blend_pd_256:
22289 case Intrinsic::x86_avx_blend_ps_256:
22290 case Intrinsic::x86_avx_blendv_pd_256:
22291 case Intrinsic::x86_avx_blendv_ps_256:
22292 // Don't try to simplify this intrinsic if we don't have AVX.
22293 if (!Subtarget->hasAVX())
22296 case Intrinsic::x86_sse41_pblendw:
22297 case Intrinsic::x86_sse41_blendpd:
22298 case Intrinsic::x86_sse41_blendps:
22299 case Intrinsic::x86_sse41_blendvps:
22300 case Intrinsic::x86_sse41_blendvpd:
22301 case Intrinsic::x86_sse41_pblendvb: {
22302 SDValue Op0 = N->getOperand(1);
22303 SDValue Op1 = N->getOperand(2);
22304 SDValue Mask = N->getOperand(3);
22306 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22307 if (!Subtarget->hasSSE41())
22310 // fold (blend A, A, Mask) -> A
22313 // fold (blend A, B, allZeros) -> A
22314 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22316 // fold (blend A, B, allOnes) -> B
22317 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22320 // Simplify the case where the mask is a constant i32 value.
22321 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22322 if (C->isNullValue())
22324 if (C->isAllOnesValue())
22331 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22332 case Intrinsic::x86_sse2_psrai_w:
22333 case Intrinsic::x86_sse2_psrai_d:
22334 case Intrinsic::x86_avx2_psrai_w:
22335 case Intrinsic::x86_avx2_psrai_d:
22336 case Intrinsic::x86_sse2_psra_w:
22337 case Intrinsic::x86_sse2_psra_d:
22338 case Intrinsic::x86_avx2_psra_w:
22339 case Intrinsic::x86_avx2_psra_d: {
22340 SDValue Op0 = N->getOperand(1);
22341 SDValue Op1 = N->getOperand(2);
22342 EVT VT = Op0.getValueType();
22343 assert(VT.isVector() && "Expected a vector type!");
22345 if (isa<BuildVectorSDNode>(Op1))
22346 Op1 = Op1.getOperand(0);
22348 if (!isa<ConstantSDNode>(Op1))
22351 EVT SVT = VT.getVectorElementType();
22352 unsigned SVTBits = SVT.getSizeInBits();
22354 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22355 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22356 uint64_t ShAmt = C.getZExtValue();
22358 // Don't try to convert this shift into a ISD::SRA if the shift
22359 // count is bigger than or equal to the element size.
22360 if (ShAmt >= SVTBits)
22363 // Trivial case: if the shift count is zero, then fold this
22364 // into the first operand.
22368 // Replace this packed shift intrinsic with a target independent
22370 SDValue Splat = DAG.getConstant(C, VT);
22371 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22376 /// PerformMulCombine - Optimize a single multiply with constant into two
22377 /// in order to implement it with two cheaper instructions, e.g.
22378 /// LEA + SHL, LEA + LEA.
22379 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22380 TargetLowering::DAGCombinerInfo &DCI) {
22381 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22384 EVT VT = N->getValueType(0);
22385 if (VT != MVT::i64)
22388 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22391 uint64_t MulAmt = C->getZExtValue();
22392 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22395 uint64_t MulAmt1 = 0;
22396 uint64_t MulAmt2 = 0;
22397 if ((MulAmt % 9) == 0) {
22399 MulAmt2 = MulAmt / 9;
22400 } else if ((MulAmt % 5) == 0) {
22402 MulAmt2 = MulAmt / 5;
22403 } else if ((MulAmt % 3) == 0) {
22405 MulAmt2 = MulAmt / 3;
22408 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22411 if (isPowerOf2_64(MulAmt2) &&
22412 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22413 // If second multiplifer is pow2, issue it first. We want the multiply by
22414 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22416 std::swap(MulAmt1, MulAmt2);
22419 if (isPowerOf2_64(MulAmt1))
22420 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22421 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
22423 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22424 DAG.getConstant(MulAmt1, VT));
22426 if (isPowerOf2_64(MulAmt2))
22427 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22428 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
22430 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22431 DAG.getConstant(MulAmt2, VT));
22433 // Do not add new nodes to DAG combiner worklist.
22434 DCI.CombineTo(N, NewMul, false);
22439 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22440 SDValue N0 = N->getOperand(0);
22441 SDValue N1 = N->getOperand(1);
22442 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22443 EVT VT = N0.getValueType();
22445 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22446 // since the result of setcc_c is all zero's or all ones.
22447 if (VT.isInteger() && !VT.isVector() &&
22448 N1C && N0.getOpcode() == ISD::AND &&
22449 N0.getOperand(1).getOpcode() == ISD::Constant) {
22450 SDValue N00 = N0.getOperand(0);
22451 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22452 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22453 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22454 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22455 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22456 APInt ShAmt = N1C->getAPIntValue();
22457 Mask = Mask.shl(ShAmt);
22459 return DAG.getNode(ISD::AND, SDLoc(N), VT,
22460 N00, DAG.getConstant(Mask, VT));
22464 // Hardware support for vector shifts is sparse which makes us scalarize the
22465 // vector operations in many cases. Also, on sandybridge ADD is faster than
22467 // (shl V, 1) -> add V,V
22468 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22469 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22470 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22471 // We shift all of the values by one. In many cases we do not have
22472 // hardware support for this operation. This is better expressed as an ADD
22474 if (N1SplatC->getZExtValue() == 1)
22475 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22481 /// \brief Returns a vector of 0s if the node in input is a vector logical
22482 /// shift by a constant amount which is known to be bigger than or equal
22483 /// to the vector element size in bits.
22484 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22485 const X86Subtarget *Subtarget) {
22486 EVT VT = N->getValueType(0);
22488 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22489 (!Subtarget->hasInt256() ||
22490 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22493 SDValue Amt = N->getOperand(1);
22495 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22496 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22497 APInt ShiftAmt = AmtSplat->getAPIntValue();
22498 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22500 // SSE2/AVX2 logical shifts always return a vector of 0s
22501 // if the shift amount is bigger than or equal to
22502 // the element size. The constant shift amount will be
22503 // encoded as a 8-bit immediate.
22504 if (ShiftAmt.trunc(8).uge(MaxAmount))
22505 return getZeroVector(VT, Subtarget, DAG, DL);
22511 /// PerformShiftCombine - Combine shifts.
22512 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22513 TargetLowering::DAGCombinerInfo &DCI,
22514 const X86Subtarget *Subtarget) {
22515 if (N->getOpcode() == ISD::SHL) {
22516 SDValue V = PerformSHLCombine(N, DAG);
22517 if (V.getNode()) return V;
22520 if (N->getOpcode() != ISD::SRA) {
22521 // Try to fold this logical shift into a zero vector.
22522 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22523 if (V.getNode()) return V;
22529 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22530 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22531 // and friends. Likewise for OR -> CMPNEQSS.
22532 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22533 TargetLowering::DAGCombinerInfo &DCI,
22534 const X86Subtarget *Subtarget) {
22537 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22538 // we're requiring SSE2 for both.
22539 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22540 SDValue N0 = N->getOperand(0);
22541 SDValue N1 = N->getOperand(1);
22542 SDValue CMP0 = N0->getOperand(1);
22543 SDValue CMP1 = N1->getOperand(1);
22546 // The SETCCs should both refer to the same CMP.
22547 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22550 SDValue CMP00 = CMP0->getOperand(0);
22551 SDValue CMP01 = CMP0->getOperand(1);
22552 EVT VT = CMP00.getValueType();
22554 if (VT == MVT::f32 || VT == MVT::f64) {
22555 bool ExpectingFlags = false;
22556 // Check for any users that want flags:
22557 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22558 !ExpectingFlags && UI != UE; ++UI)
22559 switch (UI->getOpcode()) {
22564 ExpectingFlags = true;
22566 case ISD::CopyToReg:
22567 case ISD::SIGN_EXTEND:
22568 case ISD::ZERO_EXTEND:
22569 case ISD::ANY_EXTEND:
22573 if (!ExpectingFlags) {
22574 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22575 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22577 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22578 X86::CondCode tmp = cc0;
22583 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22584 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22585 // FIXME: need symbolic constants for these magic numbers.
22586 // See X86ATTInstPrinter.cpp:printSSECC().
22587 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22588 if (Subtarget->hasAVX512()) {
22589 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22590 CMP01, DAG.getConstant(x86cc, MVT::i8));
22591 if (N->getValueType(0) != MVT::i1)
22592 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22596 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22597 CMP00.getValueType(), CMP00, CMP01,
22598 DAG.getConstant(x86cc, MVT::i8));
22600 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22601 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22603 if (is64BitFP && !Subtarget->is64Bit()) {
22604 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22605 // 64-bit integer, since that's not a legal type. Since
22606 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22607 // bits, but can do this little dance to extract the lowest 32 bits
22608 // and work with those going forward.
22609 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22611 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22613 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22614 Vector32, DAG.getIntPtrConstant(0));
22618 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22619 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22620 DAG.getConstant(1, IntVT));
22621 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22622 return OneBitOfTruth;
22630 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22631 /// so it can be folded inside ANDNP.
22632 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22633 EVT VT = N->getValueType(0);
22635 // Match direct AllOnes for 128 and 256-bit vectors
22636 if (ISD::isBuildVectorAllOnes(N))
22639 // Look through a bit convert.
22640 if (N->getOpcode() == ISD::BITCAST)
22641 N = N->getOperand(0).getNode();
22643 // Sometimes the operand may come from a insert_subvector building a 256-bit
22645 if (VT.is256BitVector() &&
22646 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22647 SDValue V1 = N->getOperand(0);
22648 SDValue V2 = N->getOperand(1);
22650 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22651 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22652 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22653 ISD::isBuildVectorAllOnes(V2.getNode()))
22660 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22661 // register. In most cases we actually compare or select YMM-sized registers
22662 // and mixing the two types creates horrible code. This method optimizes
22663 // some of the transition sequences.
22664 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22665 TargetLowering::DAGCombinerInfo &DCI,
22666 const X86Subtarget *Subtarget) {
22667 EVT VT = N->getValueType(0);
22668 if (!VT.is256BitVector())
22671 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22672 N->getOpcode() == ISD::ZERO_EXTEND ||
22673 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22675 SDValue Narrow = N->getOperand(0);
22676 EVT NarrowVT = Narrow->getValueType(0);
22677 if (!NarrowVT.is128BitVector())
22680 if (Narrow->getOpcode() != ISD::XOR &&
22681 Narrow->getOpcode() != ISD::AND &&
22682 Narrow->getOpcode() != ISD::OR)
22685 SDValue N0 = Narrow->getOperand(0);
22686 SDValue N1 = Narrow->getOperand(1);
22689 // The Left side has to be a trunc.
22690 if (N0.getOpcode() != ISD::TRUNCATE)
22693 // The type of the truncated inputs.
22694 EVT WideVT = N0->getOperand(0)->getValueType(0);
22698 // The right side has to be a 'trunc' or a constant vector.
22699 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22700 ConstantSDNode *RHSConstSplat = nullptr;
22701 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22702 RHSConstSplat = RHSBV->getConstantSplatNode();
22703 if (!RHSTrunc && !RHSConstSplat)
22706 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22708 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22711 // Set N0 and N1 to hold the inputs to the new wide operation.
22712 N0 = N0->getOperand(0);
22713 if (RHSConstSplat) {
22714 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22715 SDValue(RHSConstSplat, 0));
22716 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22717 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22718 } else if (RHSTrunc) {
22719 N1 = N1->getOperand(0);
22722 // Generate the wide operation.
22723 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22724 unsigned Opcode = N->getOpcode();
22726 case ISD::ANY_EXTEND:
22728 case ISD::ZERO_EXTEND: {
22729 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22730 APInt Mask = APInt::getAllOnesValue(InBits);
22731 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22732 return DAG.getNode(ISD::AND, DL, VT,
22733 Op, DAG.getConstant(Mask, VT));
22735 case ISD::SIGN_EXTEND:
22736 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22737 Op, DAG.getValueType(NarrowVT));
22739 llvm_unreachable("Unexpected opcode");
22743 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22744 TargetLowering::DAGCombinerInfo &DCI,
22745 const X86Subtarget *Subtarget) {
22746 EVT VT = N->getValueType(0);
22747 if (DCI.isBeforeLegalizeOps())
22750 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22754 // Create BEXTR instructions
22755 // BEXTR is ((X >> imm) & (2**size-1))
22756 if (VT == MVT::i32 || VT == MVT::i64) {
22757 SDValue N0 = N->getOperand(0);
22758 SDValue N1 = N->getOperand(1);
22761 // Check for BEXTR.
22762 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22763 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22764 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22765 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22766 if (MaskNode && ShiftNode) {
22767 uint64_t Mask = MaskNode->getZExtValue();
22768 uint64_t Shift = ShiftNode->getZExtValue();
22769 if (isMask_64(Mask)) {
22770 uint64_t MaskSize = CountPopulation_64(Mask);
22771 if (Shift + MaskSize <= VT.getSizeInBits())
22772 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22773 DAG.getConstant(Shift | (MaskSize << 8), VT));
22781 // Want to form ANDNP nodes:
22782 // 1) In the hopes of then easily combining them with OR and AND nodes
22783 // to form PBLEND/PSIGN.
22784 // 2) To match ANDN packed intrinsics
22785 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22788 SDValue N0 = N->getOperand(0);
22789 SDValue N1 = N->getOperand(1);
22792 // Check LHS for vnot
22793 if (N0.getOpcode() == ISD::XOR &&
22794 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22795 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22796 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22798 // Check RHS for vnot
22799 if (N1.getOpcode() == ISD::XOR &&
22800 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22801 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22802 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22807 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22808 TargetLowering::DAGCombinerInfo &DCI,
22809 const X86Subtarget *Subtarget) {
22810 if (DCI.isBeforeLegalizeOps())
22813 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22817 SDValue N0 = N->getOperand(0);
22818 SDValue N1 = N->getOperand(1);
22819 EVT VT = N->getValueType(0);
22821 // look for psign/blend
22822 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22823 if (!Subtarget->hasSSSE3() ||
22824 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22827 // Canonicalize pandn to RHS
22828 if (N0.getOpcode() == X86ISD::ANDNP)
22830 // or (and (m, y), (pandn m, x))
22831 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22832 SDValue Mask = N1.getOperand(0);
22833 SDValue X = N1.getOperand(1);
22835 if (N0.getOperand(0) == Mask)
22836 Y = N0.getOperand(1);
22837 if (N0.getOperand(1) == Mask)
22838 Y = N0.getOperand(0);
22840 // Check to see if the mask appeared in both the AND and ANDNP and
22844 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22845 // Look through mask bitcast.
22846 if (Mask.getOpcode() == ISD::BITCAST)
22847 Mask = Mask.getOperand(0);
22848 if (X.getOpcode() == ISD::BITCAST)
22849 X = X.getOperand(0);
22850 if (Y.getOpcode() == ISD::BITCAST)
22851 Y = Y.getOperand(0);
22853 EVT MaskVT = Mask.getValueType();
22855 // Validate that the Mask operand is a vector sra node.
22856 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22857 // there is no psrai.b
22858 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22859 unsigned SraAmt = ~0;
22860 if (Mask.getOpcode() == ISD::SRA) {
22861 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22862 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22863 SraAmt = AmtConst->getZExtValue();
22864 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22865 SDValue SraC = Mask.getOperand(1);
22866 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22868 if ((SraAmt + 1) != EltBits)
22873 // Now we know we at least have a plendvb with the mask val. See if
22874 // we can form a psignb/w/d.
22875 // psign = x.type == y.type == mask.type && y = sub(0, x);
22876 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22877 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22878 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22879 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22880 "Unsupported VT for PSIGN");
22881 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22882 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22884 // PBLENDVB only available on SSE 4.1
22885 if (!Subtarget->hasSSE41())
22888 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22890 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22891 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22892 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22893 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22894 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22898 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22901 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22902 MachineFunction &MF = DAG.getMachineFunction();
22903 bool OptForSize = MF.getFunction()->getAttributes().
22904 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
22906 // SHLD/SHRD instructions have lower register pressure, but on some
22907 // platforms they have higher latency than the equivalent
22908 // series of shifts/or that would otherwise be generated.
22909 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22910 // have higher latencies and we are not optimizing for size.
22911 if (!OptForSize && Subtarget->isSHLDSlow())
22914 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22916 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22918 if (!N0.hasOneUse() || !N1.hasOneUse())
22921 SDValue ShAmt0 = N0.getOperand(1);
22922 if (ShAmt0.getValueType() != MVT::i8)
22924 SDValue ShAmt1 = N1.getOperand(1);
22925 if (ShAmt1.getValueType() != MVT::i8)
22927 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22928 ShAmt0 = ShAmt0.getOperand(0);
22929 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22930 ShAmt1 = ShAmt1.getOperand(0);
22933 unsigned Opc = X86ISD::SHLD;
22934 SDValue Op0 = N0.getOperand(0);
22935 SDValue Op1 = N1.getOperand(0);
22936 if (ShAmt0.getOpcode() == ISD::SUB) {
22937 Opc = X86ISD::SHRD;
22938 std::swap(Op0, Op1);
22939 std::swap(ShAmt0, ShAmt1);
22942 unsigned Bits = VT.getSizeInBits();
22943 if (ShAmt1.getOpcode() == ISD::SUB) {
22944 SDValue Sum = ShAmt1.getOperand(0);
22945 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22946 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22947 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22948 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22949 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22950 return DAG.getNode(Opc, DL, VT,
22952 DAG.getNode(ISD::TRUNCATE, DL,
22955 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22956 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22958 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22959 return DAG.getNode(Opc, DL, VT,
22960 N0.getOperand(0), N1.getOperand(0),
22961 DAG.getNode(ISD::TRUNCATE, DL,
22968 // Generate NEG and CMOV for integer abs.
22969 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22970 EVT VT = N->getValueType(0);
22972 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22973 // 8-bit integer abs to NEG and CMOV.
22974 if (VT.isInteger() && VT.getSizeInBits() == 8)
22977 SDValue N0 = N->getOperand(0);
22978 SDValue N1 = N->getOperand(1);
22981 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22982 // and change it to SUB and CMOV.
22983 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22984 N0.getOpcode() == ISD::ADD &&
22985 N0.getOperand(1) == N1 &&
22986 N1.getOpcode() == ISD::SRA &&
22987 N1.getOperand(0) == N0.getOperand(0))
22988 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22989 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22990 // Generate SUB & CMOV.
22991 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22992 DAG.getConstant(0, VT), N0.getOperand(0));
22994 SDValue Ops[] = { N0.getOperand(0), Neg,
22995 DAG.getConstant(X86::COND_GE, MVT::i8),
22996 SDValue(Neg.getNode(), 1) };
22997 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23002 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23003 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23004 TargetLowering::DAGCombinerInfo &DCI,
23005 const X86Subtarget *Subtarget) {
23006 if (DCI.isBeforeLegalizeOps())
23009 if (Subtarget->hasCMov()) {
23010 SDValue RV = performIntegerAbsCombine(N, DAG);
23018 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23019 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23020 TargetLowering::DAGCombinerInfo &DCI,
23021 const X86Subtarget *Subtarget) {
23022 LoadSDNode *Ld = cast<LoadSDNode>(N);
23023 EVT RegVT = Ld->getValueType(0);
23024 EVT MemVT = Ld->getMemoryVT();
23026 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23028 // On Sandybridge unaligned 256bit loads are inefficient.
23029 ISD::LoadExtType Ext = Ld->getExtensionType();
23030 unsigned Alignment = Ld->getAlignment();
23031 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23032 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
23033 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23034 unsigned NumElems = RegVT.getVectorNumElements();
23038 SDValue Ptr = Ld->getBasePtr();
23039 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
23041 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23043 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23044 Ld->getPointerInfo(), Ld->isVolatile(),
23045 Ld->isNonTemporal(), Ld->isInvariant(),
23047 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23048 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23049 Ld->getPointerInfo(), Ld->isVolatile(),
23050 Ld->isNonTemporal(), Ld->isInvariant(),
23051 std::min(16U, Alignment));
23052 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23054 Load2.getValue(1));
23056 SDValue NewVec = DAG.getUNDEF(RegVT);
23057 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23058 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23059 return DCI.CombineTo(N, NewVec, TF, true);
23065 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23066 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23067 const X86Subtarget *Subtarget) {
23068 StoreSDNode *St = cast<StoreSDNode>(N);
23069 EVT VT = St->getValue().getValueType();
23070 EVT StVT = St->getMemoryVT();
23072 SDValue StoredVal = St->getOperand(1);
23073 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23075 // If we are saving a concatenation of two XMM registers, perform two stores.
23076 // On Sandy Bridge, 256-bit memory operations are executed by two
23077 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
23078 // memory operation.
23079 unsigned Alignment = St->getAlignment();
23080 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23081 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
23082 StVT == VT && !IsAligned) {
23083 unsigned NumElems = VT.getVectorNumElements();
23087 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23088 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23090 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
23091 SDValue Ptr0 = St->getBasePtr();
23092 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23094 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23095 St->getPointerInfo(), St->isVolatile(),
23096 St->isNonTemporal(), Alignment);
23097 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23098 St->getPointerInfo(), St->isVolatile(),
23099 St->isNonTemporal(),
23100 std::min(16U, Alignment));
23101 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23104 // Optimize trunc store (of multiple scalars) to shuffle and store.
23105 // First, pack all of the elements in one place. Next, store to memory
23106 // in fewer chunks.
23107 if (St->isTruncatingStore() && VT.isVector()) {
23108 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23109 unsigned NumElems = VT.getVectorNumElements();
23110 assert(StVT != VT && "Cannot truncate to the same type");
23111 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23112 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23114 // From, To sizes and ElemCount must be pow of two
23115 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23116 // We are going to use the original vector elt for storing.
23117 // Accumulated smaller vector elements must be a multiple of the store size.
23118 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23120 unsigned SizeRatio = FromSz / ToSz;
23122 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23124 // Create a type on which we perform the shuffle
23125 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23126 StVT.getScalarType(), NumElems*SizeRatio);
23128 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23130 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23131 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23132 for (unsigned i = 0; i != NumElems; ++i)
23133 ShuffleVec[i] = i * SizeRatio;
23135 // Can't shuffle using an illegal type.
23136 if (!TLI.isTypeLegal(WideVecVT))
23139 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23140 DAG.getUNDEF(WideVecVT),
23142 // At this point all of the data is stored at the bottom of the
23143 // register. We now need to save it to mem.
23145 // Find the largest store unit
23146 MVT StoreType = MVT::i8;
23147 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
23148 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
23149 MVT Tp = (MVT::SimpleValueType)tp;
23150 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23154 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23155 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23156 (64 <= NumElems * ToSz))
23157 StoreType = MVT::f64;
23159 // Bitcast the original vector into a vector of store-size units
23160 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23161 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23162 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23163 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23164 SmallVector<SDValue, 8> Chains;
23165 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
23166 TLI.getPointerTy());
23167 SDValue Ptr = St->getBasePtr();
23169 // Perform one or more big stores into memory.
23170 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23171 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23172 StoreType, ShuffWide,
23173 DAG.getIntPtrConstant(i));
23174 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23175 St->getPointerInfo(), St->isVolatile(),
23176 St->isNonTemporal(), St->getAlignment());
23177 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23178 Chains.push_back(Ch);
23181 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23184 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23185 // the FP state in cases where an emms may be missing.
23186 // A preferable solution to the general problem is to figure out the right
23187 // places to insert EMMS. This qualifies as a quick hack.
23189 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23190 if (VT.getSizeInBits() != 64)
23193 const Function *F = DAG.getMachineFunction().getFunction();
23194 bool NoImplicitFloatOps = F->getAttributes().
23195 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
23196 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
23197 && Subtarget->hasSSE2();
23198 if ((VT.isVector() ||
23199 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23200 isa<LoadSDNode>(St->getValue()) &&
23201 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23202 St->getChain().hasOneUse() && !St->isVolatile()) {
23203 SDNode* LdVal = St->getValue().getNode();
23204 LoadSDNode *Ld = nullptr;
23205 int TokenFactorIndex = -1;
23206 SmallVector<SDValue, 8> Ops;
23207 SDNode* ChainVal = St->getChain().getNode();
23208 // Must be a store of a load. We currently handle two cases: the load
23209 // is a direct child, and it's under an intervening TokenFactor. It is
23210 // possible to dig deeper under nested TokenFactors.
23211 if (ChainVal == LdVal)
23212 Ld = cast<LoadSDNode>(St->getChain());
23213 else if (St->getValue().hasOneUse() &&
23214 ChainVal->getOpcode() == ISD::TokenFactor) {
23215 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23216 if (ChainVal->getOperand(i).getNode() == LdVal) {
23217 TokenFactorIndex = i;
23218 Ld = cast<LoadSDNode>(St->getValue());
23220 Ops.push_back(ChainVal->getOperand(i));
23224 if (!Ld || !ISD::isNormalLoad(Ld))
23227 // If this is not the MMX case, i.e. we are just turning i64 load/store
23228 // into f64 load/store, avoid the transformation if there are multiple
23229 // uses of the loaded value.
23230 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23235 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23236 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23238 if (Subtarget->is64Bit() || F64IsLegal) {
23239 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23240 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23241 Ld->getPointerInfo(), Ld->isVolatile(),
23242 Ld->isNonTemporal(), Ld->isInvariant(),
23243 Ld->getAlignment());
23244 SDValue NewChain = NewLd.getValue(1);
23245 if (TokenFactorIndex != -1) {
23246 Ops.push_back(NewChain);
23247 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23249 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23250 St->getPointerInfo(),
23251 St->isVolatile(), St->isNonTemporal(),
23252 St->getAlignment());
23255 // Otherwise, lower to two pairs of 32-bit loads / stores.
23256 SDValue LoAddr = Ld->getBasePtr();
23257 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23258 DAG.getConstant(4, MVT::i32));
23260 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23261 Ld->getPointerInfo(),
23262 Ld->isVolatile(), Ld->isNonTemporal(),
23263 Ld->isInvariant(), Ld->getAlignment());
23264 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23265 Ld->getPointerInfo().getWithOffset(4),
23266 Ld->isVolatile(), Ld->isNonTemporal(),
23268 MinAlign(Ld->getAlignment(), 4));
23270 SDValue NewChain = LoLd.getValue(1);
23271 if (TokenFactorIndex != -1) {
23272 Ops.push_back(LoLd);
23273 Ops.push_back(HiLd);
23274 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23277 LoAddr = St->getBasePtr();
23278 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23279 DAG.getConstant(4, MVT::i32));
23281 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23282 St->getPointerInfo(),
23283 St->isVolatile(), St->isNonTemporal(),
23284 St->getAlignment());
23285 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23286 St->getPointerInfo().getWithOffset(4),
23288 St->isNonTemporal(),
23289 MinAlign(St->getAlignment(), 4));
23290 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23295 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23296 /// and return the operands for the horizontal operation in LHS and RHS. A
23297 /// horizontal operation performs the binary operation on successive elements
23298 /// of its first operand, then on successive elements of its second operand,
23299 /// returning the resulting values in a vector. For example, if
23300 /// A = < float a0, float a1, float a2, float a3 >
23302 /// B = < float b0, float b1, float b2, float b3 >
23303 /// then the result of doing a horizontal operation on A and B is
23304 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23305 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23306 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23307 /// set to A, RHS to B, and the routine returns 'true'.
23308 /// Note that the binary operation should have the property that if one of the
23309 /// operands is UNDEF then the result is UNDEF.
23310 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23311 // Look for the following pattern: if
23312 // A = < float a0, float a1, float a2, float a3 >
23313 // B = < float b0, float b1, float b2, float b3 >
23315 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23316 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23317 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23318 // which is A horizontal-op B.
23320 // At least one of the operands should be a vector shuffle.
23321 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23322 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23325 MVT VT = LHS.getSimpleValueType();
23327 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23328 "Unsupported vector type for horizontal add/sub");
23330 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23331 // operate independently on 128-bit lanes.
23332 unsigned NumElts = VT.getVectorNumElements();
23333 unsigned NumLanes = VT.getSizeInBits()/128;
23334 unsigned NumLaneElts = NumElts / NumLanes;
23335 assert((NumLaneElts % 2 == 0) &&
23336 "Vector type should have an even number of elements in each lane");
23337 unsigned HalfLaneElts = NumLaneElts/2;
23339 // View LHS in the form
23340 // LHS = VECTOR_SHUFFLE A, B, LMask
23341 // If LHS is not a shuffle then pretend it is the shuffle
23342 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23343 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23346 SmallVector<int, 16> LMask(NumElts);
23347 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23348 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23349 A = LHS.getOperand(0);
23350 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23351 B = LHS.getOperand(1);
23352 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23353 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23355 if (LHS.getOpcode() != ISD::UNDEF)
23357 for (unsigned i = 0; i != NumElts; ++i)
23361 // Likewise, view RHS in the form
23362 // RHS = VECTOR_SHUFFLE C, D, RMask
23364 SmallVector<int, 16> RMask(NumElts);
23365 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23366 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23367 C = RHS.getOperand(0);
23368 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23369 D = RHS.getOperand(1);
23370 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23371 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23373 if (RHS.getOpcode() != ISD::UNDEF)
23375 for (unsigned i = 0; i != NumElts; ++i)
23379 // Check that the shuffles are both shuffling the same vectors.
23380 if (!(A == C && B == D) && !(A == D && B == C))
23383 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23384 if (!A.getNode() && !B.getNode())
23387 // If A and B occur in reverse order in RHS, then "swap" them (which means
23388 // rewriting the mask).
23390 CommuteVectorShuffleMask(RMask, NumElts);
23392 // At this point LHS and RHS are equivalent to
23393 // LHS = VECTOR_SHUFFLE A, B, LMask
23394 // RHS = VECTOR_SHUFFLE A, B, RMask
23395 // Check that the masks correspond to performing a horizontal operation.
23396 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23397 for (unsigned i = 0; i != NumLaneElts; ++i) {
23398 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23400 // Ignore any UNDEF components.
23401 if (LIdx < 0 || RIdx < 0 ||
23402 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23403 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23406 // Check that successive elements are being operated on. If not, this is
23407 // not a horizontal operation.
23408 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23409 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23410 if (!(LIdx == Index && RIdx == Index + 1) &&
23411 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23416 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23417 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23421 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
23422 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23423 const X86Subtarget *Subtarget) {
23424 EVT VT = N->getValueType(0);
23425 SDValue LHS = N->getOperand(0);
23426 SDValue RHS = N->getOperand(1);
23428 // Try to synthesize horizontal adds from adds of shuffles.
23429 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23430 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23431 isHorizontalBinOp(LHS, RHS, true))
23432 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23436 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23437 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23438 const X86Subtarget *Subtarget) {
23439 EVT VT = N->getValueType(0);
23440 SDValue LHS = N->getOperand(0);
23441 SDValue RHS = N->getOperand(1);
23443 // Try to synthesize horizontal subs from subs of shuffles.
23444 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23445 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23446 isHorizontalBinOp(LHS, RHS, false))
23447 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23451 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23452 /// X86ISD::FXOR nodes.
23453 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23454 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23455 // F[X]OR(0.0, x) -> x
23456 // F[X]OR(x, 0.0) -> x
23457 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23458 if (C->getValueAPF().isPosZero())
23459 return N->getOperand(1);
23460 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23461 if (C->getValueAPF().isPosZero())
23462 return N->getOperand(0);
23466 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
23467 /// X86ISD::FMAX nodes.
23468 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23469 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23471 // Only perform optimizations if UnsafeMath is used.
23472 if (!DAG.getTarget().Options.UnsafeFPMath)
23475 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23476 // into FMINC and FMAXC, which are Commutative operations.
23477 unsigned NewOp = 0;
23478 switch (N->getOpcode()) {
23479 default: llvm_unreachable("unknown opcode");
23480 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23481 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23484 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23485 N->getOperand(0), N->getOperand(1));
23488 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
23489 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23490 // FAND(0.0, x) -> 0.0
23491 // FAND(x, 0.0) -> 0.0
23492 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23493 if (C->getValueAPF().isPosZero())
23494 return N->getOperand(0);
23495 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23496 if (C->getValueAPF().isPosZero())
23497 return N->getOperand(1);
23501 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
23502 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23503 // FANDN(x, 0.0) -> 0.0
23504 // FANDN(0.0, x) -> x
23505 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23506 if (C->getValueAPF().isPosZero())
23507 return N->getOperand(1);
23508 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23509 if (C->getValueAPF().isPosZero())
23510 return N->getOperand(1);
23514 static SDValue PerformBTCombine(SDNode *N,
23516 TargetLowering::DAGCombinerInfo &DCI) {
23517 // BT ignores high bits in the bit index operand.
23518 SDValue Op1 = N->getOperand(1);
23519 if (Op1.hasOneUse()) {
23520 unsigned BitWidth = Op1.getValueSizeInBits();
23521 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23522 APInt KnownZero, KnownOne;
23523 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23524 !DCI.isBeforeLegalizeOps());
23525 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23526 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23527 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23528 DCI.CommitTargetLoweringOpt(TLO);
23533 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23534 SDValue Op = N->getOperand(0);
23535 if (Op.getOpcode() == ISD::BITCAST)
23536 Op = Op.getOperand(0);
23537 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23538 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23539 VT.getVectorElementType().getSizeInBits() ==
23540 OpVT.getVectorElementType().getSizeInBits()) {
23541 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23546 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23547 const X86Subtarget *Subtarget) {
23548 EVT VT = N->getValueType(0);
23549 if (!VT.isVector())
23552 SDValue N0 = N->getOperand(0);
23553 SDValue N1 = N->getOperand(1);
23554 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23557 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23558 // both SSE and AVX2 since there is no sign-extended shift right
23559 // operation on a vector with 64-bit elements.
23560 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23561 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23562 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23563 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23564 SDValue N00 = N0.getOperand(0);
23566 // EXTLOAD has a better solution on AVX2,
23567 // it may be replaced with X86ISD::VSEXT node.
23568 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23569 if (!ISD::isNormalLoad(N00.getNode()))
23572 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23573 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23575 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23581 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23582 TargetLowering::DAGCombinerInfo &DCI,
23583 const X86Subtarget *Subtarget) {
23584 if (!DCI.isBeforeLegalizeOps())
23587 if (!Subtarget->hasFp256())
23590 EVT VT = N->getValueType(0);
23591 if (VT.isVector() && VT.getSizeInBits() == 256) {
23592 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23600 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23601 const X86Subtarget* Subtarget) {
23603 EVT VT = N->getValueType(0);
23605 // Let legalize expand this if it isn't a legal type yet.
23606 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23609 EVT ScalarVT = VT.getScalarType();
23610 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23611 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23614 SDValue A = N->getOperand(0);
23615 SDValue B = N->getOperand(1);
23616 SDValue C = N->getOperand(2);
23618 bool NegA = (A.getOpcode() == ISD::FNEG);
23619 bool NegB = (B.getOpcode() == ISD::FNEG);
23620 bool NegC = (C.getOpcode() == ISD::FNEG);
23622 // Negative multiplication when NegA xor NegB
23623 bool NegMul = (NegA != NegB);
23625 A = A.getOperand(0);
23627 B = B.getOperand(0);
23629 C = C.getOperand(0);
23633 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23635 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23637 return DAG.getNode(Opcode, dl, VT, A, B, C);
23640 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23641 TargetLowering::DAGCombinerInfo &DCI,
23642 const X86Subtarget *Subtarget) {
23643 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23644 // (and (i32 x86isd::setcc_carry), 1)
23645 // This eliminates the zext. This transformation is necessary because
23646 // ISD::SETCC is always legalized to i8.
23648 SDValue N0 = N->getOperand(0);
23649 EVT VT = N->getValueType(0);
23651 if (N0.getOpcode() == ISD::AND &&
23653 N0.getOperand(0).hasOneUse()) {
23654 SDValue N00 = N0.getOperand(0);
23655 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23656 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23657 if (!C || C->getZExtValue() != 1)
23659 return DAG.getNode(ISD::AND, dl, VT,
23660 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23661 N00.getOperand(0), N00.getOperand(1)),
23662 DAG.getConstant(1, VT));
23666 if (N0.getOpcode() == ISD::TRUNCATE &&
23668 N0.getOperand(0).hasOneUse()) {
23669 SDValue N00 = N0.getOperand(0);
23670 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23671 return DAG.getNode(ISD::AND, dl, VT,
23672 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23673 N00.getOperand(0), N00.getOperand(1)),
23674 DAG.getConstant(1, VT));
23677 if (VT.is256BitVector()) {
23678 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23686 // Optimize x == -y --> x+y == 0
23687 // x != -y --> x+y != 0
23688 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23689 const X86Subtarget* Subtarget) {
23690 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23691 SDValue LHS = N->getOperand(0);
23692 SDValue RHS = N->getOperand(1);
23693 EVT VT = N->getValueType(0);
23696 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23697 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23698 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23699 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23700 LHS.getValueType(), RHS, LHS.getOperand(1));
23701 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23702 addV, DAG.getConstant(0, addV.getValueType()), CC);
23704 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23705 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23706 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23707 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23708 RHS.getValueType(), LHS, RHS.getOperand(1));
23709 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23710 addV, DAG.getConstant(0, addV.getValueType()), CC);
23713 if (VT.getScalarType() == MVT::i1) {
23714 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23715 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23716 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
23717 if (!IsSEXT0 && !IsVZero0)
23719 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
23720 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23721 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23723 if (!IsSEXT1 && !IsVZero1)
23726 if (IsSEXT0 && IsVZero1) {
23727 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
23728 if (CC == ISD::SETEQ)
23729 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23730 return LHS.getOperand(0);
23732 if (IsSEXT1 && IsVZero0) {
23733 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
23734 if (CC == ISD::SETEQ)
23735 return DAG.getNOT(DL, RHS.getOperand(0), VT);
23736 return RHS.getOperand(0);
23743 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23744 const X86Subtarget *Subtarget) {
23746 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23747 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23748 "X86insertps is only defined for v4x32");
23750 SDValue Ld = N->getOperand(1);
23751 if (MayFoldLoad(Ld)) {
23752 // Extract the countS bits from the immediate so we can get the proper
23753 // address when narrowing the vector load to a specific element.
23754 // When the second source op is a memory address, interps doesn't use
23755 // countS and just gets an f32 from that address.
23756 unsigned DestIndex =
23757 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23758 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23762 // Create this as a scalar to vector to match the instruction pattern.
23763 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23764 // countS bits are ignored when loading from memory on insertps, which
23765 // means we don't need to explicitly set them to 0.
23766 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23767 LoadScalarToVector, N->getOperand(2));
23770 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23771 // as "sbb reg,reg", since it can be extended without zext and produces
23772 // an all-ones bit which is more useful than 0/1 in some cases.
23773 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23776 return DAG.getNode(ISD::AND, DL, VT,
23777 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23778 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
23779 DAG.getConstant(1, VT));
23780 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23781 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23782 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23783 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
23786 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23787 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23788 TargetLowering::DAGCombinerInfo &DCI,
23789 const X86Subtarget *Subtarget) {
23791 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23792 SDValue EFLAGS = N->getOperand(1);
23794 if (CC == X86::COND_A) {
23795 // Try to convert COND_A into COND_B in an attempt to facilitate
23796 // materializing "setb reg".
23798 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23799 // cannot take an immediate as its first operand.
23801 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23802 EFLAGS.getValueType().isInteger() &&
23803 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23804 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23805 EFLAGS.getNode()->getVTList(),
23806 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23807 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23808 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23812 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23813 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23815 if (CC == X86::COND_B)
23816 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23820 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23821 if (Flags.getNode()) {
23822 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23823 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23829 // Optimize branch condition evaluation.
23831 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23832 TargetLowering::DAGCombinerInfo &DCI,
23833 const X86Subtarget *Subtarget) {
23835 SDValue Chain = N->getOperand(0);
23836 SDValue Dest = N->getOperand(1);
23837 SDValue EFLAGS = N->getOperand(3);
23838 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23842 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23843 if (Flags.getNode()) {
23844 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23845 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23852 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23853 SelectionDAG &DAG) {
23854 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23855 // optimize away operation when it's from a constant.
23857 // The general transformation is:
23858 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23859 // AND(VECTOR_CMP(x,y), constant2)
23860 // constant2 = UNARYOP(constant)
23862 // Early exit if this isn't a vector operation, the operand of the
23863 // unary operation isn't a bitwise AND, or if the sizes of the operations
23864 // aren't the same.
23865 EVT VT = N->getValueType(0);
23866 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23867 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23868 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23871 // Now check that the other operand of the AND is a constant. We could
23872 // make the transformation for non-constant splats as well, but it's unclear
23873 // that would be a benefit as it would not eliminate any operations, just
23874 // perform one more step in scalar code before moving to the vector unit.
23875 if (BuildVectorSDNode *BV =
23876 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23877 // Bail out if the vector isn't a constant.
23878 if (!BV->isConstant())
23881 // Everything checks out. Build up the new and improved node.
23883 EVT IntVT = BV->getValueType(0);
23884 // Create a new constant of the appropriate type for the transformed
23886 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23887 // The AND node needs bitcasts to/from an integer vector type around it.
23888 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23889 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23890 N->getOperand(0)->getOperand(0), MaskConst);
23891 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23898 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23899 const X86TargetLowering *XTLI) {
23900 // First try to optimize away the conversion entirely when it's
23901 // conditionally from a constant. Vectors only.
23902 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23903 if (Res != SDValue())
23906 // Now move on to more general possibilities.
23907 SDValue Op0 = N->getOperand(0);
23908 EVT InVT = Op0->getValueType(0);
23910 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23911 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
23913 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23914 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
23915 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
23918 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
23919 // a 32-bit target where SSE doesn't support i64->FP operations.
23920 if (Op0.getOpcode() == ISD::LOAD) {
23921 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
23922 EVT VT = Ld->getValueType(0);
23923 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
23924 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
23925 !XTLI->getSubtarget()->is64Bit() &&
23927 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
23928 Ld->getChain(), Op0, DAG);
23929 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
23936 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
23937 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
23938 X86TargetLowering::DAGCombinerInfo &DCI) {
23939 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
23940 // the result is either zero or one (depending on the input carry bit).
23941 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
23942 if (X86::isZeroNode(N->getOperand(0)) &&
23943 X86::isZeroNode(N->getOperand(1)) &&
23944 // We don't have a good way to replace an EFLAGS use, so only do this when
23946 SDValue(N, 1).use_empty()) {
23948 EVT VT = N->getValueType(0);
23949 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
23950 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
23951 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
23952 DAG.getConstant(X86::COND_B,MVT::i8),
23954 DAG.getConstant(1, VT));
23955 return DCI.CombineTo(N, Res1, CarryOut);
23961 // fold (add Y, (sete X, 0)) -> adc 0, Y
23962 // (add Y, (setne X, 0)) -> sbb -1, Y
23963 // (sub (sete X, 0), Y) -> sbb 0, Y
23964 // (sub (setne X, 0), Y) -> adc -1, Y
23965 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23968 // Look through ZExts.
23969 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23970 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23973 SDValue SetCC = Ext.getOperand(0);
23974 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23977 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23978 if (CC != X86::COND_E && CC != X86::COND_NE)
23981 SDValue Cmp = SetCC.getOperand(1);
23982 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23983 !X86::isZeroNode(Cmp.getOperand(1)) ||
23984 !Cmp.getOperand(0).getValueType().isInteger())
23987 SDValue CmpOp0 = Cmp.getOperand(0);
23988 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
23989 DAG.getConstant(1, CmpOp0.getValueType()));
23991 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
23992 if (CC == X86::COND_NE)
23993 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23994 DL, OtherVal.getValueType(), OtherVal,
23995 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
23996 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23997 DL, OtherVal.getValueType(), OtherVal,
23998 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
24001 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24002 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24003 const X86Subtarget *Subtarget) {
24004 EVT VT = N->getValueType(0);
24005 SDValue Op0 = N->getOperand(0);
24006 SDValue Op1 = N->getOperand(1);
24008 // Try to synthesize horizontal adds from adds of shuffles.
24009 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24010 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24011 isHorizontalBinOp(Op0, Op1, true))
24012 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24014 return OptimizeConditionalInDecrement(N, DAG);
24017 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24018 const X86Subtarget *Subtarget) {
24019 SDValue Op0 = N->getOperand(0);
24020 SDValue Op1 = N->getOperand(1);
24022 // X86 can't encode an immediate LHS of a sub. See if we can push the
24023 // negation into a preceding instruction.
24024 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24025 // If the RHS of the sub is a XOR with one use and a constant, invert the
24026 // immediate. Then add one to the LHS of the sub so we can turn
24027 // X-Y -> X+~Y+1, saving one register.
24028 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24029 isa<ConstantSDNode>(Op1.getOperand(1))) {
24030 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24031 EVT VT = Op0.getValueType();
24032 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24034 DAG.getConstant(~XorC, VT));
24035 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24036 DAG.getConstant(C->getAPIntValue()+1, VT));
24040 // Try to synthesize horizontal adds from adds of shuffles.
24041 EVT VT = N->getValueType(0);
24042 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24043 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24044 isHorizontalBinOp(Op0, Op1, true))
24045 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24047 return OptimizeConditionalInDecrement(N, DAG);
24050 /// performVZEXTCombine - Performs build vector combines
24051 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24052 TargetLowering::DAGCombinerInfo &DCI,
24053 const X86Subtarget *Subtarget) {
24054 // (vzext (bitcast (vzext (x)) -> (vzext x)
24055 SDValue In = N->getOperand(0);
24056 while (In.getOpcode() == ISD::BITCAST)
24057 In = In.getOperand(0);
24059 if (In.getOpcode() != X86ISD::VZEXT)
24062 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
24066 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24067 DAGCombinerInfo &DCI) const {
24068 SelectionDAG &DAG = DCI.DAG;
24069 switch (N->getOpcode()) {
24071 case ISD::EXTRACT_VECTOR_ELT:
24072 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24074 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24075 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24076 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24077 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24078 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24079 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24082 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24083 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24084 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24085 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24086 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24087 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24088 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
24089 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24090 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24092 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24094 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24095 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24096 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24097 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24098 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24099 case ISD::ANY_EXTEND:
24100 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24101 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24102 case ISD::SIGN_EXTEND_INREG:
24103 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24104 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
24105 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24106 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24107 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24108 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24109 case X86ISD::SHUFP: // Handle all target specific shuffles
24110 case X86ISD::PALIGNR:
24111 case X86ISD::UNPCKH:
24112 case X86ISD::UNPCKL:
24113 case X86ISD::MOVHLPS:
24114 case X86ISD::MOVLHPS:
24115 case X86ISD::PSHUFB:
24116 case X86ISD::PSHUFD:
24117 case X86ISD::PSHUFHW:
24118 case X86ISD::PSHUFLW:
24119 case X86ISD::MOVSS:
24120 case X86ISD::MOVSD:
24121 case X86ISD::VPERMILPI:
24122 case X86ISD::VPERM2X128:
24123 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24124 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24125 case ISD::INTRINSIC_WO_CHAIN:
24126 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24127 case X86ISD::INSERTPS:
24128 return PerformINSERTPSCombine(N, DAG, Subtarget);
24129 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
24135 /// isTypeDesirableForOp - Return true if the target has native support for
24136 /// the specified value type and it is 'desirable' to use the type for the
24137 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24138 /// instruction encodings are longer and some i16 instructions are slow.
24139 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24140 if (!isTypeLegal(VT))
24142 if (VT != MVT::i16)
24149 case ISD::SIGN_EXTEND:
24150 case ISD::ZERO_EXTEND:
24151 case ISD::ANY_EXTEND:
24164 /// IsDesirableToPromoteOp - This method query the target whether it is
24165 /// beneficial for dag combiner to promote the specified node. If true, it
24166 /// should return the desired promotion type by reference.
24167 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24168 EVT VT = Op.getValueType();
24169 if (VT != MVT::i16)
24172 bool Promote = false;
24173 bool Commute = false;
24174 switch (Op.getOpcode()) {
24177 LoadSDNode *LD = cast<LoadSDNode>(Op);
24178 // If the non-extending load has a single use and it's not live out, then it
24179 // might be folded.
24180 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24181 Op.hasOneUse()*/) {
24182 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24183 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24184 // The only case where we'd want to promote LOAD (rather then it being
24185 // promoted as an operand is when it's only use is liveout.
24186 if (UI->getOpcode() != ISD::CopyToReg)
24193 case ISD::SIGN_EXTEND:
24194 case ISD::ZERO_EXTEND:
24195 case ISD::ANY_EXTEND:
24200 SDValue N0 = Op.getOperand(0);
24201 // Look out for (store (shl (load), x)).
24202 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24215 SDValue N0 = Op.getOperand(0);
24216 SDValue N1 = Op.getOperand(1);
24217 if (!Commute && MayFoldLoad(N1))
24219 // Avoid disabling potential load folding opportunities.
24220 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24222 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24232 //===----------------------------------------------------------------------===//
24233 // X86 Inline Assembly Support
24234 //===----------------------------------------------------------------------===//
24237 // Helper to match a string separated by whitespace.
24238 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24239 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24241 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24242 StringRef piece(*args[i]);
24243 if (!s.startswith(piece)) // Check if the piece matches.
24246 s = s.substr(piece.size());
24247 StringRef::size_type pos = s.find_first_not_of(" \t");
24248 if (pos == 0) // We matched a prefix.
24256 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24259 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24261 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24262 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24263 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24264 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24266 if (AsmPieces.size() == 3)
24268 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24275 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24276 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24278 std::string AsmStr = IA->getAsmString();
24280 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24281 if (!Ty || Ty->getBitWidth() % 16 != 0)
24284 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24285 SmallVector<StringRef, 4> AsmPieces;
24286 SplitString(AsmStr, AsmPieces, ";\n");
24288 switch (AsmPieces.size()) {
24289 default: return false;
24291 // FIXME: this should verify that we are targeting a 486 or better. If not,
24292 // we will turn this bswap into something that will be lowered to logical
24293 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24294 // lower so don't worry about this.
24296 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24297 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24298 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24299 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24300 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24301 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24302 // No need to check constraints, nothing other than the equivalent of
24303 // "=r,0" would be valid here.
24304 return IntrinsicLowering::LowerToByteSwap(CI);
24307 // rorw $$8, ${0:w} --> llvm.bswap.i16
24308 if (CI->getType()->isIntegerTy(16) &&
24309 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24310 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24311 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24313 const std::string &ConstraintsStr = IA->getConstraintString();
24314 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24315 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24316 if (clobbersFlagRegisters(AsmPieces))
24317 return IntrinsicLowering::LowerToByteSwap(CI);
24321 if (CI->getType()->isIntegerTy(32) &&
24322 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24323 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24324 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24325 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24327 const std::string &ConstraintsStr = IA->getConstraintString();
24328 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24329 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24330 if (clobbersFlagRegisters(AsmPieces))
24331 return IntrinsicLowering::LowerToByteSwap(CI);
24334 if (CI->getType()->isIntegerTy(64)) {
24335 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24336 if (Constraints.size() >= 2 &&
24337 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24338 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24339 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24340 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
24341 matchAsm(AsmPieces[1], "bswap", "%edx") &&
24342 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
24343 return IntrinsicLowering::LowerToByteSwap(CI);
24351 /// getConstraintType - Given a constraint letter, return the type of
24352 /// constraint it is for this target.
24353 X86TargetLowering::ConstraintType
24354 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24355 if (Constraint.size() == 1) {
24356 switch (Constraint[0]) {
24367 return C_RegisterClass;
24391 return TargetLowering::getConstraintType(Constraint);
24394 /// Examine constraint type and operand type and determine a weight value.
24395 /// This object must already have been set up with the operand type
24396 /// and the current alternative constraint selected.
24397 TargetLowering::ConstraintWeight
24398 X86TargetLowering::getSingleConstraintMatchWeight(
24399 AsmOperandInfo &info, const char *constraint) const {
24400 ConstraintWeight weight = CW_Invalid;
24401 Value *CallOperandVal = info.CallOperandVal;
24402 // If we don't have a value, we can't do a match,
24403 // but allow it at the lowest weight.
24404 if (!CallOperandVal)
24406 Type *type = CallOperandVal->getType();
24407 // Look at the constraint type.
24408 switch (*constraint) {
24410 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24421 if (CallOperandVal->getType()->isIntegerTy())
24422 weight = CW_SpecificReg;
24427 if (type->isFloatingPointTy())
24428 weight = CW_SpecificReg;
24431 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24432 weight = CW_SpecificReg;
24436 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24437 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24438 weight = CW_Register;
24441 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24442 if (C->getZExtValue() <= 31)
24443 weight = CW_Constant;
24447 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24448 if (C->getZExtValue() <= 63)
24449 weight = CW_Constant;
24453 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24454 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24455 weight = CW_Constant;
24459 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24460 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24461 weight = CW_Constant;
24465 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24466 if (C->getZExtValue() <= 3)
24467 weight = CW_Constant;
24471 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24472 if (C->getZExtValue() <= 0xff)
24473 weight = CW_Constant;
24478 if (dyn_cast<ConstantFP>(CallOperandVal)) {
24479 weight = CW_Constant;
24483 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24484 if ((C->getSExtValue() >= -0x80000000LL) &&
24485 (C->getSExtValue() <= 0x7fffffffLL))
24486 weight = CW_Constant;
24490 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24491 if (C->getZExtValue() <= 0xffffffff)
24492 weight = CW_Constant;
24499 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24500 /// with another that has more specific requirements based on the type of the
24501 /// corresponding operand.
24502 const char *X86TargetLowering::
24503 LowerXConstraint(EVT ConstraintVT) const {
24504 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24505 // 'f' like normal targets.
24506 if (ConstraintVT.isFloatingPoint()) {
24507 if (Subtarget->hasSSE2())
24509 if (Subtarget->hasSSE1())
24513 return TargetLowering::LowerXConstraint(ConstraintVT);
24516 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24517 /// vector. If it is invalid, don't add anything to Ops.
24518 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24519 std::string &Constraint,
24520 std::vector<SDValue>&Ops,
24521 SelectionDAG &DAG) const {
24524 // Only support length 1 constraints for now.
24525 if (Constraint.length() > 1) return;
24527 char ConstraintLetter = Constraint[0];
24528 switch (ConstraintLetter) {
24531 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24532 if (C->getZExtValue() <= 31) {
24533 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24539 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24540 if (C->getZExtValue() <= 63) {
24541 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24547 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24548 if (isInt<8>(C->getSExtValue())) {
24549 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24555 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24556 if (C->getZExtValue() <= 255) {
24557 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24563 // 32-bit signed value
24564 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24565 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24566 C->getSExtValue())) {
24567 // Widen to 64 bits here to get it sign extended.
24568 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24571 // FIXME gcc accepts some relocatable values here too, but only in certain
24572 // memory models; it's complicated.
24577 // 32-bit unsigned value
24578 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24579 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24580 C->getZExtValue())) {
24581 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24585 // FIXME gcc accepts some relocatable values here too, but only in certain
24586 // memory models; it's complicated.
24590 // Literal immediates are always ok.
24591 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24592 // Widen to 64 bits here to get it sign extended.
24593 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24597 // In any sort of PIC mode addresses need to be computed at runtime by
24598 // adding in a register or some sort of table lookup. These can't
24599 // be used as immediates.
24600 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24603 // If we are in non-pic codegen mode, we allow the address of a global (with
24604 // an optional displacement) to be used with 'i'.
24605 GlobalAddressSDNode *GA = nullptr;
24606 int64_t Offset = 0;
24608 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24610 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24611 Offset += GA->getOffset();
24613 } else if (Op.getOpcode() == ISD::ADD) {
24614 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24615 Offset += C->getZExtValue();
24616 Op = Op.getOperand(0);
24619 } else if (Op.getOpcode() == ISD::SUB) {
24620 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24621 Offset += -C->getZExtValue();
24622 Op = Op.getOperand(0);
24627 // Otherwise, this isn't something we can handle, reject it.
24631 const GlobalValue *GV = GA->getGlobal();
24632 // If we require an extra load to get this address, as in PIC mode, we
24633 // can't accept it.
24634 if (isGlobalStubReference(
24635 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24638 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24639 GA->getValueType(0), Offset);
24644 if (Result.getNode()) {
24645 Ops.push_back(Result);
24648 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24651 std::pair<unsigned, const TargetRegisterClass*>
24652 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
24654 // First, see if this is a constraint that directly corresponds to an LLVM
24656 if (Constraint.size() == 1) {
24657 // GCC Constraint Letters
24658 switch (Constraint[0]) {
24660 // TODO: Slight differences here in allocation order and leaving
24661 // RIP in the class. Do they matter any more here than they do
24662 // in the normal allocation?
24663 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24664 if (Subtarget->is64Bit()) {
24665 if (VT == MVT::i32 || VT == MVT::f32)
24666 return std::make_pair(0U, &X86::GR32RegClass);
24667 if (VT == MVT::i16)
24668 return std::make_pair(0U, &X86::GR16RegClass);
24669 if (VT == MVT::i8 || VT == MVT::i1)
24670 return std::make_pair(0U, &X86::GR8RegClass);
24671 if (VT == MVT::i64 || VT == MVT::f64)
24672 return std::make_pair(0U, &X86::GR64RegClass);
24675 // 32-bit fallthrough
24676 case 'Q': // Q_REGS
24677 if (VT == MVT::i32 || VT == MVT::f32)
24678 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24679 if (VT == MVT::i16)
24680 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24681 if (VT == MVT::i8 || VT == MVT::i1)
24682 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24683 if (VT == MVT::i64)
24684 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24686 case 'r': // GENERAL_REGS
24687 case 'l': // INDEX_REGS
24688 if (VT == MVT::i8 || VT == MVT::i1)
24689 return std::make_pair(0U, &X86::GR8RegClass);
24690 if (VT == MVT::i16)
24691 return std::make_pair(0U, &X86::GR16RegClass);
24692 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24693 return std::make_pair(0U, &X86::GR32RegClass);
24694 return std::make_pair(0U, &X86::GR64RegClass);
24695 case 'R': // LEGACY_REGS
24696 if (VT == MVT::i8 || VT == MVT::i1)
24697 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24698 if (VT == MVT::i16)
24699 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24700 if (VT == MVT::i32 || !Subtarget->is64Bit())
24701 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24702 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24703 case 'f': // FP Stack registers.
24704 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24705 // value to the correct fpstack register class.
24706 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24707 return std::make_pair(0U, &X86::RFP32RegClass);
24708 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24709 return std::make_pair(0U, &X86::RFP64RegClass);
24710 return std::make_pair(0U, &X86::RFP80RegClass);
24711 case 'y': // MMX_REGS if MMX allowed.
24712 if (!Subtarget->hasMMX()) break;
24713 return std::make_pair(0U, &X86::VR64RegClass);
24714 case 'Y': // SSE_REGS if SSE2 allowed
24715 if (!Subtarget->hasSSE2()) break;
24717 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24718 if (!Subtarget->hasSSE1()) break;
24720 switch (VT.SimpleTy) {
24722 // Scalar SSE types.
24725 return std::make_pair(0U, &X86::FR32RegClass);
24728 return std::make_pair(0U, &X86::FR64RegClass);
24736 return std::make_pair(0U, &X86::VR128RegClass);
24744 return std::make_pair(0U, &X86::VR256RegClass);
24749 return std::make_pair(0U, &X86::VR512RegClass);
24755 // Use the default implementation in TargetLowering to convert the register
24756 // constraint into a member of a register class.
24757 std::pair<unsigned, const TargetRegisterClass*> Res;
24758 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
24760 // Not found as a standard register?
24762 // Map st(0) -> st(7) -> ST0
24763 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24764 tolower(Constraint[1]) == 's' &&
24765 tolower(Constraint[2]) == 't' &&
24766 Constraint[3] == '(' &&
24767 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24768 Constraint[5] == ')' &&
24769 Constraint[6] == '}') {
24771 Res.first = X86::FP0+Constraint[4]-'0';
24772 Res.second = &X86::RFP80RegClass;
24776 // GCC allows "st(0)" to be called just plain "st".
24777 if (StringRef("{st}").equals_lower(Constraint)) {
24778 Res.first = X86::FP0;
24779 Res.second = &X86::RFP80RegClass;
24784 if (StringRef("{flags}").equals_lower(Constraint)) {
24785 Res.first = X86::EFLAGS;
24786 Res.second = &X86::CCRRegClass;
24790 // 'A' means EAX + EDX.
24791 if (Constraint == "A") {
24792 Res.first = X86::EAX;
24793 Res.second = &X86::GR32_ADRegClass;
24799 // Otherwise, check to see if this is a register class of the wrong value
24800 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24801 // turn into {ax},{dx}.
24802 if (Res.second->hasType(VT))
24803 return Res; // Correct type already, nothing to do.
24805 // All of the single-register GCC register classes map their values onto
24806 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24807 // really want an 8-bit or 32-bit register, map to the appropriate register
24808 // class and return the appropriate register.
24809 if (Res.second == &X86::GR16RegClass) {
24810 if (VT == MVT::i8 || VT == MVT::i1) {
24811 unsigned DestReg = 0;
24812 switch (Res.first) {
24814 case X86::AX: DestReg = X86::AL; break;
24815 case X86::DX: DestReg = X86::DL; break;
24816 case X86::CX: DestReg = X86::CL; break;
24817 case X86::BX: DestReg = X86::BL; break;
24820 Res.first = DestReg;
24821 Res.second = &X86::GR8RegClass;
24823 } else if (VT == MVT::i32 || VT == MVT::f32) {
24824 unsigned DestReg = 0;
24825 switch (Res.first) {
24827 case X86::AX: DestReg = X86::EAX; break;
24828 case X86::DX: DestReg = X86::EDX; break;
24829 case X86::CX: DestReg = X86::ECX; break;
24830 case X86::BX: DestReg = X86::EBX; break;
24831 case X86::SI: DestReg = X86::ESI; break;
24832 case X86::DI: DestReg = X86::EDI; break;
24833 case X86::BP: DestReg = X86::EBP; break;
24834 case X86::SP: DestReg = X86::ESP; break;
24837 Res.first = DestReg;
24838 Res.second = &X86::GR32RegClass;
24840 } else if (VT == MVT::i64 || VT == MVT::f64) {
24841 unsigned DestReg = 0;
24842 switch (Res.first) {
24844 case X86::AX: DestReg = X86::RAX; break;
24845 case X86::DX: DestReg = X86::RDX; break;
24846 case X86::CX: DestReg = X86::RCX; break;
24847 case X86::BX: DestReg = X86::RBX; break;
24848 case X86::SI: DestReg = X86::RSI; break;
24849 case X86::DI: DestReg = X86::RDI; break;
24850 case X86::BP: DestReg = X86::RBP; break;
24851 case X86::SP: DestReg = X86::RSP; break;
24854 Res.first = DestReg;
24855 Res.second = &X86::GR64RegClass;
24858 } else if (Res.second == &X86::FR32RegClass ||
24859 Res.second == &X86::FR64RegClass ||
24860 Res.second == &X86::VR128RegClass ||
24861 Res.second == &X86::VR256RegClass ||
24862 Res.second == &X86::FR32XRegClass ||
24863 Res.second == &X86::FR64XRegClass ||
24864 Res.second == &X86::VR128XRegClass ||
24865 Res.second == &X86::VR256XRegClass ||
24866 Res.second == &X86::VR512RegClass) {
24867 // Handle references to XMM physical registers that got mapped into the
24868 // wrong class. This can happen with constraints like {xmm0} where the
24869 // target independent register mapper will just pick the first match it can
24870 // find, ignoring the required type.
24872 if (VT == MVT::f32 || VT == MVT::i32)
24873 Res.second = &X86::FR32RegClass;
24874 else if (VT == MVT::f64 || VT == MVT::i64)
24875 Res.second = &X86::FR64RegClass;
24876 else if (X86::VR128RegClass.hasType(VT))
24877 Res.second = &X86::VR128RegClass;
24878 else if (X86::VR256RegClass.hasType(VT))
24879 Res.second = &X86::VR256RegClass;
24880 else if (X86::VR512RegClass.hasType(VT))
24881 Res.second = &X86::VR512RegClass;
24887 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
24889 // Scaling factors are not free at all.
24890 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
24891 // will take 2 allocations in the out of order engine instead of 1
24892 // for plain addressing mode, i.e. inst (reg1).
24894 // vaddps (%rsi,%drx), %ymm0, %ymm1
24895 // Requires two allocations (one for the load, one for the computation)
24897 // vaddps (%rsi), %ymm0, %ymm1
24898 // Requires just 1 allocation, i.e., freeing allocations for other operations
24899 // and having less micro operations to execute.
24901 // For some X86 architectures, this is even worse because for instance for
24902 // stores, the complex addressing mode forces the instruction to use the
24903 // "load" ports instead of the dedicated "store" port.
24904 // E.g., on Haswell:
24905 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
24906 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
24907 if (isLegalAddressingMode(AM, Ty))
24908 // Scale represents reg2 * scale, thus account for 1
24909 // as soon as we use a second register.
24910 return AM.Scale != 0;
24914 bool X86TargetLowering::isTargetFTOL() const {
24915 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();