1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/ADT/VariadicFunction.h"
29 #include "llvm/CodeGen/IntrinsicLowering.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 static cl::opt<int> ReciprocalEstimateRefinementSteps(
71 "x86-recip-refinement-steps", cl::init(1),
72 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
73 "result of the hardware reciprocal estimate instruction."),
76 // Forward declarations.
77 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
80 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
81 SelectionDAG &DAG, SDLoc dl,
82 unsigned vectorWidth) {
83 assert((vectorWidth == 128 || vectorWidth == 256) &&
84 "Unsupported vector width");
85 EVT VT = Vec.getValueType();
86 EVT ElVT = VT.getVectorElementType();
87 unsigned Factor = VT.getSizeInBits()/vectorWidth;
88 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
89 VT.getVectorNumElements()/Factor);
91 // Extract from UNDEF is UNDEF.
92 if (Vec.getOpcode() == ISD::UNDEF)
93 return DAG.getUNDEF(ResultVT);
95 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
96 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
98 // This is the index of the first element of the vectorWidth-bit chunk
100 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
103 // If the input is a buildvector just emit a smaller one.
104 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
105 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
106 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
109 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
110 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
113 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
114 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
115 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
116 /// instructions or a simple subregister reference. Idx is an index in the
117 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
118 /// lowering EXTRACT_VECTOR_ELT operations easier.
119 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
120 SelectionDAG &DAG, SDLoc dl) {
121 assert((Vec.getValueType().is256BitVector() ||
122 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
123 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
126 /// Generate a DAG to grab 256-bits from a 512-bit vector.
127 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
128 SelectionDAG &DAG, SDLoc dl) {
129 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
133 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
134 unsigned IdxVal, SelectionDAG &DAG,
135 SDLoc dl, unsigned vectorWidth) {
136 assert((vectorWidth == 128 || vectorWidth == 256) &&
137 "Unsupported vector width");
138 // Inserting UNDEF is Result
139 if (Vec.getOpcode() == ISD::UNDEF)
141 EVT VT = Vec.getValueType();
142 EVT ElVT = VT.getVectorElementType();
143 EVT ResultVT = Result.getValueType();
145 // Insert the relevant vectorWidth bits.
146 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
148 // This is the index of the first element of the vectorWidth-bit chunk
150 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
153 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
154 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
157 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
158 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
159 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
160 /// simple superregister reference. Idx is an index in the 128 bits
161 /// we want. It need not be aligned to a 128-bit boundary. That makes
162 /// lowering INSERT_VECTOR_ELT operations easier.
163 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
164 SelectionDAG &DAG,SDLoc dl) {
165 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
166 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
169 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
170 SelectionDAG &DAG, SDLoc dl) {
171 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
172 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
175 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
176 /// instructions. This is used because creating CONCAT_VECTOR nodes of
177 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
178 /// large BUILD_VECTORS.
179 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
180 unsigned NumElems, SelectionDAG &DAG,
182 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
183 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
186 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
187 unsigned NumElems, SelectionDAG &DAG,
189 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
190 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
193 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
194 const X86Subtarget &STI)
195 : TargetLowering(TM), Subtarget(&STI) {
196 X86ScalarSSEf64 = Subtarget->hasSSE2();
197 X86ScalarSSEf32 = Subtarget->hasSSE1();
198 TD = getDataLayout();
200 // Set up the TargetLowering object.
201 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
203 // X86 is weird. It always uses i8 for shift amounts and setcc results.
204 setBooleanContents(ZeroOrOneBooleanContent);
205 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
206 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
208 // For 64-bit, since we have so many registers, use the ILP scheduler.
209 // For 32-bit, use the register pressure specific scheduling.
210 // For Atom, always use ILP scheduling.
211 if (Subtarget->isAtom())
212 setSchedulingPreference(Sched::ILP);
213 else if (Subtarget->is64Bit())
214 setSchedulingPreference(Sched::ILP);
216 setSchedulingPreference(Sched::RegPressure);
217 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
218 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
220 // Bypass expensive divides on Atom when compiling with O2.
221 if (TM.getOptLevel() >= CodeGenOpt::Default) {
222 if (Subtarget->hasSlowDivide32())
223 addBypassSlowDiv(32, 8);
224 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
225 addBypassSlowDiv(64, 16);
228 if (Subtarget->isTargetKnownWindowsMSVC()) {
229 // Setup Windows compiler runtime calls.
230 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
231 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
232 setLibcallName(RTLIB::SREM_I64, "_allrem");
233 setLibcallName(RTLIB::UREM_I64, "_aullrem");
234 setLibcallName(RTLIB::MUL_I64, "_allmul");
235 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
236 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
237 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
238 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
239 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
241 // The _ftol2 runtime function has an unusual calling conv, which
242 // is modeled by a special pseudo-instruction.
243 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
244 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
245 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
246 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
249 if (Subtarget->isTargetDarwin()) {
250 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
251 setUseUnderscoreSetJmp(false);
252 setUseUnderscoreLongJmp(false);
253 } else if (Subtarget->isTargetWindowsGNU()) {
254 // MS runtime is weird: it exports _setjmp, but longjmp!
255 setUseUnderscoreSetJmp(true);
256 setUseUnderscoreLongJmp(false);
258 setUseUnderscoreSetJmp(true);
259 setUseUnderscoreLongJmp(true);
262 // Set up the register classes.
263 addRegisterClass(MVT::i8, &X86::GR8RegClass);
264 addRegisterClass(MVT::i16, &X86::GR16RegClass);
265 addRegisterClass(MVT::i32, &X86::GR32RegClass);
266 if (Subtarget->is64Bit())
267 addRegisterClass(MVT::i64, &X86::GR64RegClass);
269 for (MVT VT : MVT::integer_valuetypes())
270 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
272 // We don't accept any truncstore of integer registers.
273 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
274 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
275 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
276 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
277 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
278 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
280 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
282 // SETOEQ and SETUNE require checking two conditions.
283 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
284 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
285 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
286 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
287 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
288 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
290 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
292 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
293 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
294 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
296 if (Subtarget->is64Bit()) {
297 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
298 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
299 } else if (!TM.Options.UseSoftFloat) {
300 // We have an algorithm for SSE2->double, and we turn this into a
301 // 64-bit FILD followed by conditional FADD for other targets.
302 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
303 // We have an algorithm for SSE2, and we turn this into a 64-bit
304 // FILD for other targets.
305 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
308 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
310 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
311 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
313 if (!TM.Options.UseSoftFloat) {
314 // SSE has no i16 to fp conversion, only i32
315 if (X86ScalarSSEf32) {
316 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
317 // f32 and f64 cases are Legal, f80 case is not
318 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
320 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
321 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
324 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
325 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
328 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
329 // are Legal, f80 is custom lowered.
330 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
331 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
333 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
335 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
336 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
338 if (X86ScalarSSEf32) {
339 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
340 // f32 and f64 cases are Legal, f80 case is not
341 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
343 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
344 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
347 // Handle FP_TO_UINT by promoting the destination to a larger signed
349 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
350 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
351 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
353 if (Subtarget->is64Bit()) {
354 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
355 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
356 } else if (!TM.Options.UseSoftFloat) {
357 // Since AVX is a superset of SSE3, only check for SSE here.
358 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
359 // Expand FP_TO_UINT into a select.
360 // FIXME: We would like to use a Custom expander here eventually to do
361 // the optimal thing for SSE vs. the default expansion in the legalizer.
362 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
364 // With SSE3 we can use fisttpll to convert to a signed i64; without
365 // SSE, we're stuck with a fistpll.
366 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
369 if (isTargetFTOL()) {
370 // Use the _ftol2 runtime function, which has a pseudo-instruction
371 // to handle its weird calling convention.
372 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
375 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
376 if (!X86ScalarSSEf64) {
377 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
378 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
379 if (Subtarget->is64Bit()) {
380 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
381 // Without SSE, i64->f64 goes through memory.
382 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
386 // Scalar integer divide and remainder are lowered to use operations that
387 // produce two results, to match the available instructions. This exposes
388 // the two-result form to trivial CSE, which is able to combine x/y and x%y
389 // into a single instruction.
391 // Scalar integer multiply-high is also lowered to use two-result
392 // operations, to match the available instructions. However, plain multiply
393 // (low) operations are left as Legal, as there are single-result
394 // instructions for this in x86. Using the two-result multiply instructions
395 // when both high and low results are needed must be arranged by dagcombine.
396 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
398 setOperationAction(ISD::MULHS, VT, Expand);
399 setOperationAction(ISD::MULHU, VT, Expand);
400 setOperationAction(ISD::SDIV, VT, Expand);
401 setOperationAction(ISD::UDIV, VT, Expand);
402 setOperationAction(ISD::SREM, VT, Expand);
403 setOperationAction(ISD::UREM, VT, Expand);
405 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
406 setOperationAction(ISD::ADDC, VT, Custom);
407 setOperationAction(ISD::ADDE, VT, Custom);
408 setOperationAction(ISD::SUBC, VT, Custom);
409 setOperationAction(ISD::SUBE, VT, Custom);
412 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
413 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
414 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
415 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
416 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
417 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
418 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
419 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
420 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
421 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
422 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
423 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
424 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
425 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
426 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
427 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
428 if (Subtarget->is64Bit())
429 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
430 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
431 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
432 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
433 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
434 setOperationAction(ISD::FREM , MVT::f32 , Expand);
435 setOperationAction(ISD::FREM , MVT::f64 , Expand);
436 setOperationAction(ISD::FREM , MVT::f80 , Expand);
437 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
439 // Promote the i8 variants and force them on up to i32 which has a shorter
441 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
442 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
443 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
444 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
445 if (Subtarget->hasBMI()) {
446 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
447 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
448 if (Subtarget->is64Bit())
449 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
451 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
452 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
453 if (Subtarget->is64Bit())
454 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
457 if (Subtarget->hasLZCNT()) {
458 // When promoting the i8 variants, force them to i32 for a shorter
460 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
461 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
462 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
463 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
464 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
465 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
466 if (Subtarget->is64Bit())
467 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
469 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
470 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
471 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
472 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
473 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
474 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
475 if (Subtarget->is64Bit()) {
476 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
477 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
481 // Special handling for half-precision floating point conversions.
482 // If we don't have F16C support, then lower half float conversions
483 // into library calls.
484 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
485 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
486 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
489 // There's never any support for operations beyond MVT::f32.
490 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
491 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
492 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
493 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
495 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
496 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
497 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
498 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
499 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
500 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
502 if (Subtarget->hasPOPCNT()) {
503 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
505 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
506 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
507 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
508 if (Subtarget->is64Bit())
509 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
512 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
514 if (!Subtarget->hasMOVBE())
515 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
517 // These should be promoted to a larger select which is supported.
518 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
519 // X86 wants to expand cmov itself.
520 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
521 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
522 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
523 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
524 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
525 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
526 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
527 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
528 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
529 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
530 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
531 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
532 if (Subtarget->is64Bit()) {
533 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
534 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
536 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
537 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
538 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
539 // support continuation, user-level threading, and etc.. As a result, no
540 // other SjLj exception interfaces are implemented and please don't build
541 // your own exception handling based on them.
542 // LLVM/Clang supports zero-cost DWARF exception handling.
543 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
544 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
547 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
548 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
549 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
550 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
551 if (Subtarget->is64Bit())
552 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
553 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
554 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
555 if (Subtarget->is64Bit()) {
556 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
557 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
558 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
559 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
560 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
562 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
563 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
564 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
565 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
566 if (Subtarget->is64Bit()) {
567 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
568 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
569 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
572 if (Subtarget->hasSSE1())
573 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
575 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
577 // Expand certain atomics
578 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
580 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
582 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
585 if (Subtarget->hasCmpxchg16b()) {
586 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
589 // FIXME - use subtarget debug flags
590 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
591 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
592 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
595 if (Subtarget->is64Bit()) {
596 setExceptionPointerRegister(X86::RAX);
597 setExceptionSelectorRegister(X86::RDX);
599 setExceptionPointerRegister(X86::EAX);
600 setExceptionSelectorRegister(X86::EDX);
602 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
603 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
605 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
606 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
608 setOperationAction(ISD::TRAP, MVT::Other, Legal);
609 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
611 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
612 setOperationAction(ISD::VASTART , MVT::Other, Custom);
613 setOperationAction(ISD::VAEND , MVT::Other, Expand);
614 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
615 // TargetInfo::X86_64ABIBuiltinVaList
616 setOperationAction(ISD::VAARG , MVT::Other, Custom);
617 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
619 // TargetInfo::CharPtrBuiltinVaList
620 setOperationAction(ISD::VAARG , MVT::Other, Expand);
621 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
624 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
625 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
627 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
629 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
630 // f32 and f64 use SSE.
631 // Set up the FP register classes.
632 addRegisterClass(MVT::f32, &X86::FR32RegClass);
633 addRegisterClass(MVT::f64, &X86::FR64RegClass);
635 // Use ANDPD to simulate FABS.
636 setOperationAction(ISD::FABS , MVT::f64, Custom);
637 setOperationAction(ISD::FABS , MVT::f32, Custom);
639 // Use XORP to simulate FNEG.
640 setOperationAction(ISD::FNEG , MVT::f64, Custom);
641 setOperationAction(ISD::FNEG , MVT::f32, Custom);
643 // Use ANDPD and ORPD to simulate FCOPYSIGN.
644 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
645 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
647 // Lower this to FGETSIGNx86 plus an AND.
648 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
649 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
651 // We don't support sin/cos/fmod
652 setOperationAction(ISD::FSIN , MVT::f64, Expand);
653 setOperationAction(ISD::FCOS , MVT::f64, Expand);
654 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
655 setOperationAction(ISD::FSIN , MVT::f32, Expand);
656 setOperationAction(ISD::FCOS , MVT::f32, Expand);
657 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
659 // Expand FP immediates into loads from the stack, except for the special
661 addLegalFPImmediate(APFloat(+0.0)); // xorpd
662 addLegalFPImmediate(APFloat(+0.0f)); // xorps
663 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
664 // Use SSE for f32, x87 for f64.
665 // Set up the FP register classes.
666 addRegisterClass(MVT::f32, &X86::FR32RegClass);
667 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
669 // Use ANDPS to simulate FABS.
670 setOperationAction(ISD::FABS , MVT::f32, Custom);
672 // Use XORP to simulate FNEG.
673 setOperationAction(ISD::FNEG , MVT::f32, Custom);
675 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
677 // Use ANDPS and ORPS to simulate FCOPYSIGN.
678 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
679 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
681 // We don't support sin/cos/fmod
682 setOperationAction(ISD::FSIN , MVT::f32, Expand);
683 setOperationAction(ISD::FCOS , MVT::f32, Expand);
684 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
686 // Special cases we handle for FP constants.
687 addLegalFPImmediate(APFloat(+0.0f)); // xorps
688 addLegalFPImmediate(APFloat(+0.0)); // FLD0
689 addLegalFPImmediate(APFloat(+1.0)); // FLD1
690 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
691 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
693 if (!TM.Options.UnsafeFPMath) {
694 setOperationAction(ISD::FSIN , MVT::f64, Expand);
695 setOperationAction(ISD::FCOS , MVT::f64, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
698 } else if (!TM.Options.UseSoftFloat) {
699 // f32 and f64 in x87.
700 // Set up the FP register classes.
701 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
702 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
704 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
705 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
706 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
707 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
709 if (!TM.Options.UnsafeFPMath) {
710 setOperationAction(ISD::FSIN , MVT::f64, Expand);
711 setOperationAction(ISD::FSIN , MVT::f32, Expand);
712 setOperationAction(ISD::FCOS , MVT::f64, Expand);
713 setOperationAction(ISD::FCOS , MVT::f32, Expand);
714 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
715 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
717 addLegalFPImmediate(APFloat(+0.0)); // FLD0
718 addLegalFPImmediate(APFloat(+1.0)); // FLD1
719 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
720 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
721 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
722 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
723 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
724 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
727 // We don't support FMA.
728 setOperationAction(ISD::FMA, MVT::f64, Expand);
729 setOperationAction(ISD::FMA, MVT::f32, Expand);
731 // Long double always uses X87.
732 if (!TM.Options.UseSoftFloat) {
733 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
734 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
735 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
737 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
738 addLegalFPImmediate(TmpFlt); // FLD0
740 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
743 APFloat TmpFlt2(+1.0);
744 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
746 addLegalFPImmediate(TmpFlt2); // FLD1
747 TmpFlt2.changeSign();
748 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
751 if (!TM.Options.UnsafeFPMath) {
752 setOperationAction(ISD::FSIN , MVT::f80, Expand);
753 setOperationAction(ISD::FCOS , MVT::f80, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
757 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
758 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
759 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
760 setOperationAction(ISD::FRINT, MVT::f80, Expand);
761 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
762 setOperationAction(ISD::FMA, MVT::f80, Expand);
765 // Always use a library call for pow.
766 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
767 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
768 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
770 setOperationAction(ISD::FLOG, MVT::f80, Expand);
771 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
772 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
773 setOperationAction(ISD::FEXP, MVT::f80, Expand);
774 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
775 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
776 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
778 // First set operation action for all vector types to either promote
779 // (for widening) or expand (for scalarization). Then we will selectively
780 // turn on ones that can be effectively codegen'd.
781 for (MVT VT : MVT::vector_valuetypes()) {
782 setOperationAction(ISD::ADD , VT, Expand);
783 setOperationAction(ISD::SUB , VT, Expand);
784 setOperationAction(ISD::FADD, VT, Expand);
785 setOperationAction(ISD::FNEG, VT, Expand);
786 setOperationAction(ISD::FSUB, VT, Expand);
787 setOperationAction(ISD::MUL , VT, Expand);
788 setOperationAction(ISD::FMUL, VT, Expand);
789 setOperationAction(ISD::SDIV, VT, Expand);
790 setOperationAction(ISD::UDIV, VT, Expand);
791 setOperationAction(ISD::FDIV, VT, Expand);
792 setOperationAction(ISD::SREM, VT, Expand);
793 setOperationAction(ISD::UREM, VT, Expand);
794 setOperationAction(ISD::LOAD, VT, Expand);
795 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
796 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
797 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
798 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
799 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
800 setOperationAction(ISD::FABS, VT, Expand);
801 setOperationAction(ISD::FSIN, VT, Expand);
802 setOperationAction(ISD::FSINCOS, VT, Expand);
803 setOperationAction(ISD::FCOS, VT, Expand);
804 setOperationAction(ISD::FSINCOS, VT, Expand);
805 setOperationAction(ISD::FREM, VT, Expand);
806 setOperationAction(ISD::FMA, VT, Expand);
807 setOperationAction(ISD::FPOWI, VT, Expand);
808 setOperationAction(ISD::FSQRT, VT, Expand);
809 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
810 setOperationAction(ISD::FFLOOR, VT, Expand);
811 setOperationAction(ISD::FCEIL, VT, Expand);
812 setOperationAction(ISD::FTRUNC, VT, Expand);
813 setOperationAction(ISD::FRINT, VT, Expand);
814 setOperationAction(ISD::FNEARBYINT, VT, Expand);
815 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
816 setOperationAction(ISD::MULHS, VT, Expand);
817 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
818 setOperationAction(ISD::MULHU, VT, Expand);
819 setOperationAction(ISD::SDIVREM, VT, Expand);
820 setOperationAction(ISD::UDIVREM, VT, Expand);
821 setOperationAction(ISD::FPOW, VT, Expand);
822 setOperationAction(ISD::CTPOP, VT, Expand);
823 setOperationAction(ISD::CTTZ, VT, Expand);
824 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
825 setOperationAction(ISD::CTLZ, VT, Expand);
826 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
827 setOperationAction(ISD::SHL, VT, Expand);
828 setOperationAction(ISD::SRA, VT, Expand);
829 setOperationAction(ISD::SRL, VT, Expand);
830 setOperationAction(ISD::ROTL, VT, Expand);
831 setOperationAction(ISD::ROTR, VT, Expand);
832 setOperationAction(ISD::BSWAP, VT, Expand);
833 setOperationAction(ISD::SETCC, VT, Expand);
834 setOperationAction(ISD::FLOG, VT, Expand);
835 setOperationAction(ISD::FLOG2, VT, Expand);
836 setOperationAction(ISD::FLOG10, VT, Expand);
837 setOperationAction(ISD::FEXP, VT, Expand);
838 setOperationAction(ISD::FEXP2, VT, Expand);
839 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
840 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
841 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
842 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
843 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
844 setOperationAction(ISD::TRUNCATE, VT, Expand);
845 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
846 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
847 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
848 setOperationAction(ISD::VSELECT, VT, Expand);
849 setOperationAction(ISD::SELECT_CC, VT, Expand);
850 for (MVT InnerVT : MVT::vector_valuetypes()) {
851 setTruncStoreAction(InnerVT, VT, Expand);
853 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
854 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
856 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
857 // types, we have to deal with them whether we ask for Expansion or not.
858 // Setting Expand causes its own optimisation problems though, so leave
860 if (VT.getVectorElementType() == MVT::i1)
861 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
865 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
866 // with -msoft-float, disable use of MMX as well.
867 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
868 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
869 // No operations on x86mmx supported, everything uses intrinsics.
872 // MMX-sized vectors (other than x86mmx) are expected to be expanded
873 // into smaller operations.
874 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
875 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
876 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
877 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
878 setOperationAction(ISD::AND, MVT::v8i8, Expand);
879 setOperationAction(ISD::AND, MVT::v4i16, Expand);
880 setOperationAction(ISD::AND, MVT::v2i32, Expand);
881 setOperationAction(ISD::AND, MVT::v1i64, Expand);
882 setOperationAction(ISD::OR, MVT::v8i8, Expand);
883 setOperationAction(ISD::OR, MVT::v4i16, Expand);
884 setOperationAction(ISD::OR, MVT::v2i32, Expand);
885 setOperationAction(ISD::OR, MVT::v1i64, Expand);
886 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
887 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
888 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
889 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
890 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
891 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
892 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
893 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
895 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
896 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
897 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
898 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
899 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
900 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
901 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
902 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
904 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
905 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
907 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
908 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
909 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
910 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
911 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
912 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
913 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
914 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
915 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
916 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
917 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
918 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
919 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
920 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
923 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
924 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
926 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
927 // registers cannot be used even for integer operations.
928 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
929 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
930 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
931 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
933 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
934 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
935 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
936 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
937 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
938 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
939 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
940 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
941 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
942 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
943 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
944 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
945 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
946 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
947 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
948 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
949 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
950 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
951 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
952 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
953 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
954 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
956 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
958 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
959 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
961 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
967 // Only provide customized ctpop vector bit twiddling for vector types we
968 // know to perform better than using the popcnt instructions on each vector
969 // element. If popcnt isn't supported, always provide the custom version.
970 if (!Subtarget->hasPOPCNT()) {
971 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
972 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
975 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
976 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
977 MVT VT = (MVT::SimpleValueType)i;
978 // Do not attempt to custom lower non-power-of-2 vectors
979 if (!isPowerOf2_32(VT.getVectorNumElements()))
981 // Do not attempt to custom lower non-128-bit vectors
982 if (!VT.is128BitVector())
984 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
985 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
986 setOperationAction(ISD::VSELECT, VT, Custom);
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
990 // We support custom legalizing of sext and anyext loads for specific
991 // memory vector types which we can load as a scalar (or sequence of
992 // scalars) and extend in-register to a legal 128-bit vector type. For sext
993 // loads these must work with a single scalar load.
994 for (MVT VT : MVT::integer_vector_valuetypes()) {
995 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
996 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
997 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
998 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
999 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
1000 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
1001 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
1002 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
1003 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
1006 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1007 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1008 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1009 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1010 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1011 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1012 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1013 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1015 if (Subtarget->is64Bit()) {
1016 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1020 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1021 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1022 MVT VT = (MVT::SimpleValueType)i;
1024 // Do not attempt to promote non-128-bit vectors
1025 if (!VT.is128BitVector())
1028 setOperationAction(ISD::AND, VT, Promote);
1029 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1030 setOperationAction(ISD::OR, VT, Promote);
1031 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1032 setOperationAction(ISD::XOR, VT, Promote);
1033 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1034 setOperationAction(ISD::LOAD, VT, Promote);
1035 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1036 setOperationAction(ISD::SELECT, VT, Promote);
1037 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1040 // Custom lower v2i64 and v2f64 selects.
1041 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1042 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1043 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1044 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1046 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1047 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1049 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1050 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1051 // As there is no 64-bit GPR available, we need build a special custom
1052 // sequence to convert from v2i32 to v2f32.
1053 if (!Subtarget->is64Bit())
1054 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1056 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1057 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1059 for (MVT VT : MVT::fp_vector_valuetypes())
1060 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
1062 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1063 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1064 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1067 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1068 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1069 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1070 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1071 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1072 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1073 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1074 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1075 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1076 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1077 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1079 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1080 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1081 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1082 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1083 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1084 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1085 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1086 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1087 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1088 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1090 // FIXME: Do we need to handle scalar-to-vector here?
1091 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1093 // We directly match byte blends in the backend as they match the VSELECT
1095 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1097 // SSE41 brings specific instructions for doing vector sign extend even in
1098 // cases where we don't have SRA.
1099 for (MVT VT : MVT::integer_vector_valuetypes()) {
1100 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
1101 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
1102 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
1105 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
1106 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
1107 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1108 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1109 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1110 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1111 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1113 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
1114 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1115 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1116 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1117 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1118 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1120 // i8 and i16 vectors are custom because the source register and source
1121 // source memory operand types are not the same width. f32 vectors are
1122 // custom since the immediate controlling the insert encodes additional
1124 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1125 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1126 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1127 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1129 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1130 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1132 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1134 // FIXME: these should be Legal, but that's only for the case where
1135 // the index is constant. For now custom expand to deal with that.
1136 if (Subtarget->is64Bit()) {
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1138 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1142 if (Subtarget->hasSSE2()) {
1143 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1144 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1146 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1147 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1149 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1150 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1152 // In the customized shift lowering, the legal cases in AVX2 will be
1154 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1155 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1157 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1158 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1160 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1163 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1164 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1165 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1166 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1167 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1168 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1169 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1171 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1172 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1173 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1175 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1176 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1177 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1186 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1188 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1189 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1190 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1199 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1201 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1202 // even though v8i16 is a legal type.
1203 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1204 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1205 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1207 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1208 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1209 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1211 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1212 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1214 for (MVT VT : MVT::fp_vector_valuetypes())
1215 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1217 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1218 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1220 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1221 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1223 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1224 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1226 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1227 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1228 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1229 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1231 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1232 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1233 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1235 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1236 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1237 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1238 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1239 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1240 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1241 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1242 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1243 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1244 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1245 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1246 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1248 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1249 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1250 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1251 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1252 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1253 setOperationAction(ISD::FMA, MVT::f32, Legal);
1254 setOperationAction(ISD::FMA, MVT::f64, Legal);
1257 if (Subtarget->hasInt256()) {
1258 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1259 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1260 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1261 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1263 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1264 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1265 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1266 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1268 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1269 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1270 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1271 // Don't lower v32i8 because there is no 128-bit byte mul
1273 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1274 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1275 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1276 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1278 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1279 // when we have a 256bit-wide blend with immediate.
1280 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1282 // Only provide customized ctpop vector bit twiddling for vector types we
1283 // know to perform better than using the popcnt instructions on each
1284 // vector element. If popcnt isn't supported, always provide the custom
1286 if (!Subtarget->hasPOPCNT())
1287 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1289 // Custom CTPOP always performs better on natively supported v8i32
1290 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1292 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1293 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1294 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1295 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1296 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1297 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1298 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1300 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1301 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1302 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1303 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1304 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1305 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1307 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1308 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1309 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1310 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1312 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1313 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1314 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1315 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1317 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1318 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1320 // Don't lower v32i8 because there is no 128-bit byte mul
1323 // In the customized shift lowering, the legal cases in AVX2 will be
1325 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1326 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1328 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1329 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1331 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1333 // Custom lower several nodes for 256-bit types.
1334 for (MVT VT : MVT::vector_valuetypes()) {
1335 if (VT.getScalarSizeInBits() >= 32) {
1336 setOperationAction(ISD::MLOAD, VT, Legal);
1337 setOperationAction(ISD::MSTORE, VT, Legal);
1339 // Extract subvector is special because the value type
1340 // (result) is 128-bit but the source is 256-bit wide.
1341 if (VT.is128BitVector()) {
1342 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1344 // Do not attempt to custom lower other non-256-bit vectors
1345 if (!VT.is256BitVector())
1348 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1349 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1350 setOperationAction(ISD::VSELECT, VT, Custom);
1351 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1352 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1353 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1354 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1355 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1358 if (Subtarget->hasInt256())
1359 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1362 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1363 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1364 MVT VT = (MVT::SimpleValueType)i;
1366 // Do not attempt to promote non-256-bit vectors
1367 if (!VT.is256BitVector())
1370 setOperationAction(ISD::AND, VT, Promote);
1371 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1372 setOperationAction(ISD::OR, VT, Promote);
1373 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1374 setOperationAction(ISD::XOR, VT, Promote);
1375 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1376 setOperationAction(ISD::LOAD, VT, Promote);
1377 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1378 setOperationAction(ISD::SELECT, VT, Promote);
1379 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1383 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1384 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1385 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1386 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1387 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1389 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1390 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1391 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1393 for (MVT VT : MVT::fp_vector_valuetypes())
1394 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1396 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1397 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1398 setOperationAction(ISD::XOR, MVT::i1, Legal);
1399 setOperationAction(ISD::OR, MVT::i1, Legal);
1400 setOperationAction(ISD::AND, MVT::i1, Legal);
1401 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1402 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1403 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1404 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1405 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1407 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1408 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1409 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1410 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1411 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1412 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1414 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1415 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1416 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1417 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1418 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1419 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1420 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1421 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1423 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1424 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1425 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1426 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1427 if (Subtarget->is64Bit()) {
1428 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1429 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1430 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1431 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1433 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1434 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1435 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1436 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1437 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1438 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1439 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1440 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1441 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1442 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1443 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1444 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1445 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1446 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1448 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1449 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1450 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1451 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1452 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1453 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1454 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1455 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1456 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1457 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1459 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1460 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1462 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1463 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1464 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1465 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1466 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1467 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1468 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1469 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1470 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1471 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1473 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1474 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1475 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1476 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1477 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1478 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1480 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1481 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1483 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1485 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1486 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1487 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1488 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1489 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1490 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1491 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1492 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1493 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1495 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1496 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1498 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1499 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1501 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1503 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1504 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1506 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1507 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1509 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1510 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1512 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1513 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1514 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1515 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1516 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1517 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1519 if (Subtarget->hasCDI()) {
1520 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1521 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1524 // Custom lower several nodes.
1525 for (MVT VT : MVT::vector_valuetypes()) {
1526 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1527 // Extract subvector is special because the value type
1528 // (result) is 256/128-bit but the source is 512-bit wide.
1529 if (VT.is128BitVector() || VT.is256BitVector()) {
1530 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1532 if (VT.getVectorElementType() == MVT::i1)
1533 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1535 // Do not attempt to custom lower other non-512-bit vectors
1536 if (!VT.is512BitVector())
1539 if ( EltSize >= 32) {
1540 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1541 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1542 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1543 setOperationAction(ISD::VSELECT, VT, Legal);
1544 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1545 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1546 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1547 setOperationAction(ISD::MLOAD, VT, Legal);
1548 setOperationAction(ISD::MSTORE, VT, Legal);
1551 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1552 MVT VT = (MVT::SimpleValueType)i;
1554 // Do not attempt to promote non-512-bit vectors.
1555 if (!VT.is512BitVector())
1558 setOperationAction(ISD::SELECT, VT, Promote);
1559 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1563 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1564 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1565 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1567 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1568 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1570 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1571 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1572 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1573 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1574 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1575 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1576 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1577 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1578 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1580 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1581 const MVT VT = (MVT::SimpleValueType)i;
1583 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1585 // Do not attempt to promote non-512-bit vectors.
1586 if (!VT.is512BitVector())
1590 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1591 setOperationAction(ISD::VSELECT, VT, Legal);
1596 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1597 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1598 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1600 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1601 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1602 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1604 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1605 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1606 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1607 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1608 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1609 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1612 // We want to custom lower some of our intrinsics.
1613 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1614 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1615 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1616 if (!Subtarget->is64Bit())
1617 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1619 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1620 // handle type legalization for these operations here.
1622 // FIXME: We really should do custom legalization for addition and
1623 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1624 // than generic legalization for 64-bit multiplication-with-overflow, though.
1625 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1626 // Add/Sub/Mul with overflow operations are custom lowered.
1628 setOperationAction(ISD::SADDO, VT, Custom);
1629 setOperationAction(ISD::UADDO, VT, Custom);
1630 setOperationAction(ISD::SSUBO, VT, Custom);
1631 setOperationAction(ISD::USUBO, VT, Custom);
1632 setOperationAction(ISD::SMULO, VT, Custom);
1633 setOperationAction(ISD::UMULO, VT, Custom);
1637 if (!Subtarget->is64Bit()) {
1638 // These libcalls are not available in 32-bit.
1639 setLibcallName(RTLIB::SHL_I128, nullptr);
1640 setLibcallName(RTLIB::SRL_I128, nullptr);
1641 setLibcallName(RTLIB::SRA_I128, nullptr);
1644 // Combine sin / cos into one node or libcall if possible.
1645 if (Subtarget->hasSinCos()) {
1646 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1647 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1648 if (Subtarget->isTargetDarwin()) {
1649 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1650 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1651 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1652 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1656 if (Subtarget->isTargetWin64()) {
1657 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1658 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1659 setOperationAction(ISD::SREM, MVT::i128, Custom);
1660 setOperationAction(ISD::UREM, MVT::i128, Custom);
1661 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1662 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1665 // We have target-specific dag combine patterns for the following nodes:
1666 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1667 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1668 setTargetDAGCombine(ISD::BITCAST);
1669 setTargetDAGCombine(ISD::VSELECT);
1670 setTargetDAGCombine(ISD::SELECT);
1671 setTargetDAGCombine(ISD::SHL);
1672 setTargetDAGCombine(ISD::SRA);
1673 setTargetDAGCombine(ISD::SRL);
1674 setTargetDAGCombine(ISD::OR);
1675 setTargetDAGCombine(ISD::AND);
1676 setTargetDAGCombine(ISD::ADD);
1677 setTargetDAGCombine(ISD::FADD);
1678 setTargetDAGCombine(ISD::FSUB);
1679 setTargetDAGCombine(ISD::FMA);
1680 setTargetDAGCombine(ISD::SUB);
1681 setTargetDAGCombine(ISD::LOAD);
1682 setTargetDAGCombine(ISD::MLOAD);
1683 setTargetDAGCombine(ISD::STORE);
1684 setTargetDAGCombine(ISD::MSTORE);
1685 setTargetDAGCombine(ISD::ZERO_EXTEND);
1686 setTargetDAGCombine(ISD::ANY_EXTEND);
1687 setTargetDAGCombine(ISD::SIGN_EXTEND);
1688 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1689 setTargetDAGCombine(ISD::TRUNCATE);
1690 setTargetDAGCombine(ISD::SINT_TO_FP);
1691 setTargetDAGCombine(ISD::SETCC);
1692 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1693 setTargetDAGCombine(ISD::BUILD_VECTOR);
1694 setTargetDAGCombine(ISD::MUL);
1695 setTargetDAGCombine(ISD::XOR);
1697 computeRegisterProperties();
1699 // On Darwin, -Os means optimize for size without hurting performance,
1700 // do not reduce the limit.
1701 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1702 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1703 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1704 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1705 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1706 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1707 setPrefLoopAlignment(4); // 2^4 bytes.
1709 // Predictable cmov don't hurt on atom because it's in-order.
1710 PredictableSelectIsExpensive = !Subtarget->isAtom();
1711 EnableExtLdPromotion = true;
1712 setPrefFunctionAlignment(4); // 2^4 bytes.
1714 verifyIntrinsicTables();
1717 // This has so far only been implemented for 64-bit MachO.
1718 bool X86TargetLowering::useLoadStackGuardNode() const {
1719 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1722 TargetLoweringBase::LegalizeTypeAction
1723 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1724 if (ExperimentalVectorWideningLegalization &&
1725 VT.getVectorNumElements() != 1 &&
1726 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1727 return TypeWidenVector;
1729 return TargetLoweringBase::getPreferredVectorAction(VT);
1732 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1734 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1736 const unsigned NumElts = VT.getVectorNumElements();
1737 const EVT EltVT = VT.getVectorElementType();
1738 if (VT.is512BitVector()) {
1739 if (Subtarget->hasAVX512())
1740 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1741 EltVT == MVT::f32 || EltVT == MVT::f64)
1743 case 8: return MVT::v8i1;
1744 case 16: return MVT::v16i1;
1746 if (Subtarget->hasBWI())
1747 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1749 case 32: return MVT::v32i1;
1750 case 64: return MVT::v64i1;
1754 if (VT.is256BitVector() || VT.is128BitVector()) {
1755 if (Subtarget->hasVLX())
1756 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1757 EltVT == MVT::f32 || EltVT == MVT::f64)
1759 case 2: return MVT::v2i1;
1760 case 4: return MVT::v4i1;
1761 case 8: return MVT::v8i1;
1763 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1764 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1766 case 8: return MVT::v8i1;
1767 case 16: return MVT::v16i1;
1768 case 32: return MVT::v32i1;
1772 return VT.changeVectorElementTypeToInteger();
1775 /// Helper for getByValTypeAlignment to determine
1776 /// the desired ByVal argument alignment.
1777 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1780 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1781 if (VTy->getBitWidth() == 128)
1783 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1784 unsigned EltAlign = 0;
1785 getMaxByValAlign(ATy->getElementType(), EltAlign);
1786 if (EltAlign > MaxAlign)
1787 MaxAlign = EltAlign;
1788 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1789 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1790 unsigned EltAlign = 0;
1791 getMaxByValAlign(STy->getElementType(i), EltAlign);
1792 if (EltAlign > MaxAlign)
1793 MaxAlign = EltAlign;
1800 /// Return the desired alignment for ByVal aggregate
1801 /// function arguments in the caller parameter area. For X86, aggregates
1802 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1803 /// are at 4-byte boundaries.
1804 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1805 if (Subtarget->is64Bit()) {
1806 // Max of 8 and alignment of type.
1807 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1814 if (Subtarget->hasSSE1())
1815 getMaxByValAlign(Ty, Align);
1819 /// Returns the target specific optimal type for load
1820 /// and store operations as a result of memset, memcpy, and memmove
1821 /// lowering. If DstAlign is zero that means it's safe to destination
1822 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1823 /// means there isn't a need to check it against alignment requirement,
1824 /// probably because the source does not need to be loaded. If 'IsMemset' is
1825 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1826 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1827 /// source is constant so it does not need to be loaded.
1828 /// It returns EVT::Other if the type should be determined using generic
1829 /// target-independent logic.
1831 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1832 unsigned DstAlign, unsigned SrcAlign,
1833 bool IsMemset, bool ZeroMemset,
1835 MachineFunction &MF) const {
1836 const Function *F = MF.getFunction();
1837 if ((!IsMemset || ZeroMemset) &&
1838 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1840 (Subtarget->isUnalignedMemAccessFast() ||
1841 ((DstAlign == 0 || DstAlign >= 16) &&
1842 (SrcAlign == 0 || SrcAlign >= 16)))) {
1844 if (Subtarget->hasInt256())
1846 if (Subtarget->hasFp256())
1849 if (Subtarget->hasSSE2())
1851 if (Subtarget->hasSSE1())
1853 } else if (!MemcpyStrSrc && Size >= 8 &&
1854 !Subtarget->is64Bit() &&
1855 Subtarget->hasSSE2()) {
1856 // Do not use f64 to lower memcpy if source is string constant. It's
1857 // better to use i32 to avoid the loads.
1861 if (Subtarget->is64Bit() && Size >= 8)
1866 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1868 return X86ScalarSSEf32;
1869 else if (VT == MVT::f64)
1870 return X86ScalarSSEf64;
1875 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1880 *Fast = Subtarget->isUnalignedMemAccessFast();
1884 /// Return the entry encoding for a jump table in the
1885 /// current function. The returned value is a member of the
1886 /// MachineJumpTableInfo::JTEntryKind enum.
1887 unsigned X86TargetLowering::getJumpTableEncoding() const {
1888 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1890 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1891 Subtarget->isPICStyleGOT())
1892 return MachineJumpTableInfo::EK_Custom32;
1894 // Otherwise, use the normal jump table encoding heuristics.
1895 return TargetLowering::getJumpTableEncoding();
1899 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1900 const MachineBasicBlock *MBB,
1901 unsigned uid,MCContext &Ctx) const{
1902 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1903 Subtarget->isPICStyleGOT());
1904 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1906 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1907 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1910 /// Returns relocation base for the given PIC jumptable.
1911 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1912 SelectionDAG &DAG) const {
1913 if (!Subtarget->is64Bit())
1914 // This doesn't have SDLoc associated with it, but is not really the
1915 // same as a Register.
1916 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1920 /// This returns the relocation base for the given PIC jumptable,
1921 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1922 const MCExpr *X86TargetLowering::
1923 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1924 MCContext &Ctx) const {
1925 // X86-64 uses RIP relative addressing based on the jump table label.
1926 if (Subtarget->isPICStyleRIPRel())
1927 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1929 // Otherwise, the reference is relative to the PIC base.
1930 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1933 // FIXME: Why this routine is here? Move to RegInfo!
1934 std::pair<const TargetRegisterClass*, uint8_t>
1935 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1936 const TargetRegisterClass *RRC = nullptr;
1938 switch (VT.SimpleTy) {
1940 return TargetLowering::findRepresentativeClass(VT);
1941 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1942 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1945 RRC = &X86::VR64RegClass;
1947 case MVT::f32: case MVT::f64:
1948 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1949 case MVT::v4f32: case MVT::v2f64:
1950 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1952 RRC = &X86::VR128RegClass;
1955 return std::make_pair(RRC, Cost);
1958 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1959 unsigned &Offset) const {
1960 if (!Subtarget->isTargetLinux())
1963 if (Subtarget->is64Bit()) {
1964 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1966 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1978 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1979 unsigned DestAS) const {
1980 assert(SrcAS != DestAS && "Expected different address spaces!");
1982 return SrcAS < 256 && DestAS < 256;
1985 //===----------------------------------------------------------------------===//
1986 // Return Value Calling Convention Implementation
1987 //===----------------------------------------------------------------------===//
1989 #include "X86GenCallingConv.inc"
1992 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1993 MachineFunction &MF, bool isVarArg,
1994 const SmallVectorImpl<ISD::OutputArg> &Outs,
1995 LLVMContext &Context) const {
1996 SmallVector<CCValAssign, 16> RVLocs;
1997 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1998 return CCInfo.CheckReturn(Outs, RetCC_X86);
2001 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2002 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2007 X86TargetLowering::LowerReturn(SDValue Chain,
2008 CallingConv::ID CallConv, bool isVarArg,
2009 const SmallVectorImpl<ISD::OutputArg> &Outs,
2010 const SmallVectorImpl<SDValue> &OutVals,
2011 SDLoc dl, SelectionDAG &DAG) const {
2012 MachineFunction &MF = DAG.getMachineFunction();
2013 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2015 SmallVector<CCValAssign, 16> RVLocs;
2016 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2017 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2020 SmallVector<SDValue, 6> RetOps;
2021 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2022 // Operand #1 = Bytes To Pop
2023 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2026 // Copy the result values into the output registers.
2027 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2028 CCValAssign &VA = RVLocs[i];
2029 assert(VA.isRegLoc() && "Can only return in registers!");
2030 SDValue ValToCopy = OutVals[i];
2031 EVT ValVT = ValToCopy.getValueType();
2033 // Promote values to the appropriate types.
2034 if (VA.getLocInfo() == CCValAssign::SExt)
2035 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2036 else if (VA.getLocInfo() == CCValAssign::ZExt)
2037 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2038 else if (VA.getLocInfo() == CCValAssign::AExt)
2039 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2040 else if (VA.getLocInfo() == CCValAssign::BCvt)
2041 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2043 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2044 "Unexpected FP-extend for return value.");
2046 // If this is x86-64, and we disabled SSE, we can't return FP values,
2047 // or SSE or MMX vectors.
2048 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2049 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2050 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2051 report_fatal_error("SSE register return with SSE disabled");
2053 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2054 // llvm-gcc has never done it right and no one has noticed, so this
2055 // should be OK for now.
2056 if (ValVT == MVT::f64 &&
2057 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2058 report_fatal_error("SSE2 register return with SSE2 disabled");
2060 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2061 // the RET instruction and handled by the FP Stackifier.
2062 if (VA.getLocReg() == X86::FP0 ||
2063 VA.getLocReg() == X86::FP1) {
2064 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2065 // change the value to the FP stack register class.
2066 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2067 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2068 RetOps.push_back(ValToCopy);
2069 // Don't emit a copytoreg.
2073 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2074 // which is returned in RAX / RDX.
2075 if (Subtarget->is64Bit()) {
2076 if (ValVT == MVT::x86mmx) {
2077 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2078 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2079 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2081 // If we don't have SSE2 available, convert to v4f32 so the generated
2082 // register is legal.
2083 if (!Subtarget->hasSSE2())
2084 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2089 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2090 Flag = Chain.getValue(1);
2091 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2094 // The x86-64 ABIs require that for returning structs by value we copy
2095 // the sret argument into %rax/%eax (depending on ABI) for the return.
2096 // Win32 requires us to put the sret argument to %eax as well.
2097 // We saved the argument into a virtual register in the entry block,
2098 // so now we copy the value out and into %rax/%eax.
2100 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2101 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2102 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2103 // either case FuncInfo->setSRetReturnReg() will have been called.
2104 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2105 assert((Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) &&
2106 "No need for an sret register");
2107 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
2110 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2111 X86::RAX : X86::EAX;
2112 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2113 Flag = Chain.getValue(1);
2115 // RAX/EAX now acts like a return value.
2116 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2119 RetOps[0] = Chain; // Update chain.
2121 // Add the flag if we have it.
2123 RetOps.push_back(Flag);
2125 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2128 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2129 if (N->getNumValues() != 1)
2131 if (!N->hasNUsesOfValue(1, 0))
2134 SDValue TCChain = Chain;
2135 SDNode *Copy = *N->use_begin();
2136 if (Copy->getOpcode() == ISD::CopyToReg) {
2137 // If the copy has a glue operand, we conservatively assume it isn't safe to
2138 // perform a tail call.
2139 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2141 TCChain = Copy->getOperand(0);
2142 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2145 bool HasRet = false;
2146 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2148 if (UI->getOpcode() != X86ISD::RET_FLAG)
2150 // If we are returning more than one value, we can definitely
2151 // not make a tail call see PR19530
2152 if (UI->getNumOperands() > 4)
2154 if (UI->getNumOperands() == 4 &&
2155 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2168 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2169 ISD::NodeType ExtendKind) const {
2171 // TODO: Is this also valid on 32-bit?
2172 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2173 ReturnMVT = MVT::i8;
2175 ReturnMVT = MVT::i32;
2177 EVT MinVT = getRegisterType(Context, ReturnMVT);
2178 return VT.bitsLT(MinVT) ? MinVT : VT;
2181 /// Lower the result values of a call into the
2182 /// appropriate copies out of appropriate physical registers.
2185 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2186 CallingConv::ID CallConv, bool isVarArg,
2187 const SmallVectorImpl<ISD::InputArg> &Ins,
2188 SDLoc dl, SelectionDAG &DAG,
2189 SmallVectorImpl<SDValue> &InVals) const {
2191 // Assign locations to each value returned by this call.
2192 SmallVector<CCValAssign, 16> RVLocs;
2193 bool Is64Bit = Subtarget->is64Bit();
2194 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2196 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2198 // Copy all of the result registers out of their specified physreg.
2199 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2200 CCValAssign &VA = RVLocs[i];
2201 EVT CopyVT = VA.getValVT();
2203 // If this is x86-64, and we disabled SSE, we can't return FP values
2204 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2205 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2206 report_fatal_error("SSE register return with SSE disabled");
2209 // If we prefer to use the value in xmm registers, copy it out as f80 and
2210 // use a truncate to move it from fp stack reg to xmm reg.
2211 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2212 isScalarFPTypeInSSEReg(VA.getValVT()))
2215 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2216 CopyVT, InFlag).getValue(1);
2217 SDValue Val = Chain.getValue(0);
2219 if (CopyVT != VA.getValVT())
2220 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2221 // This truncation won't change the value.
2222 DAG.getIntPtrConstant(1));
2224 InFlag = Chain.getValue(2);
2225 InVals.push_back(Val);
2231 //===----------------------------------------------------------------------===//
2232 // C & StdCall & Fast Calling Convention implementation
2233 //===----------------------------------------------------------------------===//
2234 // StdCall calling convention seems to be standard for many Windows' API
2235 // routines and around. It differs from C calling convention just a little:
2236 // callee should clean up the stack, not caller. Symbols should be also
2237 // decorated in some fancy way :) It doesn't support any vector arguments.
2238 // For info on fast calling convention see Fast Calling Convention (tail call)
2239 // implementation LowerX86_32FastCCCallTo.
2241 /// CallIsStructReturn - Determines whether a call uses struct return
2243 enum StructReturnType {
2248 static StructReturnType
2249 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2251 return NotStructReturn;
2253 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2254 if (!Flags.isSRet())
2255 return NotStructReturn;
2256 if (Flags.isInReg())
2257 return RegStructReturn;
2258 return StackStructReturn;
2261 /// Determines whether a function uses struct return semantics.
2262 static StructReturnType
2263 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2265 return NotStructReturn;
2267 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2268 if (!Flags.isSRet())
2269 return NotStructReturn;
2270 if (Flags.isInReg())
2271 return RegStructReturn;
2272 return StackStructReturn;
2275 /// Make a copy of an aggregate at address specified by "Src" to address
2276 /// "Dst" with size and alignment information specified by the specific
2277 /// parameter attribute. The copy will be passed as a byval function parameter.
2279 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2280 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2282 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2284 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2285 /*isVolatile*/false, /*AlwaysInline=*/true,
2286 MachinePointerInfo(), MachinePointerInfo());
2289 /// Return true if the calling convention is one that
2290 /// supports tail call optimization.
2291 static bool IsTailCallConvention(CallingConv::ID CC) {
2292 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2293 CC == CallingConv::HiPE);
2296 /// \brief Return true if the calling convention is a C calling convention.
2297 static bool IsCCallConvention(CallingConv::ID CC) {
2298 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2299 CC == CallingConv::X86_64_SysV);
2302 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2303 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2307 CallingConv::ID CalleeCC = CS.getCallingConv();
2308 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2314 /// Return true if the function is being made into
2315 /// a tailcall target by changing its ABI.
2316 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2317 bool GuaranteedTailCallOpt) {
2318 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2322 X86TargetLowering::LowerMemArgument(SDValue Chain,
2323 CallingConv::ID CallConv,
2324 const SmallVectorImpl<ISD::InputArg> &Ins,
2325 SDLoc dl, SelectionDAG &DAG,
2326 const CCValAssign &VA,
2327 MachineFrameInfo *MFI,
2329 // Create the nodes corresponding to a load from this parameter slot.
2330 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2331 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2332 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2333 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2336 // If value is passed by pointer we have address passed instead of the value
2338 if (VA.getLocInfo() == CCValAssign::Indirect)
2339 ValVT = VA.getLocVT();
2341 ValVT = VA.getValVT();
2343 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2344 // changed with more analysis.
2345 // In case of tail call optimization mark all arguments mutable. Since they
2346 // could be overwritten by lowering of arguments in case of a tail call.
2347 if (Flags.isByVal()) {
2348 unsigned Bytes = Flags.getByValSize();
2349 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2350 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2351 return DAG.getFrameIndex(FI, getPointerTy());
2353 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2354 VA.getLocMemOffset(), isImmutable);
2355 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2356 return DAG.getLoad(ValVT, dl, Chain, FIN,
2357 MachinePointerInfo::getFixedStack(FI),
2358 false, false, false, 0);
2362 // FIXME: Get this from tablegen.
2363 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2364 const X86Subtarget *Subtarget) {
2365 assert(Subtarget->is64Bit());
2367 if (Subtarget->isCallingConvWin64(CallConv)) {
2368 static const MCPhysReg GPR64ArgRegsWin64[] = {
2369 X86::RCX, X86::RDX, X86::R8, X86::R9
2371 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2374 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2375 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2377 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2380 // FIXME: Get this from tablegen.
2381 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2382 CallingConv::ID CallConv,
2383 const X86Subtarget *Subtarget) {
2384 assert(Subtarget->is64Bit());
2385 if (Subtarget->isCallingConvWin64(CallConv)) {
2386 // The XMM registers which might contain var arg parameters are shadowed
2387 // in their paired GPR. So we only need to save the GPR to their home
2389 // TODO: __vectorcall will change this.
2393 const Function *Fn = MF.getFunction();
2394 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2395 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2396 "SSE register cannot be used when SSE is disabled!");
2397 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2398 !Subtarget->hasSSE1())
2399 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2403 static const MCPhysReg XMMArgRegs64Bit[] = {
2404 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2405 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2407 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2411 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2412 CallingConv::ID CallConv,
2414 const SmallVectorImpl<ISD::InputArg> &Ins,
2417 SmallVectorImpl<SDValue> &InVals)
2419 MachineFunction &MF = DAG.getMachineFunction();
2420 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2422 const Function* Fn = MF.getFunction();
2423 if (Fn->hasExternalLinkage() &&
2424 Subtarget->isTargetCygMing() &&
2425 Fn->getName() == "main")
2426 FuncInfo->setForceFramePointer(true);
2428 MachineFrameInfo *MFI = MF.getFrameInfo();
2429 bool Is64Bit = Subtarget->is64Bit();
2430 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2432 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2433 "Var args not supported with calling convention fastcc, ghc or hipe");
2435 // Assign locations to all of the incoming arguments.
2436 SmallVector<CCValAssign, 16> ArgLocs;
2437 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2439 // Allocate shadow area for Win64
2441 CCInfo.AllocateStack(32, 8);
2443 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2445 unsigned LastVal = ~0U;
2447 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2448 CCValAssign &VA = ArgLocs[i];
2449 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2451 assert(VA.getValNo() != LastVal &&
2452 "Don't support value assigned to multiple locs yet");
2454 LastVal = VA.getValNo();
2456 if (VA.isRegLoc()) {
2457 EVT RegVT = VA.getLocVT();
2458 const TargetRegisterClass *RC;
2459 if (RegVT == MVT::i32)
2460 RC = &X86::GR32RegClass;
2461 else if (Is64Bit && RegVT == MVT::i64)
2462 RC = &X86::GR64RegClass;
2463 else if (RegVT == MVT::f32)
2464 RC = &X86::FR32RegClass;
2465 else if (RegVT == MVT::f64)
2466 RC = &X86::FR64RegClass;
2467 else if (RegVT.is512BitVector())
2468 RC = &X86::VR512RegClass;
2469 else if (RegVT.is256BitVector())
2470 RC = &X86::VR256RegClass;
2471 else if (RegVT.is128BitVector())
2472 RC = &X86::VR128RegClass;
2473 else if (RegVT == MVT::x86mmx)
2474 RC = &X86::VR64RegClass;
2475 else if (RegVT == MVT::i1)
2476 RC = &X86::VK1RegClass;
2477 else if (RegVT == MVT::v8i1)
2478 RC = &X86::VK8RegClass;
2479 else if (RegVT == MVT::v16i1)
2480 RC = &X86::VK16RegClass;
2481 else if (RegVT == MVT::v32i1)
2482 RC = &X86::VK32RegClass;
2483 else if (RegVT == MVT::v64i1)
2484 RC = &X86::VK64RegClass;
2486 llvm_unreachable("Unknown argument type!");
2488 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2489 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2491 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2492 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2494 if (VA.getLocInfo() == CCValAssign::SExt)
2495 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2496 DAG.getValueType(VA.getValVT()));
2497 else if (VA.getLocInfo() == CCValAssign::ZExt)
2498 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2499 DAG.getValueType(VA.getValVT()));
2500 else if (VA.getLocInfo() == CCValAssign::BCvt)
2501 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2503 if (VA.isExtInLoc()) {
2504 // Handle MMX values passed in XMM regs.
2505 if (RegVT.isVector())
2506 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2508 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2511 assert(VA.isMemLoc());
2512 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2515 // If value is passed via pointer - do a load.
2516 if (VA.getLocInfo() == CCValAssign::Indirect)
2517 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2518 MachinePointerInfo(), false, false, false, 0);
2520 InVals.push_back(ArgValue);
2523 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2524 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2525 // The x86-64 ABIs require that for returning structs by value we copy
2526 // the sret argument into %rax/%eax (depending on ABI) for the return.
2527 // Win32 requires us to put the sret argument to %eax as well.
2528 // Save the argument into a virtual register so that we can access it
2529 // from the return points.
2530 if (Ins[i].Flags.isSRet()) {
2531 unsigned Reg = FuncInfo->getSRetReturnReg();
2533 MVT PtrTy = getPointerTy();
2534 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2535 FuncInfo->setSRetReturnReg(Reg);
2537 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2538 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2544 unsigned StackSize = CCInfo.getNextStackOffset();
2545 // Align stack specially for tail calls.
2546 if (FuncIsMadeTailCallSafe(CallConv,
2547 MF.getTarget().Options.GuaranteedTailCallOpt))
2548 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2550 // If the function takes variable number of arguments, make a frame index for
2551 // the start of the first vararg value... for expansion of llvm.va_start. We
2552 // can skip this if there are no va_start calls.
2553 if (MFI->hasVAStart() &&
2554 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2555 CallConv != CallingConv::X86_ThisCall))) {
2556 FuncInfo->setVarArgsFrameIndex(
2557 MFI->CreateFixedObject(1, StackSize, true));
2560 // Figure out if XMM registers are in use.
2561 assert(!(MF.getTarget().Options.UseSoftFloat &&
2562 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2563 "SSE register cannot be used when SSE is disabled!");
2565 // 64-bit calling conventions support varargs and register parameters, so we
2566 // have to do extra work to spill them in the prologue.
2567 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2568 // Find the first unallocated argument registers.
2569 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2570 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2571 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2572 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2573 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2574 "SSE register cannot be used when SSE is disabled!");
2576 // Gather all the live in physical registers.
2577 SmallVector<SDValue, 6> LiveGPRs;
2578 SmallVector<SDValue, 8> LiveXMMRegs;
2580 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2581 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2583 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2585 if (!ArgXMMs.empty()) {
2586 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2587 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2588 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2589 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2590 LiveXMMRegs.push_back(
2591 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2596 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2597 // Get to the caller-allocated home save location. Add 8 to account
2598 // for the return address.
2599 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2600 FuncInfo->setRegSaveFrameIndex(
2601 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2602 // Fixup to set vararg frame on shadow area (4 x i64).
2604 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2606 // For X86-64, if there are vararg parameters that are passed via
2607 // registers, then we must store them to their spots on the stack so
2608 // they may be loaded by deferencing the result of va_next.
2609 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2610 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2611 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2612 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2615 // Store the integer parameter registers.
2616 SmallVector<SDValue, 8> MemOps;
2617 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2619 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2620 for (SDValue Val : LiveGPRs) {
2621 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2622 DAG.getIntPtrConstant(Offset));
2624 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2625 MachinePointerInfo::getFixedStack(
2626 FuncInfo->getRegSaveFrameIndex(), Offset),
2628 MemOps.push_back(Store);
2632 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2633 // Now store the XMM (fp + vector) parameter registers.
2634 SmallVector<SDValue, 12> SaveXMMOps;
2635 SaveXMMOps.push_back(Chain);
2636 SaveXMMOps.push_back(ALVal);
2637 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2638 FuncInfo->getRegSaveFrameIndex()));
2639 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2640 FuncInfo->getVarArgsFPOffset()));
2641 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2643 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2644 MVT::Other, SaveXMMOps));
2647 if (!MemOps.empty())
2648 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2651 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2652 // Find the largest legal vector type.
2653 MVT VecVT = MVT::Other;
2654 // FIXME: Only some x86_32 calling conventions support AVX512.
2655 if (Subtarget->hasAVX512() &&
2656 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2657 CallConv == CallingConv::Intel_OCL_BI)))
2658 VecVT = MVT::v16f32;
2659 else if (Subtarget->hasAVX())
2661 else if (Subtarget->hasSSE2())
2664 // We forward some GPRs and some vector types.
2665 SmallVector<MVT, 2> RegParmTypes;
2666 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2667 RegParmTypes.push_back(IntVT);
2668 if (VecVT != MVT::Other)
2669 RegParmTypes.push_back(VecVT);
2671 // Compute the set of forwarded registers. The rest are scratch.
2672 SmallVectorImpl<ForwardedRegister> &Forwards =
2673 FuncInfo->getForwardedMustTailRegParms();
2674 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2676 // Conservatively forward AL on x86_64, since it might be used for varargs.
2677 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2678 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2679 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2682 // Copy all forwards from physical to virtual registers.
2683 for (ForwardedRegister &F : Forwards) {
2684 // FIXME: Can we use a less constrained schedule?
2685 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2686 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2687 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2691 // Some CCs need callee pop.
2692 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2693 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2694 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2696 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2697 // If this is an sret function, the return should pop the hidden pointer.
2698 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2699 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2700 argsAreStructReturn(Ins) == StackStructReturn)
2701 FuncInfo->setBytesToPopOnReturn(4);
2705 // RegSaveFrameIndex is X86-64 only.
2706 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2707 if (CallConv == CallingConv::X86_FastCall ||
2708 CallConv == CallingConv::X86_ThisCall)
2709 // fastcc functions can't have varargs.
2710 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2713 FuncInfo->setArgumentStackSize(StackSize);
2719 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2720 SDValue StackPtr, SDValue Arg,
2721 SDLoc dl, SelectionDAG &DAG,
2722 const CCValAssign &VA,
2723 ISD::ArgFlagsTy Flags) const {
2724 unsigned LocMemOffset = VA.getLocMemOffset();
2725 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2726 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2727 if (Flags.isByVal())
2728 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2730 return DAG.getStore(Chain, dl, Arg, PtrOff,
2731 MachinePointerInfo::getStack(LocMemOffset),
2735 /// Emit a load of return address if tail call
2736 /// optimization is performed and it is required.
2738 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2739 SDValue &OutRetAddr, SDValue Chain,
2740 bool IsTailCall, bool Is64Bit,
2741 int FPDiff, SDLoc dl) const {
2742 // Adjust the Return address stack slot.
2743 EVT VT = getPointerTy();
2744 OutRetAddr = getReturnAddressFrameIndex(DAG);
2746 // Load the "old" Return address.
2747 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2748 false, false, false, 0);
2749 return SDValue(OutRetAddr.getNode(), 1);
2752 /// Emit a store of the return address if tail call
2753 /// optimization is performed and it is required (FPDiff!=0).
2754 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2755 SDValue Chain, SDValue RetAddrFrIdx,
2756 EVT PtrVT, unsigned SlotSize,
2757 int FPDiff, SDLoc dl) {
2758 // Store the return address to the appropriate stack slot.
2759 if (!FPDiff) return Chain;
2760 // Calculate the new stack slot for the return address.
2761 int NewReturnAddrFI =
2762 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2764 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2765 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2766 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2772 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2773 SmallVectorImpl<SDValue> &InVals) const {
2774 SelectionDAG &DAG = CLI.DAG;
2776 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2777 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2778 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2779 SDValue Chain = CLI.Chain;
2780 SDValue Callee = CLI.Callee;
2781 CallingConv::ID CallConv = CLI.CallConv;
2782 bool &isTailCall = CLI.IsTailCall;
2783 bool isVarArg = CLI.IsVarArg;
2785 MachineFunction &MF = DAG.getMachineFunction();
2786 bool Is64Bit = Subtarget->is64Bit();
2787 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2788 StructReturnType SR = callIsStructReturn(Outs);
2789 bool IsSibcall = false;
2790 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2792 if (MF.getTarget().Options.DisableTailCalls)
2795 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2797 // Force this to be a tail call. The verifier rules are enough to ensure
2798 // that we can lower this successfully without moving the return address
2801 } else if (isTailCall) {
2802 // Check if it's really possible to do a tail call.
2803 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2804 isVarArg, SR != NotStructReturn,
2805 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2806 Outs, OutVals, Ins, DAG);
2808 // Sibcalls are automatically detected tailcalls which do not require
2810 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2817 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2818 "Var args not supported with calling convention fastcc, ghc or hipe");
2820 // Analyze operands of the call, assigning locations to each operand.
2821 SmallVector<CCValAssign, 16> ArgLocs;
2822 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2824 // Allocate shadow area for Win64
2826 CCInfo.AllocateStack(32, 8);
2828 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2830 // Get a count of how many bytes are to be pushed on the stack.
2831 unsigned NumBytes = CCInfo.getNextStackOffset();
2833 // This is a sibcall. The memory operands are available in caller's
2834 // own caller's stack.
2836 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2837 IsTailCallConvention(CallConv))
2838 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2841 if (isTailCall && !IsSibcall && !IsMustTail) {
2842 // Lower arguments at fp - stackoffset + fpdiff.
2843 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2845 FPDiff = NumBytesCallerPushed - NumBytes;
2847 // Set the delta of movement of the returnaddr stackslot.
2848 // But only set if delta is greater than previous delta.
2849 if (FPDiff < X86Info->getTCReturnAddrDelta())
2850 X86Info->setTCReturnAddrDelta(FPDiff);
2853 unsigned NumBytesToPush = NumBytes;
2854 unsigned NumBytesToPop = NumBytes;
2856 // If we have an inalloca argument, all stack space has already been allocated
2857 // for us and be right at the top of the stack. We don't support multiple
2858 // arguments passed in memory when using inalloca.
2859 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2861 if (!ArgLocs.back().isMemLoc())
2862 report_fatal_error("cannot use inalloca attribute on a register "
2864 if (ArgLocs.back().getLocMemOffset() != 0)
2865 report_fatal_error("any parameter with the inalloca attribute must be "
2866 "the only memory argument");
2870 Chain = DAG.getCALLSEQ_START(
2871 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2873 SDValue RetAddrFrIdx;
2874 // Load return address for tail calls.
2875 if (isTailCall && FPDiff)
2876 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2877 Is64Bit, FPDiff, dl);
2879 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2880 SmallVector<SDValue, 8> MemOpChains;
2883 // Walk the register/memloc assignments, inserting copies/loads. In the case
2884 // of tail call optimization arguments are handle later.
2885 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2886 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2887 // Skip inalloca arguments, they have already been written.
2888 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2889 if (Flags.isInAlloca())
2892 CCValAssign &VA = ArgLocs[i];
2893 EVT RegVT = VA.getLocVT();
2894 SDValue Arg = OutVals[i];
2895 bool isByVal = Flags.isByVal();
2897 // Promote the value if needed.
2898 switch (VA.getLocInfo()) {
2899 default: llvm_unreachable("Unknown loc info!");
2900 case CCValAssign::Full: break;
2901 case CCValAssign::SExt:
2902 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2904 case CCValAssign::ZExt:
2905 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2907 case CCValAssign::AExt:
2908 if (RegVT.is128BitVector()) {
2909 // Special case: passing MMX values in XMM registers.
2910 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2911 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2912 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2914 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2916 case CCValAssign::BCvt:
2917 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2919 case CCValAssign::Indirect: {
2920 // Store the argument.
2921 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2922 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2923 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2924 MachinePointerInfo::getFixedStack(FI),
2931 if (VA.isRegLoc()) {
2932 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2933 if (isVarArg && IsWin64) {
2934 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2935 // shadow reg if callee is a varargs function.
2936 unsigned ShadowReg = 0;
2937 switch (VA.getLocReg()) {
2938 case X86::XMM0: ShadowReg = X86::RCX; break;
2939 case X86::XMM1: ShadowReg = X86::RDX; break;
2940 case X86::XMM2: ShadowReg = X86::R8; break;
2941 case X86::XMM3: ShadowReg = X86::R9; break;
2944 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2946 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2947 assert(VA.isMemLoc());
2948 if (!StackPtr.getNode())
2949 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2951 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2952 dl, DAG, VA, Flags));
2956 if (!MemOpChains.empty())
2957 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2959 if (Subtarget->isPICStyleGOT()) {
2960 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2963 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2964 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2966 // If we are tail calling and generating PIC/GOT style code load the
2967 // address of the callee into ECX. The value in ecx is used as target of
2968 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2969 // for tail calls on PIC/GOT architectures. Normally we would just put the
2970 // address of GOT into ebx and then call target@PLT. But for tail calls
2971 // ebx would be restored (since ebx is callee saved) before jumping to the
2974 // Note: The actual moving to ECX is done further down.
2975 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2976 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2977 !G->getGlobal()->hasProtectedVisibility())
2978 Callee = LowerGlobalAddress(Callee, DAG);
2979 else if (isa<ExternalSymbolSDNode>(Callee))
2980 Callee = LowerExternalSymbol(Callee, DAG);
2984 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2985 // From AMD64 ABI document:
2986 // For calls that may call functions that use varargs or stdargs
2987 // (prototype-less calls or calls to functions containing ellipsis (...) in
2988 // the declaration) %al is used as hidden argument to specify the number
2989 // of SSE registers used. The contents of %al do not need to match exactly
2990 // the number of registers, but must be an ubound on the number of SSE
2991 // registers used and is in the range 0 - 8 inclusive.
2993 // Count the number of XMM registers allocated.
2994 static const MCPhysReg XMMArgRegs[] = {
2995 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2996 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2998 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
2999 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3000 && "SSE registers cannot be used when SSE is disabled");
3002 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3003 DAG.getConstant(NumXMMRegs, MVT::i8)));
3006 if (isVarArg && IsMustTail) {
3007 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3008 for (const auto &F : Forwards) {
3009 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3010 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3014 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3015 // don't need this because the eligibility check rejects calls that require
3016 // shuffling arguments passed in memory.
3017 if (!IsSibcall && isTailCall) {
3018 // Force all the incoming stack arguments to be loaded from the stack
3019 // before any new outgoing arguments are stored to the stack, because the
3020 // outgoing stack slots may alias the incoming argument stack slots, and
3021 // the alias isn't otherwise explicit. This is slightly more conservative
3022 // than necessary, because it means that each store effectively depends
3023 // on every argument instead of just those arguments it would clobber.
3024 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3026 SmallVector<SDValue, 8> MemOpChains2;
3029 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3030 CCValAssign &VA = ArgLocs[i];
3033 assert(VA.isMemLoc());
3034 SDValue Arg = OutVals[i];
3035 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3036 // Skip inalloca arguments. They don't require any work.
3037 if (Flags.isInAlloca())
3039 // Create frame index.
3040 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3041 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3042 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3043 FIN = DAG.getFrameIndex(FI, getPointerTy());
3045 if (Flags.isByVal()) {
3046 // Copy relative to framepointer.
3047 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3048 if (!StackPtr.getNode())
3049 StackPtr = DAG.getCopyFromReg(Chain, dl,
3050 RegInfo->getStackRegister(),
3052 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3054 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3058 // Store relative to framepointer.
3059 MemOpChains2.push_back(
3060 DAG.getStore(ArgChain, dl, Arg, FIN,
3061 MachinePointerInfo::getFixedStack(FI),
3066 if (!MemOpChains2.empty())
3067 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3069 // Store the return address to the appropriate stack slot.
3070 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3071 getPointerTy(), RegInfo->getSlotSize(),
3075 // Build a sequence of copy-to-reg nodes chained together with token chain
3076 // and flag operands which copy the outgoing args into registers.
3078 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3079 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3080 RegsToPass[i].second, InFlag);
3081 InFlag = Chain.getValue(1);
3084 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3085 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3086 // In the 64-bit large code model, we have to make all calls
3087 // through a register, since the call instruction's 32-bit
3088 // pc-relative offset may not be large enough to hold the whole
3090 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3091 // If the callee is a GlobalAddress node (quite common, every direct call
3092 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3094 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3096 // We should use extra load for direct calls to dllimported functions in
3098 const GlobalValue *GV = G->getGlobal();
3099 if (!GV->hasDLLImportStorageClass()) {
3100 unsigned char OpFlags = 0;
3101 bool ExtraLoad = false;
3102 unsigned WrapperKind = ISD::DELETED_NODE;
3104 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3105 // external symbols most go through the PLT in PIC mode. If the symbol
3106 // has hidden or protected visibility, or if it is static or local, then
3107 // we don't need to use the PLT - we can directly call it.
3108 if (Subtarget->isTargetELF() &&
3109 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3110 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3114 (!Subtarget->getTargetTriple().isMacOSX() ||
3115 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3116 // PC-relative references to external symbols should go through $stub,
3117 // unless we're building with the leopard linker or later, which
3118 // automatically synthesizes these stubs.
3119 OpFlags = X86II::MO_DARWIN_STUB;
3120 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3121 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3122 // If the function is marked as non-lazy, generate an indirect call
3123 // which loads from the GOT directly. This avoids runtime overhead
3124 // at the cost of eager binding (and one extra byte of encoding).
3125 OpFlags = X86II::MO_GOTPCREL;
3126 WrapperKind = X86ISD::WrapperRIP;
3130 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3131 G->getOffset(), OpFlags);
3133 // Add a wrapper if needed.
3134 if (WrapperKind != ISD::DELETED_NODE)
3135 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3136 // Add extra indirection if needed.
3138 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3139 MachinePointerInfo::getGOT(),
3140 false, false, false, 0);
3142 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3143 unsigned char OpFlags = 0;
3145 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3146 // external symbols should go through the PLT.
3147 if (Subtarget->isTargetELF() &&
3148 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3149 OpFlags = X86II::MO_PLT;
3150 } else if (Subtarget->isPICStyleStubAny() &&
3151 (!Subtarget->getTargetTriple().isMacOSX() ||
3152 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3153 // PC-relative references to external symbols should go through $stub,
3154 // unless we're building with the leopard linker or later, which
3155 // automatically synthesizes these stubs.
3156 OpFlags = X86II::MO_DARWIN_STUB;
3159 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3161 } else if (Subtarget->isTarget64BitILP32() &&
3162 Callee->getValueType(0) == MVT::i32) {
3163 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3164 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3167 // Returns a chain & a flag for retval copy to use.
3168 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3169 SmallVector<SDValue, 8> Ops;
3171 if (!IsSibcall && isTailCall) {
3172 Chain = DAG.getCALLSEQ_END(Chain,
3173 DAG.getIntPtrConstant(NumBytesToPop, true),
3174 DAG.getIntPtrConstant(0, true), InFlag, dl);
3175 InFlag = Chain.getValue(1);
3178 Ops.push_back(Chain);
3179 Ops.push_back(Callee);
3182 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3184 // Add argument registers to the end of the list so that they are known live
3186 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3187 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3188 RegsToPass[i].second.getValueType()));
3190 // Add a register mask operand representing the call-preserved registers.
3191 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3192 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3193 assert(Mask && "Missing call preserved mask for calling convention");
3194 Ops.push_back(DAG.getRegisterMask(Mask));
3196 if (InFlag.getNode())
3197 Ops.push_back(InFlag);
3201 //// If this is the first return lowered for this function, add the regs
3202 //// to the liveout set for the function.
3203 // This isn't right, although it's probably harmless on x86; liveouts
3204 // should be computed from returns not tail calls. Consider a void
3205 // function making a tail call to a function returning int.
3206 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3209 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3210 InFlag = Chain.getValue(1);
3212 // Create the CALLSEQ_END node.
3213 unsigned NumBytesForCalleeToPop;
3214 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3215 DAG.getTarget().Options.GuaranteedTailCallOpt))
3216 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3217 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3218 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3219 SR == StackStructReturn)
3220 // If this is a call to a struct-return function, the callee
3221 // pops the hidden struct pointer, so we have to push it back.
3222 // This is common for Darwin/X86, Linux & Mingw32 targets.
3223 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3224 NumBytesForCalleeToPop = 4;
3226 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3228 // Returns a flag for retval copy to use.
3230 Chain = DAG.getCALLSEQ_END(Chain,
3231 DAG.getIntPtrConstant(NumBytesToPop, true),
3232 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3235 InFlag = Chain.getValue(1);
3238 // Handle result values, copying them out of physregs into vregs that we
3240 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3241 Ins, dl, DAG, InVals);
3244 //===----------------------------------------------------------------------===//
3245 // Fast Calling Convention (tail call) implementation
3246 //===----------------------------------------------------------------------===//
3248 // Like std call, callee cleans arguments, convention except that ECX is
3249 // reserved for storing the tail called function address. Only 2 registers are
3250 // free for argument passing (inreg). Tail call optimization is performed
3252 // * tailcallopt is enabled
3253 // * caller/callee are fastcc
3254 // On X86_64 architecture with GOT-style position independent code only local
3255 // (within module) calls are supported at the moment.
3256 // To keep the stack aligned according to platform abi the function
3257 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3258 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3259 // If a tail called function callee has more arguments than the caller the
3260 // caller needs to make sure that there is room to move the RETADDR to. This is
3261 // achieved by reserving an area the size of the argument delta right after the
3262 // original RETADDR, but before the saved framepointer or the spilled registers
3263 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3275 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3276 /// for a 16 byte align requirement.
3278 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3279 SelectionDAG& DAG) const {
3280 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3281 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3282 unsigned StackAlignment = TFI.getStackAlignment();
3283 uint64_t AlignMask = StackAlignment - 1;
3284 int64_t Offset = StackSize;
3285 unsigned SlotSize = RegInfo->getSlotSize();
3286 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3287 // Number smaller than 12 so just add the difference.
3288 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3290 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3291 Offset = ((~AlignMask) & Offset) + StackAlignment +
3292 (StackAlignment-SlotSize);
3297 /// MatchingStackOffset - Return true if the given stack call argument is
3298 /// already available in the same position (relatively) of the caller's
3299 /// incoming argument stack.
3301 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3302 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3303 const X86InstrInfo *TII) {
3304 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3306 if (Arg.getOpcode() == ISD::CopyFromReg) {
3307 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3308 if (!TargetRegisterInfo::isVirtualRegister(VR))
3310 MachineInstr *Def = MRI->getVRegDef(VR);
3313 if (!Flags.isByVal()) {
3314 if (!TII->isLoadFromStackSlot(Def, FI))
3317 unsigned Opcode = Def->getOpcode();
3318 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3319 Opcode == X86::LEA64_32r) &&
3320 Def->getOperand(1).isFI()) {
3321 FI = Def->getOperand(1).getIndex();
3322 Bytes = Flags.getByValSize();
3326 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3327 if (Flags.isByVal())
3328 // ByVal argument is passed in as a pointer but it's now being
3329 // dereferenced. e.g.
3330 // define @foo(%struct.X* %A) {
3331 // tail call @bar(%struct.X* byval %A)
3334 SDValue Ptr = Ld->getBasePtr();
3335 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3338 FI = FINode->getIndex();
3339 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3340 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3341 FI = FINode->getIndex();
3342 Bytes = Flags.getByValSize();
3346 assert(FI != INT_MAX);
3347 if (!MFI->isFixedObjectIndex(FI))
3349 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3352 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3353 /// for tail call optimization. Targets which want to do tail call
3354 /// optimization should implement this function.
3356 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3357 CallingConv::ID CalleeCC,
3359 bool isCalleeStructRet,
3360 bool isCallerStructRet,
3362 const SmallVectorImpl<ISD::OutputArg> &Outs,
3363 const SmallVectorImpl<SDValue> &OutVals,
3364 const SmallVectorImpl<ISD::InputArg> &Ins,
3365 SelectionDAG &DAG) const {
3366 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3369 // If -tailcallopt is specified, make fastcc functions tail-callable.
3370 const MachineFunction &MF = DAG.getMachineFunction();
3371 const Function *CallerF = MF.getFunction();
3373 // If the function return type is x86_fp80 and the callee return type is not,
3374 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3375 // perform a tailcall optimization here.
3376 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3379 CallingConv::ID CallerCC = CallerF->getCallingConv();
3380 bool CCMatch = CallerCC == CalleeCC;
3381 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3382 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3384 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3385 if (IsTailCallConvention(CalleeCC) && CCMatch)
3390 // Look for obvious safe cases to perform tail call optimization that do not
3391 // require ABI changes. This is what gcc calls sibcall.
3393 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3394 // emit a special epilogue.
3395 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3396 if (RegInfo->needsStackRealignment(MF))
3399 // Also avoid sibcall optimization if either caller or callee uses struct
3400 // return semantics.
3401 if (isCalleeStructRet || isCallerStructRet)
3404 // An stdcall/thiscall caller is expected to clean up its arguments; the
3405 // callee isn't going to do that.
3406 // FIXME: this is more restrictive than needed. We could produce a tailcall
3407 // when the stack adjustment matches. For example, with a thiscall that takes
3408 // only one argument.
3409 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3410 CallerCC == CallingConv::X86_ThisCall))
3413 // Do not sibcall optimize vararg calls unless all arguments are passed via
3415 if (isVarArg && !Outs.empty()) {
3417 // Optimizing for varargs on Win64 is unlikely to be safe without
3418 // additional testing.
3419 if (IsCalleeWin64 || IsCallerWin64)
3422 SmallVector<CCValAssign, 16> ArgLocs;
3423 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3426 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3427 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3428 if (!ArgLocs[i].isRegLoc())
3432 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3433 // stack. Therefore, if it's not used by the call it is not safe to optimize
3434 // this into a sibcall.
3435 bool Unused = false;
3436 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3443 SmallVector<CCValAssign, 16> RVLocs;
3444 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3446 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3447 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3448 CCValAssign &VA = RVLocs[i];
3449 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3454 // If the calling conventions do not match, then we'd better make sure the
3455 // results are returned in the same way as what the caller expects.
3457 SmallVector<CCValAssign, 16> RVLocs1;
3458 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3460 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3462 SmallVector<CCValAssign, 16> RVLocs2;
3463 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3465 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3467 if (RVLocs1.size() != RVLocs2.size())
3469 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3470 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3472 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3474 if (RVLocs1[i].isRegLoc()) {
3475 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3478 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3484 // If the callee takes no arguments then go on to check the results of the
3486 if (!Outs.empty()) {
3487 // Check if stack adjustment is needed. For now, do not do this if any
3488 // argument is passed on the stack.
3489 SmallVector<CCValAssign, 16> ArgLocs;
3490 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3493 // Allocate shadow area for Win64
3495 CCInfo.AllocateStack(32, 8);
3497 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3498 if (CCInfo.getNextStackOffset()) {
3499 MachineFunction &MF = DAG.getMachineFunction();
3500 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3503 // Check if the arguments are already laid out in the right way as
3504 // the caller's fixed stack objects.
3505 MachineFrameInfo *MFI = MF.getFrameInfo();
3506 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3507 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3508 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3509 CCValAssign &VA = ArgLocs[i];
3510 SDValue Arg = OutVals[i];
3511 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3512 if (VA.getLocInfo() == CCValAssign::Indirect)
3514 if (!VA.isRegLoc()) {
3515 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3522 // If the tailcall address may be in a register, then make sure it's
3523 // possible to register allocate for it. In 32-bit, the call address can
3524 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3525 // callee-saved registers are restored. These happen to be the same
3526 // registers used to pass 'inreg' arguments so watch out for those.
3527 if (!Subtarget->is64Bit() &&
3528 ((!isa<GlobalAddressSDNode>(Callee) &&
3529 !isa<ExternalSymbolSDNode>(Callee)) ||
3530 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3531 unsigned NumInRegs = 0;
3532 // In PIC we need an extra register to formulate the address computation
3534 unsigned MaxInRegs =
3535 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3537 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3538 CCValAssign &VA = ArgLocs[i];
3541 unsigned Reg = VA.getLocReg();
3544 case X86::EAX: case X86::EDX: case X86::ECX:
3545 if (++NumInRegs == MaxInRegs)
3557 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3558 const TargetLibraryInfo *libInfo) const {
3559 return X86::createFastISel(funcInfo, libInfo);
3562 //===----------------------------------------------------------------------===//
3563 // Other Lowering Hooks
3564 //===----------------------------------------------------------------------===//
3566 static bool MayFoldLoad(SDValue Op) {
3567 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3570 static bool MayFoldIntoStore(SDValue Op) {
3571 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3574 static bool isTargetShuffle(unsigned Opcode) {
3576 default: return false;
3577 case X86ISD::BLENDI:
3578 case X86ISD::PSHUFB:
3579 case X86ISD::PSHUFD:
3580 case X86ISD::PSHUFHW:
3581 case X86ISD::PSHUFLW:
3583 case X86ISD::PALIGNR:
3584 case X86ISD::MOVLHPS:
3585 case X86ISD::MOVLHPD:
3586 case X86ISD::MOVHLPS:
3587 case X86ISD::MOVLPS:
3588 case X86ISD::MOVLPD:
3589 case X86ISD::MOVSHDUP:
3590 case X86ISD::MOVSLDUP:
3591 case X86ISD::MOVDDUP:
3594 case X86ISD::UNPCKL:
3595 case X86ISD::UNPCKH:
3596 case X86ISD::VPERMILPI:
3597 case X86ISD::VPERM2X128:
3598 case X86ISD::VPERMI:
3603 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3604 SDValue V1, unsigned TargetMask,
3605 SelectionDAG &DAG) {
3607 default: llvm_unreachable("Unknown x86 shuffle node");
3608 case X86ISD::PSHUFD:
3609 case X86ISD::PSHUFHW:
3610 case X86ISD::PSHUFLW:
3611 case X86ISD::VPERMILPI:
3612 case X86ISD::VPERMI:
3613 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3617 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3618 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3620 default: llvm_unreachable("Unknown x86 shuffle node");
3621 case X86ISD::MOVLHPS:
3622 case X86ISD::MOVLHPD:
3623 case X86ISD::MOVHLPS:
3624 case X86ISD::MOVLPS:
3625 case X86ISD::MOVLPD:
3628 case X86ISD::UNPCKL:
3629 case X86ISD::UNPCKH:
3630 return DAG.getNode(Opc, dl, VT, V1, V2);
3634 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3635 MachineFunction &MF = DAG.getMachineFunction();
3636 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3637 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3638 int ReturnAddrIndex = FuncInfo->getRAIndex();
3640 if (ReturnAddrIndex == 0) {
3641 // Set up a frame object for the return address.
3642 unsigned SlotSize = RegInfo->getSlotSize();
3643 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3646 FuncInfo->setRAIndex(ReturnAddrIndex);
3649 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3652 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3653 bool hasSymbolicDisplacement) {
3654 // Offset should fit into 32 bit immediate field.
3655 if (!isInt<32>(Offset))
3658 // If we don't have a symbolic displacement - we don't have any extra
3660 if (!hasSymbolicDisplacement)
3663 // FIXME: Some tweaks might be needed for medium code model.
3664 if (M != CodeModel::Small && M != CodeModel::Kernel)
3667 // For small code model we assume that latest object is 16MB before end of 31
3668 // bits boundary. We may also accept pretty large negative constants knowing
3669 // that all objects are in the positive half of address space.
3670 if (M == CodeModel::Small && Offset < 16*1024*1024)
3673 // For kernel code model we know that all object resist in the negative half
3674 // of 32bits address space. We may not accept negative offsets, since they may
3675 // be just off and we may accept pretty large positive ones.
3676 if (M == CodeModel::Kernel && Offset >= 0)
3682 /// isCalleePop - Determines whether the callee is required to pop its
3683 /// own arguments. Callee pop is necessary to support tail calls.
3684 bool X86::isCalleePop(CallingConv::ID CallingConv,
3685 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3686 switch (CallingConv) {
3689 case CallingConv::X86_StdCall:
3690 case CallingConv::X86_FastCall:
3691 case CallingConv::X86_ThisCall:
3693 case CallingConv::Fast:
3694 case CallingConv::GHC:
3695 case CallingConv::HiPE:
3702 /// \brief Return true if the condition is an unsigned comparison operation.
3703 static bool isX86CCUnsigned(unsigned X86CC) {
3705 default: llvm_unreachable("Invalid integer condition!");
3706 case X86::COND_E: return true;
3707 case X86::COND_G: return false;
3708 case X86::COND_GE: return false;
3709 case X86::COND_L: return false;
3710 case X86::COND_LE: return false;
3711 case X86::COND_NE: return true;
3712 case X86::COND_B: return true;
3713 case X86::COND_A: return true;
3714 case X86::COND_BE: return true;
3715 case X86::COND_AE: return true;
3717 llvm_unreachable("covered switch fell through?!");
3720 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3721 /// specific condition code, returning the condition code and the LHS/RHS of the
3722 /// comparison to make.
3723 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3724 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3726 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3727 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3728 // X > -1 -> X == 0, jump !sign.
3729 RHS = DAG.getConstant(0, RHS.getValueType());
3730 return X86::COND_NS;
3732 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3733 // X < 0 -> X == 0, jump on sign.
3736 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3738 RHS = DAG.getConstant(0, RHS.getValueType());
3739 return X86::COND_LE;
3743 switch (SetCCOpcode) {
3744 default: llvm_unreachable("Invalid integer condition!");
3745 case ISD::SETEQ: return X86::COND_E;
3746 case ISD::SETGT: return X86::COND_G;
3747 case ISD::SETGE: return X86::COND_GE;
3748 case ISD::SETLT: return X86::COND_L;
3749 case ISD::SETLE: return X86::COND_LE;
3750 case ISD::SETNE: return X86::COND_NE;
3751 case ISD::SETULT: return X86::COND_B;
3752 case ISD::SETUGT: return X86::COND_A;
3753 case ISD::SETULE: return X86::COND_BE;
3754 case ISD::SETUGE: return X86::COND_AE;
3758 // First determine if it is required or is profitable to flip the operands.
3760 // If LHS is a foldable load, but RHS is not, flip the condition.
3761 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3762 !ISD::isNON_EXTLoad(RHS.getNode())) {
3763 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3764 std::swap(LHS, RHS);
3767 switch (SetCCOpcode) {
3773 std::swap(LHS, RHS);
3777 // On a floating point condition, the flags are set as follows:
3779 // 0 | 0 | 0 | X > Y
3780 // 0 | 0 | 1 | X < Y
3781 // 1 | 0 | 0 | X == Y
3782 // 1 | 1 | 1 | unordered
3783 switch (SetCCOpcode) {
3784 default: llvm_unreachable("Condcode should be pre-legalized away");
3786 case ISD::SETEQ: return X86::COND_E;
3787 case ISD::SETOLT: // flipped
3789 case ISD::SETGT: return X86::COND_A;
3790 case ISD::SETOLE: // flipped
3792 case ISD::SETGE: return X86::COND_AE;
3793 case ISD::SETUGT: // flipped
3795 case ISD::SETLT: return X86::COND_B;
3796 case ISD::SETUGE: // flipped
3798 case ISD::SETLE: return X86::COND_BE;
3800 case ISD::SETNE: return X86::COND_NE;
3801 case ISD::SETUO: return X86::COND_P;
3802 case ISD::SETO: return X86::COND_NP;
3804 case ISD::SETUNE: return X86::COND_INVALID;
3808 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3809 /// code. Current x86 isa includes the following FP cmov instructions:
3810 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3811 static bool hasFPCMov(unsigned X86CC) {
3827 /// isFPImmLegal - Returns true if the target can instruction select the
3828 /// specified FP immediate natively. If false, the legalizer will
3829 /// materialize the FP immediate as a load from a constant pool.
3830 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3831 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3832 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3838 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3839 ISD::LoadExtType ExtTy,
3841 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3842 // relocation target a movq or addq instruction: don't let the load shrink.
3843 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3844 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3845 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3846 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3850 /// \brief Returns true if it is beneficial to convert a load of a constant
3851 /// to just the constant itself.
3852 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3854 assert(Ty->isIntegerTy());
3856 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3857 if (BitSize == 0 || BitSize > 64)
3862 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3863 unsigned Index) const {
3864 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3867 return (Index == 0 || Index == ResVT.getVectorNumElements());
3870 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3871 // Speculate cttz only if we can directly use TZCNT.
3872 return Subtarget->hasBMI();
3875 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3876 // Speculate ctlz only if we can directly use LZCNT.
3877 return Subtarget->hasLZCNT();
3880 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3881 /// the specified range (L, H].
3882 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3883 return (Val < 0) || (Val >= Low && Val < Hi);
3886 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3887 /// specified value.
3888 static bool isUndefOrEqual(int Val, int CmpVal) {
3889 return (Val < 0 || Val == CmpVal);
3892 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3893 /// from position Pos and ending in Pos+Size, falls within the specified
3894 /// sequential range (Low, Low+Size]. or is undef.
3895 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3896 unsigned Pos, unsigned Size, int Low) {
3897 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3898 if (!isUndefOrEqual(Mask[i], Low))
3903 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3904 /// the two vector operands have swapped position.
3905 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3906 unsigned NumElems) {
3907 for (unsigned i = 0; i != NumElems; ++i) {
3911 else if (idx < (int)NumElems)
3912 Mask[i] = idx + NumElems;
3914 Mask[i] = idx - NumElems;
3918 /// isVEXTRACTIndex - Return true if the specified
3919 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3920 /// suitable for instruction that extract 128 or 256 bit vectors
3921 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3922 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3923 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3926 // The index should be aligned on a vecWidth-bit boundary.
3928 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3930 MVT VT = N->getSimpleValueType(0);
3931 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3932 bool Result = (Index * ElSize) % vecWidth == 0;
3937 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3938 /// operand specifies a subvector insert that is suitable for input to
3939 /// insertion of 128 or 256-bit subvectors
3940 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3941 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3942 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3944 // The index should be aligned on a vecWidth-bit boundary.
3946 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3948 MVT VT = N->getSimpleValueType(0);
3949 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3950 bool Result = (Index * ElSize) % vecWidth == 0;
3955 bool X86::isVINSERT128Index(SDNode *N) {
3956 return isVINSERTIndex(N, 128);
3959 bool X86::isVINSERT256Index(SDNode *N) {
3960 return isVINSERTIndex(N, 256);
3963 bool X86::isVEXTRACT128Index(SDNode *N) {
3964 return isVEXTRACTIndex(N, 128);
3967 bool X86::isVEXTRACT256Index(SDNode *N) {
3968 return isVEXTRACTIndex(N, 256);
3971 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
3972 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3973 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3974 llvm_unreachable("Illegal extract subvector for VEXTRACT");
3977 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3979 MVT VecVT = N->getOperand(0).getSimpleValueType();
3980 MVT ElVT = VecVT.getVectorElementType();
3982 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3983 return Index / NumElemsPerChunk;
3986 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
3987 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3988 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3989 llvm_unreachable("Illegal insert subvector for VINSERT");
3992 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3994 MVT VecVT = N->getSimpleValueType(0);
3995 MVT ElVT = VecVT.getVectorElementType();
3997 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3998 return Index / NumElemsPerChunk;
4001 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4002 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4003 /// and VINSERTI128 instructions.
4004 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4005 return getExtractVEXTRACTImmediate(N, 128);
4008 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4009 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4010 /// and VINSERTI64x4 instructions.
4011 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4012 return getExtractVEXTRACTImmediate(N, 256);
4015 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4016 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4017 /// and VINSERTI128 instructions.
4018 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4019 return getInsertVINSERTImmediate(N, 128);
4022 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4023 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4024 /// and VINSERTI64x4 instructions.
4025 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4026 return getInsertVINSERTImmediate(N, 256);
4029 /// isZero - Returns true if Elt is a constant integer zero
4030 static bool isZero(SDValue V) {
4031 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4032 return C && C->isNullValue();
4035 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4037 bool X86::isZeroNode(SDValue Elt) {
4040 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4041 return CFP->getValueAPF().isPosZero();
4045 /// getZeroVector - Returns a vector of specified type with all zero elements.
4047 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4048 SelectionDAG &DAG, SDLoc dl) {
4049 assert(VT.isVector() && "Expected a vector type");
4051 // Always build SSE zero vectors as <4 x i32> bitcasted
4052 // to their dest type. This ensures they get CSE'd.
4054 if (VT.is128BitVector()) { // SSE
4055 if (Subtarget->hasSSE2()) { // SSE2
4056 SDValue Cst = DAG.getConstant(0, MVT::i32);
4057 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4059 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
4060 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4062 } else if (VT.is256BitVector()) { // AVX
4063 if (Subtarget->hasInt256()) { // AVX2
4064 SDValue Cst = DAG.getConstant(0, MVT::i32);
4065 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4066 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4068 // 256-bit logic and arithmetic instructions in AVX are all
4069 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4070 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
4071 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4072 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4074 } else if (VT.is512BitVector()) { // AVX-512
4075 SDValue Cst = DAG.getConstant(0, MVT::i32);
4076 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4077 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4078 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4079 } else if (VT.getScalarType() == MVT::i1) {
4080 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4081 SDValue Cst = DAG.getConstant(0, MVT::i1);
4082 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
4083 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4085 llvm_unreachable("Unexpected vector type");
4087 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4090 /// getOnesVector - Returns a vector of specified type with all bits set.
4091 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4092 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4093 /// Then bitcast to their original type, ensuring they get CSE'd.
4094 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4096 assert(VT.isVector() && "Expected a vector type");
4098 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
4100 if (VT.is256BitVector()) {
4101 if (HasInt256) { // AVX2
4102 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4103 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4105 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4106 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4108 } else if (VT.is128BitVector()) {
4109 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4111 llvm_unreachable("Unexpected vector type");
4113 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4116 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4117 /// operation of specified width.
4118 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4120 unsigned NumElems = VT.getVectorNumElements();
4121 SmallVector<int, 8> Mask;
4122 Mask.push_back(NumElems);
4123 for (unsigned i = 1; i != NumElems; ++i)
4125 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4128 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4129 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4131 unsigned NumElems = VT.getVectorNumElements();
4132 SmallVector<int, 8> Mask;
4133 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4135 Mask.push_back(i + NumElems);
4137 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4140 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4141 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4143 unsigned NumElems = VT.getVectorNumElements();
4144 SmallVector<int, 8> Mask;
4145 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4146 Mask.push_back(i + Half);
4147 Mask.push_back(i + NumElems + Half);
4149 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4152 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4153 /// vector of zero or undef vector. This produces a shuffle where the low
4154 /// element of V2 is swizzled into the zero/undef vector, landing at element
4155 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4156 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4158 const X86Subtarget *Subtarget,
4159 SelectionDAG &DAG) {
4160 MVT VT = V2.getSimpleValueType();
4162 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4163 unsigned NumElems = VT.getVectorNumElements();
4164 SmallVector<int, 16> MaskVec;
4165 for (unsigned i = 0; i != NumElems; ++i)
4166 // If this is the insertion idx, put the low elt of V2 here.
4167 MaskVec.push_back(i == Idx ? NumElems : i);
4168 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4171 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4172 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4173 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4174 /// shuffles which use a single input multiple times, and in those cases it will
4175 /// adjust the mask to only have indices within that single input.
4176 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4177 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4178 unsigned NumElems = VT.getVectorNumElements();
4182 bool IsFakeUnary = false;
4183 switch(N->getOpcode()) {
4184 case X86ISD::BLENDI:
4185 ImmN = N->getOperand(N->getNumOperands()-1);
4186 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4189 ImmN = N->getOperand(N->getNumOperands()-1);
4190 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4191 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4193 case X86ISD::UNPCKH:
4194 DecodeUNPCKHMask(VT, Mask);
4195 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4197 case X86ISD::UNPCKL:
4198 DecodeUNPCKLMask(VT, Mask);
4199 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4201 case X86ISD::MOVHLPS:
4202 DecodeMOVHLPSMask(NumElems, Mask);
4203 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4205 case X86ISD::MOVLHPS:
4206 DecodeMOVLHPSMask(NumElems, Mask);
4207 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4209 case X86ISD::PALIGNR:
4210 ImmN = N->getOperand(N->getNumOperands()-1);
4211 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4213 case X86ISD::PSHUFD:
4214 case X86ISD::VPERMILPI:
4215 ImmN = N->getOperand(N->getNumOperands()-1);
4216 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4219 case X86ISD::PSHUFHW:
4220 ImmN = N->getOperand(N->getNumOperands()-1);
4221 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4224 case X86ISD::PSHUFLW:
4225 ImmN = N->getOperand(N->getNumOperands()-1);
4226 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4229 case X86ISD::PSHUFB: {
4231 SDValue MaskNode = N->getOperand(1);
4232 while (MaskNode->getOpcode() == ISD::BITCAST)
4233 MaskNode = MaskNode->getOperand(0);
4235 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4236 // If we have a build-vector, then things are easy.
4237 EVT VT = MaskNode.getValueType();
4238 assert(VT.isVector() &&
4239 "Can't produce a non-vector with a build_vector!");
4240 if (!VT.isInteger())
4243 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4245 SmallVector<uint64_t, 32> RawMask;
4246 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4247 SDValue Op = MaskNode->getOperand(i);
4248 if (Op->getOpcode() == ISD::UNDEF) {
4249 RawMask.push_back((uint64_t)SM_SentinelUndef);
4252 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4255 APInt MaskElement = CN->getAPIntValue();
4257 // We now have to decode the element which could be any integer size and
4258 // extract each byte of it.
4259 for (int j = 0; j < NumBytesPerElement; ++j) {
4260 // Note that this is x86 and so always little endian: the low byte is
4261 // the first byte of the mask.
4262 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4263 MaskElement = MaskElement.lshr(8);
4266 DecodePSHUFBMask(RawMask, Mask);
4270 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4274 SDValue Ptr = MaskLoad->getBasePtr();
4275 if (Ptr->getOpcode() == X86ISD::Wrapper)
4276 Ptr = Ptr->getOperand(0);
4278 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4279 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4282 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4283 DecodePSHUFBMask(C, Mask);
4291 case X86ISD::VPERMI:
4292 ImmN = N->getOperand(N->getNumOperands()-1);
4293 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4298 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4300 case X86ISD::VPERM2X128:
4301 ImmN = N->getOperand(N->getNumOperands()-1);
4302 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4303 if (Mask.empty()) return false;
4305 case X86ISD::MOVSLDUP:
4306 DecodeMOVSLDUPMask(VT, Mask);
4309 case X86ISD::MOVSHDUP:
4310 DecodeMOVSHDUPMask(VT, Mask);
4313 case X86ISD::MOVDDUP:
4314 DecodeMOVDDUPMask(VT, Mask);
4317 case X86ISD::MOVLHPD:
4318 case X86ISD::MOVLPD:
4319 case X86ISD::MOVLPS:
4320 // Not yet implemented
4322 default: llvm_unreachable("unknown target shuffle node");
4325 // If we have a fake unary shuffle, the shuffle mask is spread across two
4326 // inputs that are actually the same node. Re-map the mask to always point
4327 // into the first input.
4330 if (M >= (int)Mask.size())
4336 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4337 /// element of the result of the vector shuffle.
4338 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4341 return SDValue(); // Limit search depth.
4343 SDValue V = SDValue(N, 0);
4344 EVT VT = V.getValueType();
4345 unsigned Opcode = V.getOpcode();
4347 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4348 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4349 int Elt = SV->getMaskElt(Index);
4352 return DAG.getUNDEF(VT.getVectorElementType());
4354 unsigned NumElems = VT.getVectorNumElements();
4355 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4356 : SV->getOperand(1);
4357 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4360 // Recurse into target specific vector shuffles to find scalars.
4361 if (isTargetShuffle(Opcode)) {
4362 MVT ShufVT = V.getSimpleValueType();
4363 unsigned NumElems = ShufVT.getVectorNumElements();
4364 SmallVector<int, 16> ShuffleMask;
4367 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4370 int Elt = ShuffleMask[Index];
4372 return DAG.getUNDEF(ShufVT.getVectorElementType());
4374 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4376 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4380 // Actual nodes that may contain scalar elements
4381 if (Opcode == ISD::BITCAST) {
4382 V = V.getOperand(0);
4383 EVT SrcVT = V.getValueType();
4384 unsigned NumElems = VT.getVectorNumElements();
4386 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4390 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4391 return (Index == 0) ? V.getOperand(0)
4392 : DAG.getUNDEF(VT.getVectorElementType());
4394 if (V.getOpcode() == ISD::BUILD_VECTOR)
4395 return V.getOperand(Index);
4400 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4402 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4403 unsigned NumNonZero, unsigned NumZero,
4405 const X86Subtarget* Subtarget,
4406 const TargetLowering &TLI) {
4413 for (unsigned i = 0; i < 16; ++i) {
4414 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4415 if (ThisIsNonZero && First) {
4417 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4419 V = DAG.getUNDEF(MVT::v8i16);
4424 SDValue ThisElt, LastElt;
4425 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4426 if (LastIsNonZero) {
4427 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4428 MVT::i16, Op.getOperand(i-1));
4430 if (ThisIsNonZero) {
4431 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4432 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4433 ThisElt, DAG.getConstant(8, MVT::i8));
4435 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4439 if (ThisElt.getNode())
4440 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4441 DAG.getIntPtrConstant(i/2));
4445 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4448 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4450 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4451 unsigned NumNonZero, unsigned NumZero,
4453 const X86Subtarget* Subtarget,
4454 const TargetLowering &TLI) {
4461 for (unsigned i = 0; i < 8; ++i) {
4462 bool isNonZero = (NonZeros & (1 << i)) != 0;
4466 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4468 V = DAG.getUNDEF(MVT::v8i16);
4471 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4472 MVT::v8i16, V, Op.getOperand(i),
4473 DAG.getIntPtrConstant(i));
4480 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4481 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4482 const X86Subtarget *Subtarget,
4483 const TargetLowering &TLI) {
4484 // Find all zeroable elements.
4485 std::bitset<4> Zeroable;
4486 for (int i=0; i < 4; ++i) {
4487 SDValue Elt = Op->getOperand(i);
4488 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4490 assert(Zeroable.size() - Zeroable.count() > 1 &&
4491 "We expect at least two non-zero elements!");
4493 // We only know how to deal with build_vector nodes where elements are either
4494 // zeroable or extract_vector_elt with constant index.
4495 SDValue FirstNonZero;
4496 unsigned FirstNonZeroIdx;
4497 for (unsigned i=0; i < 4; ++i) {
4500 SDValue Elt = Op->getOperand(i);
4501 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4502 !isa<ConstantSDNode>(Elt.getOperand(1)))
4504 // Make sure that this node is extracting from a 128-bit vector.
4505 MVT VT = Elt.getOperand(0).getSimpleValueType();
4506 if (!VT.is128BitVector())
4508 if (!FirstNonZero.getNode()) {
4510 FirstNonZeroIdx = i;
4514 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4515 SDValue V1 = FirstNonZero.getOperand(0);
4516 MVT VT = V1.getSimpleValueType();
4518 // See if this build_vector can be lowered as a blend with zero.
4520 unsigned EltMaskIdx, EltIdx;
4522 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4523 if (Zeroable[EltIdx]) {
4524 // The zero vector will be on the right hand side.
4525 Mask[EltIdx] = EltIdx+4;
4529 Elt = Op->getOperand(EltIdx);
4530 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4531 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4532 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4534 Mask[EltIdx] = EltIdx;
4538 // Let the shuffle legalizer deal with blend operations.
4539 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4540 if (V1.getSimpleValueType() != VT)
4541 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4542 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4545 // See if we can lower this build_vector to a INSERTPS.
4546 if (!Subtarget->hasSSE41())
4549 SDValue V2 = Elt.getOperand(0);
4550 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4553 bool CanFold = true;
4554 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4558 SDValue Current = Op->getOperand(i);
4559 SDValue SrcVector = Current->getOperand(0);
4562 CanFold = SrcVector == V1 &&
4563 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4569 assert(V1.getNode() && "Expected at least two non-zero elements!");
4570 if (V1.getSimpleValueType() != MVT::v4f32)
4571 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4572 if (V2.getSimpleValueType() != MVT::v4f32)
4573 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4575 // Ok, we can emit an INSERTPS instruction.
4576 unsigned ZMask = Zeroable.to_ulong();
4578 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4579 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4580 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
4581 DAG.getIntPtrConstant(InsertPSMask));
4582 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
4585 /// Return a vector logical shift node.
4586 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4587 unsigned NumBits, SelectionDAG &DAG,
4588 const TargetLowering &TLI, SDLoc dl) {
4589 assert(VT.is128BitVector() && "Unknown type for VShift");
4590 MVT ShVT = MVT::v2i64;
4591 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4592 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4593 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4594 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4595 SDValue ShiftVal = DAG.getConstant(NumBits/8, ScalarShiftTy);
4596 return DAG.getNode(ISD::BITCAST, dl, VT,
4597 DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4601 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4603 // Check if the scalar load can be widened into a vector load. And if
4604 // the address is "base + cst" see if the cst can be "absorbed" into
4605 // the shuffle mask.
4606 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4607 SDValue Ptr = LD->getBasePtr();
4608 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4610 EVT PVT = LD->getValueType(0);
4611 if (PVT != MVT::i32 && PVT != MVT::f32)
4616 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4617 FI = FINode->getIndex();
4619 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4620 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4621 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4622 Offset = Ptr.getConstantOperandVal(1);
4623 Ptr = Ptr.getOperand(0);
4628 // FIXME: 256-bit vector instructions don't require a strict alignment,
4629 // improve this code to support it better.
4630 unsigned RequiredAlign = VT.getSizeInBits()/8;
4631 SDValue Chain = LD->getChain();
4632 // Make sure the stack object alignment is at least 16 or 32.
4633 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4634 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4635 if (MFI->isFixedObjectIndex(FI)) {
4636 // Can't change the alignment. FIXME: It's possible to compute
4637 // the exact stack offset and reference FI + adjust offset instead.
4638 // If someone *really* cares about this. That's the way to implement it.
4641 MFI->setObjectAlignment(FI, RequiredAlign);
4645 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4646 // Ptr + (Offset & ~15).
4649 if ((Offset % RequiredAlign) & 3)
4651 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4653 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
4654 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4656 int EltNo = (Offset - StartOffset) >> 2;
4657 unsigned NumElems = VT.getVectorNumElements();
4659 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4660 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4661 LD->getPointerInfo().getWithOffset(StartOffset),
4662 false, false, false, 0);
4664 SmallVector<int, 8> Mask(NumElems, EltNo);
4666 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4672 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4673 /// elements can be replaced by a single large load which has the same value as
4674 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4676 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4678 /// FIXME: we'd also like to handle the case where the last elements are zero
4679 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4680 /// There's even a handy isZeroNode for that purpose.
4681 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4682 SDLoc &DL, SelectionDAG &DAG,
4683 bool isAfterLegalize) {
4684 unsigned NumElems = Elts.size();
4686 LoadSDNode *LDBase = nullptr;
4687 unsigned LastLoadedElt = -1U;
4689 // For each element in the initializer, see if we've found a load or an undef.
4690 // If we don't find an initial load element, or later load elements are
4691 // non-consecutive, bail out.
4692 for (unsigned i = 0; i < NumElems; ++i) {
4693 SDValue Elt = Elts[i];
4694 // Look through a bitcast.
4695 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4696 Elt = Elt.getOperand(0);
4697 if (!Elt.getNode() ||
4698 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4701 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4703 LDBase = cast<LoadSDNode>(Elt.getNode());
4707 if (Elt.getOpcode() == ISD::UNDEF)
4710 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4711 EVT LdVT = Elt.getValueType();
4712 // Each loaded element must be the correct fractional portion of the
4713 // requested vector load.
4714 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4716 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4721 // If we have found an entire vector of loads and undefs, then return a large
4722 // load of the entire vector width starting at the base pointer. If we found
4723 // consecutive loads for the low half, generate a vzext_load node.
4724 if (LastLoadedElt == NumElems - 1) {
4725 assert(LDBase && "Did not find base load for merging consecutive loads");
4726 EVT EltVT = LDBase->getValueType(0);
4727 // Ensure that the input vector size for the merged loads matches the
4728 // cumulative size of the input elements.
4729 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4732 if (isAfterLegalize &&
4733 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4736 SDValue NewLd = SDValue();
4738 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4739 LDBase->getPointerInfo(), LDBase->isVolatile(),
4740 LDBase->isNonTemporal(), LDBase->isInvariant(),
4741 LDBase->getAlignment());
4743 if (LDBase->hasAnyUseOfValue(1)) {
4744 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4746 SDValue(NewLd.getNode(), 1));
4747 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4748 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4749 SDValue(NewLd.getNode(), 1));
4755 //TODO: The code below fires only for for loading the low v2i32 / v2f32
4756 //of a v4i32 / v4f32. It's probably worth generalizing.
4757 EVT EltVT = VT.getVectorElementType();
4758 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
4759 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4760 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4761 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4763 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
4764 LDBase->getPointerInfo(),
4765 LDBase->getAlignment(),
4766 false/*isVolatile*/, true/*ReadMem*/,
4769 // Make sure the newly-created LOAD is in the same position as LDBase in
4770 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
4771 // update uses of LDBase's output chain to use the TokenFactor.
4772 if (LDBase->hasAnyUseOfValue(1)) {
4773 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4774 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
4775 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4776 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4777 SDValue(ResNode.getNode(), 1));
4780 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4785 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4786 /// to generate a splat value for the following cases:
4787 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4788 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4789 /// a scalar load, or a constant.
4790 /// The VBROADCAST node is returned when a pattern is found,
4791 /// or SDValue() otherwise.
4792 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
4793 SelectionDAG &DAG) {
4794 // VBROADCAST requires AVX.
4795 // TODO: Splats could be generated for non-AVX CPUs using SSE
4796 // instructions, but there's less potential gain for only 128-bit vectors.
4797 if (!Subtarget->hasAVX())
4800 MVT VT = Op.getSimpleValueType();
4803 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
4804 "Unsupported vector type for broadcast.");
4809 switch (Op.getOpcode()) {
4811 // Unknown pattern found.
4814 case ISD::BUILD_VECTOR: {
4815 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
4816 BitVector UndefElements;
4817 SDValue Splat = BVOp->getSplatValue(&UndefElements);
4819 // We need a splat of a single value to use broadcast, and it doesn't
4820 // make any sense if the value is only in one element of the vector.
4821 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
4825 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4826 Ld.getOpcode() == ISD::ConstantFP);
4828 // Make sure that all of the users of a non-constant load are from the
4829 // BUILD_VECTOR node.
4830 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
4835 case ISD::VECTOR_SHUFFLE: {
4836 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4838 // Shuffles must have a splat mask where the first element is
4840 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4843 SDValue Sc = Op.getOperand(0);
4844 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
4845 Sc.getOpcode() != ISD::BUILD_VECTOR) {
4847 if (!Subtarget->hasInt256())
4850 // Use the register form of the broadcast instruction available on AVX2.
4851 if (VT.getSizeInBits() >= 256)
4852 Sc = Extract128BitVector(Sc, 0, DAG, dl);
4853 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
4856 Ld = Sc.getOperand(0);
4857 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4858 Ld.getOpcode() == ISD::ConstantFP);
4860 // The scalar_to_vector node and the suspected
4861 // load node must have exactly one user.
4862 // Constants may have multiple users.
4864 // AVX-512 has register version of the broadcast
4865 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
4866 Ld.getValueType().getSizeInBits() >= 32;
4867 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
4874 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
4875 bool IsGE256 = (VT.getSizeInBits() >= 256);
4877 // When optimizing for size, generate up to 5 extra bytes for a broadcast
4878 // instruction to save 8 or more bytes of constant pool data.
4879 // TODO: If multiple splats are generated to load the same constant,
4880 // it may be detrimental to overall size. There needs to be a way to detect
4881 // that condition to know if this is truly a size win.
4882 const Function *F = DAG.getMachineFunction().getFunction();
4883 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
4885 // Handle broadcasting a single constant scalar from the constant pool
4887 // On Sandybridge (no AVX2), it is still better to load a constant vector
4888 // from the constant pool and not to broadcast it from a scalar.
4889 // But override that restriction when optimizing for size.
4890 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
4891 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
4892 EVT CVT = Ld.getValueType();
4893 assert(!CVT.isVector() && "Must not broadcast a vector type");
4895 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
4896 // For size optimization, also splat v2f64 and v2i64, and for size opt
4897 // with AVX2, also splat i8 and i16.
4898 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
4899 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
4900 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
4901 const Constant *C = nullptr;
4902 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
4903 C = CI->getConstantIntValue();
4904 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
4905 C = CF->getConstantFPValue();
4907 assert(C && "Invalid constant type");
4909 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4910 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
4911 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
4912 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
4913 MachinePointerInfo::getConstantPool(),
4914 false, false, false, Alignment);
4916 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4920 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
4922 // Handle AVX2 in-register broadcasts.
4923 if (!IsLoad && Subtarget->hasInt256() &&
4924 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
4925 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4927 // The scalar source must be a normal load.
4931 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
4932 (Subtarget->hasVLX() && ScalarSize == 64))
4933 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4935 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
4936 // double since there is no vbroadcastsd xmm
4937 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
4938 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
4939 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4942 // Unsupported broadcast.
4946 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
4947 /// underlying vector and index.
4949 /// Modifies \p ExtractedFromVec to the real vector and returns the real
4951 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
4953 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
4954 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
4957 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
4959 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
4961 // (extract_vector_elt (vector_shuffle<2,u,u,u>
4962 // (extract_subvector (v8f32 %vreg0), Constant<4>),
4965 // In this case the vector is the extract_subvector expression and the index
4966 // is 2, as specified by the shuffle.
4967 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
4968 SDValue ShuffleVec = SVOp->getOperand(0);
4969 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
4970 assert(ShuffleVecVT.getVectorElementType() ==
4971 ExtractedFromVec.getSimpleValueType().getVectorElementType());
4973 int ShuffleIdx = SVOp->getMaskElt(Idx);
4974 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
4975 ExtractedFromVec = ShuffleVec;
4981 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
4982 MVT VT = Op.getSimpleValueType();
4984 // Skip if insert_vec_elt is not supported.
4985 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4986 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
4990 unsigned NumElems = Op.getNumOperands();
4994 SmallVector<unsigned, 4> InsertIndices;
4995 SmallVector<int, 8> Mask(NumElems, -1);
4997 for (unsigned i = 0; i != NumElems; ++i) {
4998 unsigned Opc = Op.getOperand(i).getOpcode();
5000 if (Opc == ISD::UNDEF)
5003 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5004 // Quit if more than 1 elements need inserting.
5005 if (InsertIndices.size() > 1)
5008 InsertIndices.push_back(i);
5012 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5013 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5014 // Quit if non-constant index.
5015 if (!isa<ConstantSDNode>(ExtIdx))
5017 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5019 // Quit if extracted from vector of different type.
5020 if (ExtractedFromVec.getValueType() != VT)
5023 if (!VecIn1.getNode())
5024 VecIn1 = ExtractedFromVec;
5025 else if (VecIn1 != ExtractedFromVec) {
5026 if (!VecIn2.getNode())
5027 VecIn2 = ExtractedFromVec;
5028 else if (VecIn2 != ExtractedFromVec)
5029 // Quit if more than 2 vectors to shuffle
5033 if (ExtractedFromVec == VecIn1)
5035 else if (ExtractedFromVec == VecIn2)
5036 Mask[i] = Idx + NumElems;
5039 if (!VecIn1.getNode())
5042 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5043 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5044 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5045 unsigned Idx = InsertIndices[i];
5046 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5047 DAG.getIntPtrConstant(Idx));
5053 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5055 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5057 MVT VT = Op.getSimpleValueType();
5058 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5059 "Unexpected type in LowerBUILD_VECTORvXi1!");
5062 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5063 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5064 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5065 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5068 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5069 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5070 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5071 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5074 bool AllContants = true;
5075 uint64_t Immediate = 0;
5076 int NonConstIdx = -1;
5077 bool IsSplat = true;
5078 unsigned NumNonConsts = 0;
5079 unsigned NumConsts = 0;
5080 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5081 SDValue In = Op.getOperand(idx);
5082 if (In.getOpcode() == ISD::UNDEF)
5084 if (!isa<ConstantSDNode>(In)) {
5085 AllContants = false;
5090 if (cast<ConstantSDNode>(In)->getZExtValue())
5091 Immediate |= (1ULL << idx);
5093 if (In != Op.getOperand(0))
5098 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5099 DAG.getConstant(Immediate, MVT::i16));
5100 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5101 DAG.getIntPtrConstant(0));
5104 if (NumNonConsts == 1 && NonConstIdx != 0) {
5107 SDValue VecAsImm = DAG.getConstant(Immediate,
5108 MVT::getIntegerVT(VT.getSizeInBits()));
5109 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
5112 DstVec = DAG.getUNDEF(VT);
5113 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5114 Op.getOperand(NonConstIdx),
5115 DAG.getIntPtrConstant(NonConstIdx));
5117 if (!IsSplat && (NonConstIdx != 0))
5118 llvm_unreachable("Unsupported BUILD_VECTOR operation");
5119 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
5122 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5123 DAG.getConstant(-1, SelectVT),
5124 DAG.getConstant(0, SelectVT));
5126 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5127 DAG.getConstant((Immediate | 1), SelectVT),
5128 DAG.getConstant(Immediate, SelectVT));
5129 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
5132 /// \brief Return true if \p N implements a horizontal binop and return the
5133 /// operands for the horizontal binop into V0 and V1.
5135 /// This is a helper function of PerformBUILD_VECTORCombine.
5136 /// This function checks that the build_vector \p N in input implements a
5137 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5138 /// operation to match.
5139 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5140 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5141 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5144 /// This function only analyzes elements of \p N whose indices are
5145 /// in range [BaseIdx, LastIdx).
5146 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5148 unsigned BaseIdx, unsigned LastIdx,
5149 SDValue &V0, SDValue &V1) {
5150 EVT VT = N->getValueType(0);
5152 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5153 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5154 "Invalid Vector in input!");
5156 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5157 bool CanFold = true;
5158 unsigned ExpectedVExtractIdx = BaseIdx;
5159 unsigned NumElts = LastIdx - BaseIdx;
5160 V0 = DAG.getUNDEF(VT);
5161 V1 = DAG.getUNDEF(VT);
5163 // Check if N implements a horizontal binop.
5164 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5165 SDValue Op = N->getOperand(i + BaseIdx);
5168 if (Op->getOpcode() == ISD::UNDEF) {
5169 // Update the expected vector extract index.
5170 if (i * 2 == NumElts)
5171 ExpectedVExtractIdx = BaseIdx;
5172 ExpectedVExtractIdx += 2;
5176 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5181 SDValue Op0 = Op.getOperand(0);
5182 SDValue Op1 = Op.getOperand(1);
5184 // Try to match the following pattern:
5185 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5186 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5187 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5188 Op0.getOperand(0) == Op1.getOperand(0) &&
5189 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5190 isa<ConstantSDNode>(Op1.getOperand(1)));
5194 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5195 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5197 if (i * 2 < NumElts) {
5198 if (V0.getOpcode() == ISD::UNDEF)
5199 V0 = Op0.getOperand(0);
5201 if (V1.getOpcode() == ISD::UNDEF)
5202 V1 = Op0.getOperand(0);
5203 if (i * 2 == NumElts)
5204 ExpectedVExtractIdx = BaseIdx;
5207 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5208 if (I0 == ExpectedVExtractIdx)
5209 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5210 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5211 // Try to match the following dag sequence:
5212 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5213 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5217 ExpectedVExtractIdx += 2;
5223 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5224 /// a concat_vector.
5226 /// This is a helper function of PerformBUILD_VECTORCombine.
5227 /// This function expects two 256-bit vectors called V0 and V1.
5228 /// At first, each vector is split into two separate 128-bit vectors.
5229 /// Then, the resulting 128-bit vectors are used to implement two
5230 /// horizontal binary operations.
5232 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5234 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5235 /// the two new horizontal binop.
5236 /// When Mode is set, the first horizontal binop dag node would take as input
5237 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5238 /// horizontal binop dag node would take as input the lower 128-bit of V1
5239 /// and the upper 128-bit of V1.
5241 /// HADD V0_LO, V0_HI
5242 /// HADD V1_LO, V1_HI
5244 /// Otherwise, the first horizontal binop dag node takes as input the lower
5245 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5246 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
5248 /// HADD V0_LO, V1_LO
5249 /// HADD V0_HI, V1_HI
5251 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5252 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5253 /// the upper 128-bits of the result.
5254 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5255 SDLoc DL, SelectionDAG &DAG,
5256 unsigned X86Opcode, bool Mode,
5257 bool isUndefLO, bool isUndefHI) {
5258 EVT VT = V0.getValueType();
5259 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5260 "Invalid nodes in input!");
5262 unsigned NumElts = VT.getVectorNumElements();
5263 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5264 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5265 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5266 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5267 EVT NewVT = V0_LO.getValueType();
5269 SDValue LO = DAG.getUNDEF(NewVT);
5270 SDValue HI = DAG.getUNDEF(NewVT);
5273 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5274 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5275 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5276 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5277 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5279 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5280 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5281 V1_LO->getOpcode() != ISD::UNDEF))
5282 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5284 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5285 V1_HI->getOpcode() != ISD::UNDEF))
5286 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5289 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5292 /// \brief Try to fold a build_vector that performs an 'addsub' into the
5293 /// sequence of 'vadd + vsub + blendi'.
5294 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
5295 const X86Subtarget *Subtarget) {
5297 EVT VT = BV->getValueType(0);
5298 unsigned NumElts = VT.getVectorNumElements();
5299 SDValue InVec0 = DAG.getUNDEF(VT);
5300 SDValue InVec1 = DAG.getUNDEF(VT);
5302 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5303 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5305 // Odd-numbered elements in the input build vector are obtained from
5306 // adding two integer/float elements.
5307 // Even-numbered elements in the input build vector are obtained from
5308 // subtracting two integer/float elements.
5309 unsigned ExpectedOpcode = ISD::FSUB;
5310 unsigned NextExpectedOpcode = ISD::FADD;
5311 bool AddFound = false;
5312 bool SubFound = false;
5314 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5315 SDValue Op = BV->getOperand(i);
5317 // Skip 'undef' values.
5318 unsigned Opcode = Op.getOpcode();
5319 if (Opcode == ISD::UNDEF) {
5320 std::swap(ExpectedOpcode, NextExpectedOpcode);
5324 // Early exit if we found an unexpected opcode.
5325 if (Opcode != ExpectedOpcode)
5328 SDValue Op0 = Op.getOperand(0);
5329 SDValue Op1 = Op.getOperand(1);
5331 // Try to match the following pattern:
5332 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5333 // Early exit if we cannot match that sequence.
5334 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5335 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5336 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5337 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5338 Op0.getOperand(1) != Op1.getOperand(1))
5341 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5345 // We found a valid add/sub node. Update the information accordingly.
5351 // Update InVec0 and InVec1.
5352 if (InVec0.getOpcode() == ISD::UNDEF)
5353 InVec0 = Op0.getOperand(0);
5354 if (InVec1.getOpcode() == ISD::UNDEF)
5355 InVec1 = Op1.getOperand(0);
5357 // Make sure that operands in input to each add/sub node always
5358 // come from a same pair of vectors.
5359 if (InVec0 != Op0.getOperand(0)) {
5360 if (ExpectedOpcode == ISD::FSUB)
5363 // FADD is commutable. Try to commute the operands
5364 // and then test again.
5365 std::swap(Op0, Op1);
5366 if (InVec0 != Op0.getOperand(0))
5370 if (InVec1 != Op1.getOperand(0))
5373 // Update the pair of expected opcodes.
5374 std::swap(ExpectedOpcode, NextExpectedOpcode);
5377 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5378 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5379 InVec1.getOpcode() != ISD::UNDEF)
5380 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5385 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
5386 const X86Subtarget *Subtarget) {
5388 EVT VT = N->getValueType(0);
5389 unsigned NumElts = VT.getVectorNumElements();
5390 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
5391 SDValue InVec0, InVec1;
5393 // Try to match an ADDSUB.
5394 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
5395 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
5396 SDValue Value = matchAddSub(BV, DAG, Subtarget);
5397 if (Value.getNode())
5401 // Try to match horizontal ADD/SUB.
5402 unsigned NumUndefsLO = 0;
5403 unsigned NumUndefsHI = 0;
5404 unsigned Half = NumElts/2;
5406 // Count the number of UNDEF operands in the build_vector in input.
5407 for (unsigned i = 0, e = Half; i != e; ++i)
5408 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5411 for (unsigned i = Half, e = NumElts; i != e; ++i)
5412 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5415 // Early exit if this is either a build_vector of all UNDEFs or all the
5416 // operands but one are UNDEF.
5417 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5420 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5421 // Try to match an SSE3 float HADD/HSUB.
5422 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5423 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5425 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5426 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5427 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5428 // Try to match an SSSE3 integer HADD/HSUB.
5429 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5430 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5432 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5433 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5436 if (!Subtarget->hasAVX())
5439 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5440 // Try to match an AVX horizontal add/sub of packed single/double
5441 // precision floating point values from 256-bit vectors.
5442 SDValue InVec2, InVec3;
5443 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5444 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5445 ((InVec0.getOpcode() == ISD::UNDEF ||
5446 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5447 ((InVec1.getOpcode() == ISD::UNDEF ||
5448 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5449 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5451 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5452 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5453 ((InVec0.getOpcode() == ISD::UNDEF ||
5454 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5455 ((InVec1.getOpcode() == ISD::UNDEF ||
5456 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5457 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5458 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5459 // Try to match an AVX2 horizontal add/sub of signed integers.
5460 SDValue InVec2, InVec3;
5462 bool CanFold = true;
5464 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5465 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5466 ((InVec0.getOpcode() == ISD::UNDEF ||
5467 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5468 ((InVec1.getOpcode() == ISD::UNDEF ||
5469 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5470 X86Opcode = X86ISD::HADD;
5471 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5472 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5473 ((InVec0.getOpcode() == ISD::UNDEF ||
5474 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5475 ((InVec1.getOpcode() == ISD::UNDEF ||
5476 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5477 X86Opcode = X86ISD::HSUB;
5482 // Fold this build_vector into a single horizontal add/sub.
5483 // Do this only if the target has AVX2.
5484 if (Subtarget->hasAVX2())
5485 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5487 // Do not try to expand this build_vector into a pair of horizontal
5488 // add/sub if we can emit a pair of scalar add/sub.
5489 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5492 // Convert this build_vector into a pair of horizontal binop followed by
5494 bool isUndefLO = NumUndefsLO == Half;
5495 bool isUndefHI = NumUndefsHI == Half;
5496 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5497 isUndefLO, isUndefHI);
5501 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5502 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5504 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5505 X86Opcode = X86ISD::HADD;
5506 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5507 X86Opcode = X86ISD::HSUB;
5508 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5509 X86Opcode = X86ISD::FHADD;
5510 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5511 X86Opcode = X86ISD::FHSUB;
5515 // Don't try to expand this build_vector into a pair of horizontal add/sub
5516 // if we can simply emit a pair of scalar add/sub.
5517 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5520 // Convert this build_vector into two horizontal add/sub followed by
5522 bool isUndefLO = NumUndefsLO == Half;
5523 bool isUndefHI = NumUndefsHI == Half;
5524 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5525 isUndefLO, isUndefHI);
5532 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5535 MVT VT = Op.getSimpleValueType();
5536 MVT ExtVT = VT.getVectorElementType();
5537 unsigned NumElems = Op.getNumOperands();
5539 // Generate vectors for predicate vectors.
5540 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5541 return LowerBUILD_VECTORvXi1(Op, DAG);
5543 // Vectors containing all zeros can be matched by pxor and xorps later
5544 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5545 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5546 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5547 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5550 return getZeroVector(VT, Subtarget, DAG, dl);
5553 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5554 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5555 // vpcmpeqd on 256-bit vectors.
5556 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5557 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5560 if (!VT.is512BitVector())
5561 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5564 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5565 if (Broadcast.getNode())
5568 unsigned EVTBits = ExtVT.getSizeInBits();
5570 unsigned NumZero = 0;
5571 unsigned NumNonZero = 0;
5572 unsigned NonZeros = 0;
5573 bool IsAllConstants = true;
5574 SmallSet<SDValue, 8> Values;
5575 for (unsigned i = 0; i < NumElems; ++i) {
5576 SDValue Elt = Op.getOperand(i);
5577 if (Elt.getOpcode() == ISD::UNDEF)
5580 if (Elt.getOpcode() != ISD::Constant &&
5581 Elt.getOpcode() != ISD::ConstantFP)
5582 IsAllConstants = false;
5583 if (X86::isZeroNode(Elt))
5586 NonZeros |= (1 << i);
5591 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5592 if (NumNonZero == 0)
5593 return DAG.getUNDEF(VT);
5595 // Special case for single non-zero, non-undef, element.
5596 if (NumNonZero == 1) {
5597 unsigned Idx = countTrailingZeros(NonZeros);
5598 SDValue Item = Op.getOperand(Idx);
5600 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5601 // the value are obviously zero, truncate the value to i32 and do the
5602 // insertion that way. Only do this if the value is non-constant or if the
5603 // value is a constant being inserted into element 0. It is cheaper to do
5604 // a constant pool load than it is to do a movd + shuffle.
5605 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5606 (!IsAllConstants || Idx == 0)) {
5607 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5609 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5610 EVT VecVT = MVT::v4i32;
5612 // Truncate the value (which may itself be a constant) to i32, and
5613 // convert it to a vector with movd (S2V+shuffle to zero extend).
5614 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5615 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5617 ISD::BITCAST, dl, VT,
5618 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
5622 // If we have a constant or non-constant insertion into the low element of
5623 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5624 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5625 // depending on what the source datatype is.
5628 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5630 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5631 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5632 if (VT.is256BitVector() || VT.is512BitVector()) {
5633 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5634 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5635 Item, DAG.getIntPtrConstant(0));
5637 assert(VT.is128BitVector() && "Expected an SSE value type!");
5638 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5639 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5640 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5643 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5644 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5645 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5646 if (VT.is256BitVector()) {
5647 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5648 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5650 assert(VT.is128BitVector() && "Expected an SSE value type!");
5651 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5653 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5657 // Is it a vector logical left shift?
5658 if (NumElems == 2 && Idx == 1 &&
5659 X86::isZeroNode(Op.getOperand(0)) &&
5660 !X86::isZeroNode(Op.getOperand(1))) {
5661 unsigned NumBits = VT.getSizeInBits();
5662 return getVShift(true, VT,
5663 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5664 VT, Op.getOperand(1)),
5665 NumBits/2, DAG, *this, dl);
5668 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5671 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5672 // is a non-constant being inserted into an element other than the low one,
5673 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5674 // movd/movss) to move this into the low element, then shuffle it into
5676 if (EVTBits == 32) {
5677 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5678 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5682 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5683 if (Values.size() == 1) {
5684 if (EVTBits == 32) {
5685 // Instead of a shuffle like this:
5686 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5687 // Check if it's possible to issue this instead.
5688 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5689 unsigned Idx = countTrailingZeros(NonZeros);
5690 SDValue Item = Op.getOperand(Idx);
5691 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5692 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5697 // A vector full of immediates; various special cases are already
5698 // handled, so this is best done with a single constant-pool load.
5702 // For AVX-length vectors, see if we can use a vector load to get all of the
5703 // elements, otherwise build the individual 128-bit pieces and use
5704 // shuffles to put them in place.
5705 if (VT.is256BitVector() || VT.is512BitVector()) {
5706 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5708 // Check for a build vector of consecutive loads.
5709 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5712 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5714 // Build both the lower and upper subvector.
5715 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5716 makeArrayRef(&V[0], NumElems/2));
5717 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5718 makeArrayRef(&V[NumElems / 2], NumElems/2));
5720 // Recreate the wider vector with the lower and upper part.
5721 if (VT.is256BitVector())
5722 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5723 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5726 // Let legalizer expand 2-wide build_vectors.
5727 if (EVTBits == 64) {
5728 if (NumNonZero == 1) {
5729 // One half is zero or undef.
5730 unsigned Idx = countTrailingZeros(NonZeros);
5731 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5732 Op.getOperand(Idx));
5733 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5738 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5739 if (EVTBits == 8 && NumElems == 16) {
5740 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5742 if (V.getNode()) return V;
5745 if (EVTBits == 16 && NumElems == 8) {
5746 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5748 if (V.getNode()) return V;
5751 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
5752 if (EVTBits == 32 && NumElems == 4) {
5753 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
5758 // If element VT is == 32 bits, turn it into a number of shuffles.
5759 SmallVector<SDValue, 8> V(NumElems);
5760 if (NumElems == 4 && NumZero > 0) {
5761 for (unsigned i = 0; i < 4; ++i) {
5762 bool isZero = !(NonZeros & (1 << i));
5764 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5766 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5769 for (unsigned i = 0; i < 2; ++i) {
5770 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5773 V[i] = V[i*2]; // Must be a zero vector.
5776 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5779 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5782 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5787 bool Reverse1 = (NonZeros & 0x3) == 2;
5788 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5792 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5793 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5795 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5798 if (Values.size() > 1 && VT.is128BitVector()) {
5799 // Check for a build vector of consecutive loads.
5800 for (unsigned i = 0; i < NumElems; ++i)
5801 V[i] = Op.getOperand(i);
5803 // Check for elements which are consecutive loads.
5804 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
5808 // Check for a build vector from mostly shuffle plus few inserting.
5809 SDValue Sh = buildFromShuffleMostly(Op, DAG);
5813 // For SSE 4.1, use insertps to put the high elements into the low element.
5814 if (Subtarget->hasSSE41()) {
5816 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5817 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5819 Result = DAG.getUNDEF(VT);
5821 for (unsigned i = 1; i < NumElems; ++i) {
5822 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5823 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5824 Op.getOperand(i), DAG.getIntPtrConstant(i));
5829 // Otherwise, expand into a number of unpckl*, start by extending each of
5830 // our (non-undef) elements to the full vector width with the element in the
5831 // bottom slot of the vector (which generates no code for SSE).
5832 for (unsigned i = 0; i < NumElems; ++i) {
5833 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5834 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5836 V[i] = DAG.getUNDEF(VT);
5839 // Next, we iteratively mix elements, e.g. for v4f32:
5840 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5841 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5842 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5843 unsigned EltStride = NumElems >> 1;
5844 while (EltStride != 0) {
5845 for (unsigned i = 0; i < EltStride; ++i) {
5846 // If V[i+EltStride] is undef and this is the first round of mixing,
5847 // then it is safe to just drop this shuffle: V[i] is already in the
5848 // right place, the one element (since it's the first round) being
5849 // inserted as undef can be dropped. This isn't safe for successive
5850 // rounds because they will permute elements within both vectors.
5851 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5852 EltStride == NumElems/2)
5855 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5864 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5865 // to create 256-bit vectors from two other 128-bit ones.
5866 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5868 MVT ResVT = Op.getSimpleValueType();
5870 assert((ResVT.is256BitVector() ||
5871 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
5873 SDValue V1 = Op.getOperand(0);
5874 SDValue V2 = Op.getOperand(1);
5875 unsigned NumElems = ResVT.getVectorNumElements();
5876 if(ResVT.is256BitVector())
5877 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5879 if (Op.getNumOperands() == 4) {
5880 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
5881 ResVT.getVectorNumElements()/2);
5882 SDValue V3 = Op.getOperand(2);
5883 SDValue V4 = Op.getOperand(3);
5884 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
5885 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
5887 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5890 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5891 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
5892 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
5893 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
5894 Op.getNumOperands() == 4)));
5896 // AVX can use the vinsertf128 instruction to create 256-bit vectors
5897 // from two other 128-bit ones.
5899 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
5900 return LowerAVXCONCAT_VECTORS(Op, DAG);
5904 //===----------------------------------------------------------------------===//
5905 // Vector shuffle lowering
5907 // This is an experimental code path for lowering vector shuffles on x86. It is
5908 // designed to handle arbitrary vector shuffles and blends, gracefully
5909 // degrading performance as necessary. It works hard to recognize idiomatic
5910 // shuffles and lower them to optimal instruction patterns without leaving
5911 // a framework that allows reasonably efficient handling of all vector shuffle
5913 //===----------------------------------------------------------------------===//
5915 /// \brief Tiny helper function to identify a no-op mask.
5917 /// This is a somewhat boring predicate function. It checks whether the mask
5918 /// array input, which is assumed to be a single-input shuffle mask of the kind
5919 /// used by the X86 shuffle instructions (not a fully general
5920 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
5921 /// in-place shuffle are 'no-op's.
5922 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
5923 for (int i = 0, Size = Mask.size(); i < Size; ++i)
5924 if (Mask[i] != -1 && Mask[i] != i)
5929 /// \brief Helper function to classify a mask as a single-input mask.
5931 /// This isn't a generic single-input test because in the vector shuffle
5932 /// lowering we canonicalize single inputs to be the first input operand. This
5933 /// means we can more quickly test for a single input by only checking whether
5934 /// an input from the second operand exists. We also assume that the size of
5935 /// mask corresponds to the size of the input vectors which isn't true in the
5936 /// fully general case.
5937 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
5939 if (M >= (int)Mask.size())
5944 /// \brief Test whether there are elements crossing 128-bit lanes in this
5947 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
5948 /// and we routinely test for these.
5949 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
5950 int LaneSize = 128 / VT.getScalarSizeInBits();
5951 int Size = Mask.size();
5952 for (int i = 0; i < Size; ++i)
5953 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
5958 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
5960 /// This checks a shuffle mask to see if it is performing the same
5961 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
5962 /// that it is also not lane-crossing. It may however involve a blend from the
5963 /// same lane of a second vector.
5965 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
5966 /// non-trivial to compute in the face of undef lanes. The representation is
5967 /// *not* suitable for use with existing 128-bit shuffles as it will contain
5968 /// entries from both V1 and V2 inputs to the wider mask.
5970 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
5971 SmallVectorImpl<int> &RepeatedMask) {
5972 int LaneSize = 128 / VT.getScalarSizeInBits();
5973 RepeatedMask.resize(LaneSize, -1);
5974 int Size = Mask.size();
5975 for (int i = 0; i < Size; ++i) {
5978 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
5979 // This entry crosses lanes, so there is no way to model this shuffle.
5982 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
5983 if (RepeatedMask[i % LaneSize] == -1)
5984 // This is the first non-undef entry in this slot of a 128-bit lane.
5985 RepeatedMask[i % LaneSize] =
5986 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
5987 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
5988 // Found a mismatch with the repeated mask.
5994 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
5997 /// This is a fast way to test a shuffle mask against a fixed pattern:
5999 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6001 /// It returns true if the mask is exactly as wide as the argument list, and
6002 /// each element of the mask is either -1 (signifying undef) or the value given
6003 /// in the argument.
6004 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6005 ArrayRef<int> ExpectedMask) {
6006 if (Mask.size() != ExpectedMask.size())
6009 int Size = Mask.size();
6011 // If the values are build vectors, we can look through them to find
6012 // equivalent inputs that make the shuffles equivalent.
6013 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6014 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6016 for (int i = 0; i < Size; ++i)
6017 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6018 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6019 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6020 if (!MaskBV || !ExpectedBV ||
6021 MaskBV->getOperand(Mask[i] % Size) !=
6022 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6029 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6031 /// This helper function produces an 8-bit shuffle immediate corresponding to
6032 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6033 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6036 /// NB: We rely heavily on "undef" masks preserving the input lane.
6037 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
6038 SelectionDAG &DAG) {
6039 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6040 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6041 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6042 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6043 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6046 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6047 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6048 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6049 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6050 return DAG.getConstant(Imm, MVT::i8);
6053 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6055 /// This is used as a fallback approach when first class blend instructions are
6056 /// unavailable. Currently it is only suitable for integer vectors, but could
6057 /// be generalized for floating point vectors if desirable.
6058 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6059 SDValue V2, ArrayRef<int> Mask,
6060 SelectionDAG &DAG) {
6061 assert(VT.isInteger() && "Only supports integer vector types!");
6062 MVT EltVT = VT.getScalarType();
6063 int NumEltBits = EltVT.getSizeInBits();
6064 SDValue Zero = DAG.getConstant(0, EltVT);
6065 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), EltVT);
6066 SmallVector<SDValue, 16> MaskOps;
6067 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6068 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6069 return SDValue(); // Shuffled input!
6070 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6073 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6074 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6075 // We have to cast V2 around.
6076 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6077 V2 = DAG.getNode(ISD::BITCAST, DL, VT,
6078 DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6079 DAG.getNode(ISD::BITCAST, DL, MaskVT, V1Mask),
6080 DAG.getNode(ISD::BITCAST, DL, MaskVT, V2)));
6081 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6084 /// \brief Try to emit a blend instruction for a shuffle.
6086 /// This doesn't do any checks for the availability of instructions for blending
6087 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6088 /// be matched in the backend with the type given. What it does check for is
6089 /// that the shuffle mask is in fact a blend.
6090 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6091 SDValue V2, ArrayRef<int> Mask,
6092 const X86Subtarget *Subtarget,
6093 SelectionDAG &DAG) {
6094 unsigned BlendMask = 0;
6095 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6096 if (Mask[i] >= Size) {
6097 if (Mask[i] != i + Size)
6098 return SDValue(); // Shuffled V2 input!
6099 BlendMask |= 1u << i;
6102 if (Mask[i] >= 0 && Mask[i] != i)
6103 return SDValue(); // Shuffled V1 input!
6105 switch (VT.SimpleTy) {
6110 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6111 DAG.getConstant(BlendMask, MVT::i8));
6115 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6119 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6120 // that instruction.
6121 if (Subtarget->hasAVX2()) {
6122 // Scale the blend by the number of 32-bit dwords per element.
6123 int Scale = VT.getScalarSizeInBits() / 32;
6125 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6126 if (Mask[i] >= Size)
6127 for (int j = 0; j < Scale; ++j)
6128 BlendMask |= 1u << (i * Scale + j);
6130 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6131 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6132 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6133 return DAG.getNode(ISD::BITCAST, DL, VT,
6134 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6135 DAG.getConstant(BlendMask, MVT::i8)));
6139 // For integer shuffles we need to expand the mask and cast the inputs to
6140 // v8i16s prior to blending.
6141 int Scale = 8 / VT.getVectorNumElements();
6143 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6144 if (Mask[i] >= Size)
6145 for (int j = 0; j < Scale; ++j)
6146 BlendMask |= 1u << (i * Scale + j);
6148 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
6149 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
6150 return DAG.getNode(ISD::BITCAST, DL, VT,
6151 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6152 DAG.getConstant(BlendMask, MVT::i8)));
6156 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6157 SmallVector<int, 8> RepeatedMask;
6158 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6159 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6160 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6162 for (int i = 0; i < 8; ++i)
6163 if (RepeatedMask[i] >= 16)
6164 BlendMask |= 1u << i;
6165 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6166 DAG.getConstant(BlendMask, MVT::i8));
6172 // Scale the blend by the number of bytes per element.
6173 int Scale = VT.getScalarSizeInBits() / 8;
6175 // This form of blend is always done on bytes. Compute the byte vector
6177 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6179 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6180 // mix of LLVM's code generator and the x86 backend. We tell the code
6181 // generator that boolean values in the elements of an x86 vector register
6182 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6183 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6184 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6185 // of the element (the remaining are ignored) and 0 in that high bit would
6186 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6187 // the LLVM model for boolean values in vector elements gets the relevant
6188 // bit set, it is set backwards and over constrained relative to x86's
6190 SmallVector<SDValue, 32> VSELECTMask;
6191 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6192 for (int j = 0; j < Scale; ++j)
6193 VSELECTMask.push_back(
6194 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6195 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8));
6197 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6198 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6200 ISD::BITCAST, DL, VT,
6201 DAG.getNode(ISD::VSELECT, DL, BlendVT,
6202 DAG.getNode(ISD::BUILD_VECTOR, DL, BlendVT, VSELECTMask),
6207 llvm_unreachable("Not a supported integer vector type!");
6211 /// \brief Try to lower as a blend of elements from two inputs followed by
6212 /// a single-input permutation.
6214 /// This matches the pattern where we can blend elements from two inputs and
6215 /// then reduce the shuffle to a single-input permutation.
6216 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6219 SelectionDAG &DAG) {
6220 // We build up the blend mask while checking whether a blend is a viable way
6221 // to reduce the shuffle.
6222 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6223 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6225 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6229 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6231 if (BlendMask[Mask[i] % Size] == -1)
6232 BlendMask[Mask[i] % Size] = Mask[i];
6233 else if (BlendMask[Mask[i] % Size] != Mask[i])
6234 return SDValue(); // Can't blend in the needed input!
6236 PermuteMask[i] = Mask[i] % Size;
6239 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6240 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6243 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6244 /// blends and permutes.
6246 /// This matches the extremely common pattern for handling combined
6247 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6248 /// operations. It will try to pick the best arrangement of shuffles and
6250 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6254 SelectionDAG &DAG) {
6255 // Shuffle the input elements into the desired positions in V1 and V2 and
6256 // blend them together.
6257 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6258 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6259 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6260 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6261 if (Mask[i] >= 0 && Mask[i] < Size) {
6262 V1Mask[i] = Mask[i];
6264 } else if (Mask[i] >= Size) {
6265 V2Mask[i] = Mask[i] - Size;
6266 BlendMask[i] = i + Size;
6269 // Try to lower with the simpler initial blend strategy unless one of the
6270 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6271 // shuffle may be able to fold with a load or other benefit. However, when
6272 // we'll have to do 2x as many shuffles in order to achieve this, blending
6273 // first is a better strategy.
6274 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6275 if (SDValue BlendPerm =
6276 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6279 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6280 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6281 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6284 /// \brief Try to lower a vector shuffle as a byte rotation.
6286 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6287 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6288 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6289 /// try to generically lower a vector shuffle through such an pattern. It
6290 /// does not check for the profitability of lowering either as PALIGNR or
6291 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6292 /// This matches shuffle vectors that look like:
6294 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6296 /// Essentially it concatenates V1 and V2, shifts right by some number of
6297 /// elements, and takes the low elements as the result. Note that while this is
6298 /// specified as a *right shift* because x86 is little-endian, it is a *left
6299 /// rotate* of the vector lanes.
6300 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6303 const X86Subtarget *Subtarget,
6304 SelectionDAG &DAG) {
6305 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6307 int NumElts = Mask.size();
6308 int NumLanes = VT.getSizeInBits() / 128;
6309 int NumLaneElts = NumElts / NumLanes;
6311 // We need to detect various ways of spelling a rotation:
6312 // [11, 12, 13, 14, 15, 0, 1, 2]
6313 // [-1, 12, 13, 14, -1, -1, 1, -1]
6314 // [-1, -1, -1, -1, -1, -1, 1, 2]
6315 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6316 // [-1, 4, 5, 6, -1, -1, 9, -1]
6317 // [-1, 4, 5, 6, -1, -1, -1, -1]
6320 for (int l = 0; l < NumElts; l += NumLaneElts) {
6321 for (int i = 0; i < NumLaneElts; ++i) {
6322 if (Mask[l + i] == -1)
6324 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6326 // Get the mod-Size index and lane correct it.
6327 int LaneIdx = (Mask[l + i] % NumElts) - l;
6328 // Make sure it was in this lane.
6329 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6332 // Determine where a rotated vector would have started.
6333 int StartIdx = i - LaneIdx;
6335 // The identity rotation isn't interesting, stop.
6338 // If we found the tail of a vector the rotation must be the missing
6339 // front. If we found the head of a vector, it must be how much of the
6341 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6344 Rotation = CandidateRotation;
6345 else if (Rotation != CandidateRotation)
6346 // The rotations don't match, so we can't match this mask.
6349 // Compute which value this mask is pointing at.
6350 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6352 // Compute which of the two target values this index should be assigned
6353 // to. This reflects whether the high elements are remaining or the low
6354 // elements are remaining.
6355 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6357 // Either set up this value if we've not encountered it before, or check
6358 // that it remains consistent.
6361 else if (TargetV != MaskV)
6362 // This may be a rotation, but it pulls from the inputs in some
6363 // unsupported interleaving.
6368 // Check that we successfully analyzed the mask, and normalize the results.
6369 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6370 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6376 // The actual rotate instruction rotates bytes, so we need to scale the
6377 // rotation based on how many bytes are in the vector lane.
6378 int Scale = 16 / NumLaneElts;
6380 // SSSE3 targets can use the palignr instruction.
6381 if (Subtarget->hasSSSE3()) {
6382 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6383 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6384 Lo = DAG.getNode(ISD::BITCAST, DL, AlignVT, Lo);
6385 Hi = DAG.getNode(ISD::BITCAST, DL, AlignVT, Hi);
6387 return DAG.getNode(ISD::BITCAST, DL, VT,
6388 DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6389 DAG.getConstant(Rotation * Scale, MVT::i8)));
6392 assert(VT.getSizeInBits() == 128 &&
6393 "Rotate-based lowering only supports 128-bit lowering!");
6394 assert(Mask.size() <= 16 &&
6395 "Can shuffle at most 16 bytes in a 128-bit vector!");
6397 // Default SSE2 implementation
6398 int LoByteShift = 16 - Rotation * Scale;
6399 int HiByteShift = Rotation * Scale;
6401 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6402 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
6403 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
6405 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6406 DAG.getConstant(LoByteShift, MVT::i8));
6407 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6408 DAG.getConstant(HiByteShift, MVT::i8));
6409 return DAG.getNode(ISD::BITCAST, DL, VT,
6410 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6413 /// \brief Compute whether each element of a shuffle is zeroable.
6415 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6416 /// Either it is an undef element in the shuffle mask, the element of the input
6417 /// referenced is undef, or the element of the input referenced is known to be
6418 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6419 /// as many lanes with this technique as possible to simplify the remaining
6421 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6422 SDValue V1, SDValue V2) {
6423 SmallBitVector Zeroable(Mask.size(), false);
6425 while (V1.getOpcode() == ISD::BITCAST)
6426 V1 = V1->getOperand(0);
6427 while (V2.getOpcode() == ISD::BITCAST)
6428 V2 = V2->getOperand(0);
6430 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6431 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6433 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6435 // Handle the easy cases.
6436 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6441 // If this is an index into a build_vector node (which has the same number
6442 // of elements), dig out the input value and use it.
6443 SDValue V = M < Size ? V1 : V2;
6444 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6447 SDValue Input = V.getOperand(M % Size);
6448 // The UNDEF opcode check really should be dead code here, but not quite
6449 // worth asserting on (it isn't invalid, just unexpected).
6450 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6457 /// \brief Try to emit a bitmask instruction for a shuffle.
6459 /// This handles cases where we can model a blend exactly as a bitmask due to
6460 /// one of the inputs being zeroable.
6461 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6462 SDValue V2, ArrayRef<int> Mask,
6463 SelectionDAG &DAG) {
6464 MVT EltVT = VT.getScalarType();
6465 int NumEltBits = EltVT.getSizeInBits();
6466 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6467 SDValue Zero = DAG.getConstant(0, IntEltVT);
6468 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), IntEltVT);
6469 if (EltVT.isFloatingPoint()) {
6470 Zero = DAG.getNode(ISD::BITCAST, DL, EltVT, Zero);
6471 AllOnes = DAG.getNode(ISD::BITCAST, DL, EltVT, AllOnes);
6473 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6474 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6476 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6479 if (Mask[i] % Size != i)
6480 return SDValue(); // Not a blend.
6482 V = Mask[i] < Size ? V1 : V2;
6483 else if (V != (Mask[i] < Size ? V1 : V2))
6484 return SDValue(); // Can only let one input through the mask.
6486 VMaskOps[i] = AllOnes;
6489 return SDValue(); // No non-zeroable elements!
6491 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6492 V = DAG.getNode(VT.isFloatingPoint()
6493 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6498 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6500 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6501 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6502 /// matches elements from one of the input vectors shuffled to the left or
6503 /// right with zeroable elements 'shifted in'. It handles both the strictly
6504 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6507 /// PSHL : (little-endian) left bit shift.
6508 /// [ zz, 0, zz, 2 ]
6509 /// [ -1, 4, zz, -1 ]
6510 /// PSRL : (little-endian) right bit shift.
6512 /// [ -1, -1, 7, zz]
6513 /// PSLLDQ : (little-endian) left byte shift
6514 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6515 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6516 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6517 /// PSRLDQ : (little-endian) right byte shift
6518 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6519 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6520 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6521 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6522 SDValue V2, ArrayRef<int> Mask,
6523 SelectionDAG &DAG) {
6524 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6526 int Size = Mask.size();
6527 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6529 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6530 for (int i = 0; i < Size; i += Scale)
6531 for (int j = 0; j < Shift; ++j)
6532 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6538 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6539 for (int i = 0; i != Size; i += Scale) {
6540 unsigned Pos = Left ? i + Shift : i;
6541 unsigned Low = Left ? i : i + Shift;
6542 unsigned Len = Scale - Shift;
6543 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6544 Low + (V == V1 ? 0 : Size)))
6548 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6549 bool ByteShift = ShiftEltBits > 64;
6550 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6551 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6552 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6554 // Normalize the scale for byte shifts to still produce an i64 element
6556 Scale = ByteShift ? Scale / 2 : Scale;
6558 // We need to round trip through the appropriate type for the shift.
6559 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6560 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6561 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6562 "Illegal integer vector type");
6563 V = DAG.getNode(ISD::BITCAST, DL, ShiftVT, V);
6565 V = DAG.getNode(OpCode, DL, ShiftVT, V, DAG.getConstant(ShiftAmt, MVT::i8));
6566 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6569 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6570 // keep doubling the size of the integer elements up to that. We can
6571 // then shift the elements of the integer vector by whole multiples of
6572 // their width within the elements of the larger integer vector. Test each
6573 // multiple to see if we can find a match with the moved element indices
6574 // and that the shifted in elements are all zeroable.
6575 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6576 for (int Shift = 1; Shift != Scale; ++Shift)
6577 for (bool Left : {true, false})
6578 if (CheckZeros(Shift, Scale, Left))
6579 for (SDValue V : {V1, V2})
6580 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6587 /// \brief Lower a vector shuffle as a zero or any extension.
6589 /// Given a specific number of elements, element bit width, and extension
6590 /// stride, produce either a zero or any extension based on the available
6591 /// features of the subtarget.
6592 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6593 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
6594 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6595 assert(Scale > 1 && "Need a scale to extend.");
6596 int NumElements = VT.getVectorNumElements();
6597 int EltBits = VT.getScalarSizeInBits();
6598 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
6599 "Only 8, 16, and 32 bit elements can be extended.");
6600 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
6602 // Found a valid zext mask! Try various lowering strategies based on the
6603 // input type and available ISA extensions.
6604 if (Subtarget->hasSSE41()) {
6605 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
6606 NumElements / Scale);
6607 return DAG.getNode(ISD::BITCAST, DL, VT,
6608 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
6611 // For any extends we can cheat for larger element sizes and use shuffle
6612 // instructions that can fold with a load and/or copy.
6613 if (AnyExt && EltBits == 32) {
6614 int PSHUFDMask[4] = {0, -1, 1, -1};
6616 ISD::BITCAST, DL, VT,
6617 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6618 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6619 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
6621 if (AnyExt && EltBits == 16 && Scale > 2) {
6622 int PSHUFDMask[4] = {0, -1, 0, -1};
6623 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6624 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6625 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
6626 int PSHUFHWMask[4] = {1, -1, -1, -1};
6628 ISD::BITCAST, DL, VT,
6629 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
6630 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
6631 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
6634 // If this would require more than 2 unpack instructions to expand, use
6635 // pshufb when available. We can only use more than 2 unpack instructions
6636 // when zero extending i8 elements which also makes it easier to use pshufb.
6637 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
6638 assert(NumElements == 16 && "Unexpected byte vector width!");
6639 SDValue PSHUFBMask[16];
6640 for (int i = 0; i < 16; ++i)
6642 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
6643 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
6644 return DAG.getNode(ISD::BITCAST, DL, VT,
6645 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
6646 DAG.getNode(ISD::BUILD_VECTOR, DL,
6647 MVT::v16i8, PSHUFBMask)));
6650 // Otherwise emit a sequence of unpacks.
6652 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
6653 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
6654 : getZeroVector(InputVT, Subtarget, DAG, DL);
6655 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
6656 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
6660 } while (Scale > 1);
6661 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
6664 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
6666 /// This routine will try to do everything in its power to cleverly lower
6667 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
6668 /// check for the profitability of this lowering, it tries to aggressively
6669 /// match this pattern. It will use all of the micro-architectural details it
6670 /// can to emit an efficient lowering. It handles both blends with all-zero
6671 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
6672 /// masking out later).
6674 /// The reason we have dedicated lowering for zext-style shuffles is that they
6675 /// are both incredibly common and often quite performance sensitive.
6676 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
6677 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6678 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6679 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6681 int Bits = VT.getSizeInBits();
6682 int NumElements = VT.getVectorNumElements();
6683 assert(VT.getScalarSizeInBits() <= 32 &&
6684 "Exceeds 32-bit integer zero extension limit");
6685 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
6687 // Define a helper function to check a particular ext-scale and lower to it if
6689 auto Lower = [&](int Scale) -> SDValue {
6692 for (int i = 0; i < NumElements; ++i) {
6694 continue; // Valid anywhere but doesn't tell us anything.
6695 if (i % Scale != 0) {
6696 // Each of the extended elements need to be zeroable.
6700 // We no longer are in the anyext case.
6705 // Each of the base elements needs to be consecutive indices into the
6706 // same input vector.
6707 SDValue V = Mask[i] < NumElements ? V1 : V2;
6710 else if (InputV != V)
6711 return SDValue(); // Flip-flopping inputs.
6713 if (Mask[i] % NumElements != i / Scale)
6714 return SDValue(); // Non-consecutive strided elements.
6717 // If we fail to find an input, we have a zero-shuffle which should always
6718 // have already been handled.
6719 // FIXME: Maybe handle this here in case during blending we end up with one?
6723 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6724 DL, VT, Scale, AnyExt, InputV, Subtarget, DAG);
6727 // The widest scale possible for extending is to a 64-bit integer.
6728 assert(Bits % 64 == 0 &&
6729 "The number of bits in a vector must be divisible by 64 on x86!");
6730 int NumExtElements = Bits / 64;
6732 // Each iteration, try extending the elements half as much, but into twice as
6734 for (; NumExtElements < NumElements; NumExtElements *= 2) {
6735 assert(NumElements % NumExtElements == 0 &&
6736 "The input vector size must be divisible by the extended size.");
6737 if (SDValue V = Lower(NumElements / NumExtElements))
6741 // General extends failed, but 128-bit vectors may be able to use MOVQ.
6745 // Returns one of the source operands if the shuffle can be reduced to a
6746 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
6747 auto CanZExtLowHalf = [&]() {
6748 for (int i = NumElements / 2; i != NumElements; ++i)
6751 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
6753 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
6758 if (SDValue V = CanZExtLowHalf()) {
6759 V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V);
6760 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
6761 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6764 // No viable ext lowering found.
6768 /// \brief Try to get a scalar value for a specific element of a vector.
6770 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
6771 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
6772 SelectionDAG &DAG) {
6773 MVT VT = V.getSimpleValueType();
6774 MVT EltVT = VT.getVectorElementType();
6775 while (V.getOpcode() == ISD::BITCAST)
6776 V = V.getOperand(0);
6777 // If the bitcasts shift the element size, we can't extract an equivalent
6779 MVT NewVT = V.getSimpleValueType();
6780 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
6783 if (V.getOpcode() == ISD::BUILD_VECTOR ||
6784 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
6785 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
6790 /// \brief Helper to test for a load that can be folded with x86 shuffles.
6792 /// This is particularly important because the set of instructions varies
6793 /// significantly based on whether the operand is a load or not.
6794 static bool isShuffleFoldableLoad(SDValue V) {
6795 while (V.getOpcode() == ISD::BITCAST)
6796 V = V.getOperand(0);
6798 return ISD::isNON_EXTLoad(V.getNode());
6801 /// \brief Try to lower insertion of a single element into a zero vector.
6803 /// This is a common pattern that we have especially efficient patterns to lower
6804 /// across all subtarget feature sets.
6805 static SDValue lowerVectorShuffleAsElementInsertion(
6806 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6807 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6808 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6810 MVT EltVT = VT.getVectorElementType();
6812 int V2Index = std::find_if(Mask.begin(), Mask.end(),
6813 [&Mask](int M) { return M >= (int)Mask.size(); }) -
6815 bool IsV1Zeroable = true;
6816 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6817 if (i != V2Index && !Zeroable[i]) {
6818 IsV1Zeroable = false;
6822 // Check for a single input from a SCALAR_TO_VECTOR node.
6823 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
6824 // all the smarts here sunk into that routine. However, the current
6825 // lowering of BUILD_VECTOR makes that nearly impossible until the old
6826 // vector shuffle lowering is dead.
6827 if (SDValue V2S = getScalarValueForVectorElement(
6828 V2, Mask[V2Index] - Mask.size(), DAG)) {
6829 // We need to zext the scalar if it is smaller than an i32.
6830 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
6831 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
6832 // Using zext to expand a narrow element won't work for non-zero
6837 // Zero-extend directly to i32.
6839 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
6841 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
6842 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
6843 EltVT == MVT::i16) {
6844 // Either not inserting from the low element of the input or the input
6845 // element size is too small to use VZEXT_MOVL to clear the high bits.
6849 if (!IsV1Zeroable) {
6850 // If V1 can't be treated as a zero vector we have fewer options to lower
6851 // this. We can't support integer vectors or non-zero targets cheaply, and
6852 // the V1 elements can't be permuted in any way.
6853 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
6854 if (!VT.isFloatingPoint() || V2Index != 0)
6856 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
6857 V1Mask[V2Index] = -1;
6858 if (!isNoopShuffleMask(V1Mask))
6860 // This is essentially a special case blend operation, but if we have
6861 // general purpose blend operations, they are always faster. Bail and let
6862 // the rest of the lowering handle these as blends.
6863 if (Subtarget->hasSSE41())
6866 // Otherwise, use MOVSD or MOVSS.
6867 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
6868 "Only two types of floating point element types to handle!");
6869 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
6873 // This lowering only works for the low element with floating point vectors.
6874 if (VT.isFloatingPoint() && V2Index != 0)
6877 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
6879 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
6882 // If we have 4 or fewer lanes we can cheaply shuffle the element into
6883 // the desired position. Otherwise it is more efficient to do a vector
6884 // shift left. We know that we can do a vector shift left because all
6885 // the inputs are zero.
6886 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
6887 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
6888 V2Shuffle[V2Index] = 0;
6889 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
6891 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
6893 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
6895 V2Index * EltVT.getSizeInBits()/8,
6896 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
6897 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
6903 /// \brief Try to lower broadcast of a single element.
6905 /// For convenience, this code also bundles all of the subtarget feature set
6906 /// filtering. While a little annoying to re-dispatch on type here, there isn't
6907 /// a convenient way to factor it out.
6908 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
6910 const X86Subtarget *Subtarget,
6911 SelectionDAG &DAG) {
6912 if (!Subtarget->hasAVX())
6914 if (VT.isInteger() && !Subtarget->hasAVX2())
6917 // Check that the mask is a broadcast.
6918 int BroadcastIdx = -1;
6920 if (M >= 0 && BroadcastIdx == -1)
6922 else if (M >= 0 && M != BroadcastIdx)
6925 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
6926 "a sorted mask where the broadcast "
6929 // Go up the chain of (vector) values to try and find a scalar load that
6930 // we can combine with the broadcast.
6932 switch (V.getOpcode()) {
6933 case ISD::CONCAT_VECTORS: {
6934 int OperandSize = Mask.size() / V.getNumOperands();
6935 V = V.getOperand(BroadcastIdx / OperandSize);
6936 BroadcastIdx %= OperandSize;
6940 case ISD::INSERT_SUBVECTOR: {
6941 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
6942 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
6946 int BeginIdx = (int)ConstantIdx->getZExtValue();
6948 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
6949 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
6950 BroadcastIdx -= BeginIdx;
6961 // Check if this is a broadcast of a scalar. We special case lowering
6962 // for scalars so that we can more effectively fold with loads.
6963 if (V.getOpcode() == ISD::BUILD_VECTOR ||
6964 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
6965 V = V.getOperand(BroadcastIdx);
6967 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
6969 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
6971 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
6972 // We can't broadcast from a vector register w/o AVX2, and we can only
6973 // broadcast from the zero-element of a vector register.
6977 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
6980 // Check for whether we can use INSERTPS to perform the shuffle. We only use
6981 // INSERTPS when the V1 elements are already in the correct locations
6982 // because otherwise we can just always use two SHUFPS instructions which
6983 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
6984 // perform INSERTPS if a single V1 element is out of place and all V2
6985 // elements are zeroable.
6986 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
6988 SelectionDAG &DAG) {
6989 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
6990 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
6991 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
6992 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
6994 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6997 int V1DstIndex = -1;
6998 int V2DstIndex = -1;
6999 bool V1UsedInPlace = false;
7001 for (int i = 0; i < 4; ++i) {
7002 // Synthesize a zero mask from the zeroable elements (includes undefs).
7008 // Flag if we use any V1 inputs in place.
7010 V1UsedInPlace = true;
7014 // We can only insert a single non-zeroable element.
7015 if (V1DstIndex != -1 || V2DstIndex != -1)
7019 // V1 input out of place for insertion.
7022 // V2 input for insertion.
7027 // Don't bother if we have no (non-zeroable) element for insertion.
7028 if (V1DstIndex == -1 && V2DstIndex == -1)
7031 // Determine element insertion src/dst indices. The src index is from the
7032 // start of the inserted vector, not the start of the concatenated vector.
7033 unsigned V2SrcIndex = 0;
7034 if (V1DstIndex != -1) {
7035 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7036 // and don't use the original V2 at all.
7037 V2SrcIndex = Mask[V1DstIndex];
7038 V2DstIndex = V1DstIndex;
7041 V2SrcIndex = Mask[V2DstIndex] - 4;
7044 // If no V1 inputs are used in place, then the result is created only from
7045 // the zero mask and the V2 insertion - so remove V1 dependency.
7047 V1 = DAG.getUNDEF(MVT::v4f32);
7049 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7050 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7052 // Insert the V2 element into the desired position.
7054 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7055 DAG.getConstant(InsertPSMask, MVT::i8));
7058 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7059 /// UNPCK instruction.
7061 /// This specifically targets cases where we end up with alternating between
7062 /// the two inputs, and so can permute them into something that feeds a single
7063 /// UNPCK instruction. Note that this routine only targets integer vectors
7064 /// because for floating point vectors we have a generalized SHUFPS lowering
7065 /// strategy that handles everything that doesn't *exactly* match an unpack,
7066 /// making this clever lowering unnecessary.
7067 static SDValue lowerVectorShuffleAsUnpack(MVT VT, SDLoc DL, SDValue V1,
7068 SDValue V2, ArrayRef<int> Mask,
7069 SelectionDAG &DAG) {
7070 assert(!VT.isFloatingPoint() &&
7071 "This routine only supports integer vectors.");
7072 assert(!isSingleInputShuffleMask(Mask) &&
7073 "This routine should only be used when blending two inputs.");
7074 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7076 int Size = Mask.size();
7078 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7079 return M >= 0 && M % Size < Size / 2;
7081 int NumHiInputs = std::count_if(
7082 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7084 bool UnpackLo = NumLoInputs >= NumHiInputs;
7086 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7087 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7088 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7090 for (int i = 0; i < Size; ++i) {
7094 // Each element of the unpack contains Scale elements from this mask.
7095 int UnpackIdx = i / Scale;
7097 // We only handle the case where V1 feeds the first slots of the unpack.
7098 // We rely on canonicalization to ensure this is the case.
7099 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7102 // Setup the mask for this input. The indexing is tricky as we have to
7103 // handle the unpack stride.
7104 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7105 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7109 // If we will have to shuffle both inputs to use the unpack, check whether
7110 // we can just unpack first and shuffle the result. If so, skip this unpack.
7111 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7112 !isNoopShuffleMask(V2Mask))
7115 // Shuffle the inputs into place.
7116 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7117 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7119 // Cast the inputs to the type we will use to unpack them.
7120 V1 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V1);
7121 V2 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V2);
7123 // Unpack the inputs and cast the result back to the desired type.
7124 return DAG.getNode(ISD::BITCAST, DL, VT,
7125 DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7126 DL, UnpackVT, V1, V2));
7129 // We try each unpack from the largest to the smallest to try and find one
7130 // that fits this mask.
7131 int OrigNumElements = VT.getVectorNumElements();
7132 int OrigScalarSize = VT.getScalarSizeInBits();
7133 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7134 int Scale = ScalarSize / OrigScalarSize;
7135 int NumElements = OrigNumElements / Scale;
7136 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7137 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7141 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7143 if (NumLoInputs == 0 || NumHiInputs == 0) {
7144 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7145 "We have to have *some* inputs!");
7146 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7148 // FIXME: We could consider the total complexity of the permute of each
7149 // possible unpacking. Or at the least we should consider how many
7150 // half-crossings are created.
7151 // FIXME: We could consider commuting the unpacks.
7153 SmallVector<int, 32> PermMask;
7154 PermMask.assign(Size, -1);
7155 for (int i = 0; i < Size; ++i) {
7159 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7162 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7164 return DAG.getVectorShuffle(
7165 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7167 DAG.getUNDEF(VT), PermMask);
7173 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7175 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7176 /// support for floating point shuffles but not integer shuffles. These
7177 /// instructions will incur a domain crossing penalty on some chips though so
7178 /// it is better to avoid lowering through this for integer vectors where
7180 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7181 const X86Subtarget *Subtarget,
7182 SelectionDAG &DAG) {
7184 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7185 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7186 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7187 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7188 ArrayRef<int> Mask = SVOp->getMask();
7189 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7191 if (isSingleInputShuffleMask(Mask)) {
7192 // Use low duplicate instructions for masks that match their pattern.
7193 if (Subtarget->hasSSE3())
7194 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7195 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7197 // Straight shuffle of a single input vector. Simulate this by using the
7198 // single input as both of the "inputs" to this instruction..
7199 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7201 if (Subtarget->hasAVX()) {
7202 // If we have AVX, we can use VPERMILPS which will allow folding a load
7203 // into the shuffle.
7204 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7205 DAG.getConstant(SHUFPDMask, MVT::i8));
7208 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7209 DAG.getConstant(SHUFPDMask, MVT::i8));
7211 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7212 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7214 // If we have a single input, insert that into V1 if we can do so cheaply.
7215 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7216 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7217 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7219 // Try inverting the insertion since for v2 masks it is easy to do and we
7220 // can't reliably sort the mask one way or the other.
7221 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7222 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7223 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7224 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
7228 // Try to use one of the special instruction patterns to handle two common
7229 // blend patterns if a zero-blend above didn't work.
7230 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7231 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7232 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7233 // We can either use a special instruction to load over the low double or
7234 // to move just the low double.
7236 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7238 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7240 if (Subtarget->hasSSE41())
7241 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7245 // Use dedicated unpack instructions for masks that match their pattern.
7246 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7247 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7248 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7249 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7251 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7252 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7253 DAG.getConstant(SHUFPDMask, MVT::i8));
7256 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7258 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7259 /// the integer unit to minimize domain crossing penalties. However, for blends
7260 /// it falls back to the floating point shuffle operation with appropriate bit
7262 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7263 const X86Subtarget *Subtarget,
7264 SelectionDAG &DAG) {
7266 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7267 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7268 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7269 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7270 ArrayRef<int> Mask = SVOp->getMask();
7271 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7273 if (isSingleInputShuffleMask(Mask)) {
7274 // Check for being able to broadcast a single element.
7275 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
7276 Mask, Subtarget, DAG))
7279 // Straight shuffle of a single input vector. For everything from SSE2
7280 // onward this has a single fast instruction with no scary immediates.
7281 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7282 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7283 int WidenedMask[4] = {
7284 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7285 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7287 ISD::BITCAST, DL, MVT::v2i64,
7288 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7289 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7291 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7292 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7293 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7294 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7296 // If we have a blend of two PACKUS operations an the blend aligns with the
7297 // low and half halves, we can just merge the PACKUS operations. This is
7298 // particularly important as it lets us merge shuffles that this routine itself
7300 auto GetPackNode = [](SDValue V) {
7301 while (V.getOpcode() == ISD::BITCAST)
7302 V = V.getOperand(0);
7304 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7306 if (SDValue V1Pack = GetPackNode(V1))
7307 if (SDValue V2Pack = GetPackNode(V2))
7308 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7309 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7310 Mask[0] == 0 ? V1Pack.getOperand(0)
7311 : V1Pack.getOperand(1),
7312 Mask[1] == 2 ? V2Pack.getOperand(0)
7313 : V2Pack.getOperand(1)));
7315 // Try to use shift instructions.
7317 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7320 // When loading a scalar and then shuffling it into a vector we can often do
7321 // the insertion cheaply.
7322 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7323 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7325 // Try inverting the insertion since for v2 masks it is easy to do and we
7326 // can't reliably sort the mask one way or the other.
7327 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7328 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7329 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
7332 // We have different paths for blend lowering, but they all must use the
7333 // *exact* same predicate.
7334 bool IsBlendSupported = Subtarget->hasSSE41();
7335 if (IsBlendSupported)
7336 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7340 // Use dedicated unpack instructions for masks that match their pattern.
7341 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7342 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7343 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7344 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7346 // Try to use byte rotation instructions.
7347 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7348 if (Subtarget->hasSSSE3())
7349 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7350 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7353 // If we have direct support for blends, we should lower by decomposing into
7354 // a permute. That will be faster than the domain cross.
7355 if (IsBlendSupported)
7356 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7359 // We implement this with SHUFPD which is pretty lame because it will likely
7360 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7361 // However, all the alternatives are still more cycles and newer chips don't
7362 // have this problem. It would be really nice if x86 had better shuffles here.
7363 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7364 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7365 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7366 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7369 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7371 /// This is used to disable more specialized lowerings when the shufps lowering
7372 /// will happen to be efficient.
7373 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7374 // This routine only handles 128-bit shufps.
7375 assert(Mask.size() == 4 && "Unsupported mask size!");
7377 // To lower with a single SHUFPS we need to have the low half and high half
7378 // each requiring a single input.
7379 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7381 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7387 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7389 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7390 /// It makes no assumptions about whether this is the *best* lowering, it simply
7392 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7393 ArrayRef<int> Mask, SDValue V1,
7394 SDValue V2, SelectionDAG &DAG) {
7395 SDValue LowV = V1, HighV = V2;
7396 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7399 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7401 if (NumV2Elements == 1) {
7403 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7406 // Compute the index adjacent to V2Index and in the same half by toggling
7408 int V2AdjIndex = V2Index ^ 1;
7410 if (Mask[V2AdjIndex] == -1) {
7411 // Handles all the cases where we have a single V2 element and an undef.
7412 // This will only ever happen in the high lanes because we commute the
7413 // vector otherwise.
7415 std::swap(LowV, HighV);
7416 NewMask[V2Index] -= 4;
7418 // Handle the case where the V2 element ends up adjacent to a V1 element.
7419 // To make this work, blend them together as the first step.
7420 int V1Index = V2AdjIndex;
7421 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7422 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7423 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7425 // Now proceed to reconstruct the final blend as we have the necessary
7426 // high or low half formed.
7433 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7434 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7436 } else if (NumV2Elements == 2) {
7437 if (Mask[0] < 4 && Mask[1] < 4) {
7438 // Handle the easy case where we have V1 in the low lanes and V2 in the
7442 } else if (Mask[2] < 4 && Mask[3] < 4) {
7443 // We also handle the reversed case because this utility may get called
7444 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7445 // arrange things in the right direction.
7451 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7452 // trying to place elements directly, just blend them and set up the final
7453 // shuffle to place them.
7455 // The first two blend mask elements are for V1, the second two are for
7457 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7458 Mask[2] < 4 ? Mask[2] : Mask[3],
7459 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7460 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7461 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7462 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7464 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7467 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7468 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7469 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7470 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7473 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7474 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7477 /// \brief Lower 4-lane 32-bit floating point shuffles.
7479 /// Uses instructions exclusively from the floating point unit to minimize
7480 /// domain crossing penalties, as these are sufficient to implement all v4f32
7482 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7483 const X86Subtarget *Subtarget,
7484 SelectionDAG &DAG) {
7486 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7487 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7488 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7489 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7490 ArrayRef<int> Mask = SVOp->getMask();
7491 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7494 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7496 if (NumV2Elements == 0) {
7497 // Check for being able to broadcast a single element.
7498 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
7499 Mask, Subtarget, DAG))
7502 // Use even/odd duplicate instructions for masks that match their pattern.
7503 if (Subtarget->hasSSE3()) {
7504 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
7505 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
7506 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
7507 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
7510 if (Subtarget->hasAVX()) {
7511 // If we have AVX, we can use VPERMILPS which will allow folding a load
7512 // into the shuffle.
7513 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7514 getV4X86ShuffleImm8ForMask(Mask, DAG));
7517 // Otherwise, use a straight shuffle of a single input vector. We pass the
7518 // input vector to both operands to simulate this with a SHUFPS.
7519 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7520 getV4X86ShuffleImm8ForMask(Mask, DAG));
7523 // There are special ways we can lower some single-element blends. However, we
7524 // have custom ways we can lower more complex single-element blends below that
7525 // we defer to if both this and BLENDPS fail to match, so restrict this to
7526 // when the V2 input is targeting element 0 of the mask -- that is the fast
7528 if (NumV2Elements == 1 && Mask[0] >= 4)
7529 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
7530 Mask, Subtarget, DAG))
7533 if (Subtarget->hasSSE41()) {
7534 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7538 // Use INSERTPS if we can complete the shuffle efficiently.
7539 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
7542 if (!isSingleSHUFPSMask(Mask))
7543 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
7544 DL, MVT::v4f32, V1, V2, Mask, DAG))
7548 // Use dedicated unpack instructions for masks that match their pattern.
7549 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7550 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7551 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7552 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7553 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7554 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
7555 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7556 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
7558 // Otherwise fall back to a SHUFPS lowering strategy.
7559 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7562 /// \brief Lower 4-lane i32 vector shuffles.
7564 /// We try to handle these with integer-domain shuffles where we can, but for
7565 /// blends we use the floating point domain blend instructions.
7566 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7567 const X86Subtarget *Subtarget,
7568 SelectionDAG &DAG) {
7570 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7571 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7572 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7573 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7574 ArrayRef<int> Mask = SVOp->getMask();
7575 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7577 // Whenever we can lower this as a zext, that instruction is strictly faster
7578 // than any alternative. It also allows us to fold memory operands into the
7579 // shuffle in many cases.
7580 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7581 Mask, Subtarget, DAG))
7585 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7587 if (NumV2Elements == 0) {
7588 // Check for being able to broadcast a single element.
7589 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
7590 Mask, Subtarget, DAG))
7593 // Straight shuffle of a single input vector. For everything from SSE2
7594 // onward this has a single fast instruction with no scary immediates.
7595 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7596 // but we aren't actually going to use the UNPCK instruction because doing
7597 // so prevents folding a load into this instruction or making a copy.
7598 const int UnpackLoMask[] = {0, 0, 1, 1};
7599 const int UnpackHiMask[] = {2, 2, 3, 3};
7600 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
7601 Mask = UnpackLoMask;
7602 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
7603 Mask = UnpackHiMask;
7605 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7606 getV4X86ShuffleImm8ForMask(Mask, DAG));
7609 // Try to use shift instructions.
7611 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
7614 // There are special ways we can lower some single-element blends.
7615 if (NumV2Elements == 1)
7616 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
7617 Mask, Subtarget, DAG))
7620 // We have different paths for blend lowering, but they all must use the
7621 // *exact* same predicate.
7622 bool IsBlendSupported = Subtarget->hasSSE41();
7623 if (IsBlendSupported)
7624 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
7628 if (SDValue Masked =
7629 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
7632 // Use dedicated unpack instructions for masks that match their pattern.
7633 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7634 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7635 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7636 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7637 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7638 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
7639 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7640 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
7642 // Try to use byte rotation instructions.
7643 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7644 if (Subtarget->hasSSSE3())
7645 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7646 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
7649 // If we have direct support for blends, we should lower by decomposing into
7650 // a permute. That will be faster than the domain cross.
7651 if (IsBlendSupported)
7652 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
7655 // Try to lower by permuting the inputs into an unpack instruction.
7656 if (SDValue Unpack =
7657 lowerVectorShuffleAsUnpack(MVT::v4i32, DL, V1, V2, Mask, DAG))
7660 // We implement this with SHUFPS because it can blend from two vectors.
7661 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7662 // up the inputs, bypassing domain shift penalties that we would encur if we
7663 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7665 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7666 DAG.getVectorShuffle(
7668 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7669 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7672 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7673 /// shuffle lowering, and the most complex part.
7675 /// The lowering strategy is to try to form pairs of input lanes which are
7676 /// targeted at the same half of the final vector, and then use a dword shuffle
7677 /// to place them onto the right half, and finally unpack the paired lanes into
7678 /// their final position.
7680 /// The exact breakdown of how to form these dword pairs and align them on the
7681 /// correct sides is really tricky. See the comments within the function for
7682 /// more of the details.
7683 static SDValue lowerV8I16SingleInputVectorShuffle(
7684 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
7685 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7686 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7687 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7688 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7690 SmallVector<int, 4> LoInputs;
7691 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7692 [](int M) { return M >= 0; });
7693 std::sort(LoInputs.begin(), LoInputs.end());
7694 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7695 SmallVector<int, 4> HiInputs;
7696 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7697 [](int M) { return M >= 0; });
7698 std::sort(HiInputs.begin(), HiInputs.end());
7699 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7701 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7702 int NumHToL = LoInputs.size() - NumLToL;
7704 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7705 int NumHToH = HiInputs.size() - NumLToH;
7706 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7707 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7708 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7709 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7711 // Check for being able to broadcast a single element.
7712 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
7713 Mask, Subtarget, DAG))
7716 // Try to use shift instructions.
7718 lowerVectorShuffleAsShift(DL, MVT::v8i16, V, V, Mask, DAG))
7721 // Use dedicated unpack instructions for masks that match their pattern.
7722 if (isShuffleEquivalent(V, V, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
7723 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
7724 if (isShuffleEquivalent(V, V, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
7725 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
7727 // Try to use byte rotation instructions.
7728 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7729 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
7732 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7733 // such inputs we can swap two of the dwords across the half mark and end up
7734 // with <=2 inputs to each half in each half. Once there, we can fall through
7735 // to the generic code below. For example:
7737 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7738 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7740 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
7741 // and an existing 2-into-2 on the other half. In this case we may have to
7742 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
7743 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
7744 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
7745 // because any other situation (including a 3-into-1 or 1-into-3 in the other
7746 // half than the one we target for fixing) will be fixed when we re-enter this
7747 // path. We will also combine away any sequence of PSHUFD instructions that
7748 // result into a single instruction. Here is an example of the tricky case:
7750 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7751 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
7753 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
7755 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
7756 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
7758 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
7759 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
7761 // The result is fine to be handled by the generic logic.
7762 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
7763 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
7764 int AOffset, int BOffset) {
7765 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
7766 "Must call this with A having 3 or 1 inputs from the A half.");
7767 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
7768 "Must call this with B having 1 or 3 inputs from the B half.");
7769 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
7770 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
7772 // Compute the index of dword with only one word among the three inputs in
7773 // a half by taking the sum of the half with three inputs and subtracting
7774 // the sum of the actual three inputs. The difference is the remaining
7777 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
7778 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
7779 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
7780 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
7781 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
7782 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
7783 int TripleNonInputIdx =
7784 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
7785 TripleDWord = TripleNonInputIdx / 2;
7787 // We use xor with one to compute the adjacent DWord to whichever one the
7789 OneInputDWord = (OneInput / 2) ^ 1;
7791 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
7792 // and BToA inputs. If there is also such a problem with the BToB and AToB
7793 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
7794 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
7795 // is essential that we don't *create* a 3<-1 as then we might oscillate.
7796 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
7797 // Compute how many inputs will be flipped by swapping these DWords. We
7799 // to balance this to ensure we don't form a 3-1 shuffle in the other
7801 int NumFlippedAToBInputs =
7802 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
7803 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
7804 int NumFlippedBToBInputs =
7805 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
7806 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
7807 if ((NumFlippedAToBInputs == 1 &&
7808 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
7809 (NumFlippedBToBInputs == 1 &&
7810 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
7811 // We choose whether to fix the A half or B half based on whether that
7812 // half has zero flipped inputs. At zero, we may not be able to fix it
7813 // with that half. We also bias towards fixing the B half because that
7814 // will more commonly be the high half, and we have to bias one way.
7815 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
7816 ArrayRef<int> Inputs) {
7817 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
7818 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
7819 PinnedIdx ^ 1) != Inputs.end();
7820 // Determine whether the free index is in the flipped dword or the
7821 // unflipped dword based on where the pinned index is. We use this bit
7822 // in an xor to conditionally select the adjacent dword.
7823 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
7824 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7825 FixFreeIdx) != Inputs.end();
7826 if (IsFixIdxInput == IsFixFreeIdxInput)
7828 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7829 FixFreeIdx) != Inputs.end();
7830 assert(IsFixIdxInput != IsFixFreeIdxInput &&
7831 "We need to be changing the number of flipped inputs!");
7832 int PSHUFHalfMask[] = {0, 1, 2, 3};
7833 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
7834 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
7836 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
7839 if (M != -1 && M == FixIdx)
7841 else if (M != -1 && M == FixFreeIdx)
7844 if (NumFlippedBToBInputs != 0) {
7846 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7847 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
7849 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
7851 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7852 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
7857 int PSHUFDMask[] = {0, 1, 2, 3};
7858 PSHUFDMask[ADWord] = BDWord;
7859 PSHUFDMask[BDWord] = ADWord;
7860 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7861 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7862 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7863 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7865 // Adjust the mask to match the new locations of A and B.
7867 if (M != -1 && M/2 == ADWord)
7868 M = 2 * BDWord + M % 2;
7869 else if (M != -1 && M/2 == BDWord)
7870 M = 2 * ADWord + M % 2;
7872 // Recurse back into this routine to re-compute state now that this isn't
7873 // a 3 and 1 problem.
7874 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7877 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
7878 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
7879 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
7880 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
7882 // At this point there are at most two inputs to the low and high halves from
7883 // each half. That means the inputs can always be grouped into dwords and
7884 // those dwords can then be moved to the correct half with a dword shuffle.
7885 // We use at most one low and one high word shuffle to collect these paired
7886 // inputs into dwords, and finally a dword shuffle to place them.
7887 int PSHUFLMask[4] = {-1, -1, -1, -1};
7888 int PSHUFHMask[4] = {-1, -1, -1, -1};
7889 int PSHUFDMask[4] = {-1, -1, -1, -1};
7891 // First fix the masks for all the inputs that are staying in their
7892 // original halves. This will then dictate the targets of the cross-half
7894 auto fixInPlaceInputs =
7895 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
7896 MutableArrayRef<int> SourceHalfMask,
7897 MutableArrayRef<int> HalfMask, int HalfOffset) {
7898 if (InPlaceInputs.empty())
7900 if (InPlaceInputs.size() == 1) {
7901 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7902 InPlaceInputs[0] - HalfOffset;
7903 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
7906 if (IncomingInputs.empty()) {
7907 // Just fix all of the in place inputs.
7908 for (int Input : InPlaceInputs) {
7909 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
7910 PSHUFDMask[Input / 2] = Input / 2;
7915 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
7916 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7917 InPlaceInputs[0] - HalfOffset;
7918 // Put the second input next to the first so that they are packed into
7919 // a dword. We find the adjacent index by toggling the low bit.
7920 int AdjIndex = InPlaceInputs[0] ^ 1;
7921 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
7922 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
7923 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
7925 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
7926 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
7928 // Now gather the cross-half inputs and place them into a free dword of
7929 // their target half.
7930 // FIXME: This operation could almost certainly be simplified dramatically to
7931 // look more like the 3-1 fixing operation.
7932 auto moveInputsToRightHalf = [&PSHUFDMask](
7933 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
7934 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
7935 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
7937 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
7938 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
7940 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
7942 int LowWord = Word & ~1;
7943 int HighWord = Word | 1;
7944 return isWordClobbered(SourceHalfMask, LowWord) ||
7945 isWordClobbered(SourceHalfMask, HighWord);
7948 if (IncomingInputs.empty())
7951 if (ExistingInputs.empty()) {
7952 // Map any dwords with inputs from them into the right half.
7953 for (int Input : IncomingInputs) {
7954 // If the source half mask maps over the inputs, turn those into
7955 // swaps and use the swapped lane.
7956 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
7957 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
7958 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
7959 Input - SourceOffset;
7960 // We have to swap the uses in our half mask in one sweep.
7961 for (int &M : HalfMask)
7962 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
7964 else if (M == Input)
7965 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7967 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
7968 Input - SourceOffset &&
7969 "Previous placement doesn't match!");
7971 // Note that this correctly re-maps both when we do a swap and when
7972 // we observe the other side of the swap above. We rely on that to
7973 // avoid swapping the members of the input list directly.
7974 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7977 // Map the input's dword into the correct half.
7978 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
7979 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
7981 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
7983 "Previous placement doesn't match!");
7986 // And just directly shift any other-half mask elements to be same-half
7987 // as we will have mirrored the dword containing the element into the
7988 // same position within that half.
7989 for (int &M : HalfMask)
7990 if (M >= SourceOffset && M < SourceOffset + 4) {
7991 M = M - SourceOffset + DestOffset;
7992 assert(M >= 0 && "This should never wrap below zero!");
7997 // Ensure we have the input in a viable dword of its current half. This
7998 // is particularly tricky because the original position may be clobbered
7999 // by inputs being moved and *staying* in that half.
8000 if (IncomingInputs.size() == 1) {
8001 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8002 int InputFixed = std::find(std::begin(SourceHalfMask),
8003 std::end(SourceHalfMask), -1) -
8004 std::begin(SourceHalfMask) + SourceOffset;
8005 SourceHalfMask[InputFixed - SourceOffset] =
8006 IncomingInputs[0] - SourceOffset;
8007 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8009 IncomingInputs[0] = InputFixed;
8011 } else if (IncomingInputs.size() == 2) {
8012 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8013 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8014 // We have two non-adjacent or clobbered inputs we need to extract from
8015 // the source half. To do this, we need to map them into some adjacent
8016 // dword slot in the source mask.
8017 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8018 IncomingInputs[1] - SourceOffset};
8020 // If there is a free slot in the source half mask adjacent to one of
8021 // the inputs, place the other input in it. We use (Index XOR 1) to
8022 // compute an adjacent index.
8023 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8024 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8025 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8026 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8027 InputsFixed[1] = InputsFixed[0] ^ 1;
8028 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8029 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8030 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8031 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8032 InputsFixed[0] = InputsFixed[1] ^ 1;
8033 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8034 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8035 // The two inputs are in the same DWord but it is clobbered and the
8036 // adjacent DWord isn't used at all. Move both inputs to the free
8038 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8039 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8040 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8041 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8043 // The only way we hit this point is if there is no clobbering
8044 // (because there are no off-half inputs to this half) and there is no
8045 // free slot adjacent to one of the inputs. In this case, we have to
8046 // swap an input with a non-input.
8047 for (int i = 0; i < 4; ++i)
8048 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8049 "We can't handle any clobbers here!");
8050 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8051 "Cannot have adjacent inputs here!");
8053 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8054 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8056 // We also have to update the final source mask in this case because
8057 // it may need to undo the above swap.
8058 for (int &M : FinalSourceHalfMask)
8059 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8060 M = InputsFixed[1] + SourceOffset;
8061 else if (M == InputsFixed[1] + SourceOffset)
8062 M = (InputsFixed[0] ^ 1) + SourceOffset;
8064 InputsFixed[1] = InputsFixed[0] ^ 1;
8067 // Point everything at the fixed inputs.
8068 for (int &M : HalfMask)
8069 if (M == IncomingInputs[0])
8070 M = InputsFixed[0] + SourceOffset;
8071 else if (M == IncomingInputs[1])
8072 M = InputsFixed[1] + SourceOffset;
8074 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8075 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8078 llvm_unreachable("Unhandled input size!");
8081 // Now hoist the DWord down to the right half.
8082 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8083 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8084 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8085 for (int &M : HalfMask)
8086 for (int Input : IncomingInputs)
8088 M = FreeDWord * 2 + Input % 2;
8090 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8091 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8092 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8093 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8095 // Now enact all the shuffles we've computed to move the inputs into their
8097 if (!isNoopShuffleMask(PSHUFLMask))
8098 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8099 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8100 if (!isNoopShuffleMask(PSHUFHMask))
8101 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8102 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8103 if (!isNoopShuffleMask(PSHUFDMask))
8104 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8105 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8106 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8107 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8109 // At this point, each half should contain all its inputs, and we can then
8110 // just shuffle them into their final position.
8111 assert(std::count_if(LoMask.begin(), LoMask.end(),
8112 [](int M) { return M >= 4; }) == 0 &&
8113 "Failed to lift all the high half inputs to the low mask!");
8114 assert(std::count_if(HiMask.begin(), HiMask.end(),
8115 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8116 "Failed to lift all the low half inputs to the high mask!");
8118 // Do a half shuffle for the low mask.
8119 if (!isNoopShuffleMask(LoMask))
8120 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8121 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8123 // Do a half shuffle with the high mask after shifting its values down.
8124 for (int &M : HiMask)
8127 if (!isNoopShuffleMask(HiMask))
8128 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8129 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8134 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8135 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8136 SDValue V2, ArrayRef<int> Mask,
8137 SelectionDAG &DAG, bool &V1InUse,
8139 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8145 int Size = Mask.size();
8146 int Scale = 16 / Size;
8147 for (int i = 0; i < 16; ++i) {
8148 if (Mask[i / Scale] == -1) {
8149 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8151 const int ZeroMask = 0x80;
8152 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8154 int V2Idx = Mask[i / Scale] < Size
8156 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8157 if (Zeroable[i / Scale])
8158 V1Idx = V2Idx = ZeroMask;
8159 V1Mask[i] = DAG.getConstant(V1Idx, MVT::i8);
8160 V2Mask[i] = DAG.getConstant(V2Idx, MVT::i8);
8161 V1InUse |= (ZeroMask != V1Idx);
8162 V2InUse |= (ZeroMask != V2Idx);
8167 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8168 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V1),
8169 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8171 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8172 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V2),
8173 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8175 // If we need shuffled inputs from both, blend the two.
8177 if (V1InUse && V2InUse)
8178 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8180 V = V1InUse ? V1 : V2;
8182 // Cast the result back to the correct type.
8183 return DAG.getNode(ISD::BITCAST, DL, VT, V);
8186 /// \brief Generic lowering of 8-lane i16 shuffles.
8188 /// This handles both single-input shuffles and combined shuffle/blends with
8189 /// two inputs. The single input shuffles are immediately delegated to
8190 /// a dedicated lowering routine.
8192 /// The blends are lowered in one of three fundamental ways. If there are few
8193 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8194 /// of the input is significantly cheaper when lowered as an interleaving of
8195 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8196 /// halves of the inputs separately (making them have relatively few inputs)
8197 /// and then concatenate them.
8198 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8199 const X86Subtarget *Subtarget,
8200 SelectionDAG &DAG) {
8202 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8203 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8204 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8205 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8206 ArrayRef<int> OrigMask = SVOp->getMask();
8207 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8208 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8209 MutableArrayRef<int> Mask(MaskStorage);
8211 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8213 // Whenever we can lower this as a zext, that instruction is strictly faster
8214 // than any alternative.
8215 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8216 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8219 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8221 auto isV2 = [](int M) { return M >= 8; };
8223 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8225 if (NumV2Inputs == 0)
8226 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8228 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8229 "All single-input shuffles should be canonicalized to be V1-input "
8232 // Try to use shift instructions.
8234 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8237 // There are special ways we can lower some single-element blends.
8238 if (NumV2Inputs == 1)
8239 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8240 Mask, Subtarget, DAG))
8243 // We have different paths for blend lowering, but they all must use the
8244 // *exact* same predicate.
8245 bool IsBlendSupported = Subtarget->hasSSE41();
8246 if (IsBlendSupported)
8247 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8251 if (SDValue Masked =
8252 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8255 // Use dedicated unpack instructions for masks that match their pattern.
8256 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8257 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8258 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8259 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8261 // Try to use byte rotation instructions.
8262 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8263 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8266 if (SDValue BitBlend =
8267 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8270 if (SDValue Unpack =
8271 lowerVectorShuffleAsUnpack(MVT::v8i16, DL, V1, V2, Mask, DAG))
8274 // If we can't directly blend but can use PSHUFB, that will be better as it
8275 // can both shuffle and set up the inefficient blend.
8276 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8277 bool V1InUse, V2InUse;
8278 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8282 // We can always bit-blend if we have to so the fallback strategy is to
8283 // decompose into single-input permutes and blends.
8284 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8288 /// \brief Check whether a compaction lowering can be done by dropping even
8289 /// elements and compute how many times even elements must be dropped.
8291 /// This handles shuffles which take every Nth element where N is a power of
8292 /// two. Example shuffle masks:
8294 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8295 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8296 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8297 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8298 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8299 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8301 /// Any of these lanes can of course be undef.
8303 /// This routine only supports N <= 3.
8304 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8307 /// \returns N above, or the number of times even elements must be dropped if
8308 /// there is such a number. Otherwise returns zero.
8309 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8310 // Figure out whether we're looping over two inputs or just one.
8311 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8313 // The modulus for the shuffle vector entries is based on whether this is
8314 // a single input or not.
8315 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8316 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8317 "We should only be called with masks with a power-of-2 size!");
8319 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8321 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8322 // and 2^3 simultaneously. This is because we may have ambiguity with
8323 // partially undef inputs.
8324 bool ViableForN[3] = {true, true, true};
8326 for (int i = 0, e = Mask.size(); i < e; ++i) {
8327 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8332 bool IsAnyViable = false;
8333 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8334 if (ViableForN[j]) {
8337 // The shuffle mask must be equal to (i * 2^N) % M.
8338 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8341 ViableForN[j] = false;
8343 // Early exit if we exhaust the possible powers of two.
8348 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8352 // Return 0 as there is no viable power of two.
8356 /// \brief Generic lowering of v16i8 shuffles.
8358 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8359 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8360 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8361 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8363 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8364 const X86Subtarget *Subtarget,
8365 SelectionDAG &DAG) {
8367 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8368 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8369 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8370 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8371 ArrayRef<int> Mask = SVOp->getMask();
8372 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8374 // Try to use shift instructions.
8376 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8379 // Try to use byte rotation instructions.
8380 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8381 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8384 // Try to use a zext lowering.
8385 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8386 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8390 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8392 // For single-input shuffles, there are some nicer lowering tricks we can use.
8393 if (NumV2Elements == 0) {
8394 // Check for being able to broadcast a single element.
8395 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
8396 Mask, Subtarget, DAG))
8399 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8400 // Notably, this handles splat and partial-splat shuffles more efficiently.
8401 // However, it only makes sense if the pre-duplication shuffle simplifies
8402 // things significantly. Currently, this means we need to be able to
8403 // express the pre-duplication shuffle as an i16 shuffle.
8405 // FIXME: We should check for other patterns which can be widened into an
8406 // i16 shuffle as well.
8407 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8408 for (int i = 0; i < 16; i += 2)
8409 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8414 auto tryToWidenViaDuplication = [&]() -> SDValue {
8415 if (!canWidenViaDuplication(Mask))
8417 SmallVector<int, 4> LoInputs;
8418 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8419 [](int M) { return M >= 0 && M < 8; });
8420 std::sort(LoInputs.begin(), LoInputs.end());
8421 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8423 SmallVector<int, 4> HiInputs;
8424 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8425 [](int M) { return M >= 8; });
8426 std::sort(HiInputs.begin(), HiInputs.end());
8427 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8430 bool TargetLo = LoInputs.size() >= HiInputs.size();
8431 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8432 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8434 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8435 SmallDenseMap<int, int, 8> LaneMap;
8436 for (int I : InPlaceInputs) {
8437 PreDupI16Shuffle[I/2] = I/2;
8440 int j = TargetLo ? 0 : 4, je = j + 4;
8441 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8442 // Check if j is already a shuffle of this input. This happens when
8443 // there are two adjacent bytes after we move the low one.
8444 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8445 // If we haven't yet mapped the input, search for a slot into which
8447 while (j < je && PreDupI16Shuffle[j] != -1)
8451 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8454 // Map this input with the i16 shuffle.
8455 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8458 // Update the lane map based on the mapping we ended up with.
8459 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8462 ISD::BITCAST, DL, MVT::v16i8,
8463 DAG.getVectorShuffle(MVT::v8i16, DL,
8464 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8465 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8467 // Unpack the bytes to form the i16s that will be shuffled into place.
8468 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8469 MVT::v16i8, V1, V1);
8471 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8472 for (int i = 0; i < 16; ++i)
8473 if (Mask[i] != -1) {
8474 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8475 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8476 if (PostDupI16Shuffle[i / 2] == -1)
8477 PostDupI16Shuffle[i / 2] = MappedMask;
8479 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8480 "Conflicting entrties in the original shuffle!");
8483 ISD::BITCAST, DL, MVT::v16i8,
8484 DAG.getVectorShuffle(MVT::v8i16, DL,
8485 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8486 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8488 if (SDValue V = tryToWidenViaDuplication())
8492 // Use dedicated unpack instructions for masks that match their pattern.
8493 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8494 0, 16, 1, 17, 2, 18, 3, 19,
8496 4, 20, 5, 21, 6, 22, 7, 23}))
8497 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
8498 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8499 8, 24, 9, 25, 10, 26, 11, 27,
8501 12, 28, 13, 29, 14, 30, 15, 31}))
8502 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
8504 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8505 // with PSHUFB. It is important to do this before we attempt to generate any
8506 // blends but after all of the single-input lowerings. If the single input
8507 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8508 // want to preserve that and we can DAG combine any longer sequences into
8509 // a PSHUFB in the end. But once we start blending from multiple inputs,
8510 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8511 // and there are *very* few patterns that would actually be faster than the
8512 // PSHUFB approach because of its ability to zero lanes.
8514 // FIXME: The only exceptions to the above are blends which are exact
8515 // interleavings with direct instructions supporting them. We currently don't
8516 // handle those well here.
8517 if (Subtarget->hasSSSE3()) {
8518 bool V1InUse = false;
8519 bool V2InUse = false;
8521 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
8522 DAG, V1InUse, V2InUse);
8524 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
8525 // do so. This avoids using them to handle blends-with-zero which is
8526 // important as a single pshufb is significantly faster for that.
8527 if (V1InUse && V2InUse) {
8528 if (Subtarget->hasSSE41())
8529 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
8530 Mask, Subtarget, DAG))
8533 // We can use an unpack to do the blending rather than an or in some
8534 // cases. Even though the or may be (very minorly) more efficient, we
8535 // preference this lowering because there are common cases where part of
8536 // the complexity of the shuffles goes away when we do the final blend as
8538 // FIXME: It might be worth trying to detect if the unpack-feeding
8539 // shuffles will both be pshufb, in which case we shouldn't bother with
8541 if (SDValue Unpack =
8542 lowerVectorShuffleAsUnpack(MVT::v16i8, DL, V1, V2, Mask, DAG))
8549 // There are special ways we can lower some single-element blends.
8550 if (NumV2Elements == 1)
8551 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
8552 Mask, Subtarget, DAG))
8555 if (SDValue BitBlend =
8556 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
8559 // Check whether a compaction lowering can be done. This handles shuffles
8560 // which take every Nth element for some even N. See the helper function for
8563 // We special case these as they can be particularly efficiently handled with
8564 // the PACKUSB instruction on x86 and they show up in common patterns of
8565 // rearranging bytes to truncate wide elements.
8566 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8567 // NumEvenDrops is the power of two stride of the elements. Another way of
8568 // thinking about it is that we need to drop the even elements this many
8569 // times to get the original input.
8570 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8572 // First we need to zero all the dropped bytes.
8573 assert(NumEvenDrops <= 3 &&
8574 "No support for dropping even elements more than 3 times.");
8575 // We use the mask type to pick which bytes are preserved based on how many
8576 // elements are dropped.
8577 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8578 SDValue ByteClearMask =
8579 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8580 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
8581 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8583 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8585 // Now pack things back together.
8586 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8587 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8588 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8589 for (int i = 1; i < NumEvenDrops; ++i) {
8590 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8591 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8597 // Handle multi-input cases by blending single-input shuffles.
8598 if (NumV2Elements > 0)
8599 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
8602 // The fallback path for single-input shuffles widens this into two v8i16
8603 // vectors with unpacks, shuffles those, and then pulls them back together
8607 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8608 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8609 for (int i = 0; i < 16; ++i)
8611 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
8613 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8615 SDValue VLoHalf, VHiHalf;
8616 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8617 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8619 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
8620 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8621 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
8622 [](int M) { return M >= 0 && M % 2 == 1; })) {
8623 // Use a mask to drop the high bytes.
8624 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8625 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
8626 DAG.getConstant(0x00FF, MVT::v8i16));
8628 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
8629 VHiHalf = DAG.getUNDEF(MVT::v8i16);
8631 // Squash the masks to point directly into VLoHalf.
8632 for (int &M : LoBlendMask)
8635 for (int &M : HiBlendMask)
8639 // Otherwise just unpack the low half of V into VLoHalf and the high half into
8640 // VHiHalf so that we can blend them as i16s.
8641 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8642 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8643 VHiHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8644 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8647 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
8648 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
8650 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8653 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8655 /// This routine breaks down the specific type of 128-bit shuffle and
8656 /// dispatches to the lowering routines accordingly.
8657 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8658 MVT VT, const X86Subtarget *Subtarget,
8659 SelectionDAG &DAG) {
8660 switch (VT.SimpleTy) {
8662 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8664 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8666 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8668 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8670 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8672 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8675 llvm_unreachable("Unimplemented!");
8679 /// \brief Helper function to test whether a shuffle mask could be
8680 /// simplified by widening the elements being shuffled.
8682 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
8683 /// leaves it in an unspecified state.
8685 /// NOTE: This must handle normal vector shuffle masks and *target* vector
8686 /// shuffle masks. The latter have the special property of a '-2' representing
8687 /// a zero-ed lane of a vector.
8688 static bool canWidenShuffleElements(ArrayRef<int> Mask,
8689 SmallVectorImpl<int> &WidenedMask) {
8690 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
8691 // If both elements are undef, its trivial.
8692 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
8693 WidenedMask.push_back(SM_SentinelUndef);
8697 // Check for an undef mask and a mask value properly aligned to fit with
8698 // a pair of values. If we find such a case, use the non-undef mask's value.
8699 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
8700 WidenedMask.push_back(Mask[i + 1] / 2);
8703 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
8704 WidenedMask.push_back(Mask[i] / 2);
8708 // When zeroing, we need to spread the zeroing across both lanes to widen.
8709 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
8710 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
8711 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
8712 WidenedMask.push_back(SM_SentinelZero);
8718 // Finally check if the two mask values are adjacent and aligned with
8720 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
8721 WidenedMask.push_back(Mask[i] / 2);
8725 // Otherwise we can't safely widen the elements used in this shuffle.
8728 assert(WidenedMask.size() == Mask.size() / 2 &&
8729 "Incorrect size of mask after widening the elements!");
8734 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
8736 /// This routine just extracts two subvectors, shuffles them independently, and
8737 /// then concatenates them back together. This should work effectively with all
8738 /// AVX vector shuffle types.
8739 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
8740 SDValue V2, ArrayRef<int> Mask,
8741 SelectionDAG &DAG) {
8742 assert(VT.getSizeInBits() >= 256 &&
8743 "Only for 256-bit or wider vector shuffles!");
8744 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
8745 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
8747 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
8748 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
8750 int NumElements = VT.getVectorNumElements();
8751 int SplitNumElements = NumElements / 2;
8752 MVT ScalarVT = VT.getScalarType();
8753 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
8755 // Rather than splitting build-vectors, just build two narrower build
8756 // vectors. This helps shuffling with splats and zeros.
8757 auto SplitVector = [&](SDValue V) {
8758 while (V.getOpcode() == ISD::BITCAST)
8759 V = V->getOperand(0);
8761 MVT OrigVT = V.getSimpleValueType();
8762 int OrigNumElements = OrigVT.getVectorNumElements();
8763 int OrigSplitNumElements = OrigNumElements / 2;
8764 MVT OrigScalarVT = OrigVT.getScalarType();
8765 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
8769 auto *BV = dyn_cast<BuildVectorSDNode>(V);
8771 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
8772 DAG.getIntPtrConstant(0));
8773 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
8774 DAG.getIntPtrConstant(OrigSplitNumElements));
8777 SmallVector<SDValue, 16> LoOps, HiOps;
8778 for (int i = 0; i < OrigSplitNumElements; ++i) {
8779 LoOps.push_back(BV->getOperand(i));
8780 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
8782 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
8783 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
8785 return std::make_pair(DAG.getNode(ISD::BITCAST, DL, SplitVT, LoV),
8786 DAG.getNode(ISD::BITCAST, DL, SplitVT, HiV));
8789 SDValue LoV1, HiV1, LoV2, HiV2;
8790 std::tie(LoV1, HiV1) = SplitVector(V1);
8791 std::tie(LoV2, HiV2) = SplitVector(V2);
8793 // Now create two 4-way blends of these half-width vectors.
8794 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
8795 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
8796 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
8797 for (int i = 0; i < SplitNumElements; ++i) {
8798 int M = HalfMask[i];
8799 if (M >= NumElements) {
8800 if (M >= NumElements + SplitNumElements)
8804 V2BlendMask.push_back(M - NumElements);
8805 V1BlendMask.push_back(-1);
8806 BlendMask.push_back(SplitNumElements + i);
8807 } else if (M >= 0) {
8808 if (M >= SplitNumElements)
8812 V2BlendMask.push_back(-1);
8813 V1BlendMask.push_back(M);
8814 BlendMask.push_back(i);
8816 V2BlendMask.push_back(-1);
8817 V1BlendMask.push_back(-1);
8818 BlendMask.push_back(-1);
8822 // Because the lowering happens after all combining takes place, we need to
8823 // manually combine these blend masks as much as possible so that we create
8824 // a minimal number of high-level vector shuffle nodes.
8826 // First try just blending the halves of V1 or V2.
8827 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
8828 return DAG.getUNDEF(SplitVT);
8829 if (!UseLoV2 && !UseHiV2)
8830 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
8831 if (!UseLoV1 && !UseHiV1)
8832 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
8834 SDValue V1Blend, V2Blend;
8835 if (UseLoV1 && UseHiV1) {
8837 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
8839 // We only use half of V1 so map the usage down into the final blend mask.
8840 V1Blend = UseLoV1 ? LoV1 : HiV1;
8841 for (int i = 0; i < SplitNumElements; ++i)
8842 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
8843 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
8845 if (UseLoV2 && UseHiV2) {
8847 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
8849 // We only use half of V2 so map the usage down into the final blend mask.
8850 V2Blend = UseLoV2 ? LoV2 : HiV2;
8851 for (int i = 0; i < SplitNumElements; ++i)
8852 if (BlendMask[i] >= SplitNumElements)
8853 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
8855 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
8857 SDValue Lo = HalfBlend(LoMask);
8858 SDValue Hi = HalfBlend(HiMask);
8859 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
8862 /// \brief Either split a vector in halves or decompose the shuffles and the
8865 /// This is provided as a good fallback for many lowerings of non-single-input
8866 /// shuffles with more than one 128-bit lane. In those cases, we want to select
8867 /// between splitting the shuffle into 128-bit components and stitching those
8868 /// back together vs. extracting the single-input shuffles and blending those
8870 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
8871 SDValue V2, ArrayRef<int> Mask,
8872 SelectionDAG &DAG) {
8873 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
8874 "lower single-input shuffles as it "
8875 "could then recurse on itself.");
8876 int Size = Mask.size();
8878 // If this can be modeled as a broadcast of two elements followed by a blend,
8879 // prefer that lowering. This is especially important because broadcasts can
8880 // often fold with memory operands.
8881 auto DoBothBroadcast = [&] {
8882 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
8885 if (V2BroadcastIdx == -1)
8886 V2BroadcastIdx = M - Size;
8887 else if (M - Size != V2BroadcastIdx)
8889 } else if (M >= 0) {
8890 if (V1BroadcastIdx == -1)
8892 else if (M != V1BroadcastIdx)
8897 if (DoBothBroadcast())
8898 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
8901 // If the inputs all stem from a single 128-bit lane of each input, then we
8902 // split them rather than blending because the split will decompose to
8903 // unusually few instructions.
8904 int LaneCount = VT.getSizeInBits() / 128;
8905 int LaneSize = Size / LaneCount;
8906 SmallBitVector LaneInputs[2];
8907 LaneInputs[0].resize(LaneCount, false);
8908 LaneInputs[1].resize(LaneCount, false);
8909 for (int i = 0; i < Size; ++i)
8911 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
8912 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
8913 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
8915 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
8916 // that the decomposed single-input shuffles don't end up here.
8917 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
8920 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
8921 /// a permutation and blend of those lanes.
8923 /// This essentially blends the out-of-lane inputs to each lane into the lane
8924 /// from a permuted copy of the vector. This lowering strategy results in four
8925 /// instructions in the worst case for a single-input cross lane shuffle which
8926 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
8927 /// of. Special cases for each particular shuffle pattern should be handled
8928 /// prior to trying this lowering.
8929 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
8930 SDValue V1, SDValue V2,
8932 SelectionDAG &DAG) {
8933 // FIXME: This should probably be generalized for 512-bit vectors as well.
8934 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
8935 int LaneSize = Mask.size() / 2;
8937 // If there are only inputs from one 128-bit lane, splitting will in fact be
8938 // less expensive. The flags track wether the given lane contains an element
8939 // that crosses to another lane.
8940 bool LaneCrossing[2] = {false, false};
8941 for (int i = 0, Size = Mask.size(); i < Size; ++i)
8942 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
8943 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
8944 if (!LaneCrossing[0] || !LaneCrossing[1])
8945 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
8947 if (isSingleInputShuffleMask(Mask)) {
8948 SmallVector<int, 32> FlippedBlendMask;
8949 for (int i = 0, Size = Mask.size(); i < Size; ++i)
8950 FlippedBlendMask.push_back(
8951 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
8953 : Mask[i] % LaneSize +
8954 (i / LaneSize) * LaneSize + Size));
8956 // Flip the vector, and blend the results which should now be in-lane. The
8957 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
8958 // 5 for the high source. The value 3 selects the high half of source 2 and
8959 // the value 2 selects the low half of source 2. We only use source 2 to
8960 // allow folding it into a memory operand.
8961 unsigned PERMMask = 3 | 2 << 4;
8962 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
8963 V1, DAG.getConstant(PERMMask, MVT::i8));
8964 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
8967 // This now reduces to two single-input shuffles of V1 and V2 which at worst
8968 // will be handled by the above logic and a blend of the results, much like
8969 // other patterns in AVX.
8970 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
8973 /// \brief Handle lowering 2-lane 128-bit shuffles.
8974 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
8975 SDValue V2, ArrayRef<int> Mask,
8976 const X86Subtarget *Subtarget,
8977 SelectionDAG &DAG) {
8978 // Blends are faster and handle all the non-lane-crossing cases.
8979 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
8983 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
8984 VT.getVectorNumElements() / 2);
8985 // Check for patterns which can be matched with a single insert of a 128-bit
8987 if (isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1}) ||
8988 isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
8989 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
8990 DAG.getIntPtrConstant(0));
8991 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
8992 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
8993 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
8995 if (isShuffleEquivalent(V1, V2, Mask, {0, 1, 6, 7})) {
8996 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
8997 DAG.getIntPtrConstant(0));
8998 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
8999 DAG.getIntPtrConstant(2));
9000 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9003 // Otherwise form a 128-bit permutation.
9004 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9005 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9006 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9007 DAG.getConstant(PermMask, MVT::i8));
9010 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9011 /// shuffling each lane.
9013 /// This will only succeed when the result of fixing the 128-bit lanes results
9014 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9015 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9016 /// the lane crosses early and then use simpler shuffles within each lane.
9018 /// FIXME: It might be worthwhile at some point to support this without
9019 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9020 /// in x86 only floating point has interesting non-repeating shuffles, and even
9021 /// those are still *marginally* more expensive.
9022 static SDValue lowerVectorShuffleByMerging128BitLanes(
9023 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9024 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9025 assert(!isSingleInputShuffleMask(Mask) &&
9026 "This is only useful with multiple inputs.");
9028 int Size = Mask.size();
9029 int LaneSize = 128 / VT.getScalarSizeInBits();
9030 int NumLanes = Size / LaneSize;
9031 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9033 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9034 // check whether the in-128-bit lane shuffles share a repeating pattern.
9035 SmallVector<int, 4> Lanes;
9036 Lanes.resize(NumLanes, -1);
9037 SmallVector<int, 4> InLaneMask;
9038 InLaneMask.resize(LaneSize, -1);
9039 for (int i = 0; i < Size; ++i) {
9043 int j = i / LaneSize;
9046 // First entry we've seen for this lane.
9047 Lanes[j] = Mask[i] / LaneSize;
9048 } else if (Lanes[j] != Mask[i] / LaneSize) {
9049 // This doesn't match the lane selected previously!
9053 // Check that within each lane we have a consistent shuffle mask.
9054 int k = i % LaneSize;
9055 if (InLaneMask[k] < 0) {
9056 InLaneMask[k] = Mask[i] % LaneSize;
9057 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9058 // This doesn't fit a repeating in-lane mask.
9063 // First shuffle the lanes into place.
9064 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9065 VT.getSizeInBits() / 64);
9066 SmallVector<int, 8> LaneMask;
9067 LaneMask.resize(NumLanes * 2, -1);
9068 for (int i = 0; i < NumLanes; ++i)
9069 if (Lanes[i] >= 0) {
9070 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9071 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9074 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
9075 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
9076 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9078 // Cast it back to the type we actually want.
9079 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
9081 // Now do a simple shuffle that isn't lane crossing.
9082 SmallVector<int, 8> NewMask;
9083 NewMask.resize(Size, -1);
9084 for (int i = 0; i < Size; ++i)
9086 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9087 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9088 "Must not introduce lane crosses at this point!");
9090 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9093 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9096 /// This returns true if the elements from a particular input are already in the
9097 /// slot required by the given mask and require no permutation.
9098 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9099 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9100 int Size = Mask.size();
9101 for (int i = 0; i < Size; ++i)
9102 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9108 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9110 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9111 /// isn't available.
9112 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9113 const X86Subtarget *Subtarget,
9114 SelectionDAG &DAG) {
9116 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9117 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9118 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9119 ArrayRef<int> Mask = SVOp->getMask();
9120 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9122 SmallVector<int, 4> WidenedMask;
9123 if (canWidenShuffleElements(Mask, WidenedMask))
9124 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9127 if (isSingleInputShuffleMask(Mask)) {
9128 // Check for being able to broadcast a single element.
9129 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
9130 Mask, Subtarget, DAG))
9133 // Use low duplicate instructions for masks that match their pattern.
9134 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9135 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9137 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9138 // Non-half-crossing single input shuffles can be lowerid with an
9139 // interleaved permutation.
9140 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9141 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9142 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9143 DAG.getConstant(VPERMILPMask, MVT::i8));
9146 // With AVX2 we have direct support for this permutation.
9147 if (Subtarget->hasAVX2())
9148 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9149 getV4X86ShuffleImm8ForMask(Mask, DAG));
9151 // Otherwise, fall back.
9152 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9156 // X86 has dedicated unpack instructions that can handle specific blend
9157 // operations: UNPCKH and UNPCKL.
9158 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9159 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9160 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9161 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9162 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9163 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9164 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9165 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9167 // If we have a single input to the zero element, insert that into V1 if we
9168 // can do so cheaply.
9170 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9171 if (NumV2Elements == 1 && Mask[0] >= 4)
9172 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9173 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9176 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9180 // Check if the blend happens to exactly fit that of SHUFPD.
9181 if ((Mask[0] == -1 || Mask[0] < 2) &&
9182 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9183 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9184 (Mask[3] == -1 || Mask[3] >= 6)) {
9185 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9186 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9187 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9188 DAG.getConstant(SHUFPDMask, MVT::i8));
9190 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9191 (Mask[1] == -1 || Mask[1] < 2) &&
9192 (Mask[2] == -1 || Mask[2] >= 6) &&
9193 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9194 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9195 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9196 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9197 DAG.getConstant(SHUFPDMask, MVT::i8));
9200 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9201 // shuffle. However, if we have AVX2 and either inputs are already in place,
9202 // we will be able to shuffle even across lanes the other input in a single
9203 // instruction so skip this pattern.
9204 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9205 isShuffleMaskInputInPlace(1, Mask))))
9206 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9207 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9210 // If we have AVX2 then we always want to lower with a blend because an v4 we
9211 // can fully permute the elements.
9212 if (Subtarget->hasAVX2())
9213 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9216 // Otherwise fall back on generic lowering.
9217 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9220 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9222 /// This routine is only called when we have AVX2 and thus a reasonable
9223 /// instruction set for v4i64 shuffling..
9224 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9225 const X86Subtarget *Subtarget,
9226 SelectionDAG &DAG) {
9228 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9229 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9230 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9231 ArrayRef<int> Mask = SVOp->getMask();
9232 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9233 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9235 SmallVector<int, 4> WidenedMask;
9236 if (canWidenShuffleElements(Mask, WidenedMask))
9237 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9240 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9244 // Check for being able to broadcast a single element.
9245 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
9246 Mask, Subtarget, DAG))
9249 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9250 // use lower latency instructions that will operate on both 128-bit lanes.
9251 SmallVector<int, 2> RepeatedMask;
9252 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9253 if (isSingleInputShuffleMask(Mask)) {
9254 int PSHUFDMask[] = {-1, -1, -1, -1};
9255 for (int i = 0; i < 2; ++i)
9256 if (RepeatedMask[i] >= 0) {
9257 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9258 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9261 ISD::BITCAST, DL, MVT::v4i64,
9262 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9263 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9264 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9268 // AVX2 provides a direct instruction for permuting a single input across
9270 if (isSingleInputShuffleMask(Mask))
9271 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9272 getV4X86ShuffleImm8ForMask(Mask, DAG));
9274 // Try to use shift instructions.
9276 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9279 // Use dedicated unpack instructions for masks that match their pattern.
9280 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9281 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9282 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9283 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9284 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9285 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9286 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9287 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9289 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9290 // shuffle. However, if we have AVX2 and either inputs are already in place,
9291 // we will be able to shuffle even across lanes the other input in a single
9292 // instruction so skip this pattern.
9293 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9294 isShuffleMaskInputInPlace(1, Mask))))
9295 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9296 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9299 // Otherwise fall back on generic blend lowering.
9300 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9304 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9306 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9307 /// isn't available.
9308 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9309 const X86Subtarget *Subtarget,
9310 SelectionDAG &DAG) {
9312 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9313 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9314 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9315 ArrayRef<int> Mask = SVOp->getMask();
9316 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9318 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9322 // Check for being able to broadcast a single element.
9323 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
9324 Mask, Subtarget, DAG))
9327 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9328 // options to efficiently lower the shuffle.
9329 SmallVector<int, 4> RepeatedMask;
9330 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9331 assert(RepeatedMask.size() == 4 &&
9332 "Repeated masks must be half the mask width!");
9334 // Use even/odd duplicate instructions for masks that match their pattern.
9335 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9336 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9337 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9338 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9340 if (isSingleInputShuffleMask(Mask))
9341 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9342 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9344 // Use dedicated unpack instructions for masks that match their pattern.
9345 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9346 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9347 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9348 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9349 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9350 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9351 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9352 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9354 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9355 // have already handled any direct blends. We also need to squash the
9356 // repeated mask into a simulated v4f32 mask.
9357 for (int i = 0; i < 4; ++i)
9358 if (RepeatedMask[i] >= 8)
9359 RepeatedMask[i] -= 4;
9360 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9363 // If we have a single input shuffle with different shuffle patterns in the
9364 // two 128-bit lanes use the variable mask to VPERMILPS.
9365 if (isSingleInputShuffleMask(Mask)) {
9366 SDValue VPermMask[8];
9367 for (int i = 0; i < 8; ++i)
9368 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9369 : DAG.getConstant(Mask[i], MVT::i32);
9370 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9372 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9373 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9375 if (Subtarget->hasAVX2())
9376 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9377 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9378 DAG.getNode(ISD::BUILD_VECTOR, DL,
9379 MVT::v8i32, VPermMask)),
9382 // Otherwise, fall back.
9383 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9387 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9389 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9390 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9393 // If we have AVX2 then we always want to lower with a blend because at v8 we
9394 // can fully permute the elements.
9395 if (Subtarget->hasAVX2())
9396 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9399 // Otherwise fall back on generic lowering.
9400 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9403 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9405 /// This routine is only called when we have AVX2 and thus a reasonable
9406 /// instruction set for v8i32 shuffling..
9407 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9408 const X86Subtarget *Subtarget,
9409 SelectionDAG &DAG) {
9411 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9412 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9413 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9414 ArrayRef<int> Mask = SVOp->getMask();
9415 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9416 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9418 // Whenever we can lower this as a zext, that instruction is strictly faster
9419 // than any alternative. It also allows us to fold memory operands into the
9420 // shuffle in many cases.
9421 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9422 Mask, Subtarget, DAG))
9425 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9429 // Check for being able to broadcast a single element.
9430 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
9431 Mask, Subtarget, DAG))
9434 // If the shuffle mask is repeated in each 128-bit lane we can use more
9435 // efficient instructions that mirror the shuffles across the two 128-bit
9437 SmallVector<int, 4> RepeatedMask;
9438 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9439 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9440 if (isSingleInputShuffleMask(Mask))
9441 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9442 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9444 // Use dedicated unpack instructions for masks that match their pattern.
9445 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9446 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9447 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9448 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9449 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9450 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
9451 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9452 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
9455 // Try to use shift instructions.
9457 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
9460 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9461 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9464 // If the shuffle patterns aren't repeated but it is a single input, directly
9465 // generate a cross-lane VPERMD instruction.
9466 if (isSingleInputShuffleMask(Mask)) {
9467 SDValue VPermMask[8];
9468 for (int i = 0; i < 8; ++i)
9469 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9470 : DAG.getConstant(Mask[i], MVT::i32);
9472 X86ISD::VPERMV, DL, MVT::v8i32,
9473 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9476 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9478 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9479 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9482 // Otherwise fall back on generic blend lowering.
9483 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9487 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9489 /// This routine is only called when we have AVX2 and thus a reasonable
9490 /// instruction set for v16i16 shuffling..
9491 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9492 const X86Subtarget *Subtarget,
9493 SelectionDAG &DAG) {
9495 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9496 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9497 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9498 ArrayRef<int> Mask = SVOp->getMask();
9499 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9500 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9502 // Whenever we can lower this as a zext, that instruction is strictly faster
9503 // than any alternative. It also allows us to fold memory operands into the
9504 // shuffle in many cases.
9505 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
9506 Mask, Subtarget, DAG))
9509 // Check for being able to broadcast a single element.
9510 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
9511 Mask, Subtarget, DAG))
9514 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9518 // Use dedicated unpack instructions for masks that match their pattern.
9519 if (isShuffleEquivalent(V1, V2, Mask,
9520 {// First 128-bit lane:
9521 0, 16, 1, 17, 2, 18, 3, 19,
9522 // Second 128-bit lane:
9523 8, 24, 9, 25, 10, 26, 11, 27}))
9524 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9525 if (isShuffleEquivalent(V1, V2, Mask,
9526 {// First 128-bit lane:
9527 4, 20, 5, 21, 6, 22, 7, 23,
9528 // Second 128-bit lane:
9529 12, 28, 13, 29, 14, 30, 15, 31}))
9530 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9532 // Try to use shift instructions.
9534 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
9537 // Try to use byte rotation instructions.
9538 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9539 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9542 if (isSingleInputShuffleMask(Mask)) {
9543 // There are no generalized cross-lane shuffle operations available on i16
9545 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9546 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9549 SDValue PSHUFBMask[32];
9550 for (int i = 0; i < 16; ++i) {
9551 if (Mask[i] == -1) {
9552 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9556 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9557 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9558 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
9559 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
9562 ISD::BITCAST, DL, MVT::v16i16,
9564 X86ISD::PSHUFB, DL, MVT::v32i8,
9565 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9566 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9569 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9571 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9572 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9575 // Otherwise fall back on generic lowering.
9576 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
9579 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9581 /// This routine is only called when we have AVX2 and thus a reasonable
9582 /// instruction set for v32i8 shuffling..
9583 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9584 const X86Subtarget *Subtarget,
9585 SelectionDAG &DAG) {
9587 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9588 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9589 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9590 ArrayRef<int> Mask = SVOp->getMask();
9591 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9592 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9594 // Whenever we can lower this as a zext, that instruction is strictly faster
9595 // than any alternative. It also allows us to fold memory operands into the
9596 // shuffle in many cases.
9597 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
9598 Mask, Subtarget, DAG))
9601 // Check for being able to broadcast a single element.
9602 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
9603 Mask, Subtarget, DAG))
9606 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9610 // Use dedicated unpack instructions for masks that match their pattern.
9611 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9613 if (isShuffleEquivalent(
9615 {// First 128-bit lane:
9616 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9617 // Second 128-bit lane:
9618 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
9619 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9620 if (isShuffleEquivalent(
9622 {// First 128-bit lane:
9623 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9624 // Second 128-bit lane:
9625 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
9626 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9628 // Try to use shift instructions.
9630 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
9633 // Try to use byte rotation instructions.
9634 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9635 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9638 if (isSingleInputShuffleMask(Mask)) {
9639 // There are no generalized cross-lane shuffle operations available on i8
9641 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9642 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9645 SDValue PSHUFBMask[32];
9646 for (int i = 0; i < 32; ++i)
9649 ? DAG.getUNDEF(MVT::i8)
9650 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
9653 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9654 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9657 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9659 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9660 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9663 // Otherwise fall back on generic lowering.
9664 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
9667 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9669 /// This routine either breaks down the specific type of a 256-bit x86 vector
9670 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9671 /// together based on the available instructions.
9672 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9673 MVT VT, const X86Subtarget *Subtarget,
9674 SelectionDAG &DAG) {
9676 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9677 ArrayRef<int> Mask = SVOp->getMask();
9679 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9680 // check for those subtargets here and avoid much of the subtarget querying in
9681 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9682 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9683 // floating point types there eventually, just immediately cast everything to
9684 // a float and operate entirely in that domain.
9685 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9686 int ElementBits = VT.getScalarSizeInBits();
9687 if (ElementBits < 32)
9688 // No floating point type available, decompose into 128-bit vectors.
9689 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9691 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9692 VT.getVectorNumElements());
9693 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9694 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9695 return DAG.getNode(ISD::BITCAST, DL, VT,
9696 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9699 switch (VT.SimpleTy) {
9701 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9703 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9705 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9707 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9709 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9711 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9714 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9718 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
9719 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9720 const X86Subtarget *Subtarget,
9721 SelectionDAG &DAG) {
9723 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9724 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9725 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9726 ArrayRef<int> Mask = SVOp->getMask();
9727 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9729 // X86 has dedicated unpack instructions that can handle specific blend
9730 // operations: UNPCKH and UNPCKL.
9731 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
9732 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
9733 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
9734 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
9736 // FIXME: Implement direct support for this type!
9737 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
9740 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
9741 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9742 const X86Subtarget *Subtarget,
9743 SelectionDAG &DAG) {
9745 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9746 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9747 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9748 ArrayRef<int> Mask = SVOp->getMask();
9749 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9751 // Use dedicated unpack instructions for masks that match their pattern.
9752 if (isShuffleEquivalent(V1, V2, Mask,
9753 {// First 128-bit lane.
9754 0, 16, 1, 17, 4, 20, 5, 21,
9755 // Second 128-bit lane.
9756 8, 24, 9, 25, 12, 28, 13, 29}))
9757 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
9758 if (isShuffleEquivalent(V1, V2, Mask,
9759 {// First 128-bit lane.
9760 2, 18, 3, 19, 6, 22, 7, 23,
9761 // Second 128-bit lane.
9762 10, 26, 11, 27, 14, 30, 15, 31}))
9763 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
9765 // FIXME: Implement direct support for this type!
9766 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
9769 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
9770 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9771 const X86Subtarget *Subtarget,
9772 SelectionDAG &DAG) {
9774 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
9775 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
9776 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9777 ArrayRef<int> Mask = SVOp->getMask();
9778 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9780 // X86 has dedicated unpack instructions that can handle specific blend
9781 // operations: UNPCKH and UNPCKL.
9782 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
9783 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
9784 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
9785 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
9787 // FIXME: Implement direct support for this type!
9788 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
9791 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
9792 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9793 const X86Subtarget *Subtarget,
9794 SelectionDAG &DAG) {
9796 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
9797 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
9798 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9799 ArrayRef<int> Mask = SVOp->getMask();
9800 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9802 // Use dedicated unpack instructions for masks that match their pattern.
9803 if (isShuffleEquivalent(V1, V2, Mask,
9804 {// First 128-bit lane.
9805 0, 16, 1, 17, 4, 20, 5, 21,
9806 // Second 128-bit lane.
9807 8, 24, 9, 25, 12, 28, 13, 29}))
9808 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
9809 if (isShuffleEquivalent(V1, V2, Mask,
9810 {// First 128-bit lane.
9811 2, 18, 3, 19, 6, 22, 7, 23,
9812 // Second 128-bit lane.
9813 10, 26, 11, 27, 14, 30, 15, 31}))
9814 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
9816 // FIXME: Implement direct support for this type!
9817 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
9820 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
9821 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9822 const X86Subtarget *Subtarget,
9823 SelectionDAG &DAG) {
9825 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
9826 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
9827 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9828 ArrayRef<int> Mask = SVOp->getMask();
9829 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9830 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
9832 // FIXME: Implement direct support for this type!
9833 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
9836 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
9837 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9838 const X86Subtarget *Subtarget,
9839 SelectionDAG &DAG) {
9841 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
9842 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
9843 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9844 ArrayRef<int> Mask = SVOp->getMask();
9845 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
9846 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
9848 // FIXME: Implement direct support for this type!
9849 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
9852 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
9854 /// This routine either breaks down the specific type of a 512-bit x86 vector
9855 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
9856 /// together based on the available instructions.
9857 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9858 MVT VT, const X86Subtarget *Subtarget,
9859 SelectionDAG &DAG) {
9861 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9862 ArrayRef<int> Mask = SVOp->getMask();
9863 assert(Subtarget->hasAVX512() &&
9864 "Cannot lower 512-bit vectors w/ basic ISA!");
9866 // Check for being able to broadcast a single element.
9867 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
9868 Mask, Subtarget, DAG))
9871 // Dispatch to each element type for lowering. If we don't have supprot for
9872 // specific element type shuffles at 512 bits, immediately split them and
9873 // lower them. Each lowering routine of a given type is allowed to assume that
9874 // the requisite ISA extensions for that element type are available.
9875 switch (VT.SimpleTy) {
9877 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9879 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9881 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9883 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9885 if (Subtarget->hasBWI())
9886 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9889 if (Subtarget->hasBWI())
9890 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9894 llvm_unreachable("Not a valid 512-bit x86 vector type!");
9897 // Otherwise fall back on splitting.
9898 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9901 /// \brief Top-level lowering for x86 vector shuffles.
9903 /// This handles decomposition, canonicalization, and lowering of all x86
9904 /// vector shuffles. Most of the specific lowering strategies are encapsulated
9905 /// above in helper routines. The canonicalization attempts to widen shuffles
9906 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
9907 /// s.t. only one of the two inputs needs to be tested, etc.
9908 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9909 SelectionDAG &DAG) {
9910 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9911 ArrayRef<int> Mask = SVOp->getMask();
9912 SDValue V1 = Op.getOperand(0);
9913 SDValue V2 = Op.getOperand(1);
9914 MVT VT = Op.getSimpleValueType();
9915 int NumElements = VT.getVectorNumElements();
9918 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9920 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9921 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9922 if (V1IsUndef && V2IsUndef)
9923 return DAG.getUNDEF(VT);
9925 // When we create a shuffle node we put the UNDEF node to second operand,
9926 // but in some cases the first operand may be transformed to UNDEF.
9927 // In this case we should just commute the node.
9929 return DAG.getCommutedVectorShuffle(*SVOp);
9931 // Check for non-undef masks pointing at an undef vector and make the masks
9932 // undef as well. This makes it easier to match the shuffle based solely on
9936 if (M >= NumElements) {
9937 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
9938 for (int &M : NewMask)
9939 if (M >= NumElements)
9941 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
9944 // We actually see shuffles that are entirely re-arrangements of a set of
9945 // zero inputs. This mostly happens while decomposing complex shuffles into
9946 // simple ones. Directly lower these as a buildvector of zeros.
9947 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9949 return getZeroVector(VT, Subtarget, DAG, dl);
9951 // Try to collapse shuffles into using a vector type with fewer elements but
9952 // wider element types. We cap this to not form integers or floating point
9953 // elements wider than 64 bits, but it might be interesting to form i128
9954 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
9955 SmallVector<int, 16> WidenedMask;
9956 if (VT.getScalarSizeInBits() < 64 &&
9957 canWidenShuffleElements(Mask, WidenedMask)) {
9958 MVT NewEltVT = VT.isFloatingPoint()
9959 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
9960 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
9961 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
9962 // Make sure that the new vector type is legal. For example, v2f64 isn't
9964 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
9965 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
9966 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
9967 return DAG.getNode(ISD::BITCAST, dl, VT,
9968 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
9972 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
9973 for (int M : SVOp->getMask())
9976 else if (M < NumElements)
9981 // Commute the shuffle as needed such that more elements come from V1 than
9982 // V2. This allows us to match the shuffle pattern strictly on how many
9983 // elements come from V1 without handling the symmetric cases.
9984 if (NumV2Elements > NumV1Elements)
9985 return DAG.getCommutedVectorShuffle(*SVOp);
9987 // When the number of V1 and V2 elements are the same, try to minimize the
9988 // number of uses of V2 in the low half of the vector. When that is tied,
9989 // ensure that the sum of indices for V1 is equal to or lower than the sum
9990 // indices for V2. When those are equal, try to ensure that the number of odd
9991 // indices for V1 is lower than the number of odd indices for V2.
9992 if (NumV1Elements == NumV2Elements) {
9993 int LowV1Elements = 0, LowV2Elements = 0;
9994 for (int M : SVOp->getMask().slice(0, NumElements / 2))
9995 if (M >= NumElements)
9999 if (LowV2Elements > LowV1Elements) {
10000 return DAG.getCommutedVectorShuffle(*SVOp);
10001 } else if (LowV2Elements == LowV1Elements) {
10002 int SumV1Indices = 0, SumV2Indices = 0;
10003 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10004 if (SVOp->getMask()[i] >= NumElements)
10006 else if (SVOp->getMask()[i] >= 0)
10008 if (SumV2Indices < SumV1Indices) {
10009 return DAG.getCommutedVectorShuffle(*SVOp);
10010 } else if (SumV2Indices == SumV1Indices) {
10011 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10012 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10013 if (SVOp->getMask()[i] >= NumElements)
10014 NumV2OddIndices += i % 2;
10015 else if (SVOp->getMask()[i] >= 0)
10016 NumV1OddIndices += i % 2;
10017 if (NumV2OddIndices < NumV1OddIndices)
10018 return DAG.getCommutedVectorShuffle(*SVOp);
10023 // For each vector width, delegate to a specialized lowering routine.
10024 if (VT.getSizeInBits() == 128)
10025 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10027 if (VT.getSizeInBits() == 256)
10028 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10030 // Force AVX-512 vectors to be scalarized for now.
10031 // FIXME: Implement AVX-512 support!
10032 if (VT.getSizeInBits() == 512)
10033 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10035 llvm_unreachable("Unimplemented!");
10038 // This function assumes its argument is a BUILD_VECTOR of constants or
10039 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10041 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10042 unsigned &MaskValue) {
10044 unsigned NumElems = BuildVector->getNumOperands();
10045 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10046 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10047 unsigned NumElemsInLane = NumElems / NumLanes;
10049 // Blend for v16i16 should be symetric for the both lanes.
10050 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10051 SDValue EltCond = BuildVector->getOperand(i);
10052 SDValue SndLaneEltCond =
10053 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10055 int Lane1Cond = -1, Lane2Cond = -1;
10056 if (isa<ConstantSDNode>(EltCond))
10057 Lane1Cond = !isZero(EltCond);
10058 if (isa<ConstantSDNode>(SndLaneEltCond))
10059 Lane2Cond = !isZero(SndLaneEltCond);
10061 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10062 // Lane1Cond != 0, means we want the first argument.
10063 // Lane1Cond == 0, means we want the second argument.
10064 // The encoding of this argument is 0 for the first argument, 1
10065 // for the second. Therefore, invert the condition.
10066 MaskValue |= !Lane1Cond << i;
10067 else if (Lane1Cond < 0)
10068 MaskValue |= !Lane2Cond << i;
10075 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10076 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10077 const X86Subtarget *Subtarget,
10078 SelectionDAG &DAG) {
10079 SDValue Cond = Op.getOperand(0);
10080 SDValue LHS = Op.getOperand(1);
10081 SDValue RHS = Op.getOperand(2);
10083 MVT VT = Op.getSimpleValueType();
10085 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10087 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10089 // Only non-legal VSELECTs reach this lowering, convert those into generic
10090 // shuffles and re-use the shuffle lowering path for blends.
10091 SmallVector<int, 32> Mask;
10092 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10093 SDValue CondElt = CondBV->getOperand(i);
10095 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10097 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10100 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10101 // A vselect where all conditions and data are constants can be optimized into
10102 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10103 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10104 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10105 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10108 // Try to lower this to a blend-style vector shuffle. This can handle all
10109 // constant condition cases.
10110 SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG);
10111 if (BlendOp.getNode())
10114 // Variable blends are only legal from SSE4.1 onward.
10115 if (!Subtarget->hasSSE41())
10118 // Some types for vselect were previously set to Expand, not Legal or
10119 // Custom. Return an empty SDValue so we fall-through to Expand, after
10120 // the Custom lowering phase.
10121 MVT VT = Op.getSimpleValueType();
10122 switch (VT.SimpleTy) {
10127 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10132 // We couldn't create a "Blend with immediate" node.
10133 // This node should still be legal, but we'll have to emit a blendv*
10138 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10139 MVT VT = Op.getSimpleValueType();
10142 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10145 if (VT.getSizeInBits() == 8) {
10146 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10147 Op.getOperand(0), Op.getOperand(1));
10148 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10149 DAG.getValueType(VT));
10150 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10153 if (VT.getSizeInBits() == 16) {
10154 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10155 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10157 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10158 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10159 DAG.getNode(ISD::BITCAST, dl,
10162 Op.getOperand(1)));
10163 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10164 Op.getOperand(0), Op.getOperand(1));
10165 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10166 DAG.getValueType(VT));
10167 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10170 if (VT == MVT::f32) {
10171 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10172 // the result back to FR32 register. It's only worth matching if the
10173 // result has a single use which is a store or a bitcast to i32. And in
10174 // the case of a store, it's not worth it if the index is a constant 0,
10175 // because a MOVSSmr can be used instead, which is smaller and faster.
10176 if (!Op.hasOneUse())
10178 SDNode *User = *Op.getNode()->use_begin();
10179 if ((User->getOpcode() != ISD::STORE ||
10180 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10181 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10182 (User->getOpcode() != ISD::BITCAST ||
10183 User->getValueType(0) != MVT::i32))
10185 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10186 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10189 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10192 if (VT == MVT::i32 || VT == MVT::i64) {
10193 // ExtractPS/pextrq works with constant index.
10194 if (isa<ConstantSDNode>(Op.getOperand(1)))
10200 /// Extract one bit from mask vector, like v16i1 or v8i1.
10201 /// AVX-512 feature.
10203 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10204 SDValue Vec = Op.getOperand(0);
10206 MVT VecVT = Vec.getSimpleValueType();
10207 SDValue Idx = Op.getOperand(1);
10208 MVT EltVT = Op.getSimpleValueType();
10210 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10211 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10212 "Unexpected vector type in ExtractBitFromMaskVector");
10214 // variable index can't be handled in mask registers,
10215 // extend vector to VR512
10216 if (!isa<ConstantSDNode>(Idx)) {
10217 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10218 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10219 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10220 ExtVT.getVectorElementType(), Ext, Idx);
10221 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10224 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10225 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10226 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10227 rc = getRegClassFor(MVT::v16i1);
10228 unsigned MaxSift = rc->getSize()*8 - 1;
10229 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10230 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10231 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10232 DAG.getConstant(MaxSift, MVT::i8));
10233 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10234 DAG.getIntPtrConstant(0));
10238 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10239 SelectionDAG &DAG) const {
10241 SDValue Vec = Op.getOperand(0);
10242 MVT VecVT = Vec.getSimpleValueType();
10243 SDValue Idx = Op.getOperand(1);
10245 if (Op.getSimpleValueType() == MVT::i1)
10246 return ExtractBitFromMaskVector(Op, DAG);
10248 if (!isa<ConstantSDNode>(Idx)) {
10249 if (VecVT.is512BitVector() ||
10250 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10251 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10254 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10255 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10256 MaskEltVT.getSizeInBits());
10258 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10259 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10260 getZeroVector(MaskVT, Subtarget, DAG, dl),
10261 Idx, DAG.getConstant(0, getPointerTy()));
10262 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10263 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10264 Perm, DAG.getConstant(0, getPointerTy()));
10269 // If this is a 256-bit vector result, first extract the 128-bit vector and
10270 // then extract the element from the 128-bit vector.
10271 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10273 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10274 // Get the 128-bit vector.
10275 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10276 MVT EltVT = VecVT.getVectorElementType();
10278 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10280 //if (IdxVal >= NumElems/2)
10281 // IdxVal -= NumElems/2;
10282 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10283 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10284 DAG.getConstant(IdxVal, MVT::i32));
10287 assert(VecVT.is128BitVector() && "Unexpected vector length");
10289 if (Subtarget->hasSSE41()) {
10290 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10295 MVT VT = Op.getSimpleValueType();
10296 // TODO: handle v16i8.
10297 if (VT.getSizeInBits() == 16) {
10298 SDValue Vec = Op.getOperand(0);
10299 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10301 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10302 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10303 DAG.getNode(ISD::BITCAST, dl,
10305 Op.getOperand(1)));
10306 // Transform it so it match pextrw which produces a 32-bit result.
10307 MVT EltVT = MVT::i32;
10308 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10309 Op.getOperand(0), Op.getOperand(1));
10310 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10311 DAG.getValueType(VT));
10312 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10315 if (VT.getSizeInBits() == 32) {
10316 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10320 // SHUFPS the element to the lowest double word, then movss.
10321 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10322 MVT VVT = Op.getOperand(0).getSimpleValueType();
10323 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10324 DAG.getUNDEF(VVT), Mask);
10325 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10326 DAG.getIntPtrConstant(0));
10329 if (VT.getSizeInBits() == 64) {
10330 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10331 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10332 // to match extract_elt for f64.
10333 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10337 // UNPCKHPD the element to the lowest double word, then movsd.
10338 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10339 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10340 int Mask[2] = { 1, -1 };
10341 MVT VVT = Op.getOperand(0).getSimpleValueType();
10342 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10343 DAG.getUNDEF(VVT), Mask);
10344 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10345 DAG.getIntPtrConstant(0));
10351 /// Insert one bit to mask vector, like v16i1 or v8i1.
10352 /// AVX-512 feature.
10354 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10356 SDValue Vec = Op.getOperand(0);
10357 SDValue Elt = Op.getOperand(1);
10358 SDValue Idx = Op.getOperand(2);
10359 MVT VecVT = Vec.getSimpleValueType();
10361 if (!isa<ConstantSDNode>(Idx)) {
10362 // Non constant index. Extend source and destination,
10363 // insert element and then truncate the result.
10364 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10365 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10366 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10367 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10368 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10369 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10372 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10373 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10374 if (Vec.getOpcode() == ISD::UNDEF)
10375 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10376 DAG.getConstant(IdxVal, MVT::i8));
10377 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10378 unsigned MaxSift = rc->getSize()*8 - 1;
10379 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10380 DAG.getConstant(MaxSift, MVT::i8));
10381 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10382 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10383 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10386 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10387 SelectionDAG &DAG) const {
10388 MVT VT = Op.getSimpleValueType();
10389 MVT EltVT = VT.getVectorElementType();
10391 if (EltVT == MVT::i1)
10392 return InsertBitToMaskVector(Op, DAG);
10395 SDValue N0 = Op.getOperand(0);
10396 SDValue N1 = Op.getOperand(1);
10397 SDValue N2 = Op.getOperand(2);
10398 if (!isa<ConstantSDNode>(N2))
10400 auto *N2C = cast<ConstantSDNode>(N2);
10401 unsigned IdxVal = N2C->getZExtValue();
10403 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10404 // into that, and then insert the subvector back into the result.
10405 if (VT.is256BitVector() || VT.is512BitVector()) {
10406 // Get the desired 128-bit vector half.
10407 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10409 // Insert the element into the desired half.
10410 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10411 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
10413 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10414 DAG.getConstant(IdxIn128, MVT::i32));
10416 // Insert the changed part back to the 256-bit vector
10417 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10419 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
10421 if (Subtarget->hasSSE41()) {
10422 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
10424 if (VT == MVT::v8i16) {
10425 Opc = X86ISD::PINSRW;
10427 assert(VT == MVT::v16i8);
10428 Opc = X86ISD::PINSRB;
10431 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10433 if (N1.getValueType() != MVT::i32)
10434 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10435 if (N2.getValueType() != MVT::i32)
10436 N2 = DAG.getIntPtrConstant(IdxVal);
10437 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10440 if (EltVT == MVT::f32) {
10441 // Bits [7:6] of the constant are the source select. This will always be
10442 // zero here. The DAG Combiner may combine an extract_elt index into
10444 // bits. For example (insert (extract, 3), 2) could be matched by
10446 // the '3' into bits [7:6] of X86ISD::INSERTPS.
10447 // Bits [5:4] of the constant are the destination select. This is the
10448 // value of the incoming immediate.
10449 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10450 // combine either bitwise AND or insert of float 0.0 to set these bits.
10451 N2 = DAG.getIntPtrConstant(IdxVal << 4);
10452 // Create this as a scalar to vector..
10453 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10454 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10457 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
10458 // PINSR* works with constant index.
10463 if (EltVT == MVT::i8)
10466 if (EltVT.getSizeInBits() == 16) {
10467 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10468 // as its second argument.
10469 if (N1.getValueType() != MVT::i32)
10470 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10471 if (N2.getValueType() != MVT::i32)
10472 N2 = DAG.getIntPtrConstant(IdxVal);
10473 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10478 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10480 MVT OpVT = Op.getSimpleValueType();
10482 // If this is a 256-bit vector result, first insert into a 128-bit
10483 // vector and then insert into the 256-bit vector.
10484 if (!OpVT.is128BitVector()) {
10485 // Insert into a 128-bit vector.
10486 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10487 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10488 OpVT.getVectorNumElements() / SizeFactor);
10490 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10492 // Insert the 128-bit vector.
10493 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10496 if (OpVT == MVT::v1i64 &&
10497 Op.getOperand(0).getValueType() == MVT::i64)
10498 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10500 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10501 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10502 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10503 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10506 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10507 // a simple subregister reference or explicit instructions to grab
10508 // upper bits of a vector.
10509 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10510 SelectionDAG &DAG) {
10512 SDValue In = Op.getOperand(0);
10513 SDValue Idx = Op.getOperand(1);
10514 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10515 MVT ResVT = Op.getSimpleValueType();
10516 MVT InVT = In.getSimpleValueType();
10518 if (Subtarget->hasFp256()) {
10519 if (ResVT.is128BitVector() &&
10520 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10521 isa<ConstantSDNode>(Idx)) {
10522 return Extract128BitVector(In, IdxVal, DAG, dl);
10524 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10525 isa<ConstantSDNode>(Idx)) {
10526 return Extract256BitVector(In, IdxVal, DAG, dl);
10532 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10533 // simple superregister reference or explicit instructions to insert
10534 // the upper bits of a vector.
10535 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10536 SelectionDAG &DAG) {
10537 if (!Subtarget->hasAVX())
10541 SDValue Vec = Op.getOperand(0);
10542 SDValue SubVec = Op.getOperand(1);
10543 SDValue Idx = Op.getOperand(2);
10545 if (!isa<ConstantSDNode>(Idx))
10548 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10549 MVT OpVT = Op.getSimpleValueType();
10550 MVT SubVecVT = SubVec.getSimpleValueType();
10552 // Fold two 16-byte subvector loads into one 32-byte load:
10553 // (insert_subvector (insert_subvector undef, (load addr), 0),
10554 // (load addr + 16), Elts/2)
10556 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
10557 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
10558 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
10559 !Subtarget->isUnalignedMem32Slow()) {
10560 SDValue SubVec2 = Vec.getOperand(1);
10561 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
10562 if (Idx2->getZExtValue() == 0) {
10563 SDValue Ops[] = { SubVec2, SubVec };
10564 SDValue LD = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false);
10571 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
10572 SubVecVT.is128BitVector())
10573 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10575 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
10576 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10581 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10582 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10583 // one of the above mentioned nodes. It has to be wrapped because otherwise
10584 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10585 // be used to form addressing mode. These wrapped nodes will be selected
10588 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10589 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10591 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10592 // global base reg.
10593 unsigned char OpFlag = 0;
10594 unsigned WrapperKind = X86ISD::Wrapper;
10595 CodeModel::Model M = DAG.getTarget().getCodeModel();
10597 if (Subtarget->isPICStyleRIPRel() &&
10598 (M == CodeModel::Small || M == CodeModel::Kernel))
10599 WrapperKind = X86ISD::WrapperRIP;
10600 else if (Subtarget->isPICStyleGOT())
10601 OpFlag = X86II::MO_GOTOFF;
10602 else if (Subtarget->isPICStyleStubPIC())
10603 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10605 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10606 CP->getAlignment(),
10607 CP->getOffset(), OpFlag);
10609 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10610 // With PIC, the address is actually $g + Offset.
10612 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10613 DAG.getNode(X86ISD::GlobalBaseReg,
10614 SDLoc(), getPointerTy()),
10621 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10622 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10624 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10625 // global base reg.
10626 unsigned char OpFlag = 0;
10627 unsigned WrapperKind = X86ISD::Wrapper;
10628 CodeModel::Model M = DAG.getTarget().getCodeModel();
10630 if (Subtarget->isPICStyleRIPRel() &&
10631 (M == CodeModel::Small || M == CodeModel::Kernel))
10632 WrapperKind = X86ISD::WrapperRIP;
10633 else if (Subtarget->isPICStyleGOT())
10634 OpFlag = X86II::MO_GOTOFF;
10635 else if (Subtarget->isPICStyleStubPIC())
10636 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10638 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10641 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10643 // With PIC, the address is actually $g + Offset.
10645 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10646 DAG.getNode(X86ISD::GlobalBaseReg,
10647 SDLoc(), getPointerTy()),
10654 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
10655 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10657 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10658 // global base reg.
10659 unsigned char OpFlag = 0;
10660 unsigned WrapperKind = X86ISD::Wrapper;
10661 CodeModel::Model M = DAG.getTarget().getCodeModel();
10663 if (Subtarget->isPICStyleRIPRel() &&
10664 (M == CodeModel::Small || M == CodeModel::Kernel)) {
10665 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10666 OpFlag = X86II::MO_GOTPCREL;
10667 WrapperKind = X86ISD::WrapperRIP;
10668 } else if (Subtarget->isPICStyleGOT()) {
10669 OpFlag = X86II::MO_GOT;
10670 } else if (Subtarget->isPICStyleStubPIC()) {
10671 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10672 } else if (Subtarget->isPICStyleStubNoDynamic()) {
10673 OpFlag = X86II::MO_DARWIN_NONLAZY;
10676 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10679 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10681 // With PIC, the address is actually $g + Offset.
10682 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10683 !Subtarget->is64Bit()) {
10684 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10685 DAG.getNode(X86ISD::GlobalBaseReg,
10686 SDLoc(), getPointerTy()),
10690 // For symbols that require a load from a stub to get the address, emit the
10692 if (isGlobalStubReference(OpFlag))
10693 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
10694 MachinePointerInfo::getGOT(), false, false, false, 0);
10700 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
10701 // Create the TargetBlockAddressAddress node.
10702 unsigned char OpFlags =
10703 Subtarget->ClassifyBlockAddressReference();
10704 CodeModel::Model M = DAG.getTarget().getCodeModel();
10705 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
10706 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
10708 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
10711 if (Subtarget->isPICStyleRIPRel() &&
10712 (M == CodeModel::Small || M == CodeModel::Kernel))
10713 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10715 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10717 // With PIC, the address is actually $g + Offset.
10718 if (isGlobalRelativeToPICBase(OpFlags)) {
10719 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10720 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10728 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
10729 int64_t Offset, SelectionDAG &DAG) const {
10730 // Create the TargetGlobalAddress node, folding in the constant
10731 // offset if it is legal.
10732 unsigned char OpFlags =
10733 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
10734 CodeModel::Model M = DAG.getTarget().getCodeModel();
10736 if (OpFlags == X86II::MO_NO_FLAG &&
10737 X86::isOffsetSuitableForCodeModel(Offset, M)) {
10738 // A direct static reference to a global.
10739 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
10742 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
10745 if (Subtarget->isPICStyleRIPRel() &&
10746 (M == CodeModel::Small || M == CodeModel::Kernel))
10747 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10749 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10751 // With PIC, the address is actually $g + Offset.
10752 if (isGlobalRelativeToPICBase(OpFlags)) {
10753 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10754 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10758 // For globals that require a load from a stub to get the address, emit the
10760 if (isGlobalStubReference(OpFlags))
10761 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
10762 MachinePointerInfo::getGOT(), false, false, false, 0);
10764 // If there was a non-zero offset that we didn't fold, create an explicit
10765 // addition for it.
10767 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
10768 DAG.getConstant(Offset, getPointerTy()));
10774 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
10775 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
10776 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
10777 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
10781 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
10782 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
10783 unsigned char OperandFlags, bool LocalDynamic = false) {
10784 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10785 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10787 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10788 GA->getValueType(0),
10792 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
10796 SDValue Ops[] = { Chain, TGA, *InFlag };
10797 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10799 SDValue Ops[] = { Chain, TGA };
10800 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10803 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
10804 MFI->setAdjustsStack(true);
10805 MFI->setHasCalls(true);
10807 SDValue Flag = Chain.getValue(1);
10808 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
10811 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
10813 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10816 SDLoc dl(GA); // ? function entry point might be better
10817 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10818 DAG.getNode(X86ISD::GlobalBaseReg,
10819 SDLoc(), PtrVT), InFlag);
10820 InFlag = Chain.getValue(1);
10822 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
10825 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
10827 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10829 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
10830 X86::RAX, X86II::MO_TLSGD);
10833 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
10839 // Get the start address of the TLS block for this module.
10840 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
10841 .getInfo<X86MachineFunctionInfo>();
10842 MFI->incNumLocalDynamicTLSAccesses();
10846 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
10847 X86II::MO_TLSLD, /*LocalDynamic=*/true);
10850 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10851 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
10852 InFlag = Chain.getValue(1);
10853 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
10854 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
10857 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
10861 unsigned char OperandFlags = X86II::MO_DTPOFF;
10862 unsigned WrapperKind = X86ISD::Wrapper;
10863 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10864 GA->getValueType(0),
10865 GA->getOffset(), OperandFlags);
10866 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10868 // Add x@dtpoff with the base.
10869 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
10872 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
10873 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10874 const EVT PtrVT, TLSModel::Model model,
10875 bool is64Bit, bool isPIC) {
10878 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
10879 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
10880 is64Bit ? 257 : 256));
10882 SDValue ThreadPointer =
10883 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
10884 MachinePointerInfo(Ptr), false, false, false, 0);
10886 unsigned char OperandFlags = 0;
10887 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
10889 unsigned WrapperKind = X86ISD::Wrapper;
10890 if (model == TLSModel::LocalExec) {
10891 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
10892 } else if (model == TLSModel::InitialExec) {
10894 OperandFlags = X86II::MO_GOTTPOFF;
10895 WrapperKind = X86ISD::WrapperRIP;
10897 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
10900 llvm_unreachable("Unexpected model");
10903 // emit "addl x@ntpoff,%eax" (local exec)
10904 // or "addl x@indntpoff,%eax" (initial exec)
10905 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
10907 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
10908 GA->getOffset(), OperandFlags);
10909 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10911 if (model == TLSModel::InitialExec) {
10912 if (isPIC && !is64Bit) {
10913 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
10914 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
10918 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
10919 MachinePointerInfo::getGOT(), false, false, false, 0);
10922 // The address of the thread local variable is the add of the thread
10923 // pointer with the offset of the variable.
10924 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
10928 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
10930 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
10931 const GlobalValue *GV = GA->getGlobal();
10933 if (Subtarget->isTargetELF()) {
10934 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
10937 case TLSModel::GeneralDynamic:
10938 if (Subtarget->is64Bit())
10939 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
10940 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
10941 case TLSModel::LocalDynamic:
10942 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
10943 Subtarget->is64Bit());
10944 case TLSModel::InitialExec:
10945 case TLSModel::LocalExec:
10946 return LowerToTLSExecModel(
10947 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
10948 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
10950 llvm_unreachable("Unknown TLS model.");
10953 if (Subtarget->isTargetDarwin()) {
10954 // Darwin only has one model of TLS. Lower to that.
10955 unsigned char OpFlag = 0;
10956 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
10957 X86ISD::WrapperRIP : X86ISD::Wrapper;
10959 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10960 // global base reg.
10961 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
10962 !Subtarget->is64Bit();
10964 OpFlag = X86II::MO_TLVP_PIC_BASE;
10966 OpFlag = X86II::MO_TLVP;
10968 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
10969 GA->getValueType(0),
10970 GA->getOffset(), OpFlag);
10971 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10973 // With PIC32, the address is actually $g + Offset.
10975 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10976 DAG.getNode(X86ISD::GlobalBaseReg,
10977 SDLoc(), getPointerTy()),
10980 // Lowering the machine isd will make sure everything is in the right
10982 SDValue Chain = DAG.getEntryNode();
10983 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10984 SDValue Args[] = { Chain, Offset };
10985 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
10987 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
10988 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10989 MFI->setAdjustsStack(true);
10991 // And our return value (tls address) is in the standard call return value
10993 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
10994 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
10995 Chain.getValue(1));
10998 if (Subtarget->isTargetKnownWindowsMSVC() ||
10999 Subtarget->isTargetWindowsGNU()) {
11000 // Just use the implicit TLS architecture
11001 // Need to generate someting similar to:
11002 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11004 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11005 // mov rcx, qword [rdx+rcx*8]
11006 // mov eax, .tls$:tlsvar
11007 // [rax+rcx] contains the address
11008 // Windows 64bit: gs:0x58
11009 // Windows 32bit: fs:__tls_array
11012 SDValue Chain = DAG.getEntryNode();
11014 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11015 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11016 // use its literal value of 0x2C.
11017 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11018 ? Type::getInt8PtrTy(*DAG.getContext(),
11020 : Type::getInt32PtrTy(*DAG.getContext(),
11024 Subtarget->is64Bit()
11025 ? DAG.getIntPtrConstant(0x58)
11026 : (Subtarget->isTargetWindowsGNU()
11027 ? DAG.getIntPtrConstant(0x2C)
11028 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11030 SDValue ThreadPointer =
11031 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11032 MachinePointerInfo(Ptr), false, false, false, 0);
11034 // Load the _tls_index variable
11035 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11036 if (Subtarget->is64Bit())
11037 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
11038 IDX, MachinePointerInfo(), MVT::i32,
11039 false, false, false, 0);
11041 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11042 false, false, false, 0);
11044 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
11046 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11048 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11049 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11050 false, false, false, 0);
11052 // Get the offset of start of .tls section
11053 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11054 GA->getValueType(0),
11055 GA->getOffset(), X86II::MO_SECREL);
11056 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11058 // The address of the thread local variable is the add of the thread
11059 // pointer with the offset of the variable.
11060 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11063 llvm_unreachable("TLS not implemented for this target.");
11066 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11067 /// and take a 2 x i32 value to shift plus a shift amount.
11068 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11069 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11070 MVT VT = Op.getSimpleValueType();
11071 unsigned VTBits = VT.getSizeInBits();
11073 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11074 SDValue ShOpLo = Op.getOperand(0);
11075 SDValue ShOpHi = Op.getOperand(1);
11076 SDValue ShAmt = Op.getOperand(2);
11077 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11078 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11080 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11081 DAG.getConstant(VTBits - 1, MVT::i8));
11082 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11083 DAG.getConstant(VTBits - 1, MVT::i8))
11084 : DAG.getConstant(0, VT);
11086 SDValue Tmp2, Tmp3;
11087 if (Op.getOpcode() == ISD::SHL_PARTS) {
11088 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11089 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11091 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11092 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11095 // If the shift amount is larger or equal than the width of a part we can't
11096 // rely on the results of shld/shrd. Insert a test and select the appropriate
11097 // values for large shift amounts.
11098 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11099 DAG.getConstant(VTBits, MVT::i8));
11100 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11101 AndNode, DAG.getConstant(0, MVT::i8));
11104 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11105 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11106 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11108 if (Op.getOpcode() == ISD::SHL_PARTS) {
11109 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11110 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11112 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11113 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11116 SDValue Ops[2] = { Lo, Hi };
11117 return DAG.getMergeValues(Ops, dl);
11120 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11121 SelectionDAG &DAG) const {
11122 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11125 if (SrcVT.isVector()) {
11126 if (SrcVT.getVectorElementType() == MVT::i1) {
11127 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11128 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11129 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
11130 Op.getOperand(0)));
11135 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11136 "Unknown SINT_TO_FP to lower!");
11138 // These are really Legal; return the operand so the caller accepts it as
11140 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11142 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11143 Subtarget->is64Bit()) {
11147 unsigned Size = SrcVT.getSizeInBits()/8;
11148 MachineFunction &MF = DAG.getMachineFunction();
11149 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11150 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11151 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11153 MachinePointerInfo::getFixedStack(SSFI),
11155 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11158 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11160 SelectionDAG &DAG) const {
11164 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11166 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11168 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11170 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11172 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11173 MachineMemOperand *MMO;
11175 int SSFI = FI->getIndex();
11177 DAG.getMachineFunction()
11178 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11179 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11181 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11182 StackSlot = StackSlot.getOperand(1);
11184 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11185 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11187 Tys, Ops, SrcVT, MMO);
11190 Chain = Result.getValue(1);
11191 SDValue InFlag = Result.getValue(2);
11193 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11194 // shouldn't be necessary except that RFP cannot be live across
11195 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11196 MachineFunction &MF = DAG.getMachineFunction();
11197 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11198 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11199 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11200 Tys = DAG.getVTList(MVT::Other);
11202 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11204 MachineMemOperand *MMO =
11205 DAG.getMachineFunction()
11206 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11207 MachineMemOperand::MOStore, SSFISize, SSFISize);
11209 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11210 Ops, Op.getValueType(), MMO);
11211 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11212 MachinePointerInfo::getFixedStack(SSFI),
11213 false, false, false, 0);
11219 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11220 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11221 SelectionDAG &DAG) const {
11222 // This algorithm is not obvious. Here it is what we're trying to output:
11225 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11226 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11228 haddpd %xmm0, %xmm0
11230 pshufd $0x4e, %xmm0, %xmm1
11236 LLVMContext *Context = DAG.getContext();
11238 // Build some magic constants.
11239 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11240 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11241 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11243 SmallVector<Constant*,2> CV1;
11245 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11246 APInt(64, 0x4330000000000000ULL))));
11248 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11249 APInt(64, 0x4530000000000000ULL))));
11250 Constant *C1 = ConstantVector::get(CV1);
11251 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11253 // Load the 64-bit value into an XMM register.
11254 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11256 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11257 MachinePointerInfo::getConstantPool(),
11258 false, false, false, 16);
11259 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11260 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11263 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11264 MachinePointerInfo::getConstantPool(),
11265 false, false, false, 16);
11266 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11267 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11270 if (Subtarget->hasSSE3()) {
11271 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11272 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11274 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11275 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11277 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11278 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11282 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11283 DAG.getIntPtrConstant(0));
11286 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11287 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11288 SelectionDAG &DAG) const {
11290 // FP constant to bias correct the final result.
11291 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
11294 // Load the 32-bit value into an XMM register.
11295 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11298 // Zero out the upper parts of the register.
11299 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11301 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11302 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11303 DAG.getIntPtrConstant(0));
11305 // Or the load with the bias.
11306 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11307 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11308 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11309 MVT::v2f64, Load)),
11310 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11311 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11312 MVT::v2f64, Bias)));
11313 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11314 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11315 DAG.getIntPtrConstant(0));
11317 // Subtract the bias.
11318 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11320 // Handle final rounding.
11321 EVT DestVT = Op.getValueType();
11323 if (DestVT.bitsLT(MVT::f64))
11324 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11325 DAG.getIntPtrConstant(0));
11326 if (DestVT.bitsGT(MVT::f64))
11327 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11329 // Handle final rounding.
11333 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11334 const X86Subtarget &Subtarget) {
11335 // The algorithm is the following:
11336 // #ifdef __SSE4_1__
11337 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11338 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11339 // (uint4) 0x53000000, 0xaa);
11341 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11342 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11344 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11345 // return (float4) lo + fhi;
11348 SDValue V = Op->getOperand(0);
11349 EVT VecIntVT = V.getValueType();
11350 bool Is128 = VecIntVT == MVT::v4i32;
11351 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
11352 // If we convert to something else than the supported type, e.g., to v4f64,
11354 if (VecFloatVT != Op->getValueType(0))
11357 unsigned NumElts = VecIntVT.getVectorNumElements();
11358 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
11359 "Unsupported custom type");
11360 assert(NumElts <= 8 && "The size of the constant array must be fixed");
11362 // In the #idef/#else code, we have in common:
11363 // - The vector of constants:
11369 // Create the splat vector for 0x4b000000.
11370 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
11371 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
11372 CstLow, CstLow, CstLow, CstLow};
11373 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11374 makeArrayRef(&CstLowArray[0], NumElts));
11375 // Create the splat vector for 0x53000000.
11376 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
11377 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
11378 CstHigh, CstHigh, CstHigh, CstHigh};
11379 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11380 makeArrayRef(&CstHighArray[0], NumElts));
11382 // Create the right shift.
11383 SDValue CstShift = DAG.getConstant(16, MVT::i32);
11384 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
11385 CstShift, CstShift, CstShift, CstShift};
11386 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11387 makeArrayRef(&CstShiftArray[0], NumElts));
11388 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
11391 if (Subtarget.hasSSE41()) {
11392 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
11393 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11394 SDValue VecCstLowBitcast =
11395 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
11396 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
11397 // Low will be bitcasted right away, so do not bother bitcasting back to its
11399 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
11400 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
11401 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11402 // (uint4) 0x53000000, 0xaa);
11403 SDValue VecCstHighBitcast =
11404 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
11405 SDValue VecShiftBitcast =
11406 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
11407 // High will be bitcasted right away, so do not bother bitcasting back to
11408 // its original type.
11409 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
11410 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
11412 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
11413 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
11414 CstMask, CstMask, CstMask);
11415 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11416 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
11417 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
11419 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11420 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
11423 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
11424 SDValue CstFAdd = DAG.getConstantFP(
11425 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
11426 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
11427 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
11428 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
11429 makeArrayRef(&CstFAddArray[0], NumElts));
11431 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11432 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
11434 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
11435 // return (float4) lo + fhi;
11436 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
11437 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
11440 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11441 SelectionDAG &DAG) const {
11442 SDValue N0 = Op.getOperand(0);
11443 MVT SVT = N0.getSimpleValueType();
11446 switch (SVT.SimpleTy) {
11448 llvm_unreachable("Custom UINT_TO_FP is not supported!");
11453 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11454 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11455 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11459 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
11461 llvm_unreachable(nullptr);
11464 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11465 SelectionDAG &DAG) const {
11466 SDValue N0 = Op.getOperand(0);
11469 if (Op.getValueType().isVector())
11470 return lowerUINT_TO_FP_vec(Op, DAG);
11472 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11473 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11474 // the optimization here.
11475 if (DAG.SignBitIsZero(N0))
11476 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11478 MVT SrcVT = N0.getSimpleValueType();
11479 MVT DstVT = Op.getSimpleValueType();
11480 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11481 return LowerUINT_TO_FP_i64(Op, DAG);
11482 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11483 return LowerUINT_TO_FP_i32(Op, DAG);
11484 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11487 // Make a 64-bit buffer, and use it to build an FILD.
11488 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11489 if (SrcVT == MVT::i32) {
11490 SDValue WordOff = DAG.getConstant(4, getPointerTy());
11491 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11492 getPointerTy(), StackSlot, WordOff);
11493 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11494 StackSlot, MachinePointerInfo(),
11496 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
11497 OffsetSlot, MachinePointerInfo(),
11499 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11503 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11504 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11505 StackSlot, MachinePointerInfo(),
11507 // For i64 source, we need to add the appropriate power of 2 if the input
11508 // was negative. This is the same as the optimization in
11509 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11510 // we must be careful to do the computation in x87 extended precision, not
11511 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11512 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11513 MachineMemOperand *MMO =
11514 DAG.getMachineFunction()
11515 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11516 MachineMemOperand::MOLoad, 8, 8);
11518 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11519 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11520 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11523 APInt FF(32, 0x5F800000ULL);
11525 // Check whether the sign bit is set.
11526 SDValue SignSet = DAG.getSetCC(dl,
11527 getSetCCResultType(*DAG.getContext(), MVT::i64),
11528 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
11531 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11532 SDValue FudgePtr = DAG.getConstantPool(
11533 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11536 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11537 SDValue Zero = DAG.getIntPtrConstant(0);
11538 SDValue Four = DAG.getIntPtrConstant(4);
11539 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11541 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11543 // Load the value out, extending it from f32 to f80.
11544 // FIXME: Avoid the extend by constructing the right constant pool?
11545 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11546 FudgePtr, MachinePointerInfo::getConstantPool(),
11547 MVT::f32, false, false, false, 4);
11548 // Extend everything to 80 bits to force it to be done on x87.
11549 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11550 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
11553 std::pair<SDValue,SDValue>
11554 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11555 bool IsSigned, bool IsReplace) const {
11558 EVT DstTy = Op.getValueType();
11560 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11561 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11565 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11566 DstTy.getSimpleVT() >= MVT::i16 &&
11567 "Unknown FP_TO_INT to lower!");
11569 // These are really Legal.
11570 if (DstTy == MVT::i32 &&
11571 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11572 return std::make_pair(SDValue(), SDValue());
11573 if (Subtarget->is64Bit() &&
11574 DstTy == MVT::i64 &&
11575 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11576 return std::make_pair(SDValue(), SDValue());
11578 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11579 // stack slot, or into the FTOL runtime function.
11580 MachineFunction &MF = DAG.getMachineFunction();
11581 unsigned MemSize = DstTy.getSizeInBits()/8;
11582 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11583 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11586 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11587 Opc = X86ISD::WIN_FTOL;
11589 switch (DstTy.getSimpleVT().SimpleTy) {
11590 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11591 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11592 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11593 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11596 SDValue Chain = DAG.getEntryNode();
11597 SDValue Value = Op.getOperand(0);
11598 EVT TheVT = Op.getOperand(0).getValueType();
11599 // FIXME This causes a redundant load/store if the SSE-class value is already
11600 // in memory, such as if it is on the callstack.
11601 if (isScalarFPTypeInSSEReg(TheVT)) {
11602 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11603 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11604 MachinePointerInfo::getFixedStack(SSFI),
11606 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11608 Chain, StackSlot, DAG.getValueType(TheVT)
11611 MachineMemOperand *MMO =
11612 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11613 MachineMemOperand::MOLoad, MemSize, MemSize);
11614 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11615 Chain = Value.getValue(1);
11616 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11617 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11620 MachineMemOperand *MMO =
11621 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11622 MachineMemOperand::MOStore, MemSize, MemSize);
11624 if (Opc != X86ISD::WIN_FTOL) {
11625 // Build the FP_TO_INT*_IN_MEM
11626 SDValue Ops[] = { Chain, Value, StackSlot };
11627 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11629 return std::make_pair(FIST, StackSlot);
11631 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11632 DAG.getVTList(MVT::Other, MVT::Glue),
11634 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11635 MVT::i32, ftol.getValue(1));
11636 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11637 MVT::i32, eax.getValue(2));
11638 SDValue Ops[] = { eax, edx };
11639 SDValue pair = IsReplace
11640 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11641 : DAG.getMergeValues(Ops, DL);
11642 return std::make_pair(pair, SDValue());
11646 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11647 const X86Subtarget *Subtarget) {
11648 MVT VT = Op->getSimpleValueType(0);
11649 SDValue In = Op->getOperand(0);
11650 MVT InVT = In.getSimpleValueType();
11653 // Optimize vectors in AVX mode:
11656 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11657 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11658 // Concat upper and lower parts.
11661 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11662 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11663 // Concat upper and lower parts.
11666 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11667 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11668 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11671 if (Subtarget->hasInt256())
11672 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11674 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11675 SDValue Undef = DAG.getUNDEF(InVT);
11676 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11677 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11678 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11680 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11681 VT.getVectorNumElements()/2);
11683 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11684 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
11686 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11689 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
11690 SelectionDAG &DAG) {
11691 MVT VT = Op->getSimpleValueType(0);
11692 SDValue In = Op->getOperand(0);
11693 MVT InVT = In.getSimpleValueType();
11695 unsigned int NumElts = VT.getVectorNumElements();
11696 if (NumElts != 8 && NumElts != 16)
11699 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11700 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
11702 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11703 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11704 // Now we have only mask extension
11705 assert(InVT.getVectorElementType() == MVT::i1);
11706 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
11707 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11708 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11709 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11710 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11711 MachinePointerInfo::getConstantPool(),
11712 false, false, false, Alignment);
11714 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
11715 if (VT.is512BitVector())
11717 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
11720 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11721 SelectionDAG &DAG) {
11722 if (Subtarget->hasFp256()) {
11723 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11731 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11732 SelectionDAG &DAG) {
11734 MVT VT = Op.getSimpleValueType();
11735 SDValue In = Op.getOperand(0);
11736 MVT SVT = In.getSimpleValueType();
11738 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
11739 return LowerZERO_EXTEND_AVX512(Op, DAG);
11741 if (Subtarget->hasFp256()) {
11742 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11747 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
11748 VT.getVectorNumElements() != SVT.getVectorNumElements());
11752 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
11754 MVT VT = Op.getSimpleValueType();
11755 SDValue In = Op.getOperand(0);
11756 MVT InVT = In.getSimpleValueType();
11758 if (VT == MVT::i1) {
11759 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
11760 "Invalid scalar TRUNCATE operation");
11761 if (InVT.getSizeInBits() >= 32)
11763 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
11764 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
11766 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
11767 "Invalid TRUNCATE operation");
11769 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
11770 if (VT.getVectorElementType().getSizeInBits() >=8)
11771 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
11773 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
11774 unsigned NumElts = InVT.getVectorNumElements();
11775 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
11776 if (InVT.getSizeInBits() < 512) {
11777 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
11778 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
11782 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
11783 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11784 SDValue CP = DAG.getConstantPool(C, getPointerTy());
11785 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11786 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11787 MachinePointerInfo::getConstantPool(),
11788 false, false, false, Alignment);
11789 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
11790 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
11791 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
11794 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
11795 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
11796 if (Subtarget->hasInt256()) {
11797 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
11798 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
11799 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
11801 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
11802 DAG.getIntPtrConstant(0));
11805 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11806 DAG.getIntPtrConstant(0));
11807 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11808 DAG.getIntPtrConstant(2));
11809 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11810 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11811 static const int ShufMask[] = {0, 2, 4, 6};
11812 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
11815 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
11816 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
11817 if (Subtarget->hasInt256()) {
11818 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
11820 SmallVector<SDValue,32> pshufbMask;
11821 for (unsigned i = 0; i < 2; ++i) {
11822 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
11823 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
11824 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
11825 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
11826 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
11827 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
11828 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
11829 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
11830 for (unsigned j = 0; j < 8; ++j)
11831 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
11833 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
11834 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
11835 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
11837 static const int ShufMask[] = {0, 2, -1, -1};
11838 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
11840 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11841 DAG.getIntPtrConstant(0));
11842 return DAG.getNode(ISD::BITCAST, DL, VT, In);
11845 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11846 DAG.getIntPtrConstant(0));
11848 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11849 DAG.getIntPtrConstant(4));
11851 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
11852 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
11854 // The PSHUFB mask:
11855 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
11856 -1, -1, -1, -1, -1, -1, -1, -1};
11858 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
11859 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
11860 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
11862 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11863 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11865 // The MOVLHPS Mask:
11866 static const int ShufMask2[] = {0, 1, 4, 5};
11867 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
11868 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
11871 // Handle truncation of V256 to V128 using shuffles.
11872 if (!VT.is128BitVector() || !InVT.is256BitVector())
11875 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
11877 unsigned NumElems = VT.getVectorNumElements();
11878 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
11880 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
11881 // Prepare truncation shuffle mask
11882 for (unsigned i = 0; i != NumElems; ++i)
11883 MaskVec[i] = i * 2;
11884 SDValue V = DAG.getVectorShuffle(NVT, DL,
11885 DAG.getNode(ISD::BITCAST, DL, NVT, In),
11886 DAG.getUNDEF(NVT), &MaskVec[0]);
11887 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
11888 DAG.getIntPtrConstant(0));
11891 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
11892 SelectionDAG &DAG) const {
11893 assert(!Op.getSimpleValueType().isVector());
11895 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11896 /*IsSigned=*/ true, /*IsReplace=*/ false);
11897 SDValue FIST = Vals.first, StackSlot = Vals.second;
11898 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
11899 if (!FIST.getNode()) return Op;
11901 if (StackSlot.getNode())
11902 // Load the result.
11903 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11904 FIST, StackSlot, MachinePointerInfo(),
11905 false, false, false, 0);
11907 // The node is the result.
11911 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
11912 SelectionDAG &DAG) const {
11913 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11914 /*IsSigned=*/ false, /*IsReplace=*/ false);
11915 SDValue FIST = Vals.first, StackSlot = Vals.second;
11916 assert(FIST.getNode() && "Unexpected failure");
11918 if (StackSlot.getNode())
11919 // Load the result.
11920 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11921 FIST, StackSlot, MachinePointerInfo(),
11922 false, false, false, 0);
11924 // The node is the result.
11928 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
11930 MVT VT = Op.getSimpleValueType();
11931 SDValue In = Op.getOperand(0);
11932 MVT SVT = In.getSimpleValueType();
11934 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
11936 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
11937 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
11938 In, DAG.getUNDEF(SVT)));
11941 /// The only differences between FABS and FNEG are the mask and the logic op.
11942 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
11943 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
11944 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
11945 "Wrong opcode for lowering FABS or FNEG.");
11947 bool IsFABS = (Op.getOpcode() == ISD::FABS);
11949 // If this is a FABS and it has an FNEG user, bail out to fold the combination
11950 // into an FNABS. We'll lower the FABS after that if it is still in use.
11952 for (SDNode *User : Op->uses())
11953 if (User->getOpcode() == ISD::FNEG)
11956 SDValue Op0 = Op.getOperand(0);
11957 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
11960 MVT VT = Op.getSimpleValueType();
11961 // Assume scalar op for initialization; update for vector if needed.
11962 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
11963 // generate a 16-byte vector constant and logic op even for the scalar case.
11964 // Using a 16-byte mask allows folding the load of the mask with
11965 // the logic op, so it can save (~4 bytes) on code size.
11967 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11968 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
11969 // decide if we should generate a 16-byte constant mask when we only need 4 or
11970 // 8 bytes for the scalar case.
11971 if (VT.isVector()) {
11972 EltVT = VT.getVectorElementType();
11973 NumElts = VT.getVectorNumElements();
11976 unsigned EltBits = EltVT.getSizeInBits();
11977 LLVMContext *Context = DAG.getContext();
11978 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
11980 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
11981 Constant *C = ConstantInt::get(*Context, MaskElt);
11982 C = ConstantVector::getSplat(NumElts, C);
11983 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11984 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11985 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11986 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11987 MachinePointerInfo::getConstantPool(),
11988 false, false, false, Alignment);
11990 if (VT.isVector()) {
11991 // For a vector, cast operands to a vector type, perform the logic op,
11992 // and cast the result back to the original value type.
11993 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
11994 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
11995 SDValue Operand = IsFNABS ?
11996 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
11997 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
11998 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
11999 return DAG.getNode(ISD::BITCAST, dl, VT,
12000 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12003 // If not vector, then scalar.
12004 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12005 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12006 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12009 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12010 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12011 LLVMContext *Context = DAG.getContext();
12012 SDValue Op0 = Op.getOperand(0);
12013 SDValue Op1 = Op.getOperand(1);
12015 MVT VT = Op.getSimpleValueType();
12016 MVT SrcVT = Op1.getSimpleValueType();
12018 // If second operand is smaller, extend it first.
12019 if (SrcVT.bitsLT(VT)) {
12020 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12023 // And if it is bigger, shrink it first.
12024 if (SrcVT.bitsGT(VT)) {
12025 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
12029 // At this point the operands and the result should have the same
12030 // type, and that won't be f80 since that is not custom lowered.
12032 const fltSemantics &Sem =
12033 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12034 const unsigned SizeInBits = VT.getSizeInBits();
12036 SmallVector<Constant *, 4> CV(
12037 VT == MVT::f64 ? 2 : 4,
12038 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12040 // First, clear all bits but the sign bit from the second operand (sign).
12041 CV[0] = ConstantFP::get(*Context,
12042 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12043 Constant *C = ConstantVector::get(CV);
12044 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12045 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12046 MachinePointerInfo::getConstantPool(),
12047 false, false, false, 16);
12048 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12050 // Next, clear the sign bit from the first operand (magnitude).
12051 // If it's a constant, we can clear it here.
12052 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12053 APFloat APF = Op0CN->getValueAPF();
12054 // If the magnitude is a positive zero, the sign bit alone is enough.
12055 if (APF.isPosZero())
12058 CV[0] = ConstantFP::get(*Context, APF);
12060 CV[0] = ConstantFP::get(
12062 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12064 C = ConstantVector::get(CV);
12065 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12066 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12067 MachinePointerInfo::getConstantPool(),
12068 false, false, false, 16);
12069 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12070 if (!isa<ConstantFPSDNode>(Op0))
12071 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12073 // OR the magnitude value with the sign bit.
12074 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12077 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12078 SDValue N0 = Op.getOperand(0);
12080 MVT VT = Op.getSimpleValueType();
12082 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12083 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12084 DAG.getConstant(1, VT));
12085 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
12088 // Check whether an OR'd tree is PTEST-able.
12089 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12090 SelectionDAG &DAG) {
12091 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12093 if (!Subtarget->hasSSE41())
12096 if (!Op->hasOneUse())
12099 SDNode *N = Op.getNode();
12102 SmallVector<SDValue, 8> Opnds;
12103 DenseMap<SDValue, unsigned> VecInMap;
12104 SmallVector<SDValue, 8> VecIns;
12105 EVT VT = MVT::Other;
12107 // Recognize a special case where a vector is casted into wide integer to
12109 Opnds.push_back(N->getOperand(0));
12110 Opnds.push_back(N->getOperand(1));
12112 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12113 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12114 // BFS traverse all OR'd operands.
12115 if (I->getOpcode() == ISD::OR) {
12116 Opnds.push_back(I->getOperand(0));
12117 Opnds.push_back(I->getOperand(1));
12118 // Re-evaluate the number of nodes to be traversed.
12119 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12123 // Quit if a non-EXTRACT_VECTOR_ELT
12124 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12127 // Quit if without a constant index.
12128 SDValue Idx = I->getOperand(1);
12129 if (!isa<ConstantSDNode>(Idx))
12132 SDValue ExtractedFromVec = I->getOperand(0);
12133 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12134 if (M == VecInMap.end()) {
12135 VT = ExtractedFromVec.getValueType();
12136 // Quit if not 128/256-bit vector.
12137 if (!VT.is128BitVector() && !VT.is256BitVector())
12139 // Quit if not the same type.
12140 if (VecInMap.begin() != VecInMap.end() &&
12141 VT != VecInMap.begin()->first.getValueType())
12143 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12144 VecIns.push_back(ExtractedFromVec);
12146 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12149 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12150 "Not extracted from 128-/256-bit vector.");
12152 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12154 for (DenseMap<SDValue, unsigned>::const_iterator
12155 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12156 // Quit if not all elements are used.
12157 if (I->second != FullMask)
12161 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12163 // Cast all vectors into TestVT for PTEST.
12164 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12165 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12167 // If more than one full vectors are evaluated, OR them first before PTEST.
12168 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12169 // Each iteration will OR 2 nodes and append the result until there is only
12170 // 1 node left, i.e. the final OR'd value of all vectors.
12171 SDValue LHS = VecIns[Slot];
12172 SDValue RHS = VecIns[Slot + 1];
12173 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12176 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12177 VecIns.back(), VecIns.back());
12180 /// \brief return true if \c Op has a use that doesn't just read flags.
12181 static bool hasNonFlagsUse(SDValue Op) {
12182 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12184 SDNode *User = *UI;
12185 unsigned UOpNo = UI.getOperandNo();
12186 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12187 // Look pass truncate.
12188 UOpNo = User->use_begin().getOperandNo();
12189 User = *User->use_begin();
12192 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12193 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12199 /// Emit nodes that will be selected as "test Op0,Op0", or something
12201 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12202 SelectionDAG &DAG) const {
12203 if (Op.getValueType() == MVT::i1) {
12204 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12205 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12206 DAG.getConstant(0, MVT::i8));
12208 // CF and OF aren't always set the way we want. Determine which
12209 // of these we need.
12210 bool NeedCF = false;
12211 bool NeedOF = false;
12214 case X86::COND_A: case X86::COND_AE:
12215 case X86::COND_B: case X86::COND_BE:
12218 case X86::COND_G: case X86::COND_GE:
12219 case X86::COND_L: case X86::COND_LE:
12220 case X86::COND_O: case X86::COND_NO: {
12221 // Check if we really need to set the
12222 // Overflow flag. If NoSignedWrap is present
12223 // that is not actually needed.
12224 switch (Op->getOpcode()) {
12229 const BinaryWithFlagsSDNode *BinNode =
12230 cast<BinaryWithFlagsSDNode>(Op.getNode());
12231 if (BinNode->hasNoSignedWrap())
12241 // See if we can use the EFLAGS value from the operand instead of
12242 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12243 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12244 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12245 // Emit a CMP with 0, which is the TEST pattern.
12246 //if (Op.getValueType() == MVT::i1)
12247 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12248 // DAG.getConstant(0, MVT::i1));
12249 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12250 DAG.getConstant(0, Op.getValueType()));
12252 unsigned Opcode = 0;
12253 unsigned NumOperands = 0;
12255 // Truncate operations may prevent the merge of the SETCC instruction
12256 // and the arithmetic instruction before it. Attempt to truncate the operands
12257 // of the arithmetic instruction and use a reduced bit-width instruction.
12258 bool NeedTruncation = false;
12259 SDValue ArithOp = Op;
12260 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12261 SDValue Arith = Op->getOperand(0);
12262 // Both the trunc and the arithmetic op need to have one user each.
12263 if (Arith->hasOneUse())
12264 switch (Arith.getOpcode()) {
12271 NeedTruncation = true;
12277 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12278 // which may be the result of a CAST. We use the variable 'Op', which is the
12279 // non-casted variable when we check for possible users.
12280 switch (ArithOp.getOpcode()) {
12282 // Due to an isel shortcoming, be conservative if this add is likely to be
12283 // selected as part of a load-modify-store instruction. When the root node
12284 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12285 // uses of other nodes in the match, such as the ADD in this case. This
12286 // leads to the ADD being left around and reselected, with the result being
12287 // two adds in the output. Alas, even if none our users are stores, that
12288 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12289 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12290 // climbing the DAG back to the root, and it doesn't seem to be worth the
12292 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12293 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12294 if (UI->getOpcode() != ISD::CopyToReg &&
12295 UI->getOpcode() != ISD::SETCC &&
12296 UI->getOpcode() != ISD::STORE)
12299 if (ConstantSDNode *C =
12300 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12301 // An add of one will be selected as an INC.
12302 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12303 Opcode = X86ISD::INC;
12308 // An add of negative one (subtract of one) will be selected as a DEC.
12309 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12310 Opcode = X86ISD::DEC;
12316 // Otherwise use a regular EFLAGS-setting add.
12317 Opcode = X86ISD::ADD;
12322 // If we have a constant logical shift that's only used in a comparison
12323 // against zero turn it into an equivalent AND. This allows turning it into
12324 // a TEST instruction later.
12325 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12326 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12327 EVT VT = Op.getValueType();
12328 unsigned BitWidth = VT.getSizeInBits();
12329 unsigned ShAmt = Op->getConstantOperandVal(1);
12330 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12332 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12333 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12334 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12335 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12337 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12338 DAG.getConstant(Mask, VT));
12339 DAG.ReplaceAllUsesWith(Op, New);
12345 // If the primary and result isn't used, don't bother using X86ISD::AND,
12346 // because a TEST instruction will be better.
12347 if (!hasNonFlagsUse(Op))
12353 // Due to the ISEL shortcoming noted above, be conservative if this op is
12354 // likely to be selected as part of a load-modify-store instruction.
12355 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12356 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12357 if (UI->getOpcode() == ISD::STORE)
12360 // Otherwise use a regular EFLAGS-setting instruction.
12361 switch (ArithOp.getOpcode()) {
12362 default: llvm_unreachable("unexpected operator!");
12363 case ISD::SUB: Opcode = X86ISD::SUB; break;
12364 case ISD::XOR: Opcode = X86ISD::XOR; break;
12365 case ISD::AND: Opcode = X86ISD::AND; break;
12367 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12368 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12369 if (EFLAGS.getNode())
12372 Opcode = X86ISD::OR;
12386 return SDValue(Op.getNode(), 1);
12392 // If we found that truncation is beneficial, perform the truncation and
12394 if (NeedTruncation) {
12395 EVT VT = Op.getValueType();
12396 SDValue WideVal = Op->getOperand(0);
12397 EVT WideVT = WideVal.getValueType();
12398 unsigned ConvertedOp = 0;
12399 // Use a target machine opcode to prevent further DAGCombine
12400 // optimizations that may separate the arithmetic operations
12401 // from the setcc node.
12402 switch (WideVal.getOpcode()) {
12404 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12405 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12406 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12407 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12408 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12412 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12413 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12414 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12415 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12416 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12422 // Emit a CMP with 0, which is the TEST pattern.
12423 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12424 DAG.getConstant(0, Op.getValueType()));
12426 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12427 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
12429 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12430 DAG.ReplaceAllUsesWith(Op, New);
12431 return SDValue(New.getNode(), 1);
12434 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12436 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12437 SDLoc dl, SelectionDAG &DAG) const {
12438 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12439 if (C->getAPIntValue() == 0)
12440 return EmitTest(Op0, X86CC, dl, DAG);
12442 if (Op0.getValueType() == MVT::i1)
12443 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12446 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12447 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12448 // Do the comparison at i32 if it's smaller, besides the Atom case.
12449 // This avoids subregister aliasing issues. Keep the smaller reference
12450 // if we're optimizing for size, however, as that'll allow better folding
12451 // of memory operations.
12452 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12453 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
12454 Attribute::MinSize) &&
12455 !Subtarget->isAtom()) {
12456 unsigned ExtendOp =
12457 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12458 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12459 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12461 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12462 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12463 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12465 return SDValue(Sub.getNode(), 1);
12467 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12470 /// Convert a comparison if required by the subtarget.
12471 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12472 SelectionDAG &DAG) const {
12473 // If the subtarget does not support the FUCOMI instruction, floating-point
12474 // comparisons have to be converted.
12475 if (Subtarget->hasCMov() ||
12476 Cmp.getOpcode() != X86ISD::CMP ||
12477 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12478 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12481 // The instruction selector will select an FUCOM instruction instead of
12482 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12483 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12484 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12486 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12487 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12488 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12489 DAG.getConstant(8, MVT::i8));
12490 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12491 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12494 /// The minimum architected relative accuracy is 2^-12. We need one
12495 /// Newton-Raphson step to have a good float result (24 bits of precision).
12496 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
12497 DAGCombinerInfo &DCI,
12498 unsigned &RefinementSteps,
12499 bool &UseOneConstNR) const {
12500 // FIXME: We should use instruction latency models to calculate the cost of
12501 // each potential sequence, but this is very hard to do reliably because
12502 // at least Intel's Core* chips have variable timing based on the number of
12503 // significant digits in the divisor and/or sqrt operand.
12504 if (!Subtarget->useSqrtEst())
12507 EVT VT = Op.getValueType();
12509 // SSE1 has rsqrtss and rsqrtps.
12510 // TODO: Add support for AVX512 (v16f32).
12511 // It is likely not profitable to do this for f64 because a double-precision
12512 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
12513 // instructions: convert to single, rsqrtss, convert back to double, refine
12514 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
12515 // along with FMA, this could be a throughput win.
12516 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12517 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12518 RefinementSteps = 1;
12519 UseOneConstNR = false;
12520 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
12525 /// The minimum architected relative accuracy is 2^-12. We need one
12526 /// Newton-Raphson step to have a good float result (24 bits of precision).
12527 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
12528 DAGCombinerInfo &DCI,
12529 unsigned &RefinementSteps) const {
12530 // FIXME: We should use instruction latency models to calculate the cost of
12531 // each potential sequence, but this is very hard to do reliably because
12532 // at least Intel's Core* chips have variable timing based on the number of
12533 // significant digits in the divisor.
12534 if (!Subtarget->useReciprocalEst())
12537 EVT VT = Op.getValueType();
12539 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
12540 // TODO: Add support for AVX512 (v16f32).
12541 // It is likely not profitable to do this for f64 because a double-precision
12542 // reciprocal estimate with refinement on x86 prior to FMA requires
12543 // 15 instructions: convert to single, rcpss, convert back to double, refine
12544 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
12545 // along with FMA, this could be a throughput win.
12546 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12547 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12548 RefinementSteps = ReciprocalEstimateRefinementSteps;
12549 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
12554 static bool isAllOnes(SDValue V) {
12555 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12556 return C && C->isAllOnesValue();
12559 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12560 /// if it's possible.
12561 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12562 SDLoc dl, SelectionDAG &DAG) const {
12563 SDValue Op0 = And.getOperand(0);
12564 SDValue Op1 = And.getOperand(1);
12565 if (Op0.getOpcode() == ISD::TRUNCATE)
12566 Op0 = Op0.getOperand(0);
12567 if (Op1.getOpcode() == ISD::TRUNCATE)
12568 Op1 = Op1.getOperand(0);
12571 if (Op1.getOpcode() == ISD::SHL)
12572 std::swap(Op0, Op1);
12573 if (Op0.getOpcode() == ISD::SHL) {
12574 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
12575 if (And00C->getZExtValue() == 1) {
12576 // If we looked past a truncate, check that it's only truncating away
12578 unsigned BitWidth = Op0.getValueSizeInBits();
12579 unsigned AndBitWidth = And.getValueSizeInBits();
12580 if (BitWidth > AndBitWidth) {
12582 DAG.computeKnownBits(Op0, Zeros, Ones);
12583 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
12587 RHS = Op0.getOperand(1);
12589 } else if (Op1.getOpcode() == ISD::Constant) {
12590 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
12591 uint64_t AndRHSVal = AndRHS->getZExtValue();
12592 SDValue AndLHS = Op0;
12594 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
12595 LHS = AndLHS.getOperand(0);
12596 RHS = AndLHS.getOperand(1);
12599 // Use BT if the immediate can't be encoded in a TEST instruction.
12600 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12602 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
12606 if (LHS.getNode()) {
12607 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12608 // instruction. Since the shift amount is in-range-or-undefined, we know
12609 // that doing a bittest on the i32 value is ok. We extend to i32 because
12610 // the encoding for the i16 version is larger than the i32 version.
12611 // Also promote i16 to i32 for performance / code size reason.
12612 if (LHS.getValueType() == MVT::i8 ||
12613 LHS.getValueType() == MVT::i16)
12614 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12616 // If the operand types disagree, extend the shift amount to match. Since
12617 // BT ignores high bits (like shifts) we can use anyextend.
12618 if (LHS.getValueType() != RHS.getValueType())
12619 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12621 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12622 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
12623 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12624 DAG.getConstant(Cond, MVT::i8), BT);
12630 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
12632 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
12637 // SSE Condition code mapping:
12646 switch (SetCCOpcode) {
12647 default: llvm_unreachable("Unexpected SETCC condition");
12649 case ISD::SETEQ: SSECC = 0; break;
12651 case ISD::SETGT: Swap = true; // Fallthrough
12653 case ISD::SETOLT: SSECC = 1; break;
12655 case ISD::SETGE: Swap = true; // Fallthrough
12657 case ISD::SETOLE: SSECC = 2; break;
12658 case ISD::SETUO: SSECC = 3; break;
12660 case ISD::SETNE: SSECC = 4; break;
12661 case ISD::SETULE: Swap = true; // Fallthrough
12662 case ISD::SETUGE: SSECC = 5; break;
12663 case ISD::SETULT: Swap = true; // Fallthrough
12664 case ISD::SETUGT: SSECC = 6; break;
12665 case ISD::SETO: SSECC = 7; break;
12667 case ISD::SETONE: SSECC = 8; break;
12670 std::swap(Op0, Op1);
12675 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
12676 // ones, and then concatenate the result back.
12677 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
12678 MVT VT = Op.getSimpleValueType();
12680 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12681 "Unsupported value type for operation");
12683 unsigned NumElems = VT.getVectorNumElements();
12685 SDValue CC = Op.getOperand(2);
12687 // Extract the LHS vectors
12688 SDValue LHS = Op.getOperand(0);
12689 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12690 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12692 // Extract the RHS vectors
12693 SDValue RHS = Op.getOperand(1);
12694 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12695 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12697 // Issue the operation on the smaller types and concatenate the result back
12698 MVT EltVT = VT.getVectorElementType();
12699 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12700 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12701 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
12702 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
12705 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
12706 const X86Subtarget *Subtarget) {
12707 SDValue Op0 = Op.getOperand(0);
12708 SDValue Op1 = Op.getOperand(1);
12709 SDValue CC = Op.getOperand(2);
12710 MVT VT = Op.getSimpleValueType();
12713 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
12714 Op.getValueType().getScalarType() == MVT::i1 &&
12715 "Cannot set masked compare for this operation");
12717 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12719 bool Unsigned = false;
12722 switch (SetCCOpcode) {
12723 default: llvm_unreachable("Unexpected SETCC condition");
12724 case ISD::SETNE: SSECC = 4; break;
12725 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
12726 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
12727 case ISD::SETLT: Swap = true; //fall-through
12728 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
12729 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
12730 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
12731 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
12732 case ISD::SETULE: Unsigned = true; //fall-through
12733 case ISD::SETLE: SSECC = 2; break;
12737 std::swap(Op0, Op1);
12739 return DAG.getNode(Opc, dl, VT, Op0, Op1);
12740 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
12741 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12742 DAG.getConstant(SSECC, MVT::i8));
12745 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
12746 /// operand \p Op1. If non-trivial (for example because it's not constant)
12747 /// return an empty value.
12748 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
12750 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
12754 MVT VT = Op1.getSimpleValueType();
12755 MVT EVT = VT.getVectorElementType();
12756 unsigned n = VT.getVectorNumElements();
12757 SmallVector<SDValue, 8> ULTOp1;
12759 for (unsigned i = 0; i < n; ++i) {
12760 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
12761 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
12764 // Avoid underflow.
12765 APInt Val = Elt->getAPIntValue();
12769 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
12772 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
12775 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
12776 SelectionDAG &DAG) {
12777 SDValue Op0 = Op.getOperand(0);
12778 SDValue Op1 = Op.getOperand(1);
12779 SDValue CC = Op.getOperand(2);
12780 MVT VT = Op.getSimpleValueType();
12781 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12782 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
12787 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
12788 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
12791 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
12792 unsigned Opc = X86ISD::CMPP;
12793 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
12794 assert(VT.getVectorNumElements() <= 16);
12795 Opc = X86ISD::CMPM;
12797 // In the two special cases we can't handle, emit two comparisons.
12800 unsigned CombineOpc;
12801 if (SetCCOpcode == ISD::SETUEQ) {
12802 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
12804 assert(SetCCOpcode == ISD::SETONE);
12805 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
12808 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12809 DAG.getConstant(CC0, MVT::i8));
12810 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12811 DAG.getConstant(CC1, MVT::i8));
12812 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
12814 // Handle all other FP comparisons here.
12815 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12816 DAG.getConstant(SSECC, MVT::i8));
12819 // Break 256-bit integer vector compare into smaller ones.
12820 if (VT.is256BitVector() && !Subtarget->hasInt256())
12821 return Lower256IntVSETCC(Op, DAG);
12823 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
12824 EVT OpVT = Op1.getValueType();
12825 if (Subtarget->hasAVX512()) {
12826 if (Op1.getValueType().is512BitVector() ||
12827 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
12828 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
12829 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
12831 // In AVX-512 architecture setcc returns mask with i1 elements,
12832 // But there is no compare instruction for i8 and i16 elements in KNL.
12833 // We are not talking about 512-bit operands in this case, these
12834 // types are illegal.
12836 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
12837 OpVT.getVectorElementType().getSizeInBits() >= 8))
12838 return DAG.getNode(ISD::TRUNCATE, dl, VT,
12839 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
12842 // We are handling one of the integer comparisons here. Since SSE only has
12843 // GT and EQ comparisons for integer, swapping operands and multiple
12844 // operations may be required for some comparisons.
12846 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
12847 bool Subus = false;
12849 switch (SetCCOpcode) {
12850 default: llvm_unreachable("Unexpected SETCC condition");
12851 case ISD::SETNE: Invert = true;
12852 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
12853 case ISD::SETLT: Swap = true;
12854 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
12855 case ISD::SETGE: Swap = true;
12856 case ISD::SETLE: Opc = X86ISD::PCMPGT;
12857 Invert = true; break;
12858 case ISD::SETULT: Swap = true;
12859 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
12860 FlipSigns = true; break;
12861 case ISD::SETUGE: Swap = true;
12862 case ISD::SETULE: Opc = X86ISD::PCMPGT;
12863 FlipSigns = true; Invert = true; break;
12866 // Special case: Use min/max operations for SETULE/SETUGE
12867 MVT VET = VT.getVectorElementType();
12869 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
12870 || (Subtarget->hasSSE2() && (VET == MVT::i8));
12873 switch (SetCCOpcode) {
12875 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
12876 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
12879 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
12882 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
12883 if (!MinMax && hasSubus) {
12884 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
12886 // t = psubus Op0, Op1
12887 // pcmpeq t, <0..0>
12888 switch (SetCCOpcode) {
12890 case ISD::SETULT: {
12891 // If the comparison is against a constant we can turn this into a
12892 // setule. With psubus, setule does not require a swap. This is
12893 // beneficial because the constant in the register is no longer
12894 // destructed as the destination so it can be hoisted out of a loop.
12895 // Only do this pre-AVX since vpcmp* is no longer destructive.
12896 if (Subtarget->hasAVX())
12898 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
12899 if (ULEOp1.getNode()) {
12901 Subus = true; Invert = false; Swap = false;
12905 // Psubus is better than flip-sign because it requires no inversion.
12906 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
12907 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
12911 Opc = X86ISD::SUBUS;
12917 std::swap(Op0, Op1);
12919 // Check that the operation in question is available (most are plain SSE2,
12920 // but PCMPGTQ and PCMPEQQ have different requirements).
12921 if (VT == MVT::v2i64) {
12922 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
12923 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
12925 // First cast everything to the right type.
12926 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12927 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12929 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12930 // bits of the inputs before performing those operations. The lower
12931 // compare is always unsigned.
12934 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
12936 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
12937 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
12938 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
12939 Sign, Zero, Sign, Zero);
12941 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
12942 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
12944 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
12945 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
12946 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
12948 // Create masks for only the low parts/high parts of the 64 bit integers.
12949 static const int MaskHi[] = { 1, 1, 3, 3 };
12950 static const int MaskLo[] = { 0, 0, 2, 2 };
12951 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
12952 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
12953 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
12955 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
12956 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
12959 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12961 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12964 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
12965 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
12966 // pcmpeqd + pshufd + pand.
12967 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
12969 // First cast everything to the right type.
12970 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12971 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12974 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
12976 // Make sure the lower and upper halves are both all-ones.
12977 static const int Mask[] = { 1, 0, 3, 2 };
12978 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
12979 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
12982 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12984 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12988 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12989 // bits of the inputs before performing those operations.
12991 EVT EltVT = VT.getVectorElementType();
12992 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
12993 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
12994 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
12997 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
12999 // If the logical-not of the result is required, perform that now.
13001 Result = DAG.getNOT(dl, Result, VT);
13004 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13007 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13008 getZeroVector(VT, Subtarget, DAG, dl));
13013 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13015 MVT VT = Op.getSimpleValueType();
13017 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13019 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13020 && "SetCC type must be 8-bit or 1-bit integer");
13021 SDValue Op0 = Op.getOperand(0);
13022 SDValue Op1 = Op.getOperand(1);
13024 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13026 // Optimize to BT if possible.
13027 // Lower (X & (1 << N)) == 0 to BT(X, N).
13028 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13029 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13030 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13031 Op1.getOpcode() == ISD::Constant &&
13032 cast<ConstantSDNode>(Op1)->isNullValue() &&
13033 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13034 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13035 if (NewSetCC.getNode()) {
13037 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13042 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13044 if (Op1.getOpcode() == ISD::Constant &&
13045 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13046 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13047 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13049 // If the input is a setcc, then reuse the input setcc or use a new one with
13050 // the inverted condition.
13051 if (Op0.getOpcode() == X86ISD::SETCC) {
13052 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13053 bool Invert = (CC == ISD::SETNE) ^
13054 cast<ConstantSDNode>(Op1)->isNullValue();
13058 CCode = X86::GetOppositeBranchCondition(CCode);
13059 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13060 DAG.getConstant(CCode, MVT::i8),
13061 Op0.getOperand(1));
13063 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13067 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13068 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13069 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13071 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13072 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
13075 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13076 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
13077 if (X86CC == X86::COND_INVALID)
13080 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13081 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13082 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13083 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
13085 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13089 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13090 static bool isX86LogicalCmp(SDValue Op) {
13091 unsigned Opc = Op.getNode()->getOpcode();
13092 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13093 Opc == X86ISD::SAHF)
13095 if (Op.getResNo() == 1 &&
13096 (Opc == X86ISD::ADD ||
13097 Opc == X86ISD::SUB ||
13098 Opc == X86ISD::ADC ||
13099 Opc == X86ISD::SBB ||
13100 Opc == X86ISD::SMUL ||
13101 Opc == X86ISD::UMUL ||
13102 Opc == X86ISD::INC ||
13103 Opc == X86ISD::DEC ||
13104 Opc == X86ISD::OR ||
13105 Opc == X86ISD::XOR ||
13106 Opc == X86ISD::AND))
13109 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13115 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13116 if (V.getOpcode() != ISD::TRUNCATE)
13119 SDValue VOp0 = V.getOperand(0);
13120 unsigned InBits = VOp0.getValueSizeInBits();
13121 unsigned Bits = V.getValueSizeInBits();
13122 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13125 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13126 bool addTest = true;
13127 SDValue Cond = Op.getOperand(0);
13128 SDValue Op1 = Op.getOperand(1);
13129 SDValue Op2 = Op.getOperand(2);
13131 EVT VT = Op1.getValueType();
13134 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13135 // are available. Otherwise fp cmovs get lowered into a less efficient branch
13136 // sequence later on.
13137 if (Cond.getOpcode() == ISD::SETCC &&
13138 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13139 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13140 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13141 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13142 int SSECC = translateX86FSETCC(
13143 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13146 if (Subtarget->hasAVX512()) {
13147 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13148 DAG.getConstant(SSECC, MVT::i8));
13149 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13151 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13152 DAG.getConstant(SSECC, MVT::i8));
13153 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13154 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13155 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13159 if (Cond.getOpcode() == ISD::SETCC) {
13160 SDValue NewCond = LowerSETCC(Cond, DAG);
13161 if (NewCond.getNode())
13165 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13166 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13167 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13168 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13169 if (Cond.getOpcode() == X86ISD::SETCC &&
13170 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13171 isZero(Cond.getOperand(1).getOperand(1))) {
13172 SDValue Cmp = Cond.getOperand(1);
13174 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13176 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13177 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13178 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13180 SDValue CmpOp0 = Cmp.getOperand(0);
13181 // Apply further optimizations for special cases
13182 // (select (x != 0), -1, 0) -> neg & sbb
13183 // (select (x == 0), 0, -1) -> neg & sbb
13184 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13185 if (YC->isNullValue() &&
13186 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13187 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13188 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13189 DAG.getConstant(0, CmpOp0.getValueType()),
13191 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13192 DAG.getConstant(X86::COND_B, MVT::i8),
13193 SDValue(Neg.getNode(), 1));
13197 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13198 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
13199 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13201 SDValue Res = // Res = 0 or -1.
13202 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13203 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
13205 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13206 Res = DAG.getNOT(DL, Res, Res.getValueType());
13208 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13209 if (!N2C || !N2C->isNullValue())
13210 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13215 // Look past (and (setcc_carry (cmp ...)), 1).
13216 if (Cond.getOpcode() == ISD::AND &&
13217 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13218 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13219 if (C && C->getAPIntValue() == 1)
13220 Cond = Cond.getOperand(0);
13223 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13224 // setting operand in place of the X86ISD::SETCC.
13225 unsigned CondOpcode = Cond.getOpcode();
13226 if (CondOpcode == X86ISD::SETCC ||
13227 CondOpcode == X86ISD::SETCC_CARRY) {
13228 CC = Cond.getOperand(0);
13230 SDValue Cmp = Cond.getOperand(1);
13231 unsigned Opc = Cmp.getOpcode();
13232 MVT VT = Op.getSimpleValueType();
13234 bool IllegalFPCMov = false;
13235 if (VT.isFloatingPoint() && !VT.isVector() &&
13236 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13237 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13239 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13240 Opc == X86ISD::BT) { // FIXME
13244 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13245 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13246 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13247 Cond.getOperand(0).getValueType() != MVT::i8)) {
13248 SDValue LHS = Cond.getOperand(0);
13249 SDValue RHS = Cond.getOperand(1);
13250 unsigned X86Opcode;
13253 switch (CondOpcode) {
13254 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13255 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13256 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13257 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13258 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13259 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13260 default: llvm_unreachable("unexpected overflowing operator");
13262 if (CondOpcode == ISD::UMULO)
13263 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13266 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13268 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13270 if (CondOpcode == ISD::UMULO)
13271 Cond = X86Op.getValue(2);
13273 Cond = X86Op.getValue(1);
13275 CC = DAG.getConstant(X86Cond, MVT::i8);
13280 // Look pass the truncate if the high bits are known zero.
13281 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13282 Cond = Cond.getOperand(0);
13284 // We know the result of AND is compared against zero. Try to match
13286 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13287 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13288 if (NewSetCC.getNode()) {
13289 CC = NewSetCC.getOperand(0);
13290 Cond = NewSetCC.getOperand(1);
13297 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13298 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13301 // a < b ? -1 : 0 -> RES = ~setcc_carry
13302 // a < b ? 0 : -1 -> RES = setcc_carry
13303 // a >= b ? -1 : 0 -> RES = setcc_carry
13304 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13305 if (Cond.getOpcode() == X86ISD::SUB) {
13306 Cond = ConvertCmpIfNecessary(Cond, DAG);
13307 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13309 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13310 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13311 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13312 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
13313 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13314 return DAG.getNOT(DL, Res, Res.getValueType());
13319 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13320 // widen the cmov and push the truncate through. This avoids introducing a new
13321 // branch during isel and doesn't add any extensions.
13322 if (Op.getValueType() == MVT::i8 &&
13323 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13324 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13325 if (T1.getValueType() == T2.getValueType() &&
13326 // Blacklist CopyFromReg to avoid partial register stalls.
13327 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13328 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13329 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13330 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13334 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13335 // condition is true.
13336 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13337 SDValue Ops[] = { Op2, Op1, CC, Cond };
13338 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13341 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
13342 SelectionDAG &DAG) {
13343 MVT VT = Op->getSimpleValueType(0);
13344 SDValue In = Op->getOperand(0);
13345 MVT InVT = In.getSimpleValueType();
13346 MVT VTElt = VT.getVectorElementType();
13347 MVT InVTElt = InVT.getVectorElementType();
13351 if ((InVTElt == MVT::i1) &&
13352 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
13353 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
13355 ((Subtarget->hasBWI() && VT.is512BitVector() &&
13356 VTElt.getSizeInBits() <= 16)) ||
13358 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
13359 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
13361 ((Subtarget->hasDQI() && VT.is512BitVector() &&
13362 VTElt.getSizeInBits() >= 32))))
13363 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13365 unsigned int NumElts = VT.getVectorNumElements();
13367 if (NumElts != 8 && NumElts != 16)
13370 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
13371 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
13372 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
13373 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13376 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13377 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13379 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
13380 Constant *C = ConstantInt::get(*DAG.getContext(),
13381 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
13383 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13384 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13385 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
13386 MachinePointerInfo::getConstantPool(),
13387 false, false, false, Alignment);
13388 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
13389 if (VT.is512BitVector())
13391 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
13394 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13395 SelectionDAG &DAG) {
13396 MVT VT = Op->getSimpleValueType(0);
13397 SDValue In = Op->getOperand(0);
13398 MVT InVT = In.getSimpleValueType();
13401 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13402 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
13404 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13405 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
13406 (VT != MVT::v16i16 || InVT != MVT::v16i8))
13409 if (Subtarget->hasInt256())
13410 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13412 // Optimize vectors in AVX mode
13413 // Sign extend v8i16 to v8i32 and
13416 // Divide input vector into two parts
13417 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13418 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13419 // concat the vectors to original VT
13421 unsigned NumElems = InVT.getVectorNumElements();
13422 SDValue Undef = DAG.getUNDEF(InVT);
13424 SmallVector<int,8> ShufMask1(NumElems, -1);
13425 for (unsigned i = 0; i != NumElems/2; ++i)
13428 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
13430 SmallVector<int,8> ShufMask2(NumElems, -1);
13431 for (unsigned i = 0; i != NumElems/2; ++i)
13432 ShufMask2[i] = i + NumElems/2;
13434 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
13436 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
13437 VT.getVectorNumElements()/2);
13439 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
13440 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
13442 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13445 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
13446 // may emit an illegal shuffle but the expansion is still better than scalar
13447 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
13448 // we'll emit a shuffle and a arithmetic shift.
13449 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
13450 // TODO: It is possible to support ZExt by zeroing the undef values during
13451 // the shuffle phase or after the shuffle.
13452 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
13453 SelectionDAG &DAG) {
13454 MVT RegVT = Op.getSimpleValueType();
13455 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
13456 assert(RegVT.isInteger() &&
13457 "We only custom lower integer vector sext loads.");
13459 // Nothing useful we can do without SSE2 shuffles.
13460 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
13462 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
13464 EVT MemVT = Ld->getMemoryVT();
13465 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13466 unsigned RegSz = RegVT.getSizeInBits();
13468 ISD::LoadExtType Ext = Ld->getExtensionType();
13470 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
13471 && "Only anyext and sext are currently implemented.");
13472 assert(MemVT != RegVT && "Cannot extend to the same type");
13473 assert(MemVT.isVector() && "Must load a vector from memory");
13475 unsigned NumElems = RegVT.getVectorNumElements();
13476 unsigned MemSz = MemVT.getSizeInBits();
13477 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13479 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
13480 // The only way in which we have a legal 256-bit vector result but not the
13481 // integer 256-bit operations needed to directly lower a sextload is if we
13482 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
13483 // a 128-bit vector and a normal sign_extend to 256-bits that should get
13484 // correctly legalized. We do this late to allow the canonical form of
13485 // sextload to persist throughout the rest of the DAG combiner -- it wants
13486 // to fold together any extensions it can, and so will fuse a sign_extend
13487 // of an sextload into a sextload targeting a wider value.
13489 if (MemSz == 128) {
13490 // Just switch this to a normal load.
13491 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
13492 "it must be a legal 128-bit vector "
13494 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
13495 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
13496 Ld->isInvariant(), Ld->getAlignment());
13498 assert(MemSz < 128 &&
13499 "Can't extend a type wider than 128 bits to a 256 bit vector!");
13500 // Do an sext load to a 128-bit vector type. We want to use the same
13501 // number of elements, but elements half as wide. This will end up being
13502 // recursively lowered by this routine, but will succeed as we definitely
13503 // have all the necessary features if we're using AVX1.
13505 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
13506 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
13508 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
13509 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
13510 Ld->isNonTemporal(), Ld->isInvariant(),
13511 Ld->getAlignment());
13514 // Replace chain users with the new chain.
13515 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
13516 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
13518 // Finally, do a normal sign-extend to the desired register.
13519 return DAG.getSExtOrTrunc(Load, dl, RegVT);
13522 // All sizes must be a power of two.
13523 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
13524 "Non-power-of-two elements are not custom lowered!");
13526 // Attempt to load the original value using scalar loads.
13527 // Find the largest scalar type that divides the total loaded size.
13528 MVT SclrLoadTy = MVT::i8;
13529 for (MVT Tp : MVT::integer_valuetypes()) {
13530 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
13535 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
13536 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
13538 SclrLoadTy = MVT::f64;
13540 // Calculate the number of scalar loads that we need to perform
13541 // in order to load our vector from memory.
13542 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
13544 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
13545 "Can only lower sext loads with a single scalar load!");
13547 unsigned loadRegZize = RegSz;
13548 if (Ext == ISD::SEXTLOAD && RegSz == 256)
13551 // Represent our vector as a sequence of elements which are the
13552 // largest scalar that we can load.
13553 EVT LoadUnitVecVT = EVT::getVectorVT(
13554 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
13556 // Represent the data using the same element type that is stored in
13557 // memory. In practice, we ''widen'' MemVT.
13559 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13560 loadRegZize / MemVT.getScalarType().getSizeInBits());
13562 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
13563 "Invalid vector type");
13565 // We can't shuffle using an illegal type.
13566 assert(TLI.isTypeLegal(WideVecVT) &&
13567 "We only lower types that form legal widened vector types");
13569 SmallVector<SDValue, 8> Chains;
13570 SDValue Ptr = Ld->getBasePtr();
13571 SDValue Increment =
13572 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
13573 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
13575 for (unsigned i = 0; i < NumLoads; ++i) {
13576 // Perform a single load.
13577 SDValue ScalarLoad =
13578 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
13579 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
13580 Ld->getAlignment());
13581 Chains.push_back(ScalarLoad.getValue(1));
13582 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
13583 // another round of DAGCombining.
13585 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
13587 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
13588 ScalarLoad, DAG.getIntPtrConstant(i));
13590 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13593 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
13595 // Bitcast the loaded value to a vector of the original element type, in
13596 // the size of the target vector type.
13597 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
13598 unsigned SizeRatio = RegSz / MemSz;
13600 if (Ext == ISD::SEXTLOAD) {
13601 // If we have SSE4.1, we can directly emit a VSEXT node.
13602 if (Subtarget->hasSSE41()) {
13603 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
13604 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13608 // Otherwise we'll shuffle the small elements in the high bits of the
13609 // larger type and perform an arithmetic shift. If the shift is not legal
13610 // it's better to scalarize.
13611 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
13612 "We can't implement a sext load without an arithmetic right shift!");
13614 // Redistribute the loaded elements into the different locations.
13615 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13616 for (unsigned i = 0; i != NumElems; ++i)
13617 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
13619 SDValue Shuff = DAG.getVectorShuffle(
13620 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13622 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13624 // Build the arithmetic shift.
13625 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
13626 MemVT.getVectorElementType().getSizeInBits();
13628 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
13630 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13634 // Redistribute the loaded elements into the different locations.
13635 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13636 for (unsigned i = 0; i != NumElems; ++i)
13637 ShuffleVec[i * SizeRatio] = i;
13639 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13640 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13642 // Bitcast to the requested type.
13643 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13644 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13648 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
13649 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
13650 // from the AND / OR.
13651 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
13652 Opc = Op.getOpcode();
13653 if (Opc != ISD::OR && Opc != ISD::AND)
13655 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13656 Op.getOperand(0).hasOneUse() &&
13657 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
13658 Op.getOperand(1).hasOneUse());
13661 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
13662 // 1 and that the SETCC node has a single use.
13663 static bool isXor1OfSetCC(SDValue Op) {
13664 if (Op.getOpcode() != ISD::XOR)
13666 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
13667 if (N1C && N1C->getAPIntValue() == 1) {
13668 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13669 Op.getOperand(0).hasOneUse();
13674 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
13675 bool addTest = true;
13676 SDValue Chain = Op.getOperand(0);
13677 SDValue Cond = Op.getOperand(1);
13678 SDValue Dest = Op.getOperand(2);
13681 bool Inverted = false;
13683 if (Cond.getOpcode() == ISD::SETCC) {
13684 // Check for setcc([su]{add,sub,mul}o == 0).
13685 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
13686 isa<ConstantSDNode>(Cond.getOperand(1)) &&
13687 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
13688 Cond.getOperand(0).getResNo() == 1 &&
13689 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
13690 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
13691 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
13692 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
13693 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
13694 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
13696 Cond = Cond.getOperand(0);
13698 SDValue NewCond = LowerSETCC(Cond, DAG);
13699 if (NewCond.getNode())
13704 // FIXME: LowerXALUO doesn't handle these!!
13705 else if (Cond.getOpcode() == X86ISD::ADD ||
13706 Cond.getOpcode() == X86ISD::SUB ||
13707 Cond.getOpcode() == X86ISD::SMUL ||
13708 Cond.getOpcode() == X86ISD::UMUL)
13709 Cond = LowerXALUO(Cond, DAG);
13712 // Look pass (and (setcc_carry (cmp ...)), 1).
13713 if (Cond.getOpcode() == ISD::AND &&
13714 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13715 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13716 if (C && C->getAPIntValue() == 1)
13717 Cond = Cond.getOperand(0);
13720 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13721 // setting operand in place of the X86ISD::SETCC.
13722 unsigned CondOpcode = Cond.getOpcode();
13723 if (CondOpcode == X86ISD::SETCC ||
13724 CondOpcode == X86ISD::SETCC_CARRY) {
13725 CC = Cond.getOperand(0);
13727 SDValue Cmp = Cond.getOperand(1);
13728 unsigned Opc = Cmp.getOpcode();
13729 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
13730 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
13734 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
13738 // These can only come from an arithmetic instruction with overflow,
13739 // e.g. SADDO, UADDO.
13740 Cond = Cond.getNode()->getOperand(1);
13746 CondOpcode = Cond.getOpcode();
13747 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13748 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13749 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13750 Cond.getOperand(0).getValueType() != MVT::i8)) {
13751 SDValue LHS = Cond.getOperand(0);
13752 SDValue RHS = Cond.getOperand(1);
13753 unsigned X86Opcode;
13756 // Keep this in sync with LowerXALUO, otherwise we might create redundant
13757 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
13759 switch (CondOpcode) {
13760 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13762 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13764 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
13767 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13768 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13770 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13772 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
13775 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13776 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13777 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13778 default: llvm_unreachable("unexpected overflowing operator");
13781 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
13782 if (CondOpcode == ISD::UMULO)
13783 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13786 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13788 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
13790 if (CondOpcode == ISD::UMULO)
13791 Cond = X86Op.getValue(2);
13793 Cond = X86Op.getValue(1);
13795 CC = DAG.getConstant(X86Cond, MVT::i8);
13799 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
13800 SDValue Cmp = Cond.getOperand(0).getOperand(1);
13801 if (CondOpc == ISD::OR) {
13802 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
13803 // two branches instead of an explicit OR instruction with a
13805 if (Cmp == Cond.getOperand(1).getOperand(1) &&
13806 isX86LogicalCmp(Cmp)) {
13807 CC = Cond.getOperand(0).getOperand(0);
13808 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13809 Chain, Dest, CC, Cmp);
13810 CC = Cond.getOperand(1).getOperand(0);
13814 } else { // ISD::AND
13815 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
13816 // two branches instead of an explicit AND instruction with a
13817 // separate test. However, we only do this if this block doesn't
13818 // have a fall-through edge, because this requires an explicit
13819 // jmp when the condition is false.
13820 if (Cmp == Cond.getOperand(1).getOperand(1) &&
13821 isX86LogicalCmp(Cmp) &&
13822 Op.getNode()->hasOneUse()) {
13823 X86::CondCode CCode =
13824 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13825 CCode = X86::GetOppositeBranchCondition(CCode);
13826 CC = DAG.getConstant(CCode, MVT::i8);
13827 SDNode *User = *Op.getNode()->use_begin();
13828 // Look for an unconditional branch following this conditional branch.
13829 // We need this because we need to reverse the successors in order
13830 // to implement FCMP_OEQ.
13831 if (User->getOpcode() == ISD::BR) {
13832 SDValue FalseBB = User->getOperand(1);
13834 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13835 assert(NewBR == User);
13839 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13840 Chain, Dest, CC, Cmp);
13841 X86::CondCode CCode =
13842 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
13843 CCode = X86::GetOppositeBranchCondition(CCode);
13844 CC = DAG.getConstant(CCode, MVT::i8);
13850 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
13851 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
13852 // It should be transformed during dag combiner except when the condition
13853 // is set by a arithmetics with overflow node.
13854 X86::CondCode CCode =
13855 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13856 CCode = X86::GetOppositeBranchCondition(CCode);
13857 CC = DAG.getConstant(CCode, MVT::i8);
13858 Cond = Cond.getOperand(0).getOperand(1);
13860 } else if (Cond.getOpcode() == ISD::SETCC &&
13861 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
13862 // For FCMP_OEQ, we can emit
13863 // two branches instead of an explicit AND instruction with a
13864 // separate test. However, we only do this if this block doesn't
13865 // have a fall-through edge, because this requires an explicit
13866 // jmp when the condition is false.
13867 if (Op.getNode()->hasOneUse()) {
13868 SDNode *User = *Op.getNode()->use_begin();
13869 // Look for an unconditional branch following this conditional branch.
13870 // We need this because we need to reverse the successors in order
13871 // to implement FCMP_OEQ.
13872 if (User->getOpcode() == ISD::BR) {
13873 SDValue FalseBB = User->getOperand(1);
13875 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13876 assert(NewBR == User);
13880 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13881 Cond.getOperand(0), Cond.getOperand(1));
13882 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13883 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13884 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13885 Chain, Dest, CC, Cmp);
13886 CC = DAG.getConstant(X86::COND_P, MVT::i8);
13891 } else if (Cond.getOpcode() == ISD::SETCC &&
13892 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
13893 // For FCMP_UNE, we can emit
13894 // two branches instead of an explicit AND instruction with a
13895 // separate test. However, we only do this if this block doesn't
13896 // have a fall-through edge, because this requires an explicit
13897 // jmp when the condition is false.
13898 if (Op.getNode()->hasOneUse()) {
13899 SDNode *User = *Op.getNode()->use_begin();
13900 // Look for an unconditional branch following this conditional branch.
13901 // We need this because we need to reverse the successors in order
13902 // to implement FCMP_UNE.
13903 if (User->getOpcode() == ISD::BR) {
13904 SDValue FalseBB = User->getOperand(1);
13906 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13907 assert(NewBR == User);
13910 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13911 Cond.getOperand(0), Cond.getOperand(1));
13912 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13913 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13914 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13915 Chain, Dest, CC, Cmp);
13916 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
13926 // Look pass the truncate if the high bits are known zero.
13927 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13928 Cond = Cond.getOperand(0);
13930 // We know the result of AND is compared against zero. Try to match
13932 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13933 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
13934 if (NewSetCC.getNode()) {
13935 CC = NewSetCC.getOperand(0);
13936 Cond = NewSetCC.getOperand(1);
13943 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
13944 CC = DAG.getConstant(X86Cond, MVT::i8);
13945 Cond = EmitTest(Cond, X86Cond, dl, DAG);
13947 Cond = ConvertCmpIfNecessary(Cond, DAG);
13948 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13949 Chain, Dest, CC, Cond);
13952 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
13953 // Calls to _alloca are needed to probe the stack when allocating more than 4k
13954 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
13955 // that the guard pages used by the OS virtual memory manager are allocated in
13956 // correct sequence.
13958 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
13959 SelectionDAG &DAG) const {
13960 MachineFunction &MF = DAG.getMachineFunction();
13961 bool SplitStack = MF.shouldSplitStack();
13962 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
13967 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13968 SDNode* Node = Op.getNode();
13970 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
13971 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
13972 " not tell us which reg is the stack pointer!");
13973 EVT VT = Node->getValueType(0);
13974 SDValue Tmp1 = SDValue(Node, 0);
13975 SDValue Tmp2 = SDValue(Node, 1);
13976 SDValue Tmp3 = Node->getOperand(2);
13977 SDValue Chain = Tmp1.getOperand(0);
13979 // Chain the dynamic stack allocation so that it doesn't modify the stack
13980 // pointer when other instructions are using the stack.
13981 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
13984 SDValue Size = Tmp2.getOperand(1);
13985 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
13986 Chain = SP.getValue(1);
13987 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
13988 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
13989 unsigned StackAlign = TFI.getStackAlignment();
13990 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
13991 if (Align > StackAlign)
13992 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
13993 DAG.getConstant(-(uint64_t)Align, VT));
13994 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
13996 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
13997 DAG.getIntPtrConstant(0, true), SDValue(),
14000 SDValue Ops[2] = { Tmp1, Tmp2 };
14001 return DAG.getMergeValues(Ops, dl);
14005 SDValue Chain = Op.getOperand(0);
14006 SDValue Size = Op.getOperand(1);
14007 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14008 EVT VT = Op.getNode()->getValueType(0);
14010 bool Is64Bit = Subtarget->is64Bit();
14011 EVT SPTy = getPointerTy();
14014 MachineRegisterInfo &MRI = MF.getRegInfo();
14017 // The 64 bit implementation of segmented stacks needs to clobber both r10
14018 // r11. This makes it impossible to use it along with nested parameters.
14019 const Function *F = MF.getFunction();
14021 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14023 if (I->hasNestAttr())
14024 report_fatal_error("Cannot use segmented stacks with functions that "
14025 "have nested arguments.");
14028 const TargetRegisterClass *AddrRegClass =
14029 getRegClassFor(getPointerTy());
14030 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14031 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14032 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14033 DAG.getRegister(Vreg, SPTy));
14034 SDValue Ops1[2] = { Value, Chain };
14035 return DAG.getMergeValues(Ops1, dl);
14038 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14040 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14041 Flag = Chain.getValue(1);
14042 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14044 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14046 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14047 unsigned SPReg = RegInfo->getStackRegister();
14048 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14049 Chain = SP.getValue(1);
14052 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14053 DAG.getConstant(-(uint64_t)Align, VT));
14054 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14057 SDValue Ops1[2] = { SP, Chain };
14058 return DAG.getMergeValues(Ops1, dl);
14062 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14063 MachineFunction &MF = DAG.getMachineFunction();
14064 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14066 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14069 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14070 // vastart just stores the address of the VarArgsFrameIndex slot into the
14071 // memory location argument.
14072 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14074 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14075 MachinePointerInfo(SV), false, false, 0);
14079 // gp_offset (0 - 6 * 8)
14080 // fp_offset (48 - 48 + 8 * 16)
14081 // overflow_arg_area (point to parameters coming in memory).
14083 SmallVector<SDValue, 8> MemOps;
14084 SDValue FIN = Op.getOperand(1);
14086 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14087 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14089 FIN, MachinePointerInfo(SV), false, false, 0);
14090 MemOps.push_back(Store);
14093 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14094 FIN, DAG.getIntPtrConstant(4));
14095 Store = DAG.getStore(Op.getOperand(0), DL,
14096 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
14098 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14099 MemOps.push_back(Store);
14101 // Store ptr to overflow_arg_area
14102 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14103 FIN, DAG.getIntPtrConstant(4));
14104 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14106 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14107 MachinePointerInfo(SV, 8),
14109 MemOps.push_back(Store);
14111 // Store ptr to reg_save_area.
14112 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14113 FIN, DAG.getIntPtrConstant(8));
14114 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14116 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14117 MachinePointerInfo(SV, 16), false, false, 0);
14118 MemOps.push_back(Store);
14119 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14122 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14123 assert(Subtarget->is64Bit() &&
14124 "LowerVAARG only handles 64-bit va_arg!");
14125 assert((Subtarget->isTargetLinux() ||
14126 Subtarget->isTargetDarwin()) &&
14127 "Unhandled target in LowerVAARG");
14128 assert(Op.getNode()->getNumOperands() == 4);
14129 SDValue Chain = Op.getOperand(0);
14130 SDValue SrcPtr = Op.getOperand(1);
14131 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14132 unsigned Align = Op.getConstantOperandVal(3);
14135 EVT ArgVT = Op.getNode()->getValueType(0);
14136 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14137 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14140 // Decide which area this value should be read from.
14141 // TODO: Implement the AMD64 ABI in its entirety. This simple
14142 // selection mechanism works only for the basic types.
14143 if (ArgVT == MVT::f80) {
14144 llvm_unreachable("va_arg for f80 not yet implemented");
14145 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14146 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14147 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14148 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14150 llvm_unreachable("Unhandled argument type in LowerVAARG");
14153 if (ArgMode == 2) {
14154 // Sanity Check: Make sure using fp_offset makes sense.
14155 assert(!DAG.getTarget().Options.UseSoftFloat &&
14156 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14157 Attribute::NoImplicitFloat)) &&
14158 Subtarget->hasSSE1());
14161 // Insert VAARG_64 node into the DAG
14162 // VAARG_64 returns two values: Variable Argument Address, Chain
14163 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, MVT::i32),
14164 DAG.getConstant(ArgMode, MVT::i8),
14165 DAG.getConstant(Align, MVT::i32)};
14166 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14167 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14168 VTs, InstOps, MVT::i64,
14169 MachinePointerInfo(SV),
14171 /*Volatile=*/false,
14173 /*WriteMem=*/true);
14174 Chain = VAARG.getValue(1);
14176 // Load the next argument and return it
14177 return DAG.getLoad(ArgVT, dl,
14180 MachinePointerInfo(),
14181 false, false, false, 0);
14184 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14185 SelectionDAG &DAG) {
14186 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14187 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14188 SDValue Chain = Op.getOperand(0);
14189 SDValue DstPtr = Op.getOperand(1);
14190 SDValue SrcPtr = Op.getOperand(2);
14191 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14192 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14195 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14196 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
14198 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14201 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14202 // amount is a constant. Takes immediate version of shift as input.
14203 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14204 SDValue SrcOp, uint64_t ShiftAmt,
14205 SelectionDAG &DAG) {
14206 MVT ElementType = VT.getVectorElementType();
14208 // Fold this packed shift into its first operand if ShiftAmt is 0.
14212 // Check for ShiftAmt >= element width
14213 if (ShiftAmt >= ElementType.getSizeInBits()) {
14214 if (Opc == X86ISD::VSRAI)
14215 ShiftAmt = ElementType.getSizeInBits() - 1;
14217 return DAG.getConstant(0, VT);
14220 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14221 && "Unknown target vector shift-by-constant node");
14223 // Fold this packed vector shift into a build vector if SrcOp is a
14224 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14225 if (VT == SrcOp.getSimpleValueType() &&
14226 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14227 SmallVector<SDValue, 8> Elts;
14228 unsigned NumElts = SrcOp->getNumOperands();
14229 ConstantSDNode *ND;
14232 default: llvm_unreachable(nullptr);
14233 case X86ISD::VSHLI:
14234 for (unsigned i=0; i!=NumElts; ++i) {
14235 SDValue CurrentOp = SrcOp->getOperand(i);
14236 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14237 Elts.push_back(CurrentOp);
14240 ND = cast<ConstantSDNode>(CurrentOp);
14241 const APInt &C = ND->getAPIntValue();
14242 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
14245 case X86ISD::VSRLI:
14246 for (unsigned i=0; i!=NumElts; ++i) {
14247 SDValue CurrentOp = SrcOp->getOperand(i);
14248 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14249 Elts.push_back(CurrentOp);
14252 ND = cast<ConstantSDNode>(CurrentOp);
14253 const APInt &C = ND->getAPIntValue();
14254 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
14257 case X86ISD::VSRAI:
14258 for (unsigned i=0; i!=NumElts; ++i) {
14259 SDValue CurrentOp = SrcOp->getOperand(i);
14260 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14261 Elts.push_back(CurrentOp);
14264 ND = cast<ConstantSDNode>(CurrentOp);
14265 const APInt &C = ND->getAPIntValue();
14266 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
14271 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14274 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
14277 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14278 // may or may not be a constant. Takes immediate version of shift as input.
14279 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14280 SDValue SrcOp, SDValue ShAmt,
14281 SelectionDAG &DAG) {
14282 MVT SVT = ShAmt.getSimpleValueType();
14283 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
14285 // Catch shift-by-constant.
14286 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14287 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14288 CShAmt->getZExtValue(), DAG);
14290 // Change opcode to non-immediate version
14292 default: llvm_unreachable("Unknown target vector shift node");
14293 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14294 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14295 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14298 const X86Subtarget &Subtarget =
14299 static_cast<const X86Subtarget &>(DAG.getSubtarget());
14300 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
14301 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
14302 // Let the shuffle legalizer expand this shift amount node.
14303 SDValue Op0 = ShAmt.getOperand(0);
14304 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
14305 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
14307 // Need to build a vector containing shift amount.
14308 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
14309 SmallVector<SDValue, 4> ShOps;
14310 ShOps.push_back(ShAmt);
14311 if (SVT == MVT::i32) {
14312 ShOps.push_back(DAG.getConstant(0, SVT));
14313 ShOps.push_back(DAG.getUNDEF(SVT));
14315 ShOps.push_back(DAG.getUNDEF(SVT));
14317 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
14318 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
14321 // The return type has to be a 128-bit type with the same element
14322 // type as the input type.
14323 MVT EltVT = VT.getVectorElementType();
14324 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14326 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14327 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14330 /// \brief Return (and \p Op, \p Mask) for compare instructions or
14331 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
14332 /// necessary casting for \p Mask when lowering masking intrinsics.
14333 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14334 SDValue PreservedSrc,
14335 const X86Subtarget *Subtarget,
14336 SelectionDAG &DAG) {
14337 EVT VT = Op.getValueType();
14338 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14339 MVT::i1, VT.getVectorNumElements());
14340 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14341 Mask.getValueType().getSizeInBits());
14344 assert(MaskVT.isSimple() && "invalid mask type");
14346 if (isAllOnes(Mask))
14349 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
14350 // are extracted by EXTRACT_SUBVECTOR.
14351 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14352 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14353 DAG.getIntPtrConstant(0));
14355 switch (Op.getOpcode()) {
14357 case X86ISD::PCMPEQM:
14358 case X86ISD::PCMPGTM:
14360 case X86ISD::CMPMU:
14361 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
14363 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14364 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14365 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
14368 /// \brief Creates an SDNode for a predicated scalar operation.
14369 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
14370 /// The mask is comming as MVT::i8 and it should be truncated
14371 /// to MVT::i1 while lowering masking intrinsics.
14372 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
14373 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
14374 /// a scalar instruction.
14375 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
14376 SDValue PreservedSrc,
14377 const X86Subtarget *Subtarget,
14378 SelectionDAG &DAG) {
14379 if (isAllOnes(Mask))
14382 EVT VT = Op.getValueType();
14384 // The mask should be of type MVT::i1
14385 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
14387 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14388 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14389 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
14392 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14393 SelectionDAG &DAG) {
14395 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14396 EVT VT = Op.getValueType();
14397 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
14399 switch(IntrData->Type) {
14400 case INTR_TYPE_1OP:
14401 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
14402 case INTR_TYPE_2OP:
14403 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14405 case INTR_TYPE_3OP:
14406 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14407 Op.getOperand(2), Op.getOperand(3));
14408 case INTR_TYPE_1OP_MASK_RM: {
14409 SDValue Src = Op.getOperand(1);
14410 SDValue Src0 = Op.getOperand(2);
14411 SDValue Mask = Op.getOperand(3);
14412 SDValue RoundingMode = Op.getOperand(4);
14413 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
14415 Mask, Src0, Subtarget, DAG);
14417 case INTR_TYPE_SCALAR_MASK_RM: {
14418 SDValue Src1 = Op.getOperand(1);
14419 SDValue Src2 = Op.getOperand(2);
14420 SDValue Src0 = Op.getOperand(3);
14421 SDValue Mask = Op.getOperand(4);
14422 SDValue RoundingMode = Op.getOperand(5);
14423 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
14425 Mask, Src0, Subtarget, DAG);
14427 case INTR_TYPE_2OP_MASK: {
14428 SDValue Src1 = Op.getOperand(1);
14429 SDValue Src2 = Op.getOperand(2);
14430 SDValue PassThru = Op.getOperand(3);
14431 SDValue Mask = Op.getOperand(4);
14432 // We specify 2 possible opcodes for intrinsics with rounding modes.
14433 // First, we check if the intrinsic may have non-default rounding mode,
14434 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14435 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
14436 if (IntrWithRoundingModeOpcode != 0) {
14437 SDValue Rnd = Op.getOperand(5);
14438 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
14439 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
14440 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
14441 dl, Op.getValueType(),
14443 Mask, PassThru, Subtarget, DAG);
14446 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
14448 Mask, PassThru, Subtarget, DAG);
14450 case FMA_OP_MASK: {
14451 SDValue Src1 = Op.getOperand(1);
14452 SDValue Src2 = Op.getOperand(2);
14453 SDValue Src3 = Op.getOperand(3);
14454 SDValue Mask = Op.getOperand(4);
14455 // We specify 2 possible opcodes for intrinsics with rounding modes.
14456 // First, we check if the intrinsic may have non-default rounding mode,
14457 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14458 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
14459 if (IntrWithRoundingModeOpcode != 0) {
14460 SDValue Rnd = Op.getOperand(5);
14461 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
14462 X86::STATIC_ROUNDING::CUR_DIRECTION)
14463 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
14464 dl, Op.getValueType(),
14465 Src1, Src2, Src3, Rnd),
14466 Mask, Src1, Subtarget, DAG);
14468 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
14469 dl, Op.getValueType(),
14471 Mask, Src1, Subtarget, DAG);
14474 case CMP_MASK_CC: {
14475 // Comparison intrinsics with masks.
14476 // Example of transformation:
14477 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
14478 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
14480 // (v8i1 (insert_subvector undef,
14481 // (v2i1 (and (PCMPEQM %a, %b),
14482 // (extract_subvector
14483 // (v8i1 (bitcast %mask)), 0))), 0))))
14484 EVT VT = Op.getOperand(1).getValueType();
14485 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14486 VT.getVectorNumElements());
14487 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
14488 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14489 Mask.getValueType().getSizeInBits());
14491 if (IntrData->Type == CMP_MASK_CC) {
14492 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
14493 Op.getOperand(2), Op.getOperand(3));
14495 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
14496 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
14499 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
14500 DAG.getTargetConstant(0, MaskVT),
14502 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
14503 DAG.getUNDEF(BitcastVT), CmpMask,
14504 DAG.getIntPtrConstant(0));
14505 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
14507 case COMI: { // Comparison intrinsics
14508 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
14509 SDValue LHS = Op.getOperand(1);
14510 SDValue RHS = Op.getOperand(2);
14511 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
14512 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
14513 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
14514 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14515 DAG.getConstant(X86CC, MVT::i8), Cond);
14516 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14519 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
14520 Op.getOperand(1), Op.getOperand(2), DAG);
14522 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
14523 Op.getSimpleValueType(),
14525 Op.getOperand(2), DAG),
14526 Op.getOperand(4), Op.getOperand(3), Subtarget,
14528 case COMPRESS_EXPAND_IN_REG: {
14529 SDValue Mask = Op.getOperand(3);
14530 SDValue DataToCompress = Op.getOperand(1);
14531 SDValue PassThru = Op.getOperand(2);
14532 if (isAllOnes(Mask)) // return data as is
14533 return Op.getOperand(1);
14534 EVT VT = Op.getValueType();
14535 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14536 VT.getVectorNumElements());
14537 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14538 Mask.getValueType().getSizeInBits());
14540 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14541 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14542 DAG.getIntPtrConstant(0));
14544 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
14548 SDValue Mask = Op.getOperand(3);
14549 EVT VT = Op.getValueType();
14550 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14551 VT.getVectorNumElements());
14552 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14553 Mask.getValueType().getSizeInBits());
14555 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14556 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14557 DAG.getIntPtrConstant(0));
14558 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
14567 default: return SDValue(); // Don't custom lower most intrinsics.
14569 case Intrinsic::x86_avx512_mask_valign_q_512:
14570 case Intrinsic::x86_avx512_mask_valign_d_512:
14571 // Vector source operands are swapped.
14572 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
14573 Op.getValueType(), Op.getOperand(2),
14576 Op.getOperand(5), Op.getOperand(4),
14579 // ptest and testp intrinsics. The intrinsic these come from are designed to
14580 // return an integer value, not just an instruction so lower it to the ptest
14581 // or testp pattern and a setcc for the result.
14582 case Intrinsic::x86_sse41_ptestz:
14583 case Intrinsic::x86_sse41_ptestc:
14584 case Intrinsic::x86_sse41_ptestnzc:
14585 case Intrinsic::x86_avx_ptestz_256:
14586 case Intrinsic::x86_avx_ptestc_256:
14587 case Intrinsic::x86_avx_ptestnzc_256:
14588 case Intrinsic::x86_avx_vtestz_ps:
14589 case Intrinsic::x86_avx_vtestc_ps:
14590 case Intrinsic::x86_avx_vtestnzc_ps:
14591 case Intrinsic::x86_avx_vtestz_pd:
14592 case Intrinsic::x86_avx_vtestc_pd:
14593 case Intrinsic::x86_avx_vtestnzc_pd:
14594 case Intrinsic::x86_avx_vtestz_ps_256:
14595 case Intrinsic::x86_avx_vtestc_ps_256:
14596 case Intrinsic::x86_avx_vtestnzc_ps_256:
14597 case Intrinsic::x86_avx_vtestz_pd_256:
14598 case Intrinsic::x86_avx_vtestc_pd_256:
14599 case Intrinsic::x86_avx_vtestnzc_pd_256: {
14600 bool IsTestPacked = false;
14603 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
14604 case Intrinsic::x86_avx_vtestz_ps:
14605 case Intrinsic::x86_avx_vtestz_pd:
14606 case Intrinsic::x86_avx_vtestz_ps_256:
14607 case Intrinsic::x86_avx_vtestz_pd_256:
14608 IsTestPacked = true; // Fallthrough
14609 case Intrinsic::x86_sse41_ptestz:
14610 case Intrinsic::x86_avx_ptestz_256:
14612 X86CC = X86::COND_E;
14614 case Intrinsic::x86_avx_vtestc_ps:
14615 case Intrinsic::x86_avx_vtestc_pd:
14616 case Intrinsic::x86_avx_vtestc_ps_256:
14617 case Intrinsic::x86_avx_vtestc_pd_256:
14618 IsTestPacked = true; // Fallthrough
14619 case Intrinsic::x86_sse41_ptestc:
14620 case Intrinsic::x86_avx_ptestc_256:
14622 X86CC = X86::COND_B;
14624 case Intrinsic::x86_avx_vtestnzc_ps:
14625 case Intrinsic::x86_avx_vtestnzc_pd:
14626 case Intrinsic::x86_avx_vtestnzc_ps_256:
14627 case Intrinsic::x86_avx_vtestnzc_pd_256:
14628 IsTestPacked = true; // Fallthrough
14629 case Intrinsic::x86_sse41_ptestnzc:
14630 case Intrinsic::x86_avx_ptestnzc_256:
14632 X86CC = X86::COND_A;
14636 SDValue LHS = Op.getOperand(1);
14637 SDValue RHS = Op.getOperand(2);
14638 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
14639 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
14640 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14641 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
14642 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14644 case Intrinsic::x86_avx512_kortestz_w:
14645 case Intrinsic::x86_avx512_kortestc_w: {
14646 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
14647 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
14648 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
14649 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14650 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
14651 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
14652 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14655 case Intrinsic::x86_sse42_pcmpistria128:
14656 case Intrinsic::x86_sse42_pcmpestria128:
14657 case Intrinsic::x86_sse42_pcmpistric128:
14658 case Intrinsic::x86_sse42_pcmpestric128:
14659 case Intrinsic::x86_sse42_pcmpistrio128:
14660 case Intrinsic::x86_sse42_pcmpestrio128:
14661 case Intrinsic::x86_sse42_pcmpistris128:
14662 case Intrinsic::x86_sse42_pcmpestris128:
14663 case Intrinsic::x86_sse42_pcmpistriz128:
14664 case Intrinsic::x86_sse42_pcmpestriz128: {
14668 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14669 case Intrinsic::x86_sse42_pcmpistria128:
14670 Opcode = X86ISD::PCMPISTRI;
14671 X86CC = X86::COND_A;
14673 case Intrinsic::x86_sse42_pcmpestria128:
14674 Opcode = X86ISD::PCMPESTRI;
14675 X86CC = X86::COND_A;
14677 case Intrinsic::x86_sse42_pcmpistric128:
14678 Opcode = X86ISD::PCMPISTRI;
14679 X86CC = X86::COND_B;
14681 case Intrinsic::x86_sse42_pcmpestric128:
14682 Opcode = X86ISD::PCMPESTRI;
14683 X86CC = X86::COND_B;
14685 case Intrinsic::x86_sse42_pcmpistrio128:
14686 Opcode = X86ISD::PCMPISTRI;
14687 X86CC = X86::COND_O;
14689 case Intrinsic::x86_sse42_pcmpestrio128:
14690 Opcode = X86ISD::PCMPESTRI;
14691 X86CC = X86::COND_O;
14693 case Intrinsic::x86_sse42_pcmpistris128:
14694 Opcode = X86ISD::PCMPISTRI;
14695 X86CC = X86::COND_S;
14697 case Intrinsic::x86_sse42_pcmpestris128:
14698 Opcode = X86ISD::PCMPESTRI;
14699 X86CC = X86::COND_S;
14701 case Intrinsic::x86_sse42_pcmpistriz128:
14702 Opcode = X86ISD::PCMPISTRI;
14703 X86CC = X86::COND_E;
14705 case Intrinsic::x86_sse42_pcmpestriz128:
14706 Opcode = X86ISD::PCMPESTRI;
14707 X86CC = X86::COND_E;
14710 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14711 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14712 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
14713 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14714 DAG.getConstant(X86CC, MVT::i8),
14715 SDValue(PCMP.getNode(), 1));
14716 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14719 case Intrinsic::x86_sse42_pcmpistri128:
14720 case Intrinsic::x86_sse42_pcmpestri128: {
14722 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
14723 Opcode = X86ISD::PCMPISTRI;
14725 Opcode = X86ISD::PCMPESTRI;
14727 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14728 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14729 return DAG.getNode(Opcode, dl, VTs, NewOps);
14734 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14735 SDValue Src, SDValue Mask, SDValue Base,
14736 SDValue Index, SDValue ScaleOp, SDValue Chain,
14737 const X86Subtarget * Subtarget) {
14739 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14740 assert(C && "Invalid scale type");
14741 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14742 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14743 Index.getSimpleValueType().getVectorNumElements());
14745 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14747 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14749 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14750 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
14751 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14752 SDValue Segment = DAG.getRegister(0, MVT::i32);
14753 if (Src.getOpcode() == ISD::UNDEF)
14754 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
14755 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14756 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14757 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
14758 return DAG.getMergeValues(RetOps, dl);
14761 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14762 SDValue Src, SDValue Mask, SDValue Base,
14763 SDValue Index, SDValue ScaleOp, SDValue Chain) {
14765 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14766 assert(C && "Invalid scale type");
14767 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14768 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14769 SDValue Segment = DAG.getRegister(0, MVT::i32);
14770 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14771 Index.getSimpleValueType().getVectorNumElements());
14773 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14775 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14777 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14778 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
14779 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
14780 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14781 return SDValue(Res, 1);
14784 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14785 SDValue Mask, SDValue Base, SDValue Index,
14786 SDValue ScaleOp, SDValue Chain) {
14788 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14789 assert(C && "Invalid scale type");
14790 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14791 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14792 SDValue Segment = DAG.getRegister(0, MVT::i32);
14794 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
14796 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14798 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14800 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14801 //SDVTList VTs = DAG.getVTList(MVT::Other);
14802 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14803 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
14804 return SDValue(Res, 0);
14807 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
14808 // read performance monitor counters (x86_rdpmc).
14809 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
14810 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14811 SmallVectorImpl<SDValue> &Results) {
14812 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14813 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14816 // The ECX register is used to select the index of the performance counter
14818 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
14820 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
14822 // Reads the content of a 64-bit performance counter and returns it in the
14823 // registers EDX:EAX.
14824 if (Subtarget->is64Bit()) {
14825 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14826 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14829 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14830 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14833 Chain = HI.getValue(1);
14835 if (Subtarget->is64Bit()) {
14836 // The EAX register is loaded with the low-order 32 bits. The EDX register
14837 // is loaded with the supported high-order bits of the counter.
14838 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14839 DAG.getConstant(32, MVT::i8));
14840 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14841 Results.push_back(Chain);
14845 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14846 SDValue Ops[] = { LO, HI };
14847 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14848 Results.push_back(Pair);
14849 Results.push_back(Chain);
14852 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
14853 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
14854 // also used to custom lower READCYCLECOUNTER nodes.
14855 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
14856 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14857 SmallVectorImpl<SDValue> &Results) {
14858 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14859 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
14862 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
14863 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
14864 // and the EAX register is loaded with the low-order 32 bits.
14865 if (Subtarget->is64Bit()) {
14866 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14867 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14870 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14871 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14874 SDValue Chain = HI.getValue(1);
14876 if (Opcode == X86ISD::RDTSCP_DAG) {
14877 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14879 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
14880 // the ECX register. Add 'ecx' explicitly to the chain.
14881 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
14883 // Explicitly store the content of ECX at the location passed in input
14884 // to the 'rdtscp' intrinsic.
14885 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
14886 MachinePointerInfo(), false, false, 0);
14889 if (Subtarget->is64Bit()) {
14890 // The EDX register is loaded with the high-order 32 bits of the MSR, and
14891 // the EAX register is loaded with the low-order 32 bits.
14892 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14893 DAG.getConstant(32, MVT::i8));
14894 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14895 Results.push_back(Chain);
14899 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14900 SDValue Ops[] = { LO, HI };
14901 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14902 Results.push_back(Pair);
14903 Results.push_back(Chain);
14906 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
14907 SelectionDAG &DAG) {
14908 SmallVector<SDValue, 2> Results;
14910 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
14912 return DAG.getMergeValues(Results, DL);
14916 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14917 SelectionDAG &DAG) {
14918 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
14920 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
14925 switch(IntrData->Type) {
14927 llvm_unreachable("Unknown Intrinsic Type");
14931 // Emit the node with the right value type.
14932 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
14933 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
14935 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
14936 // Otherwise return the value from Rand, which is always 0, casted to i32.
14937 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
14938 DAG.getConstant(1, Op->getValueType(1)),
14939 DAG.getConstant(X86::COND_B, MVT::i32),
14940 SDValue(Result.getNode(), 1) };
14941 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
14942 DAG.getVTList(Op->getValueType(1), MVT::Glue),
14945 // Return { result, isValid, chain }.
14946 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
14947 SDValue(Result.getNode(), 2));
14950 //gather(v1, mask, index, base, scale);
14951 SDValue Chain = Op.getOperand(0);
14952 SDValue Src = Op.getOperand(2);
14953 SDValue Base = Op.getOperand(3);
14954 SDValue Index = Op.getOperand(4);
14955 SDValue Mask = Op.getOperand(5);
14956 SDValue Scale = Op.getOperand(6);
14957 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
14961 //scatter(base, mask, index, v1, scale);
14962 SDValue Chain = Op.getOperand(0);
14963 SDValue Base = Op.getOperand(2);
14964 SDValue Mask = Op.getOperand(3);
14965 SDValue Index = Op.getOperand(4);
14966 SDValue Src = Op.getOperand(5);
14967 SDValue Scale = Op.getOperand(6);
14968 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
14971 SDValue Hint = Op.getOperand(6);
14973 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
14974 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
14975 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
14976 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
14977 SDValue Chain = Op.getOperand(0);
14978 SDValue Mask = Op.getOperand(2);
14979 SDValue Index = Op.getOperand(3);
14980 SDValue Base = Op.getOperand(4);
14981 SDValue Scale = Op.getOperand(5);
14982 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
14984 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
14986 SmallVector<SDValue, 2> Results;
14987 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
14988 return DAG.getMergeValues(Results, dl);
14990 // Read Performance Monitoring Counters.
14992 SmallVector<SDValue, 2> Results;
14993 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
14994 return DAG.getMergeValues(Results, dl);
14996 // XTEST intrinsics.
14998 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
14999 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15000 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15001 DAG.getConstant(X86::COND_NE, MVT::i8),
15003 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15004 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15005 Ret, SDValue(InTrans.getNode(), 1));
15009 SmallVector<SDValue, 2> Results;
15010 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15011 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15012 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15013 DAG.getConstant(-1, MVT::i8));
15014 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15015 Op.getOperand(4), GenCF.getValue(1));
15016 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15017 Op.getOperand(5), MachinePointerInfo(),
15019 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15020 DAG.getConstant(X86::COND_B, MVT::i8),
15022 Results.push_back(SetCC);
15023 Results.push_back(Store);
15024 return DAG.getMergeValues(Results, dl);
15026 case COMPRESS_TO_MEM: {
15028 SDValue Mask = Op.getOperand(4);
15029 SDValue DataToCompress = Op.getOperand(3);
15030 SDValue Addr = Op.getOperand(2);
15031 SDValue Chain = Op.getOperand(0);
15033 if (isAllOnes(Mask)) // return just a store
15034 return DAG.getStore(Chain, dl, DataToCompress, Addr,
15035 MachinePointerInfo(), false, false, 0);
15037 EVT VT = DataToCompress.getValueType();
15038 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15039 VT.getVectorNumElements());
15040 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15041 Mask.getValueType().getSizeInBits());
15042 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15043 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15044 DAG.getIntPtrConstant(0));
15046 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
15047 DataToCompress, DAG.getUNDEF(VT));
15048 return DAG.getStore(Chain, dl, Compressed, Addr,
15049 MachinePointerInfo(), false, false, 0);
15051 case EXPAND_FROM_MEM: {
15053 SDValue Mask = Op.getOperand(4);
15054 SDValue PathThru = Op.getOperand(3);
15055 SDValue Addr = Op.getOperand(2);
15056 SDValue Chain = Op.getOperand(0);
15057 EVT VT = Op.getValueType();
15059 if (isAllOnes(Mask)) // return just a load
15060 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
15062 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15063 VT.getVectorNumElements());
15064 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15065 Mask.getValueType().getSizeInBits());
15066 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15067 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15068 DAG.getIntPtrConstant(0));
15070 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
15071 false, false, false, 0);
15073 SDValue Results[] = {
15074 DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand, PathThru),
15076 return DAG.getMergeValues(Results, dl);
15081 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15082 SelectionDAG &DAG) const {
15083 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15084 MFI->setReturnAddressIsTaken(true);
15086 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15089 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15091 EVT PtrVT = getPointerTy();
15094 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15095 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15096 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
15097 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15098 DAG.getNode(ISD::ADD, dl, PtrVT,
15099 FrameAddr, Offset),
15100 MachinePointerInfo(), false, false, false, 0);
15103 // Just load the return address.
15104 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15105 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15106 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15109 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15110 MachineFunction &MF = DAG.getMachineFunction();
15111 MachineFrameInfo *MFI = MF.getFrameInfo();
15112 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15113 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15114 EVT VT = Op.getValueType();
15116 MFI->setFrameAddressIsTaken(true);
15118 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
15119 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
15120 // is not possible to crawl up the stack without looking at the unwind codes
15122 int FrameAddrIndex = FuncInfo->getFAIndex();
15123 if (!FrameAddrIndex) {
15124 // Set up a frame object for the return address.
15125 unsigned SlotSize = RegInfo->getSlotSize();
15126 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
15127 SlotSize, /*Offset=*/INT64_MIN, /*IsImmutable=*/false);
15128 FuncInfo->setFAIndex(FrameAddrIndex);
15130 return DAG.getFrameIndex(FrameAddrIndex, VT);
15133 unsigned FrameReg =
15134 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15135 SDLoc dl(Op); // FIXME probably not meaningful
15136 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15137 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15138 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15139 "Invalid Frame Register!");
15140 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15142 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15143 MachinePointerInfo(),
15144 false, false, false, 0);
15148 // FIXME? Maybe this could be a TableGen attribute on some registers and
15149 // this table could be generated automatically from RegInfo.
15150 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15152 unsigned Reg = StringSwitch<unsigned>(RegName)
15153 .Case("esp", X86::ESP)
15154 .Case("rsp", X86::RSP)
15158 report_fatal_error("Invalid register name global variable");
15161 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15162 SelectionDAG &DAG) const {
15163 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15164 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
15167 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15168 SDValue Chain = Op.getOperand(0);
15169 SDValue Offset = Op.getOperand(1);
15170 SDValue Handler = Op.getOperand(2);
15173 EVT PtrVT = getPointerTy();
15174 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15175 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15176 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15177 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15178 "Invalid Frame Register!");
15179 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15180 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15182 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15183 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
15184 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15185 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15187 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15189 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15190 DAG.getRegister(StoreAddrReg, PtrVT));
15193 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15194 SelectionDAG &DAG) const {
15196 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15197 DAG.getVTList(MVT::i32, MVT::Other),
15198 Op.getOperand(0), Op.getOperand(1));
15201 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15202 SelectionDAG &DAG) const {
15204 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15205 Op.getOperand(0), Op.getOperand(1));
15208 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15209 return Op.getOperand(0);
15212 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15213 SelectionDAG &DAG) const {
15214 SDValue Root = Op.getOperand(0);
15215 SDValue Trmp = Op.getOperand(1); // trampoline
15216 SDValue FPtr = Op.getOperand(2); // nested function
15217 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15220 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15221 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
15223 if (Subtarget->is64Bit()) {
15224 SDValue OutChains[6];
15226 // Large code-model.
15227 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15228 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15230 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15231 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15233 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15235 // Load the pointer to the nested function into R11.
15236 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15237 SDValue Addr = Trmp;
15238 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15239 Addr, MachinePointerInfo(TrmpAddr),
15242 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15243 DAG.getConstant(2, MVT::i64));
15244 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15245 MachinePointerInfo(TrmpAddr, 2),
15248 // Load the 'nest' parameter value into R10.
15249 // R10 is specified in X86CallingConv.td
15250 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15251 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15252 DAG.getConstant(10, MVT::i64));
15253 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15254 Addr, MachinePointerInfo(TrmpAddr, 10),
15257 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15258 DAG.getConstant(12, MVT::i64));
15259 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15260 MachinePointerInfo(TrmpAddr, 12),
15263 // Jump to the nested function.
15264 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15265 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15266 DAG.getConstant(20, MVT::i64));
15267 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15268 Addr, MachinePointerInfo(TrmpAddr, 20),
15271 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15272 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15273 DAG.getConstant(22, MVT::i64));
15274 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
15275 MachinePointerInfo(TrmpAddr, 22),
15278 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15280 const Function *Func =
15281 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15282 CallingConv::ID CC = Func->getCallingConv();
15287 llvm_unreachable("Unsupported calling convention");
15288 case CallingConv::C:
15289 case CallingConv::X86_StdCall: {
15290 // Pass 'nest' parameter in ECX.
15291 // Must be kept in sync with X86CallingConv.td
15292 NestReg = X86::ECX;
15294 // Check that ECX wasn't needed by an 'inreg' parameter.
15295 FunctionType *FTy = Func->getFunctionType();
15296 const AttributeSet &Attrs = Func->getAttributes();
15298 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15299 unsigned InRegCount = 0;
15302 for (FunctionType::param_iterator I = FTy->param_begin(),
15303 E = FTy->param_end(); I != E; ++I, ++Idx)
15304 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15305 // FIXME: should only count parameters that are lowered to integers.
15306 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15308 if (InRegCount > 2) {
15309 report_fatal_error("Nest register in use - reduce number of inreg"
15315 case CallingConv::X86_FastCall:
15316 case CallingConv::X86_ThisCall:
15317 case CallingConv::Fast:
15318 // Pass 'nest' parameter in EAX.
15319 // Must be kept in sync with X86CallingConv.td
15320 NestReg = X86::EAX;
15324 SDValue OutChains[4];
15325 SDValue Addr, Disp;
15327 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15328 DAG.getConstant(10, MVT::i32));
15329 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15331 // This is storing the opcode for MOV32ri.
15332 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
15333 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
15334 OutChains[0] = DAG.getStore(Root, dl,
15335 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
15336 Trmp, MachinePointerInfo(TrmpAddr),
15339 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15340 DAG.getConstant(1, MVT::i32));
15341 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
15342 MachinePointerInfo(TrmpAddr, 1),
15345 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
15346 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15347 DAG.getConstant(5, MVT::i32));
15348 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
15349 MachinePointerInfo(TrmpAddr, 5),
15352 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15353 DAG.getConstant(6, MVT::i32));
15354 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
15355 MachinePointerInfo(TrmpAddr, 6),
15358 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15362 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
15363 SelectionDAG &DAG) const {
15365 The rounding mode is in bits 11:10 of FPSR, and has the following
15367 00 Round to nearest
15372 FLT_ROUNDS, on the other hand, expects the following:
15379 To perform the conversion, we do:
15380 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
15383 MachineFunction &MF = DAG.getMachineFunction();
15384 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15385 unsigned StackAlignment = TFI.getStackAlignment();
15386 MVT VT = Op.getSimpleValueType();
15389 // Save FP Control Word to stack slot
15390 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
15391 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
15393 MachineMemOperand *MMO =
15394 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
15395 MachineMemOperand::MOStore, 2, 2);
15397 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
15398 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
15399 DAG.getVTList(MVT::Other),
15400 Ops, MVT::i16, MMO);
15402 // Load FP Control Word from stack slot
15403 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
15404 MachinePointerInfo(), false, false, false, 0);
15406 // Transform as necessary
15408 DAG.getNode(ISD::SRL, DL, MVT::i16,
15409 DAG.getNode(ISD::AND, DL, MVT::i16,
15410 CWD, DAG.getConstant(0x800, MVT::i16)),
15411 DAG.getConstant(11, MVT::i8));
15413 DAG.getNode(ISD::SRL, DL, MVT::i16,
15414 DAG.getNode(ISD::AND, DL, MVT::i16,
15415 CWD, DAG.getConstant(0x400, MVT::i16)),
15416 DAG.getConstant(9, MVT::i8));
15419 DAG.getNode(ISD::AND, DL, MVT::i16,
15420 DAG.getNode(ISD::ADD, DL, MVT::i16,
15421 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
15422 DAG.getConstant(1, MVT::i16)),
15423 DAG.getConstant(3, MVT::i16));
15425 return DAG.getNode((VT.getSizeInBits() < 16 ?
15426 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
15429 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
15430 MVT VT = Op.getSimpleValueType();
15432 unsigned NumBits = VT.getSizeInBits();
15435 Op = Op.getOperand(0);
15436 if (VT == MVT::i8) {
15437 // Zero extend to i32 since there is not an i8 bsr.
15439 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15442 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
15443 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15444 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15446 // If src is zero (i.e. bsr sets ZF), returns NumBits.
15449 DAG.getConstant(NumBits+NumBits-1, OpVT),
15450 DAG.getConstant(X86::COND_E, MVT::i8),
15453 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
15455 // Finally xor with NumBits-1.
15456 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15459 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15463 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
15464 MVT VT = Op.getSimpleValueType();
15466 unsigned NumBits = VT.getSizeInBits();
15469 Op = Op.getOperand(0);
15470 if (VT == MVT::i8) {
15471 // Zero extend to i32 since there is not an i8 bsr.
15473 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15476 // Issue a bsr (scan bits in reverse).
15477 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15478 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15480 // And xor with NumBits-1.
15481 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15484 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15488 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
15489 MVT VT = Op.getSimpleValueType();
15490 unsigned NumBits = VT.getSizeInBits();
15492 Op = Op.getOperand(0);
15494 // Issue a bsf (scan bits forward) which also sets EFLAGS.
15495 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
15496 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
15498 // If src is zero (i.e. bsf sets ZF), returns NumBits.
15501 DAG.getConstant(NumBits, VT),
15502 DAG.getConstant(X86::COND_E, MVT::i8),
15505 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
15508 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
15509 // ones, and then concatenate the result back.
15510 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
15511 MVT VT = Op.getSimpleValueType();
15513 assert(VT.is256BitVector() && VT.isInteger() &&
15514 "Unsupported value type for operation");
15516 unsigned NumElems = VT.getVectorNumElements();
15519 // Extract the LHS vectors
15520 SDValue LHS = Op.getOperand(0);
15521 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15522 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15524 // Extract the RHS vectors
15525 SDValue RHS = Op.getOperand(1);
15526 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15527 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15529 MVT EltVT = VT.getVectorElementType();
15530 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15532 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15533 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
15534 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
15537 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
15538 assert(Op.getSimpleValueType().is256BitVector() &&
15539 Op.getSimpleValueType().isInteger() &&
15540 "Only handle AVX 256-bit vector integer operation");
15541 return Lower256IntArith(Op, DAG);
15544 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
15545 assert(Op.getSimpleValueType().is256BitVector() &&
15546 Op.getSimpleValueType().isInteger() &&
15547 "Only handle AVX 256-bit vector integer operation");
15548 return Lower256IntArith(Op, DAG);
15551 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
15552 SelectionDAG &DAG) {
15554 MVT VT = Op.getSimpleValueType();
15556 // Decompose 256-bit ops into smaller 128-bit ops.
15557 if (VT.is256BitVector() && !Subtarget->hasInt256())
15558 return Lower256IntArith(Op, DAG);
15560 SDValue A = Op.getOperand(0);
15561 SDValue B = Op.getOperand(1);
15563 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15564 if (VT == MVT::v4i32) {
15565 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
15566 "Should not custom lower when pmuldq is available!");
15568 // Extract the odd parts.
15569 static const int UnpackMask[] = { 1, -1, 3, -1 };
15570 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
15571 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
15573 // Multiply the even parts.
15574 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15575 // Now multiply odd parts.
15576 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15578 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
15579 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
15581 // Merge the two vectors back together with a shuffle. This expands into 2
15583 static const int ShufMask[] = { 0, 4, 2, 6 };
15584 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
15587 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15588 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15590 // Ahi = psrlqi(a, 32);
15591 // Bhi = psrlqi(b, 32);
15593 // AloBlo = pmuludq(a, b);
15594 // AloBhi = pmuludq(a, Bhi);
15595 // AhiBlo = pmuludq(Ahi, b);
15597 // AloBhi = psllqi(AloBhi, 32);
15598 // AhiBlo = psllqi(AhiBlo, 32);
15599 // return AloBlo + AloBhi + AhiBlo;
15601 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
15602 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
15604 // Bit cast to 32-bit vectors for MULUDQ
15605 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15606 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15607 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
15608 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
15609 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
15610 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
15612 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
15613 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
15614 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
15616 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
15617 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
15619 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
15620 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
15623 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
15624 assert(Subtarget->isTargetWin64() && "Unexpected target");
15625 EVT VT = Op.getValueType();
15626 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
15627 "Unexpected return type for lowering");
15631 switch (Op->getOpcode()) {
15632 default: llvm_unreachable("Unexpected request for libcall!");
15633 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
15634 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
15635 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
15636 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
15637 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
15638 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
15642 SDValue InChain = DAG.getEntryNode();
15644 TargetLowering::ArgListTy Args;
15645 TargetLowering::ArgListEntry Entry;
15646 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
15647 EVT ArgVT = Op->getOperand(i).getValueType();
15648 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
15649 "Unexpected argument type for lowering");
15650 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
15651 Entry.Node = StackPtr;
15652 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
15654 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15655 Entry.Ty = PointerType::get(ArgTy,0);
15656 Entry.isSExt = false;
15657 Entry.isZExt = false;
15658 Args.push_back(Entry);
15661 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
15664 TargetLowering::CallLoweringInfo CLI(DAG);
15665 CLI.setDebugLoc(dl).setChain(InChain)
15666 .setCallee(getLibcallCallingConv(LC),
15667 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
15668 Callee, std::move(Args), 0)
15669 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
15671 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
15672 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
15675 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
15676 SelectionDAG &DAG) {
15677 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
15678 EVT VT = Op0.getValueType();
15681 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
15682 (VT == MVT::v8i32 && Subtarget->hasInt256()));
15684 // PMULxD operations multiply each even value (starting at 0) of LHS with
15685 // the related value of RHS and produce a widen result.
15686 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
15687 // => <2 x i64> <ae|cg>
15689 // In other word, to have all the results, we need to perform two PMULxD:
15690 // 1. one with the even values.
15691 // 2. one with the odd values.
15692 // To achieve #2, with need to place the odd values at an even position.
15694 // Place the odd value at an even position (basically, shift all values 1
15695 // step to the left):
15696 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
15697 // <a|b|c|d> => <b|undef|d|undef>
15698 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
15699 // <e|f|g|h> => <f|undef|h|undef>
15700 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
15702 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
15704 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
15705 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
15707 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
15708 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
15709 // => <2 x i64> <ae|cg>
15710 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
15711 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
15712 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
15713 // => <2 x i64> <bf|dh>
15714 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
15715 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
15717 // Shuffle it back into the right order.
15718 SDValue Highs, Lows;
15719 if (VT == MVT::v8i32) {
15720 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
15721 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15722 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
15723 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15725 const int HighMask[] = {1, 5, 3, 7};
15726 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15727 const int LowMask[] = {0, 4, 2, 6};
15728 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15731 // If we have a signed multiply but no PMULDQ fix up the high parts of a
15732 // unsigned multiply.
15733 if (IsSigned && !Subtarget->hasSSE41()) {
15735 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
15736 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
15737 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
15738 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
15739 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
15741 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
15742 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
15745 // The first result of MUL_LOHI is actually the low value, followed by the
15747 SDValue Ops[] = {Lows, Highs};
15748 return DAG.getMergeValues(Ops, dl);
15751 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
15752 const X86Subtarget *Subtarget) {
15753 MVT VT = Op.getSimpleValueType();
15755 SDValue R = Op.getOperand(0);
15756 SDValue Amt = Op.getOperand(1);
15758 // Optimize shl/srl/sra with constant shift amount.
15759 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
15760 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
15761 uint64_t ShiftAmt = ShiftConst->getZExtValue();
15763 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
15764 (Subtarget->hasInt256() &&
15765 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15766 (Subtarget->hasAVX512() &&
15767 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15768 if (Op.getOpcode() == ISD::SHL)
15769 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15771 if (Op.getOpcode() == ISD::SRL)
15772 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15774 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
15775 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15779 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
15780 unsigned NumElts = VT.getVectorNumElements();
15781 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
15783 if (Op.getOpcode() == ISD::SHL) {
15784 // Make a large shift.
15785 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
15787 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15788 // Zero out the rightmost bits.
15789 SmallVector<SDValue, 32> V(
15790 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), MVT::i8));
15791 return DAG.getNode(ISD::AND, dl, VT, SHL,
15792 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15794 if (Op.getOpcode() == ISD::SRL) {
15795 // Make a large shift.
15796 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
15798 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15799 // Zero out the leftmost bits.
15800 SmallVector<SDValue, 32> V(
15801 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, MVT::i8));
15802 return DAG.getNode(ISD::AND, dl, VT, SRL,
15803 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15805 if (Op.getOpcode() == ISD::SRA) {
15806 if (ShiftAmt == 7) {
15807 // R s>> 7 === R s< 0
15808 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15809 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15812 // R s>> a === ((R u>> a) ^ m) - m
15813 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15814 SmallVector<SDValue, 32> V(NumElts,
15815 DAG.getConstant(128 >> ShiftAmt, MVT::i8));
15816 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15817 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15818 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15821 llvm_unreachable("Unknown shift opcode.");
15826 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
15827 if (!Subtarget->is64Bit() &&
15828 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
15829 Amt.getOpcode() == ISD::BITCAST &&
15830 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15831 Amt = Amt.getOperand(0);
15832 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
15833 VT.getVectorNumElements();
15834 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
15835 uint64_t ShiftAmt = 0;
15836 for (unsigned i = 0; i != Ratio; ++i) {
15837 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
15841 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
15843 // Check remaining shift amounts.
15844 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
15845 uint64_t ShAmt = 0;
15846 for (unsigned j = 0; j != Ratio; ++j) {
15847 ConstantSDNode *C =
15848 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
15852 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
15854 if (ShAmt != ShiftAmt)
15857 switch (Op.getOpcode()) {
15859 llvm_unreachable("Unknown shift opcode!");
15861 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15864 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15867 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15875 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
15876 const X86Subtarget* Subtarget) {
15877 MVT VT = Op.getSimpleValueType();
15879 SDValue R = Op.getOperand(0);
15880 SDValue Amt = Op.getOperand(1);
15882 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
15883 VT == MVT::v4i32 || VT == MVT::v8i16 ||
15884 (Subtarget->hasInt256() &&
15885 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
15886 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15887 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15889 EVT EltVT = VT.getVectorElementType();
15891 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
15892 // Check if this build_vector node is doing a splat.
15893 // If so, then set BaseShAmt equal to the splat value.
15894 BaseShAmt = BV->getSplatValue();
15895 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
15896 BaseShAmt = SDValue();
15898 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
15899 Amt = Amt.getOperand(0);
15901 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
15902 if (SVN && SVN->isSplat()) {
15903 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
15904 SDValue InVec = Amt.getOperand(0);
15905 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15906 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
15907 "Unexpected shuffle index found!");
15908 BaseShAmt = InVec.getOperand(SplatIdx);
15909 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
15910 if (ConstantSDNode *C =
15911 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
15912 if (C->getZExtValue() == SplatIdx)
15913 BaseShAmt = InVec.getOperand(1);
15918 // Avoid introducing an extract element from a shuffle.
15919 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
15920 DAG.getIntPtrConstant(SplatIdx));
15924 if (BaseShAmt.getNode()) {
15925 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
15926 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
15927 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
15928 else if (EltVT.bitsLT(MVT::i32))
15929 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
15931 switch (Op.getOpcode()) {
15933 llvm_unreachable("Unknown shift opcode!");
15935 switch (VT.SimpleTy) {
15936 default: return SDValue();
15945 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
15948 switch (VT.SimpleTy) {
15949 default: return SDValue();
15956 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
15959 switch (VT.SimpleTy) {
15960 default: return SDValue();
15969 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
15975 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
15976 if (!Subtarget->is64Bit() &&
15977 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
15978 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
15979 Amt.getOpcode() == ISD::BITCAST &&
15980 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15981 Amt = Amt.getOperand(0);
15982 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
15983 VT.getVectorNumElements();
15984 std::vector<SDValue> Vals(Ratio);
15985 for (unsigned i = 0; i != Ratio; ++i)
15986 Vals[i] = Amt.getOperand(i);
15987 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
15988 for (unsigned j = 0; j != Ratio; ++j)
15989 if (Vals[j] != Amt.getOperand(i + j))
15992 switch (Op.getOpcode()) {
15994 llvm_unreachable("Unknown shift opcode!");
15996 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
15998 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
16000 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
16007 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16008 SelectionDAG &DAG) {
16009 MVT VT = Op.getSimpleValueType();
16011 SDValue R = Op.getOperand(0);
16012 SDValue Amt = Op.getOperand(1);
16015 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16016 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16018 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
16022 V = LowerScalarVariableShift(Op, DAG, Subtarget);
16026 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
16028 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
16029 if (Subtarget->hasInt256()) {
16030 if (Op.getOpcode() == ISD::SRL &&
16031 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16032 VT == MVT::v4i64 || VT == MVT::v8i32))
16034 if (Op.getOpcode() == ISD::SHL &&
16035 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16036 VT == MVT::v4i64 || VT == MVT::v8i32))
16038 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16042 // If possible, lower this packed shift into a vector multiply instead of
16043 // expanding it into a sequence of scalar shifts.
16044 // Do this only if the vector shift count is a constant build_vector.
16045 if (Op.getOpcode() == ISD::SHL &&
16046 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16047 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16048 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16049 SmallVector<SDValue, 8> Elts;
16050 EVT SVT = VT.getScalarType();
16051 unsigned SVTBits = SVT.getSizeInBits();
16052 const APInt &One = APInt(SVTBits, 1);
16053 unsigned NumElems = VT.getVectorNumElements();
16055 for (unsigned i=0; i !=NumElems; ++i) {
16056 SDValue Op = Amt->getOperand(i);
16057 if (Op->getOpcode() == ISD::UNDEF) {
16058 Elts.push_back(Op);
16062 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16063 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16064 uint64_t ShAmt = C.getZExtValue();
16065 if (ShAmt >= SVTBits) {
16066 Elts.push_back(DAG.getUNDEF(SVT));
16069 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
16071 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16072 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16075 // Lower SHL with variable shift amount.
16076 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16077 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
16079 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
16080 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16081 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16082 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16085 // If possible, lower this shift as a sequence of two shifts by
16086 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16088 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16090 // Could be rewritten as:
16091 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16093 // The advantage is that the two shifts from the example would be
16094 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16095 // the vector shift into four scalar shifts plus four pairs of vector
16097 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16098 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16099 unsigned TargetOpcode = X86ISD::MOVSS;
16100 bool CanBeSimplified;
16101 // The splat value for the first packed shift (the 'X' from the example).
16102 SDValue Amt1 = Amt->getOperand(0);
16103 // The splat value for the second packed shift (the 'Y' from the example).
16104 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16105 Amt->getOperand(2);
16107 // See if it is possible to replace this node with a sequence of
16108 // two shifts followed by a MOVSS/MOVSD
16109 if (VT == MVT::v4i32) {
16110 // Check if it is legal to use a MOVSS.
16111 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16112 Amt2 == Amt->getOperand(3);
16113 if (!CanBeSimplified) {
16114 // Otherwise, check if we can still simplify this node using a MOVSD.
16115 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16116 Amt->getOperand(2) == Amt->getOperand(3);
16117 TargetOpcode = X86ISD::MOVSD;
16118 Amt2 = Amt->getOperand(2);
16121 // Do similar checks for the case where the machine value type
16123 CanBeSimplified = Amt1 == Amt->getOperand(1);
16124 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16125 CanBeSimplified = Amt2 == Amt->getOperand(i);
16127 if (!CanBeSimplified) {
16128 TargetOpcode = X86ISD::MOVSD;
16129 CanBeSimplified = true;
16130 Amt2 = Amt->getOperand(4);
16131 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16132 CanBeSimplified = Amt1 == Amt->getOperand(i);
16133 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16134 CanBeSimplified = Amt2 == Amt->getOperand(j);
16138 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16139 isa<ConstantSDNode>(Amt2)) {
16140 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16141 EVT CastVT = MVT::v4i32;
16143 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
16144 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16146 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
16147 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16148 if (TargetOpcode == X86ISD::MOVSD)
16149 CastVT = MVT::v2i64;
16150 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16151 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16152 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16154 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16158 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16159 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
16162 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
16163 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
16165 // Turn 'a' into a mask suitable for VSELECT
16166 SDValue VSelM = DAG.getConstant(0x80, VT);
16167 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16168 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16170 SDValue CM1 = DAG.getConstant(0x0f, VT);
16171 SDValue CM2 = DAG.getConstant(0x3f, VT);
16173 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
16174 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
16175 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
16176 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16177 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16180 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16181 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16182 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16184 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
16185 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
16186 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
16187 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16188 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16191 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16192 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16193 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16195 // return VSELECT(r, r+r, a);
16196 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16197 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16201 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16202 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16203 // solution better.
16204 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16205 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16207 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16208 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16209 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16210 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16211 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16214 // Decompose 256-bit shifts into smaller 128-bit shifts.
16215 if (VT.is256BitVector()) {
16216 unsigned NumElems = VT.getVectorNumElements();
16217 MVT EltVT = VT.getVectorElementType();
16218 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16220 // Extract the two vectors
16221 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16222 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16224 // Recreate the shift amount vectors
16225 SDValue Amt1, Amt2;
16226 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16227 // Constant shift amount
16228 SmallVector<SDValue, 4> Amt1Csts;
16229 SmallVector<SDValue, 4> Amt2Csts;
16230 for (unsigned i = 0; i != NumElems/2; ++i)
16231 Amt1Csts.push_back(Amt->getOperand(i));
16232 for (unsigned i = NumElems/2; i != NumElems; ++i)
16233 Amt2Csts.push_back(Amt->getOperand(i));
16235 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16236 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16238 // Variable shift amount
16239 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16240 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16243 // Issue new vector shifts for the smaller types
16244 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16245 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16247 // Concatenate the result back
16248 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16254 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16255 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16256 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16257 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16258 // has only one use.
16259 SDNode *N = Op.getNode();
16260 SDValue LHS = N->getOperand(0);
16261 SDValue RHS = N->getOperand(1);
16262 unsigned BaseOp = 0;
16265 switch (Op.getOpcode()) {
16266 default: llvm_unreachable("Unknown ovf instruction!");
16268 // A subtract of one will be selected as a INC. Note that INC doesn't
16269 // set CF, so we can't do this for UADDO.
16270 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16272 BaseOp = X86ISD::INC;
16273 Cond = X86::COND_O;
16276 BaseOp = X86ISD::ADD;
16277 Cond = X86::COND_O;
16280 BaseOp = X86ISD::ADD;
16281 Cond = X86::COND_B;
16284 // A subtract of one will be selected as a DEC. Note that DEC doesn't
16285 // set CF, so we can't do this for USUBO.
16286 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16288 BaseOp = X86ISD::DEC;
16289 Cond = X86::COND_O;
16292 BaseOp = X86ISD::SUB;
16293 Cond = X86::COND_O;
16296 BaseOp = X86ISD::SUB;
16297 Cond = X86::COND_B;
16300 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
16301 Cond = X86::COND_O;
16303 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
16304 if (N->getValueType(0) == MVT::i8) {
16305 BaseOp = X86ISD::UMUL8;
16306 Cond = X86::COND_O;
16309 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
16311 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
16314 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16315 DAG.getConstant(X86::COND_O, MVT::i32),
16316 SDValue(Sum.getNode(), 2));
16318 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16322 // Also sets EFLAGS.
16323 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
16324 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
16327 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
16328 DAG.getConstant(Cond, MVT::i32),
16329 SDValue(Sum.getNode(), 1));
16331 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16334 /// Returns true if the operand type is exactly twice the native width, and
16335 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
16336 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
16337 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
16338 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
16339 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
16342 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
16343 else if (OpWidth == 128)
16344 return Subtarget->hasCmpxchg16b();
16349 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
16350 return needsCmpXchgNb(SI->getValueOperand()->getType());
16353 // Note: this turns large loads into lock cmpxchg8b/16b.
16354 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
16355 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
16356 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
16357 return needsCmpXchgNb(PTy->getElementType());
16360 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
16361 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
16362 const Type *MemType = AI->getType();
16364 // If the operand is too big, we must see if cmpxchg8/16b is available
16365 // and default to library calls otherwise.
16366 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
16367 return needsCmpXchgNb(MemType);
16369 AtomicRMWInst::BinOp Op = AI->getOperation();
16372 llvm_unreachable("Unknown atomic operation");
16373 case AtomicRMWInst::Xchg:
16374 case AtomicRMWInst::Add:
16375 case AtomicRMWInst::Sub:
16376 // It's better to use xadd, xsub or xchg for these in all cases.
16378 case AtomicRMWInst::Or:
16379 case AtomicRMWInst::And:
16380 case AtomicRMWInst::Xor:
16381 // If the atomicrmw's result isn't actually used, we can just add a "lock"
16382 // prefix to a normal instruction for these operations.
16383 return !AI->use_empty();
16384 case AtomicRMWInst::Nand:
16385 case AtomicRMWInst::Max:
16386 case AtomicRMWInst::Min:
16387 case AtomicRMWInst::UMax:
16388 case AtomicRMWInst::UMin:
16389 // These always require a non-trivial set of data operations on x86. We must
16390 // use a cmpxchg loop.
16395 static bool hasMFENCE(const X86Subtarget& Subtarget) {
16396 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
16397 // no-sse2). There isn't any reason to disable it if the target processor
16399 return Subtarget.hasSSE2() || Subtarget.is64Bit();
16403 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
16404 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
16405 const Type *MemType = AI->getType();
16406 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
16407 // there is no benefit in turning such RMWs into loads, and it is actually
16408 // harmful as it introduces a mfence.
16409 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
16412 auto Builder = IRBuilder<>(AI);
16413 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
16414 auto SynchScope = AI->getSynchScope();
16415 // We must restrict the ordering to avoid generating loads with Release or
16416 // ReleaseAcquire orderings.
16417 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
16418 auto Ptr = AI->getPointerOperand();
16420 // Before the load we need a fence. Here is an example lifted from
16421 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
16424 // x.store(1, relaxed);
16425 // r1 = y.fetch_add(0, release);
16427 // y.fetch_add(42, acquire);
16428 // r2 = x.load(relaxed);
16429 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
16430 // lowered to just a load without a fence. A mfence flushes the store buffer,
16431 // making the optimization clearly correct.
16432 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
16433 // otherwise, we might be able to be more agressive on relaxed idempotent
16434 // rmw. In practice, they do not look useful, so we don't try to be
16435 // especially clever.
16436 if (SynchScope == SingleThread) {
16437 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
16438 // the IR level, so we must wrap it in an intrinsic.
16440 } else if (hasMFENCE(*Subtarget)) {
16441 Function *MFence = llvm::Intrinsic::getDeclaration(M,
16442 Intrinsic::x86_sse2_mfence);
16443 Builder.CreateCall(MFence);
16445 // FIXME: it might make sense to use a locked operation here but on a
16446 // different cache-line to prevent cache-line bouncing. In practice it
16447 // is probably a small win, and x86 processors without mfence are rare
16448 // enough that we do not bother.
16452 // Finally we can emit the atomic load.
16453 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
16454 AI->getType()->getPrimitiveSizeInBits());
16455 Loaded->setAtomic(Order, SynchScope);
16456 AI->replaceAllUsesWith(Loaded);
16457 AI->eraseFromParent();
16461 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
16462 SelectionDAG &DAG) {
16464 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
16465 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
16466 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
16467 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
16469 // The only fence that needs an instruction is a sequentially-consistent
16470 // cross-thread fence.
16471 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
16472 if (hasMFENCE(*Subtarget))
16473 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
16475 SDValue Chain = Op.getOperand(0);
16476 SDValue Zero = DAG.getConstant(0, MVT::i32);
16478 DAG.getRegister(X86::ESP, MVT::i32), // Base
16479 DAG.getTargetConstant(1, MVT::i8), // Scale
16480 DAG.getRegister(0, MVT::i32), // Index
16481 DAG.getTargetConstant(0, MVT::i32), // Disp
16482 DAG.getRegister(0, MVT::i32), // Segment.
16486 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
16487 return SDValue(Res, 0);
16490 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
16491 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
16494 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
16495 SelectionDAG &DAG) {
16496 MVT T = Op.getSimpleValueType();
16500 switch(T.SimpleTy) {
16501 default: llvm_unreachable("Invalid value type!");
16502 case MVT::i8: Reg = X86::AL; size = 1; break;
16503 case MVT::i16: Reg = X86::AX; size = 2; break;
16504 case MVT::i32: Reg = X86::EAX; size = 4; break;
16506 assert(Subtarget->is64Bit() && "Node not type legal!");
16507 Reg = X86::RAX; size = 8;
16510 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
16511 Op.getOperand(2), SDValue());
16512 SDValue Ops[] = { cpIn.getValue(0),
16515 DAG.getTargetConstant(size, MVT::i8),
16516 cpIn.getValue(1) };
16517 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16518 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
16519 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
16523 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
16524 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
16525 MVT::i32, cpOut.getValue(2));
16526 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
16527 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16529 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
16530 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
16531 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
16535 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
16536 SelectionDAG &DAG) {
16537 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
16538 MVT DstVT = Op.getSimpleValueType();
16540 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
16541 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16542 if (DstVT != MVT::f64)
16543 // This conversion needs to be expanded.
16546 SDValue InVec = Op->getOperand(0);
16548 unsigned NumElts = SrcVT.getVectorNumElements();
16549 EVT SVT = SrcVT.getVectorElementType();
16551 // Widen the vector in input in the case of MVT::v2i32.
16552 // Example: from MVT::v2i32 to MVT::v4i32.
16553 SmallVector<SDValue, 16> Elts;
16554 for (unsigned i = 0, e = NumElts; i != e; ++i)
16555 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
16556 DAG.getIntPtrConstant(i)));
16558 // Explicitly mark the extra elements as Undef.
16559 Elts.append(NumElts, DAG.getUNDEF(SVT));
16561 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16562 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
16563 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
16564 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
16565 DAG.getIntPtrConstant(0));
16568 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
16569 Subtarget->hasMMX() && "Unexpected custom BITCAST");
16570 assert((DstVT == MVT::i64 ||
16571 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
16572 "Unexpected custom BITCAST");
16573 // i64 <=> MMX conversions are Legal.
16574 if (SrcVT==MVT::i64 && DstVT.isVector())
16576 if (DstVT==MVT::i64 && SrcVT.isVector())
16578 // MMX <=> MMX conversions are Legal.
16579 if (SrcVT.isVector() && DstVT.isVector())
16581 // All other conversions need to be expanded.
16585 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
16586 SelectionDAG &DAG) {
16587 SDNode *Node = Op.getNode();
16590 Op = Op.getOperand(0);
16591 EVT VT = Op.getValueType();
16592 assert((VT.is128BitVector() || VT.is256BitVector()) &&
16593 "CTPOP lowering only implemented for 128/256-bit wide vector types");
16595 unsigned NumElts = VT.getVectorNumElements();
16596 EVT EltVT = VT.getVectorElementType();
16597 unsigned Len = EltVT.getSizeInBits();
16599 // This is the vectorized version of the "best" algorithm from
16600 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
16601 // with a minor tweak to use a series of adds + shifts instead of vector
16602 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
16604 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
16605 // v8i32 => Always profitable
16607 // FIXME: There a couple of possible improvements:
16609 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
16610 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
16612 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
16613 "CTPOP not implemented for this vector element type.");
16615 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
16616 // extra legalization.
16617 bool NeedsBitcast = EltVT == MVT::i32;
16618 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
16620 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), EltVT);
16621 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), EltVT);
16622 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), EltVT);
16624 // v = v - ((v >> 1) & 0x55555555...)
16625 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));
16626 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
16627 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
16629 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
16631 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
16632 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
16634 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
16636 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
16637 if (VT != And.getValueType())
16638 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
16639 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
16641 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
16642 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
16643 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
16644 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));
16645 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
16647 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
16648 if (NeedsBitcast) {
16649 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
16650 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
16651 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
16654 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
16655 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
16656 if (VT != AndRHS.getValueType()) {
16657 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
16658 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
16660 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
16662 // v = (v + (v >> 4)) & 0x0F0F0F0F...
16663 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));
16664 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
16665 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
16666 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
16668 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
16669 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
16670 if (NeedsBitcast) {
16671 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
16672 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
16674 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
16675 if (VT != And.getValueType())
16676 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
16678 // The algorithm mentioned above uses:
16679 // v = (v * 0x01010101...) >> (Len - 8)
16681 // Change it to use vector adds + vector shifts which yield faster results on
16682 // Haswell than using vector integer multiplication.
16684 // For i32 elements:
16685 // v = v + (v >> 8)
16686 // v = v + (v >> 16)
16688 // For i64 elements:
16689 // v = v + (v >> 8)
16690 // v = v + (v >> 16)
16691 // v = v + (v >> 32)
16694 SmallVector<SDValue, 8> Csts;
16695 for (unsigned i = 8; i <= Len/2; i *= 2) {
16696 Csts.assign(NumElts, DAG.getConstant(i, EltVT));
16697 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
16698 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
16699 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
16703 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
16704 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), EltVT);
16705 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
16706 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
16707 if (NeedsBitcast) {
16708 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
16709 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
16711 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
16712 if (VT != And.getValueType())
16713 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
16718 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
16719 SDNode *Node = Op.getNode();
16721 EVT T = Node->getValueType(0);
16722 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
16723 DAG.getConstant(0, T), Node->getOperand(2));
16724 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
16725 cast<AtomicSDNode>(Node)->getMemoryVT(),
16726 Node->getOperand(0),
16727 Node->getOperand(1), negOp,
16728 cast<AtomicSDNode>(Node)->getMemOperand(),
16729 cast<AtomicSDNode>(Node)->getOrdering(),
16730 cast<AtomicSDNode>(Node)->getSynchScope());
16733 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
16734 SDNode *Node = Op.getNode();
16736 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16738 // Convert seq_cst store -> xchg
16739 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
16740 // FIXME: On 32-bit, store -> fist or movq would be more efficient
16741 // (The only way to get a 16-byte store is cmpxchg16b)
16742 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
16743 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
16744 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
16745 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
16746 cast<AtomicSDNode>(Node)->getMemoryVT(),
16747 Node->getOperand(0),
16748 Node->getOperand(1), Node->getOperand(2),
16749 cast<AtomicSDNode>(Node)->getMemOperand(),
16750 cast<AtomicSDNode>(Node)->getOrdering(),
16751 cast<AtomicSDNode>(Node)->getSynchScope());
16752 return Swap.getValue(1);
16754 // Other atomic stores have a simple pattern.
16758 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
16759 EVT VT = Op.getNode()->getSimpleValueType(0);
16761 // Let legalize expand this if it isn't a legal type yet.
16762 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
16765 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16768 bool ExtraOp = false;
16769 switch (Op.getOpcode()) {
16770 default: llvm_unreachable("Invalid code");
16771 case ISD::ADDC: Opc = X86ISD::ADD; break;
16772 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
16773 case ISD::SUBC: Opc = X86ISD::SUB; break;
16774 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
16778 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16780 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16781 Op.getOperand(1), Op.getOperand(2));
16784 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
16785 SelectionDAG &DAG) {
16786 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
16788 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
16789 // which returns the values as { float, float } (in XMM0) or
16790 // { double, double } (which is returned in XMM0, XMM1).
16792 SDValue Arg = Op.getOperand(0);
16793 EVT ArgVT = Arg.getValueType();
16794 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16796 TargetLowering::ArgListTy Args;
16797 TargetLowering::ArgListEntry Entry;
16801 Entry.isSExt = false;
16802 Entry.isZExt = false;
16803 Args.push_back(Entry);
16805 bool isF64 = ArgVT == MVT::f64;
16806 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
16807 // the small struct {f32, f32} is returned in (eax, edx). For f64,
16808 // the results are returned via SRet in memory.
16809 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
16810 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16811 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
16813 Type *RetTy = isF64
16814 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
16815 : (Type*)VectorType::get(ArgTy, 4);
16817 TargetLowering::CallLoweringInfo CLI(DAG);
16818 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
16819 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
16821 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
16824 // Returned in xmm0 and xmm1.
16825 return CallResult.first;
16827 // Returned in bits 0:31 and 32:64 xmm0.
16828 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16829 CallResult.first, DAG.getIntPtrConstant(0));
16830 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16831 CallResult.first, DAG.getIntPtrConstant(1));
16832 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
16833 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
16836 /// LowerOperation - Provide custom lowering hooks for some operations.
16838 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
16839 switch (Op.getOpcode()) {
16840 default: llvm_unreachable("Should not custom lower this!");
16841 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
16842 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
16843 return LowerCMP_SWAP(Op, Subtarget, DAG);
16844 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
16845 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
16846 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
16847 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
16848 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
16849 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
16850 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
16851 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
16852 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
16853 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
16854 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
16855 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
16856 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
16857 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
16858 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
16859 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
16860 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
16861 case ISD::SHL_PARTS:
16862 case ISD::SRA_PARTS:
16863 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
16864 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
16865 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
16866 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
16867 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
16868 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
16869 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
16870 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
16871 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
16872 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
16873 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
16875 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
16876 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
16877 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
16878 case ISD::SETCC: return LowerSETCC(Op, DAG);
16879 case ISD::SELECT: return LowerSELECT(Op, DAG);
16880 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
16881 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
16882 case ISD::VASTART: return LowerVASTART(Op, DAG);
16883 case ISD::VAARG: return LowerVAARG(Op, DAG);
16884 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
16885 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
16886 case ISD::INTRINSIC_VOID:
16887 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
16888 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
16889 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
16890 case ISD::FRAME_TO_ARGS_OFFSET:
16891 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
16892 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
16893 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
16894 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
16895 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
16896 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
16897 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
16898 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
16899 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
16900 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
16901 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
16902 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
16903 case ISD::UMUL_LOHI:
16904 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
16907 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
16913 case ISD::UMULO: return LowerXALUO(Op, DAG);
16914 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
16915 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
16919 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
16920 case ISD::ADD: return LowerADD(Op, DAG);
16921 case ISD::SUB: return LowerSUB(Op, DAG);
16922 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
16926 /// ReplaceNodeResults - Replace a node with an illegal result type
16927 /// with a new node built out of custom code.
16928 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
16929 SmallVectorImpl<SDValue>&Results,
16930 SelectionDAG &DAG) const {
16932 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16933 switch (N->getOpcode()) {
16935 llvm_unreachable("Do not know how to custom type legalize this operation!");
16936 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
16937 case X86ISD::FMINC:
16939 case X86ISD::FMAXC:
16940 case X86ISD::FMAX: {
16941 EVT VT = N->getValueType(0);
16942 if (VT != MVT::v2f32)
16943 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
16944 SDValue UNDEF = DAG.getUNDEF(VT);
16945 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
16946 N->getOperand(0), UNDEF);
16947 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
16948 N->getOperand(1), UNDEF);
16949 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
16952 case ISD::SIGN_EXTEND_INREG:
16957 // We don't want to expand or promote these.
16964 case ISD::UDIVREM: {
16965 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
16966 Results.push_back(V);
16969 case ISD::FP_TO_SINT:
16970 case ISD::FP_TO_UINT: {
16971 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
16973 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
16976 std::pair<SDValue,SDValue> Vals =
16977 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
16978 SDValue FIST = Vals.first, StackSlot = Vals.second;
16979 if (FIST.getNode()) {
16980 EVT VT = N->getValueType(0);
16981 // Return a load from the stack slot.
16982 if (StackSlot.getNode())
16983 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
16984 MachinePointerInfo(),
16985 false, false, false, 0));
16987 Results.push_back(FIST);
16991 case ISD::UINT_TO_FP: {
16992 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16993 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
16994 N->getValueType(0) != MVT::v2f32)
16996 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
16998 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17000 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17001 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17002 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17003 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17004 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17005 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17008 case ISD::FP_ROUND: {
17009 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17011 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17012 Results.push_back(V);
17015 case ISD::INTRINSIC_W_CHAIN: {
17016 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17018 default : llvm_unreachable("Do not know how to custom type "
17019 "legalize this intrinsic operation!");
17020 case Intrinsic::x86_rdtsc:
17021 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17023 case Intrinsic::x86_rdtscp:
17024 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17026 case Intrinsic::x86_rdpmc:
17027 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17030 case ISD::READCYCLECOUNTER: {
17031 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17034 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17035 EVT T = N->getValueType(0);
17036 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17037 bool Regs64bit = T == MVT::i128;
17038 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17039 SDValue cpInL, cpInH;
17040 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17041 DAG.getConstant(0, HalfT));
17042 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17043 DAG.getConstant(1, HalfT));
17044 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17045 Regs64bit ? X86::RAX : X86::EAX,
17047 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17048 Regs64bit ? X86::RDX : X86::EDX,
17049 cpInH, cpInL.getValue(1));
17050 SDValue swapInL, swapInH;
17051 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17052 DAG.getConstant(0, HalfT));
17053 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17054 DAG.getConstant(1, HalfT));
17055 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17056 Regs64bit ? X86::RBX : X86::EBX,
17057 swapInL, cpInH.getValue(1));
17058 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17059 Regs64bit ? X86::RCX : X86::ECX,
17060 swapInH, swapInL.getValue(1));
17061 SDValue Ops[] = { swapInH.getValue(0),
17063 swapInH.getValue(1) };
17064 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17065 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17066 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17067 X86ISD::LCMPXCHG8_DAG;
17068 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17069 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17070 Regs64bit ? X86::RAX : X86::EAX,
17071 HalfT, Result.getValue(1));
17072 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17073 Regs64bit ? X86::RDX : X86::EDX,
17074 HalfT, cpOutL.getValue(2));
17075 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17077 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17078 MVT::i32, cpOutH.getValue(2));
17080 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17081 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17082 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17084 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17085 Results.push_back(Success);
17086 Results.push_back(EFLAGS.getValue(1));
17089 case ISD::ATOMIC_SWAP:
17090 case ISD::ATOMIC_LOAD_ADD:
17091 case ISD::ATOMIC_LOAD_SUB:
17092 case ISD::ATOMIC_LOAD_AND:
17093 case ISD::ATOMIC_LOAD_OR:
17094 case ISD::ATOMIC_LOAD_XOR:
17095 case ISD::ATOMIC_LOAD_NAND:
17096 case ISD::ATOMIC_LOAD_MIN:
17097 case ISD::ATOMIC_LOAD_MAX:
17098 case ISD::ATOMIC_LOAD_UMIN:
17099 case ISD::ATOMIC_LOAD_UMAX:
17100 case ISD::ATOMIC_LOAD: {
17101 // Delegate to generic TypeLegalization. Situations we can really handle
17102 // should have already been dealt with by AtomicExpandPass.cpp.
17105 case ISD::BITCAST: {
17106 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17107 EVT DstVT = N->getValueType(0);
17108 EVT SrcVT = N->getOperand(0)->getValueType(0);
17110 if (SrcVT != MVT::f64 ||
17111 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17114 unsigned NumElts = DstVT.getVectorNumElements();
17115 EVT SVT = DstVT.getVectorElementType();
17116 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17117 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17118 MVT::v2f64, N->getOperand(0));
17119 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17121 if (ExperimentalVectorWideningLegalization) {
17122 // If we are legalizing vectors by widening, we already have the desired
17123 // legal vector type, just return it.
17124 Results.push_back(ToVecInt);
17128 SmallVector<SDValue, 8> Elts;
17129 for (unsigned i = 0, e = NumElts; i != e; ++i)
17130 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17131 ToVecInt, DAG.getIntPtrConstant(i)));
17133 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17138 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17140 default: return nullptr;
17141 case X86ISD::BSF: return "X86ISD::BSF";
17142 case X86ISD::BSR: return "X86ISD::BSR";
17143 case X86ISD::SHLD: return "X86ISD::SHLD";
17144 case X86ISD::SHRD: return "X86ISD::SHRD";
17145 case X86ISD::FAND: return "X86ISD::FAND";
17146 case X86ISD::FANDN: return "X86ISD::FANDN";
17147 case X86ISD::FOR: return "X86ISD::FOR";
17148 case X86ISD::FXOR: return "X86ISD::FXOR";
17149 case X86ISD::FSRL: return "X86ISD::FSRL";
17150 case X86ISD::FILD: return "X86ISD::FILD";
17151 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17152 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17153 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17154 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17155 case X86ISD::FLD: return "X86ISD::FLD";
17156 case X86ISD::FST: return "X86ISD::FST";
17157 case X86ISD::CALL: return "X86ISD::CALL";
17158 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17159 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17160 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17161 case X86ISD::BT: return "X86ISD::BT";
17162 case X86ISD::CMP: return "X86ISD::CMP";
17163 case X86ISD::COMI: return "X86ISD::COMI";
17164 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17165 case X86ISD::CMPM: return "X86ISD::CMPM";
17166 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17167 case X86ISD::SETCC: return "X86ISD::SETCC";
17168 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17169 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17170 case X86ISD::CMOV: return "X86ISD::CMOV";
17171 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17172 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17173 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17174 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17175 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17176 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17177 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17178 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17179 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17180 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17181 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17182 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17183 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17184 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17185 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17186 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17187 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
17188 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17189 case X86ISD::HADD: return "X86ISD::HADD";
17190 case X86ISD::HSUB: return "X86ISD::HSUB";
17191 case X86ISD::FHADD: return "X86ISD::FHADD";
17192 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17193 case X86ISD::UMAX: return "X86ISD::UMAX";
17194 case X86ISD::UMIN: return "X86ISD::UMIN";
17195 case X86ISD::SMAX: return "X86ISD::SMAX";
17196 case X86ISD::SMIN: return "X86ISD::SMIN";
17197 case X86ISD::FMAX: return "X86ISD::FMAX";
17198 case X86ISD::FMIN: return "X86ISD::FMIN";
17199 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17200 case X86ISD::FMINC: return "X86ISD::FMINC";
17201 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17202 case X86ISD::FRCP: return "X86ISD::FRCP";
17203 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17204 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17205 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17206 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17207 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17208 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17209 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17210 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17211 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17212 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17213 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17214 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17215 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17216 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17217 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17218 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17219 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17220 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17221 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17222 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17223 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17224 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17225 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17226 case X86ISD::VSHL: return "X86ISD::VSHL";
17227 case X86ISD::VSRL: return "X86ISD::VSRL";
17228 case X86ISD::VSRA: return "X86ISD::VSRA";
17229 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17230 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17231 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17232 case X86ISD::CMPP: return "X86ISD::CMPP";
17233 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17234 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17235 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17236 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17237 case X86ISD::ADD: return "X86ISD::ADD";
17238 case X86ISD::SUB: return "X86ISD::SUB";
17239 case X86ISD::ADC: return "X86ISD::ADC";
17240 case X86ISD::SBB: return "X86ISD::SBB";
17241 case X86ISD::SMUL: return "X86ISD::SMUL";
17242 case X86ISD::UMUL: return "X86ISD::UMUL";
17243 case X86ISD::SMUL8: return "X86ISD::SMUL8";
17244 case X86ISD::UMUL8: return "X86ISD::UMUL8";
17245 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
17246 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
17247 case X86ISD::INC: return "X86ISD::INC";
17248 case X86ISD::DEC: return "X86ISD::DEC";
17249 case X86ISD::OR: return "X86ISD::OR";
17250 case X86ISD::XOR: return "X86ISD::XOR";
17251 case X86ISD::AND: return "X86ISD::AND";
17252 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17253 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17254 case X86ISD::PTEST: return "X86ISD::PTEST";
17255 case X86ISD::TESTP: return "X86ISD::TESTP";
17256 case X86ISD::TESTM: return "X86ISD::TESTM";
17257 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17258 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17259 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17260 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17261 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17262 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17263 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17264 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17265 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17266 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17267 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17268 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17269 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17270 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17271 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17272 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17273 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17274 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17275 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17276 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17277 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17278 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17279 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17280 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
17281 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17282 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
17283 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17284 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17285 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17286 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17287 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17288 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17289 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17290 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17291 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17292 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17293 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17294 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17295 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17296 case X86ISD::SAHF: return "X86ISD::SAHF";
17297 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17298 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17299 case X86ISD::FMADD: return "X86ISD::FMADD";
17300 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17301 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17302 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17303 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17304 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17305 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17306 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17307 case X86ISD::XTEST: return "X86ISD::XTEST";
17308 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
17309 case X86ISD::EXPAND: return "X86ISD::EXPAND";
17310 case X86ISD::SELECT: return "X86ISD::SELECT";
17311 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
17312 case X86ISD::RCP28: return "X86ISD::RCP28";
17313 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
17314 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
17315 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
17316 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
17317 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
17321 // isLegalAddressingMode - Return true if the addressing mode represented
17322 // by AM is legal for this target, for a load/store of the specified type.
17323 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
17325 // X86 supports extremely general addressing modes.
17326 CodeModel::Model M = getTargetMachine().getCodeModel();
17327 Reloc::Model R = getTargetMachine().getRelocationModel();
17329 // X86 allows a sign-extended 32-bit immediate field as a displacement.
17330 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
17335 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
17337 // If a reference to this global requires an extra load, we can't fold it.
17338 if (isGlobalStubReference(GVFlags))
17341 // If BaseGV requires a register for the PIC base, we cannot also have a
17342 // BaseReg specified.
17343 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
17346 // If lower 4G is not available, then we must use rip-relative addressing.
17347 if ((M != CodeModel::Small || R != Reloc::Static) &&
17348 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
17352 switch (AM.Scale) {
17358 // These scales always work.
17363 // These scales are formed with basereg+scalereg. Only accept if there is
17368 default: // Other stuff never works.
17375 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
17376 unsigned Bits = Ty->getScalarSizeInBits();
17378 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
17379 // particularly cheaper than those without.
17383 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
17384 // variable shifts just as cheap as scalar ones.
17385 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
17388 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
17389 // fully general vector.
17393 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
17394 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17396 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
17397 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
17398 return NumBits1 > NumBits2;
17401 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
17402 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17405 if (!isTypeLegal(EVT::getEVT(Ty1)))
17408 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
17410 // Assuming the caller doesn't have a zeroext or signext return parameter,
17411 // truncation all the way down to i1 is valid.
17415 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
17416 return isInt<32>(Imm);
17419 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
17420 // Can also use sub to handle negated immediates.
17421 return isInt<32>(Imm);
17424 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
17425 if (!VT1.isInteger() || !VT2.isInteger())
17427 unsigned NumBits1 = VT1.getSizeInBits();
17428 unsigned NumBits2 = VT2.getSizeInBits();
17429 return NumBits1 > NumBits2;
17432 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
17433 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17434 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
17437 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
17438 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17439 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
17442 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
17443 EVT VT1 = Val.getValueType();
17444 if (isZExtFree(VT1, VT2))
17447 if (Val.getOpcode() != ISD::LOAD)
17450 if (!VT1.isSimple() || !VT1.isInteger() ||
17451 !VT2.isSimple() || !VT2.isInteger())
17454 switch (VT1.getSimpleVT().SimpleTy) {
17459 // X86 has 8, 16, and 32-bit zero-extending loads.
17466 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
17469 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
17470 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
17473 VT = VT.getScalarType();
17475 if (!VT.isSimple())
17478 switch (VT.getSimpleVT().SimpleTy) {
17489 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
17490 // i16 instructions are longer (0x66 prefix) and potentially slower.
17491 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
17494 /// isShuffleMaskLegal - Targets can use this to indicate that they only
17495 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
17496 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
17497 /// are assumed to be legal.
17499 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
17501 if (!VT.isSimple())
17504 // Very little shuffling can be done for 64-bit vectors right now.
17505 if (VT.getSizeInBits() == 64)
17508 // We only care that the types being shuffled are legal. The lowering can
17509 // handle any possible shuffle mask that results.
17510 return isTypeLegal(VT.getSimpleVT());
17514 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
17516 // Just delegate to the generic legality, clear masks aren't special.
17517 return isShuffleMaskLegal(Mask, VT);
17520 //===----------------------------------------------------------------------===//
17521 // X86 Scheduler Hooks
17522 //===----------------------------------------------------------------------===//
17524 /// Utility function to emit xbegin specifying the start of an RTM region.
17525 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
17526 const TargetInstrInfo *TII) {
17527 DebugLoc DL = MI->getDebugLoc();
17529 const BasicBlock *BB = MBB->getBasicBlock();
17530 MachineFunction::iterator I = MBB;
17533 // For the v = xbegin(), we generate
17544 MachineBasicBlock *thisMBB = MBB;
17545 MachineFunction *MF = MBB->getParent();
17546 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17547 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17548 MF->insert(I, mainMBB);
17549 MF->insert(I, sinkMBB);
17551 // Transfer the remainder of BB and its successor edges to sinkMBB.
17552 sinkMBB->splice(sinkMBB->begin(), MBB,
17553 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17554 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17558 // # fallthrough to mainMBB
17559 // # abortion to sinkMBB
17560 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
17561 thisMBB->addSuccessor(mainMBB);
17562 thisMBB->addSuccessor(sinkMBB);
17566 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
17567 mainMBB->addSuccessor(sinkMBB);
17570 // EAX is live into the sinkMBB
17571 sinkMBB->addLiveIn(X86::EAX);
17572 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17573 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17576 MI->eraseFromParent();
17580 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
17581 // or XMM0_V32I8 in AVX all of this code can be replaced with that
17582 // in the .td file.
17583 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
17584 const TargetInstrInfo *TII) {
17586 switch (MI->getOpcode()) {
17587 default: llvm_unreachable("illegal opcode!");
17588 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
17589 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
17590 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
17591 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
17592 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
17593 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
17594 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
17595 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
17598 DebugLoc dl = MI->getDebugLoc();
17599 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17601 unsigned NumArgs = MI->getNumOperands();
17602 for (unsigned i = 1; i < NumArgs; ++i) {
17603 MachineOperand &Op = MI->getOperand(i);
17604 if (!(Op.isReg() && Op.isImplicit()))
17605 MIB.addOperand(Op);
17607 if (MI->hasOneMemOperand())
17608 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17610 BuildMI(*BB, MI, dl,
17611 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17612 .addReg(X86::XMM0);
17614 MI->eraseFromParent();
17618 // FIXME: Custom handling because TableGen doesn't support multiple implicit
17619 // defs in an instruction pattern
17620 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
17621 const TargetInstrInfo *TII) {
17623 switch (MI->getOpcode()) {
17624 default: llvm_unreachable("illegal opcode!");
17625 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
17626 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
17627 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
17628 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
17629 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
17630 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
17631 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
17632 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
17635 DebugLoc dl = MI->getDebugLoc();
17636 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17638 unsigned NumArgs = MI->getNumOperands(); // remove the results
17639 for (unsigned i = 1; i < NumArgs; ++i) {
17640 MachineOperand &Op = MI->getOperand(i);
17641 if (!(Op.isReg() && Op.isImplicit()))
17642 MIB.addOperand(Op);
17644 if (MI->hasOneMemOperand())
17645 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17647 BuildMI(*BB, MI, dl,
17648 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17651 MI->eraseFromParent();
17655 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
17656 const X86Subtarget *Subtarget) {
17657 DebugLoc dl = MI->getDebugLoc();
17658 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
17659 // Address into RAX/EAX, other two args into ECX, EDX.
17660 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
17661 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
17662 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
17663 for (int i = 0; i < X86::AddrNumOperands; ++i)
17664 MIB.addOperand(MI->getOperand(i));
17666 unsigned ValOps = X86::AddrNumOperands;
17667 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
17668 .addReg(MI->getOperand(ValOps).getReg());
17669 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
17670 .addReg(MI->getOperand(ValOps+1).getReg());
17672 // The instruction doesn't actually take any operands though.
17673 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
17675 MI->eraseFromParent(); // The pseudo is gone now.
17679 MachineBasicBlock *
17680 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
17681 MachineBasicBlock *MBB) const {
17682 // Emit va_arg instruction on X86-64.
17684 // Operands to this pseudo-instruction:
17685 // 0 ) Output : destination address (reg)
17686 // 1-5) Input : va_list address (addr, i64mem)
17687 // 6 ) ArgSize : Size (in bytes) of vararg type
17688 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
17689 // 8 ) Align : Alignment of type
17690 // 9 ) EFLAGS (implicit-def)
17692 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
17693 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
17695 unsigned DestReg = MI->getOperand(0).getReg();
17696 MachineOperand &Base = MI->getOperand(1);
17697 MachineOperand &Scale = MI->getOperand(2);
17698 MachineOperand &Index = MI->getOperand(3);
17699 MachineOperand &Disp = MI->getOperand(4);
17700 MachineOperand &Segment = MI->getOperand(5);
17701 unsigned ArgSize = MI->getOperand(6).getImm();
17702 unsigned ArgMode = MI->getOperand(7).getImm();
17703 unsigned Align = MI->getOperand(8).getImm();
17705 // Memory Reference
17706 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
17707 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17708 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17710 // Machine Information
17711 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
17712 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
17713 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
17714 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
17715 DebugLoc DL = MI->getDebugLoc();
17717 // struct va_list {
17720 // i64 overflow_area (address)
17721 // i64 reg_save_area (address)
17723 // sizeof(va_list) = 24
17724 // alignment(va_list) = 8
17726 unsigned TotalNumIntRegs = 6;
17727 unsigned TotalNumXMMRegs = 8;
17728 bool UseGPOffset = (ArgMode == 1);
17729 bool UseFPOffset = (ArgMode == 2);
17730 unsigned MaxOffset = TotalNumIntRegs * 8 +
17731 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
17733 /* Align ArgSize to a multiple of 8 */
17734 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
17735 bool NeedsAlign = (Align > 8);
17737 MachineBasicBlock *thisMBB = MBB;
17738 MachineBasicBlock *overflowMBB;
17739 MachineBasicBlock *offsetMBB;
17740 MachineBasicBlock *endMBB;
17742 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
17743 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
17744 unsigned OffsetReg = 0;
17746 if (!UseGPOffset && !UseFPOffset) {
17747 // If we only pull from the overflow region, we don't create a branch.
17748 // We don't need to alter control flow.
17749 OffsetDestReg = 0; // unused
17750 OverflowDestReg = DestReg;
17752 offsetMBB = nullptr;
17753 overflowMBB = thisMBB;
17756 // First emit code to check if gp_offset (or fp_offset) is below the bound.
17757 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
17758 // If not, pull from overflow_area. (branch to overflowMBB)
17763 // offsetMBB overflowMBB
17768 // Registers for the PHI in endMBB
17769 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
17770 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
17772 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17773 MachineFunction *MF = MBB->getParent();
17774 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17775 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17776 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17778 MachineFunction::iterator MBBIter = MBB;
17781 // Insert the new basic blocks
17782 MF->insert(MBBIter, offsetMBB);
17783 MF->insert(MBBIter, overflowMBB);
17784 MF->insert(MBBIter, endMBB);
17786 // Transfer the remainder of MBB and its successor edges to endMBB.
17787 endMBB->splice(endMBB->begin(), thisMBB,
17788 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
17789 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
17791 // Make offsetMBB and overflowMBB successors of thisMBB
17792 thisMBB->addSuccessor(offsetMBB);
17793 thisMBB->addSuccessor(overflowMBB);
17795 // endMBB is a successor of both offsetMBB and overflowMBB
17796 offsetMBB->addSuccessor(endMBB);
17797 overflowMBB->addSuccessor(endMBB);
17799 // Load the offset value into a register
17800 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17801 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
17805 .addDisp(Disp, UseFPOffset ? 4 : 0)
17806 .addOperand(Segment)
17807 .setMemRefs(MMOBegin, MMOEnd);
17809 // Check if there is enough room left to pull this argument.
17810 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
17812 .addImm(MaxOffset + 8 - ArgSizeA8);
17814 // Branch to "overflowMBB" if offset >= max
17815 // Fall through to "offsetMBB" otherwise
17816 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
17817 .addMBB(overflowMBB);
17820 // In offsetMBB, emit code to use the reg_save_area.
17822 assert(OffsetReg != 0);
17824 // Read the reg_save_area address.
17825 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
17826 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
17831 .addOperand(Segment)
17832 .setMemRefs(MMOBegin, MMOEnd);
17834 // Zero-extend the offset
17835 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
17836 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
17839 .addImm(X86::sub_32bit);
17841 // Add the offset to the reg_save_area to get the final address.
17842 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
17843 .addReg(OffsetReg64)
17844 .addReg(RegSaveReg);
17846 // Compute the offset for the next argument
17847 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17848 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
17850 .addImm(UseFPOffset ? 16 : 8);
17852 // Store it back into the va_list.
17853 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
17857 .addDisp(Disp, UseFPOffset ? 4 : 0)
17858 .addOperand(Segment)
17859 .addReg(NextOffsetReg)
17860 .setMemRefs(MMOBegin, MMOEnd);
17863 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
17868 // Emit code to use overflow area
17871 // Load the overflow_area address into a register.
17872 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
17873 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
17878 .addOperand(Segment)
17879 .setMemRefs(MMOBegin, MMOEnd);
17881 // If we need to align it, do so. Otherwise, just copy the address
17882 // to OverflowDestReg.
17884 // Align the overflow address
17885 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
17886 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
17888 // aligned_addr = (addr + (align-1)) & ~(align-1)
17889 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
17890 .addReg(OverflowAddrReg)
17893 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
17895 .addImm(~(uint64_t)(Align-1));
17897 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
17898 .addReg(OverflowAddrReg);
17901 // Compute the next overflow address after this argument.
17902 // (the overflow address should be kept 8-byte aligned)
17903 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
17904 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
17905 .addReg(OverflowDestReg)
17906 .addImm(ArgSizeA8);
17908 // Store the new overflow address.
17909 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
17914 .addOperand(Segment)
17915 .addReg(NextAddrReg)
17916 .setMemRefs(MMOBegin, MMOEnd);
17918 // If we branched, emit the PHI to the front of endMBB.
17920 BuildMI(*endMBB, endMBB->begin(), DL,
17921 TII->get(X86::PHI), DestReg)
17922 .addReg(OffsetDestReg).addMBB(offsetMBB)
17923 .addReg(OverflowDestReg).addMBB(overflowMBB);
17926 // Erase the pseudo instruction
17927 MI->eraseFromParent();
17932 MachineBasicBlock *
17933 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
17935 MachineBasicBlock *MBB) const {
17936 // Emit code to save XMM registers to the stack. The ABI says that the
17937 // number of registers to save is given in %al, so it's theoretically
17938 // possible to do an indirect jump trick to avoid saving all of them,
17939 // however this code takes a simpler approach and just executes all
17940 // of the stores if %al is non-zero. It's less code, and it's probably
17941 // easier on the hardware branch predictor, and stores aren't all that
17942 // expensive anyway.
17944 // Create the new basic blocks. One block contains all the XMM stores,
17945 // and one block is the final destination regardless of whether any
17946 // stores were performed.
17947 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17948 MachineFunction *F = MBB->getParent();
17949 MachineFunction::iterator MBBIter = MBB;
17951 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
17952 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
17953 F->insert(MBBIter, XMMSaveMBB);
17954 F->insert(MBBIter, EndMBB);
17956 // Transfer the remainder of MBB and its successor edges to EndMBB.
17957 EndMBB->splice(EndMBB->begin(), MBB,
17958 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17959 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
17961 // The original block will now fall through to the XMM save block.
17962 MBB->addSuccessor(XMMSaveMBB);
17963 // The XMMSaveMBB will fall through to the end block.
17964 XMMSaveMBB->addSuccessor(EndMBB);
17966 // Now add the instructions.
17967 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
17968 DebugLoc DL = MI->getDebugLoc();
17970 unsigned CountReg = MI->getOperand(0).getReg();
17971 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
17972 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
17974 if (!Subtarget->isTargetWin64()) {
17975 // If %al is 0, branch around the XMM save block.
17976 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
17977 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
17978 MBB->addSuccessor(EndMBB);
17981 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
17982 // that was just emitted, but clearly shouldn't be "saved".
17983 assert((MI->getNumOperands() <= 3 ||
17984 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
17985 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
17986 && "Expected last argument to be EFLAGS");
17987 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
17988 // In the XMM save block, save all the XMM argument registers.
17989 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
17990 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
17991 MachineMemOperand *MMO =
17992 F->getMachineMemOperand(
17993 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
17994 MachineMemOperand::MOStore,
17995 /*Size=*/16, /*Align=*/16);
17996 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
17997 .addFrameIndex(RegSaveFrameIndex)
17998 .addImm(/*Scale=*/1)
17999 .addReg(/*IndexReg=*/0)
18000 .addImm(/*Disp=*/Offset)
18001 .addReg(/*Segment=*/0)
18002 .addReg(MI->getOperand(i).getReg())
18003 .addMemOperand(MMO);
18006 MI->eraseFromParent(); // The pseudo instruction is gone now.
18011 // The EFLAGS operand of SelectItr might be missing a kill marker
18012 // because there were multiple uses of EFLAGS, and ISel didn't know
18013 // which to mark. Figure out whether SelectItr should have had a
18014 // kill marker, and set it if it should. Returns the correct kill
18016 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18017 MachineBasicBlock* BB,
18018 const TargetRegisterInfo* TRI) {
18019 // Scan forward through BB for a use/def of EFLAGS.
18020 MachineBasicBlock::iterator miI(std::next(SelectItr));
18021 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18022 const MachineInstr& mi = *miI;
18023 if (mi.readsRegister(X86::EFLAGS))
18025 if (mi.definesRegister(X86::EFLAGS))
18026 break; // Should have kill-flag - update below.
18029 // If we hit the end of the block, check whether EFLAGS is live into a
18031 if (miI == BB->end()) {
18032 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18033 sEnd = BB->succ_end();
18034 sItr != sEnd; ++sItr) {
18035 MachineBasicBlock* succ = *sItr;
18036 if (succ->isLiveIn(X86::EFLAGS))
18041 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18042 // out. SelectMI should have a kill flag on EFLAGS.
18043 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18047 MachineBasicBlock *
18048 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18049 MachineBasicBlock *BB) const {
18050 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18051 DebugLoc DL = MI->getDebugLoc();
18053 // To "insert" a SELECT_CC instruction, we actually have to insert the
18054 // diamond control-flow pattern. The incoming instruction knows the
18055 // destination vreg to set, the condition code register to branch on, the
18056 // true/false values to select between, and a branch opcode to use.
18057 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18058 MachineFunction::iterator It = BB;
18064 // cmpTY ccX, r1, r2
18066 // fallthrough --> copy0MBB
18067 MachineBasicBlock *thisMBB = BB;
18068 MachineFunction *F = BB->getParent();
18069 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18070 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18071 F->insert(It, copy0MBB);
18072 F->insert(It, sinkMBB);
18074 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18075 // live into the sink and copy blocks.
18076 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
18077 if (!MI->killsRegister(X86::EFLAGS) &&
18078 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
18079 copy0MBB->addLiveIn(X86::EFLAGS);
18080 sinkMBB->addLiveIn(X86::EFLAGS);
18083 // Transfer the remainder of BB and its successor edges to sinkMBB.
18084 sinkMBB->splice(sinkMBB->begin(), BB,
18085 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18086 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18088 // Add the true and fallthrough blocks as its successors.
18089 BB->addSuccessor(copy0MBB);
18090 BB->addSuccessor(sinkMBB);
18092 // Create the conditional branch instruction.
18094 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18095 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18098 // %FalseValue = ...
18099 // # fallthrough to sinkMBB
18100 copy0MBB->addSuccessor(sinkMBB);
18103 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18105 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18106 TII->get(X86::PHI), MI->getOperand(0).getReg())
18107 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18108 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18110 MI->eraseFromParent(); // The pseudo instruction is gone now.
18114 MachineBasicBlock *
18115 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
18116 MachineBasicBlock *BB) const {
18117 MachineFunction *MF = BB->getParent();
18118 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18119 DebugLoc DL = MI->getDebugLoc();
18120 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18122 assert(MF->shouldSplitStack());
18124 const bool Is64Bit = Subtarget->is64Bit();
18125 const bool IsLP64 = Subtarget->isTarget64BitLP64();
18127 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18128 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
18131 // ... [Till the alloca]
18132 // If stacklet is not large enough, jump to mallocMBB
18135 // Allocate by subtracting from RSP
18136 // Jump to continueMBB
18139 // Allocate by call to runtime
18143 // [rest of original BB]
18146 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18147 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18148 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18150 MachineRegisterInfo &MRI = MF->getRegInfo();
18151 const TargetRegisterClass *AddrRegClass =
18152 getRegClassFor(getPointerTy());
18154 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18155 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18156 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18157 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18158 sizeVReg = MI->getOperand(1).getReg(),
18159 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
18161 MachineFunction::iterator MBBIter = BB;
18164 MF->insert(MBBIter, bumpMBB);
18165 MF->insert(MBBIter, mallocMBB);
18166 MF->insert(MBBIter, continueMBB);
18168 continueMBB->splice(continueMBB->begin(), BB,
18169 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18170 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18172 // Add code to the main basic block to check if the stack limit has been hit,
18173 // and if so, jump to mallocMBB otherwise to bumpMBB.
18174 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18175 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18176 .addReg(tmpSPVReg).addReg(sizeVReg);
18177 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
18178 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18179 .addReg(SPLimitVReg);
18180 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
18182 // bumpMBB simply decreases the stack pointer, since we know the current
18183 // stacklet has enough space.
18184 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18185 .addReg(SPLimitVReg);
18186 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18187 .addReg(SPLimitVReg);
18188 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
18190 // Calls into a routine in libgcc to allocate more space from the heap.
18191 const uint32_t *RegMask =
18192 Subtarget->getRegisterInfo()->getCallPreservedMask(CallingConv::C);
18194 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18196 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18197 .addExternalSymbol("__morestack_allocate_stack_space")
18198 .addRegMask(RegMask)
18199 .addReg(X86::RDI, RegState::Implicit)
18200 .addReg(X86::RAX, RegState::ImplicitDefine);
18201 } else if (Is64Bit) {
18202 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
18204 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18205 .addExternalSymbol("__morestack_allocate_stack_space")
18206 .addRegMask(RegMask)
18207 .addReg(X86::EDI, RegState::Implicit)
18208 .addReg(X86::EAX, RegState::ImplicitDefine);
18210 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
18212 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
18213 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
18214 .addExternalSymbol("__morestack_allocate_stack_space")
18215 .addRegMask(RegMask)
18216 .addReg(X86::EAX, RegState::ImplicitDefine);
18220 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
18223 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
18224 .addReg(IsLP64 ? X86::RAX : X86::EAX);
18225 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
18227 // Set up the CFG correctly.
18228 BB->addSuccessor(bumpMBB);
18229 BB->addSuccessor(mallocMBB);
18230 mallocMBB->addSuccessor(continueMBB);
18231 bumpMBB->addSuccessor(continueMBB);
18233 // Take care of the PHI nodes.
18234 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
18235 MI->getOperand(0).getReg())
18236 .addReg(mallocPtrVReg).addMBB(mallocMBB)
18237 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
18239 // Delete the original pseudo instruction.
18240 MI->eraseFromParent();
18243 return continueMBB;
18246 MachineBasicBlock *
18247 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
18248 MachineBasicBlock *BB) const {
18249 DebugLoc DL = MI->getDebugLoc();
18251 assert(!Subtarget->isTargetMachO());
18253 X86FrameLowering::emitStackProbeCall(*BB->getParent(), *BB, MI, DL);
18255 MI->eraseFromParent(); // The pseudo instruction is gone now.
18259 MachineBasicBlock *
18260 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
18261 MachineBasicBlock *BB) const {
18262 // This is pretty easy. We're taking the value that we received from
18263 // our load from the relocation, sticking it in either RDI (x86-64)
18264 // or EAX and doing an indirect call. The return value will then
18265 // be in the normal return register.
18266 MachineFunction *F = BB->getParent();
18267 const X86InstrInfo *TII = Subtarget->getInstrInfo();
18268 DebugLoc DL = MI->getDebugLoc();
18270 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
18271 assert(MI->getOperand(3).isGlobal() && "This should be a global");
18273 // Get a register mask for the lowered call.
18274 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
18275 // proper register mask.
18276 const uint32_t *RegMask =
18277 Subtarget->getRegisterInfo()->getCallPreservedMask(CallingConv::C);
18278 if (Subtarget->is64Bit()) {
18279 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18280 TII->get(X86::MOV64rm), X86::RDI)
18282 .addImm(0).addReg(0)
18283 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18284 MI->getOperand(3).getTargetFlags())
18286 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
18287 addDirectMem(MIB, X86::RDI);
18288 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
18289 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
18290 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18291 TII->get(X86::MOV32rm), X86::EAX)
18293 .addImm(0).addReg(0)
18294 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18295 MI->getOperand(3).getTargetFlags())
18297 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18298 addDirectMem(MIB, X86::EAX);
18299 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18301 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18302 TII->get(X86::MOV32rm), X86::EAX)
18303 .addReg(TII->getGlobalBaseReg(F))
18304 .addImm(0).addReg(0)
18305 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18306 MI->getOperand(3).getTargetFlags())
18308 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18309 addDirectMem(MIB, X86::EAX);
18310 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18313 MI->eraseFromParent(); // The pseudo instruction is gone now.
18317 MachineBasicBlock *
18318 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
18319 MachineBasicBlock *MBB) const {
18320 DebugLoc DL = MI->getDebugLoc();
18321 MachineFunction *MF = MBB->getParent();
18322 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18323 MachineRegisterInfo &MRI = MF->getRegInfo();
18325 const BasicBlock *BB = MBB->getBasicBlock();
18326 MachineFunction::iterator I = MBB;
18329 // Memory Reference
18330 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18331 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18334 unsigned MemOpndSlot = 0;
18336 unsigned CurOp = 0;
18338 DstReg = MI->getOperand(CurOp++).getReg();
18339 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
18340 assert(RC->hasType(MVT::i32) && "Invalid destination!");
18341 unsigned mainDstReg = MRI.createVirtualRegister(RC);
18342 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
18344 MemOpndSlot = CurOp;
18346 MVT PVT = getPointerTy();
18347 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18348 "Invalid Pointer Size!");
18350 // For v = setjmp(buf), we generate
18353 // buf[LabelOffset] = restoreMBB
18354 // SjLjSetup restoreMBB
18360 // v = phi(main, restore)
18363 // if base pointer being used, load it from frame
18366 MachineBasicBlock *thisMBB = MBB;
18367 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18368 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18369 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
18370 MF->insert(I, mainMBB);
18371 MF->insert(I, sinkMBB);
18372 MF->push_back(restoreMBB);
18374 MachineInstrBuilder MIB;
18376 // Transfer the remainder of BB and its successor edges to sinkMBB.
18377 sinkMBB->splice(sinkMBB->begin(), MBB,
18378 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18379 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18382 unsigned PtrStoreOpc = 0;
18383 unsigned LabelReg = 0;
18384 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18385 Reloc::Model RM = MF->getTarget().getRelocationModel();
18386 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
18387 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
18389 // Prepare IP either in reg or imm.
18390 if (!UseImmLabel) {
18391 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
18392 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
18393 LabelReg = MRI.createVirtualRegister(PtrRC);
18394 if (Subtarget->is64Bit()) {
18395 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
18399 .addMBB(restoreMBB)
18402 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
18403 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
18404 .addReg(XII->getGlobalBaseReg(MF))
18407 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
18411 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
18413 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
18414 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18415 if (i == X86::AddrDisp)
18416 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
18418 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
18421 MIB.addReg(LabelReg);
18423 MIB.addMBB(restoreMBB);
18424 MIB.setMemRefs(MMOBegin, MMOEnd);
18426 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
18427 .addMBB(restoreMBB);
18429 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
18430 MIB.addRegMask(RegInfo->getNoPreservedMask());
18431 thisMBB->addSuccessor(mainMBB);
18432 thisMBB->addSuccessor(restoreMBB);
18436 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
18437 mainMBB->addSuccessor(sinkMBB);
18440 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18441 TII->get(X86::PHI), DstReg)
18442 .addReg(mainDstReg).addMBB(mainMBB)
18443 .addReg(restoreDstReg).addMBB(restoreMBB);
18446 if (RegInfo->hasBasePointer(*MF)) {
18447 const bool Uses64BitFramePtr =
18448 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
18449 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
18450 X86FI->setRestoreBasePointer(MF);
18451 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
18452 unsigned BasePtr = RegInfo->getBaseRegister();
18453 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
18454 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
18455 FramePtr, true, X86FI->getRestoreBasePointerOffset())
18456 .setMIFlag(MachineInstr::FrameSetup);
18458 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
18459 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
18460 restoreMBB->addSuccessor(sinkMBB);
18462 MI->eraseFromParent();
18466 MachineBasicBlock *
18467 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
18468 MachineBasicBlock *MBB) const {
18469 DebugLoc DL = MI->getDebugLoc();
18470 MachineFunction *MF = MBB->getParent();
18471 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18472 MachineRegisterInfo &MRI = MF->getRegInfo();
18474 // Memory Reference
18475 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18476 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18478 MVT PVT = getPointerTy();
18479 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18480 "Invalid Pointer Size!");
18482 const TargetRegisterClass *RC =
18483 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
18484 unsigned Tmp = MRI.createVirtualRegister(RC);
18485 // Since FP is only updated here but NOT referenced, it's treated as GPR.
18486 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
18487 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
18488 unsigned SP = RegInfo->getStackRegister();
18490 MachineInstrBuilder MIB;
18492 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18493 const int64_t SPOffset = 2 * PVT.getStoreSize();
18495 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
18496 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
18499 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
18500 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
18501 MIB.addOperand(MI->getOperand(i));
18502 MIB.setMemRefs(MMOBegin, MMOEnd);
18504 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
18505 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18506 if (i == X86::AddrDisp)
18507 MIB.addDisp(MI->getOperand(i), LabelOffset);
18509 MIB.addOperand(MI->getOperand(i));
18511 MIB.setMemRefs(MMOBegin, MMOEnd);
18513 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
18514 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18515 if (i == X86::AddrDisp)
18516 MIB.addDisp(MI->getOperand(i), SPOffset);
18518 MIB.addOperand(MI->getOperand(i));
18520 MIB.setMemRefs(MMOBegin, MMOEnd);
18522 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
18524 MI->eraseFromParent();
18528 // Replace 213-type (isel default) FMA3 instructions with 231-type for
18529 // accumulator loops. Writing back to the accumulator allows the coalescer
18530 // to remove extra copies in the loop.
18531 MachineBasicBlock *
18532 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
18533 MachineBasicBlock *MBB) const {
18534 MachineOperand &AddendOp = MI->getOperand(3);
18536 // Bail out early if the addend isn't a register - we can't switch these.
18537 if (!AddendOp.isReg())
18540 MachineFunction &MF = *MBB->getParent();
18541 MachineRegisterInfo &MRI = MF.getRegInfo();
18543 // Check whether the addend is defined by a PHI:
18544 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
18545 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
18546 if (!AddendDef.isPHI())
18549 // Look for the following pattern:
18551 // %addend = phi [%entry, 0], [%loop, %result]
18553 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
18557 // %addend = phi [%entry, 0], [%loop, %result]
18559 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
18561 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
18562 assert(AddendDef.getOperand(i).isReg());
18563 MachineOperand PHISrcOp = AddendDef.getOperand(i);
18564 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
18565 if (&PHISrcInst == MI) {
18566 // Found a matching instruction.
18567 unsigned NewFMAOpc = 0;
18568 switch (MI->getOpcode()) {
18569 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
18570 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
18571 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
18572 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
18573 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
18574 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
18575 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
18576 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
18577 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
18578 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
18579 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
18580 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
18581 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
18582 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
18583 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
18584 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
18585 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
18586 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
18587 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
18588 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
18590 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
18591 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
18592 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
18593 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
18594 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
18595 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
18596 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
18597 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
18598 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
18599 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
18600 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
18601 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
18602 default: llvm_unreachable("Unrecognized FMA variant.");
18605 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
18606 MachineInstrBuilder MIB =
18607 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
18608 .addOperand(MI->getOperand(0))
18609 .addOperand(MI->getOperand(3))
18610 .addOperand(MI->getOperand(2))
18611 .addOperand(MI->getOperand(1));
18612 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
18613 MI->eraseFromParent();
18620 MachineBasicBlock *
18621 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
18622 MachineBasicBlock *BB) const {
18623 switch (MI->getOpcode()) {
18624 default: llvm_unreachable("Unexpected instr type to insert");
18625 case X86::TAILJMPd64:
18626 case X86::TAILJMPr64:
18627 case X86::TAILJMPm64:
18628 case X86::TAILJMPd64_REX:
18629 case X86::TAILJMPr64_REX:
18630 case X86::TAILJMPm64_REX:
18631 llvm_unreachable("TAILJMP64 would not be touched here.");
18632 case X86::TCRETURNdi64:
18633 case X86::TCRETURNri64:
18634 case X86::TCRETURNmi64:
18636 case X86::WIN_ALLOCA:
18637 return EmitLoweredWinAlloca(MI, BB);
18638 case X86::SEG_ALLOCA_32:
18639 case X86::SEG_ALLOCA_64:
18640 return EmitLoweredSegAlloca(MI, BB);
18641 case X86::TLSCall_32:
18642 case X86::TLSCall_64:
18643 return EmitLoweredTLSCall(MI, BB);
18644 case X86::CMOV_GR8:
18645 case X86::CMOV_FR32:
18646 case X86::CMOV_FR64:
18647 case X86::CMOV_V4F32:
18648 case X86::CMOV_V2F64:
18649 case X86::CMOV_V2I64:
18650 case X86::CMOV_V8F32:
18651 case X86::CMOV_V4F64:
18652 case X86::CMOV_V4I64:
18653 case X86::CMOV_V16F32:
18654 case X86::CMOV_V8F64:
18655 case X86::CMOV_V8I64:
18656 case X86::CMOV_GR16:
18657 case X86::CMOV_GR32:
18658 case X86::CMOV_RFP32:
18659 case X86::CMOV_RFP64:
18660 case X86::CMOV_RFP80:
18661 return EmitLoweredSelect(MI, BB);
18663 case X86::FP32_TO_INT16_IN_MEM:
18664 case X86::FP32_TO_INT32_IN_MEM:
18665 case X86::FP32_TO_INT64_IN_MEM:
18666 case X86::FP64_TO_INT16_IN_MEM:
18667 case X86::FP64_TO_INT32_IN_MEM:
18668 case X86::FP64_TO_INT64_IN_MEM:
18669 case X86::FP80_TO_INT16_IN_MEM:
18670 case X86::FP80_TO_INT32_IN_MEM:
18671 case X86::FP80_TO_INT64_IN_MEM: {
18672 MachineFunction *F = BB->getParent();
18673 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18674 DebugLoc DL = MI->getDebugLoc();
18676 // Change the floating point control register to use "round towards zero"
18677 // mode when truncating to an integer value.
18678 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
18679 addFrameReference(BuildMI(*BB, MI, DL,
18680 TII->get(X86::FNSTCW16m)), CWFrameIdx);
18682 // Load the old value of the high byte of the control word...
18684 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
18685 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
18688 // Set the high part to be round to zero...
18689 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
18692 // Reload the modified control word now...
18693 addFrameReference(BuildMI(*BB, MI, DL,
18694 TII->get(X86::FLDCW16m)), CWFrameIdx);
18696 // Restore the memory image of control word to original value
18697 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
18700 // Get the X86 opcode to use.
18702 switch (MI->getOpcode()) {
18703 default: llvm_unreachable("illegal opcode!");
18704 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
18705 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
18706 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
18707 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
18708 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
18709 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
18710 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
18711 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
18712 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
18716 MachineOperand &Op = MI->getOperand(0);
18718 AM.BaseType = X86AddressMode::RegBase;
18719 AM.Base.Reg = Op.getReg();
18721 AM.BaseType = X86AddressMode::FrameIndexBase;
18722 AM.Base.FrameIndex = Op.getIndex();
18724 Op = MI->getOperand(1);
18726 AM.Scale = Op.getImm();
18727 Op = MI->getOperand(2);
18729 AM.IndexReg = Op.getImm();
18730 Op = MI->getOperand(3);
18731 if (Op.isGlobal()) {
18732 AM.GV = Op.getGlobal();
18734 AM.Disp = Op.getImm();
18736 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
18737 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
18739 // Reload the original control word now.
18740 addFrameReference(BuildMI(*BB, MI, DL,
18741 TII->get(X86::FLDCW16m)), CWFrameIdx);
18743 MI->eraseFromParent(); // The pseudo instruction is gone now.
18746 // String/text processing lowering.
18747 case X86::PCMPISTRM128REG:
18748 case X86::VPCMPISTRM128REG:
18749 case X86::PCMPISTRM128MEM:
18750 case X86::VPCMPISTRM128MEM:
18751 case X86::PCMPESTRM128REG:
18752 case X86::VPCMPESTRM128REG:
18753 case X86::PCMPESTRM128MEM:
18754 case X86::VPCMPESTRM128MEM:
18755 assert(Subtarget->hasSSE42() &&
18756 "Target must have SSE4.2 or AVX features enabled");
18757 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
18759 // String/text processing lowering.
18760 case X86::PCMPISTRIREG:
18761 case X86::VPCMPISTRIREG:
18762 case X86::PCMPISTRIMEM:
18763 case X86::VPCMPISTRIMEM:
18764 case X86::PCMPESTRIREG:
18765 case X86::VPCMPESTRIREG:
18766 case X86::PCMPESTRIMEM:
18767 case X86::VPCMPESTRIMEM:
18768 assert(Subtarget->hasSSE42() &&
18769 "Target must have SSE4.2 or AVX features enabled");
18770 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
18772 // Thread synchronization.
18774 return EmitMonitor(MI, BB, Subtarget);
18778 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
18780 case X86::VASTART_SAVE_XMM_REGS:
18781 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
18783 case X86::VAARG_64:
18784 return EmitVAARG64WithCustomInserter(MI, BB);
18786 case X86::EH_SjLj_SetJmp32:
18787 case X86::EH_SjLj_SetJmp64:
18788 return emitEHSjLjSetJmp(MI, BB);
18790 case X86::EH_SjLj_LongJmp32:
18791 case X86::EH_SjLj_LongJmp64:
18792 return emitEHSjLjLongJmp(MI, BB);
18794 case TargetOpcode::STATEPOINT:
18795 // As an implementation detail, STATEPOINT shares the STACKMAP format at
18796 // this point in the process. We diverge later.
18797 return emitPatchPoint(MI, BB);
18799 case TargetOpcode::STACKMAP:
18800 case TargetOpcode::PATCHPOINT:
18801 return emitPatchPoint(MI, BB);
18803 case X86::VFMADDPDr213r:
18804 case X86::VFMADDPSr213r:
18805 case X86::VFMADDSDr213r:
18806 case X86::VFMADDSSr213r:
18807 case X86::VFMSUBPDr213r:
18808 case X86::VFMSUBPSr213r:
18809 case X86::VFMSUBSDr213r:
18810 case X86::VFMSUBSSr213r:
18811 case X86::VFNMADDPDr213r:
18812 case X86::VFNMADDPSr213r:
18813 case X86::VFNMADDSDr213r:
18814 case X86::VFNMADDSSr213r:
18815 case X86::VFNMSUBPDr213r:
18816 case X86::VFNMSUBPSr213r:
18817 case X86::VFNMSUBSDr213r:
18818 case X86::VFNMSUBSSr213r:
18819 case X86::VFMADDSUBPDr213r:
18820 case X86::VFMADDSUBPSr213r:
18821 case X86::VFMSUBADDPDr213r:
18822 case X86::VFMSUBADDPSr213r:
18823 case X86::VFMADDPDr213rY:
18824 case X86::VFMADDPSr213rY:
18825 case X86::VFMSUBPDr213rY:
18826 case X86::VFMSUBPSr213rY:
18827 case X86::VFNMADDPDr213rY:
18828 case X86::VFNMADDPSr213rY:
18829 case X86::VFNMSUBPDr213rY:
18830 case X86::VFNMSUBPSr213rY:
18831 case X86::VFMADDSUBPDr213rY:
18832 case X86::VFMADDSUBPSr213rY:
18833 case X86::VFMSUBADDPDr213rY:
18834 case X86::VFMSUBADDPSr213rY:
18835 return emitFMA3Instr(MI, BB);
18839 //===----------------------------------------------------------------------===//
18840 // X86 Optimization Hooks
18841 //===----------------------------------------------------------------------===//
18843 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
18846 const SelectionDAG &DAG,
18847 unsigned Depth) const {
18848 unsigned BitWidth = KnownZero.getBitWidth();
18849 unsigned Opc = Op.getOpcode();
18850 assert((Opc >= ISD::BUILTIN_OP_END ||
18851 Opc == ISD::INTRINSIC_WO_CHAIN ||
18852 Opc == ISD::INTRINSIC_W_CHAIN ||
18853 Opc == ISD::INTRINSIC_VOID) &&
18854 "Should use MaskedValueIsZero if you don't know whether Op"
18855 " is a target node!");
18857 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
18871 // These nodes' second result is a boolean.
18872 if (Op.getResNo() == 0)
18875 case X86ISD::SETCC:
18876 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
18878 case ISD::INTRINSIC_WO_CHAIN: {
18879 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
18880 unsigned NumLoBits = 0;
18883 case Intrinsic::x86_sse_movmsk_ps:
18884 case Intrinsic::x86_avx_movmsk_ps_256:
18885 case Intrinsic::x86_sse2_movmsk_pd:
18886 case Intrinsic::x86_avx_movmsk_pd_256:
18887 case Intrinsic::x86_mmx_pmovmskb:
18888 case Intrinsic::x86_sse2_pmovmskb_128:
18889 case Intrinsic::x86_avx2_pmovmskb: {
18890 // High bits of movmskp{s|d}, pmovmskb are known zero.
18892 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
18893 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
18894 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
18895 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
18896 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
18897 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
18898 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
18899 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
18901 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
18910 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
18912 const SelectionDAG &,
18913 unsigned Depth) const {
18914 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
18915 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
18916 return Op.getValueType().getScalarType().getSizeInBits();
18922 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
18923 /// node is a GlobalAddress + offset.
18924 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
18925 const GlobalValue* &GA,
18926 int64_t &Offset) const {
18927 if (N->getOpcode() == X86ISD::Wrapper) {
18928 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
18929 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
18930 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
18934 return TargetLowering::isGAPlusOffset(N, GA, Offset);
18937 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
18938 /// same as extracting the high 128-bit part of 256-bit vector and then
18939 /// inserting the result into the low part of a new 256-bit vector
18940 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
18941 EVT VT = SVOp->getValueType(0);
18942 unsigned NumElems = VT.getVectorNumElements();
18944 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
18945 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
18946 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18947 SVOp->getMaskElt(j) >= 0)
18953 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
18954 /// same as extracting the low 128-bit part of 256-bit vector and then
18955 /// inserting the result into the high part of a new 256-bit vector
18956 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
18957 EVT VT = SVOp->getValueType(0);
18958 unsigned NumElems = VT.getVectorNumElements();
18960 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
18961 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
18962 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18963 SVOp->getMaskElt(j) >= 0)
18969 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
18970 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
18971 TargetLowering::DAGCombinerInfo &DCI,
18972 const X86Subtarget* Subtarget) {
18974 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
18975 SDValue V1 = SVOp->getOperand(0);
18976 SDValue V2 = SVOp->getOperand(1);
18977 EVT VT = SVOp->getValueType(0);
18978 unsigned NumElems = VT.getVectorNumElements();
18980 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
18981 V2.getOpcode() == ISD::CONCAT_VECTORS) {
18985 // V UNDEF BUILD_VECTOR UNDEF
18987 // CONCAT_VECTOR CONCAT_VECTOR
18990 // RESULT: V + zero extended
18992 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
18993 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
18994 V1.getOperand(1).getOpcode() != ISD::UNDEF)
18997 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19000 // To match the shuffle mask, the first half of the mask should
19001 // be exactly the first vector, and all the rest a splat with the
19002 // first element of the second one.
19003 for (unsigned i = 0; i != NumElems/2; ++i)
19004 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19005 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19008 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19009 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19010 if (Ld->hasNUsesOfValue(1, 0)) {
19011 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19012 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19014 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19016 Ld->getPointerInfo(),
19017 Ld->getAlignment(),
19018 false/*isVolatile*/, true/*ReadMem*/,
19019 false/*WriteMem*/);
19021 // Make sure the newly-created LOAD is in the same position as Ld in
19022 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19023 // and update uses of Ld's output chain to use the TokenFactor.
19024 if (Ld->hasAnyUseOfValue(1)) {
19025 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19026 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19027 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19028 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19029 SDValue(ResNode.getNode(), 1));
19032 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19036 // Emit a zeroed vector and insert the desired subvector on its
19038 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19039 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19040 return DCI.CombineTo(N, InsV);
19043 //===--------------------------------------------------------------------===//
19044 // Combine some shuffles into subvector extracts and inserts:
19047 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19048 if (isShuffleHigh128VectorInsertLow(SVOp)) {
19049 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
19050 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
19051 return DCI.CombineTo(N, InsV);
19054 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19055 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19056 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19057 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19058 return DCI.CombineTo(N, InsV);
19064 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19067 /// This is the leaf of the recursive combinine below. When we have found some
19068 /// chain of single-use x86 shuffle instructions and accumulated the combined
19069 /// shuffle mask represented by them, this will try to pattern match that mask
19070 /// into either a single instruction if there is a special purpose instruction
19071 /// for this operation, or into a PSHUFB instruction which is a fully general
19072 /// instruction but should only be used to replace chains over a certain depth.
19073 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19074 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19075 TargetLowering::DAGCombinerInfo &DCI,
19076 const X86Subtarget *Subtarget) {
19077 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19079 // Find the operand that enters the chain. Note that multiple uses are OK
19080 // here, we're not going to remove the operand we find.
19081 SDValue Input = Op.getOperand(0);
19082 while (Input.getOpcode() == ISD::BITCAST)
19083 Input = Input.getOperand(0);
19085 MVT VT = Input.getSimpleValueType();
19086 MVT RootVT = Root.getSimpleValueType();
19089 // Just remove no-op shuffle masks.
19090 if (Mask.size() == 1) {
19091 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19096 // Use the float domain if the operand type is a floating point type.
19097 bool FloatDomain = VT.isFloatingPoint();
19099 // For floating point shuffles, we don't have free copies in the shuffle
19100 // instructions or the ability to load as part of the instruction, so
19101 // canonicalize their shuffles to UNPCK or MOV variants.
19103 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
19104 // vectors because it can have a load folded into it that UNPCK cannot. This
19105 // doesn't preclude something switching to the shorter encoding post-RA.
19107 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
19108 bool Lo = Mask.equals(0, 0);
19111 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
19112 // is no slower than UNPCKLPD but has the option to fold the input operand
19113 // into even an unaligned memory load.
19114 if (Lo && Subtarget->hasSSE3()) {
19115 Shuffle = X86ISD::MOVDDUP;
19116 ShuffleVT = MVT::v2f64;
19118 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
19119 // than the UNPCK variants.
19120 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
19121 ShuffleVT = MVT::v4f32;
19123 if (Depth == 1 && Root->getOpcode() == Shuffle)
19124 return false; // Nothing to do!
19125 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19126 DCI.AddToWorklist(Op.getNode());
19127 if (Shuffle == X86ISD::MOVDDUP)
19128 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19130 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19131 DCI.AddToWorklist(Op.getNode());
19132 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19136 if (Subtarget->hasSSE3() &&
19137 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
19138 bool Lo = Mask.equals(0, 0, 2, 2);
19139 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
19140 MVT ShuffleVT = MVT::v4f32;
19141 if (Depth == 1 && Root->getOpcode() == Shuffle)
19142 return false; // Nothing to do!
19143 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19144 DCI.AddToWorklist(Op.getNode());
19145 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19146 DCI.AddToWorklist(Op.getNode());
19147 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19151 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
19152 bool Lo = Mask.equals(0, 0, 1, 1);
19153 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19154 MVT ShuffleVT = MVT::v4f32;
19155 if (Depth == 1 && Root->getOpcode() == Shuffle)
19156 return false; // Nothing to do!
19157 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19158 DCI.AddToWorklist(Op.getNode());
19159 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19160 DCI.AddToWorklist(Op.getNode());
19161 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19167 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
19168 // variants as none of these have single-instruction variants that are
19169 // superior to the UNPCK formulation.
19170 if (!FloatDomain &&
19171 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
19172 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
19173 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
19174 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
19176 bool Lo = Mask[0] == 0;
19177 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19178 if (Depth == 1 && Root->getOpcode() == Shuffle)
19179 return false; // Nothing to do!
19181 switch (Mask.size()) {
19183 ShuffleVT = MVT::v8i16;
19186 ShuffleVT = MVT::v16i8;
19189 llvm_unreachable("Impossible mask size!");
19191 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19192 DCI.AddToWorklist(Op.getNode());
19193 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19194 DCI.AddToWorklist(Op.getNode());
19195 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19200 // Don't try to re-form single instruction chains under any circumstances now
19201 // that we've done encoding canonicalization for them.
19205 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
19206 // can replace them with a single PSHUFB instruction profitably. Intel's
19207 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
19208 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
19209 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
19210 SmallVector<SDValue, 16> PSHUFBMask;
19211 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
19212 int Ratio = 16 / Mask.size();
19213 for (unsigned i = 0; i < 16; ++i) {
19214 if (Mask[i / Ratio] == SM_SentinelUndef) {
19215 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
19218 int M = Mask[i / Ratio] != SM_SentinelZero
19219 ? Ratio * Mask[i / Ratio] + i % Ratio
19221 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
19223 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
19224 DCI.AddToWorklist(Op.getNode());
19225 SDValue PSHUFBMaskOp =
19226 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
19227 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
19228 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
19229 DCI.AddToWorklist(Op.getNode());
19230 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19235 // Failed to find any combines.
19239 /// \brief Fully generic combining of x86 shuffle instructions.
19241 /// This should be the last combine run over the x86 shuffle instructions. Once
19242 /// they have been fully optimized, this will recursively consider all chains
19243 /// of single-use shuffle instructions, build a generic model of the cumulative
19244 /// shuffle operation, and check for simpler instructions which implement this
19245 /// operation. We use this primarily for two purposes:
19247 /// 1) Collapse generic shuffles to specialized single instructions when
19248 /// equivalent. In most cases, this is just an encoding size win, but
19249 /// sometimes we will collapse multiple generic shuffles into a single
19250 /// special-purpose shuffle.
19251 /// 2) Look for sequences of shuffle instructions with 3 or more total
19252 /// instructions, and replace them with the slightly more expensive SSSE3
19253 /// PSHUFB instruction if available. We do this as the last combining step
19254 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
19255 /// a suitable short sequence of other instructions. The PHUFB will either
19256 /// use a register or have to read from memory and so is slightly (but only
19257 /// slightly) more expensive than the other shuffle instructions.
19259 /// Because this is inherently a quadratic operation (for each shuffle in
19260 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
19261 /// This should never be an issue in practice as the shuffle lowering doesn't
19262 /// produce sequences of more than 8 instructions.
19264 /// FIXME: We will currently miss some cases where the redundant shuffling
19265 /// would simplify under the threshold for PSHUFB formation because of
19266 /// combine-ordering. To fix this, we should do the redundant instruction
19267 /// combining in this recursive walk.
19268 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
19269 ArrayRef<int> RootMask,
19270 int Depth, bool HasPSHUFB,
19272 TargetLowering::DAGCombinerInfo &DCI,
19273 const X86Subtarget *Subtarget) {
19274 // Bound the depth of our recursive combine because this is ultimately
19275 // quadratic in nature.
19279 // Directly rip through bitcasts to find the underlying operand.
19280 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
19281 Op = Op.getOperand(0);
19283 MVT VT = Op.getSimpleValueType();
19284 if (!VT.isVector())
19285 return false; // Bail if we hit a non-vector.
19286 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
19287 // version should be added.
19288 if (VT.getSizeInBits() != 128)
19291 assert(Root.getSimpleValueType().isVector() &&
19292 "Shuffles operate on vector types!");
19293 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
19294 "Can only combine shuffles of the same vector register size.");
19296 if (!isTargetShuffle(Op.getOpcode()))
19298 SmallVector<int, 16> OpMask;
19300 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
19301 // We only can combine unary shuffles which we can decode the mask for.
19302 if (!HaveMask || !IsUnary)
19305 assert(VT.getVectorNumElements() == OpMask.size() &&
19306 "Different mask size from vector size!");
19307 assert(((RootMask.size() > OpMask.size() &&
19308 RootMask.size() % OpMask.size() == 0) ||
19309 (OpMask.size() > RootMask.size() &&
19310 OpMask.size() % RootMask.size() == 0) ||
19311 OpMask.size() == RootMask.size()) &&
19312 "The smaller number of elements must divide the larger.");
19313 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
19314 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
19315 assert(((RootRatio == 1 && OpRatio == 1) ||
19316 (RootRatio == 1) != (OpRatio == 1)) &&
19317 "Must not have a ratio for both incoming and op masks!");
19319 SmallVector<int, 16> Mask;
19320 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
19322 // Merge this shuffle operation's mask into our accumulated mask. Note that
19323 // this shuffle's mask will be the first applied to the input, followed by the
19324 // root mask to get us all the way to the root value arrangement. The reason
19325 // for this order is that we are recursing up the operation chain.
19326 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
19327 int RootIdx = i / RootRatio;
19328 if (RootMask[RootIdx] < 0) {
19329 // This is a zero or undef lane, we're done.
19330 Mask.push_back(RootMask[RootIdx]);
19334 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
19335 int OpIdx = RootMaskedIdx / OpRatio;
19336 if (OpMask[OpIdx] < 0) {
19337 // The incoming lanes are zero or undef, it doesn't matter which ones we
19339 Mask.push_back(OpMask[OpIdx]);
19343 // Ok, we have non-zero lanes, map them through.
19344 Mask.push_back(OpMask[OpIdx] * OpRatio +
19345 RootMaskedIdx % OpRatio);
19348 // See if we can recurse into the operand to combine more things.
19349 switch (Op.getOpcode()) {
19350 case X86ISD::PSHUFB:
19352 case X86ISD::PSHUFD:
19353 case X86ISD::PSHUFHW:
19354 case X86ISD::PSHUFLW:
19355 if (Op.getOperand(0).hasOneUse() &&
19356 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19357 HasPSHUFB, DAG, DCI, Subtarget))
19361 case X86ISD::UNPCKL:
19362 case X86ISD::UNPCKH:
19363 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
19364 // We can't check for single use, we have to check that this shuffle is the only user.
19365 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
19366 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19367 HasPSHUFB, DAG, DCI, Subtarget))
19372 // Minor canonicalization of the accumulated shuffle mask to make it easier
19373 // to match below. All this does is detect masks with squential pairs of
19374 // elements, and shrink them to the half-width mask. It does this in a loop
19375 // so it will reduce the size of the mask to the minimal width mask which
19376 // performs an equivalent shuffle.
19377 SmallVector<int, 16> WidenedMask;
19378 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
19379 Mask = std::move(WidenedMask);
19380 WidenedMask.clear();
19383 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
19387 /// \brief Get the PSHUF-style mask from PSHUF node.
19389 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
19390 /// PSHUF-style masks that can be reused with such instructions.
19391 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
19392 SmallVector<int, 4> Mask;
19394 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
19398 switch (N.getOpcode()) {
19399 case X86ISD::PSHUFD:
19401 case X86ISD::PSHUFLW:
19404 case X86ISD::PSHUFHW:
19405 Mask.erase(Mask.begin(), Mask.begin() + 4);
19406 for (int &M : Mask)
19410 llvm_unreachable("No valid shuffle instruction found!");
19414 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
19416 /// We walk up the chain and look for a combinable shuffle, skipping over
19417 /// shuffles that we could hoist this shuffle's transformation past without
19418 /// altering anything.
19420 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
19422 TargetLowering::DAGCombinerInfo &DCI) {
19423 assert(N.getOpcode() == X86ISD::PSHUFD &&
19424 "Called with something other than an x86 128-bit half shuffle!");
19427 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
19428 // of the shuffles in the chain so that we can form a fresh chain to replace
19430 SmallVector<SDValue, 8> Chain;
19431 SDValue V = N.getOperand(0);
19432 for (; V.hasOneUse(); V = V.getOperand(0)) {
19433 switch (V.getOpcode()) {
19435 return SDValue(); // Nothing combined!
19438 // Skip bitcasts as we always know the type for the target specific
19442 case X86ISD::PSHUFD:
19443 // Found another dword shuffle.
19446 case X86ISD::PSHUFLW:
19447 // Check that the low words (being shuffled) are the identity in the
19448 // dword shuffle, and the high words are self-contained.
19449 if (Mask[0] != 0 || Mask[1] != 1 ||
19450 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
19453 Chain.push_back(V);
19456 case X86ISD::PSHUFHW:
19457 // Check that the high words (being shuffled) are the identity in the
19458 // dword shuffle, and the low words are self-contained.
19459 if (Mask[2] != 2 || Mask[3] != 3 ||
19460 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
19463 Chain.push_back(V);
19466 case X86ISD::UNPCKL:
19467 case X86ISD::UNPCKH:
19468 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
19469 // shuffle into a preceding word shuffle.
19470 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
19473 // Search for a half-shuffle which we can combine with.
19474 unsigned CombineOp =
19475 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
19476 if (V.getOperand(0) != V.getOperand(1) ||
19477 !V->isOnlyUserOf(V.getOperand(0).getNode()))
19479 Chain.push_back(V);
19480 V = V.getOperand(0);
19482 switch (V.getOpcode()) {
19484 return SDValue(); // Nothing to combine.
19486 case X86ISD::PSHUFLW:
19487 case X86ISD::PSHUFHW:
19488 if (V.getOpcode() == CombineOp)
19491 Chain.push_back(V);
19495 V = V.getOperand(0);
19499 } while (V.hasOneUse());
19502 // Break out of the loop if we break out of the switch.
19506 if (!V.hasOneUse())
19507 // We fell out of the loop without finding a viable combining instruction.
19510 // Merge this node's mask and our incoming mask.
19511 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19512 for (int &M : Mask)
19514 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
19515 getV4X86ShuffleImm8ForMask(Mask, DAG));
19517 // Rebuild the chain around this new shuffle.
19518 while (!Chain.empty()) {
19519 SDValue W = Chain.pop_back_val();
19521 if (V.getValueType() != W.getOperand(0).getValueType())
19522 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
19524 switch (W.getOpcode()) {
19526 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
19528 case X86ISD::UNPCKL:
19529 case X86ISD::UNPCKH:
19530 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
19533 case X86ISD::PSHUFD:
19534 case X86ISD::PSHUFLW:
19535 case X86ISD::PSHUFHW:
19536 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
19540 if (V.getValueType() != N.getValueType())
19541 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
19543 // Return the new chain to replace N.
19547 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
19549 /// We walk up the chain, skipping shuffles of the other half and looking
19550 /// through shuffles which switch halves trying to find a shuffle of the same
19551 /// pair of dwords.
19552 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
19554 TargetLowering::DAGCombinerInfo &DCI) {
19556 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
19557 "Called with something other than an x86 128-bit half shuffle!");
19559 unsigned CombineOpcode = N.getOpcode();
19561 // Walk up a single-use chain looking for a combinable shuffle.
19562 SDValue V = N.getOperand(0);
19563 for (; V.hasOneUse(); V = V.getOperand(0)) {
19564 switch (V.getOpcode()) {
19566 return false; // Nothing combined!
19569 // Skip bitcasts as we always know the type for the target specific
19573 case X86ISD::PSHUFLW:
19574 case X86ISD::PSHUFHW:
19575 if (V.getOpcode() == CombineOpcode)
19578 // Other-half shuffles are no-ops.
19581 // Break out of the loop if we break out of the switch.
19585 if (!V.hasOneUse())
19586 // We fell out of the loop without finding a viable combining instruction.
19589 // Combine away the bottom node as its shuffle will be accumulated into
19590 // a preceding shuffle.
19591 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19593 // Record the old value.
19596 // Merge this node's mask and our incoming mask (adjusted to account for all
19597 // the pshufd instructions encountered).
19598 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19599 for (int &M : Mask)
19601 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
19602 getV4X86ShuffleImm8ForMask(Mask, DAG));
19604 // Check that the shuffles didn't cancel each other out. If not, we need to
19605 // combine to the new one.
19607 // Replace the combinable shuffle with the combined one, updating all users
19608 // so that we re-evaluate the chain here.
19609 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
19614 /// \brief Try to combine x86 target specific shuffles.
19615 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
19616 TargetLowering::DAGCombinerInfo &DCI,
19617 const X86Subtarget *Subtarget) {
19619 MVT VT = N.getSimpleValueType();
19620 SmallVector<int, 4> Mask;
19622 switch (N.getOpcode()) {
19623 case X86ISD::PSHUFD:
19624 case X86ISD::PSHUFLW:
19625 case X86ISD::PSHUFHW:
19626 Mask = getPSHUFShuffleMask(N);
19627 assert(Mask.size() == 4);
19633 // Nuke no-op shuffles that show up after combining.
19634 if (isNoopShuffleMask(Mask))
19635 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19637 // Look for simplifications involving one or two shuffle instructions.
19638 SDValue V = N.getOperand(0);
19639 switch (N.getOpcode()) {
19642 case X86ISD::PSHUFLW:
19643 case X86ISD::PSHUFHW:
19644 assert(VT == MVT::v8i16);
19647 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
19648 return SDValue(); // We combined away this shuffle, so we're done.
19650 // See if this reduces to a PSHUFD which is no more expensive and can
19651 // combine with more operations. Note that it has to at least flip the
19652 // dwords as otherwise it would have been removed as a no-op.
19653 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
19654 int DMask[] = {0, 1, 2, 3};
19655 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
19656 DMask[DOffset + 0] = DOffset + 1;
19657 DMask[DOffset + 1] = DOffset + 0;
19658 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
19659 DCI.AddToWorklist(V.getNode());
19660 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
19661 getV4X86ShuffleImm8ForMask(DMask, DAG));
19662 DCI.AddToWorklist(V.getNode());
19663 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
19666 // Look for shuffle patterns which can be implemented as a single unpack.
19667 // FIXME: This doesn't handle the location of the PSHUFD generically, and
19668 // only works when we have a PSHUFD followed by two half-shuffles.
19669 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
19670 (V.getOpcode() == X86ISD::PSHUFLW ||
19671 V.getOpcode() == X86ISD::PSHUFHW) &&
19672 V.getOpcode() != N.getOpcode() &&
19674 SDValue D = V.getOperand(0);
19675 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
19676 D = D.getOperand(0);
19677 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
19678 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19679 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
19680 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19681 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19683 for (int i = 0; i < 4; ++i) {
19684 WordMask[i + NOffset] = Mask[i] + NOffset;
19685 WordMask[i + VOffset] = VMask[i] + VOffset;
19687 // Map the word mask through the DWord mask.
19689 for (int i = 0; i < 8; ++i)
19690 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
19691 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
19692 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
19693 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
19694 std::begin(UnpackLoMask)) ||
19695 std::equal(std::begin(MappedMask), std::end(MappedMask),
19696 std::begin(UnpackHiMask))) {
19697 // We can replace all three shuffles with an unpack.
19698 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
19699 DCI.AddToWorklist(V.getNode());
19700 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
19702 DL, MVT::v8i16, V, V);
19709 case X86ISD::PSHUFD:
19710 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
19719 /// \brief Try to combine a shuffle into a target-specific add-sub node.
19721 /// We combine this directly on the abstract vector shuffle nodes so it is
19722 /// easier to generically match. We also insert dummy vector shuffle nodes for
19723 /// the operands which explicitly discard the lanes which are unused by this
19724 /// operation to try to flow through the rest of the combiner the fact that
19725 /// they're unused.
19726 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
19728 EVT VT = N->getValueType(0);
19730 // We only handle target-independent shuffles.
19731 // FIXME: It would be easy and harmless to use the target shuffle mask
19732 // extraction tool to support more.
19733 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
19736 auto *SVN = cast<ShuffleVectorSDNode>(N);
19737 ArrayRef<int> Mask = SVN->getMask();
19738 SDValue V1 = N->getOperand(0);
19739 SDValue V2 = N->getOperand(1);
19741 // We require the first shuffle operand to be the SUB node, and the second to
19742 // be the ADD node.
19743 // FIXME: We should support the commuted patterns.
19744 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
19747 // If there are other uses of these operations we can't fold them.
19748 if (!V1->hasOneUse() || !V2->hasOneUse())
19751 // Ensure that both operations have the same operands. Note that we can
19752 // commute the FADD operands.
19753 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
19754 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
19755 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
19758 // We're looking for blends between FADD and FSUB nodes. We insist on these
19759 // nodes being lined up in a specific expected pattern.
19760 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
19761 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
19762 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
19765 // Only specific types are legal at this point, assert so we notice if and
19766 // when these change.
19767 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
19768 VT == MVT::v4f64) &&
19769 "Unknown vector type encountered!");
19771 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
19774 /// PerformShuffleCombine - Performs several different shuffle combines.
19775 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
19776 TargetLowering::DAGCombinerInfo &DCI,
19777 const X86Subtarget *Subtarget) {
19779 SDValue N0 = N->getOperand(0);
19780 SDValue N1 = N->getOperand(1);
19781 EVT VT = N->getValueType(0);
19783 // Don't create instructions with illegal types after legalize types has run.
19784 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19785 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
19788 // If we have legalized the vector types, look for blends of FADD and FSUB
19789 // nodes that we can fuse into an ADDSUB node.
19790 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
19791 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
19794 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
19795 if (Subtarget->hasFp256() && VT.is256BitVector() &&
19796 N->getOpcode() == ISD::VECTOR_SHUFFLE)
19797 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
19799 // During Type Legalization, when promoting illegal vector types,
19800 // the backend might introduce new shuffle dag nodes and bitcasts.
19802 // This code performs the following transformation:
19803 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
19804 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
19806 // We do this only if both the bitcast and the BINOP dag nodes have
19807 // one use. Also, perform this transformation only if the new binary
19808 // operation is legal. This is to avoid introducing dag nodes that
19809 // potentially need to be further expanded (or custom lowered) into a
19810 // less optimal sequence of dag nodes.
19811 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
19812 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
19813 N0.getOpcode() == ISD::BITCAST) {
19814 SDValue BC0 = N0.getOperand(0);
19815 EVT SVT = BC0.getValueType();
19816 unsigned Opcode = BC0.getOpcode();
19817 unsigned NumElts = VT.getVectorNumElements();
19819 if (BC0.hasOneUse() && SVT.isVector() &&
19820 SVT.getVectorNumElements() * 2 == NumElts &&
19821 TLI.isOperationLegal(Opcode, VT)) {
19822 bool CanFold = false;
19834 unsigned SVTNumElts = SVT.getVectorNumElements();
19835 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19836 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
19837 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
19838 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
19839 CanFold = SVOp->getMaskElt(i) < 0;
19842 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
19843 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
19844 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
19845 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
19850 // Only handle 128 wide vector from here on.
19851 if (!VT.is128BitVector())
19854 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
19855 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
19856 // consecutive, non-overlapping, and in the right order.
19857 SmallVector<SDValue, 16> Elts;
19858 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
19859 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
19861 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
19865 if (isTargetShuffle(N->getOpcode())) {
19867 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
19868 if (Shuffle.getNode())
19871 // Try recursively combining arbitrary sequences of x86 shuffle
19872 // instructions into higher-order shuffles. We do this after combining
19873 // specific PSHUF instruction sequences into their minimal form so that we
19874 // can evaluate how many specialized shuffle instructions are involved in
19875 // a particular chain.
19876 SmallVector<int, 1> NonceMask; // Just a placeholder.
19877 NonceMask.push_back(0);
19878 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
19879 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
19881 return SDValue(); // This routine will use CombineTo to replace N.
19887 /// PerformTruncateCombine - Converts truncate operation to
19888 /// a sequence of vector shuffle operations.
19889 /// It is possible when we truncate 256-bit vector to 128-bit vector
19890 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
19891 TargetLowering::DAGCombinerInfo &DCI,
19892 const X86Subtarget *Subtarget) {
19896 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
19897 /// specific shuffle of a load can be folded into a single element load.
19898 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
19899 /// shuffles have been custom lowered so we need to handle those here.
19900 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
19901 TargetLowering::DAGCombinerInfo &DCI) {
19902 if (DCI.isBeforeLegalizeOps())
19905 SDValue InVec = N->getOperand(0);
19906 SDValue EltNo = N->getOperand(1);
19908 if (!isa<ConstantSDNode>(EltNo))
19911 EVT OriginalVT = InVec.getValueType();
19913 if (InVec.getOpcode() == ISD::BITCAST) {
19914 // Don't duplicate a load with other uses.
19915 if (!InVec.hasOneUse())
19917 EVT BCVT = InVec.getOperand(0).getValueType();
19918 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
19920 InVec = InVec.getOperand(0);
19923 EVT CurrentVT = InVec.getValueType();
19925 if (!isTargetShuffle(InVec.getOpcode()))
19928 // Don't duplicate a load with other uses.
19929 if (!InVec.hasOneUse())
19932 SmallVector<int, 16> ShuffleMask;
19934 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
19935 ShuffleMask, UnaryShuffle))
19938 // Select the input vector, guarding against out of range extract vector.
19939 unsigned NumElems = CurrentVT.getVectorNumElements();
19940 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
19941 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
19942 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
19943 : InVec.getOperand(1);
19945 // If inputs to shuffle are the same for both ops, then allow 2 uses
19946 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
19947 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
19949 if (LdNode.getOpcode() == ISD::BITCAST) {
19950 // Don't duplicate a load with other uses.
19951 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
19954 AllowedUses = 1; // only allow 1 load use if we have a bitcast
19955 LdNode = LdNode.getOperand(0);
19958 if (!ISD::isNormalLoad(LdNode.getNode()))
19961 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
19963 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
19966 EVT EltVT = N->getValueType(0);
19967 // If there's a bitcast before the shuffle, check if the load type and
19968 // alignment is valid.
19969 unsigned Align = LN0->getAlignment();
19970 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19971 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
19972 EltVT.getTypeForEVT(*DAG.getContext()));
19974 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
19977 // All checks match so transform back to vector_shuffle so that DAG combiner
19978 // can finish the job
19981 // Create shuffle node taking into account the case that its a unary shuffle
19982 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
19983 : InVec.getOperand(1);
19984 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
19985 InVec.getOperand(0), Shuffle,
19987 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
19988 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
19992 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
19993 /// special and don't usually play with other vector types, it's better to
19994 /// handle them early to be sure we emit efficient code by avoiding
19995 /// store-load conversions.
19996 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
19997 if (N->getValueType(0) != MVT::x86mmx ||
19998 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
19999 N->getOperand(0)->getValueType(0) != MVT::v2i32)
20002 SDValue V = N->getOperand(0);
20003 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
20004 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
20005 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
20006 N->getValueType(0), V.getOperand(0));
20011 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20012 /// generation and convert it from being a bunch of shuffles and extracts
20013 /// into a somewhat faster sequence. For i686, the best sequence is apparently
20014 /// storing the value and loading scalars back, while for x64 we should
20015 /// use 64-bit extracts and shifts.
20016 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20017 TargetLowering::DAGCombinerInfo &DCI) {
20018 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20019 if (NewOp.getNode())
20022 SDValue InputVector = N->getOperand(0);
20024 // Detect mmx to i32 conversion through a v2i32 elt extract.
20025 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
20026 N->getValueType(0) == MVT::i32 &&
20027 InputVector.getValueType() == MVT::v2i32) {
20029 // The bitcast source is a direct mmx result.
20030 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
20031 if (MMXSrc.getValueType() == MVT::x86mmx)
20032 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20033 N->getValueType(0),
20034 InputVector.getNode()->getOperand(0));
20036 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
20037 SDValue MMXSrcOp = MMXSrc.getOperand(0);
20038 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
20039 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
20040 MMXSrcOp.getOpcode() == ISD::BITCAST &&
20041 MMXSrcOp.getValueType() == MVT::v1i64 &&
20042 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
20043 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20044 N->getValueType(0),
20045 MMXSrcOp.getOperand(0));
20048 // Only operate on vectors of 4 elements, where the alternative shuffling
20049 // gets to be more expensive.
20050 if (InputVector.getValueType() != MVT::v4i32)
20053 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20054 // single use which is a sign-extend or zero-extend, and all elements are
20056 SmallVector<SDNode *, 4> Uses;
20057 unsigned ExtractedElements = 0;
20058 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20059 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20060 if (UI.getUse().getResNo() != InputVector.getResNo())
20063 SDNode *Extract = *UI;
20064 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20067 if (Extract->getValueType(0) != MVT::i32)
20069 if (!Extract->hasOneUse())
20071 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20072 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20074 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20077 // Record which element was extracted.
20078 ExtractedElements |=
20079 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20081 Uses.push_back(Extract);
20084 // If not all the elements were used, this may not be worthwhile.
20085 if (ExtractedElements != 15)
20088 // Ok, we've now decided to do the transformation.
20089 // If 64-bit shifts are legal, use the extract-shift sequence,
20090 // otherwise bounce the vector off the cache.
20091 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20093 SDLoc dl(InputVector);
20095 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
20096 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
20097 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
20098 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
20099 DAG.getConstant(0, VecIdxTy));
20100 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
20101 DAG.getConstant(1, VecIdxTy));
20103 SDValue ShAmt = DAG.getConstant(32,
20104 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
20105 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
20106 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
20107 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
20108 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
20109 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
20110 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
20112 // Store the value to a temporary stack slot.
20113 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
20114 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
20115 MachinePointerInfo(), false, false, 0);
20117 EVT ElementType = InputVector.getValueType().getVectorElementType();
20118 unsigned EltSize = ElementType.getSizeInBits() / 8;
20120 // Replace each use (extract) with a load of the appropriate element.
20121 for (unsigned i = 0; i < 4; ++i) {
20122 uint64_t Offset = EltSize * i;
20123 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
20125 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
20126 StackPtr, OffsetVal);
20128 // Load the scalar.
20129 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
20130 ScalarAddr, MachinePointerInfo(),
20131 false, false, false, 0);
20136 // Replace the extracts
20137 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
20138 UE = Uses.end(); UI != UE; ++UI) {
20139 SDNode *Extract = *UI;
20141 SDValue Idx = Extract->getOperand(1);
20142 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
20143 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
20146 // The replacement was made in place; don't return anything.
20150 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
20151 static std::pair<unsigned, bool>
20152 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
20153 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
20154 if (!VT.isVector())
20155 return std::make_pair(0, false);
20157 bool NeedSplit = false;
20158 switch (VT.getSimpleVT().SimpleTy) {
20159 default: return std::make_pair(0, false);
20162 if (!Subtarget->hasVLX())
20163 return std::make_pair(0, false);
20167 if (!Subtarget->hasBWI())
20168 return std::make_pair(0, false);
20172 if (!Subtarget->hasAVX512())
20173 return std::make_pair(0, false);
20178 if (!Subtarget->hasAVX2())
20180 if (!Subtarget->hasAVX())
20181 return std::make_pair(0, false);
20186 if (!Subtarget->hasSSE2())
20187 return std::make_pair(0, false);
20190 // SSE2 has only a small subset of the operations.
20191 bool hasUnsigned = Subtarget->hasSSE41() ||
20192 (Subtarget->hasSSE2() && VT == MVT::v16i8);
20193 bool hasSigned = Subtarget->hasSSE41() ||
20194 (Subtarget->hasSSE2() && VT == MVT::v8i16);
20196 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20199 // Check for x CC y ? x : y.
20200 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20201 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20206 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20209 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20212 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20215 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20217 // Check for x CC y ? y : x -- a min/max with reversed arms.
20218 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20219 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20224 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20227 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20230 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20233 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20237 return std::make_pair(Opc, NeedSplit);
20241 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
20242 const X86Subtarget *Subtarget) {
20244 SDValue Cond = N->getOperand(0);
20245 SDValue LHS = N->getOperand(1);
20246 SDValue RHS = N->getOperand(2);
20248 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
20249 SDValue CondSrc = Cond->getOperand(0);
20250 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
20251 Cond = CondSrc->getOperand(0);
20254 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
20257 // A vselect where all conditions and data are constants can be optimized into
20258 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
20259 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
20260 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
20263 unsigned MaskValue = 0;
20264 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
20267 MVT VT = N->getSimpleValueType(0);
20268 unsigned NumElems = VT.getVectorNumElements();
20269 SmallVector<int, 8> ShuffleMask(NumElems, -1);
20270 for (unsigned i = 0; i < NumElems; ++i) {
20271 // Be sure we emit undef where we can.
20272 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
20273 ShuffleMask[i] = -1;
20275 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
20278 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20279 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
20281 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
20284 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
20286 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
20287 TargetLowering::DAGCombinerInfo &DCI,
20288 const X86Subtarget *Subtarget) {
20290 SDValue Cond = N->getOperand(0);
20291 // Get the LHS/RHS of the select.
20292 SDValue LHS = N->getOperand(1);
20293 SDValue RHS = N->getOperand(2);
20294 EVT VT = LHS.getValueType();
20295 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20297 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
20298 // instructions match the semantics of the common C idiom x<y?x:y but not
20299 // x<=y?x:y, because of how they handle negative zero (which can be
20300 // ignored in unsafe-math mode).
20301 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
20302 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
20303 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
20304 (Subtarget->hasSSE2() ||
20305 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
20306 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20308 unsigned Opcode = 0;
20309 // Check for x CC y ? x : y.
20310 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20311 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20315 // Converting this to a min would handle NaNs incorrectly, and swapping
20316 // the operands would cause it to handle comparisons between positive
20317 // and negative zero incorrectly.
20318 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20319 if (!DAG.getTarget().Options.UnsafeFPMath &&
20320 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20322 std::swap(LHS, RHS);
20324 Opcode = X86ISD::FMIN;
20327 // Converting this to a min would handle comparisons between positive
20328 // and negative zero incorrectly.
20329 if (!DAG.getTarget().Options.UnsafeFPMath &&
20330 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20332 Opcode = X86ISD::FMIN;
20335 // Converting this to a min would handle both negative zeros and NaNs
20336 // incorrectly, but we can swap the operands to fix both.
20337 std::swap(LHS, RHS);
20341 Opcode = X86ISD::FMIN;
20345 // Converting this to a max would handle comparisons between positive
20346 // and negative zero incorrectly.
20347 if (!DAG.getTarget().Options.UnsafeFPMath &&
20348 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20350 Opcode = X86ISD::FMAX;
20353 // Converting this to a max would handle NaNs incorrectly, and swapping
20354 // the operands would cause it to handle comparisons between positive
20355 // and negative zero incorrectly.
20356 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20357 if (!DAG.getTarget().Options.UnsafeFPMath &&
20358 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20360 std::swap(LHS, RHS);
20362 Opcode = X86ISD::FMAX;
20365 // Converting this to a max would handle both negative zeros and NaNs
20366 // incorrectly, but we can swap the operands to fix both.
20367 std::swap(LHS, RHS);
20371 Opcode = X86ISD::FMAX;
20374 // Check for x CC y ? y : x -- a min/max with reversed arms.
20375 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20376 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20380 // Converting this to a min would handle comparisons between positive
20381 // and negative zero incorrectly, and swapping the operands would
20382 // cause it to handle NaNs incorrectly.
20383 if (!DAG.getTarget().Options.UnsafeFPMath &&
20384 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
20385 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20387 std::swap(LHS, RHS);
20389 Opcode = X86ISD::FMIN;
20392 // Converting this to a min would handle NaNs incorrectly.
20393 if (!DAG.getTarget().Options.UnsafeFPMath &&
20394 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
20396 Opcode = X86ISD::FMIN;
20399 // Converting this to a min would handle both negative zeros and NaNs
20400 // incorrectly, but we can swap the operands to fix both.
20401 std::swap(LHS, RHS);
20405 Opcode = X86ISD::FMIN;
20409 // Converting this to a max would handle NaNs incorrectly.
20410 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20412 Opcode = X86ISD::FMAX;
20415 // Converting this to a max would handle comparisons between positive
20416 // and negative zero incorrectly, and swapping the operands would
20417 // cause it to handle NaNs incorrectly.
20418 if (!DAG.getTarget().Options.UnsafeFPMath &&
20419 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
20420 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20422 std::swap(LHS, RHS);
20424 Opcode = X86ISD::FMAX;
20427 // Converting this to a max would handle both negative zeros and NaNs
20428 // incorrectly, but we can swap the operands to fix both.
20429 std::swap(LHS, RHS);
20433 Opcode = X86ISD::FMAX;
20439 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
20442 EVT CondVT = Cond.getValueType();
20443 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
20444 CondVT.getVectorElementType() == MVT::i1) {
20445 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
20446 // lowering on KNL. In this case we convert it to
20447 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
20448 // The same situation for all 128 and 256-bit vectors of i8 and i16.
20449 // Since SKX these selects have a proper lowering.
20450 EVT OpVT = LHS.getValueType();
20451 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
20452 (OpVT.getVectorElementType() == MVT::i8 ||
20453 OpVT.getVectorElementType() == MVT::i16) &&
20454 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
20455 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
20456 DCI.AddToWorklist(Cond.getNode());
20457 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
20460 // If this is a select between two integer constants, try to do some
20462 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
20463 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
20464 // Don't do this for crazy integer types.
20465 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
20466 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
20467 // so that TrueC (the true value) is larger than FalseC.
20468 bool NeedsCondInvert = false;
20470 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
20471 // Efficiently invertible.
20472 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
20473 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
20474 isa<ConstantSDNode>(Cond.getOperand(1))))) {
20475 NeedsCondInvert = true;
20476 std::swap(TrueC, FalseC);
20479 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
20480 if (FalseC->getAPIntValue() == 0 &&
20481 TrueC->getAPIntValue().isPowerOf2()) {
20482 if (NeedsCondInvert) // Invert the condition if needed.
20483 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20484 DAG.getConstant(1, Cond.getValueType()));
20486 // Zero extend the condition if needed.
20487 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
20489 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20490 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
20491 DAG.getConstant(ShAmt, MVT::i8));
20494 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
20495 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20496 if (NeedsCondInvert) // Invert the condition if needed.
20497 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20498 DAG.getConstant(1, Cond.getValueType()));
20500 // Zero extend the condition if needed.
20501 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20502 FalseC->getValueType(0), Cond);
20503 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20504 SDValue(FalseC, 0));
20507 // Optimize cases that will turn into an LEA instruction. This requires
20508 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20509 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20510 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20511 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20513 bool isFastMultiplier = false;
20515 switch ((unsigned char)Diff) {
20517 case 1: // result = add base, cond
20518 case 2: // result = lea base( , cond*2)
20519 case 3: // result = lea base(cond, cond*2)
20520 case 4: // result = lea base( , cond*4)
20521 case 5: // result = lea base(cond, cond*4)
20522 case 8: // result = lea base( , cond*8)
20523 case 9: // result = lea base(cond, cond*8)
20524 isFastMultiplier = true;
20529 if (isFastMultiplier) {
20530 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20531 if (NeedsCondInvert) // Invert the condition if needed.
20532 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20533 DAG.getConstant(1, Cond.getValueType()));
20535 // Zero extend the condition if needed.
20536 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
20538 // Scale the condition by the difference.
20540 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
20541 DAG.getConstant(Diff, Cond.getValueType()));
20543 // Add the base if non-zero.
20544 if (FalseC->getAPIntValue() != 0)
20545 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20546 SDValue(FalseC, 0));
20553 // Canonicalize max and min:
20554 // (x > y) ? x : y -> (x >= y) ? x : y
20555 // (x < y) ? x : y -> (x <= y) ? x : y
20556 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
20557 // the need for an extra compare
20558 // against zero. e.g.
20559 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
20561 // testl %edi, %edi
20563 // cmovgl %edi, %eax
20567 // cmovsl %eax, %edi
20568 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
20569 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20570 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20571 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20576 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
20577 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
20578 Cond.getOperand(0), Cond.getOperand(1), NewCC);
20579 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
20584 // Early exit check
20585 if (!TLI.isTypeLegal(VT))
20588 // Match VSELECTs into subs with unsigned saturation.
20589 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20590 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
20591 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
20592 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
20593 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20595 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
20596 // left side invert the predicate to simplify logic below.
20598 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
20600 CC = ISD::getSetCCInverse(CC, true);
20601 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
20605 if (Other.getNode() && Other->getNumOperands() == 2 &&
20606 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
20607 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
20608 SDValue CondRHS = Cond->getOperand(1);
20610 // Look for a general sub with unsigned saturation first.
20611 // x >= y ? x-y : 0 --> subus x, y
20612 // x > y ? x-y : 0 --> subus x, y
20613 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
20614 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
20615 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
20617 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
20618 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
20619 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
20620 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
20621 // If the RHS is a constant we have to reverse the const
20622 // canonicalization.
20623 // x > C-1 ? x+-C : 0 --> subus x, C
20624 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
20625 CondRHSConst->getAPIntValue() ==
20626 (-OpRHSConst->getAPIntValue() - 1))
20627 return DAG.getNode(
20628 X86ISD::SUBUS, DL, VT, OpLHS,
20629 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
20631 // Another special case: If C was a sign bit, the sub has been
20632 // canonicalized into a xor.
20633 // FIXME: Would it be better to use computeKnownBits to determine
20634 // whether it's safe to decanonicalize the xor?
20635 // x s< 0 ? x^C : 0 --> subus x, C
20636 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
20637 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
20638 OpRHSConst->getAPIntValue().isSignBit())
20639 // Note that we have to rebuild the RHS constant here to ensure we
20640 // don't rely on particular values of undef lanes.
20641 return DAG.getNode(
20642 X86ISD::SUBUS, DL, VT, OpLHS,
20643 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
20648 // Try to match a min/max vector operation.
20649 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
20650 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
20651 unsigned Opc = ret.first;
20652 bool NeedSplit = ret.second;
20654 if (Opc && NeedSplit) {
20655 unsigned NumElems = VT.getVectorNumElements();
20656 // Extract the LHS vectors
20657 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
20658 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
20660 // Extract the RHS vectors
20661 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
20662 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
20664 // Create min/max for each subvector
20665 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
20666 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
20668 // Merge the result
20669 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
20671 return DAG.getNode(Opc, DL, VT, LHS, RHS);
20674 // Simplify vector selection if condition value type matches vselect
20676 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
20677 assert(Cond.getValueType().isVector() &&
20678 "vector select expects a vector selector!");
20680 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
20681 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
20683 // Try invert the condition if true value is not all 1s and false value
20685 if (!TValIsAllOnes && !FValIsAllZeros &&
20686 // Check if the selector will be produced by CMPP*/PCMP*
20687 Cond.getOpcode() == ISD::SETCC &&
20688 // Check if SETCC has already been promoted
20689 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
20690 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
20691 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
20693 if (TValIsAllZeros || FValIsAllOnes) {
20694 SDValue CC = Cond.getOperand(2);
20695 ISD::CondCode NewCC =
20696 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
20697 Cond.getOperand(0).getValueType().isInteger());
20698 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
20699 std::swap(LHS, RHS);
20700 TValIsAllOnes = FValIsAllOnes;
20701 FValIsAllZeros = TValIsAllZeros;
20705 if (TValIsAllOnes || FValIsAllZeros) {
20708 if (TValIsAllOnes && FValIsAllZeros)
20710 else if (TValIsAllOnes)
20711 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
20712 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
20713 else if (FValIsAllZeros)
20714 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
20715 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
20717 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
20721 // If we know that this node is legal then we know that it is going to be
20722 // matched by one of the SSE/AVX BLEND instructions. These instructions only
20723 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
20724 // to simplify previous instructions.
20725 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
20726 !DCI.isBeforeLegalize() &&
20727 // We explicitly check against SSE4.1, v8i16 and v16i16 because, although
20728 // vselect nodes may be marked as Custom, they might only be legal when
20729 // Cond is a build_vector of constants. This will be taken care in
20730 // a later condition.
20731 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) &&
20732 Subtarget->hasSSE41() && VT != MVT::v16i16 && VT != MVT::v8i16) &&
20733 // Don't optimize vector of constants. Those are handled by
20734 // the generic code and all the bits must be properly set for
20735 // the generic optimizer.
20736 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
20737 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
20739 // Don't optimize vector selects that map to mask-registers.
20743 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
20744 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
20746 APInt KnownZero, KnownOne;
20747 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
20748 DCI.isBeforeLegalizeOps());
20749 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
20750 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
20752 // If we changed the computation somewhere in the DAG, this change
20753 // will affect all users of Cond.
20754 // Make sure it is fine and update all the nodes so that we do not
20755 // use the generic VSELECT anymore. Otherwise, we may perform
20756 // wrong optimizations as we messed up with the actual expectation
20757 // for the vector boolean values.
20758 if (Cond != TLO.Old) {
20759 // Check all uses of that condition operand to check whether it will be
20760 // consumed by non-BLEND instructions, which may depend on all bits are
20762 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
20764 if (I->getOpcode() != ISD::VSELECT)
20765 // TODO: Add other opcodes eventually lowered into BLEND.
20768 // Update all the users of the condition, before committing the change,
20769 // so that the VSELECT optimizations that expect the correct vector
20770 // boolean value will not be triggered.
20771 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
20773 DAG.ReplaceAllUsesOfValueWith(
20775 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
20776 Cond, I->getOperand(1), I->getOperand(2)));
20777 DCI.CommitTargetLoweringOpt(TLO);
20780 // At this point, only Cond is changed. Change the condition
20781 // just for N to keep the opportunity to optimize all other
20782 // users their own way.
20783 DAG.ReplaceAllUsesOfValueWith(
20785 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
20786 TLO.New, N->getOperand(1), N->getOperand(2)));
20791 // We should generate an X86ISD::BLENDI from a vselect if its argument
20792 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
20793 // constants. This specific pattern gets generated when we split a
20794 // selector for a 512 bit vector in a machine without AVX512 (but with
20795 // 256-bit vectors), during legalization:
20797 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
20799 // Iff we find this pattern and the build_vectors are built from
20800 // constants, we translate the vselect into a shuffle_vector that we
20801 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
20802 if ((N->getOpcode() == ISD::VSELECT ||
20803 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
20804 !DCI.isBeforeLegalize()) {
20805 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
20806 if (Shuffle.getNode())
20813 // Check whether a boolean test is testing a boolean value generated by
20814 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
20817 // Simplify the following patterns:
20818 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
20819 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
20820 // to (Op EFLAGS Cond)
20822 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
20823 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
20824 // to (Op EFLAGS !Cond)
20826 // where Op could be BRCOND or CMOV.
20828 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
20829 // Quit if not CMP and SUB with its value result used.
20830 if (Cmp.getOpcode() != X86ISD::CMP &&
20831 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
20834 // Quit if not used as a boolean value.
20835 if (CC != X86::COND_E && CC != X86::COND_NE)
20838 // Check CMP operands. One of them should be 0 or 1 and the other should be
20839 // an SetCC or extended from it.
20840 SDValue Op1 = Cmp.getOperand(0);
20841 SDValue Op2 = Cmp.getOperand(1);
20844 const ConstantSDNode* C = nullptr;
20845 bool needOppositeCond = (CC == X86::COND_E);
20846 bool checkAgainstTrue = false; // Is it a comparison against 1?
20848 if ((C = dyn_cast<ConstantSDNode>(Op1)))
20850 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
20852 else // Quit if all operands are not constants.
20855 if (C->getZExtValue() == 1) {
20856 needOppositeCond = !needOppositeCond;
20857 checkAgainstTrue = true;
20858 } else if (C->getZExtValue() != 0)
20859 // Quit if the constant is neither 0 or 1.
20862 bool truncatedToBoolWithAnd = false;
20863 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
20864 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
20865 SetCC.getOpcode() == ISD::TRUNCATE ||
20866 SetCC.getOpcode() == ISD::AND) {
20867 if (SetCC.getOpcode() == ISD::AND) {
20869 ConstantSDNode *CS;
20870 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
20871 CS->getZExtValue() == 1)
20873 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
20874 CS->getZExtValue() == 1)
20878 SetCC = SetCC.getOperand(OpIdx);
20879 truncatedToBoolWithAnd = true;
20881 SetCC = SetCC.getOperand(0);
20884 switch (SetCC.getOpcode()) {
20885 case X86ISD::SETCC_CARRY:
20886 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
20887 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
20888 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
20889 // truncated to i1 using 'and'.
20890 if (checkAgainstTrue && !truncatedToBoolWithAnd)
20892 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
20893 "Invalid use of SETCC_CARRY!");
20895 case X86ISD::SETCC:
20896 // Set the condition code or opposite one if necessary.
20897 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
20898 if (needOppositeCond)
20899 CC = X86::GetOppositeBranchCondition(CC);
20900 return SetCC.getOperand(1);
20901 case X86ISD::CMOV: {
20902 // Check whether false/true value has canonical one, i.e. 0 or 1.
20903 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
20904 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
20905 // Quit if true value is not a constant.
20908 // Quit if false value is not a constant.
20910 SDValue Op = SetCC.getOperand(0);
20911 // Skip 'zext' or 'trunc' node.
20912 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
20913 Op.getOpcode() == ISD::TRUNCATE)
20914 Op = Op.getOperand(0);
20915 // A special case for rdrand/rdseed, where 0 is set if false cond is
20917 if ((Op.getOpcode() != X86ISD::RDRAND &&
20918 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
20921 // Quit if false value is not the constant 0 or 1.
20922 bool FValIsFalse = true;
20923 if (FVal && FVal->getZExtValue() != 0) {
20924 if (FVal->getZExtValue() != 1)
20926 // If FVal is 1, opposite cond is needed.
20927 needOppositeCond = !needOppositeCond;
20928 FValIsFalse = false;
20930 // Quit if TVal is not the constant opposite of FVal.
20931 if (FValIsFalse && TVal->getZExtValue() != 1)
20933 if (!FValIsFalse && TVal->getZExtValue() != 0)
20935 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
20936 if (needOppositeCond)
20937 CC = X86::GetOppositeBranchCondition(CC);
20938 return SetCC.getOperand(3);
20945 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
20946 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
20947 TargetLowering::DAGCombinerInfo &DCI,
20948 const X86Subtarget *Subtarget) {
20951 // If the flag operand isn't dead, don't touch this CMOV.
20952 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
20955 SDValue FalseOp = N->getOperand(0);
20956 SDValue TrueOp = N->getOperand(1);
20957 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
20958 SDValue Cond = N->getOperand(3);
20960 if (CC == X86::COND_E || CC == X86::COND_NE) {
20961 switch (Cond.getOpcode()) {
20965 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
20966 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
20967 return (CC == X86::COND_E) ? FalseOp : TrueOp;
20973 Flags = checkBoolTestSetCCCombine(Cond, CC);
20974 if (Flags.getNode() &&
20975 // Extra check as FCMOV only supports a subset of X86 cond.
20976 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
20977 SDValue Ops[] = { FalseOp, TrueOp,
20978 DAG.getConstant(CC, MVT::i8), Flags };
20979 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
20982 // If this is a select between two integer constants, try to do some
20983 // optimizations. Note that the operands are ordered the opposite of SELECT
20985 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
20986 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
20987 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
20988 // larger than FalseC (the false value).
20989 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
20990 CC = X86::GetOppositeBranchCondition(CC);
20991 std::swap(TrueC, FalseC);
20992 std::swap(TrueOp, FalseOp);
20995 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
20996 // This is efficient for any integer data type (including i8/i16) and
20998 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
20999 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21000 DAG.getConstant(CC, MVT::i8), Cond);
21002 // Zero extend the condition if needed.
21003 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21005 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21006 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21007 DAG.getConstant(ShAmt, MVT::i8));
21008 if (N->getNumValues() == 2) // Dead flag value?
21009 return DCI.CombineTo(N, Cond, SDValue());
21013 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21014 // for any integer data type, including i8/i16.
21015 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21016 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21017 DAG.getConstant(CC, MVT::i8), Cond);
21019 // Zero extend the condition if needed.
21020 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21021 FalseC->getValueType(0), Cond);
21022 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21023 SDValue(FalseC, 0));
21025 if (N->getNumValues() == 2) // Dead flag value?
21026 return DCI.CombineTo(N, Cond, SDValue());
21030 // Optimize cases that will turn into an LEA instruction. This requires
21031 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21032 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21033 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21034 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21036 bool isFastMultiplier = false;
21038 switch ((unsigned char)Diff) {
21040 case 1: // result = add base, cond
21041 case 2: // result = lea base( , cond*2)
21042 case 3: // result = lea base(cond, cond*2)
21043 case 4: // result = lea base( , cond*4)
21044 case 5: // result = lea base(cond, cond*4)
21045 case 8: // result = lea base( , cond*8)
21046 case 9: // result = lea base(cond, cond*8)
21047 isFastMultiplier = true;
21052 if (isFastMultiplier) {
21053 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21054 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21055 DAG.getConstant(CC, MVT::i8), Cond);
21056 // Zero extend the condition if needed.
21057 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21059 // Scale the condition by the difference.
21061 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21062 DAG.getConstant(Diff, Cond.getValueType()));
21064 // Add the base if non-zero.
21065 if (FalseC->getAPIntValue() != 0)
21066 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21067 SDValue(FalseC, 0));
21068 if (N->getNumValues() == 2) // Dead flag value?
21069 return DCI.CombineTo(N, Cond, SDValue());
21076 // Handle these cases:
21077 // (select (x != c), e, c) -> select (x != c), e, x),
21078 // (select (x == c), c, e) -> select (x == c), x, e)
21079 // where the c is an integer constant, and the "select" is the combination
21080 // of CMOV and CMP.
21082 // The rationale for this change is that the conditional-move from a constant
21083 // needs two instructions, however, conditional-move from a register needs
21084 // only one instruction.
21086 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
21087 // some instruction-combining opportunities. This opt needs to be
21088 // postponed as late as possible.
21090 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
21091 // the DCI.xxxx conditions are provided to postpone the optimization as
21092 // late as possible.
21094 ConstantSDNode *CmpAgainst = nullptr;
21095 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
21096 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
21097 !isa<ConstantSDNode>(Cond.getOperand(0))) {
21099 if (CC == X86::COND_NE &&
21100 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
21101 CC = X86::GetOppositeBranchCondition(CC);
21102 std::swap(TrueOp, FalseOp);
21105 if (CC == X86::COND_E &&
21106 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
21107 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
21108 DAG.getConstant(CC, MVT::i8), Cond };
21109 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
21117 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
21118 const X86Subtarget *Subtarget) {
21119 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
21121 default: return SDValue();
21122 // SSE/AVX/AVX2 blend intrinsics.
21123 case Intrinsic::x86_avx2_pblendvb:
21124 case Intrinsic::x86_avx2_pblendw:
21125 case Intrinsic::x86_avx2_pblendd_128:
21126 case Intrinsic::x86_avx2_pblendd_256:
21127 // Don't try to simplify this intrinsic if we don't have AVX2.
21128 if (!Subtarget->hasAVX2())
21131 case Intrinsic::x86_avx_blend_pd_256:
21132 case Intrinsic::x86_avx_blend_ps_256:
21133 case Intrinsic::x86_avx_blendv_pd_256:
21134 case Intrinsic::x86_avx_blendv_ps_256:
21135 // Don't try to simplify this intrinsic if we don't have AVX.
21136 if (!Subtarget->hasAVX())
21139 case Intrinsic::x86_sse41_pblendw:
21140 case Intrinsic::x86_sse41_blendpd:
21141 case Intrinsic::x86_sse41_blendps:
21142 case Intrinsic::x86_sse41_blendvps:
21143 case Intrinsic::x86_sse41_blendvpd:
21144 case Intrinsic::x86_sse41_pblendvb: {
21145 SDValue Op0 = N->getOperand(1);
21146 SDValue Op1 = N->getOperand(2);
21147 SDValue Mask = N->getOperand(3);
21149 // Don't try to simplify this intrinsic if we don't have SSE4.1.
21150 if (!Subtarget->hasSSE41())
21153 // fold (blend A, A, Mask) -> A
21156 // fold (blend A, B, allZeros) -> A
21157 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
21159 // fold (blend A, B, allOnes) -> B
21160 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
21163 // Simplify the case where the mask is a constant i32 value.
21164 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
21165 if (C->isNullValue())
21167 if (C->isAllOnesValue())
21174 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
21175 case Intrinsic::x86_sse2_psrai_w:
21176 case Intrinsic::x86_sse2_psrai_d:
21177 case Intrinsic::x86_avx2_psrai_w:
21178 case Intrinsic::x86_avx2_psrai_d:
21179 case Intrinsic::x86_sse2_psra_w:
21180 case Intrinsic::x86_sse2_psra_d:
21181 case Intrinsic::x86_avx2_psra_w:
21182 case Intrinsic::x86_avx2_psra_d: {
21183 SDValue Op0 = N->getOperand(1);
21184 SDValue Op1 = N->getOperand(2);
21185 EVT VT = Op0.getValueType();
21186 assert(VT.isVector() && "Expected a vector type!");
21188 if (isa<BuildVectorSDNode>(Op1))
21189 Op1 = Op1.getOperand(0);
21191 if (!isa<ConstantSDNode>(Op1))
21194 EVT SVT = VT.getVectorElementType();
21195 unsigned SVTBits = SVT.getSizeInBits();
21197 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
21198 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
21199 uint64_t ShAmt = C.getZExtValue();
21201 // Don't try to convert this shift into a ISD::SRA if the shift
21202 // count is bigger than or equal to the element size.
21203 if (ShAmt >= SVTBits)
21206 // Trivial case: if the shift count is zero, then fold this
21207 // into the first operand.
21211 // Replace this packed shift intrinsic with a target independent
21213 SDValue Splat = DAG.getConstant(C, VT);
21214 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
21219 /// PerformMulCombine - Optimize a single multiply with constant into two
21220 /// in order to implement it with two cheaper instructions, e.g.
21221 /// LEA + SHL, LEA + LEA.
21222 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
21223 TargetLowering::DAGCombinerInfo &DCI) {
21224 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
21227 EVT VT = N->getValueType(0);
21228 if (VT != MVT::i64 && VT != MVT::i32)
21231 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
21234 uint64_t MulAmt = C->getZExtValue();
21235 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
21238 uint64_t MulAmt1 = 0;
21239 uint64_t MulAmt2 = 0;
21240 if ((MulAmt % 9) == 0) {
21242 MulAmt2 = MulAmt / 9;
21243 } else if ((MulAmt % 5) == 0) {
21245 MulAmt2 = MulAmt / 5;
21246 } else if ((MulAmt % 3) == 0) {
21248 MulAmt2 = MulAmt / 3;
21251 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
21254 if (isPowerOf2_64(MulAmt2) &&
21255 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
21256 // If second multiplifer is pow2, issue it first. We want the multiply by
21257 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
21259 std::swap(MulAmt1, MulAmt2);
21262 if (isPowerOf2_64(MulAmt1))
21263 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
21264 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
21266 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
21267 DAG.getConstant(MulAmt1, VT));
21269 if (isPowerOf2_64(MulAmt2))
21270 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
21271 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
21273 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
21274 DAG.getConstant(MulAmt2, VT));
21276 // Do not add new nodes to DAG combiner worklist.
21277 DCI.CombineTo(N, NewMul, false);
21282 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
21283 SDValue N0 = N->getOperand(0);
21284 SDValue N1 = N->getOperand(1);
21285 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
21286 EVT VT = N0.getValueType();
21288 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
21289 // since the result of setcc_c is all zero's or all ones.
21290 if (VT.isInteger() && !VT.isVector() &&
21291 N1C && N0.getOpcode() == ISD::AND &&
21292 N0.getOperand(1).getOpcode() == ISD::Constant) {
21293 SDValue N00 = N0.getOperand(0);
21294 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
21295 ((N00.getOpcode() == ISD::ANY_EXTEND ||
21296 N00.getOpcode() == ISD::ZERO_EXTEND) &&
21297 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
21298 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
21299 APInt ShAmt = N1C->getAPIntValue();
21300 Mask = Mask.shl(ShAmt);
21302 return DAG.getNode(ISD::AND, SDLoc(N), VT,
21303 N00, DAG.getConstant(Mask, VT));
21307 // Hardware support for vector shifts is sparse which makes us scalarize the
21308 // vector operations in many cases. Also, on sandybridge ADD is faster than
21310 // (shl V, 1) -> add V,V
21311 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
21312 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
21313 assert(N0.getValueType().isVector() && "Invalid vector shift type");
21314 // We shift all of the values by one. In many cases we do not have
21315 // hardware support for this operation. This is better expressed as an ADD
21317 if (N1SplatC->getZExtValue() == 1)
21318 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
21324 /// \brief Returns a vector of 0s if the node in input is a vector logical
21325 /// shift by a constant amount which is known to be bigger than or equal
21326 /// to the vector element size in bits.
21327 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
21328 const X86Subtarget *Subtarget) {
21329 EVT VT = N->getValueType(0);
21331 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
21332 (!Subtarget->hasInt256() ||
21333 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
21336 SDValue Amt = N->getOperand(1);
21338 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
21339 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
21340 APInt ShiftAmt = AmtSplat->getAPIntValue();
21341 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
21343 // SSE2/AVX2 logical shifts always return a vector of 0s
21344 // if the shift amount is bigger than or equal to
21345 // the element size. The constant shift amount will be
21346 // encoded as a 8-bit immediate.
21347 if (ShiftAmt.trunc(8).uge(MaxAmount))
21348 return getZeroVector(VT, Subtarget, DAG, DL);
21354 /// PerformShiftCombine - Combine shifts.
21355 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
21356 TargetLowering::DAGCombinerInfo &DCI,
21357 const X86Subtarget *Subtarget) {
21358 if (N->getOpcode() == ISD::SHL) {
21359 SDValue V = PerformSHLCombine(N, DAG);
21360 if (V.getNode()) return V;
21363 if (N->getOpcode() != ISD::SRA) {
21364 // Try to fold this logical shift into a zero vector.
21365 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
21366 if (V.getNode()) return V;
21372 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
21373 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
21374 // and friends. Likewise for OR -> CMPNEQSS.
21375 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
21376 TargetLowering::DAGCombinerInfo &DCI,
21377 const X86Subtarget *Subtarget) {
21380 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
21381 // we're requiring SSE2 for both.
21382 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
21383 SDValue N0 = N->getOperand(0);
21384 SDValue N1 = N->getOperand(1);
21385 SDValue CMP0 = N0->getOperand(1);
21386 SDValue CMP1 = N1->getOperand(1);
21389 // The SETCCs should both refer to the same CMP.
21390 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
21393 SDValue CMP00 = CMP0->getOperand(0);
21394 SDValue CMP01 = CMP0->getOperand(1);
21395 EVT VT = CMP00.getValueType();
21397 if (VT == MVT::f32 || VT == MVT::f64) {
21398 bool ExpectingFlags = false;
21399 // Check for any users that want flags:
21400 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
21401 !ExpectingFlags && UI != UE; ++UI)
21402 switch (UI->getOpcode()) {
21407 ExpectingFlags = true;
21409 case ISD::CopyToReg:
21410 case ISD::SIGN_EXTEND:
21411 case ISD::ZERO_EXTEND:
21412 case ISD::ANY_EXTEND:
21416 if (!ExpectingFlags) {
21417 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
21418 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
21420 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
21421 X86::CondCode tmp = cc0;
21426 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
21427 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
21428 // FIXME: need symbolic constants for these magic numbers.
21429 // See X86ATTInstPrinter.cpp:printSSECC().
21430 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
21431 if (Subtarget->hasAVX512()) {
21432 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
21433 CMP01, DAG.getConstant(x86cc, MVT::i8));
21434 if (N->getValueType(0) != MVT::i1)
21435 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
21439 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
21440 CMP00.getValueType(), CMP00, CMP01,
21441 DAG.getConstant(x86cc, MVT::i8));
21443 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
21444 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
21446 if (is64BitFP && !Subtarget->is64Bit()) {
21447 // On a 32-bit target, we cannot bitcast the 64-bit float to a
21448 // 64-bit integer, since that's not a legal type. Since
21449 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
21450 // bits, but can do this little dance to extract the lowest 32 bits
21451 // and work with those going forward.
21452 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
21454 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
21456 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
21457 Vector32, DAG.getIntPtrConstant(0));
21461 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
21462 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
21463 DAG.getConstant(1, IntVT));
21464 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
21465 return OneBitOfTruth;
21473 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
21474 /// so it can be folded inside ANDNP.
21475 static bool CanFoldXORWithAllOnes(const SDNode *N) {
21476 EVT VT = N->getValueType(0);
21478 // Match direct AllOnes for 128 and 256-bit vectors
21479 if (ISD::isBuildVectorAllOnes(N))
21482 // Look through a bit convert.
21483 if (N->getOpcode() == ISD::BITCAST)
21484 N = N->getOperand(0).getNode();
21486 // Sometimes the operand may come from a insert_subvector building a 256-bit
21488 if (VT.is256BitVector() &&
21489 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
21490 SDValue V1 = N->getOperand(0);
21491 SDValue V2 = N->getOperand(1);
21493 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
21494 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
21495 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
21496 ISD::isBuildVectorAllOnes(V2.getNode()))
21503 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
21504 // register. In most cases we actually compare or select YMM-sized registers
21505 // and mixing the two types creates horrible code. This method optimizes
21506 // some of the transition sequences.
21507 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
21508 TargetLowering::DAGCombinerInfo &DCI,
21509 const X86Subtarget *Subtarget) {
21510 EVT VT = N->getValueType(0);
21511 if (!VT.is256BitVector())
21514 assert((N->getOpcode() == ISD::ANY_EXTEND ||
21515 N->getOpcode() == ISD::ZERO_EXTEND ||
21516 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
21518 SDValue Narrow = N->getOperand(0);
21519 EVT NarrowVT = Narrow->getValueType(0);
21520 if (!NarrowVT.is128BitVector())
21523 if (Narrow->getOpcode() != ISD::XOR &&
21524 Narrow->getOpcode() != ISD::AND &&
21525 Narrow->getOpcode() != ISD::OR)
21528 SDValue N0 = Narrow->getOperand(0);
21529 SDValue N1 = Narrow->getOperand(1);
21532 // The Left side has to be a trunc.
21533 if (N0.getOpcode() != ISD::TRUNCATE)
21536 // The type of the truncated inputs.
21537 EVT WideVT = N0->getOperand(0)->getValueType(0);
21541 // The right side has to be a 'trunc' or a constant vector.
21542 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
21543 ConstantSDNode *RHSConstSplat = nullptr;
21544 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
21545 RHSConstSplat = RHSBV->getConstantSplatNode();
21546 if (!RHSTrunc && !RHSConstSplat)
21549 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21551 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
21554 // Set N0 and N1 to hold the inputs to the new wide operation.
21555 N0 = N0->getOperand(0);
21556 if (RHSConstSplat) {
21557 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
21558 SDValue(RHSConstSplat, 0));
21559 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
21560 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
21561 } else if (RHSTrunc) {
21562 N1 = N1->getOperand(0);
21565 // Generate the wide operation.
21566 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
21567 unsigned Opcode = N->getOpcode();
21569 case ISD::ANY_EXTEND:
21571 case ISD::ZERO_EXTEND: {
21572 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
21573 APInt Mask = APInt::getAllOnesValue(InBits);
21574 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
21575 return DAG.getNode(ISD::AND, DL, VT,
21576 Op, DAG.getConstant(Mask, VT));
21578 case ISD::SIGN_EXTEND:
21579 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
21580 Op, DAG.getValueType(NarrowVT));
21582 llvm_unreachable("Unexpected opcode");
21586 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
21587 TargetLowering::DAGCombinerInfo &DCI,
21588 const X86Subtarget *Subtarget) {
21589 SDValue N0 = N->getOperand(0);
21590 SDValue N1 = N->getOperand(1);
21593 // A vector zext_in_reg may be represented as a shuffle,
21594 // feeding into a bitcast (this represents anyext) feeding into
21595 // an and with a mask.
21596 // We'd like to try to combine that into a shuffle with zero
21597 // plus a bitcast, removing the and.
21598 if (N0.getOpcode() != ISD::BITCAST ||
21599 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
21602 // The other side of the AND should be a splat of 2^C, where C
21603 // is the number of bits in the source type.
21604 if (N1.getOpcode() == ISD::BITCAST)
21605 N1 = N1.getOperand(0);
21606 if (N1.getOpcode() != ISD::BUILD_VECTOR)
21608 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
21610 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
21611 EVT SrcType = Shuffle->getValueType(0);
21613 // We expect a single-source shuffle
21614 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
21617 unsigned SrcSize = SrcType.getScalarSizeInBits();
21619 APInt SplatValue, SplatUndef;
21620 unsigned SplatBitSize;
21622 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
21623 SplatBitSize, HasAnyUndefs))
21626 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
21627 // Make sure the splat matches the mask we expect
21628 if (SplatBitSize > ResSize ||
21629 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
21632 // Make sure the input and output size make sense
21633 if (SrcSize >= ResSize || ResSize % SrcSize)
21636 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
21637 // The number of u's between each two values depends on the ratio between
21638 // the source and dest type.
21639 unsigned ZextRatio = ResSize / SrcSize;
21640 bool IsZext = true;
21641 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
21642 if (i % ZextRatio) {
21643 if (Shuffle->getMaskElt(i) > 0) {
21649 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
21650 // Expected element number
21660 // Ok, perform the transformation - replace the shuffle with
21661 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
21662 // (instead of undef) where the k elements come from the zero vector.
21663 SmallVector<int, 8> Mask;
21664 unsigned NumElems = SrcType.getVectorNumElements();
21665 for (unsigned i = 0; i < NumElems; ++i)
21667 Mask.push_back(NumElems);
21669 Mask.push_back(i / ZextRatio);
21671 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
21672 Shuffle->getOperand(0), DAG.getConstant(0, SrcType), Mask);
21673 return DAG.getNode(ISD::BITCAST, DL, N0.getValueType(), NewShuffle);
21676 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
21677 TargetLowering::DAGCombinerInfo &DCI,
21678 const X86Subtarget *Subtarget) {
21679 if (DCI.isBeforeLegalizeOps())
21682 SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget);
21683 if (Zext.getNode())
21686 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21690 EVT VT = N->getValueType(0);
21691 SDValue N0 = N->getOperand(0);
21692 SDValue N1 = N->getOperand(1);
21695 // Create BEXTR instructions
21696 // BEXTR is ((X >> imm) & (2**size-1))
21697 if (VT == MVT::i32 || VT == MVT::i64) {
21698 // Check for BEXTR.
21699 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
21700 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
21701 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
21702 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
21703 if (MaskNode && ShiftNode) {
21704 uint64_t Mask = MaskNode->getZExtValue();
21705 uint64_t Shift = ShiftNode->getZExtValue();
21706 if (isMask_64(Mask)) {
21707 uint64_t MaskSize = countPopulation(Mask);
21708 if (Shift + MaskSize <= VT.getSizeInBits())
21709 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
21710 DAG.getConstant(Shift | (MaskSize << 8), VT));
21718 // Want to form ANDNP nodes:
21719 // 1) In the hopes of then easily combining them with OR and AND nodes
21720 // to form PBLEND/PSIGN.
21721 // 2) To match ANDN packed intrinsics
21722 if (VT != MVT::v2i64 && VT != MVT::v4i64)
21725 // Check LHS for vnot
21726 if (N0.getOpcode() == ISD::XOR &&
21727 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
21728 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
21729 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
21731 // Check RHS for vnot
21732 if (N1.getOpcode() == ISD::XOR &&
21733 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
21734 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
21735 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
21740 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
21741 TargetLowering::DAGCombinerInfo &DCI,
21742 const X86Subtarget *Subtarget) {
21743 if (DCI.isBeforeLegalizeOps())
21746 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21750 SDValue N0 = N->getOperand(0);
21751 SDValue N1 = N->getOperand(1);
21752 EVT VT = N->getValueType(0);
21754 // look for psign/blend
21755 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
21756 if (!Subtarget->hasSSSE3() ||
21757 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
21760 // Canonicalize pandn to RHS
21761 if (N0.getOpcode() == X86ISD::ANDNP)
21763 // or (and (m, y), (pandn m, x))
21764 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
21765 SDValue Mask = N1.getOperand(0);
21766 SDValue X = N1.getOperand(1);
21768 if (N0.getOperand(0) == Mask)
21769 Y = N0.getOperand(1);
21770 if (N0.getOperand(1) == Mask)
21771 Y = N0.getOperand(0);
21773 // Check to see if the mask appeared in both the AND and ANDNP and
21777 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
21778 // Look through mask bitcast.
21779 if (Mask.getOpcode() == ISD::BITCAST)
21780 Mask = Mask.getOperand(0);
21781 if (X.getOpcode() == ISD::BITCAST)
21782 X = X.getOperand(0);
21783 if (Y.getOpcode() == ISD::BITCAST)
21784 Y = Y.getOperand(0);
21786 EVT MaskVT = Mask.getValueType();
21788 // Validate that the Mask operand is a vector sra node.
21789 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
21790 // there is no psrai.b
21791 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
21792 unsigned SraAmt = ~0;
21793 if (Mask.getOpcode() == ISD::SRA) {
21794 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
21795 if (auto *AmtConst = AmtBV->getConstantSplatNode())
21796 SraAmt = AmtConst->getZExtValue();
21797 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
21798 SDValue SraC = Mask.getOperand(1);
21799 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
21801 if ((SraAmt + 1) != EltBits)
21806 // Now we know we at least have a plendvb with the mask val. See if
21807 // we can form a psignb/w/d.
21808 // psign = x.type == y.type == mask.type && y = sub(0, x);
21809 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
21810 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
21811 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
21812 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
21813 "Unsupported VT for PSIGN");
21814 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
21815 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21817 // PBLENDVB only available on SSE 4.1
21818 if (!Subtarget->hasSSE41())
21821 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
21823 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
21824 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
21825 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
21826 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
21827 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21831 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
21834 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
21835 MachineFunction &MF = DAG.getMachineFunction();
21837 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
21839 // SHLD/SHRD instructions have lower register pressure, but on some
21840 // platforms they have higher latency than the equivalent
21841 // series of shifts/or that would otherwise be generated.
21842 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
21843 // have higher latencies and we are not optimizing for size.
21844 if (!OptForSize && Subtarget->isSHLDSlow())
21847 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
21849 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
21851 if (!N0.hasOneUse() || !N1.hasOneUse())
21854 SDValue ShAmt0 = N0.getOperand(1);
21855 if (ShAmt0.getValueType() != MVT::i8)
21857 SDValue ShAmt1 = N1.getOperand(1);
21858 if (ShAmt1.getValueType() != MVT::i8)
21860 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
21861 ShAmt0 = ShAmt0.getOperand(0);
21862 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
21863 ShAmt1 = ShAmt1.getOperand(0);
21866 unsigned Opc = X86ISD::SHLD;
21867 SDValue Op0 = N0.getOperand(0);
21868 SDValue Op1 = N1.getOperand(0);
21869 if (ShAmt0.getOpcode() == ISD::SUB) {
21870 Opc = X86ISD::SHRD;
21871 std::swap(Op0, Op1);
21872 std::swap(ShAmt0, ShAmt1);
21875 unsigned Bits = VT.getSizeInBits();
21876 if (ShAmt1.getOpcode() == ISD::SUB) {
21877 SDValue Sum = ShAmt1.getOperand(0);
21878 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
21879 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
21880 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
21881 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
21882 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
21883 return DAG.getNode(Opc, DL, VT,
21885 DAG.getNode(ISD::TRUNCATE, DL,
21888 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
21889 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
21891 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
21892 return DAG.getNode(Opc, DL, VT,
21893 N0.getOperand(0), N1.getOperand(0),
21894 DAG.getNode(ISD::TRUNCATE, DL,
21901 // Generate NEG and CMOV for integer abs.
21902 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
21903 EVT VT = N->getValueType(0);
21905 // Since X86 does not have CMOV for 8-bit integer, we don't convert
21906 // 8-bit integer abs to NEG and CMOV.
21907 if (VT.isInteger() && VT.getSizeInBits() == 8)
21910 SDValue N0 = N->getOperand(0);
21911 SDValue N1 = N->getOperand(1);
21914 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
21915 // and change it to SUB and CMOV.
21916 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
21917 N0.getOpcode() == ISD::ADD &&
21918 N0.getOperand(1) == N1 &&
21919 N1.getOpcode() == ISD::SRA &&
21920 N1.getOperand(0) == N0.getOperand(0))
21921 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
21922 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
21923 // Generate SUB & CMOV.
21924 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
21925 DAG.getConstant(0, VT), N0.getOperand(0));
21927 SDValue Ops[] = { N0.getOperand(0), Neg,
21928 DAG.getConstant(X86::COND_GE, MVT::i8),
21929 SDValue(Neg.getNode(), 1) };
21930 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
21935 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
21936 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
21937 TargetLowering::DAGCombinerInfo &DCI,
21938 const X86Subtarget *Subtarget) {
21939 if (DCI.isBeforeLegalizeOps())
21942 if (Subtarget->hasCMov()) {
21943 SDValue RV = performIntegerAbsCombine(N, DAG);
21951 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
21952 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
21953 TargetLowering::DAGCombinerInfo &DCI,
21954 const X86Subtarget *Subtarget) {
21955 LoadSDNode *Ld = cast<LoadSDNode>(N);
21956 EVT RegVT = Ld->getValueType(0);
21957 EVT MemVT = Ld->getMemoryVT();
21959 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21961 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
21962 // into two 16-byte operations.
21963 ISD::LoadExtType Ext = Ld->getExtensionType();
21964 unsigned Alignment = Ld->getAlignment();
21965 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
21966 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
21967 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
21968 unsigned NumElems = RegVT.getVectorNumElements();
21972 SDValue Ptr = Ld->getBasePtr();
21973 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
21975 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
21977 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
21978 Ld->getPointerInfo(), Ld->isVolatile(),
21979 Ld->isNonTemporal(), Ld->isInvariant(),
21981 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
21982 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
21983 Ld->getPointerInfo(), Ld->isVolatile(),
21984 Ld->isNonTemporal(), Ld->isInvariant(),
21985 std::min(16U, Alignment));
21986 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21988 Load2.getValue(1));
21990 SDValue NewVec = DAG.getUNDEF(RegVT);
21991 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
21992 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
21993 return DCI.CombineTo(N, NewVec, TF, true);
21999 /// PerformMLOADCombine - Resolve extending loads
22000 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
22001 TargetLowering::DAGCombinerInfo &DCI,
22002 const X86Subtarget *Subtarget) {
22003 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
22004 if (Mld->getExtensionType() != ISD::SEXTLOAD)
22007 EVT VT = Mld->getValueType(0);
22008 unsigned NumElems = VT.getVectorNumElements();
22009 EVT LdVT = Mld->getMemoryVT();
22012 assert(LdVT != VT && "Cannot extend to the same type");
22013 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
22014 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
22015 // From, To sizes and ElemCount must be pow of two
22016 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
22017 "Unexpected size for extending masked load");
22019 unsigned SizeRatio = ToSz / FromSz;
22020 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
22022 // Create a type on which we perform the shuffle
22023 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22024 LdVT.getScalarType(), NumElems*SizeRatio);
22025 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22027 // Convert Src0 value
22028 SDValue WideSrc0 = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mld->getSrc0());
22029 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
22030 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22031 for (unsigned i = 0; i != NumElems; ++i)
22032 ShuffleVec[i] = i * SizeRatio;
22034 // Can't shuffle using an illegal type.
22035 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
22036 && "WideVecVT should be legal");
22037 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
22038 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
22040 // Prepare the new mask
22042 SDValue Mask = Mld->getMask();
22043 if (Mask.getValueType() == VT) {
22044 // Mask and original value have the same type
22045 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
22046 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22047 for (unsigned i = 0; i != NumElems; ++i)
22048 ShuffleVec[i] = i * SizeRatio;
22049 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
22050 ShuffleVec[i] = NumElems*SizeRatio;
22051 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
22052 DAG.getConstant(0, WideVecVT),
22056 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
22057 unsigned WidenNumElts = NumElems*SizeRatio;
22058 unsigned MaskNumElts = VT.getVectorNumElements();
22059 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
22062 unsigned NumConcat = WidenNumElts / MaskNumElts;
22063 SmallVector<SDValue, 16> Ops(NumConcat);
22064 SDValue ZeroVal = DAG.getConstant(0, Mask.getValueType());
22066 for (unsigned i = 1; i != NumConcat; ++i)
22069 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
22072 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
22073 Mld->getBasePtr(), NewMask, WideSrc0,
22074 Mld->getMemoryVT(), Mld->getMemOperand(),
22076 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
22077 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
22080 /// PerformMSTORECombine - Resolve truncating stores
22081 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
22082 const X86Subtarget *Subtarget) {
22083 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
22084 if (!Mst->isTruncatingStore())
22087 EVT VT = Mst->getValue().getValueType();
22088 unsigned NumElems = VT.getVectorNumElements();
22089 EVT StVT = Mst->getMemoryVT();
22092 assert(StVT != VT && "Cannot truncate to the same type");
22093 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22094 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22096 // From, To sizes and ElemCount must be pow of two
22097 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
22098 "Unexpected size for truncating masked store");
22099 // We are going to use the original vector elt for storing.
22100 // Accumulated smaller vector elements must be a multiple of the store size.
22101 assert (((NumElems * FromSz) % ToSz) == 0 &&
22102 "Unexpected ratio for truncating masked store");
22104 unsigned SizeRatio = FromSz / ToSz;
22105 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22107 // Create a type on which we perform the shuffle
22108 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22109 StVT.getScalarType(), NumElems*SizeRatio);
22111 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22113 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mst->getValue());
22114 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22115 for (unsigned i = 0; i != NumElems; ++i)
22116 ShuffleVec[i] = i * SizeRatio;
22118 // Can't shuffle using an illegal type.
22119 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
22120 && "WideVecVT should be legal");
22122 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22123 DAG.getUNDEF(WideVecVT),
22127 SDValue Mask = Mst->getMask();
22128 if (Mask.getValueType() == VT) {
22129 // Mask and original value have the same type
22130 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
22131 for (unsigned i = 0; i != NumElems; ++i)
22132 ShuffleVec[i] = i * SizeRatio;
22133 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
22134 ShuffleVec[i] = NumElems*SizeRatio;
22135 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
22136 DAG.getConstant(0, WideVecVT),
22140 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
22141 unsigned WidenNumElts = NumElems*SizeRatio;
22142 unsigned MaskNumElts = VT.getVectorNumElements();
22143 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
22146 unsigned NumConcat = WidenNumElts / MaskNumElts;
22147 SmallVector<SDValue, 16> Ops(NumConcat);
22148 SDValue ZeroVal = DAG.getConstant(0, Mask.getValueType());
22150 for (unsigned i = 1; i != NumConcat; ++i)
22153 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
22156 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
22157 NewMask, StVT, Mst->getMemOperand(), false);
22159 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
22160 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
22161 const X86Subtarget *Subtarget) {
22162 StoreSDNode *St = cast<StoreSDNode>(N);
22163 EVT VT = St->getValue().getValueType();
22164 EVT StVT = St->getMemoryVT();
22166 SDValue StoredVal = St->getOperand(1);
22167 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22169 // If we are saving a concatenation of two XMM registers and 32-byte stores
22170 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
22171 unsigned Alignment = St->getAlignment();
22172 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22173 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
22174 StVT == VT && !IsAligned) {
22175 unsigned NumElems = VT.getVectorNumElements();
22179 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22180 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22182 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
22183 SDValue Ptr0 = St->getBasePtr();
22184 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22186 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22187 St->getPointerInfo(), St->isVolatile(),
22188 St->isNonTemporal(), Alignment);
22189 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22190 St->getPointerInfo(), St->isVolatile(),
22191 St->isNonTemporal(),
22192 std::min(16U, Alignment));
22193 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22196 // Optimize trunc store (of multiple scalars) to shuffle and store.
22197 // First, pack all of the elements in one place. Next, store to memory
22198 // in fewer chunks.
22199 if (St->isTruncatingStore() && VT.isVector()) {
22200 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22201 unsigned NumElems = VT.getVectorNumElements();
22202 assert(StVT != VT && "Cannot truncate to the same type");
22203 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22204 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22206 // From, To sizes and ElemCount must be pow of two
22207 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
22208 // We are going to use the original vector elt for storing.
22209 // Accumulated smaller vector elements must be a multiple of the store size.
22210 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
22212 unsigned SizeRatio = FromSz / ToSz;
22214 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22216 // Create a type on which we perform the shuffle
22217 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22218 StVT.getScalarType(), NumElems*SizeRatio);
22220 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22222 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
22223 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
22224 for (unsigned i = 0; i != NumElems; ++i)
22225 ShuffleVec[i] = i * SizeRatio;
22227 // Can't shuffle using an illegal type.
22228 if (!TLI.isTypeLegal(WideVecVT))
22231 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22232 DAG.getUNDEF(WideVecVT),
22234 // At this point all of the data is stored at the bottom of the
22235 // register. We now need to save it to mem.
22237 // Find the largest store unit
22238 MVT StoreType = MVT::i8;
22239 for (MVT Tp : MVT::integer_valuetypes()) {
22240 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
22244 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
22245 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
22246 (64 <= NumElems * ToSz))
22247 StoreType = MVT::f64;
22249 // Bitcast the original vector into a vector of store-size units
22250 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
22251 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
22252 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
22253 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
22254 SmallVector<SDValue, 8> Chains;
22255 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
22256 TLI.getPointerTy());
22257 SDValue Ptr = St->getBasePtr();
22259 // Perform one or more big stores into memory.
22260 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
22261 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
22262 StoreType, ShuffWide,
22263 DAG.getIntPtrConstant(i));
22264 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
22265 St->getPointerInfo(), St->isVolatile(),
22266 St->isNonTemporal(), St->getAlignment());
22267 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22268 Chains.push_back(Ch);
22271 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
22274 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
22275 // the FP state in cases where an emms may be missing.
22276 // A preferable solution to the general problem is to figure out the right
22277 // places to insert EMMS. This qualifies as a quick hack.
22279 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
22280 if (VT.getSizeInBits() != 64)
22283 const Function *F = DAG.getMachineFunction().getFunction();
22284 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
22285 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
22286 && Subtarget->hasSSE2();
22287 if ((VT.isVector() ||
22288 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
22289 isa<LoadSDNode>(St->getValue()) &&
22290 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
22291 St->getChain().hasOneUse() && !St->isVolatile()) {
22292 SDNode* LdVal = St->getValue().getNode();
22293 LoadSDNode *Ld = nullptr;
22294 int TokenFactorIndex = -1;
22295 SmallVector<SDValue, 8> Ops;
22296 SDNode* ChainVal = St->getChain().getNode();
22297 // Must be a store of a load. We currently handle two cases: the load
22298 // is a direct child, and it's under an intervening TokenFactor. It is
22299 // possible to dig deeper under nested TokenFactors.
22300 if (ChainVal == LdVal)
22301 Ld = cast<LoadSDNode>(St->getChain());
22302 else if (St->getValue().hasOneUse() &&
22303 ChainVal->getOpcode() == ISD::TokenFactor) {
22304 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
22305 if (ChainVal->getOperand(i).getNode() == LdVal) {
22306 TokenFactorIndex = i;
22307 Ld = cast<LoadSDNode>(St->getValue());
22309 Ops.push_back(ChainVal->getOperand(i));
22313 if (!Ld || !ISD::isNormalLoad(Ld))
22316 // If this is not the MMX case, i.e. we are just turning i64 load/store
22317 // into f64 load/store, avoid the transformation if there are multiple
22318 // uses of the loaded value.
22319 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
22324 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
22325 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
22327 if (Subtarget->is64Bit() || F64IsLegal) {
22328 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
22329 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
22330 Ld->getPointerInfo(), Ld->isVolatile(),
22331 Ld->isNonTemporal(), Ld->isInvariant(),
22332 Ld->getAlignment());
22333 SDValue NewChain = NewLd.getValue(1);
22334 if (TokenFactorIndex != -1) {
22335 Ops.push_back(NewChain);
22336 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22338 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
22339 St->getPointerInfo(),
22340 St->isVolatile(), St->isNonTemporal(),
22341 St->getAlignment());
22344 // Otherwise, lower to two pairs of 32-bit loads / stores.
22345 SDValue LoAddr = Ld->getBasePtr();
22346 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
22347 DAG.getConstant(4, MVT::i32));
22349 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
22350 Ld->getPointerInfo(),
22351 Ld->isVolatile(), Ld->isNonTemporal(),
22352 Ld->isInvariant(), Ld->getAlignment());
22353 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
22354 Ld->getPointerInfo().getWithOffset(4),
22355 Ld->isVolatile(), Ld->isNonTemporal(),
22357 MinAlign(Ld->getAlignment(), 4));
22359 SDValue NewChain = LoLd.getValue(1);
22360 if (TokenFactorIndex != -1) {
22361 Ops.push_back(LoLd);
22362 Ops.push_back(HiLd);
22363 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22366 LoAddr = St->getBasePtr();
22367 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
22368 DAG.getConstant(4, MVT::i32));
22370 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
22371 St->getPointerInfo(),
22372 St->isVolatile(), St->isNonTemporal(),
22373 St->getAlignment());
22374 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
22375 St->getPointerInfo().getWithOffset(4),
22377 St->isNonTemporal(),
22378 MinAlign(St->getAlignment(), 4));
22379 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
22384 /// Return 'true' if this vector operation is "horizontal"
22385 /// and return the operands for the horizontal operation in LHS and RHS. A
22386 /// horizontal operation performs the binary operation on successive elements
22387 /// of its first operand, then on successive elements of its second operand,
22388 /// returning the resulting values in a vector. For example, if
22389 /// A = < float a0, float a1, float a2, float a3 >
22391 /// B = < float b0, float b1, float b2, float b3 >
22392 /// then the result of doing a horizontal operation on A and B is
22393 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
22394 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
22395 /// A horizontal-op B, for some already available A and B, and if so then LHS is
22396 /// set to A, RHS to B, and the routine returns 'true'.
22397 /// Note that the binary operation should have the property that if one of the
22398 /// operands is UNDEF then the result is UNDEF.
22399 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
22400 // Look for the following pattern: if
22401 // A = < float a0, float a1, float a2, float a3 >
22402 // B = < float b0, float b1, float b2, float b3 >
22404 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
22405 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
22406 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
22407 // which is A horizontal-op B.
22409 // At least one of the operands should be a vector shuffle.
22410 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
22411 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
22414 MVT VT = LHS.getSimpleValueType();
22416 assert((VT.is128BitVector() || VT.is256BitVector()) &&
22417 "Unsupported vector type for horizontal add/sub");
22419 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
22420 // operate independently on 128-bit lanes.
22421 unsigned NumElts = VT.getVectorNumElements();
22422 unsigned NumLanes = VT.getSizeInBits()/128;
22423 unsigned NumLaneElts = NumElts / NumLanes;
22424 assert((NumLaneElts % 2 == 0) &&
22425 "Vector type should have an even number of elements in each lane");
22426 unsigned HalfLaneElts = NumLaneElts/2;
22428 // View LHS in the form
22429 // LHS = VECTOR_SHUFFLE A, B, LMask
22430 // If LHS is not a shuffle then pretend it is the shuffle
22431 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
22432 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
22435 SmallVector<int, 16> LMask(NumElts);
22436 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22437 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
22438 A = LHS.getOperand(0);
22439 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
22440 B = LHS.getOperand(1);
22441 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
22442 std::copy(Mask.begin(), Mask.end(), LMask.begin());
22444 if (LHS.getOpcode() != ISD::UNDEF)
22446 for (unsigned i = 0; i != NumElts; ++i)
22450 // Likewise, view RHS in the form
22451 // RHS = VECTOR_SHUFFLE C, D, RMask
22453 SmallVector<int, 16> RMask(NumElts);
22454 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22455 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
22456 C = RHS.getOperand(0);
22457 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
22458 D = RHS.getOperand(1);
22459 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
22460 std::copy(Mask.begin(), Mask.end(), RMask.begin());
22462 if (RHS.getOpcode() != ISD::UNDEF)
22464 for (unsigned i = 0; i != NumElts; ++i)
22468 // Check that the shuffles are both shuffling the same vectors.
22469 if (!(A == C && B == D) && !(A == D && B == C))
22472 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
22473 if (!A.getNode() && !B.getNode())
22476 // If A and B occur in reverse order in RHS, then "swap" them (which means
22477 // rewriting the mask).
22479 CommuteVectorShuffleMask(RMask, NumElts);
22481 // At this point LHS and RHS are equivalent to
22482 // LHS = VECTOR_SHUFFLE A, B, LMask
22483 // RHS = VECTOR_SHUFFLE A, B, RMask
22484 // Check that the masks correspond to performing a horizontal operation.
22485 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
22486 for (unsigned i = 0; i != NumLaneElts; ++i) {
22487 int LIdx = LMask[i+l], RIdx = RMask[i+l];
22489 // Ignore any UNDEF components.
22490 if (LIdx < 0 || RIdx < 0 ||
22491 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
22492 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
22495 // Check that successive elements are being operated on. If not, this is
22496 // not a horizontal operation.
22497 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
22498 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
22499 if (!(LIdx == Index && RIdx == Index + 1) &&
22500 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
22505 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
22506 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
22510 /// Do target-specific dag combines on floating point adds.
22511 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
22512 const X86Subtarget *Subtarget) {
22513 EVT VT = N->getValueType(0);
22514 SDValue LHS = N->getOperand(0);
22515 SDValue RHS = N->getOperand(1);
22517 // Try to synthesize horizontal adds from adds of shuffles.
22518 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22519 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22520 isHorizontalBinOp(LHS, RHS, true))
22521 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
22525 /// Do target-specific dag combines on floating point subs.
22526 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
22527 const X86Subtarget *Subtarget) {
22528 EVT VT = N->getValueType(0);
22529 SDValue LHS = N->getOperand(0);
22530 SDValue RHS = N->getOperand(1);
22532 // Try to synthesize horizontal subs from subs of shuffles.
22533 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22534 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22535 isHorizontalBinOp(LHS, RHS, false))
22536 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
22540 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
22541 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
22542 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
22544 // F[X]OR(0.0, x) -> x
22545 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22546 if (C->getValueAPF().isPosZero())
22547 return N->getOperand(1);
22549 // F[X]OR(x, 0.0) -> x
22550 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22551 if (C->getValueAPF().isPosZero())
22552 return N->getOperand(0);
22556 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
22557 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
22558 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
22560 // Only perform optimizations if UnsafeMath is used.
22561 if (!DAG.getTarget().Options.UnsafeFPMath)
22564 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
22565 // into FMINC and FMAXC, which are Commutative operations.
22566 unsigned NewOp = 0;
22567 switch (N->getOpcode()) {
22568 default: llvm_unreachable("unknown opcode");
22569 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
22570 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
22573 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
22574 N->getOperand(0), N->getOperand(1));
22577 /// Do target-specific dag combines on X86ISD::FAND nodes.
22578 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
22579 // FAND(0.0, x) -> 0.0
22580 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22581 if (C->getValueAPF().isPosZero())
22582 return N->getOperand(0);
22584 // FAND(x, 0.0) -> 0.0
22585 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22586 if (C->getValueAPF().isPosZero())
22587 return N->getOperand(1);
22592 /// Do target-specific dag combines on X86ISD::FANDN nodes
22593 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
22594 // FANDN(0.0, x) -> x
22595 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22596 if (C->getValueAPF().isPosZero())
22597 return N->getOperand(1);
22599 // FANDN(x, 0.0) -> 0.0
22600 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22601 if (C->getValueAPF().isPosZero())
22602 return N->getOperand(1);
22607 static SDValue PerformBTCombine(SDNode *N,
22609 TargetLowering::DAGCombinerInfo &DCI) {
22610 // BT ignores high bits in the bit index operand.
22611 SDValue Op1 = N->getOperand(1);
22612 if (Op1.hasOneUse()) {
22613 unsigned BitWidth = Op1.getValueSizeInBits();
22614 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
22615 APInt KnownZero, KnownOne;
22616 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
22617 !DCI.isBeforeLegalizeOps());
22618 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22619 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
22620 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
22621 DCI.CommitTargetLoweringOpt(TLO);
22626 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
22627 SDValue Op = N->getOperand(0);
22628 if (Op.getOpcode() == ISD::BITCAST)
22629 Op = Op.getOperand(0);
22630 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
22631 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
22632 VT.getVectorElementType().getSizeInBits() ==
22633 OpVT.getVectorElementType().getSizeInBits()) {
22634 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
22639 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
22640 const X86Subtarget *Subtarget) {
22641 EVT VT = N->getValueType(0);
22642 if (!VT.isVector())
22645 SDValue N0 = N->getOperand(0);
22646 SDValue N1 = N->getOperand(1);
22647 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
22650 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
22651 // both SSE and AVX2 since there is no sign-extended shift right
22652 // operation on a vector with 64-bit elements.
22653 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
22654 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
22655 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
22656 N0.getOpcode() == ISD::SIGN_EXTEND)) {
22657 SDValue N00 = N0.getOperand(0);
22659 // EXTLOAD has a better solution on AVX2,
22660 // it may be replaced with X86ISD::VSEXT node.
22661 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
22662 if (!ISD::isNormalLoad(N00.getNode()))
22665 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
22666 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
22668 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
22674 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
22675 TargetLowering::DAGCombinerInfo &DCI,
22676 const X86Subtarget *Subtarget) {
22677 SDValue N0 = N->getOperand(0);
22678 EVT VT = N->getValueType(0);
22680 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
22681 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
22682 // This exposes the sext to the sdivrem lowering, so that it directly extends
22683 // from AH (which we otherwise need to do contortions to access).
22684 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
22685 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
22687 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
22688 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
22689 N0.getOperand(0), N0.getOperand(1));
22690 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
22691 return R.getValue(1);
22694 if (!DCI.isBeforeLegalizeOps())
22697 if (!Subtarget->hasFp256())
22700 if (VT.isVector() && VT.getSizeInBits() == 256) {
22701 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22709 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
22710 const X86Subtarget* Subtarget) {
22712 EVT VT = N->getValueType(0);
22714 // Let legalize expand this if it isn't a legal type yet.
22715 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
22718 EVT ScalarVT = VT.getScalarType();
22719 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
22720 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
22723 SDValue A = N->getOperand(0);
22724 SDValue B = N->getOperand(1);
22725 SDValue C = N->getOperand(2);
22727 bool NegA = (A.getOpcode() == ISD::FNEG);
22728 bool NegB = (B.getOpcode() == ISD::FNEG);
22729 bool NegC = (C.getOpcode() == ISD::FNEG);
22731 // Negative multiplication when NegA xor NegB
22732 bool NegMul = (NegA != NegB);
22734 A = A.getOperand(0);
22736 B = B.getOperand(0);
22738 C = C.getOperand(0);
22742 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
22744 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
22746 return DAG.getNode(Opcode, dl, VT, A, B, C);
22749 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
22750 TargetLowering::DAGCombinerInfo &DCI,
22751 const X86Subtarget *Subtarget) {
22752 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
22753 // (and (i32 x86isd::setcc_carry), 1)
22754 // This eliminates the zext. This transformation is necessary because
22755 // ISD::SETCC is always legalized to i8.
22757 SDValue N0 = N->getOperand(0);
22758 EVT VT = N->getValueType(0);
22760 if (N0.getOpcode() == ISD::AND &&
22762 N0.getOperand(0).hasOneUse()) {
22763 SDValue N00 = N0.getOperand(0);
22764 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22765 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22766 if (!C || C->getZExtValue() != 1)
22768 return DAG.getNode(ISD::AND, dl, VT,
22769 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22770 N00.getOperand(0), N00.getOperand(1)),
22771 DAG.getConstant(1, VT));
22775 if (N0.getOpcode() == ISD::TRUNCATE &&
22777 N0.getOperand(0).hasOneUse()) {
22778 SDValue N00 = N0.getOperand(0);
22779 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22780 return DAG.getNode(ISD::AND, dl, VT,
22781 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22782 N00.getOperand(0), N00.getOperand(1)),
22783 DAG.getConstant(1, VT));
22786 if (VT.is256BitVector()) {
22787 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22792 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
22793 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
22794 // This exposes the zext to the udivrem lowering, so that it directly extends
22795 // from AH (which we otherwise need to do contortions to access).
22796 if (N0.getOpcode() == ISD::UDIVREM &&
22797 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
22798 (VT == MVT::i32 || VT == MVT::i64)) {
22799 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
22800 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
22801 N0.getOperand(0), N0.getOperand(1));
22802 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
22803 return R.getValue(1);
22809 // Optimize x == -y --> x+y == 0
22810 // x != -y --> x+y != 0
22811 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
22812 const X86Subtarget* Subtarget) {
22813 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
22814 SDValue LHS = N->getOperand(0);
22815 SDValue RHS = N->getOperand(1);
22816 EVT VT = N->getValueType(0);
22819 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
22820 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
22821 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
22822 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22823 LHS.getValueType(), RHS, LHS.getOperand(1));
22824 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22825 addV, DAG.getConstant(0, addV.getValueType()), CC);
22827 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
22828 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
22829 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
22830 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22831 RHS.getValueType(), LHS, RHS.getOperand(1));
22832 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22833 addV, DAG.getConstant(0, addV.getValueType()), CC);
22836 if (VT.getScalarType() == MVT::i1) {
22837 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
22838 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22839 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
22840 if (!IsSEXT0 && !IsVZero0)
22842 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
22843 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22844 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
22846 if (!IsSEXT1 && !IsVZero1)
22849 if (IsSEXT0 && IsVZero1) {
22850 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
22851 if (CC == ISD::SETEQ)
22852 return DAG.getNOT(DL, LHS.getOperand(0), VT);
22853 return LHS.getOperand(0);
22855 if (IsSEXT1 && IsVZero0) {
22856 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
22857 if (CC == ISD::SETEQ)
22858 return DAG.getNOT(DL, RHS.getOperand(0), VT);
22859 return RHS.getOperand(0);
22866 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
22867 SelectionDAG &DAG) {
22869 MVT VT = Load->getSimpleValueType(0);
22870 MVT EVT = VT.getVectorElementType();
22871 SDValue Addr = Load->getOperand(1);
22872 SDValue NewAddr = DAG.getNode(
22873 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
22874 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
22877 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
22878 DAG.getMachineFunction().getMachineMemOperand(
22879 Load->getMemOperand(), 0, EVT.getStoreSize()));
22883 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
22884 const X86Subtarget *Subtarget) {
22886 MVT VT = N->getOperand(1)->getSimpleValueType(0);
22887 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
22888 "X86insertps is only defined for v4x32");
22890 SDValue Ld = N->getOperand(1);
22891 if (MayFoldLoad(Ld)) {
22892 // Extract the countS bits from the immediate so we can get the proper
22893 // address when narrowing the vector load to a specific element.
22894 // When the second source op is a memory address, interps doesn't use
22895 // countS and just gets an f32 from that address.
22896 unsigned DestIndex =
22897 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
22898 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
22902 // Create this as a scalar to vector to match the instruction pattern.
22903 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
22904 // countS bits are ignored when loading from memory on insertps, which
22905 // means we don't need to explicitly set them to 0.
22906 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
22907 LoadScalarToVector, N->getOperand(2));
22910 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
22911 SDValue V0 = N->getOperand(0);
22912 SDValue V1 = N->getOperand(1);
22914 EVT VT = N->getValueType(0);
22916 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
22917 // operands and changing the mask to 1. This saves us a bunch of
22918 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
22919 // x86InstrInfo knows how to commute this back after instruction selection
22920 // if it would help register allocation.
22922 // TODO: If optimizing for size or a processor that doesn't suffer from
22923 // partial register update stalls, this should be transformed into a MOVSD
22924 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
22926 if (VT == MVT::v2f64)
22927 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
22928 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
22929 SDValue NewMask = DAG.getConstant(1, MVT::i8);
22930 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
22936 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
22937 // as "sbb reg,reg", since it can be extended without zext and produces
22938 // an all-ones bit which is more useful than 0/1 in some cases.
22939 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
22942 return DAG.getNode(ISD::AND, DL, VT,
22943 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22944 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
22945 DAG.getConstant(1, VT));
22946 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
22947 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
22948 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22949 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
22952 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
22953 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
22954 TargetLowering::DAGCombinerInfo &DCI,
22955 const X86Subtarget *Subtarget) {
22957 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
22958 SDValue EFLAGS = N->getOperand(1);
22960 if (CC == X86::COND_A) {
22961 // Try to convert COND_A into COND_B in an attempt to facilitate
22962 // materializing "setb reg".
22964 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
22965 // cannot take an immediate as its first operand.
22967 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
22968 EFLAGS.getValueType().isInteger() &&
22969 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
22970 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
22971 EFLAGS.getNode()->getVTList(),
22972 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
22973 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
22974 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
22978 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
22979 // a zext and produces an all-ones bit which is more useful than 0/1 in some
22981 if (CC == X86::COND_B)
22982 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
22986 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22987 if (Flags.getNode()) {
22988 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22989 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
22995 // Optimize branch condition evaluation.
22997 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
22998 TargetLowering::DAGCombinerInfo &DCI,
22999 const X86Subtarget *Subtarget) {
23001 SDValue Chain = N->getOperand(0);
23002 SDValue Dest = N->getOperand(1);
23003 SDValue EFLAGS = N->getOperand(3);
23004 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23008 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23009 if (Flags.getNode()) {
23010 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23011 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23018 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23019 SelectionDAG &DAG) {
23020 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23021 // optimize away operation when it's from a constant.
23023 // The general transformation is:
23024 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23025 // AND(VECTOR_CMP(x,y), constant2)
23026 // constant2 = UNARYOP(constant)
23028 // Early exit if this isn't a vector operation, the operand of the
23029 // unary operation isn't a bitwise AND, or if the sizes of the operations
23030 // aren't the same.
23031 EVT VT = N->getValueType(0);
23032 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23033 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23034 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23037 // Now check that the other operand of the AND is a constant. We could
23038 // make the transformation for non-constant splats as well, but it's unclear
23039 // that would be a benefit as it would not eliminate any operations, just
23040 // perform one more step in scalar code before moving to the vector unit.
23041 if (BuildVectorSDNode *BV =
23042 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23043 // Bail out if the vector isn't a constant.
23044 if (!BV->isConstant())
23047 // Everything checks out. Build up the new and improved node.
23049 EVT IntVT = BV->getValueType(0);
23050 // Create a new constant of the appropriate type for the transformed
23052 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23053 // The AND node needs bitcasts to/from an integer vector type around it.
23054 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23055 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23056 N->getOperand(0)->getOperand(0), MaskConst);
23057 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23064 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23065 const X86Subtarget *Subtarget) {
23066 // First try to optimize away the conversion entirely when it's
23067 // conditionally from a constant. Vectors only.
23068 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23069 if (Res != SDValue())
23072 // Now move on to more general possibilities.
23073 SDValue Op0 = N->getOperand(0);
23074 EVT InVT = Op0->getValueType(0);
23076 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23077 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
23079 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23080 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
23081 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
23084 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
23085 // a 32-bit target where SSE doesn't support i64->FP operations.
23086 if (Op0.getOpcode() == ISD::LOAD) {
23087 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
23088 EVT VT = Ld->getValueType(0);
23089 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
23090 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
23091 !Subtarget->is64Bit() && VT == MVT::i64) {
23092 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
23093 SDValue(N, 0), Ld->getValueType(0), Ld->getChain(), Op0, DAG);
23094 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
23101 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
23102 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
23103 X86TargetLowering::DAGCombinerInfo &DCI) {
23104 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
23105 // the result is either zero or one (depending on the input carry bit).
23106 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
23107 if (X86::isZeroNode(N->getOperand(0)) &&
23108 X86::isZeroNode(N->getOperand(1)) &&
23109 // We don't have a good way to replace an EFLAGS use, so only do this when
23111 SDValue(N, 1).use_empty()) {
23113 EVT VT = N->getValueType(0);
23114 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
23115 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
23116 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
23117 DAG.getConstant(X86::COND_B,MVT::i8),
23119 DAG.getConstant(1, VT));
23120 return DCI.CombineTo(N, Res1, CarryOut);
23126 // fold (add Y, (sete X, 0)) -> adc 0, Y
23127 // (add Y, (setne X, 0)) -> sbb -1, Y
23128 // (sub (sete X, 0), Y) -> sbb 0, Y
23129 // (sub (setne X, 0), Y) -> adc -1, Y
23130 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23133 // Look through ZExts.
23134 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23135 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23138 SDValue SetCC = Ext.getOperand(0);
23139 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23142 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23143 if (CC != X86::COND_E && CC != X86::COND_NE)
23146 SDValue Cmp = SetCC.getOperand(1);
23147 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23148 !X86::isZeroNode(Cmp.getOperand(1)) ||
23149 !Cmp.getOperand(0).getValueType().isInteger())
23152 SDValue CmpOp0 = Cmp.getOperand(0);
23153 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
23154 DAG.getConstant(1, CmpOp0.getValueType()));
23156 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
23157 if (CC == X86::COND_NE)
23158 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23159 DL, OtherVal.getValueType(), OtherVal,
23160 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
23161 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23162 DL, OtherVal.getValueType(), OtherVal,
23163 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
23166 /// PerformADDCombine - Do target-specific dag combines on integer adds.
23167 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
23168 const X86Subtarget *Subtarget) {
23169 EVT VT = N->getValueType(0);
23170 SDValue Op0 = N->getOperand(0);
23171 SDValue Op1 = N->getOperand(1);
23173 // Try to synthesize horizontal adds from adds of shuffles.
23174 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23175 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23176 isHorizontalBinOp(Op0, Op1, true))
23177 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
23179 return OptimizeConditionalInDecrement(N, DAG);
23182 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
23183 const X86Subtarget *Subtarget) {
23184 SDValue Op0 = N->getOperand(0);
23185 SDValue Op1 = N->getOperand(1);
23187 // X86 can't encode an immediate LHS of a sub. See if we can push the
23188 // negation into a preceding instruction.
23189 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
23190 // If the RHS of the sub is a XOR with one use and a constant, invert the
23191 // immediate. Then add one to the LHS of the sub so we can turn
23192 // X-Y -> X+~Y+1, saving one register.
23193 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
23194 isa<ConstantSDNode>(Op1.getOperand(1))) {
23195 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
23196 EVT VT = Op0.getValueType();
23197 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
23199 DAG.getConstant(~XorC, VT));
23200 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
23201 DAG.getConstant(C->getAPIntValue()+1, VT));
23205 // Try to synthesize horizontal adds from adds of shuffles.
23206 EVT VT = N->getValueType(0);
23207 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23208 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23209 isHorizontalBinOp(Op0, Op1, true))
23210 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
23212 return OptimizeConditionalInDecrement(N, DAG);
23215 /// performVZEXTCombine - Performs build vector combines
23216 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
23217 TargetLowering::DAGCombinerInfo &DCI,
23218 const X86Subtarget *Subtarget) {
23220 MVT VT = N->getSimpleValueType(0);
23221 SDValue Op = N->getOperand(0);
23222 MVT OpVT = Op.getSimpleValueType();
23223 MVT OpEltVT = OpVT.getVectorElementType();
23224 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
23226 // (vzext (bitcast (vzext (x)) -> (vzext x)
23228 while (V.getOpcode() == ISD::BITCAST)
23229 V = V.getOperand(0);
23231 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
23232 MVT InnerVT = V.getSimpleValueType();
23233 MVT InnerEltVT = InnerVT.getVectorElementType();
23235 // If the element sizes match exactly, we can just do one larger vzext. This
23236 // is always an exact type match as vzext operates on integer types.
23237 if (OpEltVT == InnerEltVT) {
23238 assert(OpVT == InnerVT && "Types must match for vzext!");
23239 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
23242 // The only other way we can combine them is if only a single element of the
23243 // inner vzext is used in the input to the outer vzext.
23244 if (InnerEltVT.getSizeInBits() < InputBits)
23247 // In this case, the inner vzext is completely dead because we're going to
23248 // only look at bits inside of the low element. Just do the outer vzext on
23249 // a bitcast of the input to the inner.
23250 return DAG.getNode(X86ISD::VZEXT, DL, VT,
23251 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
23254 // Check if we can bypass extracting and re-inserting an element of an input
23255 // vector. Essentialy:
23256 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
23257 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
23258 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
23259 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
23260 SDValue ExtractedV = V.getOperand(0);
23261 SDValue OrigV = ExtractedV.getOperand(0);
23262 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
23263 if (ExtractIdx->getZExtValue() == 0) {
23264 MVT OrigVT = OrigV.getSimpleValueType();
23265 // Extract a subvector if necessary...
23266 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
23267 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
23268 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
23269 OrigVT.getVectorNumElements() / Ratio);
23270 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
23271 DAG.getIntPtrConstant(0));
23273 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
23274 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
23281 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
23282 DAGCombinerInfo &DCI) const {
23283 SelectionDAG &DAG = DCI.DAG;
23284 switch (N->getOpcode()) {
23286 case ISD::EXTRACT_VECTOR_ELT:
23287 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
23290 case X86ISD::SHRUNKBLEND:
23291 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
23292 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
23293 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
23294 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
23295 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
23296 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
23297 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23300 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
23301 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
23302 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
23303 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
23304 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
23305 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
23306 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
23307 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
23308 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
23309 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
23310 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
23312 case X86ISD::FOR: return PerformFORCombine(N, DAG);
23314 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
23315 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
23316 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
23317 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
23318 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
23319 case ISD::ANY_EXTEND:
23320 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
23321 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
23322 case ISD::SIGN_EXTEND_INREG:
23323 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
23324 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
23325 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
23326 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
23327 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
23328 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
23329 case X86ISD::SHUFP: // Handle all target specific shuffles
23330 case X86ISD::PALIGNR:
23331 case X86ISD::UNPCKH:
23332 case X86ISD::UNPCKL:
23333 case X86ISD::MOVHLPS:
23334 case X86ISD::MOVLHPS:
23335 case X86ISD::PSHUFB:
23336 case X86ISD::PSHUFD:
23337 case X86ISD::PSHUFHW:
23338 case X86ISD::PSHUFLW:
23339 case X86ISD::MOVSS:
23340 case X86ISD::MOVSD:
23341 case X86ISD::VPERMILPI:
23342 case X86ISD::VPERM2X128:
23343 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
23344 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
23345 case ISD::INTRINSIC_WO_CHAIN:
23346 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
23347 case X86ISD::INSERTPS: {
23348 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
23349 return PerformINSERTPSCombine(N, DAG, Subtarget);
23352 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
23353 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
23359 /// isTypeDesirableForOp - Return true if the target has native support for
23360 /// the specified value type and it is 'desirable' to use the type for the
23361 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
23362 /// instruction encodings are longer and some i16 instructions are slow.
23363 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
23364 if (!isTypeLegal(VT))
23366 if (VT != MVT::i16)
23373 case ISD::SIGN_EXTEND:
23374 case ISD::ZERO_EXTEND:
23375 case ISD::ANY_EXTEND:
23388 /// IsDesirableToPromoteOp - This method query the target whether it is
23389 /// beneficial for dag combiner to promote the specified node. If true, it
23390 /// should return the desired promotion type by reference.
23391 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
23392 EVT VT = Op.getValueType();
23393 if (VT != MVT::i16)
23396 bool Promote = false;
23397 bool Commute = false;
23398 switch (Op.getOpcode()) {
23401 LoadSDNode *LD = cast<LoadSDNode>(Op);
23402 // If the non-extending load has a single use and it's not live out, then it
23403 // might be folded.
23404 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
23405 Op.hasOneUse()*/) {
23406 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
23407 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
23408 // The only case where we'd want to promote LOAD (rather then it being
23409 // promoted as an operand is when it's only use is liveout.
23410 if (UI->getOpcode() != ISD::CopyToReg)
23417 case ISD::SIGN_EXTEND:
23418 case ISD::ZERO_EXTEND:
23419 case ISD::ANY_EXTEND:
23424 SDValue N0 = Op.getOperand(0);
23425 // Look out for (store (shl (load), x)).
23426 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
23439 SDValue N0 = Op.getOperand(0);
23440 SDValue N1 = Op.getOperand(1);
23441 if (!Commute && MayFoldLoad(N1))
23443 // Avoid disabling potential load folding opportunities.
23444 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
23446 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
23456 //===----------------------------------------------------------------------===//
23457 // X86 Inline Assembly Support
23458 //===----------------------------------------------------------------------===//
23461 // Helper to match a string separated by whitespace.
23462 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
23463 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
23465 for (unsigned i = 0, e = args.size(); i != e; ++i) {
23466 StringRef piece(*args[i]);
23467 if (!s.startswith(piece)) // Check if the piece matches.
23470 s = s.substr(piece.size());
23471 StringRef::size_type pos = s.find_first_not_of(" \t");
23472 if (pos == 0) // We matched a prefix.
23480 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
23483 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
23485 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
23486 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
23487 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
23488 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
23490 if (AsmPieces.size() == 3)
23492 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
23499 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
23500 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
23502 std::string AsmStr = IA->getAsmString();
23504 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
23505 if (!Ty || Ty->getBitWidth() % 16 != 0)
23508 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
23509 SmallVector<StringRef, 4> AsmPieces;
23510 SplitString(AsmStr, AsmPieces, ";\n");
23512 switch (AsmPieces.size()) {
23513 default: return false;
23515 // FIXME: this should verify that we are targeting a 486 or better. If not,
23516 // we will turn this bswap into something that will be lowered to logical
23517 // ops instead of emitting the bswap asm. For now, we don't support 486 or
23518 // lower so don't worry about this.
23520 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
23521 matchAsm(AsmPieces[0], "bswapl", "$0") ||
23522 matchAsm(AsmPieces[0], "bswapq", "$0") ||
23523 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
23524 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
23525 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
23526 // No need to check constraints, nothing other than the equivalent of
23527 // "=r,0" would be valid here.
23528 return IntrinsicLowering::LowerToByteSwap(CI);
23531 // rorw $$8, ${0:w} --> llvm.bswap.i16
23532 if (CI->getType()->isIntegerTy(16) &&
23533 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23534 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
23535 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
23537 const std::string &ConstraintsStr = IA->getConstraintString();
23538 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23539 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23540 if (clobbersFlagRegisters(AsmPieces))
23541 return IntrinsicLowering::LowerToByteSwap(CI);
23545 if (CI->getType()->isIntegerTy(32) &&
23546 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23547 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
23548 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
23549 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
23551 const std::string &ConstraintsStr = IA->getConstraintString();
23552 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23553 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23554 if (clobbersFlagRegisters(AsmPieces))
23555 return IntrinsicLowering::LowerToByteSwap(CI);
23558 if (CI->getType()->isIntegerTy(64)) {
23559 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
23560 if (Constraints.size() >= 2 &&
23561 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
23562 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
23563 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
23564 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
23565 matchAsm(AsmPieces[1], "bswap", "%edx") &&
23566 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
23567 return IntrinsicLowering::LowerToByteSwap(CI);
23575 /// getConstraintType - Given a constraint letter, return the type of
23576 /// constraint it is for this target.
23577 X86TargetLowering::ConstraintType
23578 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
23579 if (Constraint.size() == 1) {
23580 switch (Constraint[0]) {
23591 return C_RegisterClass;
23615 return TargetLowering::getConstraintType(Constraint);
23618 /// Examine constraint type and operand type and determine a weight value.
23619 /// This object must already have been set up with the operand type
23620 /// and the current alternative constraint selected.
23621 TargetLowering::ConstraintWeight
23622 X86TargetLowering::getSingleConstraintMatchWeight(
23623 AsmOperandInfo &info, const char *constraint) const {
23624 ConstraintWeight weight = CW_Invalid;
23625 Value *CallOperandVal = info.CallOperandVal;
23626 // If we don't have a value, we can't do a match,
23627 // but allow it at the lowest weight.
23628 if (!CallOperandVal)
23630 Type *type = CallOperandVal->getType();
23631 // Look at the constraint type.
23632 switch (*constraint) {
23634 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
23645 if (CallOperandVal->getType()->isIntegerTy())
23646 weight = CW_SpecificReg;
23651 if (type->isFloatingPointTy())
23652 weight = CW_SpecificReg;
23655 if (type->isX86_MMXTy() && Subtarget->hasMMX())
23656 weight = CW_SpecificReg;
23660 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
23661 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
23662 weight = CW_Register;
23665 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
23666 if (C->getZExtValue() <= 31)
23667 weight = CW_Constant;
23671 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23672 if (C->getZExtValue() <= 63)
23673 weight = CW_Constant;
23677 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23678 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
23679 weight = CW_Constant;
23683 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23684 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
23685 weight = CW_Constant;
23689 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23690 if (C->getZExtValue() <= 3)
23691 weight = CW_Constant;
23695 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23696 if (C->getZExtValue() <= 0xff)
23697 weight = CW_Constant;
23702 if (dyn_cast<ConstantFP>(CallOperandVal)) {
23703 weight = CW_Constant;
23707 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23708 if ((C->getSExtValue() >= -0x80000000LL) &&
23709 (C->getSExtValue() <= 0x7fffffffLL))
23710 weight = CW_Constant;
23714 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23715 if (C->getZExtValue() <= 0xffffffff)
23716 weight = CW_Constant;
23723 /// LowerXConstraint - try to replace an X constraint, which matches anything,
23724 /// with another that has more specific requirements based on the type of the
23725 /// corresponding operand.
23726 const char *X86TargetLowering::
23727 LowerXConstraint(EVT ConstraintVT) const {
23728 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
23729 // 'f' like normal targets.
23730 if (ConstraintVT.isFloatingPoint()) {
23731 if (Subtarget->hasSSE2())
23733 if (Subtarget->hasSSE1())
23737 return TargetLowering::LowerXConstraint(ConstraintVT);
23740 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
23741 /// vector. If it is invalid, don't add anything to Ops.
23742 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
23743 std::string &Constraint,
23744 std::vector<SDValue>&Ops,
23745 SelectionDAG &DAG) const {
23748 // Only support length 1 constraints for now.
23749 if (Constraint.length() > 1) return;
23751 char ConstraintLetter = Constraint[0];
23752 switch (ConstraintLetter) {
23755 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23756 if (C->getZExtValue() <= 31) {
23757 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23763 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23764 if (C->getZExtValue() <= 63) {
23765 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23771 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23772 if (isInt<8>(C->getSExtValue())) {
23773 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23779 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23780 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
23781 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
23782 Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType());
23788 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23789 if (C->getZExtValue() <= 3) {
23790 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23796 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23797 if (C->getZExtValue() <= 255) {
23798 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23804 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23805 if (C->getZExtValue() <= 127) {
23806 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23812 // 32-bit signed value
23813 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23814 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23815 C->getSExtValue())) {
23816 // Widen to 64 bits here to get it sign extended.
23817 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
23820 // FIXME gcc accepts some relocatable values here too, but only in certain
23821 // memory models; it's complicated.
23826 // 32-bit unsigned value
23827 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23828 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23829 C->getZExtValue())) {
23830 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23834 // FIXME gcc accepts some relocatable values here too, but only in certain
23835 // memory models; it's complicated.
23839 // Literal immediates are always ok.
23840 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
23841 // Widen to 64 bits here to get it sign extended.
23842 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
23846 // In any sort of PIC mode addresses need to be computed at runtime by
23847 // adding in a register or some sort of table lookup. These can't
23848 // be used as immediates.
23849 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
23852 // If we are in non-pic codegen mode, we allow the address of a global (with
23853 // an optional displacement) to be used with 'i'.
23854 GlobalAddressSDNode *GA = nullptr;
23855 int64_t Offset = 0;
23857 // Match either (GA), (GA+C), (GA+C1+C2), etc.
23859 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
23860 Offset += GA->getOffset();
23862 } else if (Op.getOpcode() == ISD::ADD) {
23863 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23864 Offset += C->getZExtValue();
23865 Op = Op.getOperand(0);
23868 } else if (Op.getOpcode() == ISD::SUB) {
23869 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23870 Offset += -C->getZExtValue();
23871 Op = Op.getOperand(0);
23876 // Otherwise, this isn't something we can handle, reject it.
23880 const GlobalValue *GV = GA->getGlobal();
23881 // If we require an extra load to get this address, as in PIC mode, we
23882 // can't accept it.
23883 if (isGlobalStubReference(
23884 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
23887 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
23888 GA->getValueType(0), Offset);
23893 if (Result.getNode()) {
23894 Ops.push_back(Result);
23897 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
23900 std::pair<unsigned, const TargetRegisterClass*>
23901 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
23903 // First, see if this is a constraint that directly corresponds to an LLVM
23905 if (Constraint.size() == 1) {
23906 // GCC Constraint Letters
23907 switch (Constraint[0]) {
23909 // TODO: Slight differences here in allocation order and leaving
23910 // RIP in the class. Do they matter any more here than they do
23911 // in the normal allocation?
23912 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
23913 if (Subtarget->is64Bit()) {
23914 if (VT == MVT::i32 || VT == MVT::f32)
23915 return std::make_pair(0U, &X86::GR32RegClass);
23916 if (VT == MVT::i16)
23917 return std::make_pair(0U, &X86::GR16RegClass);
23918 if (VT == MVT::i8 || VT == MVT::i1)
23919 return std::make_pair(0U, &X86::GR8RegClass);
23920 if (VT == MVT::i64 || VT == MVT::f64)
23921 return std::make_pair(0U, &X86::GR64RegClass);
23924 // 32-bit fallthrough
23925 case 'Q': // Q_REGS
23926 if (VT == MVT::i32 || VT == MVT::f32)
23927 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
23928 if (VT == MVT::i16)
23929 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
23930 if (VT == MVT::i8 || VT == MVT::i1)
23931 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
23932 if (VT == MVT::i64)
23933 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
23935 case 'r': // GENERAL_REGS
23936 case 'l': // INDEX_REGS
23937 if (VT == MVT::i8 || VT == MVT::i1)
23938 return std::make_pair(0U, &X86::GR8RegClass);
23939 if (VT == MVT::i16)
23940 return std::make_pair(0U, &X86::GR16RegClass);
23941 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
23942 return std::make_pair(0U, &X86::GR32RegClass);
23943 return std::make_pair(0U, &X86::GR64RegClass);
23944 case 'R': // LEGACY_REGS
23945 if (VT == MVT::i8 || VT == MVT::i1)
23946 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
23947 if (VT == MVT::i16)
23948 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
23949 if (VT == MVT::i32 || !Subtarget->is64Bit())
23950 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
23951 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
23952 case 'f': // FP Stack registers.
23953 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
23954 // value to the correct fpstack register class.
23955 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
23956 return std::make_pair(0U, &X86::RFP32RegClass);
23957 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
23958 return std::make_pair(0U, &X86::RFP64RegClass);
23959 return std::make_pair(0U, &X86::RFP80RegClass);
23960 case 'y': // MMX_REGS if MMX allowed.
23961 if (!Subtarget->hasMMX()) break;
23962 return std::make_pair(0U, &X86::VR64RegClass);
23963 case 'Y': // SSE_REGS if SSE2 allowed
23964 if (!Subtarget->hasSSE2()) break;
23966 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
23967 if (!Subtarget->hasSSE1()) break;
23969 switch (VT.SimpleTy) {
23971 // Scalar SSE types.
23974 return std::make_pair(0U, &X86::FR32RegClass);
23977 return std::make_pair(0U, &X86::FR64RegClass);
23985 return std::make_pair(0U, &X86::VR128RegClass);
23993 return std::make_pair(0U, &X86::VR256RegClass);
23998 return std::make_pair(0U, &X86::VR512RegClass);
24004 // Use the default implementation in TargetLowering to convert the register
24005 // constraint into a member of a register class.
24006 std::pair<unsigned, const TargetRegisterClass*> Res;
24007 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
24009 // Not found as a standard register?
24011 // Map st(0) -> st(7) -> ST0
24012 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24013 tolower(Constraint[1]) == 's' &&
24014 tolower(Constraint[2]) == 't' &&
24015 Constraint[3] == '(' &&
24016 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24017 Constraint[5] == ')' &&
24018 Constraint[6] == '}') {
24020 Res.first = X86::FP0+Constraint[4]-'0';
24021 Res.second = &X86::RFP80RegClass;
24025 // GCC allows "st(0)" to be called just plain "st".
24026 if (StringRef("{st}").equals_lower(Constraint)) {
24027 Res.first = X86::FP0;
24028 Res.second = &X86::RFP80RegClass;
24033 if (StringRef("{flags}").equals_lower(Constraint)) {
24034 Res.first = X86::EFLAGS;
24035 Res.second = &X86::CCRRegClass;
24039 // 'A' means EAX + EDX.
24040 if (Constraint == "A") {
24041 Res.first = X86::EAX;
24042 Res.second = &X86::GR32_ADRegClass;
24048 // Otherwise, check to see if this is a register class of the wrong value
24049 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24050 // turn into {ax},{dx}.
24051 if (Res.second->hasType(VT))
24052 return Res; // Correct type already, nothing to do.
24054 // All of the single-register GCC register classes map their values onto
24055 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24056 // really want an 8-bit or 32-bit register, map to the appropriate register
24057 // class and return the appropriate register.
24058 if (Res.second == &X86::GR16RegClass) {
24059 if (VT == MVT::i8 || VT == MVT::i1) {
24060 unsigned DestReg = 0;
24061 switch (Res.first) {
24063 case X86::AX: DestReg = X86::AL; break;
24064 case X86::DX: DestReg = X86::DL; break;
24065 case X86::CX: DestReg = X86::CL; break;
24066 case X86::BX: DestReg = X86::BL; break;
24069 Res.first = DestReg;
24070 Res.second = &X86::GR8RegClass;
24072 } else if (VT == MVT::i32 || VT == MVT::f32) {
24073 unsigned DestReg = 0;
24074 switch (Res.first) {
24076 case X86::AX: DestReg = X86::EAX; break;
24077 case X86::DX: DestReg = X86::EDX; break;
24078 case X86::CX: DestReg = X86::ECX; break;
24079 case X86::BX: DestReg = X86::EBX; break;
24080 case X86::SI: DestReg = X86::ESI; break;
24081 case X86::DI: DestReg = X86::EDI; break;
24082 case X86::BP: DestReg = X86::EBP; break;
24083 case X86::SP: DestReg = X86::ESP; break;
24086 Res.first = DestReg;
24087 Res.second = &X86::GR32RegClass;
24089 } else if (VT == MVT::i64 || VT == MVT::f64) {
24090 unsigned DestReg = 0;
24091 switch (Res.first) {
24093 case X86::AX: DestReg = X86::RAX; break;
24094 case X86::DX: DestReg = X86::RDX; break;
24095 case X86::CX: DestReg = X86::RCX; break;
24096 case X86::BX: DestReg = X86::RBX; break;
24097 case X86::SI: DestReg = X86::RSI; break;
24098 case X86::DI: DestReg = X86::RDI; break;
24099 case X86::BP: DestReg = X86::RBP; break;
24100 case X86::SP: DestReg = X86::RSP; break;
24103 Res.first = DestReg;
24104 Res.second = &X86::GR64RegClass;
24107 } else if (Res.second == &X86::FR32RegClass ||
24108 Res.second == &X86::FR64RegClass ||
24109 Res.second == &X86::VR128RegClass ||
24110 Res.second == &X86::VR256RegClass ||
24111 Res.second == &X86::FR32XRegClass ||
24112 Res.second == &X86::FR64XRegClass ||
24113 Res.second == &X86::VR128XRegClass ||
24114 Res.second == &X86::VR256XRegClass ||
24115 Res.second == &X86::VR512RegClass) {
24116 // Handle references to XMM physical registers that got mapped into the
24117 // wrong class. This can happen with constraints like {xmm0} where the
24118 // target independent register mapper will just pick the first match it can
24119 // find, ignoring the required type.
24121 if (VT == MVT::f32 || VT == MVT::i32)
24122 Res.second = &X86::FR32RegClass;
24123 else if (VT == MVT::f64 || VT == MVT::i64)
24124 Res.second = &X86::FR64RegClass;
24125 else if (X86::VR128RegClass.hasType(VT))
24126 Res.second = &X86::VR128RegClass;
24127 else if (X86::VR256RegClass.hasType(VT))
24128 Res.second = &X86::VR256RegClass;
24129 else if (X86::VR512RegClass.hasType(VT))
24130 Res.second = &X86::VR512RegClass;
24136 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
24138 // Scaling factors are not free at all.
24139 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
24140 // will take 2 allocations in the out of order engine instead of 1
24141 // for plain addressing mode, i.e. inst (reg1).
24143 // vaddps (%rsi,%drx), %ymm0, %ymm1
24144 // Requires two allocations (one for the load, one for the computation)
24146 // vaddps (%rsi), %ymm0, %ymm1
24147 // Requires just 1 allocation, i.e., freeing allocations for other operations
24148 // and having less micro operations to execute.
24150 // For some X86 architectures, this is even worse because for instance for
24151 // stores, the complex addressing mode forces the instruction to use the
24152 // "load" ports instead of the dedicated "store" port.
24153 // E.g., on Haswell:
24154 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
24155 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
24156 if (isLegalAddressingMode(AM, Ty))
24157 // Scale represents reg2 * scale, thus account for 1
24158 // as soon as we use a second register.
24159 return AM.Scale != 0;
24163 bool X86TargetLowering::isTargetFTOL() const {
24164 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();