1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/ADT/SmallSet.h"
41 #include "llvm/ADT/StringExtras.h"
44 // Forward declarations.
45 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG);
47 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
48 : TargetLowering(TM) {
49 Subtarget = &TM.getSubtarget<X86Subtarget>();
50 X86ScalarSSEf64 = Subtarget->hasSSE2();
51 X86ScalarSSEf32 = Subtarget->hasSSE1();
52 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
56 RegInfo = TM.getRegisterInfo();
58 // Set up the TargetLowering object.
60 // X86 is weird, it always uses i8 for shift amounts and setcc results.
61 setShiftAmountType(MVT::i8);
62 setSetCCResultContents(ZeroOrOneSetCCResult);
63 setSchedulingPreference(SchedulingForRegPressure);
64 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
65 setStackPointerRegisterToSaveRestore(X86StackPtr);
67 if (Subtarget->isTargetDarwin()) {
68 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(false);
70 setUseUnderscoreLongJmp(false);
71 } else if (Subtarget->isTargetMingw()) {
72 // MS runtime is weird: it exports _setjmp, but longjmp!
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(false);
76 setUseUnderscoreSetJmp(true);
77 setUseUnderscoreLongJmp(true);
80 // Set up the register classes.
81 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
82 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
83 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
84 if (Subtarget->is64Bit())
85 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
87 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
89 // We don't accept any truncstore of integer registers.
90 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
91 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
92 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
93 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
94 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
95 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
97 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
99 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
100 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
101 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
103 if (Subtarget->is64Bit()) {
104 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
105 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
108 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
109 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
111 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
114 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
116 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
117 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
118 // SSE has no i16 to fp conversion, only i32
119 if (X86ScalarSSEf32) {
120 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
121 // f32 and f64 cases are Legal, f80 case is not
122 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
124 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
125 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
128 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
129 // are Legal, f80 is custom lowered.
130 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
131 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
133 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
135 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
136 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
138 if (X86ScalarSSEf32) {
139 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
140 // f32 and f64 cases are Legal, f80 case is not
141 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
143 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
144 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
147 // Handle FP_TO_UINT by promoting the destination to a larger signed
149 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
150 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
151 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
153 if (Subtarget->is64Bit()) {
154 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
155 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
157 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
158 // Expand FP_TO_UINT into a select.
159 // FIXME: We would like to use a Custom expander here eventually to do
160 // the optimal thing for SSE vs. the default expansion in the legalizer.
161 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
163 // With SSE3 we can use fisttpll to convert to a signed i64.
164 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
167 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
168 if (!X86ScalarSSEf64) {
169 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
170 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
173 // Scalar integer divide and remainder are lowered to use operations that
174 // produce two results, to match the available instructions. This exposes
175 // the two-result form to trivial CSE, which is able to combine x/y and x%y
176 // into a single instruction.
178 // Scalar integer multiply-high is also lowered to use two-result
179 // operations, to match the available instructions. However, plain multiply
180 // (low) operations are left as Legal, as there are single-result
181 // instructions for this in x86. Using the two-result multiply instructions
182 // when both high and low results are needed must be arranged by dagcombine.
183 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
184 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
185 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
186 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
187 setOperationAction(ISD::SREM , MVT::i8 , Expand);
188 setOperationAction(ISD::UREM , MVT::i8 , Expand);
189 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
190 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
191 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
192 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
193 setOperationAction(ISD::SREM , MVT::i16 , Expand);
194 setOperationAction(ISD::UREM , MVT::i16 , Expand);
195 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
196 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
197 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
198 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
199 setOperationAction(ISD::SREM , MVT::i32 , Expand);
200 setOperationAction(ISD::UREM , MVT::i32 , Expand);
201 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
202 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
203 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
204 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
205 setOperationAction(ISD::SREM , MVT::i64 , Expand);
206 setOperationAction(ISD::UREM , MVT::i64 , Expand);
208 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
209 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
210 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
211 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
212 if (Subtarget->is64Bit())
213 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
215 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
216 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
217 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
218 setOperationAction(ISD::FREM , MVT::f32 , Expand);
219 setOperationAction(ISD::FREM , MVT::f64 , Expand);
220 setOperationAction(ISD::FREM , MVT::f80 , Expand);
221 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
223 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
224 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
225 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
226 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
227 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
228 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
229 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
230 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
231 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
232 if (Subtarget->is64Bit()) {
233 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
234 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
235 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
238 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
239 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
241 // These should be promoted to a larger select which is supported.
242 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
243 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
244 // X86 wants to expand cmov itself.
245 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
246 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
247 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
248 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
249 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
250 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
251 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
252 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
253 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
254 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
255 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
258 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
260 // X86 ret instruction may pop stack.
261 setOperationAction(ISD::RET , MVT::Other, Custom);
262 if (!Subtarget->is64Bit())
263 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
266 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
267 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
268 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
269 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
270 if (Subtarget->is64Bit())
271 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
272 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
273 if (Subtarget->is64Bit()) {
274 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
275 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
276 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
277 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
279 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
280 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
281 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
282 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
283 if (Subtarget->is64Bit()) {
284 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
285 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
286 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
289 if (Subtarget->hasSSE1())
290 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
292 if (!Subtarget->hasSSE2())
293 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
295 // Expand certain atomics
296 setOperationAction(ISD::ATOMIC_LCS , MVT::i8, Custom);
297 setOperationAction(ISD::ATOMIC_LCS , MVT::i16, Custom);
298 setOperationAction(ISD::ATOMIC_LCS , MVT::i32, Custom);
299 setOperationAction(ISD::ATOMIC_LCS , MVT::i64, Custom);
300 setOperationAction(ISD::ATOMIC_LSS , MVT::i32, Expand);
302 // Use the default ISD::LOCATION, ISD::DECLARE expansion.
303 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
304 // FIXME - use subtarget debug flags
305 if (!Subtarget->isTargetDarwin() &&
306 !Subtarget->isTargetELF() &&
307 !Subtarget->isTargetCygMing())
308 setOperationAction(ISD::LABEL, MVT::Other, Expand);
310 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
311 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
312 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
313 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
314 if (Subtarget->is64Bit()) {
316 setExceptionPointerRegister(X86::RAX);
317 setExceptionSelectorRegister(X86::RDX);
319 setExceptionPointerRegister(X86::EAX);
320 setExceptionSelectorRegister(X86::EDX);
322 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
324 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
326 setOperationAction(ISD::TRAP, MVT::Other, Legal);
328 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
329 setOperationAction(ISD::VASTART , MVT::Other, Custom);
330 setOperationAction(ISD::VAEND , MVT::Other, Expand);
331 if (Subtarget->is64Bit()) {
332 setOperationAction(ISD::VAARG , MVT::Other, Custom);
333 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
335 setOperationAction(ISD::VAARG , MVT::Other, Expand);
336 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
339 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
340 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
341 if (Subtarget->is64Bit())
342 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
343 if (Subtarget->isTargetCygMing())
344 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
346 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
348 if (X86ScalarSSEf64) {
349 // f32 and f64 use SSE.
350 // Set up the FP register classes.
351 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
352 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
354 // Use ANDPD to simulate FABS.
355 setOperationAction(ISD::FABS , MVT::f64, Custom);
356 setOperationAction(ISD::FABS , MVT::f32, Custom);
358 // Use XORP to simulate FNEG.
359 setOperationAction(ISD::FNEG , MVT::f64, Custom);
360 setOperationAction(ISD::FNEG , MVT::f32, Custom);
362 // Use ANDPD and ORPD to simulate FCOPYSIGN.
363 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
364 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
366 // We don't support sin/cos/fmod
367 setOperationAction(ISD::FSIN , MVT::f64, Expand);
368 setOperationAction(ISD::FCOS , MVT::f64, Expand);
369 setOperationAction(ISD::FSIN , MVT::f32, Expand);
370 setOperationAction(ISD::FCOS , MVT::f32, Expand);
372 // Expand FP immediates into loads from the stack, except for the special
374 addLegalFPImmediate(APFloat(+0.0)); // xorpd
375 addLegalFPImmediate(APFloat(+0.0f)); // xorps
377 // Floating truncations from f80 and extensions to f80 go through memory.
378 // If optimizing, we lie about this though and handle it in
379 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
381 setConvertAction(MVT::f32, MVT::f80, Expand);
382 setConvertAction(MVT::f64, MVT::f80, Expand);
383 setConvertAction(MVT::f80, MVT::f32, Expand);
384 setConvertAction(MVT::f80, MVT::f64, Expand);
386 } else if (X86ScalarSSEf32) {
387 // Use SSE for f32, x87 for f64.
388 // Set up the FP register classes.
389 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
390 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
392 // Use ANDPS to simulate FABS.
393 setOperationAction(ISD::FABS , MVT::f32, Custom);
395 // Use XORP to simulate FNEG.
396 setOperationAction(ISD::FNEG , MVT::f32, Custom);
398 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
400 // Use ANDPS and ORPS to simulate FCOPYSIGN.
401 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
402 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
404 // We don't support sin/cos/fmod
405 setOperationAction(ISD::FSIN , MVT::f32, Expand);
406 setOperationAction(ISD::FCOS , MVT::f32, Expand);
408 // Special cases we handle for FP constants.
409 addLegalFPImmediate(APFloat(+0.0f)); // xorps
410 addLegalFPImmediate(APFloat(+0.0)); // FLD0
411 addLegalFPImmediate(APFloat(+1.0)); // FLD1
412 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
413 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
415 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
416 // this though and handle it in InstructionSelectPreprocess so that
417 // dagcombine2 can hack on these.
419 setConvertAction(MVT::f32, MVT::f64, Expand);
420 setConvertAction(MVT::f32, MVT::f80, Expand);
421 setConvertAction(MVT::f80, MVT::f32, Expand);
422 setConvertAction(MVT::f64, MVT::f32, Expand);
423 // And x87->x87 truncations also.
424 setConvertAction(MVT::f80, MVT::f64, Expand);
428 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
429 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
432 // f32 and f64 in x87.
433 // Set up the FP register classes.
434 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
435 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
437 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
438 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
439 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
440 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
442 // Floating truncations go through memory. If optimizing, we lie about
443 // this though and handle it in InstructionSelectPreprocess so that
444 // dagcombine2 can hack on these.
446 setConvertAction(MVT::f80, MVT::f32, Expand);
447 setConvertAction(MVT::f64, MVT::f32, Expand);
448 setConvertAction(MVT::f80, MVT::f64, Expand);
452 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
453 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
455 addLegalFPImmediate(APFloat(+0.0)); // FLD0
456 addLegalFPImmediate(APFloat(+1.0)); // FLD1
457 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
458 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
459 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
460 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
461 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
462 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
465 // Long double always uses X87.
466 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
467 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
468 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
470 APFloat TmpFlt(+0.0);
471 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
472 addLegalFPImmediate(TmpFlt); // FLD0
474 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
475 APFloat TmpFlt2(+1.0);
476 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
477 addLegalFPImmediate(TmpFlt2); // FLD1
478 TmpFlt2.changeSign();
479 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
483 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
484 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
487 // Always use a library call for pow.
488 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
489 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
490 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
492 // First set operation action for all vector types to expand. Then we
493 // will selectively turn on ones that can be effectively codegen'd.
494 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
495 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
496 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
497 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
498 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
499 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
500 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
501 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
502 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
503 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
504 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
505 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
506 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
507 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
508 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
509 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
510 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
511 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
512 setOperationAction(ISD::FABS, (MVT::ValueType)VT, Expand);
513 setOperationAction(ISD::FSIN, (MVT::ValueType)VT, Expand);
514 setOperationAction(ISD::FCOS, (MVT::ValueType)VT, Expand);
515 setOperationAction(ISD::FREM, (MVT::ValueType)VT, Expand);
516 setOperationAction(ISD::FPOWI, (MVT::ValueType)VT, Expand);
517 setOperationAction(ISD::FSQRT, (MVT::ValueType)VT, Expand);
518 setOperationAction(ISD::FCOPYSIGN, (MVT::ValueType)VT, Expand);
519 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand);
520 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand);
521 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
522 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
523 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
524 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
525 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
526 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
527 setOperationAction(ISD::SHL, (MVT::ValueType)VT, Expand);
528 setOperationAction(ISD::SRA, (MVT::ValueType)VT, Expand);
529 setOperationAction(ISD::SRL, (MVT::ValueType)VT, Expand);
530 setOperationAction(ISD::ROTL, (MVT::ValueType)VT, Expand);
531 setOperationAction(ISD::ROTR, (MVT::ValueType)VT, Expand);
532 setOperationAction(ISD::BSWAP, (MVT::ValueType)VT, Expand);
533 setOperationAction(ISD::VSETCC, (MVT::ValueType)VT, Expand);
536 if (Subtarget->hasMMX()) {
537 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
538 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
539 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
540 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
542 // FIXME: add MMX packed arithmetics
544 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
545 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
546 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
547 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
549 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
550 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
551 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
552 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
554 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
555 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
557 setOperationAction(ISD::AND, MVT::v8i8, Promote);
558 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
559 setOperationAction(ISD::AND, MVT::v4i16, Promote);
560 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
561 setOperationAction(ISD::AND, MVT::v2i32, Promote);
562 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
563 setOperationAction(ISD::AND, MVT::v1i64, Legal);
565 setOperationAction(ISD::OR, MVT::v8i8, Promote);
566 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
567 setOperationAction(ISD::OR, MVT::v4i16, Promote);
568 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
569 setOperationAction(ISD::OR, MVT::v2i32, Promote);
570 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
571 setOperationAction(ISD::OR, MVT::v1i64, Legal);
573 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
574 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
575 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
576 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
577 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
578 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
579 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
581 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
582 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
583 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
584 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
585 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
586 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
587 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
589 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
590 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
591 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
592 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
594 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
595 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
596 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
597 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
599 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
600 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
601 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
604 if (Subtarget->hasSSE1()) {
605 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
607 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
608 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
609 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
610 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
611 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
612 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
613 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
614 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
615 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
616 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
617 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
618 setOperationAction(ISD::VSETCC, MVT::v4f32, Legal);
621 if (Subtarget->hasSSE2()) {
622 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
623 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
624 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
625 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
626 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
628 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
629 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
630 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
631 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
632 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
633 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
634 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
635 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
636 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
637 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
638 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
639 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
640 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
641 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
642 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
644 setOperationAction(ISD::VSETCC, MVT::v2f64, Legal);
645 setOperationAction(ISD::VSETCC, MVT::v16i8, Legal);
646 setOperationAction(ISD::VSETCC, MVT::v8i16, Legal);
647 setOperationAction(ISD::VSETCC, MVT::v4i32, Legal);
648 setOperationAction(ISD::VSETCC, MVT::v2i64, Legal);
650 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
651 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
652 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
653 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
654 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
656 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
657 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
658 // Do not attempt to custom lower non-power-of-2 vectors
659 if (!isPowerOf2_32(MVT::getVectorNumElements(VT)))
661 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
662 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
663 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
665 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
666 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
667 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
668 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
669 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
670 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
671 if (Subtarget->is64Bit()) {
672 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
673 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
676 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
677 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
678 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
679 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
680 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
681 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
682 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
683 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
684 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
685 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
686 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
687 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
690 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
692 // Custom lower v2i64 and v2f64 selects.
693 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
694 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
695 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
696 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
700 if (Subtarget->hasSSE41()) {
701 // FIXME: Do we need to handle scalar-to-vector here?
702 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
704 // i8 and i16 vectors are custom , because the source register and source
705 // source memory operand types are not the same width. f32 vectors are
706 // custom since the immediate controlling the insert encodes additional
708 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
709 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
710 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
711 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
713 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
714 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
715 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
716 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
718 if (Subtarget->is64Bit()) {
719 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
720 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
724 // We want to custom lower some of our intrinsics.
725 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
727 // We have target-specific dag combine patterns for the following nodes:
728 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
729 setTargetDAGCombine(ISD::BUILD_VECTOR);
730 setTargetDAGCombine(ISD::SELECT);
731 setTargetDAGCombine(ISD::STORE);
733 computeRegisterProperties();
735 // FIXME: These should be based on subtarget info. Plus, the values should
736 // be smaller when we are in optimizing for size mode.
737 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
738 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
739 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
740 allowUnalignedMemoryAccesses = true; // x86 supports it!
741 setPrefLoopAlignment(16);
746 X86TargetLowering::getSetCCResultType(const SDOperand &) const {
751 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
752 /// the desired ByVal argument alignment.
753 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
756 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
757 if (VTy->getBitWidth() == 128)
759 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
760 unsigned EltAlign = 0;
761 getMaxByValAlign(ATy->getElementType(), EltAlign);
762 if (EltAlign > MaxAlign)
764 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
765 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
766 unsigned EltAlign = 0;
767 getMaxByValAlign(STy->getElementType(i), EltAlign);
768 if (EltAlign > MaxAlign)
777 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
778 /// function arguments in the caller parameter area. For X86, aggregates
779 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
780 /// are at 4-byte boundaries.
781 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
782 if (Subtarget->is64Bit())
783 return getTargetData()->getABITypeAlignment(Ty);
785 if (Subtarget->hasSSE1())
786 getMaxByValAlign(Ty, Align);
790 /// getOptimalMemOpType - Returns the target specific optimal type for load
791 /// store operations as result of memset, memcpy, and memmove lowering.
792 /// It returns MVT::iAny if SelectionDAG should be responsible for
795 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
796 bool isSrcConst, bool isSrcStr) const {
797 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
799 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
801 if (Subtarget->is64Bit() && Size >= 8)
807 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
809 SDOperand X86TargetLowering::getPICJumpTableRelocBase(SDOperand Table,
810 SelectionDAG &DAG) const {
811 if (usesGlobalOffsetTable())
812 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
813 if (!Subtarget->isPICStyleRIPRel())
814 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
818 //===----------------------------------------------------------------------===//
819 // Return Value Calling Convention Implementation
820 //===----------------------------------------------------------------------===//
822 #include "X86GenCallingConv.inc"
824 /// LowerRET - Lower an ISD::RET node.
825 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
826 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
828 SmallVector<CCValAssign, 16> RVLocs;
829 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
830 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
831 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
832 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
834 // If this is the first return lowered for this function, add the regs to the
835 // liveout set for the function.
836 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
837 for (unsigned i = 0; i != RVLocs.size(); ++i)
838 if (RVLocs[i].isRegLoc())
839 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
841 SDOperand Chain = Op.getOperand(0);
843 // Handle tail call return.
844 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
845 if (Chain.getOpcode() == X86ISD::TAILCALL) {
846 SDOperand TailCall = Chain;
847 SDOperand TargetAddress = TailCall.getOperand(1);
848 SDOperand StackAdjustment = TailCall.getOperand(2);
849 assert(((TargetAddress.getOpcode() == ISD::Register &&
850 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX ||
851 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
852 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
853 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
854 "Expecting an global address, external symbol, or register");
855 assert(StackAdjustment.getOpcode() == ISD::Constant &&
856 "Expecting a const value");
858 SmallVector<SDOperand,8> Operands;
859 Operands.push_back(Chain.getOperand(0));
860 Operands.push_back(TargetAddress);
861 Operands.push_back(StackAdjustment);
862 // Copy registers used by the call. Last operand is a flag so it is not
864 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
865 Operands.push_back(Chain.getOperand(i));
867 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
874 SmallVector<SDOperand, 6> RetOps;
875 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
876 // Operand #1 = Bytes To Pop
877 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
879 // Copy the result values into the output registers.
880 for (unsigned i = 0; i != RVLocs.size(); ++i) {
881 CCValAssign &VA = RVLocs[i];
882 assert(VA.isRegLoc() && "Can only return in registers!");
883 SDOperand ValToCopy = Op.getOperand(i*2+1);
885 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
886 // the RET instruction and handled by the FP Stackifier.
887 if (RVLocs[i].getLocReg() == X86::ST0 ||
888 RVLocs[i].getLocReg() == X86::ST1) {
889 // If this is a copy from an xmm register to ST(0), use an FPExtend to
890 // change the value to the FP stack register class.
891 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT()))
892 ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy);
893 RetOps.push_back(ValToCopy);
894 // Don't emit a copytoreg.
898 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag);
899 Flag = Chain.getValue(1);
902 // The x86-64 ABI for returning structs by value requires that we copy
903 // the sret argument into %rax for the return. We saved the argument into
904 // a virtual register in the entry block, so now we copy the value out
906 if (Subtarget->is64Bit() &&
907 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
908 MachineFunction &MF = DAG.getMachineFunction();
909 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
910 unsigned Reg = FuncInfo->getSRetReturnReg();
912 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
913 FuncInfo->setSRetReturnReg(Reg);
915 SDOperand Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
917 Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag);
918 Flag = Chain.getValue(1);
921 RetOps[0] = Chain; // Update chain.
923 // Add the flag if we have it.
925 RetOps.push_back(Flag);
927 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size());
931 /// LowerCallResult - Lower the result values of an ISD::CALL into the
932 /// appropriate copies out of appropriate physical registers. This assumes that
933 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
934 /// being lowered. The returns a SDNode with the same number of values as the
936 SDNode *X86TargetLowering::
937 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
938 unsigned CallingConv, SelectionDAG &DAG) {
940 // Assign locations to each value returned by this call.
941 SmallVector<CCValAssign, 16> RVLocs;
942 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
943 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
944 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
946 SmallVector<SDOperand, 8> ResultVals;
948 // Copy all of the result registers out of their specified physreg.
949 for (unsigned i = 0; i != RVLocs.size(); ++i) {
950 MVT::ValueType CopyVT = RVLocs[i].getValVT();
952 // If this is a call to a function that returns an fp value on the floating
953 // point stack, but where we prefer to use the value in xmm registers, copy
954 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
955 if (RVLocs[i].getLocReg() == X86::ST0 &&
956 isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
960 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
961 CopyVT, InFlag).getValue(1);
962 SDOperand Val = Chain.getValue(0);
963 InFlag = Chain.getValue(2);
965 if (CopyVT != RVLocs[i].getValVT()) {
966 // Round the F80 the right size, which also moves to the appropriate xmm
968 Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val,
969 // This truncation won't change the value.
970 DAG.getIntPtrConstant(1));
973 ResultVals.push_back(Val);
976 // Merge everything together with a MERGE_VALUES node.
977 ResultVals.push_back(Chain);
978 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
979 &ResultVals[0], ResultVals.size()).Val;
983 //===----------------------------------------------------------------------===//
984 // C & StdCall & Fast Calling Convention implementation
985 //===----------------------------------------------------------------------===//
986 // StdCall calling convention seems to be standard for many Windows' API
987 // routines and around. It differs from C calling convention just a little:
988 // callee should clean up the stack, not caller. Symbols should be also
989 // decorated in some fancy way :) It doesn't support any vector arguments.
990 // For info on fast calling convention see Fast Calling Convention (tail call)
991 // implementation LowerX86_32FastCCCallTo.
993 /// AddLiveIn - This helper function adds the specified physical register to the
994 /// MachineFunction as a live in value. It also creates a corresponding virtual
996 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
997 const TargetRegisterClass *RC) {
998 assert(RC->contains(PReg) && "Not the correct regclass!");
999 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1000 MF.getRegInfo().addLiveIn(PReg, VReg);
1004 /// CallIsStructReturn - Determines whether a CALL node uses struct return
1006 static bool CallIsStructReturn(SDOperand Op) {
1007 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1011 return cast<ARG_FLAGSSDNode>(Op.getOperand(6))->getArgFlags().isSRet();
1014 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1015 /// return semantics.
1016 static bool ArgsAreStructReturn(SDOperand Op) {
1017 unsigned NumArgs = Op.Val->getNumValues() - 1;
1021 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
1024 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1025 /// the callee to pop its own arguments. Callee pop is necessary to support tail
1027 bool X86TargetLowering::IsCalleePop(SDOperand Op) {
1028 bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1032 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
1035 case CallingConv::X86_StdCall:
1036 return !Subtarget->is64Bit();
1037 case CallingConv::X86_FastCall:
1038 return !Subtarget->is64Bit();
1039 case CallingConv::Fast:
1040 return PerformTailCallOpt;
1044 /// CCAssignFnForNode - Selects the correct CCAssignFn for a CALL or
1045 /// FORMAL_ARGUMENTS node.
1046 CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDOperand Op) const {
1047 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1049 if (Subtarget->is64Bit()) {
1050 if (Subtarget->isTargetWin64())
1051 return CC_X86_Win64_C;
1053 if (CC == CallingConv::Fast && PerformTailCallOpt)
1054 return CC_X86_64_TailCall;
1060 if (CC == CallingConv::X86_FastCall)
1061 return CC_X86_32_FastCall;
1062 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1063 return CC_X86_32_TailCall;
1068 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1069 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1071 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDOperand Op) {
1072 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1073 if (CC == CallingConv::X86_FastCall)
1075 else if (CC == CallingConv::X86_StdCall)
1081 /// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1082 /// in a register before calling.
1083 bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1084 return !IsTailCall && !Is64Bit &&
1085 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1086 Subtarget->isPICStyleGOT();
1089 /// CallRequiresFnAddressInReg - Check whether the call requires the function
1090 /// address to be loaded in a register.
1092 X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1093 return !Is64Bit && IsTailCall &&
1094 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1095 Subtarget->isPICStyleGOT();
1098 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1099 /// by "Src" to address "Dst" with size and alignment information specified by
1100 /// the specific parameter attribute. The copy will be passed as a byval
1101 /// function parameter.
1103 CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain,
1104 ISD::ArgFlagsTy Flags, SelectionDAG &DAG) {
1105 SDOperand SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1106 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(),
1107 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1110 SDOperand X86TargetLowering::LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
1111 const CCValAssign &VA,
1112 MachineFrameInfo *MFI,
1114 SDOperand Root, unsigned i) {
1115 // Create the nodes corresponding to a load from this parameter slot.
1116 ISD::ArgFlagsTy Flags =
1117 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1118 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1119 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1121 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1122 // changed with more analysis.
1123 // In case of tail call optimization mark all arguments mutable. Since they
1124 // could be overwritten by lowering of arguments in case of a tail call.
1125 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
1126 VA.getLocMemOffset(), isImmutable);
1127 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1128 if (Flags.isByVal())
1130 return DAG.getLoad(VA.getValVT(), Root, FIN,
1131 PseudoSourceValue::getFixedStack(), FI);
1135 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
1136 MachineFunction &MF = DAG.getMachineFunction();
1137 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1139 const Function* Fn = MF.getFunction();
1140 if (Fn->hasExternalLinkage() &&
1141 Subtarget->isTargetCygMing() &&
1142 Fn->getName() == "main")
1143 FuncInfo->setForceFramePointer(true);
1145 // Decorate the function name.
1146 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1148 MachineFrameInfo *MFI = MF.getFrameInfo();
1149 SDOperand Root = Op.getOperand(0);
1150 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1151 unsigned CC = MF.getFunction()->getCallingConv();
1152 bool Is64Bit = Subtarget->is64Bit();
1153 bool IsWin64 = Subtarget->isTargetWin64();
1155 assert(!(isVarArg && CC == CallingConv::Fast) &&
1156 "Var args not supported with calling convention fastcc");
1158 // Assign locations to all of the incoming arguments.
1159 SmallVector<CCValAssign, 16> ArgLocs;
1160 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1161 CCInfo.AnalyzeFormalArguments(Op.Val, CCAssignFnForNode(Op));
1163 SmallVector<SDOperand, 8> ArgValues;
1164 unsigned LastVal = ~0U;
1165 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1166 CCValAssign &VA = ArgLocs[i];
1167 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1169 assert(VA.getValNo() != LastVal &&
1170 "Don't support value assigned to multiple locs yet");
1171 LastVal = VA.getValNo();
1173 if (VA.isRegLoc()) {
1174 MVT::ValueType RegVT = VA.getLocVT();
1175 TargetRegisterClass *RC;
1176 if (RegVT == MVT::i32)
1177 RC = X86::GR32RegisterClass;
1178 else if (Is64Bit && RegVT == MVT::i64)
1179 RC = X86::GR64RegisterClass;
1180 else if (RegVT == MVT::f32)
1181 RC = X86::FR32RegisterClass;
1182 else if (RegVT == MVT::f64)
1183 RC = X86::FR64RegisterClass;
1184 else if (MVT::isVector(RegVT) && MVT::getSizeInBits(RegVT) == 128)
1185 RC = X86::VR128RegisterClass;
1186 else if (MVT::isVector(RegVT)) {
1187 assert(MVT::getSizeInBits(RegVT) == 64);
1189 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1191 // Darwin calling convention passes MMX values in either GPRs or
1192 // XMMs in x86-64. Other targets pass them in memory.
1193 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1194 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1197 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1202 assert(0 && "Unknown argument type!");
1205 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1206 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1208 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1209 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1211 if (VA.getLocInfo() == CCValAssign::SExt)
1212 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1213 DAG.getValueType(VA.getValVT()));
1214 else if (VA.getLocInfo() == CCValAssign::ZExt)
1215 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1216 DAG.getValueType(VA.getValVT()));
1218 if (VA.getLocInfo() != CCValAssign::Full)
1219 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1221 // Handle MMX values passed in GPRs.
1222 if (Is64Bit && RegVT != VA.getLocVT()) {
1223 if (MVT::getSizeInBits(RegVT) == 64 && RC == X86::GR64RegisterClass)
1224 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1225 else if (RC == X86::VR128RegisterClass) {
1226 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue,
1227 DAG.getConstant(0, MVT::i64));
1228 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1232 ArgValues.push_back(ArgValue);
1234 assert(VA.isMemLoc());
1235 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1239 // The x86-64 ABI for returning structs by value requires that we copy
1240 // the sret argument into %rax for the return. Save the argument into
1241 // a virtual register so that we can access it from the return points.
1242 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1243 MachineFunction &MF = DAG.getMachineFunction();
1244 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1245 unsigned Reg = FuncInfo->getSRetReturnReg();
1247 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1248 FuncInfo->setSRetReturnReg(Reg);
1250 SDOperand Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
1251 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
1254 unsigned StackSize = CCInfo.getNextStackOffset();
1255 // align stack specially for tail calls
1256 if (CC == CallingConv::Fast)
1257 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1259 // If the function takes variable number of arguments, make a frame index for
1260 // the start of the first vararg value... for expansion of llvm.va_start.
1262 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1263 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1266 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1268 // FIXME: We should really autogenerate these arrays
1269 static const unsigned GPR64ArgRegsWin64[] = {
1270 X86::RCX, X86::RDX, X86::R8, X86::R9
1272 static const unsigned XMMArgRegsWin64[] = {
1273 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1275 static const unsigned GPR64ArgRegs64Bit[] = {
1276 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1278 static const unsigned XMMArgRegs64Bit[] = {
1279 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1280 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1282 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1285 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1286 GPR64ArgRegs = GPR64ArgRegsWin64;
1287 XMMArgRegs = XMMArgRegsWin64;
1289 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1290 GPR64ArgRegs = GPR64ArgRegs64Bit;
1291 XMMArgRegs = XMMArgRegs64Bit;
1293 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1295 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1298 // For X86-64, if there are vararg parameters that are passed via
1299 // registers, then we must store them to their spots on the stack so they
1300 // may be loaded by deferencing the result of va_next.
1301 VarArgsGPOffset = NumIntRegs * 8;
1302 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1303 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1304 TotalNumXMMRegs * 16, 16);
1306 // Store the integer parameter registers.
1307 SmallVector<SDOperand, 8> MemOps;
1308 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1309 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1310 DAG.getIntPtrConstant(VarArgsGPOffset));
1311 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1312 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1313 X86::GR64RegisterClass);
1314 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1316 DAG.getStore(Val.getValue(1), Val, FIN,
1317 PseudoSourceValue::getFixedStack(),
1319 MemOps.push_back(Store);
1320 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1321 DAG.getIntPtrConstant(8));
1324 // Now store the XMM (fp + vector) parameter registers.
1325 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1326 DAG.getIntPtrConstant(VarArgsFPOffset));
1327 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1328 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1329 X86::VR128RegisterClass);
1330 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1332 DAG.getStore(Val.getValue(1), Val, FIN,
1333 PseudoSourceValue::getFixedStack(),
1335 MemOps.push_back(Store);
1336 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1337 DAG.getIntPtrConstant(16));
1339 if (!MemOps.empty())
1340 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1341 &MemOps[0], MemOps.size());
1345 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1346 // arguments and the arguments after the retaddr has been pushed are
1348 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1349 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1350 (StackSize & 7) == 0)
1353 ArgValues.push_back(Root);
1355 // Some CCs need callee pop.
1356 if (IsCalleePop(Op)) {
1357 BytesToPopOnReturn = StackSize; // Callee pops everything.
1358 BytesCallerReserves = 0;
1360 BytesToPopOnReturn = 0; // Callee pops nothing.
1361 // If this is an sret function, the return should pop the hidden pointer.
1362 if (!Is64Bit && ArgsAreStructReturn(Op))
1363 BytesToPopOnReturn = 4;
1364 BytesCallerReserves = StackSize;
1368 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1369 if (CC == CallingConv::X86_FastCall)
1370 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1373 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1375 // Return the new list of results.
1376 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1377 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1381 X86TargetLowering::LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
1382 const SDOperand &StackPtr,
1383 const CCValAssign &VA,
1386 unsigned LocMemOffset = VA.getLocMemOffset();
1387 SDOperand PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1388 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1389 ISD::ArgFlagsTy Flags =
1390 cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->getArgFlags();
1391 if (Flags.isByVal()) {
1392 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
1394 return DAG.getStore(Chain, Arg, PtrOff,
1395 PseudoSourceValue::getStack(), LocMemOffset);
1398 /// EmitTailCallLoadRetAddr - Emit a load of return adress if tail call
1399 /// optimization is performed and it is required.
1401 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1402 SDOperand &OutRetAddr,
1407 if (!IsTailCall || FPDiff==0) return Chain;
1409 // Adjust the Return address stack slot.
1410 MVT::ValueType VT = getPointerTy();
1411 OutRetAddr = getReturnAddressFrameIndex(DAG);
1412 // Load the "old" Return address.
1413 OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0);
1414 return SDOperand(OutRetAddr.Val, 1);
1417 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1418 /// optimization is performed and it is required (FPDiff!=0).
1420 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1421 SDOperand Chain, SDOperand RetAddrFrIdx,
1422 bool Is64Bit, int FPDiff) {
1423 // Store the return address to the appropriate stack slot.
1424 if (!FPDiff) return Chain;
1425 // Calculate the new stack slot for the return address.
1426 int SlotSize = Is64Bit ? 8 : 4;
1427 int NewReturnAddrFI =
1428 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1429 MVT::ValueType VT = Is64Bit ? MVT::i64 : MVT::i32;
1430 SDOperand NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1431 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx,
1432 PseudoSourceValue::getFixedStack(), NewReturnAddrFI);
1436 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
1437 MachineFunction &MF = DAG.getMachineFunction();
1438 SDOperand Chain = Op.getOperand(0);
1439 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1440 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1441 bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0
1442 && CC == CallingConv::Fast && PerformTailCallOpt;
1443 SDOperand Callee = Op.getOperand(4);
1444 bool Is64Bit = Subtarget->is64Bit();
1445 bool IsStructRet = CallIsStructReturn(Op);
1447 assert(!(isVarArg && CC == CallingConv::Fast) &&
1448 "Var args not supported with calling convention fastcc");
1450 // Analyze operands of the call, assigning locations to each operand.
1451 SmallVector<CCValAssign, 16> ArgLocs;
1452 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1453 CCInfo.AnalyzeCallOperands(Op.Val, CCAssignFnForNode(Op));
1455 // Get a count of how many bytes are to be pushed on the stack.
1456 unsigned NumBytes = CCInfo.getNextStackOffset();
1457 if (CC == CallingConv::Fast)
1458 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1460 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1461 // arguments and the arguments after the retaddr has been pushed are aligned.
1462 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1463 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1464 (NumBytes & 7) == 0)
1469 // Lower arguments at fp - stackoffset + fpdiff.
1470 unsigned NumBytesCallerPushed =
1471 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1472 FPDiff = NumBytesCallerPushed - NumBytes;
1474 // Set the delta of movement of the returnaddr stackslot.
1475 // But only set if delta is greater than previous delta.
1476 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1477 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1480 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes));
1482 SDOperand RetAddrFrIdx;
1483 // Load return adress for tail calls.
1484 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1487 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1488 SmallVector<SDOperand, 8> MemOpChains;
1491 // Walk the register/memloc assignments, inserting copies/loads. In the case
1492 // of tail call optimization arguments are handle later.
1493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1494 CCValAssign &VA = ArgLocs[i];
1495 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1496 bool isByVal = cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->
1497 getArgFlags().isByVal();
1499 // Promote the value if needed.
1500 switch (VA.getLocInfo()) {
1501 default: assert(0 && "Unknown loc info!");
1502 case CCValAssign::Full: break;
1503 case CCValAssign::SExt:
1504 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1506 case CCValAssign::ZExt:
1507 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1509 case CCValAssign::AExt:
1510 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1514 if (VA.isRegLoc()) {
1516 MVT::ValueType RegVT = VA.getLocVT();
1517 if (MVT::isVector(RegVT) && MVT::getSizeInBits(RegVT) == 64)
1518 switch (VA.getLocReg()) {
1521 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1523 // Special case: passing MMX values in GPR registers.
1524 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1527 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1528 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1529 // Special case: passing MMX values in XMM registers.
1530 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1531 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg);
1532 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
1533 DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg,
1534 getMOVLMask(2, DAG));
1539 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1541 if (!IsTailCall || (IsTailCall && isByVal)) {
1542 assert(VA.isMemLoc());
1543 if (StackPtr.Val == 0)
1544 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1546 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain,
1552 if (!MemOpChains.empty())
1553 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1554 &MemOpChains[0], MemOpChains.size());
1556 // Build a sequence of copy-to-reg nodes chained together with token chain
1557 // and flag operands which copy the outgoing args into registers.
1559 // Tail call byval lowering might overwrite argument registers so in case of
1560 // tail call optimization the copies to registers are lowered later.
1562 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1563 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1565 InFlag = Chain.getValue(1);
1568 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1570 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1571 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1572 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1574 InFlag = Chain.getValue(1);
1576 // If we are tail calling and generating PIC/GOT style code load the address
1577 // of the callee into ecx. The value in ecx is used as target of the tail
1578 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1579 // calls on PIC/GOT architectures. Normally we would just put the address of
1580 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1581 // restored (since ebx is callee saved) before jumping to the target@PLT.
1582 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
1583 // Note: The actual moving to ecx is done further down.
1584 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1585 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1586 !G->getGlobal()->hasProtectedVisibility())
1587 Callee = LowerGlobalAddress(Callee, DAG);
1588 else if (isa<ExternalSymbolSDNode>(Callee))
1589 Callee = LowerExternalSymbol(Callee,DAG);
1592 if (Is64Bit && isVarArg) {
1593 // From AMD64 ABI document:
1594 // For calls that may call functions that use varargs or stdargs
1595 // (prototype-less calls or calls to functions containing ellipsis (...) in
1596 // the declaration) %al is used as hidden argument to specify the number
1597 // of SSE registers used. The contents of %al do not need to match exactly
1598 // the number of registers, but must be an ubound on the number of SSE
1599 // registers used and is in the range 0 - 8 inclusive.
1601 // FIXME: Verify this on Win64
1602 // Count the number of XMM registers allocated.
1603 static const unsigned XMMArgRegs[] = {
1604 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1605 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1607 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1609 Chain = DAG.getCopyToReg(Chain, X86::AL,
1610 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1611 InFlag = Chain.getValue(1);
1615 // For tail calls lower the arguments to the 'real' stack slot.
1617 SmallVector<SDOperand, 8> MemOpChains2;
1620 // Do not flag preceeding copytoreg stuff together with the following stuff.
1621 InFlag = SDOperand();
1622 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1623 CCValAssign &VA = ArgLocs[i];
1624 if (!VA.isRegLoc()) {
1625 assert(VA.isMemLoc());
1626 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1627 SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
1628 ISD::ArgFlagsTy Flags =
1629 cast<ARG_FLAGSSDNode>(FlagsOp)->getArgFlags();
1630 // Create frame index.
1631 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1632 uint32_t OpSize = (MVT::getSizeInBits(VA.getLocVT())+7)/8;
1633 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1634 FIN = DAG.getFrameIndex(FI, getPointerTy());
1636 if (Flags.isByVal()) {
1637 // Copy relative to framepointer.
1638 SDOperand Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1639 if (StackPtr.Val == 0)
1640 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1641 Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
1643 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1646 // Store relative to framepointer.
1647 MemOpChains2.push_back(
1648 DAG.getStore(Chain, Arg, FIN,
1649 PseudoSourceValue::getFixedStack(), FI));
1654 if (!MemOpChains2.empty())
1655 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1656 &MemOpChains2[0], MemOpChains2.size());
1658 // Copy arguments to their registers.
1659 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1660 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1662 InFlag = Chain.getValue(1);
1664 InFlag =SDOperand();
1666 // Store the return address to the appropriate stack slot.
1667 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1671 // If the callee is a GlobalAddress node (quite common, every direct call is)
1672 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1673 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1674 // We should use extra load for direct calls to dllimported functions in
1676 if ((IsTailCall || !Is64Bit ||
1677 getTargetMachine().getCodeModel() != CodeModel::Large)
1678 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1679 getTargetMachine(), true))
1680 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1681 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1682 if (IsTailCall || !Is64Bit ||
1683 getTargetMachine().getCodeModel() != CodeModel::Large)
1684 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1685 } else if (IsTailCall) {
1686 unsigned Opc = Is64Bit ? X86::R9 : X86::ECX;
1688 Chain = DAG.getCopyToReg(Chain,
1689 DAG.getRegister(Opc, getPointerTy()),
1691 Callee = DAG.getRegister(Opc, getPointerTy());
1692 // Add register as live out.
1693 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1696 // Returns a chain & a flag for retval copy to use.
1697 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1698 SmallVector<SDOperand, 8> Ops;
1701 Ops.push_back(Chain);
1702 Ops.push_back(DAG.getIntPtrConstant(NumBytes));
1703 Ops.push_back(DAG.getIntPtrConstant(0));
1705 Ops.push_back(InFlag);
1706 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1707 InFlag = Chain.getValue(1);
1709 // Returns a chain & a flag for retval copy to use.
1710 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1714 Ops.push_back(Chain);
1715 Ops.push_back(Callee);
1718 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1720 // Add argument registers to the end of the list so that they are known live
1722 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1723 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1724 RegsToPass[i].second.getValueType()));
1726 // Add an implicit use GOT pointer in EBX.
1727 if (!IsTailCall && !Is64Bit &&
1728 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1729 Subtarget->isPICStyleGOT())
1730 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1732 // Add an implicit use of AL for x86 vararg functions.
1733 if (Is64Bit && isVarArg)
1734 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1737 Ops.push_back(InFlag);
1740 assert(InFlag.Val &&
1741 "Flag must be set. Depend on flag being set in LowerRET");
1742 Chain = DAG.getNode(X86ISD::TAILCALL,
1743 Op.Val->getVTList(), &Ops[0], Ops.size());
1745 return SDOperand(Chain.Val, Op.ResNo);
1748 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
1749 InFlag = Chain.getValue(1);
1751 // Create the CALLSEQ_END node.
1752 unsigned NumBytesForCalleeToPush;
1753 if (IsCalleePop(Op))
1754 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1755 else if (!Is64Bit && IsStructRet)
1756 // If this is is a call to a struct-return function, the callee
1757 // pops the hidden struct pointer, so we have to push it back.
1758 // This is common for Darwin/X86, Linux & Mingw32 targets.
1759 NumBytesForCalleeToPush = 4;
1761 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1763 // Returns a flag for retval copy to use.
1764 Chain = DAG.getCALLSEQ_END(Chain,
1765 DAG.getIntPtrConstant(NumBytes),
1766 DAG.getIntPtrConstant(NumBytesForCalleeToPush),
1768 InFlag = Chain.getValue(1);
1770 // Handle result values, copying them out of physregs into vregs that we
1772 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1776 //===----------------------------------------------------------------------===//
1777 // Fast Calling Convention (tail call) implementation
1778 //===----------------------------------------------------------------------===//
1780 // Like std call, callee cleans arguments, convention except that ECX is
1781 // reserved for storing the tail called function address. Only 2 registers are
1782 // free for argument passing (inreg). Tail call optimization is performed
1784 // * tailcallopt is enabled
1785 // * caller/callee are fastcc
1786 // On X86_64 architecture with GOT-style position independent code only local
1787 // (within module) calls are supported at the moment.
1788 // To keep the stack aligned according to platform abi the function
1789 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1790 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1791 // If a tail called function callee has more arguments than the caller the
1792 // caller needs to make sure that there is room to move the RETADDR to. This is
1793 // achieved by reserving an area the size of the argument delta right after the
1794 // original REtADDR, but before the saved framepointer or the spilled registers
1795 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1807 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1808 /// for a 16 byte align requirement.
1809 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1810 SelectionDAG& DAG) {
1811 if (PerformTailCallOpt) {
1812 MachineFunction &MF = DAG.getMachineFunction();
1813 const TargetMachine &TM = MF.getTarget();
1814 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1815 unsigned StackAlignment = TFI.getStackAlignment();
1816 uint64_t AlignMask = StackAlignment - 1;
1817 int64_t Offset = StackSize;
1818 unsigned SlotSize = Subtarget->is64Bit() ? 8 : 4;
1819 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1820 // Number smaller than 12 so just add the difference.
1821 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1823 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1824 Offset = ((~AlignMask) & Offset) + StackAlignment +
1825 (StackAlignment-SlotSize);
1832 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1833 /// following the call is a return. A function is eligible if caller/callee
1834 /// calling conventions match, currently only fastcc supports tail calls, and
1835 /// the function CALL is immediatly followed by a RET.
1836 bool X86TargetLowering::IsEligibleForTailCallOptimization(SDOperand Call,
1838 SelectionDAG& DAG) const {
1839 if (!PerformTailCallOpt)
1842 if (CheckTailCallReturnConstraints(Call, Ret)) {
1843 MachineFunction &MF = DAG.getMachineFunction();
1844 unsigned CallerCC = MF.getFunction()->getCallingConv();
1845 unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue();
1846 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1847 SDOperand Callee = Call.getOperand(4);
1848 // On x86/32Bit PIC/GOT tail calls are supported.
1849 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1850 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
1853 // Can only do local tail calls (in same module, hidden or protected) on
1854 // x86_64 PIC/GOT at the moment.
1855 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1856 return G->getGlobal()->hasHiddenVisibility()
1857 || G->getGlobal()->hasProtectedVisibility();
1864 //===----------------------------------------------------------------------===//
1865 // Other Lowering Hooks
1866 //===----------------------------------------------------------------------===//
1869 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1870 MachineFunction &MF = DAG.getMachineFunction();
1871 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1872 int ReturnAddrIndex = FuncInfo->getRAIndex();
1874 if (ReturnAddrIndex == 0) {
1875 // Set up a frame object for the return address.
1876 if (Subtarget->is64Bit())
1877 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1879 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1881 FuncInfo->setRAIndex(ReturnAddrIndex);
1884 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1889 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1890 /// specific condition code. It returns a false if it cannot do a direct
1891 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1893 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1894 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1895 SelectionDAG &DAG) {
1896 X86CC = X86::COND_INVALID;
1898 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1899 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1900 // X > -1 -> X == 0, jump !sign.
1901 RHS = DAG.getConstant(0, RHS.getValueType());
1902 X86CC = X86::COND_NS;
1904 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1905 // X < 0 -> X == 0, jump on sign.
1906 X86CC = X86::COND_S;
1908 } else if (SetCCOpcode == ISD::SETLT && RHSC->getValue() == 1) {
1910 RHS = DAG.getConstant(0, RHS.getValueType());
1911 X86CC = X86::COND_LE;
1916 switch (SetCCOpcode) {
1918 case ISD::SETEQ: X86CC = X86::COND_E; break;
1919 case ISD::SETGT: X86CC = X86::COND_G; break;
1920 case ISD::SETGE: X86CC = X86::COND_GE; break;
1921 case ISD::SETLT: X86CC = X86::COND_L; break;
1922 case ISD::SETLE: X86CC = X86::COND_LE; break;
1923 case ISD::SETNE: X86CC = X86::COND_NE; break;
1924 case ISD::SETULT: X86CC = X86::COND_B; break;
1925 case ISD::SETUGT: X86CC = X86::COND_A; break;
1926 case ISD::SETULE: X86CC = X86::COND_BE; break;
1927 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1930 // On a floating point condition, the flags are set as follows:
1932 // 0 | 0 | 0 | X > Y
1933 // 0 | 0 | 1 | X < Y
1934 // 1 | 0 | 0 | X == Y
1935 // 1 | 1 | 1 | unordered
1937 switch (SetCCOpcode) {
1940 case ISD::SETEQ: X86CC = X86::COND_E; break;
1941 case ISD::SETOLT: Flip = true; // Fallthrough
1943 case ISD::SETGT: X86CC = X86::COND_A; break;
1944 case ISD::SETOLE: Flip = true; // Fallthrough
1946 case ISD::SETGE: X86CC = X86::COND_AE; break;
1947 case ISD::SETUGT: Flip = true; // Fallthrough
1949 case ISD::SETLT: X86CC = X86::COND_B; break;
1950 case ISD::SETUGE: Flip = true; // Fallthrough
1952 case ISD::SETLE: X86CC = X86::COND_BE; break;
1954 case ISD::SETNE: X86CC = X86::COND_NE; break;
1955 case ISD::SETUO: X86CC = X86::COND_P; break;
1956 case ISD::SETO: X86CC = X86::COND_NP; break;
1959 std::swap(LHS, RHS);
1962 return X86CC != X86::COND_INVALID;
1965 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1966 /// code. Current x86 isa includes the following FP cmov instructions:
1967 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1968 static bool hasFPCMov(unsigned X86CC) {
1984 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
1985 /// true if Op is undef or if its value falls within the specified range (L, H].
1986 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1987 if (Op.getOpcode() == ISD::UNDEF)
1990 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
1991 return (Val >= Low && Val < Hi);
1994 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
1995 /// true if Op is undef or if its value equal to the specified value.
1996 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
1997 if (Op.getOpcode() == ISD::UNDEF)
1999 return cast<ConstantSDNode>(Op)->getValue() == Val;
2002 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2003 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
2004 bool X86::isPSHUFDMask(SDNode *N) {
2005 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2007 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
2010 // Check if the value doesn't reference the second vector.
2011 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2012 SDOperand Arg = N->getOperand(i);
2013 if (Arg.getOpcode() == ISD::UNDEF) continue;
2014 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2015 if (cast<ConstantSDNode>(Arg)->getValue() >= e)
2022 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2023 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2024 bool X86::isPSHUFHWMask(SDNode *N) {
2025 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2027 if (N->getNumOperands() != 8)
2030 // Lower quadword copied in order.
2031 for (unsigned i = 0; i != 4; ++i) {
2032 SDOperand Arg = N->getOperand(i);
2033 if (Arg.getOpcode() == ISD::UNDEF) continue;
2034 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2035 if (cast<ConstantSDNode>(Arg)->getValue() != i)
2039 // Upper quadword shuffled.
2040 for (unsigned i = 4; i != 8; ++i) {
2041 SDOperand Arg = N->getOperand(i);
2042 if (Arg.getOpcode() == ISD::UNDEF) continue;
2043 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2044 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2045 if (Val < 4 || Val > 7)
2052 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2053 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2054 bool X86::isPSHUFLWMask(SDNode *N) {
2055 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2057 if (N->getNumOperands() != 8)
2060 // Upper quadword copied in order.
2061 for (unsigned i = 4; i != 8; ++i)
2062 if (!isUndefOrEqual(N->getOperand(i), i))
2065 // Lower quadword shuffled.
2066 for (unsigned i = 0; i != 4; ++i)
2067 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2073 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2074 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2075 static bool isSHUFPMask(SDOperandPtr Elems, unsigned NumElems) {
2076 if (NumElems != 2 && NumElems != 4) return false;
2078 unsigned Half = NumElems / 2;
2079 for (unsigned i = 0; i < Half; ++i)
2080 if (!isUndefOrInRange(Elems[i], 0, NumElems))
2082 for (unsigned i = Half; i < NumElems; ++i)
2083 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
2089 bool X86::isSHUFPMask(SDNode *N) {
2090 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2091 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
2094 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2095 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2096 /// half elements to come from vector 1 (which would equal the dest.) and
2097 /// the upper half to come from vector 2.
2098 static bool isCommutedSHUFP(SDOperandPtr Ops, unsigned NumOps) {
2099 if (NumOps != 2 && NumOps != 4) return false;
2101 unsigned Half = NumOps / 2;
2102 for (unsigned i = 0; i < Half; ++i)
2103 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
2105 for (unsigned i = Half; i < NumOps; ++i)
2106 if (!isUndefOrInRange(Ops[i], 0, NumOps))
2111 static bool isCommutedSHUFP(SDNode *N) {
2112 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2113 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
2116 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2117 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2118 bool X86::isMOVHLPSMask(SDNode *N) {
2119 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2121 if (N->getNumOperands() != 4)
2124 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2125 return isUndefOrEqual(N->getOperand(0), 6) &&
2126 isUndefOrEqual(N->getOperand(1), 7) &&
2127 isUndefOrEqual(N->getOperand(2), 2) &&
2128 isUndefOrEqual(N->getOperand(3), 3);
2131 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2132 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2134 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2135 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2137 if (N->getNumOperands() != 4)
2140 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2141 return isUndefOrEqual(N->getOperand(0), 2) &&
2142 isUndefOrEqual(N->getOperand(1), 3) &&
2143 isUndefOrEqual(N->getOperand(2), 2) &&
2144 isUndefOrEqual(N->getOperand(3), 3);
2147 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2148 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2149 bool X86::isMOVLPMask(SDNode *N) {
2150 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2152 unsigned NumElems = N->getNumOperands();
2153 if (NumElems != 2 && NumElems != 4)
2156 for (unsigned i = 0; i < NumElems/2; ++i)
2157 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2160 for (unsigned i = NumElems/2; i < NumElems; ++i)
2161 if (!isUndefOrEqual(N->getOperand(i), i))
2167 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2168 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2170 bool X86::isMOVHPMask(SDNode *N) {
2171 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2173 unsigned NumElems = N->getNumOperands();
2174 if (NumElems != 2 && NumElems != 4)
2177 for (unsigned i = 0; i < NumElems/2; ++i)
2178 if (!isUndefOrEqual(N->getOperand(i), i))
2181 for (unsigned i = 0; i < NumElems/2; ++i) {
2182 SDOperand Arg = N->getOperand(i + NumElems/2);
2183 if (!isUndefOrEqual(Arg, i + NumElems))
2190 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2191 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2192 bool static isUNPCKLMask(SDOperandPtr Elts, unsigned NumElts,
2193 bool V2IsSplat = false) {
2194 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2197 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2198 SDOperand BitI = Elts[i];
2199 SDOperand BitI1 = Elts[i+1];
2200 if (!isUndefOrEqual(BitI, j))
2203 if (isUndefOrEqual(BitI1, NumElts))
2206 if (!isUndefOrEqual(BitI1, j + NumElts))
2214 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2215 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2216 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2219 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2220 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2221 bool static isUNPCKHMask(SDOperandPtr Elts, unsigned NumElts,
2222 bool V2IsSplat = false) {
2223 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2226 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2227 SDOperand BitI = Elts[i];
2228 SDOperand BitI1 = Elts[i+1];
2229 if (!isUndefOrEqual(BitI, j + NumElts/2))
2232 if (isUndefOrEqual(BitI1, NumElts))
2235 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2243 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2244 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2245 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2248 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2249 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2251 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2252 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2254 unsigned NumElems = N->getNumOperands();
2255 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2258 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2259 SDOperand BitI = N->getOperand(i);
2260 SDOperand BitI1 = N->getOperand(i+1);
2262 if (!isUndefOrEqual(BitI, j))
2264 if (!isUndefOrEqual(BitI1, j))
2271 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2272 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2274 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2275 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2277 unsigned NumElems = N->getNumOperands();
2278 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2281 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2282 SDOperand BitI = N->getOperand(i);
2283 SDOperand BitI1 = N->getOperand(i + 1);
2285 if (!isUndefOrEqual(BitI, j))
2287 if (!isUndefOrEqual(BitI1, j))
2294 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2295 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2296 /// MOVSD, and MOVD, i.e. setting the lowest element.
2297 static bool isMOVLMask(SDOperandPtr Elts, unsigned NumElts) {
2298 if (NumElts != 2 && NumElts != 4)
2301 if (!isUndefOrEqual(Elts[0], NumElts))
2304 for (unsigned i = 1; i < NumElts; ++i) {
2305 if (!isUndefOrEqual(Elts[i], i))
2312 bool X86::isMOVLMask(SDNode *N) {
2313 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2314 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2317 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2318 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2319 /// element of vector 2 and the other elements to come from vector 1 in order.
2320 static bool isCommutedMOVL(SDOperandPtr Ops, unsigned NumOps,
2321 bool V2IsSplat = false,
2322 bool V2IsUndef = false) {
2323 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2326 if (!isUndefOrEqual(Ops[0], 0))
2329 for (unsigned i = 1; i < NumOps; ++i) {
2330 SDOperand Arg = Ops[i];
2331 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2332 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2333 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2340 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2341 bool V2IsUndef = false) {
2342 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2343 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2344 V2IsSplat, V2IsUndef);
2347 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2348 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2349 bool X86::isMOVSHDUPMask(SDNode *N) {
2350 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2352 if (N->getNumOperands() != 4)
2355 // Expect 1, 1, 3, 3
2356 for (unsigned i = 0; i < 2; ++i) {
2357 SDOperand Arg = N->getOperand(i);
2358 if (Arg.getOpcode() == ISD::UNDEF) continue;
2359 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2360 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2361 if (Val != 1) return false;
2365 for (unsigned i = 2; i < 4; ++i) {
2366 SDOperand Arg = N->getOperand(i);
2367 if (Arg.getOpcode() == ISD::UNDEF) continue;
2368 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2369 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2370 if (Val != 3) return false;
2374 // Don't use movshdup if it can be done with a shufps.
2378 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2379 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2380 bool X86::isMOVSLDUPMask(SDNode *N) {
2381 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2383 if (N->getNumOperands() != 4)
2386 // Expect 0, 0, 2, 2
2387 for (unsigned i = 0; i < 2; ++i) {
2388 SDOperand Arg = N->getOperand(i);
2389 if (Arg.getOpcode() == ISD::UNDEF) continue;
2390 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2391 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2392 if (Val != 0) return false;
2396 for (unsigned i = 2; i < 4; ++i) {
2397 SDOperand Arg = N->getOperand(i);
2398 if (Arg.getOpcode() == ISD::UNDEF) continue;
2399 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2400 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2401 if (Val != 2) return false;
2405 // Don't use movshdup if it can be done with a shufps.
2409 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2410 /// specifies a identity operation on the LHS or RHS.
2411 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2412 unsigned NumElems = N->getNumOperands();
2413 for (unsigned i = 0; i < NumElems; ++i)
2414 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2419 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2420 /// a splat of a single element.
2421 static bool isSplatMask(SDNode *N) {
2422 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2424 // This is a splat operation if each element of the permute is the same, and
2425 // if the value doesn't reference the second vector.
2426 unsigned NumElems = N->getNumOperands();
2427 SDOperand ElementBase;
2429 for (; i != NumElems; ++i) {
2430 SDOperand Elt = N->getOperand(i);
2431 if (isa<ConstantSDNode>(Elt)) {
2437 if (!ElementBase.Val)
2440 for (; i != NumElems; ++i) {
2441 SDOperand Arg = N->getOperand(i);
2442 if (Arg.getOpcode() == ISD::UNDEF) continue;
2443 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2444 if (Arg != ElementBase) return false;
2447 // Make sure it is a splat of the first vector operand.
2448 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
2451 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2452 /// a splat of a single element and it's a 2 or 4 element mask.
2453 bool X86::isSplatMask(SDNode *N) {
2454 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2456 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2457 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2459 return ::isSplatMask(N);
2462 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2463 /// specifies a splat of zero element.
2464 bool X86::isSplatLoMask(SDNode *N) {
2465 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2467 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2468 if (!isUndefOrEqual(N->getOperand(i), 0))
2473 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2474 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2476 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2477 unsigned NumOperands = N->getNumOperands();
2478 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2480 for (unsigned i = 0; i < NumOperands; ++i) {
2482 SDOperand Arg = N->getOperand(NumOperands-i-1);
2483 if (Arg.getOpcode() != ISD::UNDEF)
2484 Val = cast<ConstantSDNode>(Arg)->getValue();
2485 if (Val >= NumOperands) Val -= NumOperands;
2487 if (i != NumOperands - 1)
2494 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2495 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2497 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2499 // 8 nodes, but we only care about the last 4.
2500 for (unsigned i = 7; i >= 4; --i) {
2502 SDOperand Arg = N->getOperand(i);
2503 if (Arg.getOpcode() != ISD::UNDEF)
2504 Val = cast<ConstantSDNode>(Arg)->getValue();
2513 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2514 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2516 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2518 // 8 nodes, but we only care about the first 4.
2519 for (int i = 3; i >= 0; --i) {
2521 SDOperand Arg = N->getOperand(i);
2522 if (Arg.getOpcode() != ISD::UNDEF)
2523 Val = cast<ConstantSDNode>(Arg)->getValue();
2532 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2533 /// specifies a 8 element shuffle that can be broken into a pair of
2534 /// PSHUFHW and PSHUFLW.
2535 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2536 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2538 if (N->getNumOperands() != 8)
2541 // Lower quadword shuffled.
2542 for (unsigned i = 0; i != 4; ++i) {
2543 SDOperand Arg = N->getOperand(i);
2544 if (Arg.getOpcode() == ISD::UNDEF) continue;
2545 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2546 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2551 // Upper quadword shuffled.
2552 for (unsigned i = 4; i != 8; ++i) {
2553 SDOperand Arg = N->getOperand(i);
2554 if (Arg.getOpcode() == ISD::UNDEF) continue;
2555 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2556 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2557 if (Val < 4 || Val > 7)
2564 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2565 /// values in ther permute mask.
2566 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2567 SDOperand &V2, SDOperand &Mask,
2568 SelectionDAG &DAG) {
2569 MVT::ValueType VT = Op.getValueType();
2570 MVT::ValueType MaskVT = Mask.getValueType();
2571 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
2572 unsigned NumElems = Mask.getNumOperands();
2573 SmallVector<SDOperand, 8> MaskVec;
2575 for (unsigned i = 0; i != NumElems; ++i) {
2576 SDOperand Arg = Mask.getOperand(i);
2577 if (Arg.getOpcode() == ISD::UNDEF) {
2578 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2581 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2582 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2584 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2586 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2590 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2591 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2594 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2595 /// the two vector operands have swapped position.
2597 SDOperand CommuteVectorShuffleMask(SDOperand Mask, SelectionDAG &DAG) {
2598 MVT::ValueType MaskVT = Mask.getValueType();
2599 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
2600 unsigned NumElems = Mask.getNumOperands();
2601 SmallVector<SDOperand, 8> MaskVec;
2602 for (unsigned i = 0; i != NumElems; ++i) {
2603 SDOperand Arg = Mask.getOperand(i);
2604 if (Arg.getOpcode() == ISD::UNDEF) {
2605 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2608 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2609 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2611 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2613 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2615 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2619 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2620 /// match movhlps. The lower half elements should come from upper half of
2621 /// V1 (and in order), and the upper half elements should come from the upper
2622 /// half of V2 (and in order).
2623 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2624 unsigned NumElems = Mask->getNumOperands();
2627 for (unsigned i = 0, e = 2; i != e; ++i)
2628 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2630 for (unsigned i = 2; i != 4; ++i)
2631 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2636 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2637 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2639 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2640 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2641 N = N->getOperand(0).Val;
2642 if (ISD::isNON_EXTLoad(N)) {
2644 *LD = cast<LoadSDNode>(N);
2651 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2652 /// match movlp{s|d}. The lower half elements should come from lower half of
2653 /// V1 (and in order), and the upper half elements should come from the upper
2654 /// half of V2 (and in order). And since V1 will become the source of the
2655 /// MOVLP, it must be either a vector load or a scalar load to vector.
2656 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2657 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2659 // Is V2 is a vector load, don't do this transformation. We will try to use
2660 // load folding shufps op.
2661 if (ISD::isNON_EXTLoad(V2))
2664 unsigned NumElems = Mask->getNumOperands();
2665 if (NumElems != 2 && NumElems != 4)
2667 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2668 if (!isUndefOrEqual(Mask->getOperand(i), i))
2670 for (unsigned i = NumElems/2; i != NumElems; ++i)
2671 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2676 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2678 static bool isSplatVector(SDNode *N) {
2679 if (N->getOpcode() != ISD::BUILD_VECTOR)
2682 SDOperand SplatValue = N->getOperand(0);
2683 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2684 if (N->getOperand(i) != SplatValue)
2689 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2691 static bool isUndefShuffle(SDNode *N) {
2692 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2695 SDOperand V1 = N->getOperand(0);
2696 SDOperand V2 = N->getOperand(1);
2697 SDOperand Mask = N->getOperand(2);
2698 unsigned NumElems = Mask.getNumOperands();
2699 for (unsigned i = 0; i != NumElems; ++i) {
2700 SDOperand Arg = Mask.getOperand(i);
2701 if (Arg.getOpcode() != ISD::UNDEF) {
2702 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2703 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2705 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2712 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2714 static inline bool isZeroNode(SDOperand Elt) {
2715 return ((isa<ConstantSDNode>(Elt) &&
2716 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2717 (isa<ConstantFPSDNode>(Elt) &&
2718 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2721 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2722 /// to an zero vector.
2723 static bool isZeroShuffle(SDNode *N) {
2724 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2727 SDOperand V1 = N->getOperand(0);
2728 SDOperand V2 = N->getOperand(1);
2729 SDOperand Mask = N->getOperand(2);
2730 unsigned NumElems = Mask.getNumOperands();
2731 for (unsigned i = 0; i != NumElems; ++i) {
2732 SDOperand Arg = Mask.getOperand(i);
2733 if (Arg.getOpcode() == ISD::UNDEF)
2736 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
2737 if (Idx < NumElems) {
2738 unsigned Opc = V1.Val->getOpcode();
2739 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.Val))
2741 if (Opc != ISD::BUILD_VECTOR ||
2742 !isZeroNode(V1.Val->getOperand(Idx)))
2744 } else if (Idx >= NumElems) {
2745 unsigned Opc = V2.Val->getOpcode();
2746 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.Val))
2748 if (Opc != ISD::BUILD_VECTOR ||
2749 !isZeroNode(V2.Val->getOperand(Idx - NumElems)))
2756 /// getZeroVector - Returns a vector of specified type with all zero elements.
2758 static SDOperand getZeroVector(MVT::ValueType VT, bool HasSSE2,
2759 SelectionDAG &DAG) {
2760 assert(MVT::isVector(VT) && "Expected a vector type");
2762 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2763 // type. This ensures they get CSE'd.
2765 if (MVT::getSizeInBits(VT) == 64) { // MMX
2766 SDOperand Cst = DAG.getTargetConstant(0, MVT::i32);
2767 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2768 } else if (HasSSE2) { // SSE2
2769 SDOperand Cst = DAG.getTargetConstant(0, MVT::i32);
2770 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2772 SDOperand Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2773 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst);
2775 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2778 /// getOnesVector - Returns a vector of specified type with all bits set.
2780 static SDOperand getOnesVector(MVT::ValueType VT, SelectionDAG &DAG) {
2781 assert(MVT::isVector(VT) && "Expected a vector type");
2783 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2784 // type. This ensures they get CSE'd.
2785 SDOperand Cst = DAG.getTargetConstant(~0U, MVT::i32);
2787 if (MVT::getSizeInBits(VT) == 64) // MMX
2788 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2790 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2791 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2795 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2796 /// that point to V2 points to its first element.
2797 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2798 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2800 bool Changed = false;
2801 SmallVector<SDOperand, 8> MaskVec;
2802 unsigned NumElems = Mask.getNumOperands();
2803 for (unsigned i = 0; i != NumElems; ++i) {
2804 SDOperand Arg = Mask.getOperand(i);
2805 if (Arg.getOpcode() != ISD::UNDEF) {
2806 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2807 if (Val > NumElems) {
2808 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2812 MaskVec.push_back(Arg);
2816 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2817 &MaskVec[0], MaskVec.size());
2821 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2822 /// operation of specified width.
2823 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2824 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2825 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2827 SmallVector<SDOperand, 8> MaskVec;
2828 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2829 for (unsigned i = 1; i != NumElems; ++i)
2830 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2831 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2834 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2835 /// of specified width.
2836 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2837 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2838 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2839 SmallVector<SDOperand, 8> MaskVec;
2840 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2841 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2842 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2844 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2847 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2848 /// of specified width.
2849 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2850 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2851 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2852 unsigned Half = NumElems/2;
2853 SmallVector<SDOperand, 8> MaskVec;
2854 for (unsigned i = 0; i != Half; ++i) {
2855 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2856 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2858 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2861 /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
2862 /// element #0 of a vector with the specified index, leaving the rest of the
2863 /// elements in place.
2864 static SDOperand getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
2865 SelectionDAG &DAG) {
2866 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2867 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2868 SmallVector<SDOperand, 8> MaskVec;
2869 // Element #0 of the result gets the elt we are replacing.
2870 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
2871 for (unsigned i = 1; i != NumElems; ++i)
2872 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
2873 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2876 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
2877 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG, bool HasSSE2) {
2878 MVT::ValueType PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32;
2879 MVT::ValueType VT = Op.getValueType();
2882 SDOperand V1 = Op.getOperand(0);
2883 SDOperand Mask = Op.getOperand(2);
2884 unsigned NumElems = Mask.getNumOperands();
2885 // Special handling of v4f32 -> v4i32.
2886 if (VT != MVT::v4f32) {
2887 Mask = getUnpacklMask(NumElems, DAG);
2888 while (NumElems > 4) {
2889 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2892 Mask = getZeroVector(MVT::v4i32, true, DAG);
2895 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
2896 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
2897 DAG.getNode(ISD::UNDEF, PVT), Mask);
2898 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2901 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2902 /// vector of zero or undef vector. This produces a shuffle where the low
2903 /// element of V2 is swizzled into the zero/undef vector, landing at element
2904 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
2905 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, unsigned Idx,
2906 bool isZero, bool HasSSE2,
2907 SelectionDAG &DAG) {
2908 MVT::ValueType VT = V2.getValueType();
2909 SDOperand V1 = isZero
2910 ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT);
2911 unsigned NumElems = MVT::getVectorNumElements(V2.getValueType());
2912 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2913 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
2914 SmallVector<SDOperand, 16> MaskVec;
2915 for (unsigned i = 0; i != NumElems; ++i)
2916 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
2917 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
2919 MaskVec.push_back(DAG.getConstant(i, EVT));
2920 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2921 &MaskVec[0], MaskVec.size());
2922 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2925 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2927 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2928 unsigned NumNonZero, unsigned NumZero,
2929 SelectionDAG &DAG, TargetLowering &TLI) {
2935 for (unsigned i = 0; i < 16; ++i) {
2936 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2937 if (ThisIsNonZero && First) {
2939 V = getZeroVector(MVT::v8i16, true, DAG);
2941 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2946 SDOperand ThisElt(0, 0), LastElt(0, 0);
2947 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2948 if (LastIsNonZero) {
2949 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2951 if (ThisIsNonZero) {
2952 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2953 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2954 ThisElt, DAG.getConstant(8, MVT::i8));
2956 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2961 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
2962 DAG.getIntPtrConstant(i/2));
2966 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2969 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
2971 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2972 unsigned NumNonZero, unsigned NumZero,
2973 SelectionDAG &DAG, TargetLowering &TLI) {
2979 for (unsigned i = 0; i < 8; ++i) {
2980 bool isNonZero = (NonZeros & (1 << i)) != 0;
2984 V = getZeroVector(MVT::v8i16, true, DAG);
2986 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2989 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
2990 DAG.getIntPtrConstant(i));
2998 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2999 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3000 if (ISD::isBuildVectorAllZeros(Op.Val) || ISD::isBuildVectorAllOnes(Op.Val)) {
3001 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3002 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3003 // eliminated on x86-32 hosts.
3004 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3007 if (ISD::isBuildVectorAllOnes(Op.Val))
3008 return getOnesVector(Op.getValueType(), DAG);
3009 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG);
3012 MVT::ValueType VT = Op.getValueType();
3013 MVT::ValueType EVT = MVT::getVectorElementType(VT);
3014 unsigned EVTBits = MVT::getSizeInBits(EVT);
3016 unsigned NumElems = Op.getNumOperands();
3017 unsigned NumZero = 0;
3018 unsigned NumNonZero = 0;
3019 unsigned NonZeros = 0;
3020 bool IsAllConstants = true;
3021 SmallSet<SDOperand, 8> Values;
3022 for (unsigned i = 0; i < NumElems; ++i) {
3023 SDOperand Elt = Op.getOperand(i);
3024 if (Elt.getOpcode() == ISD::UNDEF)
3027 if (Elt.getOpcode() != ISD::Constant &&
3028 Elt.getOpcode() != ISD::ConstantFP)
3029 IsAllConstants = false;
3030 if (isZeroNode(Elt))
3033 NonZeros |= (1 << i);
3038 if (NumNonZero == 0) {
3039 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3040 return DAG.getNode(ISD::UNDEF, VT);
3043 // Special case for single non-zero, non-undef, element.
3044 if (NumNonZero == 1 && NumElems <= 4) {
3045 unsigned Idx = CountTrailingZeros_32(NonZeros);
3046 SDOperand Item = Op.getOperand(Idx);
3048 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3049 // the value are obviously zero, truncate the value to i32 and do the
3050 // insertion that way. Only do this if the value is non-constant or if the
3051 // value is a constant being inserted into element 0. It is cheaper to do
3052 // a constant pool load than it is to do a movd + shuffle.
3053 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3054 (!IsAllConstants || Idx == 0)) {
3055 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3056 // Handle MMX and SSE both.
3057 MVT::ValueType VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3058 MVT::ValueType VecElts = VT == MVT::v2i64 ? 4 : 2;
3060 // Truncate the value (which may itself be a constant) to i32, and
3061 // convert it to a vector with movd (S2V+shuffle to zero extend).
3062 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item);
3063 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item);
3064 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3065 Subtarget->hasSSE2(), DAG);
3067 // Now we have our 32-bit value zero extended in the low element of
3068 // a vector. If Idx != 0, swizzle it into place.
3071 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()),
3072 getSwapEltZeroMask(VecElts, Idx, DAG)
3074 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3);
3076 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item);
3080 // If we have a constant or non-constant insertion into the low element of
3081 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3082 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3083 // depending on what the source datatype is. Because we can only get here
3084 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
3086 // Don't do this for i64 values on x86-32.
3087 (EVT != MVT::i64 || Subtarget->is64Bit())) {
3088 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3089 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3090 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3091 Subtarget->hasSSE2(), DAG);
3094 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3097 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3098 // is a non-constant being inserted into an element other than the low one,
3099 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3100 // movd/movss) to move this into the low element, then shuffle it into
3102 if (EVTBits == 32) {
3103 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3105 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3106 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3107 Subtarget->hasSSE2(), DAG);
3108 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3109 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
3110 SmallVector<SDOperand, 8> MaskVec;
3111 for (unsigned i = 0; i < NumElems; i++)
3112 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
3113 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3114 &MaskVec[0], MaskVec.size());
3115 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
3116 DAG.getNode(ISD::UNDEF, VT), Mask);
3120 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3121 if (Values.size() == 1)
3124 // A vector full of immediates; various special cases are already
3125 // handled, so this is best done with a single constant-pool load.
3129 // Let legalizer expand 2-wide build_vectors.
3130 if (EVTBits == 64) {
3131 if (NumNonZero == 1) {
3132 // One half is zero or undef.
3133 unsigned Idx = CountTrailingZeros_32(NonZeros);
3134 SDOperand V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT,
3135 Op.getOperand(Idx));
3136 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3137 Subtarget->hasSSE2(), DAG);
3142 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3143 if (EVTBits == 8 && NumElems == 16) {
3144 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3146 if (V.Val) return V;
3149 if (EVTBits == 16 && NumElems == 8) {
3150 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3152 if (V.Val) return V;
3155 // If element VT is == 32 bits, turn it into a number of shuffles.
3156 SmallVector<SDOperand, 8> V;
3158 if (NumElems == 4 && NumZero > 0) {
3159 for (unsigned i = 0; i < 4; ++i) {
3160 bool isZero = !(NonZeros & (1 << i));
3162 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3164 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3167 for (unsigned i = 0; i < 2; ++i) {
3168 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3171 V[i] = V[i*2]; // Must be a zero vector.
3174 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
3175 getMOVLMask(NumElems, DAG));
3178 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3179 getMOVLMask(NumElems, DAG));
3182 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3183 getUnpacklMask(NumElems, DAG));
3188 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3189 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
3190 SmallVector<SDOperand, 8> MaskVec;
3191 bool Reverse = (NonZeros & 0x3) == 2;
3192 for (unsigned i = 0; i < 2; ++i)
3194 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3196 MaskVec.push_back(DAG.getConstant(i, EVT));
3197 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3198 for (unsigned i = 0; i < 2; ++i)
3200 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3202 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
3203 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3204 &MaskVec[0], MaskVec.size());
3205 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
3208 if (Values.size() > 2) {
3209 // Expand into a number of unpckl*.
3211 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3212 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3213 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3214 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
3215 for (unsigned i = 0; i < NumElems; ++i)
3216 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3218 while (NumElems != 0) {
3219 for (unsigned i = 0; i < NumElems; ++i)
3220 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3231 SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2,
3232 SDOperand PermMask, SelectionDAG &DAG,
3233 TargetLowering &TLI) {
3235 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(8);
3236 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
3237 MVT::ValueType PtrVT = TLI.getPointerTy();
3238 SmallVector<SDOperand, 8> MaskElts(PermMask.Val->op_begin(),
3239 PermMask.Val->op_end());
3241 // First record which half of which vector the low elements come from.
3242 SmallVector<unsigned, 4> LowQuad(4);
3243 for (unsigned i = 0; i < 4; ++i) {
3244 SDOperand Elt = MaskElts[i];
3245 if (Elt.getOpcode() == ISD::UNDEF)
3247 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3248 int QuadIdx = EltIdx / 4;
3251 int BestLowQuad = -1;
3252 unsigned MaxQuad = 1;
3253 for (unsigned i = 0; i < 4; ++i) {
3254 if (LowQuad[i] > MaxQuad) {
3256 MaxQuad = LowQuad[i];
3260 // Record which half of which vector the high elements come from.
3261 SmallVector<unsigned, 4> HighQuad(4);
3262 for (unsigned i = 4; i < 8; ++i) {
3263 SDOperand Elt = MaskElts[i];
3264 if (Elt.getOpcode() == ISD::UNDEF)
3266 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3267 int QuadIdx = EltIdx / 4;
3268 ++HighQuad[QuadIdx];
3270 int BestHighQuad = -1;
3272 for (unsigned i = 0; i < 4; ++i) {
3273 if (HighQuad[i] > MaxQuad) {
3275 MaxQuad = HighQuad[i];
3279 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
3280 if (BestLowQuad != -1 || BestHighQuad != -1) {
3281 // First sort the 4 chunks in order using shufpd.
3282 SmallVector<SDOperand, 8> MaskVec;
3283 if (BestLowQuad != -1)
3284 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3286 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
3287 if (BestHighQuad != -1)
3288 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3290 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3291 SDOperand Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
3292 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3293 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3294 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3295 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3297 // Now sort high and low parts separately.
3298 BitVector InOrder(8);
3299 if (BestLowQuad != -1) {
3300 // Sort lower half in order using PSHUFLW.
3302 bool AnyOutOrder = false;
3303 for (unsigned i = 0; i != 4; ++i) {
3304 SDOperand Elt = MaskElts[i];
3305 if (Elt.getOpcode() == ISD::UNDEF) {
3306 MaskVec.push_back(Elt);
3309 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3312 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3313 // If this element is in the right place after this shuffle, then
3315 if ((int)(EltIdx / 4) == BestLowQuad)
3320 for (unsigned i = 4; i != 8; ++i)
3321 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3322 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3323 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3327 if (BestHighQuad != -1) {
3328 // Sort high half in order using PSHUFHW if possible.
3330 for (unsigned i = 0; i != 4; ++i)
3331 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3332 bool AnyOutOrder = false;
3333 for (unsigned i = 4; i != 8; ++i) {
3334 SDOperand Elt = MaskElts[i];
3335 if (Elt.getOpcode() == ISD::UNDEF) {
3336 MaskVec.push_back(Elt);
3339 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3342 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3343 // If this element is in the right place after this shuffle, then
3345 if ((int)(EltIdx / 4) == BestHighQuad)
3350 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3351 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3355 // The other elements are put in the right place using pextrw and pinsrw.
3356 for (unsigned i = 0; i != 8; ++i) {
3359 SDOperand Elt = MaskElts[i];
3360 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3363 SDOperand ExtOp = (EltIdx < 8)
3364 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3365 DAG.getConstant(EltIdx, PtrVT))
3366 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3367 DAG.getConstant(EltIdx - 8, PtrVT));
3368 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3369 DAG.getConstant(i, PtrVT));
3374 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use
3375 ///as few as possible.
3376 // First, let's find out how many elements are already in the right order.
3377 unsigned V1InOrder = 0;
3378 unsigned V1FromV1 = 0;
3379 unsigned V2InOrder = 0;
3380 unsigned V2FromV2 = 0;
3381 SmallVector<SDOperand, 8> V1Elts;
3382 SmallVector<SDOperand, 8> V2Elts;
3383 for (unsigned i = 0; i < 8; ++i) {
3384 SDOperand Elt = MaskElts[i];
3385 if (Elt.getOpcode() == ISD::UNDEF) {
3386 V1Elts.push_back(Elt);
3387 V2Elts.push_back(Elt);
3392 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3394 V1Elts.push_back(Elt);
3395 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3397 } else if (EltIdx == i+8) {
3398 V1Elts.push_back(Elt);
3399 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3401 } else if (EltIdx < 8) {
3402 V1Elts.push_back(Elt);
3405 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3410 if (V2InOrder > V1InOrder) {
3411 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3413 std::swap(V1Elts, V2Elts);
3414 std::swap(V1FromV1, V2FromV2);
3417 if ((V1FromV1 + V1InOrder) != 8) {
3418 // Some elements are from V2.
3420 // If there are elements that are from V1 but out of place,
3421 // then first sort them in place
3422 SmallVector<SDOperand, 8> MaskVec;
3423 for (unsigned i = 0; i < 8; ++i) {
3424 SDOperand Elt = V1Elts[i];
3425 if (Elt.getOpcode() == ISD::UNDEF) {
3426 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3429 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3431 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3433 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3435 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3436 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
3440 for (unsigned i = 0; i < 8; ++i) {
3441 SDOperand Elt = V1Elts[i];
3442 if (Elt.getOpcode() == ISD::UNDEF)
3444 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3447 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3448 DAG.getConstant(EltIdx - 8, PtrVT));
3449 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3450 DAG.getConstant(i, PtrVT));
3454 // All elements are from V1.
3456 for (unsigned i = 0; i < 8; ++i) {
3457 SDOperand Elt = V1Elts[i];
3458 if (Elt.getOpcode() == ISD::UNDEF)
3460 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3461 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3462 DAG.getConstant(EltIdx, PtrVT));
3463 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3464 DAG.getConstant(i, PtrVT));
3470 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3471 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3472 /// done when every pair / quad of shuffle mask elements point to elements in
3473 /// the right sequence. e.g.
3474 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3476 SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2,
3478 SDOperand PermMask, SelectionDAG &DAG,
3479 TargetLowering &TLI) {
3480 unsigned NumElems = PermMask.getNumOperands();
3481 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3482 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3483 MVT::ValueType NewVT = MaskVT;
3485 case MVT::v4f32: NewVT = MVT::v2f64; break;
3486 case MVT::v4i32: NewVT = MVT::v2i64; break;
3487 case MVT::v8i16: NewVT = MVT::v4i32; break;
3488 case MVT::v16i8: NewVT = MVT::v4i32; break;
3489 default: assert(false && "Unexpected!");
3492 if (NewWidth == 2) {
3493 if (MVT::isInteger(VT))
3498 unsigned Scale = NumElems / NewWidth;
3499 SmallVector<SDOperand, 8> MaskVec;
3500 for (unsigned i = 0; i < NumElems; i += Scale) {
3501 unsigned StartIdx = ~0U;
3502 for (unsigned j = 0; j < Scale; ++j) {
3503 SDOperand Elt = PermMask.getOperand(i+j);
3504 if (Elt.getOpcode() == ISD::UNDEF)
3506 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3507 if (StartIdx == ~0U)
3508 StartIdx = EltIdx - (EltIdx % Scale);
3509 if (EltIdx != StartIdx + j)
3512 if (StartIdx == ~0U)
3513 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
3515 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MVT::i32));
3518 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3519 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3520 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3521 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3522 &MaskVec[0], MaskVec.size()));
3525 /// getVZextMovL - Return a zero-extending vector move low node.
3527 static SDOperand getVZextMovL(MVT::ValueType VT, MVT::ValueType OpVT,
3528 SDOperand SrcOp, SelectionDAG &DAG,
3529 const X86Subtarget *Subtarget) {
3530 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3531 LoadSDNode *LD = NULL;
3532 if (!isScalarLoadToVector(SrcOp.Val, &LD))
3533 LD = dyn_cast<LoadSDNode>(SrcOp);
3535 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3537 MVT::ValueType EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3538 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3539 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3540 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3541 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3543 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3544 return DAG.getNode(ISD::BIT_CONVERT, VT,
3545 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3546 DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT,
3547 SrcOp.getOperand(0).getOperand(0))));
3552 return DAG.getNode(ISD::BIT_CONVERT, VT,
3553 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3554 DAG.getNode(ISD::BIT_CONVERT, OpVT, SrcOp)));
3558 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
3559 SDOperand V1 = Op.getOperand(0);
3560 SDOperand V2 = Op.getOperand(1);
3561 SDOperand PermMask = Op.getOperand(2);
3562 MVT::ValueType VT = Op.getValueType();
3563 unsigned NumElems = PermMask.getNumOperands();
3564 bool isMMX = MVT::getSizeInBits(VT) == 64;
3565 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3566 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
3567 bool V1IsSplat = false;
3568 bool V2IsSplat = false;
3570 if (isUndefShuffle(Op.Val))
3571 return DAG.getNode(ISD::UNDEF, VT);
3573 if (isZeroShuffle(Op.Val))
3574 return getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3576 if (isIdentityMask(PermMask.Val))
3578 else if (isIdentityMask(PermMask.Val, true))
3581 if (isSplatMask(PermMask.Val)) {
3582 if (isMMX || NumElems < 4) return Op;
3583 // Promote it to a v4{if}32 splat.
3584 return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
3587 // If the shuffle can be profitably rewritten as a narrower shuffle, then
3589 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
3590 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3592 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3593 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
3594 // FIXME: Figure out a cleaner way to do this.
3595 // Try to make use of movq to zero out the top part.
3596 if (ISD::isBuildVectorAllZeros(V2.Val)) {
3597 SDOperand NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
3600 SDOperand NewV1 = NewOp.getOperand(0);
3601 SDOperand NewV2 = NewOp.getOperand(1);
3602 SDOperand NewMask = NewOp.getOperand(2);
3603 if (isCommutedMOVL(NewMask.Val, true, false)) {
3604 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
3605 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget);
3608 } else if (ISD::isBuildVectorAllZeros(V1.Val)) {
3609 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
3611 if (NewOp.Val && X86::isMOVLMask(NewOp.getOperand(2).Val))
3612 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
3617 if (X86::isMOVLMask(PermMask.Val)) {
3620 if (ISD::isBuildVectorAllZeros(V1.Val))
3621 return getVZextMovL(VT, VT, V2, DAG, Subtarget);
3625 if (X86::isMOVSHDUPMask(PermMask.Val) ||
3626 X86::isMOVSLDUPMask(PermMask.Val) ||
3627 X86::isMOVHLPSMask(PermMask.Val) ||
3628 X86::isMOVHPMask(PermMask.Val) ||
3629 X86::isMOVLPMask(PermMask.Val))
3632 if (ShouldXformToMOVHLPS(PermMask.Val) ||
3633 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
3634 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3636 bool Commuted = false;
3637 // FIXME: This should also accept a bitcast of a splat? Be careful, not
3638 // 1,1,1,1 -> v8i16 though.
3639 V1IsSplat = isSplatVector(V1.Val);
3640 V2IsSplat = isSplatVector(V2.Val);
3642 // Canonicalize the splat or undef, if present, to be on the RHS.
3643 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
3644 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3645 std::swap(V1IsSplat, V2IsSplat);
3646 std::swap(V1IsUndef, V2IsUndef);
3650 // FIXME: Figure out a cleaner way to do this.
3651 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
3652 if (V2IsUndef) return V1;
3653 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3655 // V2 is a splat, so the mask may be malformed. That is, it may point
3656 // to any V2 element. The instruction selectior won't like this. Get
3657 // a corrected mask and commute to form a proper MOVS{S|D}.
3658 SDOperand NewMask = getMOVLMask(NumElems, DAG);
3659 if (NewMask.Val != PermMask.Val)
3660 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3665 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3666 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
3667 X86::isUNPCKLMask(PermMask.Val) ||
3668 X86::isUNPCKHMask(PermMask.Val))
3672 // Normalize mask so all entries that point to V2 points to its first
3673 // element then try to match unpck{h|l} again. If match, return a
3674 // new vector_shuffle with the corrected mask.
3675 SDOperand NewMask = NormalizeMask(PermMask, DAG);
3676 if (NewMask.Val != PermMask.Val) {
3677 if (X86::isUNPCKLMask(PermMask.Val, true)) {
3678 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
3679 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3680 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
3681 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
3682 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3687 // Normalize the node to match x86 shuffle ops if needed
3688 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
3689 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3692 // Commute is back and try unpck* again.
3693 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3694 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3695 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
3696 X86::isUNPCKLMask(PermMask.Val) ||
3697 X86::isUNPCKHMask(PermMask.Val))
3701 // Try PSHUF* first, then SHUFP*.
3702 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically
3703 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
3704 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.Val)) {
3705 if (V2.getOpcode() != ISD::UNDEF)
3706 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3707 DAG.getNode(ISD::UNDEF, VT), PermMask);
3712 if (Subtarget->hasSSE2() &&
3713 (X86::isPSHUFDMask(PermMask.Val) ||
3714 X86::isPSHUFHWMask(PermMask.Val) ||
3715 X86::isPSHUFLWMask(PermMask.Val))) {
3716 MVT::ValueType RVT = VT;
3717 if (VT == MVT::v4f32) {
3719 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT,
3720 DAG.getNode(ISD::BIT_CONVERT, RVT, V1),
3721 DAG.getNode(ISD::UNDEF, RVT), PermMask);
3722 } else if (V2.getOpcode() != ISD::UNDEF)
3723 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1,
3724 DAG.getNode(ISD::UNDEF, RVT), PermMask);
3726 Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
3730 // Binary or unary shufps.
3731 if (X86::isSHUFPMask(PermMask.Val) ||
3732 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.Val)))
3736 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
3737 if (VT == MVT::v8i16) {
3738 SDOperand NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
3743 // Handle all 4 wide cases with a number of shuffles.
3744 if (NumElems == 4 && !isMMX) {
3745 // Don't do this for MMX.
3746 MVT::ValueType MaskVT = PermMask.getValueType();
3747 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
3748 SmallVector<std::pair<int, int>, 8> Locs;
3749 Locs.reserve(NumElems);
3750 SmallVector<SDOperand, 8> Mask1(NumElems,
3751 DAG.getNode(ISD::UNDEF, MaskEVT));
3752 SmallVector<SDOperand, 8> Mask2(NumElems,
3753 DAG.getNode(ISD::UNDEF, MaskEVT));
3756 // If no more than two elements come from either vector. This can be
3757 // implemented with two shuffles. First shuffle gather the elements.
3758 // The second shuffle, which takes the first shuffle as both of its
3759 // vector operands, put the elements into the right order.
3760 for (unsigned i = 0; i != NumElems; ++i) {
3761 SDOperand Elt = PermMask.getOperand(i);
3762 if (Elt.getOpcode() == ISD::UNDEF) {
3763 Locs[i] = std::make_pair(-1, -1);
3765 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
3766 if (Val < NumElems) {
3767 Locs[i] = std::make_pair(0, NumLo);
3771 Locs[i] = std::make_pair(1, NumHi);
3772 if (2+NumHi < NumElems)
3773 Mask1[2+NumHi] = Elt;
3778 if (NumLo <= 2 && NumHi <= 2) {
3779 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3780 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3781 &Mask1[0], Mask1.size()));
3782 for (unsigned i = 0; i != NumElems; ++i) {
3783 if (Locs[i].first == -1)
3786 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
3787 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
3788 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3792 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3793 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3794 &Mask2[0], Mask2.size()));
3797 // Break it into (shuffle shuffle_hi, shuffle_lo).
3799 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3800 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3801 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
3802 unsigned MaskIdx = 0;
3804 unsigned HiIdx = NumElems/2;
3805 for (unsigned i = 0; i != NumElems; ++i) {
3806 if (i == NumElems/2) {
3812 SDOperand Elt = PermMask.getOperand(i);
3813 if (Elt.getOpcode() == ISD::UNDEF) {
3814 Locs[i] = std::make_pair(-1, -1);
3815 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
3816 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3817 (*MaskPtr)[LoIdx] = Elt;
3820 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3821 (*MaskPtr)[HiIdx] = Elt;
3826 SDOperand LoShuffle =
3827 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3828 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3829 &LoMask[0], LoMask.size()));
3830 SDOperand HiShuffle =
3831 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3832 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3833 &HiMask[0], HiMask.size()));
3834 SmallVector<SDOperand, 8> MaskOps;
3835 for (unsigned i = 0; i != NumElems; ++i) {
3836 if (Locs[i].first == -1) {
3837 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3839 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
3840 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3843 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3844 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3845 &MaskOps[0], MaskOps.size()));
3852 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op,
3853 SelectionDAG &DAG) {
3854 MVT::ValueType VT = Op.getValueType();
3855 if (MVT::getSizeInBits(VT) == 8) {
3856 SDOperand Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
3857 Op.getOperand(0), Op.getOperand(1));
3858 SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
3859 DAG.getValueType(VT));
3860 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3861 } else if (MVT::getSizeInBits(VT) == 16) {
3862 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
3863 Op.getOperand(0), Op.getOperand(1));
3864 SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
3865 DAG.getValueType(VT));
3866 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3867 } else if (VT == MVT::f32) {
3868 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
3869 // the result back to FR32 register. It's only worth matching if the
3870 // result has a single use which is a store or a bitcast to i32.
3871 if (!Op.hasOneUse())
3873 SDNode *User = Op.Val->use_begin()->getUser();
3874 if (User->getOpcode() != ISD::STORE &&
3875 (User->getOpcode() != ISD::BIT_CONVERT ||
3876 User->getValueType(0) != MVT::i32))
3878 SDOperand Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
3879 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)),
3881 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract);
3888 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3889 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3892 if (Subtarget->hasSSE41()) {
3893 SDOperand Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
3898 MVT::ValueType VT = Op.getValueType();
3899 // TODO: handle v16i8.
3900 if (MVT::getSizeInBits(VT) == 16) {
3901 SDOperand Vec = Op.getOperand(0);
3902 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3904 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
3905 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
3906 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
3908 // Transform it so it match pextrw which produces a 32-bit result.
3909 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
3910 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
3911 Op.getOperand(0), Op.getOperand(1));
3912 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
3913 DAG.getValueType(VT));
3914 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3915 } else if (MVT::getSizeInBits(VT) == 32) {
3916 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3919 // SHUFPS the element to the lowest double word, then movss.
3920 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3921 SmallVector<SDOperand, 8> IdxVec;
3923 push_back(DAG.getConstant(Idx, MVT::getVectorElementType(MaskVT)));
3925 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3927 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3929 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3930 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3931 &IdxVec[0], IdxVec.size());
3932 SDOperand Vec = Op.getOperand(0);
3933 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3934 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3935 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3936 DAG.getIntPtrConstant(0));
3937 } else if (MVT::getSizeInBits(VT) == 64) {
3938 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
3939 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
3940 // to match extract_elt for f64.
3941 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3945 // UNPCKHPD the element to the lowest double word, then movsd.
3946 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
3947 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
3948 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3949 SmallVector<SDOperand, 8> IdxVec;
3950 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorElementType(MaskVT)));
3952 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3953 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3954 &IdxVec[0], IdxVec.size());
3955 SDOperand Vec = Op.getOperand(0);
3956 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3957 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3958 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3959 DAG.getIntPtrConstant(0));
3966 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG){
3967 MVT::ValueType VT = Op.getValueType();
3968 MVT::ValueType EVT = MVT::getVectorElementType(VT);
3970 SDOperand N0 = Op.getOperand(0);
3971 SDOperand N1 = Op.getOperand(1);
3972 SDOperand N2 = Op.getOperand(2);
3974 if ((MVT::getSizeInBits(EVT) == 8) || (MVT::getSizeInBits(EVT) == 16)) {
3975 unsigned Opc = (MVT::getSizeInBits(EVT) == 8) ? X86ISD::PINSRB
3977 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
3979 if (N1.getValueType() != MVT::i32)
3980 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
3981 if (N2.getValueType() != MVT::i32)
3982 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
3983 return DAG.getNode(Opc, VT, N0, N1, N2);
3984 } else if (EVT == MVT::f32) {
3985 // Bits [7:6] of the constant are the source select. This will always be
3986 // zero here. The DAG Combiner may combine an extract_elt index into these
3987 // bits. For example (insert (extract, 3), 2) could be matched by putting
3988 // the '3' into bits [7:6] of X86ISD::INSERTPS.
3989 // Bits [5:4] of the constant are the destination select. This is the
3990 // value of the incoming immediate.
3991 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
3992 // combine either bitwise AND or insert of float 0.0 to set these bits.
3993 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue() << 4);
3994 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
4000 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
4001 MVT::ValueType VT = Op.getValueType();
4002 MVT::ValueType EVT = MVT::getVectorElementType(VT);
4004 if (Subtarget->hasSSE41())
4005 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4010 SDOperand N0 = Op.getOperand(0);
4011 SDOperand N1 = Op.getOperand(1);
4012 SDOperand N2 = Op.getOperand(2);
4014 if (MVT::getSizeInBits(EVT) == 16) {
4015 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4016 // as its second argument.
4017 if (N1.getValueType() != MVT::i32)
4018 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4019 if (N2.getValueType() != MVT::i32)
4020 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
4021 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
4027 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
4028 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
4029 MVT::ValueType VT = MVT::v2i32;
4030 switch (Op.getValueType()) {
4037 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(),
4038 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt));
4041 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4042 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4043 // one of the above mentioned nodes. It has to be wrapped because otherwise
4044 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4045 // be used to form addressing mode. These wrapped nodes will be selected
4048 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
4049 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4050 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
4052 CP->getAlignment());
4053 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4054 // With PIC, the address is actually $g + Offset.
4055 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4056 !Subtarget->isPICStyleRIPRel()) {
4057 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4058 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4066 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
4067 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4068 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
4069 // If it's a debug information descriptor, don't mess with it.
4070 if (DAG.isVerifiedDebugInfoDesc(Op))
4072 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4073 // With PIC, the address is actually $g + Offset.
4074 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4075 !Subtarget->isPICStyleRIPRel()) {
4076 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4077 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4081 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4082 // load the value at address GV, not the value of GV itself. This means that
4083 // the GlobalAddress must be in the base or index register of the address, not
4084 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
4085 // The same applies for external symbols during PIC codegen
4086 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
4087 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result,
4088 PseudoSourceValue::getGOT(), 0);
4093 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4095 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4096 const MVT::ValueType PtrVT) {
4098 SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
4099 DAG.getNode(X86ISD::GlobalBaseReg,
4101 InFlag = Chain.getValue(1);
4103 // emit leal symbol@TLSGD(,%ebx,1), %eax
4104 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4105 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4106 GA->getValueType(0),
4108 SDOperand Ops[] = { Chain, TGA, InFlag };
4109 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
4110 InFlag = Result.getValue(2);
4111 Chain = Result.getValue(1);
4113 // call ___tls_get_addr. This function receives its argument in
4114 // the register EAX.
4115 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
4116 InFlag = Chain.getValue(1);
4118 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4119 SDOperand Ops1[] = { Chain,
4120 DAG.getTargetExternalSymbol("___tls_get_addr",
4122 DAG.getRegister(X86::EAX, PtrVT),
4123 DAG.getRegister(X86::EBX, PtrVT),
4125 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
4126 InFlag = Chain.getValue(1);
4128 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
4131 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4133 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4134 const MVT::ValueType PtrVT) {
4135 SDOperand InFlag, Chain;
4137 // emit leaq symbol@TLSGD(%rip), %rdi
4138 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4139 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4140 GA->getValueType(0),
4142 SDOperand Ops[] = { DAG.getEntryNode(), TGA};
4143 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2);
4144 Chain = Result.getValue(1);
4145 InFlag = Result.getValue(2);
4147 // call ___tls_get_addr. This function receives its argument in
4148 // the register RDI.
4149 Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag);
4150 InFlag = Chain.getValue(1);
4152 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4153 SDOperand Ops1[] = { Chain,
4154 DAG.getTargetExternalSymbol("___tls_get_addr",
4156 DAG.getRegister(X86::RDI, PtrVT),
4158 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4);
4159 InFlag = Chain.getValue(1);
4161 return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag);
4164 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4165 // "local exec" model.
4167 LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4168 const MVT::ValueType PtrVT) {
4169 // Get the Thread Pointer
4170 SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
4171 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4173 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4174 GA->getValueType(0),
4176 SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
4178 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
4179 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset,
4180 PseudoSourceValue::getGOT(), 0);
4182 // The address of the thread local variable is the add of the thread
4183 // pointer with the offset of the variable.
4184 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
4188 X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
4189 // TODO: implement the "local dynamic" model
4190 // TODO: implement the "initial exec"model for pic executables
4191 assert(Subtarget->isTargetELF() &&
4192 "TLS not implemented for non-ELF targets");
4193 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4194 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
4195 // otherwise use the "Local Exec"TLS Model
4196 if (Subtarget->is64Bit()) {
4197 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4199 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4200 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4202 return LowerToTLSExecModel(GA, DAG, getPointerTy());
4207 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
4208 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4209 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
4210 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4211 // With PIC, the address is actually $g + Offset.
4212 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4213 !Subtarget->isPICStyleRIPRel()) {
4214 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4215 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4222 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
4223 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4224 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
4225 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4226 // With PIC, the address is actually $g + Offset.
4227 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4228 !Subtarget->isPICStyleRIPRel()) {
4229 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4230 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4237 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4238 /// take a 2 x i32 value to shift plus a shift amount.
4239 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
4240 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4241 MVT::ValueType VT = Op.getValueType();
4242 unsigned VTBits = MVT::getSizeInBits(VT);
4243 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4244 SDOperand ShOpLo = Op.getOperand(0);
4245 SDOperand ShOpHi = Op.getOperand(1);
4246 SDOperand ShAmt = Op.getOperand(2);
4247 SDOperand Tmp1 = isSRA ?
4248 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) :
4249 DAG.getConstant(0, VT);
4251 SDOperand Tmp2, Tmp3;
4252 if (Op.getOpcode() == ISD::SHL_PARTS) {
4253 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt);
4254 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt);
4256 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt);
4257 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt);
4260 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
4261 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
4262 DAG.getConstant(VTBits, MVT::i8));
4263 SDOperand Cond = DAG.getNode(X86ISD::CMP, VT,
4264 AndNode, DAG.getConstant(0, MVT::i8));
4267 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4268 VTs = DAG.getNodeValueTypes(VT, MVT::Flag);
4269 SmallVector<SDOperand, 4> Ops;
4270 if (Op.getOpcode() == ISD::SHL_PARTS) {
4271 Ops.push_back(Tmp2);
4272 Ops.push_back(Tmp3);
4274 Ops.push_back(Cond);
4275 Hi = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size());
4278 Ops.push_back(Tmp3);
4279 Ops.push_back(Tmp1);
4281 Ops.push_back(Cond);
4282 Lo = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size());
4284 Ops.push_back(Tmp2);
4285 Ops.push_back(Tmp3);
4287 Ops.push_back(Cond);
4288 Lo = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size());
4291 Ops.push_back(Tmp3);
4292 Ops.push_back(Tmp1);
4294 Ops.push_back(Cond);
4295 Hi = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size());
4298 VTs = DAG.getNodeValueTypes(VT, VT);
4302 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
4305 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
4306 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
4307 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
4308 "Unknown SINT_TO_FP to lower!");
4310 // These are really Legal; caller falls through into that case.
4311 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4313 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
4314 Subtarget->is64Bit())
4317 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
4318 MachineFunction &MF = DAG.getMachineFunction();
4319 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4320 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4321 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
4323 PseudoSourceValue::getFixedStack(),
4328 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4330 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4332 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4333 SmallVector<SDOperand, 8> Ops;
4334 Ops.push_back(Chain);
4335 Ops.push_back(StackSlot);
4336 Ops.push_back(DAG.getValueType(SrcVT));
4337 SDOperand Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD,
4338 Tys, &Ops[0], Ops.size());
4341 Chain = Result.getValue(1);
4342 SDOperand InFlag = Result.getValue(2);
4344 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4345 // shouldn't be necessary except that RFP cannot be live across
4346 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4347 MachineFunction &MF = DAG.getMachineFunction();
4348 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4349 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4350 Tys = DAG.getVTList(MVT::Other);
4351 SmallVector<SDOperand, 8> Ops;
4352 Ops.push_back(Chain);
4353 Ops.push_back(Result);
4354 Ops.push_back(StackSlot);
4355 Ops.push_back(DAG.getValueType(Op.getValueType()));
4356 Ops.push_back(InFlag);
4357 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
4358 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
4359 PseudoSourceValue::getFixedStack(), SSFI);
4365 std::pair<SDOperand,SDOperand> X86TargetLowering::
4366 FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) {
4367 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
4368 "Unknown FP_TO_SINT to lower!");
4370 // These are really Legal.
4371 if (Op.getValueType() == MVT::i32 &&
4372 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
4373 return std::make_pair(SDOperand(), SDOperand());
4374 if (Subtarget->is64Bit() &&
4375 Op.getValueType() == MVT::i64 &&
4376 Op.getOperand(0).getValueType() != MVT::f80)
4377 return std::make_pair(SDOperand(), SDOperand());
4379 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
4381 MachineFunction &MF = DAG.getMachineFunction();
4382 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
4383 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4384 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4386 switch (Op.getValueType()) {
4387 default: assert(0 && "Invalid FP_TO_SINT to lower!");
4388 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
4389 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
4390 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
4393 SDOperand Chain = DAG.getEntryNode();
4394 SDOperand Value = Op.getOperand(0);
4395 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
4396 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
4397 Chain = DAG.getStore(Chain, Value, StackSlot,
4398 PseudoSourceValue::getFixedStack(), SSFI);
4399 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
4401 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
4403 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
4404 Chain = Value.getValue(1);
4405 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4406 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4409 // Build the FP_TO_INT*_IN_MEM
4410 SDOperand Ops[] = { Chain, Value, StackSlot };
4411 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
4413 return std::make_pair(FIST, StackSlot);
4416 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
4417 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(Op, DAG);
4418 SDOperand FIST = Vals.first, StackSlot = Vals.second;
4419 if (FIST.Val == 0) return SDOperand();
4422 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
4425 SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) {
4426 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(SDOperand(N, 0), DAG);
4427 SDOperand FIST = Vals.first, StackSlot = Vals.second;
4428 if (FIST.Val == 0) return 0;
4430 // Return an i64 load from the stack slot.
4431 SDOperand Res = DAG.getLoad(MVT::i64, FIST, StackSlot, NULL, 0);
4433 // Use a MERGE_VALUES node to drop the chain result value.
4434 return DAG.getNode(ISD::MERGE_VALUES, MVT::i64, Res).Val;
4437 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
4438 MVT::ValueType VT = Op.getValueType();
4439 MVT::ValueType EltVT = VT;
4440 if (MVT::isVector(VT))
4441 EltVT = MVT::getVectorElementType(VT);
4442 std::vector<Constant*> CV;
4443 if (EltVT == MVT::f64) {
4444 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
4448 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
4454 Constant *C = ConstantVector::get(CV);
4455 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4456 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4457 PseudoSourceValue::getConstantPool(), 0,
4459 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
4462 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
4463 MVT::ValueType VT = Op.getValueType();
4464 MVT::ValueType EltVT = VT;
4465 unsigned EltNum = 1;
4466 if (MVT::isVector(VT)) {
4467 EltVT = MVT::getVectorElementType(VT);
4468 EltNum = MVT::getVectorNumElements(VT);
4470 std::vector<Constant*> CV;
4471 if (EltVT == MVT::f64) {
4472 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
4476 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
4482 Constant *C = ConstantVector::get(CV);
4483 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4484 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4485 PseudoSourceValue::getConstantPool(), 0,
4487 if (MVT::isVector(VT)) {
4488 return DAG.getNode(ISD::BIT_CONVERT, VT,
4489 DAG.getNode(ISD::XOR, MVT::v2i64,
4490 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
4491 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
4493 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
4497 SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
4498 SDOperand Op0 = Op.getOperand(0);
4499 SDOperand Op1 = Op.getOperand(1);
4500 MVT::ValueType VT = Op.getValueType();
4501 MVT::ValueType SrcVT = Op1.getValueType();
4503 // If second operand is smaller, extend it first.
4504 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) {
4505 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
4508 // And if it is bigger, shrink it first.
4509 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
4510 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
4514 // At this point the operands and the result should have the same
4515 // type, and that won't be f80 since that is not custom lowered.
4517 // First get the sign bit of second operand.
4518 std::vector<Constant*> CV;
4519 if (SrcVT == MVT::f64) {
4520 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
4521 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4523 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
4524 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4525 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4526 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4528 Constant *C = ConstantVector::get(CV);
4529 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4530 SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
4531 PseudoSourceValue::getConstantPool(), 0,
4533 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
4535 // Shift sign bit right or left if the two operands have different types.
4536 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
4537 // Op0 is MVT::f32, Op1 is MVT::f64.
4538 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
4539 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
4540 DAG.getConstant(32, MVT::i32));
4541 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
4542 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
4543 DAG.getIntPtrConstant(0));
4546 // Clear first operand sign bit.
4548 if (VT == MVT::f64) {
4549 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
4550 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4552 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
4553 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4554 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4555 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4557 C = ConstantVector::get(CV);
4558 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4559 SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4560 PseudoSourceValue::getConstantPool(), 0,
4562 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
4564 // Or the value with the sign bit.
4565 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
4568 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
4569 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
4571 SDOperand Op0 = Op.getOperand(0);
4572 SDOperand Op1 = Op.getOperand(1);
4573 SDOperand CC = Op.getOperand(2);
4574 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4575 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
4578 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
4580 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4581 return DAG.getNode(X86ISD::SETCC, MVT::i8,
4582 DAG.getConstant(X86CC, MVT::i8), Cond);
4585 assert(isFP && "Illegal integer SetCC!");
4587 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4588 switch (SetCCOpcode) {
4589 default: assert(false && "Illegal floating point SetCC!");
4590 case ISD::SETOEQ: { // !PF & ZF
4591 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4592 DAG.getConstant(X86::COND_NP, MVT::i8), Cond);
4593 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4594 DAG.getConstant(X86::COND_E, MVT::i8), Cond);
4595 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
4597 case ISD::SETUNE: { // PF | !ZF
4598 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4599 DAG.getConstant(X86::COND_P, MVT::i8), Cond);
4600 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4601 DAG.getConstant(X86::COND_NE, MVT::i8), Cond);
4602 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
4608 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
4609 bool addTest = true;
4610 SDOperand Cond = Op.getOperand(0);
4613 if (Cond.getOpcode() == ISD::SETCC)
4614 Cond = LowerSETCC(Cond, DAG);
4616 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4617 // setting operand in place of the X86ISD::SETCC.
4618 if (Cond.getOpcode() == X86ISD::SETCC) {
4619 CC = Cond.getOperand(0);
4621 SDOperand Cmp = Cond.getOperand(1);
4622 unsigned Opc = Cmp.getOpcode();
4623 MVT::ValueType VT = Op.getValueType();
4625 bool IllegalFPCMov = false;
4626 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT) &&
4627 !isScalarFPTypeInSSEReg(VT)) // FPStack?
4628 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
4630 if ((Opc == X86ISD::CMP ||
4631 Opc == X86ISD::COMI ||
4632 Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
4639 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4640 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
4643 const MVT::ValueType *VTs = DAG.getNodeValueTypes(Op.getValueType(),
4645 SmallVector<SDOperand, 4> Ops;
4646 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
4647 // condition is true.
4648 Ops.push_back(Op.getOperand(2));
4649 Ops.push_back(Op.getOperand(1));
4651 Ops.push_back(Cond);
4652 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
4655 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
4656 bool addTest = true;
4657 SDOperand Chain = Op.getOperand(0);
4658 SDOperand Cond = Op.getOperand(1);
4659 SDOperand Dest = Op.getOperand(2);
4662 if (Cond.getOpcode() == ISD::SETCC)
4663 Cond = LowerSETCC(Cond, DAG);
4665 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4666 // setting operand in place of the X86ISD::SETCC.
4667 if (Cond.getOpcode() == X86ISD::SETCC) {
4668 CC = Cond.getOperand(0);
4670 SDOperand Cmp = Cond.getOperand(1);
4671 unsigned Opc = Cmp.getOpcode();
4672 if (Opc == X86ISD::CMP ||
4673 Opc == X86ISD::COMI ||
4674 Opc == X86ISD::UCOMI) {
4681 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4682 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
4684 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
4685 Chain, Op.getOperand(2), CC, Cond);
4689 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
4690 // Calls to _alloca is needed to probe the stack when allocating more than 4k
4691 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
4692 // that the guard pages used by the OS virtual memory manager are allocated in
4693 // correct sequence.
4695 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
4696 SelectionDAG &DAG) {
4697 assert(Subtarget->isTargetCygMing() &&
4698 "This should be used only on Cygwin/Mingw targets");
4701 SDOperand Chain = Op.getOperand(0);
4702 SDOperand Size = Op.getOperand(1);
4703 // FIXME: Ensure alignment here
4707 MVT::ValueType IntPtr = getPointerTy();
4708 MVT::ValueType SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
4710 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
4711 Flag = Chain.getValue(1);
4713 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4714 SDOperand Ops[] = { Chain,
4715 DAG.getTargetExternalSymbol("_alloca", IntPtr),
4716 DAG.getRegister(X86::EAX, IntPtr),
4718 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 4);
4719 Flag = Chain.getValue(1);
4721 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
4723 std::vector<MVT::ValueType> Tys;
4724 Tys.push_back(SPTy);
4725 Tys.push_back(MVT::Other);
4726 SDOperand Ops1[2] = { Chain.getValue(0), Chain };
4727 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops1, 2);
4731 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
4733 SDOperand Dst, SDOperand Src,
4734 SDOperand Size, unsigned Align,
4735 const Value *DstSV, uint64_t DstSVOff) {
4736 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
4738 /// If not DWORD aligned or size is more than the threshold, call the library.
4739 /// The libc version is likely to be faster for these cases. It can use the
4740 /// address value and run time information about the CPU.
4741 if ((Align & 3) == 0 ||
4743 ConstantSize->getValue() > getSubtarget()->getMaxInlineSizeThreshold()) {
4744 SDOperand InFlag(0, 0);
4746 // Check to see if there is a specialized entry-point for memory zeroing.
4747 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
4748 if (const char *bzeroEntry =
4749 V && V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
4750 MVT::ValueType IntPtr = getPointerTy();
4751 const Type *IntPtrTy = getTargetData()->getIntPtrType();
4752 TargetLowering::ArgListTy Args;
4753 TargetLowering::ArgListEntry Entry;
4755 Entry.Ty = IntPtrTy;
4756 Args.push_back(Entry);
4758 Args.push_back(Entry);
4759 std::pair<SDOperand,SDOperand> CallResult =
4760 LowerCallTo(Chain, Type::VoidTy, false, false, false, CallingConv::C,
4761 false, DAG.getExternalSymbol(bzeroEntry, IntPtr),
4763 return CallResult.second;
4766 // Otherwise have the target-independent code call memset.
4770 uint64_t SizeVal = ConstantSize->getValue();
4771 SDOperand InFlag(0, 0);
4774 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
4775 unsigned BytesLeft = 0;
4776 bool TwoRepStos = false;
4779 uint64_t Val = ValC->getValue() & 255;
4781 // If the value is a constant, then we can potentially use larger sets.
4782 switch (Align & 3) {
4783 case 2: // WORD aligned
4786 Val = (Val << 8) | Val;
4788 case 0: // DWORD aligned
4791 Val = (Val << 8) | Val;
4792 Val = (Val << 16) | Val;
4793 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
4796 Val = (Val << 32) | Val;
4799 default: // Byte aligned
4802 Count = DAG.getIntPtrConstant(SizeVal);
4806 if (AVT > MVT::i8) {
4807 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4808 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
4809 BytesLeft = SizeVal % UBytes;
4812 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
4814 InFlag = Chain.getValue(1);
4817 Count = DAG.getIntPtrConstant(SizeVal);
4818 Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag);
4819 InFlag = Chain.getValue(1);
4822 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4824 InFlag = Chain.getValue(1);
4825 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4827 InFlag = Chain.getValue(1);
4829 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4830 SmallVector<SDOperand, 8> Ops;
4831 Ops.push_back(Chain);
4832 Ops.push_back(DAG.getValueType(AVT));
4833 Ops.push_back(InFlag);
4834 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4837 InFlag = Chain.getValue(1);
4839 MVT::ValueType CVT = Count.getValueType();
4840 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
4841 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4842 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4844 InFlag = Chain.getValue(1);
4845 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4847 Ops.push_back(Chain);
4848 Ops.push_back(DAG.getValueType(MVT::i8));
4849 Ops.push_back(InFlag);
4850 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4851 } else if (BytesLeft) {
4852 // Handle the last 1 - 7 bytes.
4853 unsigned Offset = SizeVal - BytesLeft;
4854 MVT::ValueType AddrVT = Dst.getValueType();
4855 MVT::ValueType SizeVT = Size.getValueType();
4857 Chain = DAG.getMemset(Chain,
4858 DAG.getNode(ISD::ADD, AddrVT, Dst,
4859 DAG.getConstant(Offset, AddrVT)),
4861 DAG.getConstant(BytesLeft, SizeVT),
4862 Align, DstSV, DstSVOff + Offset);
4865 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
4870 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
4872 SDOperand Dst, SDOperand Src,
4873 SDOperand Size, unsigned Align,
4875 const Value *DstSV, uint64_t DstSVOff,
4876 const Value *SrcSV, uint64_t SrcSVOff){
4878 // This requires the copy size to be a constant, preferrably
4879 // within a subtarget-specific limit.
4880 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
4883 uint64_t SizeVal = ConstantSize->getValue();
4884 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
4888 unsigned BytesLeft = 0;
4889 if (Align >= 8 && Subtarget->is64Bit())
4891 else if (Align >= 4)
4893 else if (Align >= 2)
4898 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4899 unsigned CountVal = SizeVal / UBytes;
4900 SDOperand Count = DAG.getIntPtrConstant(CountVal);
4901 BytesLeft = SizeVal % UBytes;
4903 SDOperand InFlag(0, 0);
4904 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4906 InFlag = Chain.getValue(1);
4907 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4909 InFlag = Chain.getValue(1);
4910 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
4912 InFlag = Chain.getValue(1);
4914 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4915 SmallVector<SDOperand, 8> Ops;
4916 Ops.push_back(Chain);
4917 Ops.push_back(DAG.getValueType(AVT));
4918 Ops.push_back(InFlag);
4919 SDOperand RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
4921 SmallVector<SDOperand, 4> Results;
4922 Results.push_back(RepMovs);
4924 // Handle the last 1 - 7 bytes.
4925 unsigned Offset = SizeVal - BytesLeft;
4926 MVT::ValueType DstVT = Dst.getValueType();
4927 MVT::ValueType SrcVT = Src.getValueType();
4928 MVT::ValueType SizeVT = Size.getValueType();
4929 Results.push_back(DAG.getMemcpy(Chain,
4930 DAG.getNode(ISD::ADD, DstVT, Dst,
4931 DAG.getConstant(Offset, DstVT)),
4932 DAG.getNode(ISD::ADD, SrcVT, Src,
4933 DAG.getConstant(Offset, SrcVT)),
4934 DAG.getConstant(BytesLeft, SizeVT),
4935 Align, AlwaysInline,
4936 DstSV, DstSVOff + Offset,
4937 SrcSV, SrcSVOff + Offset));
4940 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size());
4943 /// Expand the result of: i64,outchain = READCYCLECOUNTER inchain
4944 SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){
4945 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4946 SDOperand TheChain = N->getOperand(0);
4947 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
4948 if (Subtarget->is64Bit()) {
4949 SDOperand rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
4950 SDOperand rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX,
4951 MVT::i64, rax.getValue(2));
4952 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
4953 DAG.getConstant(32, MVT::i8));
4955 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
4958 Tys = DAG.getVTList(MVT::i64, MVT::Other);
4959 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val;
4962 SDOperand eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
4963 SDOperand edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX,
4964 MVT::i32, eax.getValue(2));
4965 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
4966 SDOperand Ops[] = { eax, edx };
4967 Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2);
4969 // Use a MERGE_VALUES to return the value and chain.
4970 Ops[1] = edx.getValue(1);
4971 Tys = DAG.getVTList(MVT::i64, MVT::Other);
4972 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val;
4975 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
4976 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4978 if (!Subtarget->is64Bit()) {
4979 // vastart just stores the address of the VarArgsFrameIndex slot into the
4980 // memory location argument.
4981 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4982 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0);
4986 // gp_offset (0 - 6 * 8)
4987 // fp_offset (48 - 48 + 8 * 16)
4988 // overflow_arg_area (point to parameters coming in memory).
4990 SmallVector<SDOperand, 8> MemOps;
4991 SDOperand FIN = Op.getOperand(1);
4993 SDOperand Store = DAG.getStore(Op.getOperand(0),
4994 DAG.getConstant(VarArgsGPOffset, MVT::i32),
4996 MemOps.push_back(Store);
4999 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5000 Store = DAG.getStore(Op.getOperand(0),
5001 DAG.getConstant(VarArgsFPOffset, MVT::i32),
5003 MemOps.push_back(Store);
5005 // Store ptr to overflow_arg_area
5006 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5007 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5008 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0);
5009 MemOps.push_back(Store);
5011 // Store ptr to reg_save_area.
5012 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
5013 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
5014 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0);
5015 MemOps.push_back(Store);
5016 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
5019 SDOperand X86TargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG) {
5020 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5021 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
5022 SDOperand Chain = Op.getOperand(0);
5023 SDOperand SrcPtr = Op.getOperand(1);
5024 SDOperand SrcSV = Op.getOperand(2);
5026 assert(0 && "VAArgInst is not yet implemented for x86-64!");
5031 SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
5032 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5033 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
5034 SDOperand Chain = Op.getOperand(0);
5035 SDOperand DstPtr = Op.getOperand(1);
5036 SDOperand SrcPtr = Op.getOperand(2);
5037 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
5038 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5040 return DAG.getMemcpy(Chain, DstPtr, SrcPtr,
5041 DAG.getIntPtrConstant(24), 8, false,
5042 DstSV, 0, SrcSV, 0);
5046 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
5047 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
5049 default: return SDOperand(); // Don't custom lower most intrinsics.
5050 // Comparison intrinsics.
5051 case Intrinsic::x86_sse_comieq_ss:
5052 case Intrinsic::x86_sse_comilt_ss:
5053 case Intrinsic::x86_sse_comile_ss:
5054 case Intrinsic::x86_sse_comigt_ss:
5055 case Intrinsic::x86_sse_comige_ss:
5056 case Intrinsic::x86_sse_comineq_ss:
5057 case Intrinsic::x86_sse_ucomieq_ss:
5058 case Intrinsic::x86_sse_ucomilt_ss:
5059 case Intrinsic::x86_sse_ucomile_ss:
5060 case Intrinsic::x86_sse_ucomigt_ss:
5061 case Intrinsic::x86_sse_ucomige_ss:
5062 case Intrinsic::x86_sse_ucomineq_ss:
5063 case Intrinsic::x86_sse2_comieq_sd:
5064 case Intrinsic::x86_sse2_comilt_sd:
5065 case Intrinsic::x86_sse2_comile_sd:
5066 case Intrinsic::x86_sse2_comigt_sd:
5067 case Intrinsic::x86_sse2_comige_sd:
5068 case Intrinsic::x86_sse2_comineq_sd:
5069 case Intrinsic::x86_sse2_ucomieq_sd:
5070 case Intrinsic::x86_sse2_ucomilt_sd:
5071 case Intrinsic::x86_sse2_ucomile_sd:
5072 case Intrinsic::x86_sse2_ucomigt_sd:
5073 case Intrinsic::x86_sse2_ucomige_sd:
5074 case Intrinsic::x86_sse2_ucomineq_sd: {
5076 ISD::CondCode CC = ISD::SETCC_INVALID;
5079 case Intrinsic::x86_sse_comieq_ss:
5080 case Intrinsic::x86_sse2_comieq_sd:
5084 case Intrinsic::x86_sse_comilt_ss:
5085 case Intrinsic::x86_sse2_comilt_sd:
5089 case Intrinsic::x86_sse_comile_ss:
5090 case Intrinsic::x86_sse2_comile_sd:
5094 case Intrinsic::x86_sse_comigt_ss:
5095 case Intrinsic::x86_sse2_comigt_sd:
5099 case Intrinsic::x86_sse_comige_ss:
5100 case Intrinsic::x86_sse2_comige_sd:
5104 case Intrinsic::x86_sse_comineq_ss:
5105 case Intrinsic::x86_sse2_comineq_sd:
5109 case Intrinsic::x86_sse_ucomieq_ss:
5110 case Intrinsic::x86_sse2_ucomieq_sd:
5111 Opc = X86ISD::UCOMI;
5114 case Intrinsic::x86_sse_ucomilt_ss:
5115 case Intrinsic::x86_sse2_ucomilt_sd:
5116 Opc = X86ISD::UCOMI;
5119 case Intrinsic::x86_sse_ucomile_ss:
5120 case Intrinsic::x86_sse2_ucomile_sd:
5121 Opc = X86ISD::UCOMI;
5124 case Intrinsic::x86_sse_ucomigt_ss:
5125 case Intrinsic::x86_sse2_ucomigt_sd:
5126 Opc = X86ISD::UCOMI;
5129 case Intrinsic::x86_sse_ucomige_ss:
5130 case Intrinsic::x86_sse2_ucomige_sd:
5131 Opc = X86ISD::UCOMI;
5134 case Intrinsic::x86_sse_ucomineq_ss:
5135 case Intrinsic::x86_sse2_ucomineq_sd:
5136 Opc = X86ISD::UCOMI;
5142 SDOperand LHS = Op.getOperand(1);
5143 SDOperand RHS = Op.getOperand(2);
5144 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
5146 SDOperand Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
5147 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
5148 DAG.getConstant(X86CC, MVT::i8), Cond);
5149 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
5152 // Fix vector shift instructions where the last operand is a non-immediate
5154 case Intrinsic::x86_sse2_pslli_w:
5155 case Intrinsic::x86_sse2_pslli_d:
5156 case Intrinsic::x86_sse2_pslli_q:
5157 case Intrinsic::x86_sse2_psrli_w:
5158 case Intrinsic::x86_sse2_psrli_d:
5159 case Intrinsic::x86_sse2_psrli_q:
5160 case Intrinsic::x86_sse2_psrai_w:
5161 case Intrinsic::x86_sse2_psrai_d:
5162 case Intrinsic::x86_mmx_pslli_w:
5163 case Intrinsic::x86_mmx_pslli_d:
5164 case Intrinsic::x86_mmx_pslli_q:
5165 case Intrinsic::x86_mmx_psrli_w:
5166 case Intrinsic::x86_mmx_psrli_d:
5167 case Intrinsic::x86_mmx_psrli_q:
5168 case Intrinsic::x86_mmx_psrai_w:
5169 case Intrinsic::x86_mmx_psrai_d: {
5170 SDOperand ShAmt = Op.getOperand(2);
5171 if (isa<ConstantSDNode>(ShAmt))
5174 unsigned NewIntNo = 0;
5175 MVT::ValueType ShAmtVT = MVT::v4i32;
5177 case Intrinsic::x86_sse2_pslli_w:
5178 NewIntNo = Intrinsic::x86_sse2_psll_w;
5180 case Intrinsic::x86_sse2_pslli_d:
5181 NewIntNo = Intrinsic::x86_sse2_psll_d;
5183 case Intrinsic::x86_sse2_pslli_q:
5184 NewIntNo = Intrinsic::x86_sse2_psll_q;
5186 case Intrinsic::x86_sse2_psrli_w:
5187 NewIntNo = Intrinsic::x86_sse2_psrl_w;
5189 case Intrinsic::x86_sse2_psrli_d:
5190 NewIntNo = Intrinsic::x86_sse2_psrl_d;
5192 case Intrinsic::x86_sse2_psrli_q:
5193 NewIntNo = Intrinsic::x86_sse2_psrl_q;
5195 case Intrinsic::x86_sse2_psrai_w:
5196 NewIntNo = Intrinsic::x86_sse2_psra_w;
5198 case Intrinsic::x86_sse2_psrai_d:
5199 NewIntNo = Intrinsic::x86_sse2_psra_d;
5202 ShAmtVT = MVT::v2i32;
5204 case Intrinsic::x86_mmx_pslli_w:
5205 NewIntNo = Intrinsic::x86_mmx_psll_w;
5207 case Intrinsic::x86_mmx_pslli_d:
5208 NewIntNo = Intrinsic::x86_mmx_psll_d;
5210 case Intrinsic::x86_mmx_pslli_q:
5211 NewIntNo = Intrinsic::x86_mmx_psll_q;
5213 case Intrinsic::x86_mmx_psrli_w:
5214 NewIntNo = Intrinsic::x86_mmx_psrl_w;
5216 case Intrinsic::x86_mmx_psrli_d:
5217 NewIntNo = Intrinsic::x86_mmx_psrl_d;
5219 case Intrinsic::x86_mmx_psrli_q:
5220 NewIntNo = Intrinsic::x86_mmx_psrl_q;
5222 case Intrinsic::x86_mmx_psrai_w:
5223 NewIntNo = Intrinsic::x86_mmx_psra_w;
5225 case Intrinsic::x86_mmx_psrai_d:
5226 NewIntNo = Intrinsic::x86_mmx_psra_d;
5228 default: abort(); // Can't reach here.
5233 MVT::ValueType VT = Op.getValueType();
5234 ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT,
5235 DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt));
5236 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
5237 DAG.getConstant(NewIntNo, MVT::i32),
5238 Op.getOperand(1), ShAmt);
5243 SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
5244 // Depths > 0 not supported yet!
5245 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
5248 // Just load the return address
5249 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
5250 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
5253 SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
5254 // Depths > 0 not supported yet!
5255 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
5258 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
5259 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
5260 DAG.getIntPtrConstant(4));
5263 SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op,
5264 SelectionDAG &DAG) {
5265 // Is not yet supported on x86-64
5266 if (Subtarget->is64Bit())
5269 return DAG.getIntPtrConstant(8);
5272 SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
5274 assert(!Subtarget->is64Bit() &&
5275 "Lowering of eh_return builtin is not supported yet on x86-64");
5277 MachineFunction &MF = DAG.getMachineFunction();
5278 SDOperand Chain = Op.getOperand(0);
5279 SDOperand Offset = Op.getOperand(1);
5280 SDOperand Handler = Op.getOperand(2);
5282 SDOperand Frame = DAG.getRegister(RegInfo->getFrameRegister(MF),
5285 SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
5286 DAG.getIntPtrConstant(-4UL));
5287 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
5288 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
5289 Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);
5290 MF.getRegInfo().addLiveOut(X86::ECX);
5292 return DAG.getNode(X86ISD::EH_RETURN, MVT::Other,
5293 Chain, DAG.getRegister(X86::ECX, getPointerTy()));
5296 SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
5297 SelectionDAG &DAG) {
5298 SDOperand Root = Op.getOperand(0);
5299 SDOperand Trmp = Op.getOperand(1); // trampoline
5300 SDOperand FPtr = Op.getOperand(2); // nested function
5301 SDOperand Nest = Op.getOperand(3); // 'nest' parameter value
5303 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5305 const X86InstrInfo *TII =
5306 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
5308 if (Subtarget->is64Bit()) {
5309 SDOperand OutChains[6];
5311 // Large code-model.
5313 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
5314 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
5316 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
5317 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
5319 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
5321 // Load the pointer to the nested function into R11.
5322 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
5323 SDOperand Addr = Trmp;
5324 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5327 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
5328 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2);
5330 // Load the 'nest' parameter value into R10.
5331 // R10 is specified in X86CallingConv.td
5332 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
5333 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
5334 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5337 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
5338 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2);
5340 // Jump to the nested function.
5341 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
5342 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
5343 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5346 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
5347 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
5348 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
5352 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
5353 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2);
5355 const Function *Func =
5356 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
5357 unsigned CC = Func->getCallingConv();
5362 assert(0 && "Unsupported calling convention");
5363 case CallingConv::C:
5364 case CallingConv::X86_StdCall: {
5365 // Pass 'nest' parameter in ECX.
5366 // Must be kept in sync with X86CallingConv.td
5369 // Check that ECX wasn't needed by an 'inreg' parameter.
5370 const FunctionType *FTy = Func->getFunctionType();
5371 const PAListPtr &Attrs = Func->getParamAttrs();
5373 if (!Attrs.isEmpty() && !Func->isVarArg()) {
5374 unsigned InRegCount = 0;
5377 for (FunctionType::param_iterator I = FTy->param_begin(),
5378 E = FTy->param_end(); I != E; ++I, ++Idx)
5379 if (Attrs.paramHasAttr(Idx, ParamAttr::InReg))
5380 // FIXME: should only count parameters that are lowered to integers.
5381 InRegCount += (getTargetData()->getTypeSizeInBits(*I) + 31) / 32;
5383 if (InRegCount > 2) {
5384 cerr << "Nest register in use - reduce number of inreg parameters!\n";
5390 case CallingConv::X86_FastCall:
5391 // Pass 'nest' parameter in EAX.
5392 // Must be kept in sync with X86CallingConv.td
5397 SDOperand OutChains[4];
5398 SDOperand Addr, Disp;
5400 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
5401 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
5403 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
5404 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
5405 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
5408 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
5409 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1);
5411 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
5412 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
5413 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
5414 TrmpAddr, 5, false, 1);
5416 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
5417 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1);
5420 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
5421 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2);
5425 SDOperand X86TargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
5427 The rounding mode is in bits 11:10 of FPSR, and has the following
5434 FLT_ROUNDS, on the other hand, expects the following:
5441 To perform the conversion, we do:
5442 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
5445 MachineFunction &MF = DAG.getMachineFunction();
5446 const TargetMachine &TM = MF.getTarget();
5447 const TargetFrameInfo &TFI = *TM.getFrameInfo();
5448 unsigned StackAlignment = TFI.getStackAlignment();
5449 MVT::ValueType VT = Op.getValueType();
5451 // Save FP Control Word to stack slot
5452 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
5453 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5455 SDOperand Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
5456 DAG.getEntryNode(), StackSlot);
5458 // Load FP Control Word from stack slot
5459 SDOperand CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
5461 // Transform as necessary
5463 DAG.getNode(ISD::SRL, MVT::i16,
5464 DAG.getNode(ISD::AND, MVT::i16,
5465 CWD, DAG.getConstant(0x800, MVT::i16)),
5466 DAG.getConstant(11, MVT::i8));
5468 DAG.getNode(ISD::SRL, MVT::i16,
5469 DAG.getNode(ISD::AND, MVT::i16,
5470 CWD, DAG.getConstant(0x400, MVT::i16)),
5471 DAG.getConstant(9, MVT::i8));
5474 DAG.getNode(ISD::AND, MVT::i16,
5475 DAG.getNode(ISD::ADD, MVT::i16,
5476 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
5477 DAG.getConstant(1, MVT::i16)),
5478 DAG.getConstant(3, MVT::i16));
5481 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ?
5482 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
5485 SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) {
5486 MVT::ValueType VT = Op.getValueType();
5487 MVT::ValueType OpVT = VT;
5488 unsigned NumBits = MVT::getSizeInBits(VT);
5490 Op = Op.getOperand(0);
5491 if (VT == MVT::i8) {
5492 // Zero extend to i32 since there is not an i8 bsr.
5494 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5497 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
5498 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5499 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
5501 // If src is zero (i.e. bsr sets ZF), returns NumBits.
5502 SmallVector<SDOperand, 4> Ops;
5504 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
5505 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5506 Ops.push_back(Op.getValue(1));
5507 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5509 // Finally xor with NumBits-1.
5510 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
5513 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5517 SDOperand X86TargetLowering::LowerCTTZ(SDOperand Op, SelectionDAG &DAG) {
5518 MVT::ValueType VT = Op.getValueType();
5519 MVT::ValueType OpVT = VT;
5520 unsigned NumBits = MVT::getSizeInBits(VT);
5522 Op = Op.getOperand(0);
5523 if (VT == MVT::i8) {
5525 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5528 // Issue a bsf (scan bits forward) which also sets EFLAGS.
5529 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5530 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
5532 // If src is zero (i.e. bsf sets ZF), returns NumBits.
5533 SmallVector<SDOperand, 4> Ops;
5535 Ops.push_back(DAG.getConstant(NumBits, OpVT));
5536 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5537 Ops.push_back(Op.getValue(1));
5538 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5541 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5545 SDOperand X86TargetLowering::LowerLCS(SDOperand Op, SelectionDAG &DAG) {
5546 MVT::ValueType T = cast<AtomicSDNode>(Op.Val)->getVT();
5550 case MVT::i8: Reg = X86::AL; size = 1; break;
5551 case MVT::i16: Reg = X86::AX; size = 2; break;
5552 case MVT::i32: Reg = X86::EAX; size = 4; break;
5554 if (Subtarget->is64Bit()) {
5555 Reg = X86::RAX; size = 8;
5556 } else //Should go away when LowerType stuff lands
5557 return SDOperand(ExpandATOMIC_LCS(Op.Val, DAG), 0);
5560 SDOperand cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
5561 Op.getOperand(3), SDOperand());
5562 SDOperand Ops[] = { cpIn.getValue(0),
5565 DAG.getTargetConstant(size, MVT::i8),
5567 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5568 SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
5570 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
5574 SDNode* X86TargetLowering::ExpandATOMIC_LCS(SDNode* Op, SelectionDAG &DAG) {
5575 MVT::ValueType T = cast<AtomicSDNode>(Op)->getVT();
5576 assert (T == MVT::i64 && "Only know how to expand i64 CAS");
5577 SDOperand cpInL, cpInH;
5578 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
5579 DAG.getConstant(0, MVT::i32));
5580 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
5581 DAG.getConstant(1, MVT::i32));
5582 cpInL = DAG.getCopyToReg(Op->getOperand(0), X86::EAX,
5583 cpInL, SDOperand());
5584 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX,
5585 cpInH, cpInL.getValue(1));
5586 SDOperand swapInL, swapInH;
5587 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
5588 DAG.getConstant(0, MVT::i32));
5589 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
5590 DAG.getConstant(1, MVT::i32));
5591 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX,
5592 swapInL, cpInH.getValue(1));
5593 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX,
5594 swapInH, swapInL.getValue(1));
5595 SDOperand Ops[] = { swapInH.getValue(0),
5597 swapInH.getValue(1)};
5598 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5599 SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3);
5600 SDOperand cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
5601 Result.getValue(1));
5602 SDOperand cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
5603 cpOutL.getValue(2));
5604 SDOperand OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
5605 SDOperand ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
5606 Tys = DAG.getVTList(MVT::i64, MVT::Other);
5607 return DAG.getNode(ISD::MERGE_VALUES, Tys, ResultVal, cpOutH.getValue(1)).Val;
5610 SDNode* X86TargetLowering::ExpandATOMIC_LSS(SDNode* Op, SelectionDAG &DAG) {
5611 MVT::ValueType T = cast<AtomicSDNode>(Op)->getVT();
5612 assert (T == MVT::i32 && "Only know how to expand i32 LSS");
5613 SDOperand negOp = DAG.getNode(ISD::SUB, T,
5614 DAG.getConstant(0, T), Op->getOperand(2));
5615 return DAG.getAtomic(ISD::ATOMIC_LAS, Op->getOperand(0),
5616 Op->getOperand(1), negOp, T).Val;
5619 /// LowerOperation - Provide custom lowering hooks for some operations.
5621 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
5622 switch (Op.getOpcode()) {
5623 default: assert(0 && "Should not custom lower this!");
5624 case ISD::ATOMIC_LCS: return LowerLCS(Op,DAG);
5625 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5626 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5627 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
5628 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
5629 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5630 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5631 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5632 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5633 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
5634 case ISD::SHL_PARTS:
5635 case ISD::SRA_PARTS:
5636 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
5637 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
5638 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
5639 case ISD::FABS: return LowerFABS(Op, DAG);
5640 case ISD::FNEG: return LowerFNEG(Op, DAG);
5641 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
5642 case ISD::SETCC: return LowerSETCC(Op, DAG);
5643 case ISD::SELECT: return LowerSELECT(Op, DAG);
5644 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
5645 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5646 case ISD::CALL: return LowerCALL(Op, DAG);
5647 case ISD::RET: return LowerRET(Op, DAG);
5648 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
5649 case ISD::VASTART: return LowerVASTART(Op, DAG);
5650 case ISD::VAARG: return LowerVAARG(Op, DAG);
5651 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
5652 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5653 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5654 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5655 case ISD::FRAME_TO_ARGS_OFFSET:
5656 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
5657 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
5658 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
5659 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
5660 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5661 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
5662 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
5664 // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
5665 case ISD::READCYCLECOUNTER:
5666 return SDOperand(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0);
5670 /// ExpandOperation - Provide custom lowering hooks for expanding operations.
5671 SDNode *X86TargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
5672 switch (N->getOpcode()) {
5673 default: assert(0 && "Should not custom lower this!");
5674 case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG);
5675 case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG);
5676 case ISD::ATOMIC_LCS: return ExpandATOMIC_LCS(N, DAG);
5677 case ISD::ATOMIC_LSS: return ExpandATOMIC_LSS(N,DAG);
5681 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
5683 default: return NULL;
5684 case X86ISD::BSF: return "X86ISD::BSF";
5685 case X86ISD::BSR: return "X86ISD::BSR";
5686 case X86ISD::SHLD: return "X86ISD::SHLD";
5687 case X86ISD::SHRD: return "X86ISD::SHRD";
5688 case X86ISD::FAND: return "X86ISD::FAND";
5689 case X86ISD::FOR: return "X86ISD::FOR";
5690 case X86ISD::FXOR: return "X86ISD::FXOR";
5691 case X86ISD::FSRL: return "X86ISD::FSRL";
5692 case X86ISD::FILD: return "X86ISD::FILD";
5693 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
5694 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
5695 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
5696 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
5697 case X86ISD::FLD: return "X86ISD::FLD";
5698 case X86ISD::FST: return "X86ISD::FST";
5699 case X86ISD::CALL: return "X86ISD::CALL";
5700 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
5701 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
5702 case X86ISD::CMP: return "X86ISD::CMP";
5703 case X86ISD::COMI: return "X86ISD::COMI";
5704 case X86ISD::UCOMI: return "X86ISD::UCOMI";
5705 case X86ISD::SETCC: return "X86ISD::SETCC";
5706 case X86ISD::CMOV: return "X86ISD::CMOV";
5707 case X86ISD::BRCOND: return "X86ISD::BRCOND";
5708 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
5709 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
5710 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
5711 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
5712 case X86ISD::Wrapper: return "X86ISD::Wrapper";
5713 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
5714 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
5715 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
5716 case X86ISD::PINSRB: return "X86ISD::PINSRB";
5717 case X86ISD::PINSRW: return "X86ISD::PINSRW";
5718 case X86ISD::FMAX: return "X86ISD::FMAX";
5719 case X86ISD::FMIN: return "X86ISD::FMIN";
5720 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
5721 case X86ISD::FRCP: return "X86ISD::FRCP";
5722 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
5723 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
5724 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
5725 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
5726 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
5727 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
5728 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
5729 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
5730 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
5734 // isLegalAddressingMode - Return true if the addressing mode represented
5735 // by AM is legal for this target, for a load/store of the specified type.
5736 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
5737 const Type *Ty) const {
5738 // X86 supports extremely general addressing modes.
5740 // X86 allows a sign-extended 32-bit immediate field as a displacement.
5741 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
5745 // We can only fold this if we don't need an extra load.
5746 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
5749 // X86-64 only supports addr of globals in small code model.
5750 if (Subtarget->is64Bit()) {
5751 if (getTargetMachine().getCodeModel() != CodeModel::Small)
5753 // If lower 4G is not available, then we must use rip-relative addressing.
5754 if (AM.BaseOffs || AM.Scale > 1)
5765 // These scales always work.
5770 // These scales are formed with basereg+scalereg. Only accept if there is
5775 default: // Other stuff never works.
5783 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
5784 if (!Ty1->isInteger() || !Ty2->isInteger())
5786 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
5787 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
5788 if (NumBits1 <= NumBits2)
5790 return Subtarget->is64Bit() || NumBits1 < 64;
5793 bool X86TargetLowering::isTruncateFree(MVT::ValueType VT1,
5794 MVT::ValueType VT2) const {
5795 if (!MVT::isInteger(VT1) || !MVT::isInteger(VT2))
5797 unsigned NumBits1 = MVT::getSizeInBits(VT1);
5798 unsigned NumBits2 = MVT::getSizeInBits(VT2);
5799 if (NumBits1 <= NumBits2)
5801 return Subtarget->is64Bit() || NumBits1 < 64;
5804 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5805 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5806 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5807 /// are assumed to be legal.
5809 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
5810 // Only do shuffles on 128-bit vector types for now.
5811 if (MVT::getSizeInBits(VT) == 64) return false;
5812 return (Mask.Val->getNumOperands() <= 4 ||
5813 isIdentityMask(Mask.Val) ||
5814 isIdentityMask(Mask.Val, true) ||
5815 isSplatMask(Mask.Val) ||
5816 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
5817 X86::isUNPCKLMask(Mask.Val) ||
5818 X86::isUNPCKHMask(Mask.Val) ||
5819 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
5820 X86::isUNPCKH_v_undef_Mask(Mask.Val));
5824 X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDOperand> &BVOps,
5826 SelectionDAG &DAG) const {
5827 unsigned NumElts = BVOps.size();
5828 // Only do shuffles on 128-bit vector types for now.
5829 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
5830 if (NumElts == 2) return true;
5832 return (isMOVLMask(&BVOps[0], 4) ||
5833 isCommutedMOVL(&BVOps[0], 4, true) ||
5834 isSHUFPMask(&BVOps[0], 4) ||
5835 isCommutedSHUFP(&BVOps[0], 4));
5840 //===----------------------------------------------------------------------===//
5841 // X86 Scheduler Hooks
5842 //===----------------------------------------------------------------------===//
5844 // private utility function
5846 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
5847 MachineBasicBlock *MBB,
5850 // For the atomic bitwise operator, we generate
5853 // ld t1 = [bitinstr.addr]
5854 // op t2 = t1, [bitinstr.val]
5856 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
5858 // fallthrough -->nextMBB
5859 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5860 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
5861 ilist<MachineBasicBlock>::iterator MBBIter = MBB;
5864 /// First build the CFG
5865 MachineFunction *F = MBB->getParent();
5866 MachineBasicBlock *thisMBB = MBB;
5867 MachineBasicBlock *newMBB = new MachineBasicBlock(LLVM_BB);
5868 MachineBasicBlock *nextMBB = new MachineBasicBlock(LLVM_BB);
5869 F->getBasicBlockList().insert(MBBIter, newMBB);
5870 F->getBasicBlockList().insert(MBBIter, nextMBB);
5872 // Move all successors to thisMBB to nextMBB
5873 nextMBB->transferSuccessors(thisMBB);
5875 // Update thisMBB to fall through to newMBB
5876 thisMBB->addSuccessor(newMBB);
5878 // newMBB jumps to itself and fall through to nextMBB
5879 newMBB->addSuccessor(nextMBB);
5880 newMBB->addSuccessor(newMBB);
5882 // Insert instructions into newMBB based on incoming instruction
5883 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands");
5884 MachineOperand& destOper = bInstr->getOperand(0);
5885 MachineOperand* argOpers[6];
5886 int numArgs = bInstr->getNumOperands() - 1;
5887 for (int i=0; i < numArgs; ++i)
5888 argOpers[i] = &bInstr->getOperand(i+1);
5890 // x86 address has 4 operands: base, index, scale, and displacement
5891 int lastAddrIndx = 3; // [0,3]
5894 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
5895 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
5896 for (int i=0; i <= lastAddrIndx; ++i)
5897 (*MIB).addOperand(*argOpers[i]);
5899 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
5900 assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm())
5901 && "invalid operand");
5902 if (argOpers[valArgIndx]->isReg())
5903 MIB = BuildMI(newMBB, TII->get(regOpc), t2);
5905 MIB = BuildMI(newMBB, TII->get(immOpc), t2);
5907 (*MIB).addOperand(*argOpers[valArgIndx]);
5909 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
5912 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32));
5913 for (int i=0; i <= lastAddrIndx; ++i)
5914 (*MIB).addOperand(*argOpers[i]);
5917 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
5918 MIB.addReg(X86::EAX);
5921 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
5923 delete bInstr; // The pseudo instruction is gone now.
5927 // private utility function
5929 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
5930 MachineBasicBlock *MBB,
5932 // For the atomic min/max operator, we generate
5935 // ld t1 = [min/max.addr]
5936 // mov t2 = [min/max.val]
5938 // cmov[cond] t2 = t1
5940 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
5942 // fallthrough -->nextMBB
5944 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5945 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
5946 ilist<MachineBasicBlock>::iterator MBBIter = MBB;
5949 /// First build the CFG
5950 MachineFunction *F = MBB->getParent();
5951 MachineBasicBlock *thisMBB = MBB;
5952 MachineBasicBlock *newMBB = new MachineBasicBlock(LLVM_BB);
5953 MachineBasicBlock *nextMBB = new MachineBasicBlock(LLVM_BB);
5954 F->getBasicBlockList().insert(MBBIter, newMBB);
5955 F->getBasicBlockList().insert(MBBIter, nextMBB);
5957 // Move all successors to thisMBB to nextMBB
5958 nextMBB->transferSuccessors(thisMBB);
5960 // Update thisMBB to fall through to newMBB
5961 thisMBB->addSuccessor(newMBB);
5963 // newMBB jumps to newMBB and fall through to nextMBB
5964 newMBB->addSuccessor(nextMBB);
5965 newMBB->addSuccessor(newMBB);
5967 // Insert instructions into newMBB based on incoming instruction
5968 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands");
5969 MachineOperand& destOper = mInstr->getOperand(0);
5970 MachineOperand* argOpers[6];
5971 int numArgs = mInstr->getNumOperands() - 1;
5972 for (int i=0; i < numArgs; ++i)
5973 argOpers[i] = &mInstr->getOperand(i+1);
5975 // x86 address has 4 operands: base, index, scale, and displacement
5976 int lastAddrIndx = 3; // [0,3]
5979 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
5980 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
5981 for (int i=0; i <= lastAddrIndx; ++i)
5982 (*MIB).addOperand(*argOpers[i]);
5984 // We only support register and immediate values
5985 assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm())
5986 && "invalid operand");
5988 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
5989 if (argOpers[valArgIndx]->isReg())
5990 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
5992 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
5993 (*MIB).addOperand(*argOpers[valArgIndx]);
5995 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
5998 MIB = BuildMI(newMBB, TII->get(X86::CMP32rr));
6003 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6004 MIB = BuildMI(newMBB, TII->get(cmovOpc),t3);
6008 // Cmp and exchange if none has modified the memory location
6009 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32));
6010 for (int i=0; i <= lastAddrIndx; ++i)
6011 (*MIB).addOperand(*argOpers[i]);
6014 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
6015 MIB.addReg(X86::EAX);
6018 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6020 delete mInstr; // The pseudo instruction is gone now.
6026 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6027 MachineBasicBlock *BB) {
6028 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6029 switch (MI->getOpcode()) {
6030 default: assert(false && "Unexpected instr type to insert");
6031 case X86::CMOV_FR32:
6032 case X86::CMOV_FR64:
6033 case X86::CMOV_V4F32:
6034 case X86::CMOV_V2F64:
6035 case X86::CMOV_V2I64: {
6036 // To "insert" a SELECT_CC instruction, we actually have to insert the
6037 // diamond control-flow pattern. The incoming instruction knows the
6038 // destination vreg to set, the condition code register to branch on, the
6039 // true/false values to select between, and a branch opcode to use.
6040 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6041 ilist<MachineBasicBlock>::iterator It = BB;
6047 // cmpTY ccX, r1, r2
6049 // fallthrough --> copy0MBB
6050 MachineBasicBlock *thisMBB = BB;
6051 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
6052 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
6054 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
6055 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
6056 MachineFunction *F = BB->getParent();
6057 F->getBasicBlockList().insert(It, copy0MBB);
6058 F->getBasicBlockList().insert(It, sinkMBB);
6059 // Update machine-CFG edges by transferring all successors of the current
6060 // block to the new block which will contain the Phi node for the select.
6061 sinkMBB->transferSuccessors(BB);
6063 // Add the true and fallthrough blocks as its successors.
6064 BB->addSuccessor(copy0MBB);
6065 BB->addSuccessor(sinkMBB);
6068 // %FalseValue = ...
6069 // # fallthrough to sinkMBB
6072 // Update machine-CFG edges
6073 BB->addSuccessor(sinkMBB);
6076 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6079 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
6080 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
6081 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6083 delete MI; // The pseudo instruction is gone now.
6087 case X86::FP32_TO_INT16_IN_MEM:
6088 case X86::FP32_TO_INT32_IN_MEM:
6089 case X86::FP32_TO_INT64_IN_MEM:
6090 case X86::FP64_TO_INT16_IN_MEM:
6091 case X86::FP64_TO_INT32_IN_MEM:
6092 case X86::FP64_TO_INT64_IN_MEM:
6093 case X86::FP80_TO_INT16_IN_MEM:
6094 case X86::FP80_TO_INT32_IN_MEM:
6095 case X86::FP80_TO_INT64_IN_MEM: {
6096 // Change the floating point control register to use "round towards zero"
6097 // mode when truncating to an integer value.
6098 MachineFunction *F = BB->getParent();
6099 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
6100 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
6102 // Load the old value of the high byte of the control word...
6104 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
6105 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
6107 // Set the high part to be round to zero...
6108 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
6111 // Reload the modified control word now...
6112 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
6114 // Restore the memory image of control word to original value
6115 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
6118 // Get the X86 opcode to use.
6120 switch (MI->getOpcode()) {
6121 default: assert(0 && "illegal opcode!");
6122 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
6123 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
6124 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
6125 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
6126 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
6127 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
6128 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
6129 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
6130 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
6134 MachineOperand &Op = MI->getOperand(0);
6135 if (Op.isRegister()) {
6136 AM.BaseType = X86AddressMode::RegBase;
6137 AM.Base.Reg = Op.getReg();
6139 AM.BaseType = X86AddressMode::FrameIndexBase;
6140 AM.Base.FrameIndex = Op.getIndex();
6142 Op = MI->getOperand(1);
6143 if (Op.isImmediate())
6144 AM.Scale = Op.getImm();
6145 Op = MI->getOperand(2);
6146 if (Op.isImmediate())
6147 AM.IndexReg = Op.getImm();
6148 Op = MI->getOperand(3);
6149 if (Op.isGlobalAddress()) {
6150 AM.GV = Op.getGlobal();
6152 AM.Disp = Op.getImm();
6154 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
6155 .addReg(MI->getOperand(4).getReg());
6157 // Reload the original control word now.
6158 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
6160 delete MI; // The pseudo instruction is gone now.
6163 case X86::ATOMAND32:
6164 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
6167 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
6169 case X86::ATOMXOR32:
6170 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
6172 case X86::ATOMMIN32:
6173 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
6174 case X86::ATOMMAX32:
6175 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
6176 case X86::ATOMUMIN32:
6177 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
6178 case X86::ATOMUMAX32:
6179 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
6183 //===----------------------------------------------------------------------===//
6184 // X86 Optimization Hooks
6185 //===----------------------------------------------------------------------===//
6187 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
6191 const SelectionDAG &DAG,
6192 unsigned Depth) const {
6193 unsigned Opc = Op.getOpcode();
6194 assert((Opc >= ISD::BUILTIN_OP_END ||
6195 Opc == ISD::INTRINSIC_WO_CHAIN ||
6196 Opc == ISD::INTRINSIC_W_CHAIN ||
6197 Opc == ISD::INTRINSIC_VOID) &&
6198 "Should use MaskedValueIsZero if you don't know whether Op"
6199 " is a target node!");
6201 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
6205 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
6206 Mask.getBitWidth() - 1);
6211 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
6212 /// node is a GlobalAddress + offset.
6213 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
6214 GlobalValue* &GA, int64_t &Offset) const{
6215 if (N->getOpcode() == X86ISD::Wrapper) {
6216 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
6217 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
6221 return TargetLowering::isGAPlusOffset(N, GA, Offset);
6224 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
6225 const TargetLowering &TLI) {
6228 if (TLI.isGAPlusOffset(Base, GV, Offset))
6229 return (GV->getAlignment() >= N && (Offset % N) == 0);
6230 // DAG combine handles the stack object case.
6234 static bool EltsFromConsecutiveLoads(SDNode *N, SDOperand PermMask,
6235 unsigned NumElems, MVT::ValueType EVT,
6237 SelectionDAG &DAG, MachineFrameInfo *MFI,
6238 const TargetLowering &TLI) {
6240 for (unsigned i = 0; i < NumElems; ++i) {
6241 SDOperand Idx = PermMask.getOperand(i);
6242 if (Idx.getOpcode() == ISD::UNDEF) {
6248 unsigned Index = cast<ConstantSDNode>(Idx)->getValue();
6249 SDOperand Elt = DAG.getShuffleScalarElt(N, Index);
6251 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.Val)))
6255 if (Base->getOpcode() == ISD::UNDEF)
6259 if (Elt.getOpcode() == ISD::UNDEF)
6262 if (!TLI.isConsecutiveLoad(Elt.Val, Base,
6263 MVT::getSizeInBits(EVT)/8, i, MFI))
6269 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
6270 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
6271 /// if the load addresses are consecutive, non-overlapping, and in the right
6273 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
6274 const TargetLowering &TLI) {
6275 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6276 MVT::ValueType VT = N->getValueType(0);
6277 MVT::ValueType EVT = MVT::getVectorElementType(VT);
6278 SDOperand PermMask = N->getOperand(2);
6279 unsigned NumElems = PermMask.getNumOperands();
6280 SDNode *Base = NULL;
6281 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
6285 LoadSDNode *LD = cast<LoadSDNode>(Base);
6286 if (isBaseAlignmentOfN(16, Base->getOperand(1).Val, TLI))
6287 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
6288 LD->getSrcValueOffset(), LD->isVolatile());
6289 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
6290 LD->getSrcValueOffset(), LD->isVolatile(),
6291 LD->getAlignment());
6294 /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
6295 static SDOperand PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
6296 const X86Subtarget *Subtarget,
6297 const TargetLowering &TLI) {
6298 // Ignore single operand BUILD_VECTOR.
6299 if (N->getNumOperands() == 1)
6302 MVT::ValueType VT = N->getValueType(0);
6303 MVT::ValueType EVT = MVT::getVectorElementType(VT);
6304 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit())
6305 // We are looking for load i64 and zero extend. We want to transform
6306 // it before legalizer has a chance to expand it. Also look for i64
6307 // BUILD_PAIR bit casted to f64.
6309 // This must be an insertion into a zero vector.
6310 SDOperand HighElt = N->getOperand(1);
6311 if (!isZeroNode(HighElt))
6314 // Value must be a load.
6315 SDNode *Base = N->getOperand(0).Val;
6316 if (!isa<LoadSDNode>(Base)) {
6317 if (Base->getOpcode() != ISD::BIT_CONVERT)
6319 Base = Base->getOperand(0).Val;
6320 if (!isa<LoadSDNode>(Base))
6324 // Transform it into VZEXT_LOAD addr.
6325 LoadSDNode *LD = cast<LoadSDNode>(Base);
6326 return DAG.getNode(X86ISD::VZEXT_LOAD, VT, LD->getChain(), LD->getBasePtr());
6329 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
6330 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
6331 const X86Subtarget *Subtarget) {
6332 SDOperand Cond = N->getOperand(0);
6334 // If we have SSE[12] support, try to form min/max nodes.
6335 if (Subtarget->hasSSE2() &&
6336 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
6337 if (Cond.getOpcode() == ISD::SETCC) {
6338 // Get the LHS/RHS of the select.
6339 SDOperand LHS = N->getOperand(1);
6340 SDOperand RHS = N->getOperand(2);
6341 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
6343 unsigned Opcode = 0;
6344 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
6347 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
6350 if (!UnsafeFPMath) break;
6352 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
6354 Opcode = X86ISD::FMIN;
6357 case ISD::SETOGT: // (X > Y) ? X : Y -> max
6360 if (!UnsafeFPMath) break;
6362 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
6364 Opcode = X86ISD::FMAX;
6367 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
6370 case ISD::SETOGT: // (X > Y) ? Y : X -> min
6373 if (!UnsafeFPMath) break;
6375 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
6377 Opcode = X86ISD::FMIN;
6380 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
6383 if (!UnsafeFPMath) break;
6385 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
6387 Opcode = X86ISD::FMAX;
6393 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
6401 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
6402 static SDOperand PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
6403 const X86Subtarget *Subtarget) {
6404 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
6405 // the FP state in cases where an emms may be missing.
6406 // A preferable solution to the general problem is to figure out the right
6407 // places to insert EMMS. This qualifies as a quick hack.
6408 StoreSDNode *St = cast<StoreSDNode>(N);
6409 if (MVT::isVector(St->getValue().getValueType()) &&
6410 MVT::getSizeInBits(St->getValue().getValueType()) == 64 &&
6411 isa<LoadSDNode>(St->getValue()) &&
6412 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
6413 St->getChain().hasOneUse() && !St->isVolatile()) {
6414 SDNode* LdVal = St->getValue().Val;
6416 int TokenFactorIndex = -1;
6417 SmallVector<SDOperand, 8> Ops;
6418 SDNode* ChainVal = St->getChain().Val;
6419 // Must be a store of a load. We currently handle two cases: the load
6420 // is a direct child, and it's under an intervening TokenFactor. It is
6421 // possible to dig deeper under nested TokenFactors.
6422 if (ChainVal == LdVal)
6423 Ld = cast<LoadSDNode>(St->getChain());
6424 else if (St->getValue().hasOneUse() &&
6425 ChainVal->getOpcode() == ISD::TokenFactor) {
6426 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
6427 if (ChainVal->getOperand(i).Val == LdVal) {
6428 TokenFactorIndex = i;
6429 Ld = cast<LoadSDNode>(St->getValue());
6431 Ops.push_back(ChainVal->getOperand(i));
6435 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
6436 if (Subtarget->is64Bit()) {
6437 SDOperand NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
6438 Ld->getBasePtr(), Ld->getSrcValue(),
6439 Ld->getSrcValueOffset(), Ld->isVolatile(),
6440 Ld->getAlignment());
6441 SDOperand NewChain = NewLd.getValue(1);
6442 if (TokenFactorIndex != -1) {
6443 Ops.push_back(NewChain);
6444 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
6447 return DAG.getStore(NewChain, NewLd, St->getBasePtr(),
6448 St->getSrcValue(), St->getSrcValueOffset(),
6449 St->isVolatile(), St->getAlignment());
6452 // Otherwise, lower to two 32-bit copies.
6453 SDOperand LoAddr = Ld->getBasePtr();
6454 SDOperand HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
6455 DAG.getConstant(MVT::i32, 4));
6457 SDOperand LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
6458 Ld->getSrcValue(), Ld->getSrcValueOffset(),
6459 Ld->isVolatile(), Ld->getAlignment());
6460 SDOperand HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
6461 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
6463 MinAlign(Ld->getAlignment(), 4));
6465 SDOperand NewChain = LoLd.getValue(1);
6466 if (TokenFactorIndex != -1) {
6467 Ops.push_back(LoLd);
6468 Ops.push_back(HiLd);
6469 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
6473 LoAddr = St->getBasePtr();
6474 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
6475 DAG.getConstant(MVT::i32, 4));
6477 SDOperand LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
6478 St->getSrcValue(), St->getSrcValueOffset(),
6479 St->isVolatile(), St->getAlignment());
6480 SDOperand HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
6481 St->getSrcValue(), St->getSrcValueOffset()+4,
6483 MinAlign(St->getAlignment(), 4));
6484 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
6490 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
6491 /// X86ISD::FXOR nodes.
6492 static SDOperand PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
6493 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
6494 // F[X]OR(0.0, x) -> x
6495 // F[X]OR(x, 0.0) -> x
6496 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
6497 if (C->getValueAPF().isPosZero())
6498 return N->getOperand(1);
6499 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
6500 if (C->getValueAPF().isPosZero())
6501 return N->getOperand(0);
6505 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
6506 static SDOperand PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
6507 // FAND(0.0, x) -> 0.0
6508 // FAND(x, 0.0) -> 0.0
6509 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
6510 if (C->getValueAPF().isPosZero())
6511 return N->getOperand(0);
6512 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
6513 if (C->getValueAPF().isPosZero())
6514 return N->getOperand(1);
6519 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
6520 DAGCombinerInfo &DCI) const {
6521 SelectionDAG &DAG = DCI.DAG;
6522 switch (N->getOpcode()) {
6524 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
6525 case ISD::BUILD_VECTOR:
6526 return PerformBuildVectorCombine(N, DAG, Subtarget, *this);
6527 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
6528 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
6530 case X86ISD::FOR: return PerformFORCombine(N, DAG);
6531 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
6537 //===----------------------------------------------------------------------===//
6538 // X86 Inline Assembly Support
6539 //===----------------------------------------------------------------------===//
6541 /// getConstraintType - Given a constraint letter, return the type of
6542 /// constraint it is for this target.
6543 X86TargetLowering::ConstraintType
6544 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
6545 if (Constraint.size() == 1) {
6546 switch (Constraint[0]) {
6557 return C_RegisterClass;
6562 return TargetLowering::getConstraintType(Constraint);
6565 /// LowerXConstraint - try to replace an X constraint, which matches anything,
6566 /// with another that has more specific requirements based on the type of the
6567 /// corresponding operand.
6568 const char *X86TargetLowering::
6569 LowerXConstraint(MVT::ValueType ConstraintVT) const {
6570 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
6571 // 'f' like normal targets.
6572 if (MVT::isFloatingPoint(ConstraintVT)) {
6573 if (Subtarget->hasSSE2())
6575 if (Subtarget->hasSSE1())
6579 return TargetLowering::LowerXConstraint(ConstraintVT);
6582 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
6583 /// vector. If it is invalid, don't add anything to Ops.
6584 void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
6586 std::vector<SDOperand>&Ops,
6587 SelectionDAG &DAG) const {
6588 SDOperand Result(0, 0);
6590 switch (Constraint) {
6593 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
6594 if (C->getValue() <= 31) {
6595 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
6601 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
6602 if (C->getValue() <= 255) {
6603 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
6609 // Literal immediates are always ok.
6610 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
6611 Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType());
6615 // If we are in non-pic codegen mode, we allow the address of a global (with
6616 // an optional displacement) to be used with 'i'.
6617 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
6620 // Match either (GA) or (GA+C)
6622 Offset = GA->getOffset();
6623 } else if (Op.getOpcode() == ISD::ADD) {
6624 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6625 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
6627 Offset = GA->getOffset()+C->getValue();
6629 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6630 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
6632 Offset = GA->getOffset()+C->getValue();
6639 // If addressing this global requires a load (e.g. in PIC mode), we can't
6641 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
6645 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
6651 // Otherwise, not valid for this mode.
6657 Ops.push_back(Result);
6660 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
6663 std::vector<unsigned> X86TargetLowering::
6664 getRegClassForInlineAsmConstraint(const std::string &Constraint,
6665 MVT::ValueType VT) const {
6666 if (Constraint.size() == 1) {
6667 // FIXME: not handling fp-stack yet!
6668 switch (Constraint[0]) { // GCC X86 Constraint Letters
6669 default: break; // Unknown constraint letter
6670 case 'A': // EAX/EDX
6671 if (VT == MVT::i32 || VT == MVT::i64)
6672 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
6674 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
6677 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
6678 else if (VT == MVT::i16)
6679 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
6680 else if (VT == MVT::i8)
6681 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
6682 else if (VT == MVT::i64)
6683 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
6688 return std::vector<unsigned>();
6691 std::pair<unsigned, const TargetRegisterClass*>
6692 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
6693 MVT::ValueType VT) const {
6694 // First, see if this is a constraint that directly corresponds to an LLVM
6696 if (Constraint.size() == 1) {
6697 // GCC Constraint Letters
6698 switch (Constraint[0]) {
6700 case 'r': // GENERAL_REGS
6701 case 'R': // LEGACY_REGS
6702 case 'l': // INDEX_REGS
6703 if (VT == MVT::i64 && Subtarget->is64Bit())
6704 return std::make_pair(0U, X86::GR64RegisterClass);
6706 return std::make_pair(0U, X86::GR32RegisterClass);
6707 else if (VT == MVT::i16)
6708 return std::make_pair(0U, X86::GR16RegisterClass);
6709 else if (VT == MVT::i8)
6710 return std::make_pair(0U, X86::GR8RegisterClass);
6712 case 'f': // FP Stack registers.
6713 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
6714 // value to the correct fpstack register class.
6715 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
6716 return std::make_pair(0U, X86::RFP32RegisterClass);
6717 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
6718 return std::make_pair(0U, X86::RFP64RegisterClass);
6719 return std::make_pair(0U, X86::RFP80RegisterClass);
6720 case 'y': // MMX_REGS if MMX allowed.
6721 if (!Subtarget->hasMMX()) break;
6722 return std::make_pair(0U, X86::VR64RegisterClass);
6724 case 'Y': // SSE_REGS if SSE2 allowed
6725 if (!Subtarget->hasSSE2()) break;
6727 case 'x': // SSE_REGS if SSE1 allowed
6728 if (!Subtarget->hasSSE1()) break;
6732 // Scalar SSE types.
6735 return std::make_pair(0U, X86::FR32RegisterClass);
6738 return std::make_pair(0U, X86::FR64RegisterClass);
6746 return std::make_pair(0U, X86::VR128RegisterClass);
6752 // Use the default implementation in TargetLowering to convert the register
6753 // constraint into a member of a register class.
6754 std::pair<unsigned, const TargetRegisterClass*> Res;
6755 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
6757 // Not found as a standard register?
6758 if (Res.second == 0) {
6759 // GCC calls "st(0)" just plain "st".
6760 if (StringsEqualNoCase("{st}", Constraint)) {
6761 Res.first = X86::ST0;
6762 Res.second = X86::RFP80RegisterClass;
6768 // Otherwise, check to see if this is a register class of the wrong value
6769 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
6770 // turn into {ax},{dx}.
6771 if (Res.second->hasType(VT))
6772 return Res; // Correct type already, nothing to do.
6774 // All of the single-register GCC register classes map their values onto
6775 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
6776 // really want an 8-bit or 32-bit register, map to the appropriate register
6777 // class and return the appropriate register.
6778 if (Res.second != X86::GR16RegisterClass)
6781 if (VT == MVT::i8) {
6782 unsigned DestReg = 0;
6783 switch (Res.first) {
6785 case X86::AX: DestReg = X86::AL; break;
6786 case X86::DX: DestReg = X86::DL; break;
6787 case X86::CX: DestReg = X86::CL; break;
6788 case X86::BX: DestReg = X86::BL; break;
6791 Res.first = DestReg;
6792 Res.second = Res.second = X86::GR8RegisterClass;
6794 } else if (VT == MVT::i32) {
6795 unsigned DestReg = 0;
6796 switch (Res.first) {
6798 case X86::AX: DestReg = X86::EAX; break;
6799 case X86::DX: DestReg = X86::EDX; break;
6800 case X86::CX: DestReg = X86::ECX; break;
6801 case X86::BX: DestReg = X86::EBX; break;
6802 case X86::SI: DestReg = X86::ESI; break;
6803 case X86::DI: DestReg = X86::EDI; break;
6804 case X86::BP: DestReg = X86::EBP; break;
6805 case X86::SP: DestReg = X86::ESP; break;
6808 Res.first = DestReg;
6809 Res.second = Res.second = X86::GR32RegisterClass;
6811 } else if (VT == MVT::i64) {
6812 unsigned DestReg = 0;
6813 switch (Res.first) {
6815 case X86::AX: DestReg = X86::RAX; break;
6816 case X86::DX: DestReg = X86::RDX; break;
6817 case X86::CX: DestReg = X86::RCX; break;
6818 case X86::BX: DestReg = X86::RBX; break;
6819 case X86::SI: DestReg = X86::RSI; break;
6820 case X86::DI: DestReg = X86::RDI; break;
6821 case X86::BP: DestReg = X86::RBP; break;
6822 case X86::SP: DestReg = X86::RSP; break;
6825 Res.first = DestReg;
6826 Res.second = Res.second = X86::GR64RegisterClass;