1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/GlobalAlias.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/ADT/BitVector.h"
29 #include "llvm/ADT/VectorExtras.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/ADT/SmallSet.h"
42 #include "llvm/ADT/StringExtras.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/raw_ostream.h"
48 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
50 // Forward declarations.
51 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
54 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
55 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
56 default: llvm_unreachable("unknown subtarget type");
57 case X86Subtarget::isDarwin:
58 return new TargetLoweringObjectFileMachO();
59 case X86Subtarget::isELF:
60 return new TargetLoweringObjectFileELF();
61 case X86Subtarget::isMingw:
62 case X86Subtarget::isCygwin:
63 case X86Subtarget::isWindows:
64 return new TargetLoweringObjectFileCOFF();
69 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
70 : TargetLowering(TM, createTLOF(TM)) {
71 Subtarget = &TM.getSubtarget<X86Subtarget>();
72 X86ScalarSSEf64 = Subtarget->hasSSE2();
73 X86ScalarSSEf32 = Subtarget->hasSSE1();
74 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
76 RegInfo = TM.getRegisterInfo();
79 // Set up the TargetLowering object.
81 // X86 is weird, it always uses i8 for shift amounts and setcc results.
82 setShiftAmountType(MVT::i8);
83 setBooleanContents(ZeroOrOneBooleanContent);
84 setSchedulingPreference(SchedulingForRegPressure);
85 setStackPointerRegisterToSaveRestore(X86StackPtr);
87 if (Subtarget->isTargetDarwin()) {
88 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
89 setUseUnderscoreSetJmp(false);
90 setUseUnderscoreLongJmp(false);
91 } else if (Subtarget->isTargetMingw()) {
92 // MS runtime is weird: it exports _setjmp, but longjmp!
93 setUseUnderscoreSetJmp(true);
94 setUseUnderscoreLongJmp(false);
96 setUseUnderscoreSetJmp(true);
97 setUseUnderscoreLongJmp(true);
100 // Set up the register classes.
101 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
102 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
103 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
104 if (Subtarget->is64Bit())
105 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
107 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
109 // We don't accept any truncstore of integer registers.
110 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
111 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
112 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
113 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
114 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
115 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
117 // SETOEQ and SETUNE require checking two conditions.
118 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
119 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
120 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
121 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
122 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
123 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
125 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
127 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
128 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
129 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
131 if (Subtarget->is64Bit()) {
132 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
133 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
134 } else if (!UseSoftFloat) {
135 if (X86ScalarSSEf64) {
136 // We have an impenetrably clever algorithm for ui64->double only.
137 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
139 // We have an algorithm for SSE2, and we turn this into a 64-bit
140 // FILD for other targets.
141 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
144 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
146 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
147 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
150 // SSE has no i16 to fp conversion, only i32
151 if (X86ScalarSSEf32) {
152 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
153 // f32 and f64 cases are Legal, f80 case is not
154 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
156 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
157 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
160 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
161 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
164 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
165 // are Legal, f80 is custom lowered.
166 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
167 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
169 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
171 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
172 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
174 if (X86ScalarSSEf32) {
175 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
176 // f32 and f64 cases are Legal, f80 case is not
177 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
179 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
180 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
183 // Handle FP_TO_UINT by promoting the destination to a larger signed
185 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
186 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
187 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
189 if (Subtarget->is64Bit()) {
190 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
191 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
192 } else if (!UseSoftFloat) {
193 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
194 // Expand FP_TO_UINT into a select.
195 // FIXME: We would like to use a Custom expander here eventually to do
196 // the optimal thing for SSE vs. the default expansion in the legalizer.
197 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
199 // With SSE3 we can use fisttpll to convert to a signed i64; without
200 // SSE, we're stuck with a fistpll.
201 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
204 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
205 if (!X86ScalarSSEf64) {
206 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
207 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
210 // Scalar integer divide and remainder are lowered to use operations that
211 // produce two results, to match the available instructions. This exposes
212 // the two-result form to trivial CSE, which is able to combine x/y and x%y
213 // into a single instruction.
215 // Scalar integer multiply-high is also lowered to use two-result
216 // operations, to match the available instructions. However, plain multiply
217 // (low) operations are left as Legal, as there are single-result
218 // instructions for this in x86. Using the two-result multiply instructions
219 // when both high and low results are needed must be arranged by dagcombine.
220 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
221 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
222 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
223 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
224 setOperationAction(ISD::SREM , MVT::i8 , Expand);
225 setOperationAction(ISD::UREM , MVT::i8 , Expand);
226 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
227 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
228 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
229 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
230 setOperationAction(ISD::SREM , MVT::i16 , Expand);
231 setOperationAction(ISD::UREM , MVT::i16 , Expand);
232 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
233 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
234 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
235 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
236 setOperationAction(ISD::SREM , MVT::i32 , Expand);
237 setOperationAction(ISD::UREM , MVT::i32 , Expand);
238 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
239 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
240 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
241 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
242 setOperationAction(ISD::SREM , MVT::i64 , Expand);
243 setOperationAction(ISD::UREM , MVT::i64 , Expand);
245 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
246 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
247 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
248 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
249 if (Subtarget->is64Bit())
250 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
251 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
252 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
253 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
254 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
255 setOperationAction(ISD::FREM , MVT::f32 , Expand);
256 setOperationAction(ISD::FREM , MVT::f64 , Expand);
257 setOperationAction(ISD::FREM , MVT::f80 , Expand);
258 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
260 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
261 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
262 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
263 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
264 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
265 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
266 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
267 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
268 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
269 if (Subtarget->is64Bit()) {
270 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
271 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
272 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
275 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
276 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
278 // These should be promoted to a larger select which is supported.
279 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
280 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
281 // X86 wants to expand cmov itself.
282 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
283 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
284 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
285 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
286 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
287 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
288 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
289 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
290 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
291 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
292 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
293 if (Subtarget->is64Bit()) {
294 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
295 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
297 // X86 ret instruction may pop stack.
298 setOperationAction(ISD::RET , MVT::Other, Custom);
299 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
302 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
303 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
304 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
305 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
306 if (Subtarget->is64Bit())
307 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
308 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
309 if (Subtarget->is64Bit()) {
310 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
311 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
312 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
313 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
315 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
316 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
317 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
318 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
319 if (Subtarget->is64Bit()) {
320 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
321 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
322 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
325 if (Subtarget->hasSSE1())
326 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
328 if (!Subtarget->hasSSE2())
329 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
331 // Expand certain atomics
332 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
333 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
334 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
335 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
337 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
338 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
339 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
340 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
342 if (!Subtarget->is64Bit()) {
343 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
344 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
345 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
346 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
347 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
348 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
349 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
352 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
353 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
354 // FIXME - use subtarget debug flags
355 if (!Subtarget->isTargetDarwin() &&
356 !Subtarget->isTargetELF() &&
357 !Subtarget->isTargetCygMing()) {
358 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
359 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
362 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
363 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
364 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
365 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
366 if (Subtarget->is64Bit()) {
367 setExceptionPointerRegister(X86::RAX);
368 setExceptionSelectorRegister(X86::RDX);
370 setExceptionPointerRegister(X86::EAX);
371 setExceptionSelectorRegister(X86::EDX);
373 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
374 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
376 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
378 setOperationAction(ISD::TRAP, MVT::Other, Legal);
380 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
381 setOperationAction(ISD::VASTART , MVT::Other, Custom);
382 setOperationAction(ISD::VAEND , MVT::Other, Expand);
383 if (Subtarget->is64Bit()) {
384 setOperationAction(ISD::VAARG , MVT::Other, Custom);
385 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
387 setOperationAction(ISD::VAARG , MVT::Other, Expand);
388 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
391 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
392 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
393 if (Subtarget->is64Bit())
394 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
395 if (Subtarget->isTargetCygMing())
396 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
398 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
400 if (!UseSoftFloat && X86ScalarSSEf64) {
401 // f32 and f64 use SSE.
402 // Set up the FP register classes.
403 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
404 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
406 // Use ANDPD to simulate FABS.
407 setOperationAction(ISD::FABS , MVT::f64, Custom);
408 setOperationAction(ISD::FABS , MVT::f32, Custom);
410 // Use XORP to simulate FNEG.
411 setOperationAction(ISD::FNEG , MVT::f64, Custom);
412 setOperationAction(ISD::FNEG , MVT::f32, Custom);
414 // Use ANDPD and ORPD to simulate FCOPYSIGN.
415 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
416 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
418 // We don't support sin/cos/fmod
419 setOperationAction(ISD::FSIN , MVT::f64, Expand);
420 setOperationAction(ISD::FCOS , MVT::f64, Expand);
421 setOperationAction(ISD::FSIN , MVT::f32, Expand);
422 setOperationAction(ISD::FCOS , MVT::f32, Expand);
424 // Expand FP immediates into loads from the stack, except for the special
426 addLegalFPImmediate(APFloat(+0.0)); // xorpd
427 addLegalFPImmediate(APFloat(+0.0f)); // xorps
428 } else if (!UseSoftFloat && X86ScalarSSEf32) {
429 // Use SSE for f32, x87 for f64.
430 // Set up the FP register classes.
431 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
432 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
434 // Use ANDPS to simulate FABS.
435 setOperationAction(ISD::FABS , MVT::f32, Custom);
437 // Use XORP to simulate FNEG.
438 setOperationAction(ISD::FNEG , MVT::f32, Custom);
440 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
442 // Use ANDPS and ORPS to simulate FCOPYSIGN.
443 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
444 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
446 // We don't support sin/cos/fmod
447 setOperationAction(ISD::FSIN , MVT::f32, Expand);
448 setOperationAction(ISD::FCOS , MVT::f32, Expand);
450 // Special cases we handle for FP constants.
451 addLegalFPImmediate(APFloat(+0.0f)); // xorps
452 addLegalFPImmediate(APFloat(+0.0)); // FLD0
453 addLegalFPImmediate(APFloat(+1.0)); // FLD1
454 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
455 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
458 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
459 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
461 } else if (!UseSoftFloat) {
462 // f32 and f64 in x87.
463 // Set up the FP register classes.
464 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
465 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
467 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
468 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
469 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
470 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
473 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
474 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
476 addLegalFPImmediate(APFloat(+0.0)); // FLD0
477 addLegalFPImmediate(APFloat(+1.0)); // FLD1
478 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
479 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
480 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
481 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
482 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
483 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
486 // Long double always uses X87.
488 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
489 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
490 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
493 APFloat TmpFlt(+0.0);
494 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
496 addLegalFPImmediate(TmpFlt); // FLD0
498 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
499 APFloat TmpFlt2(+1.0);
500 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
502 addLegalFPImmediate(TmpFlt2); // FLD1
503 TmpFlt2.changeSign();
504 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
508 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
509 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
513 // Always use a library call for pow.
514 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
515 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
516 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
518 setOperationAction(ISD::FLOG, MVT::f80, Expand);
519 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
520 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
521 setOperationAction(ISD::FEXP, MVT::f80, Expand);
522 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
524 // First set operation action for all vector types to either promote
525 // (for widening) or expand (for scalarization). Then we will selectively
526 // turn on ones that can be effectively codegen'd.
527 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
528 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
529 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
530 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
531 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
532 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
533 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
534 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
535 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
538 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
539 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
540 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
541 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
542 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
543 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
544 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
545 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
579 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
580 // with -msoft-float, disable use of MMX as well.
581 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
582 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
583 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
584 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
585 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
586 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
588 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
589 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
590 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
591 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
593 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
594 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
595 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
596 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
598 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
599 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
601 setOperationAction(ISD::AND, MVT::v8i8, Promote);
602 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
603 setOperationAction(ISD::AND, MVT::v4i16, Promote);
604 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
605 setOperationAction(ISD::AND, MVT::v2i32, Promote);
606 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
607 setOperationAction(ISD::AND, MVT::v1i64, Legal);
609 setOperationAction(ISD::OR, MVT::v8i8, Promote);
610 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
611 setOperationAction(ISD::OR, MVT::v4i16, Promote);
612 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
613 setOperationAction(ISD::OR, MVT::v2i32, Promote);
614 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
615 setOperationAction(ISD::OR, MVT::v1i64, Legal);
617 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
618 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
619 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
620 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
621 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
622 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
623 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
625 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
626 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
627 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
628 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
629 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
630 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
631 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
632 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
633 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
635 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
636 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
637 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
638 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
639 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
641 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
642 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
643 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
644 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
646 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
647 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
648 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
649 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
651 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
653 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
654 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
655 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
656 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
657 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
658 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
659 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
660 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
661 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
664 if (!UseSoftFloat && Subtarget->hasSSE1()) {
665 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
667 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
668 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
669 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
670 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
671 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
672 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
673 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
674 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
675 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
676 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
677 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
678 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
681 if (!UseSoftFloat && Subtarget->hasSSE2()) {
682 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
684 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
685 // registers cannot be used even for integer operations.
686 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
687 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
688 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
689 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
691 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
692 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
693 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
694 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
695 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
696 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
697 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
698 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
699 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
700 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
701 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
702 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
703 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
704 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
705 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
706 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
708 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
709 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
710 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
711 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
713 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
714 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
715 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
716 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
717 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
719 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
720 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
721 MVT VT = (MVT::SimpleValueType)i;
722 // Do not attempt to custom lower non-power-of-2 vectors
723 if (!isPowerOf2_32(VT.getVectorNumElements()))
725 // Do not attempt to custom lower non-128-bit vectors
726 if (!VT.is128BitVector())
728 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
729 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
730 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
733 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
734 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
735 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
736 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
737 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
738 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
740 if (Subtarget->is64Bit()) {
741 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
742 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
745 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
746 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
747 MVT VT = (MVT::SimpleValueType)i;
749 // Do not attempt to promote non-128-bit vectors
750 if (!VT.is128BitVector()) {
753 setOperationAction(ISD::AND, VT, Promote);
754 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
755 setOperationAction(ISD::OR, VT, Promote);
756 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
757 setOperationAction(ISD::XOR, VT, Promote);
758 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
759 setOperationAction(ISD::LOAD, VT, Promote);
760 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
761 setOperationAction(ISD::SELECT, VT, Promote);
762 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
765 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
767 // Custom lower v2i64 and v2f64 selects.
768 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
769 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
770 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
771 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
773 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
774 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
775 if (!DisableMMX && Subtarget->hasMMX()) {
776 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
777 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
781 if (Subtarget->hasSSE41()) {
782 // FIXME: Do we need to handle scalar-to-vector here?
783 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
785 // i8 and i16 vectors are custom , because the source register and source
786 // source memory operand types are not the same width. f32 vectors are
787 // custom since the immediate controlling the insert encodes additional
789 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
790 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
791 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
792 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
794 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
795 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
796 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
797 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
799 if (Subtarget->is64Bit()) {
800 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
801 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
805 if (Subtarget->hasSSE42()) {
806 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
809 if (!UseSoftFloat && Subtarget->hasAVX()) {
810 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
811 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
812 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
813 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
815 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
816 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
817 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
818 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
819 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
820 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
821 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
822 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
823 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
824 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
825 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
826 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
827 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
828 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
829 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
831 // Operations to consider commented out -v16i16 v32i8
832 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
833 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
834 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
835 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
836 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
837 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
838 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
839 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
840 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
841 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
842 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
843 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
844 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
845 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
847 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
848 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
849 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
850 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
852 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
853 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
854 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
855 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
856 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
858 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
859 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
860 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
861 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
862 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
863 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
866 // Not sure we want to do this since there are no 256-bit integer
869 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
870 // This includes 256-bit vectors
871 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
872 MVT VT = (MVT::SimpleValueType)i;
874 // Do not attempt to custom lower non-power-of-2 vectors
875 if (!isPowerOf2_32(VT.getVectorNumElements()))
878 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
879 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
880 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
883 if (Subtarget->is64Bit()) {
884 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
885 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
890 // Not sure we want to do this since there are no 256-bit integer
893 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
894 // Including 256-bit vectors
895 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
896 MVT VT = (MVT::SimpleValueType)i;
898 if (!VT.is256BitVector()) {
901 setOperationAction(ISD::AND, VT, Promote);
902 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
903 setOperationAction(ISD::OR, VT, Promote);
904 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
905 setOperationAction(ISD::XOR, VT, Promote);
906 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
907 setOperationAction(ISD::LOAD, VT, Promote);
908 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
909 setOperationAction(ISD::SELECT, VT, Promote);
910 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
913 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
917 // We want to custom lower some of our intrinsics.
918 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
920 // Add/Sub/Mul with overflow operations are custom lowered.
921 setOperationAction(ISD::SADDO, MVT::i32, Custom);
922 setOperationAction(ISD::SADDO, MVT::i64, Custom);
923 setOperationAction(ISD::UADDO, MVT::i32, Custom);
924 setOperationAction(ISD::UADDO, MVT::i64, Custom);
925 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
926 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
927 setOperationAction(ISD::USUBO, MVT::i32, Custom);
928 setOperationAction(ISD::USUBO, MVT::i64, Custom);
929 setOperationAction(ISD::SMULO, MVT::i32, Custom);
930 setOperationAction(ISD::SMULO, MVT::i64, Custom);
932 if (!Subtarget->is64Bit()) {
933 // These libcalls are not available in 32-bit.
934 setLibcallName(RTLIB::SHL_I128, 0);
935 setLibcallName(RTLIB::SRL_I128, 0);
936 setLibcallName(RTLIB::SRA_I128, 0);
939 // We have target-specific dag combine patterns for the following nodes:
940 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
941 setTargetDAGCombine(ISD::BUILD_VECTOR);
942 setTargetDAGCombine(ISD::SELECT);
943 setTargetDAGCombine(ISD::SHL);
944 setTargetDAGCombine(ISD::SRA);
945 setTargetDAGCombine(ISD::SRL);
946 setTargetDAGCombine(ISD::STORE);
947 setTargetDAGCombine(ISD::MEMBARRIER);
948 if (Subtarget->is64Bit())
949 setTargetDAGCombine(ISD::MUL);
951 computeRegisterProperties();
953 // FIXME: These should be based on subtarget info. Plus, the values should
954 // be smaller when we are in optimizing for size mode.
955 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
956 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
957 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
958 allowUnalignedMemoryAccesses = true; // x86 supports it!
959 setPrefLoopAlignment(16);
960 benefitFromCodePlacementOpt = true;
964 MVT X86TargetLowering::getSetCCResultType(MVT VT) const {
969 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
970 /// the desired ByVal argument alignment.
971 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
974 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
975 if (VTy->getBitWidth() == 128)
977 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
978 unsigned EltAlign = 0;
979 getMaxByValAlign(ATy->getElementType(), EltAlign);
980 if (EltAlign > MaxAlign)
982 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
983 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
984 unsigned EltAlign = 0;
985 getMaxByValAlign(STy->getElementType(i), EltAlign);
986 if (EltAlign > MaxAlign)
995 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
996 /// function arguments in the caller parameter area. For X86, aggregates
997 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
998 /// are at 4-byte boundaries.
999 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1000 if (Subtarget->is64Bit()) {
1001 // Max of 8 and alignment of type.
1002 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1009 if (Subtarget->hasSSE1())
1010 getMaxByValAlign(Ty, Align);
1014 /// getOptimalMemOpType - Returns the target specific optimal type for load
1015 /// and store operations as a result of memset, memcpy, and memmove
1016 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1019 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1020 bool isSrcConst, bool isSrcStr,
1021 SelectionDAG &DAG) const {
1022 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1023 // linux. This is because the stack realignment code can't handle certain
1024 // cases like PR2962. This should be removed when PR2962 is fixed.
1025 const Function *F = DAG.getMachineFunction().getFunction();
1026 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1027 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1028 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1030 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1033 if (Subtarget->is64Bit() && Size >= 8)
1038 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1040 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1041 SelectionDAG &DAG) const {
1042 if (usesGlobalOffsetTable())
1043 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1044 if (!Subtarget->is64Bit())
1045 // This doesn't have DebugLoc associated with it, but is not really the
1046 // same as a Register.
1047 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1052 /// getFunctionAlignment - Return the Log2 alignment of this function.
1053 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1054 return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 4;
1057 //===----------------------------------------------------------------------===//
1058 // Return Value Calling Convention Implementation
1059 //===----------------------------------------------------------------------===//
1061 #include "X86GenCallingConv.inc"
1063 /// LowerRET - Lower an ISD::RET node.
1064 SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
1065 DebugLoc dl = Op.getDebugLoc();
1066 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
1068 SmallVector<CCValAssign, 16> RVLocs;
1069 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1070 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1071 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs, *DAG.getContext());
1072 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
1074 // If this is the first return lowered for this function, add the regs to the
1075 // liveout set for the function.
1076 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1077 for (unsigned i = 0; i != RVLocs.size(); ++i)
1078 if (RVLocs[i].isRegLoc())
1079 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1081 SDValue Chain = Op.getOperand(0);
1083 // Handle tail call return.
1084 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
1085 if (Chain.getOpcode() == X86ISD::TAILCALL) {
1086 SDValue TailCall = Chain;
1087 SDValue TargetAddress = TailCall.getOperand(1);
1088 SDValue StackAdjustment = TailCall.getOperand(2);
1089 assert(((TargetAddress.getOpcode() == ISD::Register &&
1090 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX ||
1091 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R11)) ||
1092 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
1093 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
1094 "Expecting an global address, external symbol, or register");
1095 assert(StackAdjustment.getOpcode() == ISD::Constant &&
1096 "Expecting a const value");
1098 SmallVector<SDValue,8> Operands;
1099 Operands.push_back(Chain.getOperand(0));
1100 Operands.push_back(TargetAddress);
1101 Operands.push_back(StackAdjustment);
1102 // Copy registers used by the call. Last operand is a flag so it is not
1104 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
1105 Operands.push_back(Chain.getOperand(i));
1107 return DAG.getNode(X86ISD::TC_RETURN, dl, MVT::Other, &Operands[0],
1114 SmallVector<SDValue, 6> RetOps;
1115 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1116 // Operand #1 = Bytes To Pop
1117 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
1119 // Copy the result values into the output registers.
1120 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1121 CCValAssign &VA = RVLocs[i];
1122 assert(VA.isRegLoc() && "Can only return in registers!");
1123 SDValue ValToCopy = Op.getOperand(i*2+1);
1125 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1126 // the RET instruction and handled by the FP Stackifier.
1127 if (VA.getLocReg() == X86::ST0 ||
1128 VA.getLocReg() == X86::ST1) {
1129 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1130 // change the value to the FP stack register class.
1131 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1132 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1133 RetOps.push_back(ValToCopy);
1134 // Don't emit a copytoreg.
1138 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1139 // which is returned in RAX / RDX.
1140 if (Subtarget->is64Bit()) {
1141 MVT ValVT = ValToCopy.getValueType();
1142 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1143 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1144 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1145 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1149 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1150 Flag = Chain.getValue(1);
1153 // The x86-64 ABI for returning structs by value requires that we copy
1154 // the sret argument into %rax for the return. We saved the argument into
1155 // a virtual register in the entry block, so now we copy the value out
1157 if (Subtarget->is64Bit() &&
1158 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1159 MachineFunction &MF = DAG.getMachineFunction();
1160 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1161 unsigned Reg = FuncInfo->getSRetReturnReg();
1163 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1164 FuncInfo->setSRetReturnReg(Reg);
1166 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1168 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1169 Flag = Chain.getValue(1);
1172 RetOps[0] = Chain; // Update chain.
1174 // Add the flag if we have it.
1176 RetOps.push_back(Flag);
1178 return DAG.getNode(X86ISD::RET_FLAG, dl,
1179 MVT::Other, &RetOps[0], RetOps.size());
1183 /// LowerCallResult - Lower the result values of an ISD::CALL into the
1184 /// appropriate copies out of appropriate physical registers. This assumes that
1185 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
1186 /// being lowered. The returns a SDNode with the same number of values as the
1188 SDNode *X86TargetLowering::
1189 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
1190 unsigned CallingConv, SelectionDAG &DAG) {
1192 DebugLoc dl = TheCall->getDebugLoc();
1193 // Assign locations to each value returned by this call.
1194 SmallVector<CCValAssign, 16> RVLocs;
1195 bool isVarArg = TheCall->isVarArg();
1196 bool Is64Bit = Subtarget->is64Bit();
1197 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(),
1198 RVLocs, *DAG.getContext());
1199 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
1201 SmallVector<SDValue, 8> ResultVals;
1203 // Copy all of the result registers out of their specified physreg.
1204 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1205 CCValAssign &VA = RVLocs[i];
1206 MVT CopyVT = VA.getValVT();
1208 // If this is x86-64, and we disabled SSE, we can't return FP values
1209 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1210 ((Is64Bit || TheCall->isInreg()) && !Subtarget->hasSSE1())) {
1211 llvm_report_error("SSE register return with SSE disabled");
1214 // If this is a call to a function that returns an fp value on the floating
1215 // point stack, but where we prefer to use the value in xmm registers, copy
1216 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1217 if ((VA.getLocReg() == X86::ST0 ||
1218 VA.getLocReg() == X86::ST1) &&
1219 isScalarFPTypeInSSEReg(VA.getValVT())) {
1224 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1225 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1226 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1227 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1228 MVT::v2i64, InFlag).getValue(1);
1229 Val = Chain.getValue(0);
1230 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1231 Val, DAG.getConstant(0, MVT::i64));
1233 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1234 MVT::i64, InFlag).getValue(1);
1235 Val = Chain.getValue(0);
1237 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1239 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1240 CopyVT, InFlag).getValue(1);
1241 Val = Chain.getValue(0);
1243 InFlag = Chain.getValue(2);
1245 if (CopyVT != VA.getValVT()) {
1246 // Round the F80 the right size, which also moves to the appropriate xmm
1248 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1249 // This truncation won't change the value.
1250 DAG.getIntPtrConstant(1));
1253 ResultVals.push_back(Val);
1256 // Merge everything together with a MERGE_VALUES node.
1257 ResultVals.push_back(Chain);
1258 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
1259 &ResultVals[0], ResultVals.size()).getNode();
1263 //===----------------------------------------------------------------------===//
1264 // C & StdCall & Fast Calling Convention implementation
1265 //===----------------------------------------------------------------------===//
1266 // StdCall calling convention seems to be standard for many Windows' API
1267 // routines and around. It differs from C calling convention just a little:
1268 // callee should clean up the stack, not caller. Symbols should be also
1269 // decorated in some fancy way :) It doesn't support any vector arguments.
1270 // For info on fast calling convention see Fast Calling Convention (tail call)
1271 // implementation LowerX86_32FastCCCallTo.
1273 /// CallIsStructReturn - Determines whether a CALL node uses struct return
1275 static bool CallIsStructReturn(CallSDNode *TheCall) {
1276 unsigned NumOps = TheCall->getNumArgs();
1280 return TheCall->getArgFlags(0).isSRet();
1283 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1284 /// return semantics.
1285 static bool ArgsAreStructReturn(SDValue Op) {
1286 unsigned NumArgs = Op.getNode()->getNumValues() - 1;
1290 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
1293 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1294 /// the callee to pop its own arguments. Callee pop is necessary to support tail
1296 bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
1300 switch (CallingConv) {
1303 case CallingConv::X86_StdCall:
1304 return !Subtarget->is64Bit();
1305 case CallingConv::X86_FastCall:
1306 return !Subtarget->is64Bit();
1307 case CallingConv::Fast:
1308 return PerformTailCallOpt;
1312 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1313 /// given CallingConvention value.
1314 CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
1315 if (Subtarget->is64Bit()) {
1316 if (Subtarget->isTargetWin64())
1317 return CC_X86_Win64_C;
1322 if (CC == CallingConv::X86_FastCall)
1323 return CC_X86_32_FastCall;
1324 else if (CC == CallingConv::Fast)
1325 return CC_X86_32_FastCC;
1330 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1331 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1333 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
1334 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1335 if (CC == CallingConv::X86_FastCall)
1337 else if (CC == CallingConv::X86_StdCall)
1343 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1344 /// by "Src" to address "Dst" with size and alignment information specified by
1345 /// the specific parameter attribute. The copy will be passed as a byval
1346 /// function parameter.
1348 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1349 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1351 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1352 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1353 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1356 SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
1357 const CCValAssign &VA,
1358 MachineFrameInfo *MFI,
1360 SDValue Root, unsigned i) {
1361 // Create the nodes corresponding to a load from this parameter slot.
1362 ISD::ArgFlagsTy Flags =
1363 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1364 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1365 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1367 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1368 // changed with more analysis.
1369 // In case of tail call optimization mark all arguments mutable. Since they
1370 // could be overwritten by lowering of arguments in case of a tail call.
1371 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1372 VA.getLocMemOffset(), isImmutable);
1373 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1374 if (Flags.isByVal())
1376 return DAG.getLoad(VA.getValVT(), Op.getDebugLoc(), Root, FIN,
1377 PseudoSourceValue::getFixedStack(FI), 0);
1381 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1382 MachineFunction &MF = DAG.getMachineFunction();
1383 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1384 DebugLoc dl = Op.getDebugLoc();
1386 const Function* Fn = MF.getFunction();
1387 if (Fn->hasExternalLinkage() &&
1388 Subtarget->isTargetCygMing() &&
1389 Fn->getName() == "main")
1390 FuncInfo->setForceFramePointer(true);
1392 // Decorate the function name.
1393 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1395 MachineFrameInfo *MFI = MF.getFrameInfo();
1396 SDValue Root = Op.getOperand(0);
1397 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1398 unsigned CC = MF.getFunction()->getCallingConv();
1399 bool Is64Bit = Subtarget->is64Bit();
1400 bool IsWin64 = Subtarget->isTargetWin64();
1402 assert(!(isVarArg && CC == CallingConv::Fast) &&
1403 "Var args not supported with calling convention fastcc");
1405 // Assign locations to all of the incoming arguments.
1406 SmallVector<CCValAssign, 16> ArgLocs;
1407 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext());
1408 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC));
1410 SmallVector<SDValue, 8> ArgValues;
1411 unsigned LastVal = ~0U;
1412 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1413 CCValAssign &VA = ArgLocs[i];
1414 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1416 assert(VA.getValNo() != LastVal &&
1417 "Don't support value assigned to multiple locs yet");
1418 LastVal = VA.getValNo();
1420 if (VA.isRegLoc()) {
1421 MVT RegVT = VA.getLocVT();
1422 TargetRegisterClass *RC = NULL;
1423 if (RegVT == MVT::i32)
1424 RC = X86::GR32RegisterClass;
1425 else if (Is64Bit && RegVT == MVT::i64)
1426 RC = X86::GR64RegisterClass;
1427 else if (RegVT == MVT::f32)
1428 RC = X86::FR32RegisterClass;
1429 else if (RegVT == MVT::f64)
1430 RC = X86::FR64RegisterClass;
1431 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1432 RC = X86::VR128RegisterClass;
1433 else if (RegVT.isVector()) {
1434 assert(RegVT.getSizeInBits() == 64);
1436 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1438 // Darwin calling convention passes MMX values in either GPRs or
1439 // XMMs in x86-64. Other targets pass them in memory.
1440 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1441 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1444 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1449 llvm_unreachable("Unknown argument type!");
1452 unsigned Reg = DAG.getMachineFunction().addLiveIn(VA.getLocReg(), RC);
1453 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
1455 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1456 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1458 if (VA.getLocInfo() == CCValAssign::SExt)
1459 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1460 DAG.getValueType(VA.getValVT()));
1461 else if (VA.getLocInfo() == CCValAssign::ZExt)
1462 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1463 DAG.getValueType(VA.getValVT()));
1465 if (VA.getLocInfo() != CCValAssign::Full)
1466 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1468 // Handle MMX values passed in GPRs.
1469 if (Is64Bit && RegVT != VA.getLocVT()) {
1470 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
1471 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
1472 else if (RC == X86::VR128RegisterClass) {
1473 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1474 ArgValue, DAG.getConstant(0, MVT::i64));
1475 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
1479 ArgValues.push_back(ArgValue);
1481 assert(VA.isMemLoc());
1482 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1486 // The x86-64 ABI for returning structs by value requires that we copy
1487 // the sret argument into %rax for the return. Save the argument into
1488 // a virtual register so that we can access it from the return points.
1489 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1490 MachineFunction &MF = DAG.getMachineFunction();
1491 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1492 unsigned Reg = FuncInfo->getSRetReturnReg();
1494 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1495 FuncInfo->setSRetReturnReg(Reg);
1497 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]);
1498 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root);
1501 unsigned StackSize = CCInfo.getNextStackOffset();
1502 // align stack specially for tail calls
1503 if (PerformTailCallOpt && CC == CallingConv::Fast)
1504 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1506 // If the function takes variable number of arguments, make a frame index for
1507 // the start of the first vararg value... for expansion of llvm.va_start.
1509 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1510 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1513 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1515 // FIXME: We should really autogenerate these arrays
1516 static const unsigned GPR64ArgRegsWin64[] = {
1517 X86::RCX, X86::RDX, X86::R8, X86::R9
1519 static const unsigned XMMArgRegsWin64[] = {
1520 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1522 static const unsigned GPR64ArgRegs64Bit[] = {
1523 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1525 static const unsigned XMMArgRegs64Bit[] = {
1526 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1527 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1529 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1532 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1533 GPR64ArgRegs = GPR64ArgRegsWin64;
1534 XMMArgRegs = XMMArgRegsWin64;
1536 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1537 GPR64ArgRegs = GPR64ArgRegs64Bit;
1538 XMMArgRegs = XMMArgRegs64Bit;
1540 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1542 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1545 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1546 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1547 "SSE register cannot be used when SSE is disabled!");
1548 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1549 "SSE register cannot be used when SSE is disabled!");
1550 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1551 // Kernel mode asks for SSE to be disabled, so don't push them
1553 TotalNumXMMRegs = 0;
1555 // For X86-64, if there are vararg parameters that are passed via
1556 // registers, then we must store them to their spots on the stack so they
1557 // may be loaded by deferencing the result of va_next.
1558 VarArgsGPOffset = NumIntRegs * 8;
1559 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1560 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1561 TotalNumXMMRegs * 16, 16);
1563 // Store the integer parameter registers.
1564 SmallVector<SDValue, 8> MemOps;
1565 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1566 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1567 DAG.getIntPtrConstant(VarArgsGPOffset));
1568 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1569 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1570 X86::GR64RegisterClass);
1571 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
1573 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1574 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1575 MemOps.push_back(Store);
1576 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1577 DAG.getIntPtrConstant(8));
1580 // Now store the XMM (fp + vector) parameter registers.
1581 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1582 DAG.getIntPtrConstant(VarArgsFPOffset));
1583 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1584 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1585 X86::VR128RegisterClass);
1586 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::v4f32);
1588 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1589 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1590 MemOps.push_back(Store);
1591 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1592 DAG.getIntPtrConstant(16));
1594 if (!MemOps.empty())
1595 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1596 &MemOps[0], MemOps.size());
1600 ArgValues.push_back(Root);
1602 // Some CCs need callee pop.
1603 if (IsCalleePop(isVarArg, CC)) {
1604 BytesToPopOnReturn = StackSize; // Callee pops everything.
1605 BytesCallerReserves = 0;
1607 BytesToPopOnReturn = 0; // Callee pops nothing.
1608 // If this is an sret function, the return should pop the hidden pointer.
1609 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op))
1610 BytesToPopOnReturn = 4;
1611 BytesCallerReserves = StackSize;
1615 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1616 if (CC == CallingConv::X86_FastCall)
1617 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1620 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1622 // Return the new list of results.
1623 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1624 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1628 X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
1629 const SDValue &StackPtr,
1630 const CCValAssign &VA,
1632 SDValue Arg, ISD::ArgFlagsTy Flags) {
1633 DebugLoc dl = TheCall->getDebugLoc();
1634 unsigned LocMemOffset = VA.getLocMemOffset();
1635 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1636 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1637 if (Flags.isByVal()) {
1638 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1640 return DAG.getStore(Chain, dl, Arg, PtrOff,
1641 PseudoSourceValue::getStack(), LocMemOffset);
1644 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1645 /// optimization is performed and it is required.
1647 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1648 SDValue &OutRetAddr,
1654 if (!IsTailCall || FPDiff==0) return Chain;
1656 // Adjust the Return address stack slot.
1657 MVT VT = getPointerTy();
1658 OutRetAddr = getReturnAddressFrameIndex(DAG);
1660 // Load the "old" Return address.
1661 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1662 return SDValue(OutRetAddr.getNode(), 1);
1665 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1666 /// optimization is performed and it is required (FPDiff!=0).
1668 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1669 SDValue Chain, SDValue RetAddrFrIdx,
1670 bool Is64Bit, int FPDiff, DebugLoc dl) {
1671 // Store the return address to the appropriate stack slot.
1672 if (!FPDiff) return Chain;
1673 // Calculate the new stack slot for the return address.
1674 int SlotSize = Is64Bit ? 8 : 4;
1675 int NewReturnAddrFI =
1676 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1677 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1678 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1679 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1680 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1684 SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1685 MachineFunction &MF = DAG.getMachineFunction();
1686 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
1687 SDValue Chain = TheCall->getChain();
1688 unsigned CC = TheCall->getCallingConv();
1689 bool isVarArg = TheCall->isVarArg();
1690 bool IsTailCall = TheCall->isTailCall() &&
1691 CC == CallingConv::Fast && PerformTailCallOpt;
1692 SDValue Callee = TheCall->getCallee();
1693 bool Is64Bit = Subtarget->is64Bit();
1694 bool IsStructRet = CallIsStructReturn(TheCall);
1695 DebugLoc dl = TheCall->getDebugLoc();
1697 assert(!(isVarArg && CC == CallingConv::Fast) &&
1698 "Var args not supported with calling convention fastcc");
1700 // Analyze operands of the call, assigning locations to each operand.
1701 SmallVector<CCValAssign, 16> ArgLocs;
1702 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext());
1703 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC));
1705 // Get a count of how many bytes are to be pushed on the stack.
1706 unsigned NumBytes = CCInfo.getNextStackOffset();
1707 if (PerformTailCallOpt && CC == CallingConv::Fast)
1708 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1712 // Lower arguments at fp - stackoffset + fpdiff.
1713 unsigned NumBytesCallerPushed =
1714 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1715 FPDiff = NumBytesCallerPushed - NumBytes;
1717 // Set the delta of movement of the returnaddr stackslot.
1718 // But only set if delta is greater than previous delta.
1719 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1720 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1723 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1725 SDValue RetAddrFrIdx;
1726 // Load return adress for tail calls.
1727 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1730 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1731 SmallVector<SDValue, 8> MemOpChains;
1734 // Walk the register/memloc assignments, inserting copies/loads. In the case
1735 // of tail call optimization arguments are handle later.
1736 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1737 CCValAssign &VA = ArgLocs[i];
1738 SDValue Arg = TheCall->getArg(i);
1739 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1740 bool isByVal = Flags.isByVal();
1742 // Promote the value if needed.
1743 switch (VA.getLocInfo()) {
1744 default: llvm_unreachable("Unknown loc info!");
1745 case CCValAssign::Full: break;
1746 case CCValAssign::SExt:
1747 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1749 case CCValAssign::ZExt:
1750 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1752 case CCValAssign::AExt:
1753 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1757 if (VA.isRegLoc()) {
1759 MVT RegVT = VA.getLocVT();
1760 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1761 switch (VA.getLocReg()) {
1764 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1766 // Special case: passing MMX values in GPR registers.
1767 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1770 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1771 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1772 // Special case: passing MMX values in XMM registers.
1773 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1774 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1775 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1780 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1782 if (!IsTailCall || (IsTailCall && isByVal)) {
1783 assert(VA.isMemLoc());
1784 if (StackPtr.getNode() == 0)
1785 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1787 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
1788 Chain, Arg, Flags));
1793 if (!MemOpChains.empty())
1794 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1795 &MemOpChains[0], MemOpChains.size());
1797 // Build a sequence of copy-to-reg nodes chained together with token chain
1798 // and flag operands which copy the outgoing args into registers.
1800 // Tail call byval lowering might overwrite argument registers so in case of
1801 // tail call optimization the copies to registers are lowered later.
1803 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1804 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1805 RegsToPass[i].second, InFlag);
1806 InFlag = Chain.getValue(1);
1810 if (Subtarget->isPICStyleGOT()) {
1811 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1814 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1815 DAG.getNode(X86ISD::GlobalBaseReg,
1816 DebugLoc::getUnknownLoc(),
1819 InFlag = Chain.getValue(1);
1821 // If we are tail calling and generating PIC/GOT style code load the
1822 // address of the callee into ECX. The value in ecx is used as target of
1823 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1824 // for tail calls on PIC/GOT architectures. Normally we would just put the
1825 // address of GOT into ebx and then call target@PLT. But for tail calls
1826 // ebx would be restored (since ebx is callee saved) before jumping to the
1829 // Note: The actual moving to ECX is done further down.
1830 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1831 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1832 !G->getGlobal()->hasProtectedVisibility())
1833 Callee = LowerGlobalAddress(Callee, DAG);
1834 else if (isa<ExternalSymbolSDNode>(Callee))
1835 Callee = LowerExternalSymbol(Callee, DAG);
1839 if (Is64Bit && isVarArg) {
1840 // From AMD64 ABI document:
1841 // For calls that may call functions that use varargs or stdargs
1842 // (prototype-less calls or calls to functions containing ellipsis (...) in
1843 // the declaration) %al is used as hidden argument to specify the number
1844 // of SSE registers used. The contents of %al do not need to match exactly
1845 // the number of registers, but must be an ubound on the number of SSE
1846 // registers used and is in the range 0 - 8 inclusive.
1848 // FIXME: Verify this on Win64
1849 // Count the number of XMM registers allocated.
1850 static const unsigned XMMArgRegs[] = {
1851 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1852 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1854 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1855 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1856 && "SSE registers cannot be used when SSE is disabled");
1858 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1859 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1860 InFlag = Chain.getValue(1);
1864 // For tail calls lower the arguments to the 'real' stack slot.
1866 SmallVector<SDValue, 8> MemOpChains2;
1869 // Do not flag preceeding copytoreg stuff together with the following stuff.
1871 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1872 CCValAssign &VA = ArgLocs[i];
1873 if (!VA.isRegLoc()) {
1874 assert(VA.isMemLoc());
1875 SDValue Arg = TheCall->getArg(i);
1876 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1877 // Create frame index.
1878 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1879 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1880 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1881 FIN = DAG.getFrameIndex(FI, getPointerTy());
1883 if (Flags.isByVal()) {
1884 // Copy relative to framepointer.
1885 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1886 if (StackPtr.getNode() == 0)
1887 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1889 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1891 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1894 // Store relative to framepointer.
1895 MemOpChains2.push_back(
1896 DAG.getStore(Chain, dl, Arg, FIN,
1897 PseudoSourceValue::getFixedStack(FI), 0));
1902 if (!MemOpChains2.empty())
1903 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1904 &MemOpChains2[0], MemOpChains2.size());
1906 // Copy arguments to their registers.
1907 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1908 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1909 RegsToPass[i].second, InFlag);
1910 InFlag = Chain.getValue(1);
1914 // Store the return address to the appropriate stack slot.
1915 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1919 // If the callee is a GlobalAddress node (quite common, every direct call is)
1920 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1921 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1922 // We should use extra load for direct calls to dllimported functions in
1924 GlobalValue *GV = G->getGlobal();
1925 if (!GV->hasDLLImportLinkage()) {
1926 unsigned char OpFlags = 0;
1928 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1929 // external symbols most go through the PLT in PIC mode. If the symbol
1930 // has hidden or protected visibility, or if it is static or local, then
1931 // we don't need to use the PLT - we can directly call it.
1932 if (Subtarget->isTargetELF() &&
1933 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1934 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1935 OpFlags = X86II::MO_PLT;
1936 } else if (Subtarget->isPICStyleStubAny() &&
1937 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1938 Subtarget->getDarwinVers() < 9) {
1939 // PC-relative references to external symbols should go through $stub,
1940 // unless we're building with the leopard linker or later, which
1941 // automatically synthesizes these stubs.
1942 OpFlags = X86II::MO_DARWIN_STUB;
1945 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
1946 G->getOffset(), OpFlags);
1948 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1949 unsigned char OpFlags = 0;
1951 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
1952 // symbols should go through the PLT.
1953 if (Subtarget->isTargetELF() &&
1954 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1955 OpFlags = X86II::MO_PLT;
1956 } else if (Subtarget->isPICStyleStubAny() &&
1957 Subtarget->getDarwinVers() < 9) {
1958 // PC-relative references to external symbols should go through $stub,
1959 // unless we're building with the leopard linker or later, which
1960 // automatically synthesizes these stubs.
1961 OpFlags = X86II::MO_DARWIN_STUB;
1964 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
1966 } else if (IsTailCall) {
1967 unsigned Opc = Is64Bit ? X86::R11 : X86::EAX;
1969 Chain = DAG.getCopyToReg(Chain, dl,
1970 DAG.getRegister(Opc, getPointerTy()),
1972 Callee = DAG.getRegister(Opc, getPointerTy());
1973 // Add register as live out.
1974 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1977 // Returns a chain & a flag for retval copy to use.
1978 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1979 SmallVector<SDValue, 8> Ops;
1982 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1983 DAG.getIntPtrConstant(0, true), InFlag);
1984 InFlag = Chain.getValue(1);
1986 // Returns a chain & a flag for retval copy to use.
1987 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1991 Ops.push_back(Chain);
1992 Ops.push_back(Callee);
1995 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1997 // Add argument registers to the end of the list so that they are known live
1999 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2000 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2001 RegsToPass[i].second.getValueType()));
2003 // Add an implicit use GOT pointer in EBX.
2004 if (!IsTailCall && Subtarget->isPICStyleGOT())
2005 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2007 // Add an implicit use of AL for x86 vararg functions.
2008 if (Is64Bit && isVarArg)
2009 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2011 if (InFlag.getNode())
2012 Ops.push_back(InFlag);
2015 assert(InFlag.getNode() &&
2016 "Flag must be set. Depend on flag being set in LowerRET");
2017 Chain = DAG.getNode(X86ISD::TAILCALL, dl,
2018 TheCall->getVTList(), &Ops[0], Ops.size());
2020 return SDValue(Chain.getNode(), Op.getResNo());
2023 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2024 InFlag = Chain.getValue(1);
2026 // Create the CALLSEQ_END node.
2027 unsigned NumBytesForCalleeToPush;
2028 if (IsCalleePop(isVarArg, CC))
2029 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2030 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet)
2031 // If this is is a call to a struct-return function, the callee
2032 // pops the hidden struct pointer, so we have to push it back.
2033 // This is common for Darwin/X86, Linux & Mingw32 targets.
2034 NumBytesForCalleeToPush = 4;
2036 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2038 // Returns a flag for retval copy to use.
2039 Chain = DAG.getCALLSEQ_END(Chain,
2040 DAG.getIntPtrConstant(NumBytes, true),
2041 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2044 InFlag = Chain.getValue(1);
2046 // Handle result values, copying them out of physregs into vregs that we
2048 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
2053 //===----------------------------------------------------------------------===//
2054 // Fast Calling Convention (tail call) implementation
2055 //===----------------------------------------------------------------------===//
2057 // Like std call, callee cleans arguments, convention except that ECX is
2058 // reserved for storing the tail called function address. Only 2 registers are
2059 // free for argument passing (inreg). Tail call optimization is performed
2061 // * tailcallopt is enabled
2062 // * caller/callee are fastcc
2063 // On X86_64 architecture with GOT-style position independent code only local
2064 // (within module) calls are supported at the moment.
2065 // To keep the stack aligned according to platform abi the function
2066 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2067 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2068 // If a tail called function callee has more arguments than the caller the
2069 // caller needs to make sure that there is room to move the RETADDR to. This is
2070 // achieved by reserving an area the size of the argument delta right after the
2071 // original REtADDR, but before the saved framepointer or the spilled registers
2072 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2084 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2085 /// for a 16 byte align requirement.
2086 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2087 SelectionDAG& DAG) {
2088 MachineFunction &MF = DAG.getMachineFunction();
2089 const TargetMachine &TM = MF.getTarget();
2090 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2091 unsigned StackAlignment = TFI.getStackAlignment();
2092 uint64_t AlignMask = StackAlignment - 1;
2093 int64_t Offset = StackSize;
2094 uint64_t SlotSize = TD->getPointerSize();
2095 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2096 // Number smaller than 12 so just add the difference.
2097 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2099 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2100 Offset = ((~AlignMask) & Offset) + StackAlignment +
2101 (StackAlignment-SlotSize);
2106 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
2107 /// following the call is a return. A function is eligible if caller/callee
2108 /// calling conventions match, currently only fastcc supports tail calls, and
2109 /// the function CALL is immediatly followed by a RET.
2110 bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
2112 SelectionDAG& DAG) const {
2113 if (!PerformTailCallOpt)
2116 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
2118 DAG.getMachineFunction().getFunction()->getCallingConv();
2119 unsigned CalleeCC = TheCall->getCallingConv();
2120 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC)
2128 X86TargetLowering::createFastISel(MachineFunction &mf,
2129 MachineModuleInfo *mmo,
2131 DenseMap<const Value *, unsigned> &vm,
2132 DenseMap<const BasicBlock *,
2133 MachineBasicBlock *> &bm,
2134 DenseMap<const AllocaInst *, int> &am
2136 , SmallSet<Instruction*, 8> &cil
2139 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2147 //===----------------------------------------------------------------------===//
2148 // Other Lowering Hooks
2149 //===----------------------------------------------------------------------===//
2152 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2153 MachineFunction &MF = DAG.getMachineFunction();
2154 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2155 int ReturnAddrIndex = FuncInfo->getRAIndex();
2157 if (ReturnAddrIndex == 0) {
2158 // Set up a frame object for the return address.
2159 uint64_t SlotSize = TD->getPointerSize();
2160 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
2161 FuncInfo->setRAIndex(ReturnAddrIndex);
2164 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2168 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2169 /// specific condition code, returning the condition code and the LHS/RHS of the
2170 /// comparison to make.
2171 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2172 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2174 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2175 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2176 // X > -1 -> X == 0, jump !sign.
2177 RHS = DAG.getConstant(0, RHS.getValueType());
2178 return X86::COND_NS;
2179 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2180 // X < 0 -> X == 0, jump on sign.
2182 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2184 RHS = DAG.getConstant(0, RHS.getValueType());
2185 return X86::COND_LE;
2189 switch (SetCCOpcode) {
2190 default: llvm_unreachable("Invalid integer condition!");
2191 case ISD::SETEQ: return X86::COND_E;
2192 case ISD::SETGT: return X86::COND_G;
2193 case ISD::SETGE: return X86::COND_GE;
2194 case ISD::SETLT: return X86::COND_L;
2195 case ISD::SETLE: return X86::COND_LE;
2196 case ISD::SETNE: return X86::COND_NE;
2197 case ISD::SETULT: return X86::COND_B;
2198 case ISD::SETUGT: return X86::COND_A;
2199 case ISD::SETULE: return X86::COND_BE;
2200 case ISD::SETUGE: return X86::COND_AE;
2204 // First determine if it is required or is profitable to flip the operands.
2206 // If LHS is a foldable load, but RHS is not, flip the condition.
2207 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2208 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2209 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2210 std::swap(LHS, RHS);
2213 switch (SetCCOpcode) {
2219 std::swap(LHS, RHS);
2223 // On a floating point condition, the flags are set as follows:
2225 // 0 | 0 | 0 | X > Y
2226 // 0 | 0 | 1 | X < Y
2227 // 1 | 0 | 0 | X == Y
2228 // 1 | 1 | 1 | unordered
2229 switch (SetCCOpcode) {
2230 default: llvm_unreachable("Condcode should be pre-legalized away");
2232 case ISD::SETEQ: return X86::COND_E;
2233 case ISD::SETOLT: // flipped
2235 case ISD::SETGT: return X86::COND_A;
2236 case ISD::SETOLE: // flipped
2238 case ISD::SETGE: return X86::COND_AE;
2239 case ISD::SETUGT: // flipped
2241 case ISD::SETLT: return X86::COND_B;
2242 case ISD::SETUGE: // flipped
2244 case ISD::SETLE: return X86::COND_BE;
2246 case ISD::SETNE: return X86::COND_NE;
2247 case ISD::SETUO: return X86::COND_P;
2248 case ISD::SETO: return X86::COND_NP;
2252 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2253 /// code. Current x86 isa includes the following FP cmov instructions:
2254 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2255 static bool hasFPCMov(unsigned X86CC) {
2271 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2272 /// the specified range (L, H].
2273 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2274 return (Val < 0) || (Val >= Low && Val < Hi);
2277 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2278 /// specified value.
2279 static bool isUndefOrEqual(int Val, int CmpVal) {
2280 if (Val < 0 || Val == CmpVal)
2285 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2286 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2287 /// the second operand.
2288 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2289 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2290 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2291 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2292 return (Mask[0] < 2 && Mask[1] < 2);
2296 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2297 SmallVector<int, 8> M;
2299 return ::isPSHUFDMask(M, N->getValueType(0));
2302 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2303 /// is suitable for input to PSHUFHW.
2304 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2305 if (VT != MVT::v8i16)
2308 // Lower quadword copied in order or undef.
2309 for (int i = 0; i != 4; ++i)
2310 if (Mask[i] >= 0 && Mask[i] != i)
2313 // Upper quadword shuffled.
2314 for (int i = 4; i != 8; ++i)
2315 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2321 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2322 SmallVector<int, 8> M;
2324 return ::isPSHUFHWMask(M, N->getValueType(0));
2327 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2328 /// is suitable for input to PSHUFLW.
2329 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2330 if (VT != MVT::v8i16)
2333 // Upper quadword copied in order.
2334 for (int i = 4; i != 8; ++i)
2335 if (Mask[i] >= 0 && Mask[i] != i)
2338 // Lower quadword shuffled.
2339 for (int i = 0; i != 4; ++i)
2346 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2347 SmallVector<int, 8> M;
2349 return ::isPSHUFLWMask(M, N->getValueType(0));
2352 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2353 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2354 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2355 int NumElems = VT.getVectorNumElements();
2356 if (NumElems != 2 && NumElems != 4)
2359 int Half = NumElems / 2;
2360 for (int i = 0; i < Half; ++i)
2361 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2363 for (int i = Half; i < NumElems; ++i)
2364 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2370 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2371 SmallVector<int, 8> M;
2373 return ::isSHUFPMask(M, N->getValueType(0));
2376 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2377 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2378 /// half elements to come from vector 1 (which would equal the dest.) and
2379 /// the upper half to come from vector 2.
2380 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2381 int NumElems = VT.getVectorNumElements();
2383 if (NumElems != 2 && NumElems != 4)
2386 int Half = NumElems / 2;
2387 for (int i = 0; i < Half; ++i)
2388 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2390 for (int i = Half; i < NumElems; ++i)
2391 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2396 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2397 SmallVector<int, 8> M;
2399 return isCommutedSHUFPMask(M, N->getValueType(0));
2402 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2403 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2404 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2405 if (N->getValueType(0).getVectorNumElements() != 4)
2408 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2409 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2410 isUndefOrEqual(N->getMaskElt(1), 7) &&
2411 isUndefOrEqual(N->getMaskElt(2), 2) &&
2412 isUndefOrEqual(N->getMaskElt(3), 3);
2415 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2416 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2417 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2418 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2420 if (NumElems != 2 && NumElems != 4)
2423 for (unsigned i = 0; i < NumElems/2; ++i)
2424 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2427 for (unsigned i = NumElems/2; i < NumElems; ++i)
2428 if (!isUndefOrEqual(N->getMaskElt(i), i))
2434 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2435 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2437 bool X86::isMOVHPMask(ShuffleVectorSDNode *N) {
2438 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2440 if (NumElems != 2 && NumElems != 4)
2443 for (unsigned i = 0; i < NumElems/2; ++i)
2444 if (!isUndefOrEqual(N->getMaskElt(i), i))
2447 for (unsigned i = 0; i < NumElems/2; ++i)
2448 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2454 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2455 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2457 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2458 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2463 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2464 isUndefOrEqual(N->getMaskElt(1), 3) &&
2465 isUndefOrEqual(N->getMaskElt(2), 2) &&
2466 isUndefOrEqual(N->getMaskElt(3), 3);
2469 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2470 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2471 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, MVT VT,
2472 bool V2IsSplat = false) {
2473 int NumElts = VT.getVectorNumElements();
2474 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2477 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2479 int BitI1 = Mask[i+1];
2480 if (!isUndefOrEqual(BitI, j))
2483 if (!isUndefOrEqual(BitI1, NumElts))
2486 if (!isUndefOrEqual(BitI1, j + NumElts))
2493 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2494 SmallVector<int, 8> M;
2496 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2499 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2500 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2501 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, MVT VT,
2502 bool V2IsSplat = false) {
2503 int NumElts = VT.getVectorNumElements();
2504 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2507 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2509 int BitI1 = Mask[i+1];
2510 if (!isUndefOrEqual(BitI, j + NumElts/2))
2513 if (isUndefOrEqual(BitI1, NumElts))
2516 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2523 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2524 SmallVector<int, 8> M;
2526 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2529 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2530 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2532 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) {
2533 int NumElems = VT.getVectorNumElements();
2534 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2537 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2539 int BitI1 = Mask[i+1];
2540 if (!isUndefOrEqual(BitI, j))
2542 if (!isUndefOrEqual(BitI1, j))
2548 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2549 SmallVector<int, 8> M;
2551 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2554 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2555 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2557 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) {
2558 int NumElems = VT.getVectorNumElements();
2559 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2562 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2564 int BitI1 = Mask[i+1];
2565 if (!isUndefOrEqual(BitI, j))
2567 if (!isUndefOrEqual(BitI1, j))
2573 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2574 SmallVector<int, 8> M;
2576 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2579 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2580 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2581 /// MOVSD, and MOVD, i.e. setting the lowest element.
2582 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2583 if (VT.getVectorElementType().getSizeInBits() < 32)
2586 int NumElts = VT.getVectorNumElements();
2588 if (!isUndefOrEqual(Mask[0], NumElts))
2591 for (int i = 1; i < NumElts; ++i)
2592 if (!isUndefOrEqual(Mask[i], i))
2598 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2599 SmallVector<int, 8> M;
2601 return ::isMOVLMask(M, N->getValueType(0));
2604 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2605 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2606 /// element of vector 2 and the other elements to come from vector 1 in order.
2607 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT,
2608 bool V2IsSplat = false, bool V2IsUndef = false) {
2609 int NumOps = VT.getVectorNumElements();
2610 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2613 if (!isUndefOrEqual(Mask[0], 0))
2616 for (int i = 1; i < NumOps; ++i)
2617 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2618 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2619 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2625 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2626 bool V2IsUndef = false) {
2627 SmallVector<int, 8> M;
2629 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2632 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2633 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2634 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2635 if (N->getValueType(0).getVectorNumElements() != 4)
2638 // Expect 1, 1, 3, 3
2639 for (unsigned i = 0; i < 2; ++i) {
2640 int Elt = N->getMaskElt(i);
2641 if (Elt >= 0 && Elt != 1)
2646 for (unsigned i = 2; i < 4; ++i) {
2647 int Elt = N->getMaskElt(i);
2648 if (Elt >= 0 && Elt != 3)
2653 // Don't use movshdup if it can be done with a shufps.
2654 // FIXME: verify that matching u, u, 3, 3 is what we want.
2658 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2659 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2660 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2661 if (N->getValueType(0).getVectorNumElements() != 4)
2664 // Expect 0, 0, 2, 2
2665 for (unsigned i = 0; i < 2; ++i)
2666 if (N->getMaskElt(i) > 0)
2670 for (unsigned i = 2; i < 4; ++i) {
2671 int Elt = N->getMaskElt(i);
2672 if (Elt >= 0 && Elt != 2)
2677 // Don't use movsldup if it can be done with a shufps.
2681 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2682 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2683 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
2684 int e = N->getValueType(0).getVectorNumElements() / 2;
2686 for (int i = 0; i < e; ++i)
2687 if (!isUndefOrEqual(N->getMaskElt(i), i))
2689 for (int i = 0; i < e; ++i)
2690 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
2695 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2696 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2698 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2699 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2700 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
2702 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2704 for (int i = 0; i < NumOperands; ++i) {
2705 int Val = SVOp->getMaskElt(NumOperands-i-1);
2706 if (Val < 0) Val = 0;
2707 if (Val >= NumOperands) Val -= NumOperands;
2709 if (i != NumOperands - 1)
2715 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2716 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2718 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2719 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2721 // 8 nodes, but we only care about the last 4.
2722 for (unsigned i = 7; i >= 4; --i) {
2723 int Val = SVOp->getMaskElt(i);
2732 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2733 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2735 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2736 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2738 // 8 nodes, but we only care about the first 4.
2739 for (int i = 3; i >= 0; --i) {
2740 int Val = SVOp->getMaskElt(i);
2749 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2751 bool X86::isZeroNode(SDValue Elt) {
2752 return ((isa<ConstantSDNode>(Elt) &&
2753 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2754 (isa<ConstantFPSDNode>(Elt) &&
2755 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2758 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
2759 /// their permute mask.
2760 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
2761 SelectionDAG &DAG) {
2762 MVT VT = SVOp->getValueType(0);
2763 unsigned NumElems = VT.getVectorNumElements();
2764 SmallVector<int, 8> MaskVec;
2766 for (unsigned i = 0; i != NumElems; ++i) {
2767 int idx = SVOp->getMaskElt(i);
2769 MaskVec.push_back(idx);
2770 else if (idx < (int)NumElems)
2771 MaskVec.push_back(idx + NumElems);
2773 MaskVec.push_back(idx - NumElems);
2775 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
2776 SVOp->getOperand(0), &MaskVec[0]);
2779 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2780 /// the two vector operands have swapped position.
2781 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, MVT VT) {
2782 unsigned NumElems = VT.getVectorNumElements();
2783 for (unsigned i = 0; i != NumElems; ++i) {
2787 else if (idx < (int)NumElems)
2788 Mask[i] = idx + NumElems;
2790 Mask[i] = idx - NumElems;
2794 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2795 /// match movhlps. The lower half elements should come from upper half of
2796 /// V1 (and in order), and the upper half elements should come from the upper
2797 /// half of V2 (and in order).
2798 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
2799 if (Op->getValueType(0).getVectorNumElements() != 4)
2801 for (unsigned i = 0, e = 2; i != e; ++i)
2802 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
2804 for (unsigned i = 2; i != 4; ++i)
2805 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
2810 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2811 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2813 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2814 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2816 N = N->getOperand(0).getNode();
2817 if (!ISD::isNON_EXTLoad(N))
2820 *LD = cast<LoadSDNode>(N);
2824 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2825 /// match movlp{s|d}. The lower half elements should come from lower half of
2826 /// V1 (and in order), and the upper half elements should come from the upper
2827 /// half of V2 (and in order). And since V1 will become the source of the
2828 /// MOVLP, it must be either a vector load or a scalar load to vector.
2829 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
2830 ShuffleVectorSDNode *Op) {
2831 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2833 // Is V2 is a vector load, don't do this transformation. We will try to use
2834 // load folding shufps op.
2835 if (ISD::isNON_EXTLoad(V2))
2838 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
2840 if (NumElems != 2 && NumElems != 4)
2842 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2843 if (!isUndefOrEqual(Op->getMaskElt(i), i))
2845 for (unsigned i = NumElems/2; i != NumElems; ++i)
2846 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
2851 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2853 static bool isSplatVector(SDNode *N) {
2854 if (N->getOpcode() != ISD::BUILD_VECTOR)
2857 SDValue SplatValue = N->getOperand(0);
2858 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2859 if (N->getOperand(i) != SplatValue)
2864 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2865 /// to an zero vector.
2866 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
2867 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
2868 SDValue V1 = N->getOperand(0);
2869 SDValue V2 = N->getOperand(1);
2870 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2871 for (unsigned i = 0; i != NumElems; ++i) {
2872 int Idx = N->getMaskElt(i);
2873 if (Idx >= (int)NumElems) {
2874 unsigned Opc = V2.getOpcode();
2875 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2877 if (Opc != ISD::BUILD_VECTOR ||
2878 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
2880 } else if (Idx >= 0) {
2881 unsigned Opc = V1.getOpcode();
2882 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2884 if (Opc != ISD::BUILD_VECTOR ||
2885 !X86::isZeroNode(V1.getOperand(Idx)))
2892 /// getZeroVector - Returns a vector of specified type with all zero elements.
2894 static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG,
2896 assert(VT.isVector() && "Expected a vector type");
2898 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2899 // type. This ensures they get CSE'd.
2901 if (VT.getSizeInBits() == 64) { // MMX
2902 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2903 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2904 } else if (HasSSE2) { // SSE2
2905 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2906 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2908 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2909 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
2911 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2914 /// getOnesVector - Returns a vector of specified type with all bits set.
2916 static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
2917 assert(VT.isVector() && "Expected a vector type");
2919 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2920 // type. This ensures they get CSE'd.
2921 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2923 if (VT.getSizeInBits() == 64) // MMX
2924 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2926 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2927 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2931 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2932 /// that point to V2 points to its first element.
2933 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
2934 MVT VT = SVOp->getValueType(0);
2935 unsigned NumElems = VT.getVectorNumElements();
2937 bool Changed = false;
2938 SmallVector<int, 8> MaskVec;
2939 SVOp->getMask(MaskVec);
2941 for (unsigned i = 0; i != NumElems; ++i) {
2942 if (MaskVec[i] > (int)NumElems) {
2943 MaskVec[i] = NumElems;
2948 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
2949 SVOp->getOperand(1), &MaskVec[0]);
2950 return SDValue(SVOp, 0);
2953 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2954 /// operation of specified width.
2955 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
2957 unsigned NumElems = VT.getVectorNumElements();
2958 SmallVector<int, 8> Mask;
2959 Mask.push_back(NumElems);
2960 for (unsigned i = 1; i != NumElems; ++i)
2962 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2965 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
2966 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
2968 unsigned NumElems = VT.getVectorNumElements();
2969 SmallVector<int, 8> Mask;
2970 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2972 Mask.push_back(i + NumElems);
2974 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2977 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
2978 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
2980 unsigned NumElems = VT.getVectorNumElements();
2981 unsigned Half = NumElems/2;
2982 SmallVector<int, 8> Mask;
2983 for (unsigned i = 0; i != Half; ++i) {
2984 Mask.push_back(i + Half);
2985 Mask.push_back(i + NumElems + Half);
2987 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2990 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
2991 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
2993 if (SV->getValueType(0).getVectorNumElements() <= 4)
2994 return SDValue(SV, 0);
2996 MVT PVT = MVT::v4f32;
2997 MVT VT = SV->getValueType(0);
2998 DebugLoc dl = SV->getDebugLoc();
2999 SDValue V1 = SV->getOperand(0);
3000 int NumElems = VT.getVectorNumElements();
3001 int EltNo = SV->getSplatIndex();
3003 // unpack elements to the correct location
3004 while (NumElems > 4) {
3005 if (EltNo < NumElems/2) {
3006 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3008 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3009 EltNo -= NumElems/2;
3014 // Perform the splat.
3015 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3016 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3017 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3018 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3021 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3022 /// vector of zero or undef vector. This produces a shuffle where the low
3023 /// element of V2 is swizzled into the zero/undef vector, landing at element
3024 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3025 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3026 bool isZero, bool HasSSE2,
3027 SelectionDAG &DAG) {
3028 MVT VT = V2.getValueType();
3030 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3031 unsigned NumElems = VT.getVectorNumElements();
3032 SmallVector<int, 16> MaskVec;
3033 for (unsigned i = 0; i != NumElems; ++i)
3034 // If this is the insertion idx, put the low elt of V2 here.
3035 MaskVec.push_back(i == Idx ? NumElems : i);
3036 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3039 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3040 /// a shuffle that is zero.
3042 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3043 bool Low, SelectionDAG &DAG) {
3044 unsigned NumZeros = 0;
3045 for (int i = 0; i < NumElems; ++i) {
3046 unsigned Index = Low ? i : NumElems-i-1;
3047 int Idx = SVOp->getMaskElt(Index);
3052 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3053 if (Elt.getNode() && X86::isZeroNode(Elt))
3061 /// isVectorShift - Returns true if the shuffle can be implemented as a
3062 /// logical left or right shift of a vector.
3063 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3064 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3065 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3066 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3069 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3072 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3076 bool SeenV1 = false;
3077 bool SeenV2 = false;
3078 for (int i = NumZeros; i < NumElems; ++i) {
3079 int Val = isLeft ? (i - NumZeros) : i;
3080 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3092 if (SeenV1 && SeenV2)
3095 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3101 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3103 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3104 unsigned NumNonZero, unsigned NumZero,
3105 SelectionDAG &DAG, TargetLowering &TLI) {
3109 DebugLoc dl = Op.getDebugLoc();
3112 for (unsigned i = 0; i < 16; ++i) {
3113 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3114 if (ThisIsNonZero && First) {
3116 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3118 V = DAG.getUNDEF(MVT::v8i16);
3123 SDValue ThisElt(0, 0), LastElt(0, 0);
3124 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3125 if (LastIsNonZero) {
3126 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3127 MVT::i16, Op.getOperand(i-1));
3129 if (ThisIsNonZero) {
3130 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3131 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3132 ThisElt, DAG.getConstant(8, MVT::i8));
3134 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3138 if (ThisElt.getNode())
3139 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3140 DAG.getIntPtrConstant(i/2));
3144 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3147 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3149 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3150 unsigned NumNonZero, unsigned NumZero,
3151 SelectionDAG &DAG, TargetLowering &TLI) {
3155 DebugLoc dl = Op.getDebugLoc();
3158 for (unsigned i = 0; i < 8; ++i) {
3159 bool isNonZero = (NonZeros & (1 << i)) != 0;
3163 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3165 V = DAG.getUNDEF(MVT::v8i16);
3168 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3169 MVT::v8i16, V, Op.getOperand(i),
3170 DAG.getIntPtrConstant(i));
3177 /// getVShift - Return a vector logical shift node.
3179 static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
3180 unsigned NumBits, SelectionDAG &DAG,
3181 const TargetLowering &TLI, DebugLoc dl) {
3182 bool isMMX = VT.getSizeInBits() == 64;
3183 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3184 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3185 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3186 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3187 DAG.getNode(Opc, dl, ShVT, SrcOp,
3188 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3192 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3193 DebugLoc dl = Op.getDebugLoc();
3194 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3195 if (ISD::isBuildVectorAllZeros(Op.getNode())
3196 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3197 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3198 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3199 // eliminated on x86-32 hosts.
3200 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3203 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3204 return getOnesVector(Op.getValueType(), DAG, dl);
3205 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3208 MVT VT = Op.getValueType();
3209 MVT EVT = VT.getVectorElementType();
3210 unsigned EVTBits = EVT.getSizeInBits();
3212 unsigned NumElems = Op.getNumOperands();
3213 unsigned NumZero = 0;
3214 unsigned NumNonZero = 0;
3215 unsigned NonZeros = 0;
3216 bool IsAllConstants = true;
3217 SmallSet<SDValue, 8> Values;
3218 for (unsigned i = 0; i < NumElems; ++i) {
3219 SDValue Elt = Op.getOperand(i);
3220 if (Elt.getOpcode() == ISD::UNDEF)
3223 if (Elt.getOpcode() != ISD::Constant &&
3224 Elt.getOpcode() != ISD::ConstantFP)
3225 IsAllConstants = false;
3226 if (X86::isZeroNode(Elt))
3229 NonZeros |= (1 << i);
3234 if (NumNonZero == 0) {
3235 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3236 return DAG.getUNDEF(VT);
3239 // Special case for single non-zero, non-undef, element.
3240 if (NumNonZero == 1) {
3241 unsigned Idx = CountTrailingZeros_32(NonZeros);
3242 SDValue Item = Op.getOperand(Idx);
3244 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3245 // the value are obviously zero, truncate the value to i32 and do the
3246 // insertion that way. Only do this if the value is non-constant or if the
3247 // value is a constant being inserted into element 0. It is cheaper to do
3248 // a constant pool load than it is to do a movd + shuffle.
3249 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3250 (!IsAllConstants || Idx == 0)) {
3251 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3252 // Handle MMX and SSE both.
3253 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3254 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3256 // Truncate the value (which may itself be a constant) to i32, and
3257 // convert it to a vector with movd (S2V+shuffle to zero extend).
3258 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3259 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3260 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3261 Subtarget->hasSSE2(), DAG);
3263 // Now we have our 32-bit value zero extended in the low element of
3264 // a vector. If Idx != 0, swizzle it into place.
3266 SmallVector<int, 4> Mask;
3267 Mask.push_back(Idx);
3268 for (unsigned i = 1; i != VecElts; ++i)
3270 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3271 DAG.getUNDEF(Item.getValueType()),
3274 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3278 // If we have a constant or non-constant insertion into the low element of
3279 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3280 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3281 // depending on what the source datatype is.
3284 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3285 } else if (EVT == MVT::i32 || EVT == MVT::f32 || EVT == MVT::f64 ||
3286 (EVT == MVT::i64 && Subtarget->is64Bit())) {
3287 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3288 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3289 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3291 } else if (EVT == MVT::i16 || EVT == MVT::i8) {
3292 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3293 MVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3294 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3295 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3296 Subtarget->hasSSE2(), DAG);
3297 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3301 // Is it a vector logical left shift?
3302 if (NumElems == 2 && Idx == 1 &&
3303 X86::isZeroNode(Op.getOperand(0)) &&
3304 !X86::isZeroNode(Op.getOperand(1))) {
3305 unsigned NumBits = VT.getSizeInBits();
3306 return getVShift(true, VT,
3307 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3308 VT, Op.getOperand(1)),
3309 NumBits/2, DAG, *this, dl);
3312 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3315 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3316 // is a non-constant being inserted into an element other than the low one,
3317 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3318 // movd/movss) to move this into the low element, then shuffle it into
3320 if (EVTBits == 32) {
3321 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3323 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3324 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3325 Subtarget->hasSSE2(), DAG);
3326 SmallVector<int, 8> MaskVec;
3327 for (unsigned i = 0; i < NumElems; i++)
3328 MaskVec.push_back(i == Idx ? 0 : 1);
3329 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3333 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3334 if (Values.size() == 1)
3337 // A vector full of immediates; various special cases are already
3338 // handled, so this is best done with a single constant-pool load.
3342 // Let legalizer expand 2-wide build_vectors.
3343 if (EVTBits == 64) {
3344 if (NumNonZero == 1) {
3345 // One half is zero or undef.
3346 unsigned Idx = CountTrailingZeros_32(NonZeros);
3347 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3348 Op.getOperand(Idx));
3349 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3350 Subtarget->hasSSE2(), DAG);
3355 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3356 if (EVTBits == 8 && NumElems == 16) {
3357 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3359 if (V.getNode()) return V;
3362 if (EVTBits == 16 && NumElems == 8) {
3363 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3365 if (V.getNode()) return V;
3368 // If element VT is == 32 bits, turn it into a number of shuffles.
3369 SmallVector<SDValue, 8> V;
3371 if (NumElems == 4 && NumZero > 0) {
3372 for (unsigned i = 0; i < 4; ++i) {
3373 bool isZero = !(NonZeros & (1 << i));
3375 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3377 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3380 for (unsigned i = 0; i < 2; ++i) {
3381 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3384 V[i] = V[i*2]; // Must be a zero vector.
3387 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3390 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3393 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3398 SmallVector<int, 8> MaskVec;
3399 bool Reverse = (NonZeros & 0x3) == 2;
3400 for (unsigned i = 0; i < 2; ++i)
3401 MaskVec.push_back(Reverse ? 1-i : i);
3402 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3403 for (unsigned i = 0; i < 2; ++i)
3404 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3405 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3408 if (Values.size() > 2) {
3409 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3410 // values to be inserted is equal to the number of elements, in which case
3411 // use the unpack code below in the hopes of matching the consecutive elts
3412 // load merge pattern for shuffles.
3413 // FIXME: We could probably just check that here directly.
3414 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3415 getSubtarget()->hasSSE41()) {
3416 V[0] = DAG.getUNDEF(VT);
3417 for (unsigned i = 0; i < NumElems; ++i)
3418 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3419 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3420 Op.getOperand(i), DAG.getIntPtrConstant(i));
3423 // Expand into a number of unpckl*.
3425 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3426 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3427 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3428 for (unsigned i = 0; i < NumElems; ++i)
3429 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3431 while (NumElems != 0) {
3432 for (unsigned i = 0; i < NumElems; ++i)
3433 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3442 // v8i16 shuffles - Prefer shuffles in the following order:
3443 // 1. [all] pshuflw, pshufhw, optional move
3444 // 2. [ssse3] 1 x pshufb
3445 // 3. [ssse3] 2 x pshufb + 1 x por
3446 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3448 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3449 SelectionDAG &DAG, X86TargetLowering &TLI) {
3450 SDValue V1 = SVOp->getOperand(0);
3451 SDValue V2 = SVOp->getOperand(1);
3452 DebugLoc dl = SVOp->getDebugLoc();
3453 SmallVector<int, 8> MaskVals;
3455 // Determine if more than 1 of the words in each of the low and high quadwords
3456 // of the result come from the same quadword of one of the two inputs. Undef
3457 // mask values count as coming from any quadword, for better codegen.
3458 SmallVector<unsigned, 4> LoQuad(4);
3459 SmallVector<unsigned, 4> HiQuad(4);
3460 BitVector InputQuads(4);
3461 for (unsigned i = 0; i < 8; ++i) {
3462 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3463 int EltIdx = SVOp->getMaskElt(i);
3464 MaskVals.push_back(EltIdx);
3473 InputQuads.set(EltIdx / 4);
3476 int BestLoQuad = -1;
3477 unsigned MaxQuad = 1;
3478 for (unsigned i = 0; i < 4; ++i) {
3479 if (LoQuad[i] > MaxQuad) {
3481 MaxQuad = LoQuad[i];
3485 int BestHiQuad = -1;
3487 for (unsigned i = 0; i < 4; ++i) {
3488 if (HiQuad[i] > MaxQuad) {
3490 MaxQuad = HiQuad[i];
3494 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3495 // of the two input vectors, shuffle them into one input vector so only a
3496 // single pshufb instruction is necessary. If There are more than 2 input
3497 // quads, disable the next transformation since it does not help SSSE3.
3498 bool V1Used = InputQuads[0] || InputQuads[1];
3499 bool V2Used = InputQuads[2] || InputQuads[3];
3500 if (TLI.getSubtarget()->hasSSSE3()) {
3501 if (InputQuads.count() == 2 && V1Used && V2Used) {
3502 BestLoQuad = InputQuads.find_first();
3503 BestHiQuad = InputQuads.find_next(BestLoQuad);
3505 if (InputQuads.count() > 2) {
3511 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3512 // the shuffle mask. If a quad is scored as -1, that means that it contains
3513 // words from all 4 input quadwords.
3515 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3516 SmallVector<int, 8> MaskV;
3517 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3518 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3519 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3520 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3521 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3522 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3524 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3525 // source words for the shuffle, to aid later transformations.
3526 bool AllWordsInNewV = true;
3527 bool InOrder[2] = { true, true };
3528 for (unsigned i = 0; i != 8; ++i) {
3529 int idx = MaskVals[i];
3531 InOrder[i/4] = false;
3532 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3534 AllWordsInNewV = false;
3538 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3539 if (AllWordsInNewV) {
3540 for (int i = 0; i != 8; ++i) {
3541 int idx = MaskVals[i];
3544 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3545 if ((idx != i) && idx < 4)
3547 if ((idx != i) && idx > 3)
3556 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3557 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3558 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3559 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
3560 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
3564 // If we have SSSE3, and all words of the result are from 1 input vector,
3565 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
3566 // is present, fall back to case 4.
3567 if (TLI.getSubtarget()->hasSSSE3()) {
3568 SmallVector<SDValue,16> pshufbMask;
3570 // If we have elements from both input vectors, set the high bit of the
3571 // shuffle mask element to zero out elements that come from V2 in the V1
3572 // mask, and elements that come from V1 in the V2 mask, so that the two
3573 // results can be OR'd together.
3574 bool TwoInputs = V1Used && V2Used;
3575 for (unsigned i = 0; i != 8; ++i) {
3576 int EltIdx = MaskVals[i] * 2;
3577 if (TwoInputs && (EltIdx >= 16)) {
3578 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3579 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3582 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3583 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
3585 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
3586 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3587 DAG.getNode(ISD::BUILD_VECTOR, dl,
3588 MVT::v16i8, &pshufbMask[0], 16));
3590 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3592 // Calculate the shuffle mask for the second input, shuffle it, and
3593 // OR it with the first shuffled input.
3595 for (unsigned i = 0; i != 8; ++i) {
3596 int EltIdx = MaskVals[i] * 2;
3598 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3599 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3602 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3603 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
3605 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
3606 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3607 DAG.getNode(ISD::BUILD_VECTOR, dl,
3608 MVT::v16i8, &pshufbMask[0], 16));
3609 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3610 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3613 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
3614 // and update MaskVals with new element order.
3615 BitVector InOrder(8);
3616 if (BestLoQuad >= 0) {
3617 SmallVector<int, 8> MaskV;
3618 for (int i = 0; i != 4; ++i) {
3619 int idx = MaskVals[i];
3621 MaskV.push_back(-1);
3623 } else if ((idx / 4) == BestLoQuad) {
3624 MaskV.push_back(idx & 3);
3627 MaskV.push_back(-1);
3630 for (unsigned i = 4; i != 8; ++i)
3632 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3636 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
3637 // and update MaskVals with the new element order.
3638 if (BestHiQuad >= 0) {
3639 SmallVector<int, 8> MaskV;
3640 for (unsigned i = 0; i != 4; ++i)
3642 for (unsigned i = 4; i != 8; ++i) {
3643 int idx = MaskVals[i];
3645 MaskV.push_back(-1);
3647 } else if ((idx / 4) == BestHiQuad) {
3648 MaskV.push_back((idx & 3) + 4);
3651 MaskV.push_back(-1);
3654 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3658 // In case BestHi & BestLo were both -1, which means each quadword has a word
3659 // from each of the four input quadwords, calculate the InOrder bitvector now
3660 // before falling through to the insert/extract cleanup.
3661 if (BestLoQuad == -1 && BestHiQuad == -1) {
3663 for (int i = 0; i != 8; ++i)
3664 if (MaskVals[i] < 0 || MaskVals[i] == i)
3668 // The other elements are put in the right place using pextrw and pinsrw.
3669 for (unsigned i = 0; i != 8; ++i) {
3672 int EltIdx = MaskVals[i];
3675 SDValue ExtOp = (EltIdx < 8)
3676 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3677 DAG.getIntPtrConstant(EltIdx))
3678 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3679 DAG.getIntPtrConstant(EltIdx - 8));
3680 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3681 DAG.getIntPtrConstant(i));
3686 // v16i8 shuffles - Prefer shuffles in the following order:
3687 // 1. [ssse3] 1 x pshufb
3688 // 2. [ssse3] 2 x pshufb + 1 x por
3689 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
3691 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
3692 SelectionDAG &DAG, X86TargetLowering &TLI) {
3693 SDValue V1 = SVOp->getOperand(0);
3694 SDValue V2 = SVOp->getOperand(1);
3695 DebugLoc dl = SVOp->getDebugLoc();
3696 SmallVector<int, 16> MaskVals;
3697 SVOp->getMask(MaskVals);
3699 // If we have SSSE3, case 1 is generated when all result bytes come from
3700 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
3701 // present, fall back to case 3.
3702 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
3705 for (unsigned i = 0; i < 16; ++i) {
3706 int EltIdx = MaskVals[i];
3715 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
3716 if (TLI.getSubtarget()->hasSSSE3()) {
3717 SmallVector<SDValue,16> pshufbMask;
3719 // If all result elements are from one input vector, then only translate
3720 // undef mask values to 0x80 (zero out result) in the pshufb mask.
3722 // Otherwise, we have elements from both input vectors, and must zero out
3723 // elements that come from V2 in the first mask, and V1 in the second mask
3724 // so that we can OR them together.
3725 bool TwoInputs = !(V1Only || V2Only);
3726 for (unsigned i = 0; i != 16; ++i) {
3727 int EltIdx = MaskVals[i];
3728 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
3729 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3732 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3734 // If all the elements are from V2, assign it to V1 and return after
3735 // building the first pshufb.
3738 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3739 DAG.getNode(ISD::BUILD_VECTOR, dl,
3740 MVT::v16i8, &pshufbMask[0], 16));
3744 // Calculate the shuffle mask for the second input, shuffle it, and
3745 // OR it with the first shuffled input.
3747 for (unsigned i = 0; i != 16; ++i) {
3748 int EltIdx = MaskVals[i];
3750 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3753 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3755 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3756 DAG.getNode(ISD::BUILD_VECTOR, dl,
3757 MVT::v16i8, &pshufbMask[0], 16));
3758 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3761 // No SSSE3 - Calculate in place words and then fix all out of place words
3762 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
3763 // the 16 different words that comprise the two doublequadword input vectors.
3764 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3765 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
3766 SDValue NewV = V2Only ? V2 : V1;
3767 for (int i = 0; i != 8; ++i) {
3768 int Elt0 = MaskVals[i*2];
3769 int Elt1 = MaskVals[i*2+1];
3771 // This word of the result is all undef, skip it.
3772 if (Elt0 < 0 && Elt1 < 0)
3775 // This word of the result is already in the correct place, skip it.
3776 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
3778 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
3781 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
3782 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
3785 // If Elt0 and Elt1 are defined, are consecutive, and can be load
3786 // using a single extract together, load it and store it.
3787 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
3788 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3789 DAG.getIntPtrConstant(Elt1 / 2));
3790 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3791 DAG.getIntPtrConstant(i));
3795 // If Elt1 is defined, extract it from the appropriate source. If the
3796 // source byte is not also odd, shift the extracted word left 8 bits
3797 // otherwise clear the bottom 8 bits if we need to do an or.
3799 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3800 DAG.getIntPtrConstant(Elt1 / 2));
3801 if ((Elt1 & 1) == 0)
3802 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
3803 DAG.getConstant(8, TLI.getShiftAmountTy()));
3805 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
3806 DAG.getConstant(0xFF00, MVT::i16));
3808 // If Elt0 is defined, extract it from the appropriate source. If the
3809 // source byte is not also even, shift the extracted word right 8 bits. If
3810 // Elt1 was also defined, OR the extracted values together before
3811 // inserting them in the result.
3813 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
3814 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
3815 if ((Elt0 & 1) != 0)
3816 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
3817 DAG.getConstant(8, TLI.getShiftAmountTy()));
3819 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
3820 DAG.getConstant(0x00FF, MVT::i16));
3821 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
3824 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3825 DAG.getIntPtrConstant(i));
3827 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
3830 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3831 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3832 /// done when every pair / quad of shuffle mask elements point to elements in
3833 /// the right sequence. e.g.
3834 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3836 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
3838 TargetLowering &TLI, DebugLoc dl) {
3839 MVT VT = SVOp->getValueType(0);
3840 SDValue V1 = SVOp->getOperand(0);
3841 SDValue V2 = SVOp->getOperand(1);
3842 unsigned NumElems = VT.getVectorNumElements();
3843 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3844 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3845 MVT MaskEltVT = MaskVT.getVectorElementType();
3847 switch (VT.getSimpleVT()) {
3848 default: assert(false && "Unexpected!");
3849 case MVT::v4f32: NewVT = MVT::v2f64; break;
3850 case MVT::v4i32: NewVT = MVT::v2i64; break;
3851 case MVT::v8i16: NewVT = MVT::v4i32; break;
3852 case MVT::v16i8: NewVT = MVT::v4i32; break;
3855 if (NewWidth == 2) {
3861 int Scale = NumElems / NewWidth;
3862 SmallVector<int, 8> MaskVec;
3863 for (unsigned i = 0; i < NumElems; i += Scale) {
3865 for (int j = 0; j < Scale; ++j) {
3866 int EltIdx = SVOp->getMaskElt(i+j);
3870 StartIdx = EltIdx - (EltIdx % Scale);
3871 if (EltIdx != StartIdx + j)
3875 MaskVec.push_back(-1);
3877 MaskVec.push_back(StartIdx / Scale);
3880 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
3881 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
3882 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
3885 /// getVZextMovL - Return a zero-extending vector move low node.
3887 static SDValue getVZextMovL(MVT VT, MVT OpVT,
3888 SDValue SrcOp, SelectionDAG &DAG,
3889 const X86Subtarget *Subtarget, DebugLoc dl) {
3890 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3891 LoadSDNode *LD = NULL;
3892 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
3893 LD = dyn_cast<LoadSDNode>(SrcOp);
3895 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3897 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3898 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3899 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3900 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3901 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3903 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3904 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3905 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
3906 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3914 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3915 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
3916 DAG.getNode(ISD::BIT_CONVERT, dl,
3920 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3923 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3924 SDValue V1 = SVOp->getOperand(0);
3925 SDValue V2 = SVOp->getOperand(1);
3926 DebugLoc dl = SVOp->getDebugLoc();
3927 MVT VT = SVOp->getValueType(0);
3929 SmallVector<std::pair<int, int>, 8> Locs;
3931 SmallVector<int, 8> Mask1(4U, -1);
3932 SmallVector<int, 8> PermMask;
3933 SVOp->getMask(PermMask);
3937 for (unsigned i = 0; i != 4; ++i) {
3938 int Idx = PermMask[i];
3940 Locs[i] = std::make_pair(-1, -1);
3942 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
3944 Locs[i] = std::make_pair(0, NumLo);
3948 Locs[i] = std::make_pair(1, NumHi);
3950 Mask1[2+NumHi] = Idx;
3956 if (NumLo <= 2 && NumHi <= 2) {
3957 // If no more than two elements come from either vector. This can be
3958 // implemented with two shuffles. First shuffle gather the elements.
3959 // The second shuffle, which takes the first shuffle as both of its
3960 // vector operands, put the elements into the right order.
3961 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
3963 SmallVector<int, 8> Mask2(4U, -1);
3965 for (unsigned i = 0; i != 4; ++i) {
3966 if (Locs[i].first == -1)
3969 unsigned Idx = (i < 2) ? 0 : 4;
3970 Idx += Locs[i].first * 2 + Locs[i].second;
3975 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
3976 } else if (NumLo == 3 || NumHi == 3) {
3977 // Otherwise, we must have three elements from one vector, call it X, and
3978 // one element from the other, call it Y. First, use a shufps to build an
3979 // intermediate vector with the one element from Y and the element from X
3980 // that will be in the same half in the final destination (the indexes don't
3981 // matter). Then, use a shufps to build the final vector, taking the half
3982 // containing the element from Y from the intermediate, and the other half
3985 // Normalize it so the 3 elements come from V1.
3986 CommuteVectorShuffleMask(PermMask, VT);
3990 // Find the element from V2.
3992 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
3993 int Val = PermMask[HiIndex];
4000 Mask1[0] = PermMask[HiIndex];
4002 Mask1[2] = PermMask[HiIndex^1];
4004 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4007 Mask1[0] = PermMask[0];
4008 Mask1[1] = PermMask[1];
4009 Mask1[2] = HiIndex & 1 ? 6 : 4;
4010 Mask1[3] = HiIndex & 1 ? 4 : 6;
4011 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4013 Mask1[0] = HiIndex & 1 ? 2 : 0;
4014 Mask1[1] = HiIndex & 1 ? 0 : 2;
4015 Mask1[2] = PermMask[2];
4016 Mask1[3] = PermMask[3];
4021 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4025 // Break it into (shuffle shuffle_hi, shuffle_lo).
4027 SmallVector<int,8> LoMask(4U, -1);
4028 SmallVector<int,8> HiMask(4U, -1);
4030 SmallVector<int,8> *MaskPtr = &LoMask;
4031 unsigned MaskIdx = 0;
4034 for (unsigned i = 0; i != 4; ++i) {
4041 int Idx = PermMask[i];
4043 Locs[i] = std::make_pair(-1, -1);
4044 } else if (Idx < 4) {
4045 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4046 (*MaskPtr)[LoIdx] = Idx;
4049 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4050 (*MaskPtr)[HiIdx] = Idx;
4055 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4056 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4057 SmallVector<int, 8> MaskOps;
4058 for (unsigned i = 0; i != 4; ++i) {
4059 if (Locs[i].first == -1) {
4060 MaskOps.push_back(-1);
4062 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4063 MaskOps.push_back(Idx);
4066 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4070 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4071 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4072 SDValue V1 = Op.getOperand(0);
4073 SDValue V2 = Op.getOperand(1);
4074 MVT VT = Op.getValueType();
4075 DebugLoc dl = Op.getDebugLoc();
4076 unsigned NumElems = VT.getVectorNumElements();
4077 bool isMMX = VT.getSizeInBits() == 64;
4078 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4079 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4080 bool V1IsSplat = false;
4081 bool V2IsSplat = false;
4083 if (isZeroShuffle(SVOp))
4084 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4086 // Promote splats to v4f32.
4087 if (SVOp->isSplat()) {
4088 if (isMMX || NumElems < 4)
4090 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4093 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4095 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4096 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4097 if (NewOp.getNode())
4098 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4099 LowerVECTOR_SHUFFLE(NewOp, DAG));
4100 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4101 // FIXME: Figure out a cleaner way to do this.
4102 // Try to make use of movq to zero out the top part.
4103 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4104 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4105 if (NewOp.getNode()) {
4106 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4107 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4108 DAG, Subtarget, dl);
4110 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4111 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4112 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4113 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4114 DAG, Subtarget, dl);
4118 if (X86::isPSHUFDMask(SVOp))
4121 // Check if this can be converted into a logical shift.
4122 bool isLeft = false;
4125 bool isShift = getSubtarget()->hasSSE2() &&
4126 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4127 if (isShift && ShVal.hasOneUse()) {
4128 // If the shifted value has multiple uses, it may be cheaper to use
4129 // v_set0 + movlhps or movhlps, etc.
4130 MVT EVT = VT.getVectorElementType();
4131 ShAmt *= EVT.getSizeInBits();
4132 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4135 if (X86::isMOVLMask(SVOp)) {
4138 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4139 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4144 // FIXME: fold these into legal mask.
4145 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4146 X86::isMOVSLDUPMask(SVOp) ||
4147 X86::isMOVHLPSMask(SVOp) ||
4148 X86::isMOVHPMask(SVOp) ||
4149 X86::isMOVLPMask(SVOp)))
4152 if (ShouldXformToMOVHLPS(SVOp) ||
4153 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4154 return CommuteVectorShuffle(SVOp, DAG);
4157 // No better options. Use a vshl / vsrl.
4158 MVT EVT = VT.getVectorElementType();
4159 ShAmt *= EVT.getSizeInBits();
4160 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4163 bool Commuted = false;
4164 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4165 // 1,1,1,1 -> v8i16 though.
4166 V1IsSplat = isSplatVector(V1.getNode());
4167 V2IsSplat = isSplatVector(V2.getNode());
4169 // Canonicalize the splat or undef, if present, to be on the RHS.
4170 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4171 Op = CommuteVectorShuffle(SVOp, DAG);
4172 SVOp = cast<ShuffleVectorSDNode>(Op);
4173 V1 = SVOp->getOperand(0);
4174 V2 = SVOp->getOperand(1);
4175 std::swap(V1IsSplat, V2IsSplat);
4176 std::swap(V1IsUndef, V2IsUndef);
4180 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4181 // Shuffling low element of v1 into undef, just return v1.
4184 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4185 // the instruction selector will not match, so get a canonical MOVL with
4186 // swapped operands to undo the commute.
4187 return getMOVL(DAG, dl, VT, V2, V1);
4190 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4191 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4192 X86::isUNPCKLMask(SVOp) ||
4193 X86::isUNPCKHMask(SVOp))
4197 // Normalize mask so all entries that point to V2 points to its first
4198 // element then try to match unpck{h|l} again. If match, return a
4199 // new vector_shuffle with the corrected mask.
4200 SDValue NewMask = NormalizeMask(SVOp, DAG);
4201 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4202 if (NSVOp != SVOp) {
4203 if (X86::isUNPCKLMask(NSVOp, true)) {
4205 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4212 // Commute is back and try unpck* again.
4213 // FIXME: this seems wrong.
4214 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4215 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4216 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4217 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4218 X86::isUNPCKLMask(NewSVOp) ||
4219 X86::isUNPCKHMask(NewSVOp))
4223 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4225 // Normalize the node to match x86 shuffle ops if needed
4226 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4227 return CommuteVectorShuffle(SVOp, DAG);
4229 // Check for legal shuffle and return?
4230 SmallVector<int, 16> PermMask;
4231 SVOp->getMask(PermMask);
4232 if (isShuffleMaskLegal(PermMask, VT))
4235 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4236 if (VT == MVT::v8i16) {
4237 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4238 if (NewOp.getNode())
4242 if (VT == MVT::v16i8) {
4243 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4244 if (NewOp.getNode())
4248 // Handle all 4 wide cases with a number of shuffles except for MMX.
4249 if (NumElems == 4 && !isMMX)
4250 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4256 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4257 SelectionDAG &DAG) {
4258 MVT VT = Op.getValueType();
4259 DebugLoc dl = Op.getDebugLoc();
4260 if (VT.getSizeInBits() == 8) {
4261 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4262 Op.getOperand(0), Op.getOperand(1));
4263 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4264 DAG.getValueType(VT));
4265 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4266 } else if (VT.getSizeInBits() == 16) {
4267 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4268 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4270 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4271 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4272 DAG.getNode(ISD::BIT_CONVERT, dl,
4276 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4277 Op.getOperand(0), Op.getOperand(1));
4278 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4279 DAG.getValueType(VT));
4280 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4281 } else if (VT == MVT::f32) {
4282 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4283 // the result back to FR32 register. It's only worth matching if the
4284 // result has a single use which is a store or a bitcast to i32. And in
4285 // the case of a store, it's not worth it if the index is a constant 0,
4286 // because a MOVSSmr can be used instead, which is smaller and faster.
4287 if (!Op.hasOneUse())
4289 SDNode *User = *Op.getNode()->use_begin();
4290 if ((User->getOpcode() != ISD::STORE ||
4291 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4292 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4293 (User->getOpcode() != ISD::BIT_CONVERT ||
4294 User->getValueType(0) != MVT::i32))
4296 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4297 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4300 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4301 } else if (VT == MVT::i32) {
4302 // ExtractPS works with constant index.
4303 if (isa<ConstantSDNode>(Op.getOperand(1)))
4311 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4312 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4315 if (Subtarget->hasSSE41()) {
4316 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4321 MVT VT = Op.getValueType();
4322 DebugLoc dl = Op.getDebugLoc();
4323 // TODO: handle v16i8.
4324 if (VT.getSizeInBits() == 16) {
4325 SDValue Vec = Op.getOperand(0);
4326 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4328 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4329 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4330 DAG.getNode(ISD::BIT_CONVERT, dl,
4333 // Transform it so it match pextrw which produces a 32-bit result.
4334 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
4335 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT,
4336 Op.getOperand(0), Op.getOperand(1));
4337 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract,
4338 DAG.getValueType(VT));
4339 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4340 } else if (VT.getSizeInBits() == 32) {
4341 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4345 // SHUFPS the element to the lowest double word, then movss.
4346 int Mask[4] = { Idx, -1, -1, -1 };
4347 MVT VVT = Op.getOperand(0).getValueType();
4348 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4349 DAG.getUNDEF(VVT), Mask);
4350 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4351 DAG.getIntPtrConstant(0));
4352 } else if (VT.getSizeInBits() == 64) {
4353 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4354 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4355 // to match extract_elt for f64.
4356 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4360 // UNPCKHPD the element to the lowest double word, then movsd.
4361 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4362 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4363 int Mask[2] = { 1, -1 };
4364 MVT VVT = Op.getOperand(0).getValueType();
4365 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4366 DAG.getUNDEF(VVT), Mask);
4367 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4368 DAG.getIntPtrConstant(0));
4375 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4376 MVT VT = Op.getValueType();
4377 MVT EVT = VT.getVectorElementType();
4378 DebugLoc dl = Op.getDebugLoc();
4380 SDValue N0 = Op.getOperand(0);
4381 SDValue N1 = Op.getOperand(1);
4382 SDValue N2 = Op.getOperand(2);
4384 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4385 isa<ConstantSDNode>(N2)) {
4386 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4388 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4390 if (N1.getValueType() != MVT::i32)
4391 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4392 if (N2.getValueType() != MVT::i32)
4393 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4394 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4395 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4396 // Bits [7:6] of the constant are the source select. This will always be
4397 // zero here. The DAG Combiner may combine an extract_elt index into these
4398 // bits. For example (insert (extract, 3), 2) could be matched by putting
4399 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4400 // Bits [5:4] of the constant are the destination select. This is the
4401 // value of the incoming immediate.
4402 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4403 // combine either bitwise AND or insert of float 0.0 to set these bits.
4404 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4405 // Create this as a scalar to vector..
4406 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4407 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4408 } else if (EVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4409 // PINSR* works with constant index.
4416 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4417 MVT VT = Op.getValueType();
4418 MVT EVT = VT.getVectorElementType();
4420 if (Subtarget->hasSSE41())
4421 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4426 DebugLoc dl = Op.getDebugLoc();
4427 SDValue N0 = Op.getOperand(0);
4428 SDValue N1 = Op.getOperand(1);
4429 SDValue N2 = Op.getOperand(2);
4431 if (EVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4432 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4433 // as its second argument.
4434 if (N1.getValueType() != MVT::i32)
4435 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4436 if (N2.getValueType() != MVT::i32)
4437 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4438 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4444 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4445 DebugLoc dl = Op.getDebugLoc();
4446 if (Op.getValueType() == MVT::v2f32)
4447 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4448 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4449 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4450 Op.getOperand(0))));
4452 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4453 MVT VT = MVT::v2i32;
4454 switch (Op.getValueType().getSimpleVT()) {
4461 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4462 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4465 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4466 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4467 // one of the above mentioned nodes. It has to be wrapped because otherwise
4468 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4469 // be used to form addressing mode. These wrapped nodes will be selected
4472 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4473 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4475 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4477 unsigned char OpFlag = 0;
4478 unsigned WrapperKind = X86ISD::Wrapper;
4480 if (Subtarget->isPICStyleRIPRel() &&
4481 getTargetMachine().getCodeModel() == CodeModel::Small)
4482 WrapperKind = X86ISD::WrapperRIP;
4483 else if (Subtarget->isPICStyleGOT())
4484 OpFlag = X86II::MO_GOTOFF;
4485 else if (Subtarget->isPICStyleStubPIC())
4486 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4488 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4490 CP->getOffset(), OpFlag);
4491 DebugLoc DL = CP->getDebugLoc();
4492 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4493 // With PIC, the address is actually $g + Offset.
4495 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4496 DAG.getNode(X86ISD::GlobalBaseReg,
4497 DebugLoc::getUnknownLoc(), getPointerTy()),
4504 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4505 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4507 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4509 unsigned char OpFlag = 0;
4510 unsigned WrapperKind = X86ISD::Wrapper;
4512 if (Subtarget->isPICStyleRIPRel() &&
4513 getTargetMachine().getCodeModel() == CodeModel::Small)
4514 WrapperKind = X86ISD::WrapperRIP;
4515 else if (Subtarget->isPICStyleGOT())
4516 OpFlag = X86II::MO_GOTOFF;
4517 else if (Subtarget->isPICStyleStubPIC())
4518 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4520 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4522 DebugLoc DL = JT->getDebugLoc();
4523 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4525 // With PIC, the address is actually $g + Offset.
4527 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4528 DAG.getNode(X86ISD::GlobalBaseReg,
4529 DebugLoc::getUnknownLoc(), getPointerTy()),
4537 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4538 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4540 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4542 unsigned char OpFlag = 0;
4543 unsigned WrapperKind = X86ISD::Wrapper;
4544 if (Subtarget->isPICStyleRIPRel() &&
4545 getTargetMachine().getCodeModel() == CodeModel::Small)
4546 WrapperKind = X86ISD::WrapperRIP;
4547 else if (Subtarget->isPICStyleGOT())
4548 OpFlag = X86II::MO_GOTOFF;
4549 else if (Subtarget->isPICStyleStubPIC())
4550 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4552 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
4554 DebugLoc DL = Op.getDebugLoc();
4555 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4558 // With PIC, the address is actually $g + Offset.
4559 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4560 !Subtarget->is64Bit()) {
4561 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4562 DAG.getNode(X86ISD::GlobalBaseReg,
4563 DebugLoc::getUnknownLoc(),
4572 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
4574 SelectionDAG &DAG) const {
4575 // Create the TargetGlobalAddress node, folding in the constant
4576 // offset if it is legal.
4577 unsigned char OpFlags =
4578 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
4580 if (OpFlags == X86II::MO_NO_FLAG && isInt32(Offset)) {
4581 // A direct static reference to a global.
4582 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4585 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
4588 if (Subtarget->isPICStyleRIPRel() &&
4589 getTargetMachine().getCodeModel() == CodeModel::Small)
4590 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4592 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4594 // With PIC, the address is actually $g + Offset.
4595 if (isGlobalRelativeToPICBase(OpFlags)) {
4596 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4597 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4601 // For globals that require a load from a stub to get the address, emit the
4603 if (isGlobalStubReference(OpFlags))
4604 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
4605 PseudoSourceValue::getGOT(), 0);
4607 // If there was a non-zero offset that we didn't fold, create an explicit
4610 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
4611 DAG.getConstant(Offset, getPointerTy()));
4617 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4618 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4619 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4620 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
4624 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
4625 SDValue *InFlag, const MVT PtrVT, unsigned ReturnReg,
4626 unsigned char OperandFlags) {
4627 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4628 DebugLoc dl = GA->getDebugLoc();
4629 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4630 GA->getValueType(0),
4634 SDValue Ops[] = { Chain, TGA, *InFlag };
4635 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
4637 SDValue Ops[] = { Chain, TGA };
4638 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
4640 SDValue Flag = Chain.getValue(1);
4641 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
4644 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4646 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4649 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4650 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
4651 DAG.getNode(X86ISD::GlobalBaseReg,
4652 DebugLoc::getUnknownLoc(),
4654 InFlag = Chain.getValue(1);
4656 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
4659 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4661 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4663 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
4664 X86::RAX, X86II::MO_TLSGD);
4667 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4668 // "local exec" model.
4669 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4670 const MVT PtrVT, TLSModel::Model model,
4672 DebugLoc dl = GA->getDebugLoc();
4673 // Get the Thread Pointer
4674 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
4675 DebugLoc::getUnknownLoc(), PtrVT,
4676 DAG.getRegister(is64Bit? X86::FS : X86::GS,
4679 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
4682 unsigned char OperandFlags = 0;
4683 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
4685 unsigned WrapperKind = X86ISD::Wrapper;
4686 if (model == TLSModel::LocalExec) {
4687 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
4688 } else if (is64Bit) {
4689 assert(model == TLSModel::InitialExec);
4690 OperandFlags = X86II::MO_GOTTPOFF;
4691 WrapperKind = X86ISD::WrapperRIP;
4693 assert(model == TLSModel::InitialExec);
4694 OperandFlags = X86II::MO_INDNTPOFF;
4697 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4699 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4700 GA->getOffset(), OperandFlags);
4701 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
4703 if (model == TLSModel::InitialExec)
4704 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
4705 PseudoSourceValue::getGOT(), 0);
4707 // The address of the thread local variable is the add of the thread
4708 // pointer with the offset of the variable.
4709 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
4713 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4714 // TODO: implement the "local dynamic" model
4715 // TODO: implement the "initial exec"model for pic executables
4716 assert(Subtarget->isTargetELF() &&
4717 "TLS not implemented for non-ELF targets");
4718 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4719 const GlobalValue *GV = GA->getGlobal();
4721 // If GV is an alias then use the aliasee for determining
4722 // thread-localness.
4723 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
4724 GV = GA->resolveAliasedGlobal(false);
4726 TLSModel::Model model = getTLSModel(GV,
4727 getTargetMachine().getRelocationModel());
4730 case TLSModel::GeneralDynamic:
4731 case TLSModel::LocalDynamic: // not implemented
4732 if (Subtarget->is64Bit())
4733 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4734 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4736 case TLSModel::InitialExec:
4737 case TLSModel::LocalExec:
4738 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
4739 Subtarget->is64Bit());
4742 llvm_unreachable("Unreachable");
4747 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4748 /// take a 2 x i32 value to shift plus a shift amount.
4749 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4750 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4751 MVT VT = Op.getValueType();
4752 unsigned VTBits = VT.getSizeInBits();
4753 DebugLoc dl = Op.getDebugLoc();
4754 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4755 SDValue ShOpLo = Op.getOperand(0);
4756 SDValue ShOpHi = Op.getOperand(1);
4757 SDValue ShAmt = Op.getOperand(2);
4758 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
4759 DAG.getConstant(VTBits - 1, MVT::i8))
4760 : DAG.getConstant(0, VT);
4763 if (Op.getOpcode() == ISD::SHL_PARTS) {
4764 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
4765 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4767 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
4768 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
4771 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
4772 DAG.getConstant(VTBits, MVT::i8));
4773 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
4774 AndNode, DAG.getConstant(0, MVT::i8));
4777 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4778 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4779 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4781 if (Op.getOpcode() == ISD::SHL_PARTS) {
4782 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4783 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4785 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4786 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4789 SDValue Ops[2] = { Lo, Hi };
4790 return DAG.getMergeValues(Ops, 2, dl);
4793 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4794 MVT SrcVT = Op.getOperand(0).getValueType();
4796 if (SrcVT.isVector()) {
4797 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
4803 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4804 "Unknown SINT_TO_FP to lower!");
4806 // These are really Legal; return the operand so the caller accepts it as
4808 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4810 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
4811 Subtarget->is64Bit()) {
4815 DebugLoc dl = Op.getDebugLoc();
4816 unsigned Size = SrcVT.getSizeInBits()/8;
4817 MachineFunction &MF = DAG.getMachineFunction();
4818 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4819 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4820 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
4822 PseudoSourceValue::getFixedStack(SSFI), 0);
4823 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
4826 SDValue X86TargetLowering::BuildFILD(SDValue Op, MVT SrcVT, SDValue Chain,
4828 SelectionDAG &DAG) {
4830 DebugLoc dl = Op.getDebugLoc();
4832 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4834 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4836 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4837 SmallVector<SDValue, 8> Ops;
4838 Ops.push_back(Chain);
4839 Ops.push_back(StackSlot);
4840 Ops.push_back(DAG.getValueType(SrcVT));
4841 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
4842 Tys, &Ops[0], Ops.size());
4845 Chain = Result.getValue(1);
4846 SDValue InFlag = Result.getValue(2);
4848 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4849 // shouldn't be necessary except that RFP cannot be live across
4850 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4851 MachineFunction &MF = DAG.getMachineFunction();
4852 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4853 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4854 Tys = DAG.getVTList(MVT::Other);
4855 SmallVector<SDValue, 8> Ops;
4856 Ops.push_back(Chain);
4857 Ops.push_back(Result);
4858 Ops.push_back(StackSlot);
4859 Ops.push_back(DAG.getValueType(Op.getValueType()));
4860 Ops.push_back(InFlag);
4861 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
4862 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
4863 PseudoSourceValue::getFixedStack(SSFI), 0);
4869 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
4870 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
4871 // This algorithm is not obvious. Here it is in C code, more or less:
4873 double uint64_to_double( uint32_t hi, uint32_t lo ) {
4874 static const __m128i exp = { 0x4330000045300000ULL, 0 };
4875 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
4877 // Copy ints to xmm registers.
4878 __m128i xh = _mm_cvtsi32_si128( hi );
4879 __m128i xl = _mm_cvtsi32_si128( lo );
4881 // Combine into low half of a single xmm register.
4882 __m128i x = _mm_unpacklo_epi32( xh, xl );
4886 // Merge in appropriate exponents to give the integer bits the right
4888 x = _mm_unpacklo_epi32( x, exp );
4890 // Subtract away the biases to deal with the IEEE-754 double precision
4892 d = _mm_sub_pd( (__m128d) x, bias );
4894 // All conversions up to here are exact. The correctly rounded result is
4895 // calculated using the current rounding mode using the following
4897 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
4898 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
4899 // store doesn't really need to be here (except
4900 // maybe to zero the other double)
4905 DebugLoc dl = Op.getDebugLoc();
4906 LLVMContext *Context = DAG.getContext();
4908 // Build some magic constants.
4909 std::vector<Constant*> CV0;
4910 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
4911 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
4912 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
4913 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
4914 Constant *C0 = ConstantVector::get(CV0);
4915 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
4917 std::vector<Constant*> CV1;
4919 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
4921 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
4922 Constant *C1 = ConstantVector::get(CV1);
4923 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
4925 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4926 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4928 DAG.getIntPtrConstant(1)));
4929 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4930 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4932 DAG.getIntPtrConstant(0)));
4933 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
4934 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
4935 PseudoSourceValue::getConstantPool(), 0,
4937 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
4938 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
4939 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
4940 PseudoSourceValue::getConstantPool(), 0,
4942 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
4944 // Add the halves; easiest way is to swap them into another reg first.
4945 int ShufMask[2] = { 1, -1 };
4946 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
4947 DAG.getUNDEF(MVT::v2f64), ShufMask);
4948 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
4949 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
4950 DAG.getIntPtrConstant(0));
4953 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
4954 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
4955 DebugLoc dl = Op.getDebugLoc();
4956 // FP constant to bias correct the final result.
4957 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
4960 // Load the 32-bit value into an XMM register.
4961 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4962 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4964 DAG.getIntPtrConstant(0)));
4966 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
4967 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
4968 DAG.getIntPtrConstant(0));
4970 // Or the load with the bias.
4971 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
4972 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
4973 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4975 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
4976 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4977 MVT::v2f64, Bias)));
4978 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
4979 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
4980 DAG.getIntPtrConstant(0));
4982 // Subtract the bias.
4983 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
4985 // Handle final rounding.
4986 MVT DestVT = Op.getValueType();
4988 if (DestVT.bitsLT(MVT::f64)) {
4989 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
4990 DAG.getIntPtrConstant(0));
4991 } else if (DestVT.bitsGT(MVT::f64)) {
4992 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
4995 // Handle final rounding.
4999 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5000 SDValue N0 = Op.getOperand(0);
5001 DebugLoc dl = Op.getDebugLoc();
5003 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5004 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5005 // the optimization here.
5006 if (DAG.SignBitIsZero(N0))
5007 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5009 MVT SrcVT = N0.getValueType();
5010 if (SrcVT == MVT::i64) {
5011 // We only handle SSE2 f64 target here; caller can expand the rest.
5012 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5015 return LowerUINT_TO_FP_i64(Op, DAG);
5016 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5017 return LowerUINT_TO_FP_i32(Op, DAG);
5020 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5022 // Make a 64-bit buffer, and use it to build an FILD.
5023 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5024 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5025 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5026 getPointerTy(), StackSlot, WordOff);
5027 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5028 StackSlot, NULL, 0);
5029 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5030 OffsetSlot, NULL, 0);
5031 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5034 std::pair<SDValue,SDValue> X86TargetLowering::
5035 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5036 DebugLoc dl = Op.getDebugLoc();
5038 MVT DstTy = Op.getValueType();
5041 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5045 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5046 DstTy.getSimpleVT() >= MVT::i16 &&
5047 "Unknown FP_TO_SINT to lower!");
5049 // These are really Legal.
5050 if (DstTy == MVT::i32 &&
5051 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5052 return std::make_pair(SDValue(), SDValue());
5053 if (Subtarget->is64Bit() &&
5054 DstTy == MVT::i64 &&
5055 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5056 return std::make_pair(SDValue(), SDValue());
5058 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5060 MachineFunction &MF = DAG.getMachineFunction();
5061 unsigned MemSize = DstTy.getSizeInBits()/8;
5062 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5063 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5066 switch (DstTy.getSimpleVT()) {
5067 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5068 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5069 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5070 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5073 SDValue Chain = DAG.getEntryNode();
5074 SDValue Value = Op.getOperand(0);
5075 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5076 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5077 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5078 PseudoSourceValue::getFixedStack(SSFI), 0);
5079 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5081 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5083 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5084 Chain = Value.getValue(1);
5085 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5086 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5089 // Build the FP_TO_INT*_IN_MEM
5090 SDValue Ops[] = { Chain, Value, StackSlot };
5091 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5093 return std::make_pair(FIST, StackSlot);
5096 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5097 if (Op.getValueType().isVector()) {
5098 if (Op.getValueType() == MVT::v2i32 &&
5099 Op.getOperand(0).getValueType() == MVT::v2f64) {
5105 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5106 SDValue FIST = Vals.first, StackSlot = Vals.second;
5107 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5108 if (FIST.getNode() == 0) return Op;
5111 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5112 FIST, StackSlot, NULL, 0);
5115 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5116 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5117 SDValue FIST = Vals.first, StackSlot = Vals.second;
5118 assert(FIST.getNode() && "Unexpected failure");
5121 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5122 FIST, StackSlot, NULL, 0);
5125 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5126 LLVMContext *Context = DAG.getContext();
5127 DebugLoc dl = Op.getDebugLoc();
5128 MVT VT = Op.getValueType();
5131 EltVT = VT.getVectorElementType();
5132 std::vector<Constant*> CV;
5133 if (EltVT == MVT::f64) {
5134 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5138 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5144 Constant *C = ConstantVector::get(CV);
5145 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5146 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5147 PseudoSourceValue::getConstantPool(), 0,
5149 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5152 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5153 LLVMContext *Context = DAG.getContext();
5154 DebugLoc dl = Op.getDebugLoc();
5155 MVT VT = Op.getValueType();
5157 unsigned EltNum = 1;
5158 if (VT.isVector()) {
5159 EltVT = VT.getVectorElementType();
5160 EltNum = VT.getVectorNumElements();
5162 std::vector<Constant*> CV;
5163 if (EltVT == MVT::f64) {
5164 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5168 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5174 Constant *C = ConstantVector::get(CV);
5175 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5176 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5177 PseudoSourceValue::getConstantPool(), 0,
5179 if (VT.isVector()) {
5180 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5181 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5182 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5184 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5186 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5190 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5191 LLVMContext *Context = DAG.getContext();
5192 SDValue Op0 = Op.getOperand(0);
5193 SDValue Op1 = Op.getOperand(1);
5194 DebugLoc dl = Op.getDebugLoc();
5195 MVT VT = Op.getValueType();
5196 MVT SrcVT = Op1.getValueType();
5198 // If second operand is smaller, extend it first.
5199 if (SrcVT.bitsLT(VT)) {
5200 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5203 // And if it is bigger, shrink it first.
5204 if (SrcVT.bitsGT(VT)) {
5205 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5209 // At this point the operands and the result should have the same
5210 // type, and that won't be f80 since that is not custom lowered.
5212 // First get the sign bit of second operand.
5213 std::vector<Constant*> CV;
5214 if (SrcVT == MVT::f64) {
5215 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5216 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5218 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5219 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5220 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5221 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5223 Constant *C = ConstantVector::get(CV);
5224 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5225 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5226 PseudoSourceValue::getConstantPool(), 0,
5228 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5230 // Shift sign bit right or left if the two operands have different types.
5231 if (SrcVT.bitsGT(VT)) {
5232 // Op0 is MVT::f32, Op1 is MVT::f64.
5233 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5234 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5235 DAG.getConstant(32, MVT::i32));
5236 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5237 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5238 DAG.getIntPtrConstant(0));
5241 // Clear first operand sign bit.
5243 if (VT == MVT::f64) {
5244 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5245 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5247 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5248 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5249 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5250 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5252 C = ConstantVector::get(CV);
5253 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5254 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5255 PseudoSourceValue::getConstantPool(), 0,
5257 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5259 // Or the value with the sign bit.
5260 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5263 /// Emit nodes that will be selected as "test Op0,Op0", or something
5265 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5266 SelectionDAG &DAG) {
5267 DebugLoc dl = Op.getDebugLoc();
5269 // CF and OF aren't always set the way we want. Determine which
5270 // of these we need.
5271 bool NeedCF = false;
5272 bool NeedOF = false;
5274 case X86::COND_A: case X86::COND_AE:
5275 case X86::COND_B: case X86::COND_BE:
5278 case X86::COND_G: case X86::COND_GE:
5279 case X86::COND_L: case X86::COND_LE:
5280 case X86::COND_O: case X86::COND_NO:
5286 // See if we can use the EFLAGS value from the operand instead of
5287 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5288 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5289 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5290 unsigned Opcode = 0;
5291 unsigned NumOperands = 0;
5292 switch (Op.getNode()->getOpcode()) {
5294 // Due to an isel shortcoming, be conservative if this add is likely to
5295 // be selected as part of a load-modify-store instruction. When the root
5296 // node in a match is a store, isel doesn't know how to remap non-chain
5297 // non-flag uses of other nodes in the match, such as the ADD in this
5298 // case. This leads to the ADD being left around and reselected, with
5299 // the result being two adds in the output.
5300 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5301 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5302 if (UI->getOpcode() == ISD::STORE)
5304 if (ConstantSDNode *C =
5305 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5306 // An add of one will be selected as an INC.
5307 if (C->getAPIntValue() == 1) {
5308 Opcode = X86ISD::INC;
5312 // An add of negative one (subtract of one) will be selected as a DEC.
5313 if (C->getAPIntValue().isAllOnesValue()) {
5314 Opcode = X86ISD::DEC;
5319 // Otherwise use a regular EFLAGS-setting add.
5320 Opcode = X86ISD::ADD;
5324 // Due to the ISEL shortcoming noted above, be conservative if this sub is
5325 // likely to be selected as part of a load-modify-store instruction.
5326 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5327 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5328 if (UI->getOpcode() == ISD::STORE)
5330 // Otherwise use a regular EFLAGS-setting sub.
5331 Opcode = X86ISD::SUB;
5338 return SDValue(Op.getNode(), 1);
5344 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5345 SmallVector<SDValue, 4> Ops;
5346 for (unsigned i = 0; i != NumOperands; ++i)
5347 Ops.push_back(Op.getOperand(i));
5348 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5349 DAG.ReplaceAllUsesWith(Op, New);
5350 return SDValue(New.getNode(), 1);
5354 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5355 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5356 DAG.getConstant(0, Op.getValueType()));
5359 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5361 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5362 SelectionDAG &DAG) {
5363 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5364 if (C->getAPIntValue() == 0)
5365 return EmitTest(Op0, X86CC, DAG);
5367 DebugLoc dl = Op0.getDebugLoc();
5368 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5371 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5372 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5373 SDValue Op0 = Op.getOperand(0);
5374 SDValue Op1 = Op.getOperand(1);
5375 DebugLoc dl = Op.getDebugLoc();
5376 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5378 // Lower (X & (1 << N)) == 0 to BT(X, N).
5379 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5380 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5381 if (Op0.getOpcode() == ISD::AND &&
5383 Op1.getOpcode() == ISD::Constant &&
5384 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5385 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5387 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5388 if (ConstantSDNode *Op010C =
5389 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5390 if (Op010C->getZExtValue() == 1) {
5391 LHS = Op0.getOperand(0);
5392 RHS = Op0.getOperand(1).getOperand(1);
5394 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5395 if (ConstantSDNode *Op000C =
5396 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5397 if (Op000C->getZExtValue() == 1) {
5398 LHS = Op0.getOperand(1);
5399 RHS = Op0.getOperand(0).getOperand(1);
5401 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5402 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5403 SDValue AndLHS = Op0.getOperand(0);
5404 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5405 LHS = AndLHS.getOperand(0);
5406 RHS = AndLHS.getOperand(1);
5410 if (LHS.getNode()) {
5411 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5412 // instruction. Since the shift amount is in-range-or-undefined, we know
5413 // that doing a bittest on the i16 value is ok. We extend to i32 because
5414 // the encoding for the i16 version is larger than the i32 version.
5415 if (LHS.getValueType() == MVT::i8)
5416 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5418 // If the operand types disagree, extend the shift amount to match. Since
5419 // BT ignores high bits (like shifts) we can use anyextend.
5420 if (LHS.getValueType() != RHS.getValueType())
5421 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5423 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5424 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5425 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5426 DAG.getConstant(Cond, MVT::i8), BT);
5430 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5431 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5433 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5434 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5435 DAG.getConstant(X86CC, MVT::i8), Cond);
5438 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5440 SDValue Op0 = Op.getOperand(0);
5441 SDValue Op1 = Op.getOperand(1);
5442 SDValue CC = Op.getOperand(2);
5443 MVT VT = Op.getValueType();
5444 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5445 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5446 DebugLoc dl = Op.getDebugLoc();
5450 MVT VT0 = Op0.getValueType();
5451 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5452 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5455 switch (SetCCOpcode) {
5458 case ISD::SETEQ: SSECC = 0; break;
5460 case ISD::SETGT: Swap = true; // Fallthrough
5462 case ISD::SETOLT: SSECC = 1; break;
5464 case ISD::SETGE: Swap = true; // Fallthrough
5466 case ISD::SETOLE: SSECC = 2; break;
5467 case ISD::SETUO: SSECC = 3; break;
5469 case ISD::SETNE: SSECC = 4; break;
5470 case ISD::SETULE: Swap = true;
5471 case ISD::SETUGE: SSECC = 5; break;
5472 case ISD::SETULT: Swap = true;
5473 case ISD::SETUGT: SSECC = 6; break;
5474 case ISD::SETO: SSECC = 7; break;
5477 std::swap(Op0, Op1);
5479 // In the two special cases we can't handle, emit two comparisons.
5481 if (SetCCOpcode == ISD::SETUEQ) {
5483 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5484 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5485 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
5487 else if (SetCCOpcode == ISD::SETONE) {
5489 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5490 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5491 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
5493 llvm_unreachable("Illegal FP comparison");
5495 // Handle all other FP comparisons here.
5496 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5499 // We are handling one of the integer comparisons here. Since SSE only has
5500 // GT and EQ comparisons for integer, swapping operands and multiple
5501 // operations may be required for some comparisons.
5502 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5503 bool Swap = false, Invert = false, FlipSigns = false;
5505 switch (VT.getSimpleVT()) {
5508 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5510 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5512 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5513 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5516 switch (SetCCOpcode) {
5518 case ISD::SETNE: Invert = true;
5519 case ISD::SETEQ: Opc = EQOpc; break;
5520 case ISD::SETLT: Swap = true;
5521 case ISD::SETGT: Opc = GTOpc; break;
5522 case ISD::SETGE: Swap = true;
5523 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5524 case ISD::SETULT: Swap = true;
5525 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5526 case ISD::SETUGE: Swap = true;
5527 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5530 std::swap(Op0, Op1);
5532 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5533 // bits of the inputs before performing those operations.
5535 MVT EltVT = VT.getVectorElementType();
5536 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5538 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5539 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
5541 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
5542 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
5545 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
5547 // If the logical-not of the result is required, perform that now.
5549 Result = DAG.getNOT(dl, Result, VT);
5554 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5555 static bool isX86LogicalCmp(SDValue Op) {
5556 unsigned Opc = Op.getNode()->getOpcode();
5557 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
5559 if (Op.getResNo() == 1 &&
5560 (Opc == X86ISD::ADD ||
5561 Opc == X86ISD::SUB ||
5562 Opc == X86ISD::SMUL ||
5563 Opc == X86ISD::UMUL ||
5564 Opc == X86ISD::INC ||
5565 Opc == X86ISD::DEC))
5571 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5572 bool addTest = true;
5573 SDValue Cond = Op.getOperand(0);
5574 DebugLoc dl = Op.getDebugLoc();
5577 if (Cond.getOpcode() == ISD::SETCC)
5578 Cond = LowerSETCC(Cond, DAG);
5580 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5581 // setting operand in place of the X86ISD::SETCC.
5582 if (Cond.getOpcode() == X86ISD::SETCC) {
5583 CC = Cond.getOperand(0);
5585 SDValue Cmp = Cond.getOperand(1);
5586 unsigned Opc = Cmp.getOpcode();
5587 MVT VT = Op.getValueType();
5589 bool IllegalFPCMov = false;
5590 if (VT.isFloatingPoint() && !VT.isVector() &&
5591 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5592 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5594 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
5595 Opc == X86ISD::BT) { // FIXME
5602 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5603 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5606 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
5607 SmallVector<SDValue, 4> Ops;
5608 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5609 // condition is true.
5610 Ops.push_back(Op.getOperand(2));
5611 Ops.push_back(Op.getOperand(1));
5613 Ops.push_back(Cond);
5614 return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size());
5617 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5618 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5619 // from the AND / OR.
5620 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5621 Opc = Op.getOpcode();
5622 if (Opc != ISD::OR && Opc != ISD::AND)
5624 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5625 Op.getOperand(0).hasOneUse() &&
5626 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5627 Op.getOperand(1).hasOneUse());
5630 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
5631 // 1 and that the SETCC node has a single use.
5632 static bool isXor1OfSetCC(SDValue Op) {
5633 if (Op.getOpcode() != ISD::XOR)
5635 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5636 if (N1C && N1C->getAPIntValue() == 1) {
5637 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5638 Op.getOperand(0).hasOneUse();
5643 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5644 bool addTest = true;
5645 SDValue Chain = Op.getOperand(0);
5646 SDValue Cond = Op.getOperand(1);
5647 SDValue Dest = Op.getOperand(2);
5648 DebugLoc dl = Op.getDebugLoc();
5651 if (Cond.getOpcode() == ISD::SETCC)
5652 Cond = LowerSETCC(Cond, DAG);
5654 // FIXME: LowerXALUO doesn't handle these!!
5655 else if (Cond.getOpcode() == X86ISD::ADD ||
5656 Cond.getOpcode() == X86ISD::SUB ||
5657 Cond.getOpcode() == X86ISD::SMUL ||
5658 Cond.getOpcode() == X86ISD::UMUL)
5659 Cond = LowerXALUO(Cond, DAG);
5662 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5663 // setting operand in place of the X86ISD::SETCC.
5664 if (Cond.getOpcode() == X86ISD::SETCC) {
5665 CC = Cond.getOperand(0);
5667 SDValue Cmp = Cond.getOperand(1);
5668 unsigned Opc = Cmp.getOpcode();
5669 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
5670 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
5674 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
5678 // These can only come from an arithmetic instruction with overflow,
5679 // e.g. SADDO, UADDO.
5680 Cond = Cond.getNode()->getOperand(1);
5687 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
5688 SDValue Cmp = Cond.getOperand(0).getOperand(1);
5689 if (CondOpc == ISD::OR) {
5690 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
5691 // two branches instead of an explicit OR instruction with a
5693 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5694 isX86LogicalCmp(Cmp)) {
5695 CC = Cond.getOperand(0).getOperand(0);
5696 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5697 Chain, Dest, CC, Cmp);
5698 CC = Cond.getOperand(1).getOperand(0);
5702 } else { // ISD::AND
5703 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
5704 // two branches instead of an explicit AND instruction with a
5705 // separate test. However, we only do this if this block doesn't
5706 // have a fall-through edge, because this requires an explicit
5707 // jmp when the condition is false.
5708 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5709 isX86LogicalCmp(Cmp) &&
5710 Op.getNode()->hasOneUse()) {
5711 X86::CondCode CCode =
5712 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5713 CCode = X86::GetOppositeBranchCondition(CCode);
5714 CC = DAG.getConstant(CCode, MVT::i8);
5715 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
5716 // Look for an unconditional branch following this conditional branch.
5717 // We need this because we need to reverse the successors in order
5718 // to implement FCMP_OEQ.
5719 if (User.getOpcode() == ISD::BR) {
5720 SDValue FalseBB = User.getOperand(1);
5722 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
5723 assert(NewBR == User);
5726 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5727 Chain, Dest, CC, Cmp);
5728 X86::CondCode CCode =
5729 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
5730 CCode = X86::GetOppositeBranchCondition(CCode);
5731 CC = DAG.getConstant(CCode, MVT::i8);
5737 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
5738 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
5739 // It should be transformed during dag combiner except when the condition
5740 // is set by a arithmetics with overflow node.
5741 X86::CondCode CCode =
5742 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5743 CCode = X86::GetOppositeBranchCondition(CCode);
5744 CC = DAG.getConstant(CCode, MVT::i8);
5745 Cond = Cond.getOperand(0).getOperand(1);
5751 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5752 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5754 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5755 Chain, Dest, CC, Cond);
5759 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5760 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5761 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5762 // that the guard pages used by the OS virtual memory manager are allocated in
5763 // correct sequence.
5765 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5766 SelectionDAG &DAG) {
5767 assert(Subtarget->isTargetCygMing() &&
5768 "This should be used only on Cygwin/Mingw targets");
5769 DebugLoc dl = Op.getDebugLoc();
5772 SDValue Chain = Op.getOperand(0);
5773 SDValue Size = Op.getOperand(1);
5774 // FIXME: Ensure alignment here
5778 MVT IntPtr = getPointerTy();
5779 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5781 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
5783 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
5784 Flag = Chain.getValue(1);
5786 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5787 SDValue Ops[] = { Chain,
5788 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5789 DAG.getRegister(X86::EAX, IntPtr),
5790 DAG.getRegister(X86StackPtr, SPTy),
5792 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
5793 Flag = Chain.getValue(1);
5795 Chain = DAG.getCALLSEQ_END(Chain,
5796 DAG.getIntPtrConstant(0, true),
5797 DAG.getIntPtrConstant(0, true),
5800 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
5802 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5803 return DAG.getMergeValues(Ops1, 2, dl);
5807 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
5809 SDValue Dst, SDValue Src,
5810 SDValue Size, unsigned Align,
5812 uint64_t DstSVOff) {
5813 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5815 // If not DWORD aligned or size is more than the threshold, call the library.
5816 // The libc version is likely to be faster for these cases. It can use the
5817 // address value and run time information about the CPU.
5818 if ((Align & 3) != 0 ||
5820 ConstantSize->getZExtValue() >
5821 getSubtarget()->getMaxInlineSizeThreshold()) {
5822 SDValue InFlag(0, 0);
5824 // Check to see if there is a specialized entry-point for memory zeroing.
5825 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5827 if (const char *bzeroEntry = V &&
5828 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5829 MVT IntPtr = getPointerTy();
5830 const Type *IntPtrTy = TD->getIntPtrType();
5831 TargetLowering::ArgListTy Args;
5832 TargetLowering::ArgListEntry Entry;
5834 Entry.Ty = IntPtrTy;
5835 Args.push_back(Entry);
5837 Args.push_back(Entry);
5838 std::pair<SDValue,SDValue> CallResult =
5839 LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
5840 0, CallingConv::C, false,
5841 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
5842 return CallResult.second;
5845 // Otherwise have the target-independent code call memset.
5849 uint64_t SizeVal = ConstantSize->getZExtValue();
5850 SDValue InFlag(0, 0);
5853 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5854 unsigned BytesLeft = 0;
5855 bool TwoRepStos = false;
5858 uint64_t Val = ValC->getZExtValue() & 255;
5860 // If the value is a constant, then we can potentially use larger sets.
5861 switch (Align & 3) {
5862 case 2: // WORD aligned
5865 Val = (Val << 8) | Val;
5867 case 0: // DWORD aligned
5870 Val = (Val << 8) | Val;
5871 Val = (Val << 16) | Val;
5872 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5875 Val = (Val << 32) | Val;
5878 default: // Byte aligned
5881 Count = DAG.getIntPtrConstant(SizeVal);
5885 if (AVT.bitsGT(MVT::i8)) {
5886 unsigned UBytes = AVT.getSizeInBits() / 8;
5887 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5888 BytesLeft = SizeVal % UBytes;
5891 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
5893 InFlag = Chain.getValue(1);
5896 Count = DAG.getIntPtrConstant(SizeVal);
5897 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
5898 InFlag = Chain.getValue(1);
5901 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
5904 InFlag = Chain.getValue(1);
5905 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
5908 InFlag = Chain.getValue(1);
5910 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5911 SmallVector<SDValue, 8> Ops;
5912 Ops.push_back(Chain);
5913 Ops.push_back(DAG.getValueType(AVT));
5914 Ops.push_back(InFlag);
5915 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
5918 InFlag = Chain.getValue(1);
5920 MVT CVT = Count.getValueType();
5921 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
5922 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5923 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
5926 InFlag = Chain.getValue(1);
5927 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5929 Ops.push_back(Chain);
5930 Ops.push_back(DAG.getValueType(MVT::i8));
5931 Ops.push_back(InFlag);
5932 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
5933 } else if (BytesLeft) {
5934 // Handle the last 1 - 7 bytes.
5935 unsigned Offset = SizeVal - BytesLeft;
5936 MVT AddrVT = Dst.getValueType();
5937 MVT SizeVT = Size.getValueType();
5939 Chain = DAG.getMemset(Chain, dl,
5940 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
5941 DAG.getConstant(Offset, AddrVT)),
5943 DAG.getConstant(BytesLeft, SizeVT),
5944 Align, DstSV, DstSVOff + Offset);
5947 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
5952 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
5953 SDValue Chain, SDValue Dst, SDValue Src,
5954 SDValue Size, unsigned Align,
5956 const Value *DstSV, uint64_t DstSVOff,
5957 const Value *SrcSV, uint64_t SrcSVOff) {
5958 // This requires the copy size to be a constant, preferrably
5959 // within a subtarget-specific limit.
5960 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5963 uint64_t SizeVal = ConstantSize->getZExtValue();
5964 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
5967 /// If not DWORD aligned, call the library.
5968 if ((Align & 3) != 0)
5973 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
5976 unsigned UBytes = AVT.getSizeInBits() / 8;
5977 unsigned CountVal = SizeVal / UBytes;
5978 SDValue Count = DAG.getIntPtrConstant(CountVal);
5979 unsigned BytesLeft = SizeVal % UBytes;
5981 SDValue InFlag(0, 0);
5982 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
5985 InFlag = Chain.getValue(1);
5986 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
5989 InFlag = Chain.getValue(1);
5990 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
5993 InFlag = Chain.getValue(1);
5995 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5996 SmallVector<SDValue, 8> Ops;
5997 Ops.push_back(Chain);
5998 Ops.push_back(DAG.getValueType(AVT));
5999 Ops.push_back(InFlag);
6000 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size());
6002 SmallVector<SDValue, 4> Results;
6003 Results.push_back(RepMovs);
6005 // Handle the last 1 - 7 bytes.
6006 unsigned Offset = SizeVal - BytesLeft;
6007 MVT DstVT = Dst.getValueType();
6008 MVT SrcVT = Src.getValueType();
6009 MVT SizeVT = Size.getValueType();
6010 Results.push_back(DAG.getMemcpy(Chain, dl,
6011 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6012 DAG.getConstant(Offset, DstVT)),
6013 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6014 DAG.getConstant(Offset, SrcVT)),
6015 DAG.getConstant(BytesLeft, SizeVT),
6016 Align, AlwaysInline,
6017 DstSV, DstSVOff + Offset,
6018 SrcSV, SrcSVOff + Offset));
6021 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6022 &Results[0], Results.size());
6025 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6026 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6027 DebugLoc dl = Op.getDebugLoc();
6029 if (!Subtarget->is64Bit()) {
6030 // vastart just stores the address of the VarArgsFrameIndex slot into the
6031 // memory location argument.
6032 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6033 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6037 // gp_offset (0 - 6 * 8)
6038 // fp_offset (48 - 48 + 8 * 16)
6039 // overflow_arg_area (point to parameters coming in memory).
6041 SmallVector<SDValue, 8> MemOps;
6042 SDValue FIN = Op.getOperand(1);
6044 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6045 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6047 MemOps.push_back(Store);
6050 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6051 FIN, DAG.getIntPtrConstant(4));
6052 Store = DAG.getStore(Op.getOperand(0), dl,
6053 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6055 MemOps.push_back(Store);
6057 // Store ptr to overflow_arg_area
6058 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6059 FIN, DAG.getIntPtrConstant(4));
6060 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6061 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6062 MemOps.push_back(Store);
6064 // Store ptr to reg_save_area.
6065 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6066 FIN, DAG.getIntPtrConstant(8));
6067 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6068 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6069 MemOps.push_back(Store);
6070 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6071 &MemOps[0], MemOps.size());
6074 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6075 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6076 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6077 SDValue Chain = Op.getOperand(0);
6078 SDValue SrcPtr = Op.getOperand(1);
6079 SDValue SrcSV = Op.getOperand(2);
6081 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6085 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6086 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6087 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6088 SDValue Chain = Op.getOperand(0);
6089 SDValue DstPtr = Op.getOperand(1);
6090 SDValue SrcPtr = Op.getOperand(2);
6091 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6092 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6093 DebugLoc dl = Op.getDebugLoc();
6095 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6096 DAG.getIntPtrConstant(24), 8, false,
6097 DstSV, 0, SrcSV, 0);
6101 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6102 DebugLoc dl = Op.getDebugLoc();
6103 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6105 default: return SDValue(); // Don't custom lower most intrinsics.
6106 // Comparison intrinsics.
6107 case Intrinsic::x86_sse_comieq_ss:
6108 case Intrinsic::x86_sse_comilt_ss:
6109 case Intrinsic::x86_sse_comile_ss:
6110 case Intrinsic::x86_sse_comigt_ss:
6111 case Intrinsic::x86_sse_comige_ss:
6112 case Intrinsic::x86_sse_comineq_ss:
6113 case Intrinsic::x86_sse_ucomieq_ss:
6114 case Intrinsic::x86_sse_ucomilt_ss:
6115 case Intrinsic::x86_sse_ucomile_ss:
6116 case Intrinsic::x86_sse_ucomigt_ss:
6117 case Intrinsic::x86_sse_ucomige_ss:
6118 case Intrinsic::x86_sse_ucomineq_ss:
6119 case Intrinsic::x86_sse2_comieq_sd:
6120 case Intrinsic::x86_sse2_comilt_sd:
6121 case Intrinsic::x86_sse2_comile_sd:
6122 case Intrinsic::x86_sse2_comigt_sd:
6123 case Intrinsic::x86_sse2_comige_sd:
6124 case Intrinsic::x86_sse2_comineq_sd:
6125 case Intrinsic::x86_sse2_ucomieq_sd:
6126 case Intrinsic::x86_sse2_ucomilt_sd:
6127 case Intrinsic::x86_sse2_ucomile_sd:
6128 case Intrinsic::x86_sse2_ucomigt_sd:
6129 case Intrinsic::x86_sse2_ucomige_sd:
6130 case Intrinsic::x86_sse2_ucomineq_sd: {
6132 ISD::CondCode CC = ISD::SETCC_INVALID;
6135 case Intrinsic::x86_sse_comieq_ss:
6136 case Intrinsic::x86_sse2_comieq_sd:
6140 case Intrinsic::x86_sse_comilt_ss:
6141 case Intrinsic::x86_sse2_comilt_sd:
6145 case Intrinsic::x86_sse_comile_ss:
6146 case Intrinsic::x86_sse2_comile_sd:
6150 case Intrinsic::x86_sse_comigt_ss:
6151 case Intrinsic::x86_sse2_comigt_sd:
6155 case Intrinsic::x86_sse_comige_ss:
6156 case Intrinsic::x86_sse2_comige_sd:
6160 case Intrinsic::x86_sse_comineq_ss:
6161 case Intrinsic::x86_sse2_comineq_sd:
6165 case Intrinsic::x86_sse_ucomieq_ss:
6166 case Intrinsic::x86_sse2_ucomieq_sd:
6167 Opc = X86ISD::UCOMI;
6170 case Intrinsic::x86_sse_ucomilt_ss:
6171 case Intrinsic::x86_sse2_ucomilt_sd:
6172 Opc = X86ISD::UCOMI;
6175 case Intrinsic::x86_sse_ucomile_ss:
6176 case Intrinsic::x86_sse2_ucomile_sd:
6177 Opc = X86ISD::UCOMI;
6180 case Intrinsic::x86_sse_ucomigt_ss:
6181 case Intrinsic::x86_sse2_ucomigt_sd:
6182 Opc = X86ISD::UCOMI;
6185 case Intrinsic::x86_sse_ucomige_ss:
6186 case Intrinsic::x86_sse2_ucomige_sd:
6187 Opc = X86ISD::UCOMI;
6190 case Intrinsic::x86_sse_ucomineq_ss:
6191 case Intrinsic::x86_sse2_ucomineq_sd:
6192 Opc = X86ISD::UCOMI;
6197 SDValue LHS = Op.getOperand(1);
6198 SDValue RHS = Op.getOperand(2);
6199 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6200 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6201 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6202 DAG.getConstant(X86CC, MVT::i8), Cond);
6203 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6205 // ptest intrinsics. The intrinsic these come from are designed to return
6206 // an integer value, not just an instruction so lower it to the ptest
6207 // pattern and a setcc for the result.
6208 case Intrinsic::x86_sse41_ptestz:
6209 case Intrinsic::x86_sse41_ptestc:
6210 case Intrinsic::x86_sse41_ptestnzc:{
6213 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6214 case Intrinsic::x86_sse41_ptestz:
6216 X86CC = X86::COND_E;
6218 case Intrinsic::x86_sse41_ptestc:
6220 X86CC = X86::COND_B;
6222 case Intrinsic::x86_sse41_ptestnzc:
6224 X86CC = X86::COND_A;
6228 SDValue LHS = Op.getOperand(1);
6229 SDValue RHS = Op.getOperand(2);
6230 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6231 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6232 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6233 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6236 // Fix vector shift instructions where the last operand is a non-immediate
6238 case Intrinsic::x86_sse2_pslli_w:
6239 case Intrinsic::x86_sse2_pslli_d:
6240 case Intrinsic::x86_sse2_pslli_q:
6241 case Intrinsic::x86_sse2_psrli_w:
6242 case Intrinsic::x86_sse2_psrli_d:
6243 case Intrinsic::x86_sse2_psrli_q:
6244 case Intrinsic::x86_sse2_psrai_w:
6245 case Intrinsic::x86_sse2_psrai_d:
6246 case Intrinsic::x86_mmx_pslli_w:
6247 case Intrinsic::x86_mmx_pslli_d:
6248 case Intrinsic::x86_mmx_pslli_q:
6249 case Intrinsic::x86_mmx_psrli_w:
6250 case Intrinsic::x86_mmx_psrli_d:
6251 case Intrinsic::x86_mmx_psrli_q:
6252 case Intrinsic::x86_mmx_psrai_w:
6253 case Intrinsic::x86_mmx_psrai_d: {
6254 SDValue ShAmt = Op.getOperand(2);
6255 if (isa<ConstantSDNode>(ShAmt))
6258 unsigned NewIntNo = 0;
6259 MVT ShAmtVT = MVT::v4i32;
6261 case Intrinsic::x86_sse2_pslli_w:
6262 NewIntNo = Intrinsic::x86_sse2_psll_w;
6264 case Intrinsic::x86_sse2_pslli_d:
6265 NewIntNo = Intrinsic::x86_sse2_psll_d;
6267 case Intrinsic::x86_sse2_pslli_q:
6268 NewIntNo = Intrinsic::x86_sse2_psll_q;
6270 case Intrinsic::x86_sse2_psrli_w:
6271 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6273 case Intrinsic::x86_sse2_psrli_d:
6274 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6276 case Intrinsic::x86_sse2_psrli_q:
6277 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6279 case Intrinsic::x86_sse2_psrai_w:
6280 NewIntNo = Intrinsic::x86_sse2_psra_w;
6282 case Intrinsic::x86_sse2_psrai_d:
6283 NewIntNo = Intrinsic::x86_sse2_psra_d;
6286 ShAmtVT = MVT::v2i32;
6288 case Intrinsic::x86_mmx_pslli_w:
6289 NewIntNo = Intrinsic::x86_mmx_psll_w;
6291 case Intrinsic::x86_mmx_pslli_d:
6292 NewIntNo = Intrinsic::x86_mmx_psll_d;
6294 case Intrinsic::x86_mmx_pslli_q:
6295 NewIntNo = Intrinsic::x86_mmx_psll_q;
6297 case Intrinsic::x86_mmx_psrli_w:
6298 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6300 case Intrinsic::x86_mmx_psrli_d:
6301 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6303 case Intrinsic::x86_mmx_psrli_q:
6304 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6306 case Intrinsic::x86_mmx_psrai_w:
6307 NewIntNo = Intrinsic::x86_mmx_psra_w;
6309 case Intrinsic::x86_mmx_psrai_d:
6310 NewIntNo = Intrinsic::x86_mmx_psra_d;
6312 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6317 MVT VT = Op.getValueType();
6318 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT,
6319 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt));
6320 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6321 DAG.getConstant(NewIntNo, MVT::i32),
6322 Op.getOperand(1), ShAmt);
6327 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6328 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6329 DebugLoc dl = Op.getDebugLoc();
6332 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6334 DAG.getConstant(TD->getPointerSize(),
6335 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6336 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6337 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6342 // Just load the return address.
6343 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6344 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6345 RetAddrFI, NULL, 0);
6348 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6349 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6350 MFI->setFrameAddressIsTaken(true);
6351 MVT VT = Op.getValueType();
6352 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6353 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6354 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6355 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6357 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6361 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6362 SelectionDAG &DAG) {
6363 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6366 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6368 MachineFunction &MF = DAG.getMachineFunction();
6369 SDValue Chain = Op.getOperand(0);
6370 SDValue Offset = Op.getOperand(1);
6371 SDValue Handler = Op.getOperand(2);
6372 DebugLoc dl = Op.getDebugLoc();
6374 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6376 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6378 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6379 DAG.getIntPtrConstant(-TD->getPointerSize()));
6380 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6381 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6382 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6383 MF.getRegInfo().addLiveOut(StoreAddrReg);
6385 return DAG.getNode(X86ISD::EH_RETURN, dl,
6387 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6390 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6391 SelectionDAG &DAG) {
6392 SDValue Root = Op.getOperand(0);
6393 SDValue Trmp = Op.getOperand(1); // trampoline
6394 SDValue FPtr = Op.getOperand(2); // nested function
6395 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6396 DebugLoc dl = Op.getDebugLoc();
6398 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6400 const X86InstrInfo *TII =
6401 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6403 if (Subtarget->is64Bit()) {
6404 SDValue OutChains[6];
6406 // Large code-model.
6408 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6409 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6411 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6412 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6414 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6416 // Load the pointer to the nested function into R11.
6417 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6418 SDValue Addr = Trmp;
6419 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6422 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6423 DAG.getConstant(2, MVT::i64));
6424 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
6426 // Load the 'nest' parameter value into R10.
6427 // R10 is specified in X86CallingConv.td
6428 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6429 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6430 DAG.getConstant(10, MVT::i64));
6431 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6432 Addr, TrmpAddr, 10);
6434 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6435 DAG.getConstant(12, MVT::i64));
6436 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
6438 // Jump to the nested function.
6439 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6440 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6441 DAG.getConstant(20, MVT::i64));
6442 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6443 Addr, TrmpAddr, 20);
6445 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6446 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6447 DAG.getConstant(22, MVT::i64));
6448 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
6452 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
6453 return DAG.getMergeValues(Ops, 2, dl);
6455 const Function *Func =
6456 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6457 unsigned CC = Func->getCallingConv();
6462 llvm_unreachable("Unsupported calling convention");
6463 case CallingConv::C:
6464 case CallingConv::X86_StdCall: {
6465 // Pass 'nest' parameter in ECX.
6466 // Must be kept in sync with X86CallingConv.td
6469 // Check that ECX wasn't needed by an 'inreg' parameter.
6470 const FunctionType *FTy = Func->getFunctionType();
6471 const AttrListPtr &Attrs = Func->getAttributes();
6473 if (!Attrs.isEmpty() && !Func->isVarArg()) {
6474 unsigned InRegCount = 0;
6477 for (FunctionType::param_iterator I = FTy->param_begin(),
6478 E = FTy->param_end(); I != E; ++I, ++Idx)
6479 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6480 // FIXME: should only count parameters that are lowered to integers.
6481 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6483 if (InRegCount > 2) {
6484 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
6489 case CallingConv::X86_FastCall:
6490 case CallingConv::Fast:
6491 // Pass 'nest' parameter in EAX.
6492 // Must be kept in sync with X86CallingConv.td
6497 SDValue OutChains[4];
6500 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6501 DAG.getConstant(10, MVT::i32));
6502 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
6504 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6505 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6506 OutChains[0] = DAG.getStore(Root, dl,
6507 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6510 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6511 DAG.getConstant(1, MVT::i32));
6512 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
6514 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6515 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6516 DAG.getConstant(5, MVT::i32));
6517 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
6518 TrmpAddr, 5, false, 1);
6520 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6521 DAG.getConstant(6, MVT::i32));
6522 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
6525 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
6526 return DAG.getMergeValues(Ops, 2, dl);
6530 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6532 The rounding mode is in bits 11:10 of FPSR, and has the following
6539 FLT_ROUNDS, on the other hand, expects the following:
6546 To perform the conversion, we do:
6547 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6550 MachineFunction &MF = DAG.getMachineFunction();
6551 const TargetMachine &TM = MF.getTarget();
6552 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6553 unsigned StackAlignment = TFI.getStackAlignment();
6554 MVT VT = Op.getValueType();
6555 DebugLoc dl = Op.getDebugLoc();
6557 // Save FP Control Word to stack slot
6558 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
6559 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6561 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
6562 DAG.getEntryNode(), StackSlot);
6564 // Load FP Control Word from stack slot
6565 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
6567 // Transform as necessary
6569 DAG.getNode(ISD::SRL, dl, MVT::i16,
6570 DAG.getNode(ISD::AND, dl, MVT::i16,
6571 CWD, DAG.getConstant(0x800, MVT::i16)),
6572 DAG.getConstant(11, MVT::i8));
6574 DAG.getNode(ISD::SRL, dl, MVT::i16,
6575 DAG.getNode(ISD::AND, dl, MVT::i16,
6576 CWD, DAG.getConstant(0x400, MVT::i16)),
6577 DAG.getConstant(9, MVT::i8));
6580 DAG.getNode(ISD::AND, dl, MVT::i16,
6581 DAG.getNode(ISD::ADD, dl, MVT::i16,
6582 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
6583 DAG.getConstant(1, MVT::i16)),
6584 DAG.getConstant(3, MVT::i16));
6587 return DAG.getNode((VT.getSizeInBits() < 16 ?
6588 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6591 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6592 MVT VT = Op.getValueType();
6594 unsigned NumBits = VT.getSizeInBits();
6595 DebugLoc dl = Op.getDebugLoc();
6597 Op = Op.getOperand(0);
6598 if (VT == MVT::i8) {
6599 // Zero extend to i32 since there is not an i8 bsr.
6601 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6604 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6605 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6606 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
6608 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6609 SmallVector<SDValue, 4> Ops;
6611 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6612 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6613 Ops.push_back(Op.getValue(1));
6614 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6616 // Finally xor with NumBits-1.
6617 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6620 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6624 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6625 MVT VT = Op.getValueType();
6627 unsigned NumBits = VT.getSizeInBits();
6628 DebugLoc dl = Op.getDebugLoc();
6630 Op = Op.getOperand(0);
6631 if (VT == MVT::i8) {
6633 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6636 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6637 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6638 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
6640 // If src is zero (i.e. bsf sets ZF), returns NumBits.
6641 SmallVector<SDValue, 4> Ops;
6643 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6644 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6645 Ops.push_back(Op.getValue(1));
6646 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6649 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6653 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
6654 MVT VT = Op.getValueType();
6655 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
6656 DebugLoc dl = Op.getDebugLoc();
6658 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
6659 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
6660 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
6661 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
6662 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
6664 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
6665 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
6666 // return AloBlo + AloBhi + AhiBlo;
6668 SDValue A = Op.getOperand(0);
6669 SDValue B = Op.getOperand(1);
6671 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6672 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6673 A, DAG.getConstant(32, MVT::i32));
6674 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6675 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6676 B, DAG.getConstant(32, MVT::i32));
6677 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6678 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6680 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6681 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6683 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6684 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6686 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6687 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6688 AloBhi, DAG.getConstant(32, MVT::i32));
6689 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6690 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6691 AhiBlo, DAG.getConstant(32, MVT::i32));
6692 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
6693 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
6698 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
6699 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
6700 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
6701 // looks for this combo and may remove the "setcc" instruction if the "setcc"
6702 // has only one use.
6703 SDNode *N = Op.getNode();
6704 SDValue LHS = N->getOperand(0);
6705 SDValue RHS = N->getOperand(1);
6706 unsigned BaseOp = 0;
6708 DebugLoc dl = Op.getDebugLoc();
6710 switch (Op.getOpcode()) {
6711 default: llvm_unreachable("Unknown ovf instruction!");
6713 // A subtract of one will be selected as a INC. Note that INC doesn't
6714 // set CF, so we can't do this for UADDO.
6715 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6716 if (C->getAPIntValue() == 1) {
6717 BaseOp = X86ISD::INC;
6721 BaseOp = X86ISD::ADD;
6725 BaseOp = X86ISD::ADD;
6729 // A subtract of one will be selected as a DEC. Note that DEC doesn't
6730 // set CF, so we can't do this for USUBO.
6731 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6732 if (C->getAPIntValue() == 1) {
6733 BaseOp = X86ISD::DEC;
6737 BaseOp = X86ISD::SUB;
6741 BaseOp = X86ISD::SUB;
6745 BaseOp = X86ISD::SMUL;
6749 BaseOp = X86ISD::UMUL;
6754 // Also sets EFLAGS.
6755 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
6756 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
6759 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
6760 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
6762 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
6766 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
6767 MVT T = Op.getValueType();
6768 DebugLoc dl = Op.getDebugLoc();
6771 switch(T.getSimpleVT()) {
6773 assert(false && "Invalid value type!");
6774 case MVT::i8: Reg = X86::AL; size = 1; break;
6775 case MVT::i16: Reg = X86::AX; size = 2; break;
6776 case MVT::i32: Reg = X86::EAX; size = 4; break;
6778 assert(Subtarget->is64Bit() && "Node not type legal!");
6779 Reg = X86::RAX; size = 8;
6782 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
6783 Op.getOperand(2), SDValue());
6784 SDValue Ops[] = { cpIn.getValue(0),
6787 DAG.getTargetConstant(size, MVT::i8),
6789 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6790 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
6792 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
6796 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
6797 SelectionDAG &DAG) {
6798 assert(Subtarget->is64Bit() && "Result not type legalized?");
6799 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6800 SDValue TheChain = Op.getOperand(0);
6801 DebugLoc dl = Op.getDebugLoc();
6802 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
6803 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
6804 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
6806 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
6807 DAG.getConstant(32, MVT::i8));
6809 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
6812 return DAG.getMergeValues(Ops, 2, dl);
6815 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
6816 SDNode *Node = Op.getNode();
6817 DebugLoc dl = Node->getDebugLoc();
6818 MVT T = Node->getValueType(0);
6819 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
6820 DAG.getConstant(0, T), Node->getOperand(2));
6821 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
6822 cast<AtomicSDNode>(Node)->getMemoryVT(),
6823 Node->getOperand(0),
6824 Node->getOperand(1), negOp,
6825 cast<AtomicSDNode>(Node)->getSrcValue(),
6826 cast<AtomicSDNode>(Node)->getAlignment());
6829 /// LowerOperation - Provide custom lowering hooks for some operations.
6831 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
6832 switch (Op.getOpcode()) {
6833 default: llvm_unreachable("Should not custom lower this!");
6834 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
6835 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
6836 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6837 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6838 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6839 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6840 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6841 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6842 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6843 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6844 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
6845 case ISD::SHL_PARTS:
6846 case ISD::SRA_PARTS:
6847 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
6848 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
6849 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
6850 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
6851 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
6852 case ISD::FABS: return LowerFABS(Op, DAG);
6853 case ISD::FNEG: return LowerFNEG(Op, DAG);
6854 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6855 case ISD::SETCC: return LowerSETCC(Op, DAG);
6856 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
6857 case ISD::SELECT: return LowerSELECT(Op, DAG);
6858 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
6859 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6860 case ISD::CALL: return LowerCALL(Op, DAG);
6861 case ISD::RET: return LowerRET(Op, DAG);
6862 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
6863 case ISD::VASTART: return LowerVASTART(Op, DAG);
6864 case ISD::VAARG: return LowerVAARG(Op, DAG);
6865 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
6866 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6867 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6868 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6869 case ISD::FRAME_TO_ARGS_OFFSET:
6870 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
6871 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
6872 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
6873 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
6874 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6875 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6876 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
6877 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
6883 case ISD::UMULO: return LowerXALUO(Op, DAG);
6884 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
6888 void X86TargetLowering::
6889 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
6890 SelectionDAG &DAG, unsigned NewOp) {
6891 MVT T = Node->getValueType(0);
6892 DebugLoc dl = Node->getDebugLoc();
6893 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
6895 SDValue Chain = Node->getOperand(0);
6896 SDValue In1 = Node->getOperand(1);
6897 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6898 Node->getOperand(2), DAG.getIntPtrConstant(0));
6899 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6900 Node->getOperand(2), DAG.getIntPtrConstant(1));
6901 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
6902 // have a MemOperand. Pass the info through as a normal operand.
6903 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
6904 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
6905 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6906 SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5);
6907 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
6908 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
6909 Results.push_back(Result.getValue(2));
6912 /// ReplaceNodeResults - Replace a node with an illegal result type
6913 /// with a new node built out of custom code.
6914 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
6915 SmallVectorImpl<SDValue>&Results,
6916 SelectionDAG &DAG) {
6917 DebugLoc dl = N->getDebugLoc();
6918 switch (N->getOpcode()) {
6920 assert(false && "Do not know how to custom type legalize this operation!");
6922 case ISD::FP_TO_SINT: {
6923 std::pair<SDValue,SDValue> Vals =
6924 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
6925 SDValue FIST = Vals.first, StackSlot = Vals.second;
6926 if (FIST.getNode() != 0) {
6927 MVT VT = N->getValueType(0);
6928 // Return a load from the stack slot.
6929 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
6933 case ISD::READCYCLECOUNTER: {
6934 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6935 SDValue TheChain = N->getOperand(0);
6936 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
6937 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
6939 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
6941 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
6942 SDValue Ops[] = { eax, edx };
6943 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
6944 Results.push_back(edx.getValue(1));
6947 case ISD::ATOMIC_CMP_SWAP: {
6948 MVT T = N->getValueType(0);
6949 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
6950 SDValue cpInL, cpInH;
6951 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
6952 DAG.getConstant(0, MVT::i32));
6953 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
6954 DAG.getConstant(1, MVT::i32));
6955 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
6956 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
6958 SDValue swapInL, swapInH;
6959 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
6960 DAG.getConstant(0, MVT::i32));
6961 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
6962 DAG.getConstant(1, MVT::i32));
6963 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
6965 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
6966 swapInL.getValue(1));
6967 SDValue Ops[] = { swapInH.getValue(0),
6969 swapInH.getValue(1) };
6970 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6971 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
6972 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
6973 MVT::i32, Result.getValue(1));
6974 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
6975 MVT::i32, cpOutL.getValue(2));
6976 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
6977 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
6978 Results.push_back(cpOutH.getValue(1));
6981 case ISD::ATOMIC_LOAD_ADD:
6982 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
6984 case ISD::ATOMIC_LOAD_AND:
6985 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
6987 case ISD::ATOMIC_LOAD_NAND:
6988 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
6990 case ISD::ATOMIC_LOAD_OR:
6991 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
6993 case ISD::ATOMIC_LOAD_SUB:
6994 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
6996 case ISD::ATOMIC_LOAD_XOR:
6997 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
6999 case ISD::ATOMIC_SWAP:
7000 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7005 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7007 default: return NULL;
7008 case X86ISD::BSF: return "X86ISD::BSF";
7009 case X86ISD::BSR: return "X86ISD::BSR";
7010 case X86ISD::SHLD: return "X86ISD::SHLD";
7011 case X86ISD::SHRD: return "X86ISD::SHRD";
7012 case X86ISD::FAND: return "X86ISD::FAND";
7013 case X86ISD::FOR: return "X86ISD::FOR";
7014 case X86ISD::FXOR: return "X86ISD::FXOR";
7015 case X86ISD::FSRL: return "X86ISD::FSRL";
7016 case X86ISD::FILD: return "X86ISD::FILD";
7017 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7018 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7019 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7020 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7021 case X86ISD::FLD: return "X86ISD::FLD";
7022 case X86ISD::FST: return "X86ISD::FST";
7023 case X86ISD::CALL: return "X86ISD::CALL";
7024 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
7025 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7026 case X86ISD::BT: return "X86ISD::BT";
7027 case X86ISD::CMP: return "X86ISD::CMP";
7028 case X86ISD::COMI: return "X86ISD::COMI";
7029 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7030 case X86ISD::SETCC: return "X86ISD::SETCC";
7031 case X86ISD::CMOV: return "X86ISD::CMOV";
7032 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7033 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7034 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7035 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7036 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7037 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7038 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7039 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7040 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7041 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7042 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7043 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7044 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7045 case X86ISD::FMAX: return "X86ISD::FMAX";
7046 case X86ISD::FMIN: return "X86ISD::FMIN";
7047 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7048 case X86ISD::FRCP: return "X86ISD::FRCP";
7049 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7050 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7051 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7052 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7053 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7054 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7055 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7056 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7057 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7058 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7059 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7060 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7061 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7062 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7063 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7064 case X86ISD::VSHL: return "X86ISD::VSHL";
7065 case X86ISD::VSRL: return "X86ISD::VSRL";
7066 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7067 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7068 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7069 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7070 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7071 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7072 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7073 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7074 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7075 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7076 case X86ISD::ADD: return "X86ISD::ADD";
7077 case X86ISD::SUB: return "X86ISD::SUB";
7078 case X86ISD::SMUL: return "X86ISD::SMUL";
7079 case X86ISD::UMUL: return "X86ISD::UMUL";
7080 case X86ISD::INC: return "X86ISD::INC";
7081 case X86ISD::DEC: return "X86ISD::DEC";
7082 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7083 case X86ISD::PTEST: return "X86ISD::PTEST";
7087 // isLegalAddressingMode - Return true if the addressing mode represented
7088 // by AM is legal for this target, for a load/store of the specified type.
7089 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7090 const Type *Ty) const {
7091 // X86 supports extremely general addressing modes.
7093 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7094 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
7099 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7101 // If a reference to this global requires an extra load, we can't fold it.
7102 if (isGlobalStubReference(GVFlags))
7105 // If BaseGV requires a register for the PIC base, we cannot also have a
7106 // BaseReg specified.
7107 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7110 // X86-64 only supports addr of globals in small code model.
7111 if (Subtarget->is64Bit()) {
7112 if (getTargetMachine().getCodeModel() != CodeModel::Small)
7114 // If lower 4G is not available, then we must use rip-relative addressing.
7115 if (AM.BaseOffs || AM.Scale > 1)
7126 // These scales always work.
7131 // These scales are formed with basereg+scalereg. Only accept if there is
7136 default: // Other stuff never works.
7144 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7145 if (!Ty1->isInteger() || !Ty2->isInteger())
7147 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7148 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7149 if (NumBits1 <= NumBits2)
7151 return Subtarget->is64Bit() || NumBits1 < 64;
7154 bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
7155 if (!VT1.isInteger() || !VT2.isInteger())
7157 unsigned NumBits1 = VT1.getSizeInBits();
7158 unsigned NumBits2 = VT2.getSizeInBits();
7159 if (NumBits1 <= NumBits2)
7161 return Subtarget->is64Bit() || NumBits1 < 64;
7164 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7165 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7166 return Ty1 == Type::Int32Ty && Ty2 == Type::Int64Ty && Subtarget->is64Bit();
7169 bool X86TargetLowering::isZExtFree(MVT VT1, MVT VT2) const {
7170 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7171 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7174 bool X86TargetLowering::isNarrowingProfitable(MVT VT1, MVT VT2) const {
7175 // i16 instructions are longer (0x66 prefix) and potentially slower.
7176 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7179 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7180 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7181 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7182 /// are assumed to be legal.
7184 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7186 // Only do shuffles on 128-bit vector types for now.
7187 if (VT.getSizeInBits() == 64)
7190 // FIXME: pshufb, blends, palignr, shifts.
7191 return (VT.getVectorNumElements() == 2 ||
7192 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7193 isMOVLMask(M, VT) ||
7194 isSHUFPMask(M, VT) ||
7195 isPSHUFDMask(M, VT) ||
7196 isPSHUFHWMask(M, VT) ||
7197 isPSHUFLWMask(M, VT) ||
7198 isUNPCKLMask(M, VT) ||
7199 isUNPCKHMask(M, VT) ||
7200 isUNPCKL_v_undef_Mask(M, VT) ||
7201 isUNPCKH_v_undef_Mask(M, VT));
7205 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7207 unsigned NumElts = VT.getVectorNumElements();
7208 // FIXME: This collection of masks seems suspect.
7211 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7212 return (isMOVLMask(Mask, VT) ||
7213 isCommutedMOVLMask(Mask, VT, true) ||
7214 isSHUFPMask(Mask, VT) ||
7215 isCommutedSHUFPMask(Mask, VT));
7220 //===----------------------------------------------------------------------===//
7221 // X86 Scheduler Hooks
7222 //===----------------------------------------------------------------------===//
7224 // private utility function
7226 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7227 MachineBasicBlock *MBB,
7235 TargetRegisterClass *RC,
7236 bool invSrc) const {
7237 // For the atomic bitwise operator, we generate
7240 // ld t1 = [bitinstr.addr]
7241 // op t2 = t1, [bitinstr.val]
7243 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7245 // fallthrough -->nextMBB
7246 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7247 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7248 MachineFunction::iterator MBBIter = MBB;
7251 /// First build the CFG
7252 MachineFunction *F = MBB->getParent();
7253 MachineBasicBlock *thisMBB = MBB;
7254 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7255 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7256 F->insert(MBBIter, newMBB);
7257 F->insert(MBBIter, nextMBB);
7259 // Move all successors to thisMBB to nextMBB
7260 nextMBB->transferSuccessors(thisMBB);
7262 // Update thisMBB to fall through to newMBB
7263 thisMBB->addSuccessor(newMBB);
7265 // newMBB jumps to itself and fall through to nextMBB
7266 newMBB->addSuccessor(nextMBB);
7267 newMBB->addSuccessor(newMBB);
7269 // Insert instructions into newMBB based on incoming instruction
7270 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7271 "unexpected number of operands");
7272 DebugLoc dl = bInstr->getDebugLoc();
7273 MachineOperand& destOper = bInstr->getOperand(0);
7274 MachineOperand* argOpers[2 + X86AddrNumOperands];
7275 int numArgs = bInstr->getNumOperands() - 1;
7276 for (int i=0; i < numArgs; ++i)
7277 argOpers[i] = &bInstr->getOperand(i+1);
7279 // x86 address has 4 operands: base, index, scale, and displacement
7280 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7281 int valArgIndx = lastAddrIndx + 1;
7283 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7284 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7285 for (int i=0; i <= lastAddrIndx; ++i)
7286 (*MIB).addOperand(*argOpers[i]);
7288 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7290 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7295 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7296 assert((argOpers[valArgIndx]->isReg() ||
7297 argOpers[valArgIndx]->isImm()) &&
7299 if (argOpers[valArgIndx]->isReg())
7300 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7302 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7304 (*MIB).addOperand(*argOpers[valArgIndx]);
7306 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7309 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7310 for (int i=0; i <= lastAddrIndx; ++i)
7311 (*MIB).addOperand(*argOpers[i]);
7313 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7314 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7316 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7320 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7322 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7326 // private utility function: 64 bit atomics on 32 bit host.
7328 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7329 MachineBasicBlock *MBB,
7334 bool invSrc) const {
7335 // For the atomic bitwise operator, we generate
7336 // thisMBB (instructions are in pairs, except cmpxchg8b)
7337 // ld t1,t2 = [bitinstr.addr]
7339 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7340 // op t5, t6 <- out1, out2, [bitinstr.val]
7341 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7342 // mov ECX, EBX <- t5, t6
7343 // mov EAX, EDX <- t1, t2
7344 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7345 // mov t3, t4 <- EAX, EDX
7347 // result in out1, out2
7348 // fallthrough -->nextMBB
7350 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7351 const unsigned LoadOpc = X86::MOV32rm;
7352 const unsigned copyOpc = X86::MOV32rr;
7353 const unsigned NotOpc = X86::NOT32r;
7354 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7355 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7356 MachineFunction::iterator MBBIter = MBB;
7359 /// First build the CFG
7360 MachineFunction *F = MBB->getParent();
7361 MachineBasicBlock *thisMBB = MBB;
7362 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7363 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7364 F->insert(MBBIter, newMBB);
7365 F->insert(MBBIter, nextMBB);
7367 // Move all successors to thisMBB to nextMBB
7368 nextMBB->transferSuccessors(thisMBB);
7370 // Update thisMBB to fall through to newMBB
7371 thisMBB->addSuccessor(newMBB);
7373 // newMBB jumps to itself and fall through to nextMBB
7374 newMBB->addSuccessor(nextMBB);
7375 newMBB->addSuccessor(newMBB);
7377 DebugLoc dl = bInstr->getDebugLoc();
7378 // Insert instructions into newMBB based on incoming instruction
7379 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7380 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
7381 "unexpected number of operands");
7382 MachineOperand& dest1Oper = bInstr->getOperand(0);
7383 MachineOperand& dest2Oper = bInstr->getOperand(1);
7384 MachineOperand* argOpers[2 + X86AddrNumOperands];
7385 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
7386 argOpers[i] = &bInstr->getOperand(i+2);
7388 // x86 address has 4 operands: base, index, scale, and displacement
7389 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7391 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7392 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
7393 for (int i=0; i <= lastAddrIndx; ++i)
7394 (*MIB).addOperand(*argOpers[i]);
7395 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7396 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
7397 // add 4 to displacement.
7398 for (int i=0; i <= lastAddrIndx-2; ++i)
7399 (*MIB).addOperand(*argOpers[i]);
7400 MachineOperand newOp3 = *(argOpers[3]);
7402 newOp3.setImm(newOp3.getImm()+4);
7404 newOp3.setOffset(newOp3.getOffset()+4);
7405 (*MIB).addOperand(newOp3);
7406 (*MIB).addOperand(*argOpers[lastAddrIndx]);
7408 // t3/4 are defined later, at the bottom of the loop
7409 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
7410 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
7411 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
7412 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
7413 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
7414 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
7416 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
7417 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
7419 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
7420 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
7426 int valArgIndx = lastAddrIndx + 1;
7427 assert((argOpers[valArgIndx]->isReg() ||
7428 argOpers[valArgIndx]->isImm()) &&
7430 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7431 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
7432 if (argOpers[valArgIndx]->isReg())
7433 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
7435 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
7436 if (regOpcL != X86::MOV32rr)
7438 (*MIB).addOperand(*argOpers[valArgIndx]);
7439 assert(argOpers[valArgIndx + 1]->isReg() ==
7440 argOpers[valArgIndx]->isReg());
7441 assert(argOpers[valArgIndx + 1]->isImm() ==
7442 argOpers[valArgIndx]->isImm());
7443 if (argOpers[valArgIndx + 1]->isReg())
7444 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
7446 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
7447 if (regOpcH != X86::MOV32rr)
7449 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
7451 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
7453 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
7456 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
7458 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
7461 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
7462 for (int i=0; i <= lastAddrIndx; ++i)
7463 (*MIB).addOperand(*argOpers[i]);
7465 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7466 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7468 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
7469 MIB.addReg(X86::EAX);
7470 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
7471 MIB.addReg(X86::EDX);
7474 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7476 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7480 // private utility function
7482 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7483 MachineBasicBlock *MBB,
7484 unsigned cmovOpc) const {
7485 // For the atomic min/max operator, we generate
7488 // ld t1 = [min/max.addr]
7489 // mov t2 = [min/max.val]
7491 // cmov[cond] t2 = t1
7493 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7495 // fallthrough -->nextMBB
7497 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7498 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7499 MachineFunction::iterator MBBIter = MBB;
7502 /// First build the CFG
7503 MachineFunction *F = MBB->getParent();
7504 MachineBasicBlock *thisMBB = MBB;
7505 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7506 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7507 F->insert(MBBIter, newMBB);
7508 F->insert(MBBIter, nextMBB);
7510 // Move all successors to thisMBB to nextMBB
7511 nextMBB->transferSuccessors(thisMBB);
7513 // Update thisMBB to fall through to newMBB
7514 thisMBB->addSuccessor(newMBB);
7516 // newMBB jumps to newMBB and fall through to nextMBB
7517 newMBB->addSuccessor(nextMBB);
7518 newMBB->addSuccessor(newMBB);
7520 DebugLoc dl = mInstr->getDebugLoc();
7521 // Insert instructions into newMBB based on incoming instruction
7522 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7523 "unexpected number of operands");
7524 MachineOperand& destOper = mInstr->getOperand(0);
7525 MachineOperand* argOpers[2 + X86AddrNumOperands];
7526 int numArgs = mInstr->getNumOperands() - 1;
7527 for (int i=0; i < numArgs; ++i)
7528 argOpers[i] = &mInstr->getOperand(i+1);
7530 // x86 address has 4 operands: base, index, scale, and displacement
7531 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7532 int valArgIndx = lastAddrIndx + 1;
7534 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7535 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
7536 for (int i=0; i <= lastAddrIndx; ++i)
7537 (*MIB).addOperand(*argOpers[i]);
7539 // We only support register and immediate values
7540 assert((argOpers[valArgIndx]->isReg() ||
7541 argOpers[valArgIndx]->isImm()) &&
7544 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7545 if (argOpers[valArgIndx]->isReg())
7546 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7548 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7549 (*MIB).addOperand(*argOpers[valArgIndx]);
7551 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
7554 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
7559 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7560 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
7564 // Cmp and exchange if none has modified the memory location
7565 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
7566 for (int i=0; i <= lastAddrIndx; ++i)
7567 (*MIB).addOperand(*argOpers[i]);
7569 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7570 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
7572 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
7573 MIB.addReg(X86::EAX);
7576 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7578 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7584 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7585 MachineBasicBlock *BB) const {
7586 DebugLoc dl = MI->getDebugLoc();
7587 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7588 switch (MI->getOpcode()) {
7589 default: assert(false && "Unexpected instr type to insert");
7590 case X86::CMOV_V1I64:
7591 case X86::CMOV_FR32:
7592 case X86::CMOV_FR64:
7593 case X86::CMOV_V4F32:
7594 case X86::CMOV_V2F64:
7595 case X86::CMOV_V2I64: {
7596 // To "insert" a SELECT_CC instruction, we actually have to insert the
7597 // diamond control-flow pattern. The incoming instruction knows the
7598 // destination vreg to set, the condition code register to branch on, the
7599 // true/false values to select between, and a branch opcode to use.
7600 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7601 MachineFunction::iterator It = BB;
7607 // cmpTY ccX, r1, r2
7609 // fallthrough --> copy0MBB
7610 MachineBasicBlock *thisMBB = BB;
7611 MachineFunction *F = BB->getParent();
7612 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7613 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7615 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
7616 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
7617 F->insert(It, copy0MBB);
7618 F->insert(It, sinkMBB);
7619 // Update machine-CFG edges by transferring all successors of the current
7620 // block to the new block which will contain the Phi node for the select.
7621 sinkMBB->transferSuccessors(BB);
7623 // Add the true and fallthrough blocks as its successors.
7624 BB->addSuccessor(copy0MBB);
7625 BB->addSuccessor(sinkMBB);
7628 // %FalseValue = ...
7629 // # fallthrough to sinkMBB
7632 // Update machine-CFG edges
7633 BB->addSuccessor(sinkMBB);
7636 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7639 BuildMI(BB, dl, TII->get(X86::PHI), MI->getOperand(0).getReg())
7640 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7641 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7643 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7647 case X86::FP32_TO_INT16_IN_MEM:
7648 case X86::FP32_TO_INT32_IN_MEM:
7649 case X86::FP32_TO_INT64_IN_MEM:
7650 case X86::FP64_TO_INT16_IN_MEM:
7651 case X86::FP64_TO_INT32_IN_MEM:
7652 case X86::FP64_TO_INT64_IN_MEM:
7653 case X86::FP80_TO_INT16_IN_MEM:
7654 case X86::FP80_TO_INT32_IN_MEM:
7655 case X86::FP80_TO_INT64_IN_MEM: {
7656 // Change the floating point control register to use "round towards zero"
7657 // mode when truncating to an integer value.
7658 MachineFunction *F = BB->getParent();
7659 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
7660 addFrameReference(BuildMI(BB, dl, TII->get(X86::FNSTCW16m)), CWFrameIdx);
7662 // Load the old value of the high byte of the control word...
7664 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
7665 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW),
7668 // Set the high part to be round to zero...
7669 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mi)), CWFrameIdx)
7672 // Reload the modified control word now...
7673 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
7675 // Restore the memory image of control word to original value
7676 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mr)), CWFrameIdx)
7679 // Get the X86 opcode to use.
7681 switch (MI->getOpcode()) {
7682 default: llvm_unreachable("illegal opcode!");
7683 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
7684 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
7685 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
7686 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
7687 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
7688 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
7689 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
7690 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
7691 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
7695 MachineOperand &Op = MI->getOperand(0);
7697 AM.BaseType = X86AddressMode::RegBase;
7698 AM.Base.Reg = Op.getReg();
7700 AM.BaseType = X86AddressMode::FrameIndexBase;
7701 AM.Base.FrameIndex = Op.getIndex();
7703 Op = MI->getOperand(1);
7705 AM.Scale = Op.getImm();
7706 Op = MI->getOperand(2);
7708 AM.IndexReg = Op.getImm();
7709 Op = MI->getOperand(3);
7710 if (Op.isGlobal()) {
7711 AM.GV = Op.getGlobal();
7713 AM.Disp = Op.getImm();
7715 addFullAddress(BuildMI(BB, dl, TII->get(Opc)), AM)
7716 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
7718 // Reload the original control word now.
7719 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
7721 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7724 case X86::ATOMAND32:
7725 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7726 X86::AND32ri, X86::MOV32rm,
7727 X86::LCMPXCHG32, X86::MOV32rr,
7728 X86::NOT32r, X86::EAX,
7729 X86::GR32RegisterClass);
7731 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
7732 X86::OR32ri, X86::MOV32rm,
7733 X86::LCMPXCHG32, X86::MOV32rr,
7734 X86::NOT32r, X86::EAX,
7735 X86::GR32RegisterClass);
7736 case X86::ATOMXOR32:
7737 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
7738 X86::XOR32ri, X86::MOV32rm,
7739 X86::LCMPXCHG32, X86::MOV32rr,
7740 X86::NOT32r, X86::EAX,
7741 X86::GR32RegisterClass);
7742 case X86::ATOMNAND32:
7743 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7744 X86::AND32ri, X86::MOV32rm,
7745 X86::LCMPXCHG32, X86::MOV32rr,
7746 X86::NOT32r, X86::EAX,
7747 X86::GR32RegisterClass, true);
7748 case X86::ATOMMIN32:
7749 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
7750 case X86::ATOMMAX32:
7751 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
7752 case X86::ATOMUMIN32:
7753 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
7754 case X86::ATOMUMAX32:
7755 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
7757 case X86::ATOMAND16:
7758 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7759 X86::AND16ri, X86::MOV16rm,
7760 X86::LCMPXCHG16, X86::MOV16rr,
7761 X86::NOT16r, X86::AX,
7762 X86::GR16RegisterClass);
7764 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
7765 X86::OR16ri, X86::MOV16rm,
7766 X86::LCMPXCHG16, X86::MOV16rr,
7767 X86::NOT16r, X86::AX,
7768 X86::GR16RegisterClass);
7769 case X86::ATOMXOR16:
7770 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
7771 X86::XOR16ri, X86::MOV16rm,
7772 X86::LCMPXCHG16, X86::MOV16rr,
7773 X86::NOT16r, X86::AX,
7774 X86::GR16RegisterClass);
7775 case X86::ATOMNAND16:
7776 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7777 X86::AND16ri, X86::MOV16rm,
7778 X86::LCMPXCHG16, X86::MOV16rr,
7779 X86::NOT16r, X86::AX,
7780 X86::GR16RegisterClass, true);
7781 case X86::ATOMMIN16:
7782 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
7783 case X86::ATOMMAX16:
7784 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
7785 case X86::ATOMUMIN16:
7786 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
7787 case X86::ATOMUMAX16:
7788 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
7791 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7792 X86::AND8ri, X86::MOV8rm,
7793 X86::LCMPXCHG8, X86::MOV8rr,
7794 X86::NOT8r, X86::AL,
7795 X86::GR8RegisterClass);
7797 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
7798 X86::OR8ri, X86::MOV8rm,
7799 X86::LCMPXCHG8, X86::MOV8rr,
7800 X86::NOT8r, X86::AL,
7801 X86::GR8RegisterClass);
7803 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
7804 X86::XOR8ri, X86::MOV8rm,
7805 X86::LCMPXCHG8, X86::MOV8rr,
7806 X86::NOT8r, X86::AL,
7807 X86::GR8RegisterClass);
7808 case X86::ATOMNAND8:
7809 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7810 X86::AND8ri, X86::MOV8rm,
7811 X86::LCMPXCHG8, X86::MOV8rr,
7812 X86::NOT8r, X86::AL,
7813 X86::GR8RegisterClass, true);
7814 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
7815 // This group is for 64-bit host.
7816 case X86::ATOMAND64:
7817 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7818 X86::AND64ri32, X86::MOV64rm,
7819 X86::LCMPXCHG64, X86::MOV64rr,
7820 X86::NOT64r, X86::RAX,
7821 X86::GR64RegisterClass);
7823 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
7824 X86::OR64ri32, X86::MOV64rm,
7825 X86::LCMPXCHG64, X86::MOV64rr,
7826 X86::NOT64r, X86::RAX,
7827 X86::GR64RegisterClass);
7828 case X86::ATOMXOR64:
7829 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
7830 X86::XOR64ri32, X86::MOV64rm,
7831 X86::LCMPXCHG64, X86::MOV64rr,
7832 X86::NOT64r, X86::RAX,
7833 X86::GR64RegisterClass);
7834 case X86::ATOMNAND64:
7835 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7836 X86::AND64ri32, X86::MOV64rm,
7837 X86::LCMPXCHG64, X86::MOV64rr,
7838 X86::NOT64r, X86::RAX,
7839 X86::GR64RegisterClass, true);
7840 case X86::ATOMMIN64:
7841 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
7842 case X86::ATOMMAX64:
7843 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
7844 case X86::ATOMUMIN64:
7845 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
7846 case X86::ATOMUMAX64:
7847 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
7849 // This group does 64-bit operations on a 32-bit host.
7850 case X86::ATOMAND6432:
7851 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7852 X86::AND32rr, X86::AND32rr,
7853 X86::AND32ri, X86::AND32ri,
7855 case X86::ATOMOR6432:
7856 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7857 X86::OR32rr, X86::OR32rr,
7858 X86::OR32ri, X86::OR32ri,
7860 case X86::ATOMXOR6432:
7861 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7862 X86::XOR32rr, X86::XOR32rr,
7863 X86::XOR32ri, X86::XOR32ri,
7865 case X86::ATOMNAND6432:
7866 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7867 X86::AND32rr, X86::AND32rr,
7868 X86::AND32ri, X86::AND32ri,
7870 case X86::ATOMADD6432:
7871 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7872 X86::ADD32rr, X86::ADC32rr,
7873 X86::ADD32ri, X86::ADC32ri,
7875 case X86::ATOMSUB6432:
7876 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7877 X86::SUB32rr, X86::SBB32rr,
7878 X86::SUB32ri, X86::SBB32ri,
7880 case X86::ATOMSWAP6432:
7881 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7882 X86::MOV32rr, X86::MOV32rr,
7883 X86::MOV32ri, X86::MOV32ri,
7888 //===----------------------------------------------------------------------===//
7889 // X86 Optimization Hooks
7890 //===----------------------------------------------------------------------===//
7892 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7896 const SelectionDAG &DAG,
7897 unsigned Depth) const {
7898 unsigned Opc = Op.getOpcode();
7899 assert((Opc >= ISD::BUILTIN_OP_END ||
7900 Opc == ISD::INTRINSIC_WO_CHAIN ||
7901 Opc == ISD::INTRINSIC_W_CHAIN ||
7902 Opc == ISD::INTRINSIC_VOID) &&
7903 "Should use MaskedValueIsZero if you don't know whether Op"
7904 " is a target node!");
7906 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
7915 // These nodes' second result is a boolean.
7916 if (Op.getResNo() == 0)
7920 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
7921 Mask.getBitWidth() - 1);
7926 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
7927 /// node is a GlobalAddress + offset.
7928 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
7929 GlobalValue* &GA, int64_t &Offset) const{
7930 if (N->getOpcode() == X86ISD::Wrapper) {
7931 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
7932 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
7933 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
7937 return TargetLowering::isGAPlusOffset(N, GA, Offset);
7940 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
7941 const TargetLowering &TLI) {
7944 if (TLI.isGAPlusOffset(Base, GV, Offset))
7945 return (GV->getAlignment() >= N && (Offset % N) == 0);
7946 // DAG combine handles the stack object case.
7950 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
7951 MVT EVT, LoadSDNode *&LDBase,
7952 unsigned &LastLoadedElt,
7953 SelectionDAG &DAG, MachineFrameInfo *MFI,
7954 const TargetLowering &TLI) {
7956 LastLoadedElt = -1U;
7957 for (unsigned i = 0; i < NumElems; ++i) {
7958 if (N->getMaskElt(i) < 0) {
7964 SDValue Elt = DAG.getShuffleScalarElt(N, i);
7965 if (!Elt.getNode() ||
7966 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
7969 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
7971 LDBase = cast<LoadSDNode>(Elt.getNode());
7975 if (Elt.getOpcode() == ISD::UNDEF)
7978 LoadSDNode *LD = cast<LoadSDNode>(Elt);
7979 if (!TLI.isConsecutiveLoad(LD, LDBase, EVT.getSizeInBits()/8, i, MFI))
7986 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
7987 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
7988 /// if the load addresses are consecutive, non-overlapping, and in the right
7989 /// order. In the case of v2i64, it will see if it can rewrite the
7990 /// shuffle to be an appropriate build vector so it can take advantage of
7991 // performBuildVectorCombine.
7992 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
7993 const TargetLowering &TLI) {
7994 DebugLoc dl = N->getDebugLoc();
7995 MVT VT = N->getValueType(0);
7996 MVT EVT = VT.getVectorElementType();
7997 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7998 unsigned NumElems = VT.getVectorNumElements();
8000 if (VT.getSizeInBits() != 128)
8003 // Try to combine a vector_shuffle into a 128-bit load.
8004 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8005 LoadSDNode *LD = NULL;
8006 unsigned LastLoadedElt;
8007 if (!EltsFromConsecutiveLoads(SVN, NumElems, EVT, LD, LastLoadedElt, DAG,
8011 if (LastLoadedElt == NumElems - 1) {
8012 if (isBaseAlignmentOfN(16, LD->getBasePtr().getNode(), TLI))
8013 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8014 LD->getSrcValue(), LD->getSrcValueOffset(),
8016 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8017 LD->getSrcValue(), LD->getSrcValueOffset(),
8018 LD->isVolatile(), LD->getAlignment());
8019 } else if (NumElems == 4 && LastLoadedElt == 1) {
8020 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8021 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8022 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8023 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8028 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8029 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8030 const X86Subtarget *Subtarget) {
8031 DebugLoc DL = N->getDebugLoc();
8032 SDValue Cond = N->getOperand(0);
8033 // Get the LHS/RHS of the select.
8034 SDValue LHS = N->getOperand(1);
8035 SDValue RHS = N->getOperand(2);
8037 // If we have SSE[12] support, try to form min/max nodes.
8038 if (Subtarget->hasSSE2() &&
8039 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8040 Cond.getOpcode() == ISD::SETCC) {
8041 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8043 unsigned Opcode = 0;
8044 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
8047 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
8050 if (!UnsafeFPMath) break;
8052 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
8054 Opcode = X86ISD::FMIN;
8057 case ISD::SETOGT: // (X > Y) ? X : Y -> max
8060 if (!UnsafeFPMath) break;
8062 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
8064 Opcode = X86ISD::FMAX;
8067 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8070 case ISD::SETOGT: // (X > Y) ? Y : X -> min
8073 if (!UnsafeFPMath) break;
8075 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
8077 Opcode = X86ISD::FMIN;
8080 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
8083 if (!UnsafeFPMath) break;
8085 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
8087 Opcode = X86ISD::FMAX;
8093 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8096 // If this is a select between two integer constants, try to do some
8098 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8099 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8100 // Don't do this for crazy integer types.
8101 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8102 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8103 // so that TrueC (the true value) is larger than FalseC.
8104 bool NeedsCondInvert = false;
8106 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8107 // Efficiently invertible.
8108 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
8109 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
8110 isa<ConstantSDNode>(Cond.getOperand(1))))) {
8111 NeedsCondInvert = true;
8112 std::swap(TrueC, FalseC);
8115 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
8116 if (FalseC->getAPIntValue() == 0 &&
8117 TrueC->getAPIntValue().isPowerOf2()) {
8118 if (NeedsCondInvert) // Invert the condition if needed.
8119 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8120 DAG.getConstant(1, Cond.getValueType()));
8122 // Zero extend the condition if needed.
8123 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8125 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8126 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
8127 DAG.getConstant(ShAmt, MVT::i8));
8130 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
8131 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8132 if (NeedsCondInvert) // Invert the condition if needed.
8133 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8134 DAG.getConstant(1, Cond.getValueType()));
8136 // Zero extend the condition if needed.
8137 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8138 FalseC->getValueType(0), Cond);
8139 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8140 SDValue(FalseC, 0));
8143 // Optimize cases that will turn into an LEA instruction. This requires
8144 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8145 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8146 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8147 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8149 bool isFastMultiplier = false;
8151 switch ((unsigned char)Diff) {
8153 case 1: // result = add base, cond
8154 case 2: // result = lea base( , cond*2)
8155 case 3: // result = lea base(cond, cond*2)
8156 case 4: // result = lea base( , cond*4)
8157 case 5: // result = lea base(cond, cond*4)
8158 case 8: // result = lea base( , cond*8)
8159 case 9: // result = lea base(cond, cond*8)
8160 isFastMultiplier = true;
8165 if (isFastMultiplier) {
8166 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8167 if (NeedsCondInvert) // Invert the condition if needed.
8168 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8169 DAG.getConstant(1, Cond.getValueType()));
8171 // Zero extend the condition if needed.
8172 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8174 // Scale the condition by the difference.
8176 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8177 DAG.getConstant(Diff, Cond.getValueType()));
8179 // Add the base if non-zero.
8180 if (FalseC->getAPIntValue() != 0)
8181 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8182 SDValue(FalseC, 0));
8192 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
8193 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
8194 TargetLowering::DAGCombinerInfo &DCI) {
8195 DebugLoc DL = N->getDebugLoc();
8197 // If the flag operand isn't dead, don't touch this CMOV.
8198 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
8201 // If this is a select between two integer constants, try to do some
8202 // optimizations. Note that the operands are ordered the opposite of SELECT
8204 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
8205 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8206 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
8207 // larger than FalseC (the false value).
8208 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
8210 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
8211 CC = X86::GetOppositeBranchCondition(CC);
8212 std::swap(TrueC, FalseC);
8215 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
8216 // This is efficient for any integer data type (including i8/i16) and
8218 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
8219 SDValue Cond = N->getOperand(3);
8220 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8221 DAG.getConstant(CC, MVT::i8), Cond);
8223 // Zero extend the condition if needed.
8224 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
8226 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8227 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
8228 DAG.getConstant(ShAmt, MVT::i8));
8229 if (N->getNumValues() == 2) // Dead flag value?
8230 return DCI.CombineTo(N, Cond, SDValue());
8234 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
8235 // for any integer data type, including i8/i16.
8236 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8237 SDValue Cond = N->getOperand(3);
8238 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8239 DAG.getConstant(CC, MVT::i8), Cond);
8241 // Zero extend the condition if needed.
8242 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8243 FalseC->getValueType(0), Cond);
8244 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8245 SDValue(FalseC, 0));
8247 if (N->getNumValues() == 2) // Dead flag value?
8248 return DCI.CombineTo(N, Cond, SDValue());
8252 // Optimize cases that will turn into an LEA instruction. This requires
8253 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8254 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8255 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8256 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8258 bool isFastMultiplier = false;
8260 switch ((unsigned char)Diff) {
8262 case 1: // result = add base, cond
8263 case 2: // result = lea base( , cond*2)
8264 case 3: // result = lea base(cond, cond*2)
8265 case 4: // result = lea base( , cond*4)
8266 case 5: // result = lea base(cond, cond*4)
8267 case 8: // result = lea base( , cond*8)
8268 case 9: // result = lea base(cond, cond*8)
8269 isFastMultiplier = true;
8274 if (isFastMultiplier) {
8275 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8276 SDValue Cond = N->getOperand(3);
8277 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8278 DAG.getConstant(CC, MVT::i8), Cond);
8279 // Zero extend the condition if needed.
8280 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8282 // Scale the condition by the difference.
8284 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8285 DAG.getConstant(Diff, Cond.getValueType()));
8287 // Add the base if non-zero.
8288 if (FalseC->getAPIntValue() != 0)
8289 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8290 SDValue(FalseC, 0));
8291 if (N->getNumValues() == 2) // Dead flag value?
8292 return DCI.CombineTo(N, Cond, SDValue());
8302 /// PerformMulCombine - Optimize a single multiply with constant into two
8303 /// in order to implement it with two cheaper instructions, e.g.
8304 /// LEA + SHL, LEA + LEA.
8305 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
8306 TargetLowering::DAGCombinerInfo &DCI) {
8307 if (DAG.getMachineFunction().
8308 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
8311 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8314 MVT VT = N->getValueType(0);
8318 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8321 uint64_t MulAmt = C->getZExtValue();
8322 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
8325 uint64_t MulAmt1 = 0;
8326 uint64_t MulAmt2 = 0;
8327 if ((MulAmt % 9) == 0) {
8329 MulAmt2 = MulAmt / 9;
8330 } else if ((MulAmt % 5) == 0) {
8332 MulAmt2 = MulAmt / 5;
8333 } else if ((MulAmt % 3) == 0) {
8335 MulAmt2 = MulAmt / 3;
8338 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
8339 DebugLoc DL = N->getDebugLoc();
8341 if (isPowerOf2_64(MulAmt2) &&
8342 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
8343 // If second multiplifer is pow2, issue it first. We want the multiply by
8344 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
8346 std::swap(MulAmt1, MulAmt2);
8349 if (isPowerOf2_64(MulAmt1))
8350 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
8351 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
8353 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
8354 DAG.getConstant(MulAmt1, VT));
8356 if (isPowerOf2_64(MulAmt2))
8357 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
8358 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
8360 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
8361 DAG.getConstant(MulAmt2, VT));
8363 // Do not add new nodes to DAG combiner worklist.
8364 DCI.CombineTo(N, NewMul, false);
8370 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
8372 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
8373 const X86Subtarget *Subtarget) {
8374 // On X86 with SSE2 support, we can transform this to a vector shift if
8375 // all elements are shifted by the same amount. We can't do this in legalize
8376 // because the a constant vector is typically transformed to a constant pool
8377 // so we have no knowledge of the shift amount.
8378 if (!Subtarget->hasSSE2())
8381 MVT VT = N->getValueType(0);
8382 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
8385 SDValue ShAmtOp = N->getOperand(1);
8386 MVT EltVT = VT.getVectorElementType();
8387 DebugLoc DL = N->getDebugLoc();
8389 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
8390 unsigned NumElts = VT.getVectorNumElements();
8392 for (; i != NumElts; ++i) {
8393 SDValue Arg = ShAmtOp.getOperand(i);
8394 if (Arg.getOpcode() == ISD::UNDEF) continue;
8398 for (; i != NumElts; ++i) {
8399 SDValue Arg = ShAmtOp.getOperand(i);
8400 if (Arg.getOpcode() == ISD::UNDEF) continue;
8401 if (Arg != BaseShAmt) {
8405 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
8406 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
8407 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
8408 DAG.getIntPtrConstant(0));
8412 if (EltVT.bitsGT(MVT::i32))
8413 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
8414 else if (EltVT.bitsLT(MVT::i32))
8415 BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, BaseShAmt);
8417 // The shift amount is identical so we can do a vector shift.
8418 SDValue ValOp = N->getOperand(0);
8419 switch (N->getOpcode()) {
8421 llvm_unreachable("Unknown shift opcode!");
8424 if (VT == MVT::v2i64)
8425 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8426 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8428 if (VT == MVT::v4i32)
8429 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8430 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8432 if (VT == MVT::v8i16)
8433 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8434 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8438 if (VT == MVT::v4i32)
8439 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8440 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
8442 if (VT == MVT::v8i16)
8443 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8444 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
8448 if (VT == MVT::v2i64)
8449 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8450 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8452 if (VT == MVT::v4i32)
8453 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8454 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
8456 if (VT == MVT::v8i16)
8457 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8458 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
8465 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
8466 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
8467 const X86Subtarget *Subtarget) {
8468 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
8469 // the FP state in cases where an emms may be missing.
8470 // A preferable solution to the general problem is to figure out the right
8471 // places to insert EMMS. This qualifies as a quick hack.
8473 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
8474 StoreSDNode *St = cast<StoreSDNode>(N);
8475 MVT VT = St->getValue().getValueType();
8476 if (VT.getSizeInBits() != 64)
8479 const Function *F = DAG.getMachineFunction().getFunction();
8480 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
8481 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
8482 && Subtarget->hasSSE2();
8483 if ((VT.isVector() ||
8484 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
8485 isa<LoadSDNode>(St->getValue()) &&
8486 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
8487 St->getChain().hasOneUse() && !St->isVolatile()) {
8488 SDNode* LdVal = St->getValue().getNode();
8490 int TokenFactorIndex = -1;
8491 SmallVector<SDValue, 8> Ops;
8492 SDNode* ChainVal = St->getChain().getNode();
8493 // Must be a store of a load. We currently handle two cases: the load
8494 // is a direct child, and it's under an intervening TokenFactor. It is
8495 // possible to dig deeper under nested TokenFactors.
8496 if (ChainVal == LdVal)
8497 Ld = cast<LoadSDNode>(St->getChain());
8498 else if (St->getValue().hasOneUse() &&
8499 ChainVal->getOpcode() == ISD::TokenFactor) {
8500 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
8501 if (ChainVal->getOperand(i).getNode() == LdVal) {
8502 TokenFactorIndex = i;
8503 Ld = cast<LoadSDNode>(St->getValue());
8505 Ops.push_back(ChainVal->getOperand(i));
8509 if (!Ld || !ISD::isNormalLoad(Ld))
8512 // If this is not the MMX case, i.e. we are just turning i64 load/store
8513 // into f64 load/store, avoid the transformation if there are multiple
8514 // uses of the loaded value.
8515 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
8518 DebugLoc LdDL = Ld->getDebugLoc();
8519 DebugLoc StDL = N->getDebugLoc();
8520 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
8521 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
8523 if (Subtarget->is64Bit() || F64IsLegal) {
8524 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
8525 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
8526 Ld->getBasePtr(), Ld->getSrcValue(),
8527 Ld->getSrcValueOffset(), Ld->isVolatile(),
8528 Ld->getAlignment());
8529 SDValue NewChain = NewLd.getValue(1);
8530 if (TokenFactorIndex != -1) {
8531 Ops.push_back(NewChain);
8532 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
8535 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
8536 St->getSrcValue(), St->getSrcValueOffset(),
8537 St->isVolatile(), St->getAlignment());
8540 // Otherwise, lower to two pairs of 32-bit loads / stores.
8541 SDValue LoAddr = Ld->getBasePtr();
8542 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
8543 DAG.getConstant(4, MVT::i32));
8545 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
8546 Ld->getSrcValue(), Ld->getSrcValueOffset(),
8547 Ld->isVolatile(), Ld->getAlignment());
8548 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
8549 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
8551 MinAlign(Ld->getAlignment(), 4));
8553 SDValue NewChain = LoLd.getValue(1);
8554 if (TokenFactorIndex != -1) {
8555 Ops.push_back(LoLd);
8556 Ops.push_back(HiLd);
8557 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
8561 LoAddr = St->getBasePtr();
8562 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
8563 DAG.getConstant(4, MVT::i32));
8565 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
8566 St->getSrcValue(), St->getSrcValueOffset(),
8567 St->isVolatile(), St->getAlignment());
8568 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
8570 St->getSrcValueOffset() + 4,
8572 MinAlign(St->getAlignment(), 4));
8573 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
8578 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
8579 /// X86ISD::FXOR nodes.
8580 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
8581 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
8582 // F[X]OR(0.0, x) -> x
8583 // F[X]OR(x, 0.0) -> x
8584 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8585 if (C->getValueAPF().isPosZero())
8586 return N->getOperand(1);
8587 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8588 if (C->getValueAPF().isPosZero())
8589 return N->getOperand(0);
8593 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
8594 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
8595 // FAND(0.0, x) -> 0.0
8596 // FAND(x, 0.0) -> 0.0
8597 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8598 if (C->getValueAPF().isPosZero())
8599 return N->getOperand(0);
8600 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8601 if (C->getValueAPF().isPosZero())
8602 return N->getOperand(1);
8606 static SDValue PerformBTCombine(SDNode *N,
8608 TargetLowering::DAGCombinerInfo &DCI) {
8609 // BT ignores high bits in the bit index operand.
8610 SDValue Op1 = N->getOperand(1);
8611 if (Op1.hasOneUse()) {
8612 unsigned BitWidth = Op1.getValueSizeInBits();
8613 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
8614 APInt KnownZero, KnownOne;
8615 TargetLowering::TargetLoweringOpt TLO(DAG);
8616 TargetLowering &TLI = DAG.getTargetLoweringInfo();
8617 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
8618 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
8619 DCI.CommitTargetLoweringOpt(TLO);
8624 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
8625 SDValue Op = N->getOperand(0);
8626 if (Op.getOpcode() == ISD::BIT_CONVERT)
8627 Op = Op.getOperand(0);
8628 MVT VT = N->getValueType(0), OpVT = Op.getValueType();
8629 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
8630 VT.getVectorElementType().getSizeInBits() ==
8631 OpVT.getVectorElementType().getSizeInBits()) {
8632 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
8637 // On X86 and X86-64, atomic operations are lowered to locked instructions.
8638 // Locked instructions, in turn, have implicit fence semantics (all memory
8639 // operations are flushed before issuing the locked instruction, and the
8640 // are not buffered), so we can fold away the common pattern of
8641 // fence-atomic-fence.
8642 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
8643 SDValue atomic = N->getOperand(0);
8644 switch (atomic.getOpcode()) {
8645 case ISD::ATOMIC_CMP_SWAP:
8646 case ISD::ATOMIC_SWAP:
8647 case ISD::ATOMIC_LOAD_ADD:
8648 case ISD::ATOMIC_LOAD_SUB:
8649 case ISD::ATOMIC_LOAD_AND:
8650 case ISD::ATOMIC_LOAD_OR:
8651 case ISD::ATOMIC_LOAD_XOR:
8652 case ISD::ATOMIC_LOAD_NAND:
8653 case ISD::ATOMIC_LOAD_MIN:
8654 case ISD::ATOMIC_LOAD_MAX:
8655 case ISD::ATOMIC_LOAD_UMIN:
8656 case ISD::ATOMIC_LOAD_UMAX:
8662 SDValue fence = atomic.getOperand(0);
8663 if (fence.getOpcode() != ISD::MEMBARRIER)
8666 switch (atomic.getOpcode()) {
8667 case ISD::ATOMIC_CMP_SWAP:
8668 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
8669 atomic.getOperand(1), atomic.getOperand(2),
8670 atomic.getOperand(3));
8671 case ISD::ATOMIC_SWAP:
8672 case ISD::ATOMIC_LOAD_ADD:
8673 case ISD::ATOMIC_LOAD_SUB:
8674 case ISD::ATOMIC_LOAD_AND:
8675 case ISD::ATOMIC_LOAD_OR:
8676 case ISD::ATOMIC_LOAD_XOR:
8677 case ISD::ATOMIC_LOAD_NAND:
8678 case ISD::ATOMIC_LOAD_MIN:
8679 case ISD::ATOMIC_LOAD_MAX:
8680 case ISD::ATOMIC_LOAD_UMIN:
8681 case ISD::ATOMIC_LOAD_UMAX:
8682 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
8683 atomic.getOperand(1), atomic.getOperand(2));
8689 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
8690 DAGCombinerInfo &DCI) const {
8691 SelectionDAG &DAG = DCI.DAG;
8692 switch (N->getOpcode()) {
8694 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
8695 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
8696 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
8697 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
8700 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
8701 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
8703 case X86ISD::FOR: return PerformFORCombine(N, DAG);
8704 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
8705 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
8706 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
8707 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
8713 //===----------------------------------------------------------------------===//
8714 // X86 Inline Assembly Support
8715 //===----------------------------------------------------------------------===//
8717 static bool LowerToBSwap(CallInst *CI) {
8718 // FIXME: this should verify that we are targetting a 486 or better. If not,
8719 // we will turn this bswap into something that will be lowered to logical ops
8720 // instead of emitting the bswap asm. For now, we don't support 486 or lower
8721 // so don't worry about this.
8723 // Verify this is a simple bswap.
8724 if (CI->getNumOperands() != 2 ||
8725 CI->getType() != CI->getOperand(1)->getType() ||
8726 !CI->getType()->isInteger())
8729 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
8730 if (!Ty || Ty->getBitWidth() % 16 != 0)
8733 // Okay, we can do this xform, do so now.
8734 const Type *Tys[] = { Ty };
8735 Module *M = CI->getParent()->getParent()->getParent();
8736 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
8738 Value *Op = CI->getOperand(1);
8739 Op = CallInst::Create(Int, Op, CI->getName(), CI);
8741 CI->replaceAllUsesWith(Op);
8742 CI->eraseFromParent();
8746 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
8747 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
8748 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
8750 std::string AsmStr = IA->getAsmString();
8752 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
8753 std::vector<std::string> AsmPieces;
8754 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
8756 switch (AsmPieces.size()) {
8757 default: return false;
8759 AsmStr = AsmPieces[0];
8761 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
8764 if (AsmPieces.size() == 2 &&
8765 (AsmPieces[0] == "bswap" ||
8766 AsmPieces[0] == "bswapq" ||
8767 AsmPieces[0] == "bswapl") &&
8768 (AsmPieces[1] == "$0" ||
8769 AsmPieces[1] == "${0:q}")) {
8770 // No need to check constraints, nothing other than the equivalent of
8771 // "=r,0" would be valid here.
8772 return LowerToBSwap(CI);
8774 // rorw $$8, ${0:w} --> llvm.bswap.i16
8775 if (CI->getType() == Type::Int16Ty &&
8776 AsmPieces.size() == 3 &&
8777 AsmPieces[0] == "rorw" &&
8778 AsmPieces[1] == "$$8," &&
8779 AsmPieces[2] == "${0:w}" &&
8780 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
8781 return LowerToBSwap(CI);
8785 if (CI->getType() == Type::Int64Ty && Constraints.size() >= 2 &&
8786 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
8787 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
8788 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
8789 std::vector<std::string> Words;
8790 SplitString(AsmPieces[0], Words, " \t");
8791 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
8793 SplitString(AsmPieces[1], Words, " \t");
8794 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
8796 SplitString(AsmPieces[2], Words, " \t,");
8797 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
8798 Words[2] == "%edx") {
8799 return LowerToBSwap(CI);
8811 /// getConstraintType - Given a constraint letter, return the type of
8812 /// constraint it is for this target.
8813 X86TargetLowering::ConstraintType
8814 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
8815 if (Constraint.size() == 1) {
8816 switch (Constraint[0]) {
8828 return C_RegisterClass;
8836 return TargetLowering::getConstraintType(Constraint);
8839 /// LowerXConstraint - try to replace an X constraint, which matches anything,
8840 /// with another that has more specific requirements based on the type of the
8841 /// corresponding operand.
8842 const char *X86TargetLowering::
8843 LowerXConstraint(MVT ConstraintVT) const {
8844 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
8845 // 'f' like normal targets.
8846 if (ConstraintVT.isFloatingPoint()) {
8847 if (Subtarget->hasSSE2())
8849 if (Subtarget->hasSSE1())
8853 return TargetLowering::LowerXConstraint(ConstraintVT);
8856 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8857 /// vector. If it is invalid, don't add anything to Ops.
8858 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8861 std::vector<SDValue>&Ops,
8862 SelectionDAG &DAG) const {
8863 SDValue Result(0, 0);
8865 switch (Constraint) {
8868 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8869 if (C->getZExtValue() <= 31) {
8870 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8876 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8877 if (C->getZExtValue() <= 63) {
8878 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8884 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8885 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
8886 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8892 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8893 if (C->getZExtValue() <= 255) {
8894 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8900 // 32-bit signed value
8901 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8902 const ConstantInt *CI = C->getConstantIntValue();
8903 if (CI->isValueValidForType(Type::Int32Ty, C->getSExtValue())) {
8904 // Widen to 64 bits here to get it sign extended.
8905 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
8908 // FIXME gcc accepts some relocatable values here too, but only in certain
8909 // memory models; it's complicated.
8914 // 32-bit unsigned value
8915 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8916 const ConstantInt *CI = C->getConstantIntValue();
8917 if (CI->isValueValidForType(Type::Int32Ty, C->getZExtValue())) {
8918 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8922 // FIXME gcc accepts some relocatable values here too, but only in certain
8923 // memory models; it's complicated.
8927 // Literal immediates are always ok.
8928 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
8929 // Widen to 64 bits here to get it sign extended.
8930 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
8934 // If we are in non-pic codegen mode, we allow the address of a global (with
8935 // an optional displacement) to be used with 'i'.
8936 GlobalAddressSDNode *GA = 0;
8939 // Match either (GA), (GA+C), (GA+C1+C2), etc.
8941 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
8942 Offset += GA->getOffset();
8944 } else if (Op.getOpcode() == ISD::ADD) {
8945 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
8946 Offset += C->getZExtValue();
8947 Op = Op.getOperand(0);
8950 } else if (Op.getOpcode() == ISD::SUB) {
8951 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
8952 Offset += -C->getZExtValue();
8953 Op = Op.getOperand(0);
8958 // Otherwise, this isn't something we can handle, reject it.
8962 GlobalValue *GV = GA->getGlobal();
8963 // If we require an extra load to get this address, as in PIC mode, we
8965 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
8966 getTargetMachine())))
8970 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
8972 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
8978 if (Result.getNode()) {
8979 Ops.push_back(Result);
8982 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
8986 std::vector<unsigned> X86TargetLowering::
8987 getRegClassForInlineAsmConstraint(const std::string &Constraint,
8989 if (Constraint.size() == 1) {
8990 // FIXME: not handling fp-stack yet!
8991 switch (Constraint[0]) { // GCC X86 Constraint Letters
8992 default: break; // Unknown constraint letter
8993 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
8994 if (Subtarget->is64Bit()) {
8996 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
8997 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
8998 X86::R10D,X86::R11D,X86::R12D,
8999 X86::R13D,X86::R14D,X86::R15D,
9000 X86::EBP, X86::ESP, 0);
9001 else if (VT == MVT::i16)
9002 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
9003 X86::SI, X86::DI, X86::R8W,X86::R9W,
9004 X86::R10W,X86::R11W,X86::R12W,
9005 X86::R13W,X86::R14W,X86::R15W,
9006 X86::BP, X86::SP, 0);
9007 else if (VT == MVT::i8)
9008 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
9009 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
9010 X86::R10B,X86::R11B,X86::R12B,
9011 X86::R13B,X86::R14B,X86::R15B,
9012 X86::BPL, X86::SPL, 0);
9014 else if (VT == MVT::i64)
9015 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
9016 X86::RSI, X86::RDI, X86::R8, X86::R9,
9017 X86::R10, X86::R11, X86::R12,
9018 X86::R13, X86::R14, X86::R15,
9019 X86::RBP, X86::RSP, 0);
9023 // 32-bit fallthrough
9026 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
9027 else if (VT == MVT::i16)
9028 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
9029 else if (VT == MVT::i8)
9030 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
9031 else if (VT == MVT::i64)
9032 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
9037 return std::vector<unsigned>();
9040 std::pair<unsigned, const TargetRegisterClass*>
9041 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9043 // First, see if this is a constraint that directly corresponds to an LLVM
9045 if (Constraint.size() == 1) {
9046 // GCC Constraint Letters
9047 switch (Constraint[0]) {
9049 case 'r': // GENERAL_REGS
9050 case 'R': // LEGACY_REGS
9051 case 'l': // INDEX_REGS
9053 return std::make_pair(0U, X86::GR8RegisterClass);
9055 return std::make_pair(0U, X86::GR16RegisterClass);
9056 if (VT == MVT::i32 || !Subtarget->is64Bit())
9057 return std::make_pair(0U, X86::GR32RegisterClass);
9058 return std::make_pair(0U, X86::GR64RegisterClass);
9059 case 'f': // FP Stack registers.
9060 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
9061 // value to the correct fpstack register class.
9062 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
9063 return std::make_pair(0U, X86::RFP32RegisterClass);
9064 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
9065 return std::make_pair(0U, X86::RFP64RegisterClass);
9066 return std::make_pair(0U, X86::RFP80RegisterClass);
9067 case 'y': // MMX_REGS if MMX allowed.
9068 if (!Subtarget->hasMMX()) break;
9069 return std::make_pair(0U, X86::VR64RegisterClass);
9070 case 'Y': // SSE_REGS if SSE2 allowed
9071 if (!Subtarget->hasSSE2()) break;
9073 case 'x': // SSE_REGS if SSE1 allowed
9074 if (!Subtarget->hasSSE1()) break;
9076 switch (VT.getSimpleVT()) {
9078 // Scalar SSE types.
9081 return std::make_pair(0U, X86::FR32RegisterClass);
9084 return std::make_pair(0U, X86::FR64RegisterClass);
9092 return std::make_pair(0U, X86::VR128RegisterClass);
9098 // Use the default implementation in TargetLowering to convert the register
9099 // constraint into a member of a register class.
9100 std::pair<unsigned, const TargetRegisterClass*> Res;
9101 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9103 // Not found as a standard register?
9104 if (Res.second == 0) {
9105 // GCC calls "st(0)" just plain "st".
9106 if (StringsEqualNoCase("{st}", Constraint)) {
9107 Res.first = X86::ST0;
9108 Res.second = X86::RFP80RegisterClass;
9110 // 'A' means EAX + EDX.
9111 if (Constraint == "A") {
9112 Res.first = X86::EAX;
9113 Res.second = X86::GR32_ADRegisterClass;
9118 // Otherwise, check to see if this is a register class of the wrong value
9119 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
9120 // turn into {ax},{dx}.
9121 if (Res.second->hasType(VT))
9122 return Res; // Correct type already, nothing to do.
9124 // All of the single-register GCC register classes map their values onto
9125 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
9126 // really want an 8-bit or 32-bit register, map to the appropriate register
9127 // class and return the appropriate register.
9128 if (Res.second == X86::GR16RegisterClass) {
9129 if (VT == MVT::i8) {
9130 unsigned DestReg = 0;
9131 switch (Res.first) {
9133 case X86::AX: DestReg = X86::AL; break;
9134 case X86::DX: DestReg = X86::DL; break;
9135 case X86::CX: DestReg = X86::CL; break;
9136 case X86::BX: DestReg = X86::BL; break;
9139 Res.first = DestReg;
9140 Res.second = X86::GR8RegisterClass;
9142 } else if (VT == MVT::i32) {
9143 unsigned DestReg = 0;
9144 switch (Res.first) {
9146 case X86::AX: DestReg = X86::EAX; break;
9147 case X86::DX: DestReg = X86::EDX; break;
9148 case X86::CX: DestReg = X86::ECX; break;
9149 case X86::BX: DestReg = X86::EBX; break;
9150 case X86::SI: DestReg = X86::ESI; break;
9151 case X86::DI: DestReg = X86::EDI; break;
9152 case X86::BP: DestReg = X86::EBP; break;
9153 case X86::SP: DestReg = X86::ESP; break;
9156 Res.first = DestReg;
9157 Res.second = X86::GR32RegisterClass;
9159 } else if (VT == MVT::i64) {
9160 unsigned DestReg = 0;
9161 switch (Res.first) {
9163 case X86::AX: DestReg = X86::RAX; break;
9164 case X86::DX: DestReg = X86::RDX; break;
9165 case X86::CX: DestReg = X86::RCX; break;
9166 case X86::BX: DestReg = X86::RBX; break;
9167 case X86::SI: DestReg = X86::RSI; break;
9168 case X86::DI: DestReg = X86::RDI; break;
9169 case X86::BP: DestReg = X86::RBP; break;
9170 case X86::SP: DestReg = X86::RSP; break;
9173 Res.first = DestReg;
9174 Res.second = X86::GR64RegisterClass;
9177 } else if (Res.second == X86::FR32RegisterClass ||
9178 Res.second == X86::FR64RegisterClass ||
9179 Res.second == X86::VR128RegisterClass) {
9180 // Handle references to XMM physical registers that got mapped into the
9181 // wrong class. This can happen with constraints like {xmm0} where the
9182 // target independent register mapper will just pick the first match it can
9183 // find, ignoring the required type.
9185 Res.second = X86::FR32RegisterClass;
9186 else if (VT == MVT::f64)
9187 Res.second = X86::FR64RegisterClass;
9188 else if (X86::VR128RegisterClass->hasType(VT))
9189 Res.second = X86::VR128RegisterClass;
9195 //===----------------------------------------------------------------------===//
9196 // X86 Widen vector type
9197 //===----------------------------------------------------------------------===//
9199 /// getWidenVectorType: given a vector type, returns the type to widen
9200 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
9201 /// If there is no vector type that we want to widen to, returns MVT::Other
9202 /// When and where to widen is target dependent based on the cost of
9203 /// scalarizing vs using the wider vector type.
9205 MVT X86TargetLowering::getWidenVectorType(MVT VT) const {
9206 assert(VT.isVector());
9207 if (isTypeLegal(VT))
9210 // TODO: In computeRegisterProperty, we can compute the list of legal vector
9211 // type based on element type. This would speed up our search (though
9212 // it may not be worth it since the size of the list is relatively
9214 MVT EltVT = VT.getVectorElementType();
9215 unsigned NElts = VT.getVectorNumElements();
9217 // On X86, it make sense to widen any vector wider than 1
9221 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
9222 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
9223 MVT SVT = (MVT::SimpleValueType)nVT;
9225 if (isTypeLegal(SVT) &&
9226 SVT.getVectorElementType() == EltVT &&
9227 SVT.getVectorNumElements() > NElts)