1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
71 const X86Subtarget &STI)
72 : TargetLowering(TM), Subtarget(&STI) {
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
77 // Set up the TargetLowering object.
78 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
168 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
169 } else if (!Subtarget->useSoftFloat()) {
170 // We have an algorithm for SSE2->double, and we turn this into a
171 // 64-bit FILD followed by conditional FADD for other targets.
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 // We have an algorithm for SSE2, and we turn this into a 64-bit
174 // FILD for other targets.
175 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
178 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
180 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
181 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
183 if (!Subtarget->useSoftFloat()) {
184 // SSE has no i16 to fp conversion, only i32
185 if (X86ScalarSSEf32) {
186 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
187 // f32 and f64 cases are Legal, f80 case is not
188 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
191 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
198 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
199 // are Legal, f80 is custom lowered.
200 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
201 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
203 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
205 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
206 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
208 if (X86ScalarSSEf32) {
209 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
210 // f32 and f64 cases are Legal, f80 case is not
211 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
213 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
214 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
217 // Handle FP_TO_UINT by promoting the destination to a larger signed
219 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
220 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
221 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
223 if (Subtarget->is64Bit()) {
224 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
225 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
226 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
227 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
229 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
230 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
232 } else if (!Subtarget->useSoftFloat()) {
233 // Since AVX is a superset of SSE3, only check for SSE here.
234 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
235 // Expand FP_TO_UINT into a select.
236 // FIXME: We would like to use a Custom expander here eventually to do
237 // the optimal thing for SSE vs. the default expansion in the legalizer.
238 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
240 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
241 // With SSE3 we can use fisttpll to convert to a signed i64; without
242 // SSE, we're stuck with a fistpll.
243 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
245 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
248 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
249 if (!X86ScalarSSEf64) {
250 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
251 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
252 if (Subtarget->is64Bit()) {
253 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
254 // Without SSE, i64->f64 goes through memory.
255 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
259 // Scalar integer divide and remainder are lowered to use operations that
260 // produce two results, to match the available instructions. This exposes
261 // the two-result form to trivial CSE, which is able to combine x/y and x%y
262 // into a single instruction.
264 // Scalar integer multiply-high is also lowered to use two-result
265 // operations, to match the available instructions. However, plain multiply
266 // (low) operations are left as Legal, as there are single-result
267 // instructions for this in x86. Using the two-result multiply instructions
268 // when both high and low results are needed must be arranged by dagcombine.
269 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
271 setOperationAction(ISD::MULHS, VT, Expand);
272 setOperationAction(ISD::MULHU, VT, Expand);
273 setOperationAction(ISD::SDIV, VT, Expand);
274 setOperationAction(ISD::UDIV, VT, Expand);
275 setOperationAction(ISD::SREM, VT, Expand);
276 setOperationAction(ISD::UREM, VT, Expand);
278 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
279 setOperationAction(ISD::ADDC, VT, Custom);
280 setOperationAction(ISD::ADDE, VT, Custom);
281 setOperationAction(ISD::SUBC, VT, Custom);
282 setOperationAction(ISD::SUBE, VT, Custom);
285 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
286 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
287 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
288 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
289 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
290 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
291 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
292 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
293 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
294 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
295 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
296 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
297 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
298 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
299 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
300 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
301 if (Subtarget->is64Bit())
302 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
303 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
304 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
305 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
306 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
308 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
309 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
310 // is. We should promote the value to 64-bits to solve this.
311 // This is what the CRT headers do - `fmodf` is an inline header
312 // function casting to f64 and calling `fmod`.
313 setOperationAction(ISD::FREM , MVT::f32 , Promote);
315 setOperationAction(ISD::FREM , MVT::f32 , Expand);
318 setOperationAction(ISD::FREM , MVT::f64 , Expand);
319 setOperationAction(ISD::FREM , MVT::f80 , Expand);
320 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
322 // Promote the i8 variants and force them on up to i32 which has a shorter
324 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
325 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
326 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
327 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
328 if (Subtarget->hasBMI()) {
329 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
331 if (Subtarget->is64Bit())
332 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
334 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
335 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
336 if (Subtarget->is64Bit())
337 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
340 if (Subtarget->hasLZCNT()) {
341 // When promoting the i8 variants, force them to i32 for a shorter
343 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
344 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
345 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
346 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
347 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
348 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
349 if (Subtarget->is64Bit())
350 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
352 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
353 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
354 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
355 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
356 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
358 if (Subtarget->is64Bit()) {
359 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
364 // Special handling for half-precision floating point conversions.
365 // If we don't have F16C support, then lower half float conversions
366 // into library calls.
367 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
368 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
369 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
372 // There's never any support for operations beyond MVT::f32.
373 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
374 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
375 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
376 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
378 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
379 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
380 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
381 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
382 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
383 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
385 if (Subtarget->hasPOPCNT()) {
386 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
388 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
389 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
390 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
391 if (Subtarget->is64Bit())
392 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
395 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
397 if (!Subtarget->hasMOVBE())
398 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
400 // These should be promoted to a larger select which is supported.
401 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
402 // X86 wants to expand cmov itself.
403 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
404 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
405 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
406 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
407 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
408 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
409 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
410 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
411 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
412 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
413 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
414 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
415 if (Subtarget->is64Bit()) {
416 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
417 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
419 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
420 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
421 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
422 // support continuation, user-level threading, and etc.. As a result, no
423 // other SjLj exception interfaces are implemented and please don't build
424 // your own exception handling based on them.
425 // LLVM/Clang supports zero-cost DWARF exception handling.
426 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
427 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
430 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
431 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
432 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
433 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
434 if (Subtarget->is64Bit())
435 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
436 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
437 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
438 if (Subtarget->is64Bit()) {
439 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
440 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
441 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
442 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
443 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
445 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
446 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
447 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
448 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
449 if (Subtarget->is64Bit()) {
450 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
455 if (Subtarget->hasSSE1())
456 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
458 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
460 // Expand certain atomics
461 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
463 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
464 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
465 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
468 if (Subtarget->hasCmpxchg16b()) {
469 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
472 // FIXME - use subtarget debug flags
473 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
474 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
475 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
478 if (Subtarget->isTarget64BitLP64()) {
479 setExceptionPointerRegister(X86::RAX);
480 setExceptionSelectorRegister(X86::RDX);
482 setExceptionPointerRegister(X86::EAX);
483 setExceptionSelectorRegister(X86::EDX);
485 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
486 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
488 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
489 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
491 setOperationAction(ISD::TRAP, MVT::Other, Legal);
492 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
494 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
495 setOperationAction(ISD::VASTART , MVT::Other, Custom);
496 setOperationAction(ISD::VAEND , MVT::Other, Expand);
497 if (Subtarget->is64Bit()) {
498 setOperationAction(ISD::VAARG , MVT::Other, Custom);
499 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
501 // TargetInfo::CharPtrBuiltinVaList
502 setOperationAction(ISD::VAARG , MVT::Other, Expand);
503 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
506 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
507 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
509 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
511 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
512 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
513 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
515 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
516 // f32 and f64 use SSE.
517 // Set up the FP register classes.
518 addRegisterClass(MVT::f32, &X86::FR32RegClass);
519 addRegisterClass(MVT::f64, &X86::FR64RegClass);
521 // Use ANDPD to simulate FABS.
522 setOperationAction(ISD::FABS , MVT::f64, Custom);
523 setOperationAction(ISD::FABS , MVT::f32, Custom);
525 // Use XORP to simulate FNEG.
526 setOperationAction(ISD::FNEG , MVT::f64, Custom);
527 setOperationAction(ISD::FNEG , MVT::f32, Custom);
529 // Use ANDPD and ORPD to simulate FCOPYSIGN.
530 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
531 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
533 // Lower this to FGETSIGNx86 plus an AND.
534 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
535 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
537 // We don't support sin/cos/fmod
538 setOperationAction(ISD::FSIN , MVT::f64, Expand);
539 setOperationAction(ISD::FCOS , MVT::f64, Expand);
540 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
541 setOperationAction(ISD::FSIN , MVT::f32, Expand);
542 setOperationAction(ISD::FCOS , MVT::f32, Expand);
543 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
545 // Expand FP immediates into loads from the stack, except for the special
547 addLegalFPImmediate(APFloat(+0.0)); // xorpd
548 addLegalFPImmediate(APFloat(+0.0f)); // xorps
549 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
550 // Use SSE for f32, x87 for f64.
551 // Set up the FP register classes.
552 addRegisterClass(MVT::f32, &X86::FR32RegClass);
553 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
555 // Use ANDPS to simulate FABS.
556 setOperationAction(ISD::FABS , MVT::f32, Custom);
558 // Use XORP to simulate FNEG.
559 setOperationAction(ISD::FNEG , MVT::f32, Custom);
561 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
563 // Use ANDPS and ORPS to simulate FCOPYSIGN.
564 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
565 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
567 // We don't support sin/cos/fmod
568 setOperationAction(ISD::FSIN , MVT::f32, Expand);
569 setOperationAction(ISD::FCOS , MVT::f32, Expand);
570 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
572 // Special cases we handle for FP constants.
573 addLegalFPImmediate(APFloat(+0.0f)); // xorps
574 addLegalFPImmediate(APFloat(+0.0)); // FLD0
575 addLegalFPImmediate(APFloat(+1.0)); // FLD1
576 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
577 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
579 if (!TM.Options.UnsafeFPMath) {
580 setOperationAction(ISD::FSIN , MVT::f64, Expand);
581 setOperationAction(ISD::FCOS , MVT::f64, Expand);
582 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
584 } else if (!Subtarget->useSoftFloat()) {
585 // f32 and f64 in x87.
586 // Set up the FP register classes.
587 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
588 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
590 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
591 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
592 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
593 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
595 if (!TM.Options.UnsafeFPMath) {
596 setOperationAction(ISD::FSIN , MVT::f64, Expand);
597 setOperationAction(ISD::FSIN , MVT::f32, Expand);
598 setOperationAction(ISD::FCOS , MVT::f64, Expand);
599 setOperationAction(ISD::FCOS , MVT::f32, Expand);
600 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
601 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
603 addLegalFPImmediate(APFloat(+0.0)); // FLD0
604 addLegalFPImmediate(APFloat(+1.0)); // FLD1
605 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
606 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
607 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
608 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
609 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
610 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
613 // We don't support FMA.
614 setOperationAction(ISD::FMA, MVT::f64, Expand);
615 setOperationAction(ISD::FMA, MVT::f32, Expand);
617 // Long double always uses X87.
618 if (!Subtarget->useSoftFloat()) {
619 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
620 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
621 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
623 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
624 addLegalFPImmediate(TmpFlt); // FLD0
626 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
629 APFloat TmpFlt2(+1.0);
630 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
632 addLegalFPImmediate(TmpFlt2); // FLD1
633 TmpFlt2.changeSign();
634 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
637 if (!TM.Options.UnsafeFPMath) {
638 setOperationAction(ISD::FSIN , MVT::f80, Expand);
639 setOperationAction(ISD::FCOS , MVT::f80, Expand);
640 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
643 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
644 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
645 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
646 setOperationAction(ISD::FRINT, MVT::f80, Expand);
647 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
648 setOperationAction(ISD::FMA, MVT::f80, Expand);
651 // Always use a library call for pow.
652 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
653 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
654 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
656 setOperationAction(ISD::FLOG, MVT::f80, Expand);
657 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
658 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
659 setOperationAction(ISD::FEXP, MVT::f80, Expand);
660 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
661 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
662 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
664 // First set operation action for all vector types to either promote
665 // (for widening) or expand (for scalarization). Then we will selectively
666 // turn on ones that can be effectively codegen'd.
667 for (MVT VT : MVT::vector_valuetypes()) {
668 setOperationAction(ISD::ADD , VT, Expand);
669 setOperationAction(ISD::SUB , VT, Expand);
670 setOperationAction(ISD::FADD, VT, Expand);
671 setOperationAction(ISD::FNEG, VT, Expand);
672 setOperationAction(ISD::FSUB, VT, Expand);
673 setOperationAction(ISD::MUL , VT, Expand);
674 setOperationAction(ISD::FMUL, VT, Expand);
675 setOperationAction(ISD::SDIV, VT, Expand);
676 setOperationAction(ISD::UDIV, VT, Expand);
677 setOperationAction(ISD::FDIV, VT, Expand);
678 setOperationAction(ISD::SREM, VT, Expand);
679 setOperationAction(ISD::UREM, VT, Expand);
680 setOperationAction(ISD::LOAD, VT, Expand);
681 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
682 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
683 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
684 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
685 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
686 setOperationAction(ISD::FABS, VT, Expand);
687 setOperationAction(ISD::FSIN, VT, Expand);
688 setOperationAction(ISD::FSINCOS, VT, Expand);
689 setOperationAction(ISD::FCOS, VT, Expand);
690 setOperationAction(ISD::FSINCOS, VT, Expand);
691 setOperationAction(ISD::FREM, VT, Expand);
692 setOperationAction(ISD::FMA, VT, Expand);
693 setOperationAction(ISD::FPOWI, VT, Expand);
694 setOperationAction(ISD::FSQRT, VT, Expand);
695 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
696 setOperationAction(ISD::FFLOOR, VT, Expand);
697 setOperationAction(ISD::FCEIL, VT, Expand);
698 setOperationAction(ISD::FTRUNC, VT, Expand);
699 setOperationAction(ISD::FRINT, VT, Expand);
700 setOperationAction(ISD::FNEARBYINT, VT, Expand);
701 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
702 setOperationAction(ISD::MULHS, VT, Expand);
703 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
704 setOperationAction(ISD::MULHU, VT, Expand);
705 setOperationAction(ISD::SDIVREM, VT, Expand);
706 setOperationAction(ISD::UDIVREM, VT, Expand);
707 setOperationAction(ISD::FPOW, VT, Expand);
708 setOperationAction(ISD::CTPOP, VT, Expand);
709 setOperationAction(ISD::CTTZ, VT, Expand);
710 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
711 setOperationAction(ISD::CTLZ, VT, Expand);
712 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
713 setOperationAction(ISD::SHL, VT, Expand);
714 setOperationAction(ISD::SRA, VT, Expand);
715 setOperationAction(ISD::SRL, VT, Expand);
716 setOperationAction(ISD::ROTL, VT, Expand);
717 setOperationAction(ISD::ROTR, VT, Expand);
718 setOperationAction(ISD::BSWAP, VT, Expand);
719 setOperationAction(ISD::SETCC, VT, Expand);
720 setOperationAction(ISD::FLOG, VT, Expand);
721 setOperationAction(ISD::FLOG2, VT, Expand);
722 setOperationAction(ISD::FLOG10, VT, Expand);
723 setOperationAction(ISD::FEXP, VT, Expand);
724 setOperationAction(ISD::FEXP2, VT, Expand);
725 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
726 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
727 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
728 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
729 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
730 setOperationAction(ISD::TRUNCATE, VT, Expand);
731 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
732 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
733 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
734 setOperationAction(ISD::VSELECT, VT, Expand);
735 setOperationAction(ISD::SELECT_CC, VT, Expand);
736 for (MVT InnerVT : MVT::vector_valuetypes()) {
737 setTruncStoreAction(InnerVT, VT, Expand);
739 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
740 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
742 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
743 // types, we have to deal with them whether we ask for Expansion or not.
744 // Setting Expand causes its own optimisation problems though, so leave
746 if (VT.getVectorElementType() == MVT::i1)
747 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
749 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
750 // split/scalarized right now.
751 if (VT.getVectorElementType() == MVT::f16)
752 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
756 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
757 // with -msoft-float, disable use of MMX as well.
758 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
759 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
760 // No operations on x86mmx supported, everything uses intrinsics.
763 // MMX-sized vectors (other than x86mmx) are expected to be expanded
764 // into smaller operations.
765 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
766 setOperationAction(ISD::MULHS, MMXTy, Expand);
767 setOperationAction(ISD::AND, MMXTy, Expand);
768 setOperationAction(ISD::OR, MMXTy, Expand);
769 setOperationAction(ISD::XOR, MMXTy, Expand);
770 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
771 setOperationAction(ISD::SELECT, MMXTy, Expand);
772 setOperationAction(ISD::BITCAST, MMXTy, Expand);
774 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
776 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
777 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
779 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
780 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
781 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
782 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
783 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
784 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
785 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
786 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
787 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
788 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
789 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
790 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
791 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
792 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
795 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
796 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
798 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
799 // registers cannot be used even for integer operations.
800 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
801 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
802 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
803 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
805 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
806 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
807 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
808 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
809 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
810 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
811 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
812 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
813 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
814 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
815 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
816 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
817 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
818 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
819 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
820 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
821 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
822 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
823 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
824 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
825 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
826 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
827 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
829 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
830 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
831 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
832 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
834 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
835 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
836 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
837 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
840 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
843 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
845 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
846 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
847 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
848 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
850 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
851 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
852 MVT VT = (MVT::SimpleValueType)i;
853 // Do not attempt to custom lower non-power-of-2 vectors
854 if (!isPowerOf2_32(VT.getVectorNumElements()))
856 // Do not attempt to custom lower non-128-bit vectors
857 if (!VT.is128BitVector())
859 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
860 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
861 setOperationAction(ISD::VSELECT, VT, Custom);
862 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
865 // We support custom legalizing of sext and anyext loads for specific
866 // memory vector types which we can load as a scalar (or sequence of
867 // scalars) and extend in-register to a legal 128-bit vector type. For sext
868 // loads these must work with a single scalar load.
869 for (MVT VT : MVT::integer_vector_valuetypes()) {
870 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
871 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
872 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
873 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
874 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
875 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
876 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
877 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
878 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
881 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
882 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
883 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
884 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
885 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
886 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
887 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
888 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
890 if (Subtarget->is64Bit()) {
891 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
892 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
895 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
896 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
897 MVT VT = (MVT::SimpleValueType)i;
899 // Do not attempt to promote non-128-bit vectors
900 if (!VT.is128BitVector())
903 setOperationAction(ISD::AND, VT, Promote);
904 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
905 setOperationAction(ISD::OR, VT, Promote);
906 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
907 setOperationAction(ISD::XOR, VT, Promote);
908 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
909 setOperationAction(ISD::LOAD, VT, Promote);
910 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
911 setOperationAction(ISD::SELECT, VT, Promote);
912 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
915 // Custom lower v2i64 and v2f64 selects.
916 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
917 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
918 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
919 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
921 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
922 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
924 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
926 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
927 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
928 // As there is no 64-bit GPR available, we need build a special custom
929 // sequence to convert from v2i32 to v2f32.
930 if (!Subtarget->is64Bit())
931 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
933 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
934 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
936 for (MVT VT : MVT::fp_vector_valuetypes())
937 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
940 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
941 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
944 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
945 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
946 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
947 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
948 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
949 setOperationAction(ISD::FRINT, RoundedTy, Legal);
950 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
953 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
954 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
955 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
956 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
957 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
958 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
959 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
960 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
962 // FIXME: Do we need to handle scalar-to-vector here?
963 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
965 // We directly match byte blends in the backend as they match the VSELECT
967 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
969 // SSE41 brings specific instructions for doing vector sign extend even in
970 // cases where we don't have SRA.
971 for (MVT VT : MVT::integer_vector_valuetypes()) {
972 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
973 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
974 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
977 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
978 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
979 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
981 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
982 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
983 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
985 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
988 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
989 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
990 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
992 // i8 and i16 vectors are custom because the source register and source
993 // source memory operand types are not the same width. f32 vectors are
994 // custom since the immediate controlling the insert encodes additional
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1001 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1006 // FIXME: these should be Legal, but that's only for the case where
1007 // the index is constant. For now custom expand to deal with that.
1008 if (Subtarget->is64Bit()) {
1009 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1010 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1014 if (Subtarget->hasSSE2()) {
1015 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1016 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1017 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1019 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1020 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1022 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1023 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1025 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1026 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1028 // In the customized shift lowering, the legal cases in AVX2 will be
1030 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1031 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1033 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1034 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1036 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1037 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1040 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1041 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1042 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1043 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1044 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1045 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1046 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1048 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1049 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1050 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1052 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1053 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1054 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1055 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1056 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1057 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1058 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1059 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1060 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1061 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1062 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1063 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1065 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1066 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1067 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1068 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1069 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1070 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1071 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1072 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1073 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1074 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1075 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1076 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1078 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1079 // even though v8i16 is a legal type.
1080 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1081 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1082 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1084 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1085 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1086 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1088 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1089 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1091 for (MVT VT : MVT::fp_vector_valuetypes())
1092 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1094 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1095 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1097 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1098 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1100 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1101 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1103 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1104 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1105 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1106 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1108 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1109 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1110 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1112 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1113 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1114 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1115 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1116 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1117 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1118 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1119 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1120 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1121 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1122 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1123 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1125 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1126 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1127 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1128 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1130 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1131 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1133 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1134 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1135 setOperationAction(ISD::FMA, MVT::f32, Legal);
1136 setOperationAction(ISD::FMA, MVT::f64, Legal);
1139 if (Subtarget->hasInt256()) {
1140 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1141 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1142 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1143 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1145 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1146 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1147 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1148 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1150 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1151 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1152 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1153 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1155 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1156 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1157 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1158 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1160 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1161 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1162 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1163 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1164 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1165 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1166 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1167 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1168 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1169 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1170 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1171 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1173 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1174 // when we have a 256bit-wide blend with immediate.
1175 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1177 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1178 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1179 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1180 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1181 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1182 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1183 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1185 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1186 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1187 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1188 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1189 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1190 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1192 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1193 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1194 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1195 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1197 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1198 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1199 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1200 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1202 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1203 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1204 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1205 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1207 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1208 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1209 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1210 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1211 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1212 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1213 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1214 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1215 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1216 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1217 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1218 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1221 // In the customized shift lowering, the legal cases in AVX2 will be
1223 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1224 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1226 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1227 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1229 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1230 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1232 // Custom lower several nodes for 256-bit types.
1233 for (MVT VT : MVT::vector_valuetypes()) {
1234 if (VT.getScalarSizeInBits() >= 32) {
1235 setOperationAction(ISD::MLOAD, VT, Legal);
1236 setOperationAction(ISD::MSTORE, VT, Legal);
1238 // Extract subvector is special because the value type
1239 // (result) is 128-bit but the source is 256-bit wide.
1240 if (VT.is128BitVector()) {
1241 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1243 // Do not attempt to custom lower other non-256-bit vectors
1244 if (!VT.is256BitVector())
1247 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1248 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1249 setOperationAction(ISD::VSELECT, VT, Custom);
1250 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1251 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1252 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1253 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1254 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1257 if (Subtarget->hasInt256())
1258 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1261 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1262 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1263 MVT VT = (MVT::SimpleValueType)i;
1265 // Do not attempt to promote non-256-bit vectors
1266 if (!VT.is256BitVector())
1269 setOperationAction(ISD::AND, VT, Promote);
1270 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1271 setOperationAction(ISD::OR, VT, Promote);
1272 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1273 setOperationAction(ISD::XOR, VT, Promote);
1274 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1275 setOperationAction(ISD::LOAD, VT, Promote);
1276 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1277 setOperationAction(ISD::SELECT, VT, Promote);
1278 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1282 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1283 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1284 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1285 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1286 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1288 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1289 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1290 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1292 for (MVT VT : MVT::fp_vector_valuetypes())
1293 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1295 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1296 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1297 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1298 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1299 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1300 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1301 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1302 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1303 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1304 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1305 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1306 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1308 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1309 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1310 setOperationAction(ISD::XOR, MVT::i1, Legal);
1311 setOperationAction(ISD::OR, MVT::i1, Legal);
1312 setOperationAction(ISD::AND, MVT::i1, Legal);
1313 setOperationAction(ISD::SUB, MVT::i1, Custom);
1314 setOperationAction(ISD::ADD, MVT::i1, Custom);
1315 setOperationAction(ISD::MUL, MVT::i1, Custom);
1316 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1317 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1318 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1319 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1320 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1322 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1323 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1324 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1325 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1326 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1327 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1329 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1330 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1331 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1332 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1333 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1334 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1335 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1336 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1338 // FIXME: [US]INT_TO_FP are not legal for f80.
1339 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1340 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1341 if (Subtarget->is64Bit()) {
1342 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1343 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1345 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1346 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1347 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1348 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1349 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1350 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1351 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1352 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1353 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1354 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1355 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1356 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1357 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1358 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1359 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1360 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1362 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1363 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1364 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1365 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1366 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1367 if (Subtarget->hasVLX()){
1368 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1369 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1370 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1371 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1372 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1374 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1375 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1376 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1377 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1378 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1380 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1381 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1382 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1383 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1384 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1385 if (Subtarget->hasDQI()) {
1386 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1387 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1389 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1390 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1391 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1392 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1393 if (Subtarget->hasVLX()) {
1394 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1395 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1396 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1397 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1398 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1399 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1400 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1401 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1404 if (Subtarget->hasVLX()) {
1405 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1407 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1408 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1409 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1411 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1412 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1414 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1415 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1416 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1417 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1418 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1419 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1420 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1421 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1422 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1423 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1424 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1425 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1426 if (Subtarget->hasDQI()) {
1427 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1428 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1430 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1431 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1432 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1433 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1434 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1435 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1436 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1437 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1438 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1439 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1444 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1445 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1447 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1448 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1450 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1452 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1454 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1455 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1456 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1457 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1459 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1460 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1461 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1464 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1465 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1466 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1467 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1468 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1469 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1470 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1471 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1473 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1474 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1476 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1477 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1479 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1481 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1482 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1484 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1485 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1487 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1488 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1490 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1491 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1492 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1493 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1494 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1495 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1497 if (Subtarget->hasCDI()) {
1498 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1499 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1500 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1503 if (Subtarget->hasVLX() && Subtarget->hasCDI()) {
1504 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1505 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1506 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1507 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1513 if (Subtarget->hasDQI()) {
1514 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1515 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1516 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1518 // Custom lower several nodes.
1519 for (MVT VT : MVT::vector_valuetypes()) {
1520 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1522 setOperationAction(ISD::AND, VT, Legal);
1523 setOperationAction(ISD::OR, VT, Legal);
1524 setOperationAction(ISD::XOR, VT, Legal);
1526 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1527 setOperationAction(ISD::MGATHER, VT, Custom);
1528 setOperationAction(ISD::MSCATTER, VT, Custom);
1530 // Extract subvector is special because the value type
1531 // (result) is 256/128-bit but the source is 512-bit wide.
1532 if (VT.is128BitVector() || VT.is256BitVector()) {
1533 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1535 if (VT.getVectorElementType() == MVT::i1)
1536 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1538 // Do not attempt to custom lower other non-512-bit vectors
1539 if (!VT.is512BitVector())
1542 if (EltSize >= 32) {
1543 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1544 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1545 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1546 setOperationAction(ISD::VSELECT, VT, Legal);
1547 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1548 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1549 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1550 setOperationAction(ISD::MLOAD, VT, Legal);
1551 setOperationAction(ISD::MSTORE, VT, Legal);
1554 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1555 MVT VT = (MVT::SimpleValueType)i;
1557 // Do not attempt to promote non-512-bit vectors.
1558 if (!VT.is512BitVector())
1561 setOperationAction(ISD::SELECT, VT, Promote);
1562 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1566 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1567 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1568 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1570 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1571 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1573 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1574 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1575 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1576 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1577 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1578 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1579 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1580 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1581 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1582 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1583 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1584 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Legal);
1585 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Legal);
1586 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1587 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1588 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1589 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1590 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1591 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1592 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1593 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1594 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1595 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1596 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1597 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1598 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1599 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1600 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1601 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1602 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1603 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1604 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1605 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1607 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1608 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1609 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1610 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1611 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1612 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1613 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1614 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1616 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1617 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1618 if (Subtarget->hasVLX())
1619 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1621 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1622 const MVT VT = (MVT::SimpleValueType)i;
1624 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1626 // Do not attempt to promote non-512-bit vectors.
1627 if (!VT.is512BitVector())
1631 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1632 setOperationAction(ISD::VSELECT, VT, Legal);
1637 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1638 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1639 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1641 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1642 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1643 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1644 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1645 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1646 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1647 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1648 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1649 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1650 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1651 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1652 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1654 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1655 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1656 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1657 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1658 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1659 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1660 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1661 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1663 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1664 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1665 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1666 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1667 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1668 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1669 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1670 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1673 // We want to custom lower some of our intrinsics.
1674 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1675 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1676 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1677 if (!Subtarget->is64Bit())
1678 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1680 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1681 // handle type legalization for these operations here.
1683 // FIXME: We really should do custom legalization for addition and
1684 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1685 // than generic legalization for 64-bit multiplication-with-overflow, though.
1686 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1687 // Add/Sub/Mul with overflow operations are custom lowered.
1689 setOperationAction(ISD::SADDO, VT, Custom);
1690 setOperationAction(ISD::UADDO, VT, Custom);
1691 setOperationAction(ISD::SSUBO, VT, Custom);
1692 setOperationAction(ISD::USUBO, VT, Custom);
1693 setOperationAction(ISD::SMULO, VT, Custom);
1694 setOperationAction(ISD::UMULO, VT, Custom);
1698 if (!Subtarget->is64Bit()) {
1699 // These libcalls are not available in 32-bit.
1700 setLibcallName(RTLIB::SHL_I128, nullptr);
1701 setLibcallName(RTLIB::SRL_I128, nullptr);
1702 setLibcallName(RTLIB::SRA_I128, nullptr);
1705 // Combine sin / cos into one node or libcall if possible.
1706 if (Subtarget->hasSinCos()) {
1707 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1708 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1709 if (Subtarget->isTargetDarwin()) {
1710 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1711 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1712 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1713 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1717 if (Subtarget->isTargetWin64()) {
1718 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1719 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1720 setOperationAction(ISD::SREM, MVT::i128, Custom);
1721 setOperationAction(ISD::UREM, MVT::i128, Custom);
1722 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1723 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1726 // We have target-specific dag combine patterns for the following nodes:
1727 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1728 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1729 setTargetDAGCombine(ISD::BITCAST);
1730 setTargetDAGCombine(ISD::VSELECT);
1731 setTargetDAGCombine(ISD::SELECT);
1732 setTargetDAGCombine(ISD::SHL);
1733 setTargetDAGCombine(ISD::SRA);
1734 setTargetDAGCombine(ISD::SRL);
1735 setTargetDAGCombine(ISD::OR);
1736 setTargetDAGCombine(ISD::AND);
1737 setTargetDAGCombine(ISD::ADD);
1738 setTargetDAGCombine(ISD::FADD);
1739 setTargetDAGCombine(ISD::FSUB);
1740 setTargetDAGCombine(ISD::FMA);
1741 setTargetDAGCombine(ISD::SUB);
1742 setTargetDAGCombine(ISD::LOAD);
1743 setTargetDAGCombine(ISD::MLOAD);
1744 setTargetDAGCombine(ISD::STORE);
1745 setTargetDAGCombine(ISD::MSTORE);
1746 setTargetDAGCombine(ISD::ZERO_EXTEND);
1747 setTargetDAGCombine(ISD::ANY_EXTEND);
1748 setTargetDAGCombine(ISD::SIGN_EXTEND);
1749 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1750 setTargetDAGCombine(ISD::SINT_TO_FP);
1751 setTargetDAGCombine(ISD::UINT_TO_FP);
1752 setTargetDAGCombine(ISD::SETCC);
1753 setTargetDAGCombine(ISD::BUILD_VECTOR);
1754 setTargetDAGCombine(ISD::MUL);
1755 setTargetDAGCombine(ISD::XOR);
1757 computeRegisterProperties(Subtarget->getRegisterInfo());
1759 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1760 MaxStoresPerMemsetOptSize = 8;
1761 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1762 MaxStoresPerMemcpyOptSize = 4;
1763 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1764 MaxStoresPerMemmoveOptSize = 4;
1765 setPrefLoopAlignment(4); // 2^4 bytes.
1767 // Predictable cmov don't hurt on atom because it's in-order.
1768 PredictableSelectIsExpensive = !Subtarget->isAtom();
1769 EnableExtLdPromotion = true;
1770 setPrefFunctionAlignment(4); // 2^4 bytes.
1772 verifyIntrinsicTables();
1775 // This has so far only been implemented for 64-bit MachO.
1776 bool X86TargetLowering::useLoadStackGuardNode() const {
1777 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1780 TargetLoweringBase::LegalizeTypeAction
1781 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1782 if (ExperimentalVectorWideningLegalization &&
1783 VT.getVectorNumElements() != 1 &&
1784 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1785 return TypeWidenVector;
1787 return TargetLoweringBase::getPreferredVectorAction(VT);
1790 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1793 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1795 const unsigned NumElts = VT.getVectorNumElements();
1796 const EVT EltVT = VT.getVectorElementType();
1797 if (VT.is512BitVector()) {
1798 if (Subtarget->hasAVX512())
1799 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1800 EltVT == MVT::f32 || EltVT == MVT::f64)
1802 case 8: return MVT::v8i1;
1803 case 16: return MVT::v16i1;
1805 if (Subtarget->hasBWI())
1806 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1808 case 32: return MVT::v32i1;
1809 case 64: return MVT::v64i1;
1813 if (VT.is256BitVector() || VT.is128BitVector()) {
1814 if (Subtarget->hasVLX())
1815 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1816 EltVT == MVT::f32 || EltVT == MVT::f64)
1818 case 2: return MVT::v2i1;
1819 case 4: return MVT::v4i1;
1820 case 8: return MVT::v8i1;
1822 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1823 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1825 case 8: return MVT::v8i1;
1826 case 16: return MVT::v16i1;
1827 case 32: return MVT::v32i1;
1831 return VT.changeVectorElementTypeToInteger();
1834 /// Helper for getByValTypeAlignment to determine
1835 /// the desired ByVal argument alignment.
1836 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1839 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1840 if (VTy->getBitWidth() == 128)
1842 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1843 unsigned EltAlign = 0;
1844 getMaxByValAlign(ATy->getElementType(), EltAlign);
1845 if (EltAlign > MaxAlign)
1846 MaxAlign = EltAlign;
1847 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1848 for (auto *EltTy : STy->elements()) {
1849 unsigned EltAlign = 0;
1850 getMaxByValAlign(EltTy, EltAlign);
1851 if (EltAlign > MaxAlign)
1852 MaxAlign = EltAlign;
1859 /// Return the desired alignment for ByVal aggregate
1860 /// function arguments in the caller parameter area. For X86, aggregates
1861 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1862 /// are at 4-byte boundaries.
1863 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1864 const DataLayout &DL) const {
1865 if (Subtarget->is64Bit()) {
1866 // Max of 8 and alignment of type.
1867 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1874 if (Subtarget->hasSSE1())
1875 getMaxByValAlign(Ty, Align);
1879 /// Returns the target specific optimal type for load
1880 /// and store operations as a result of memset, memcpy, and memmove
1881 /// lowering. If DstAlign is zero that means it's safe to destination
1882 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1883 /// means there isn't a need to check it against alignment requirement,
1884 /// probably because the source does not need to be loaded. If 'IsMemset' is
1885 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1886 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1887 /// source is constant so it does not need to be loaded.
1888 /// It returns EVT::Other if the type should be determined using generic
1889 /// target-independent logic.
1891 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1892 unsigned DstAlign, unsigned SrcAlign,
1893 bool IsMemset, bool ZeroMemset,
1895 MachineFunction &MF) const {
1896 const Function *F = MF.getFunction();
1897 if ((!IsMemset || ZeroMemset) &&
1898 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1900 (!Subtarget->isUnalignedMem16Slow() ||
1901 ((DstAlign == 0 || DstAlign >= 16) &&
1902 (SrcAlign == 0 || SrcAlign >= 16)))) {
1904 // FIXME: Check if unaligned 32-byte accesses are slow.
1905 if (Subtarget->hasInt256())
1907 if (Subtarget->hasFp256())
1910 if (Subtarget->hasSSE2())
1912 if (Subtarget->hasSSE1())
1914 } else if (!MemcpyStrSrc && Size >= 8 &&
1915 !Subtarget->is64Bit() &&
1916 Subtarget->hasSSE2()) {
1917 // Do not use f64 to lower memcpy if source is string constant. It's
1918 // better to use i32 to avoid the loads.
1922 // This is a compromise. If we reach here, unaligned accesses may be slow on
1923 // this target. However, creating smaller, aligned accesses could be even
1924 // slower and would certainly be a lot more code.
1925 if (Subtarget->is64Bit() && Size >= 8)
1930 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1932 return X86ScalarSSEf32;
1933 else if (VT == MVT::f64)
1934 return X86ScalarSSEf64;
1939 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1944 switch (VT.getSizeInBits()) {
1946 // 8-byte and under are always assumed to be fast.
1950 *Fast = !Subtarget->isUnalignedMem16Slow();
1953 *Fast = !Subtarget->isUnalignedMem32Slow();
1955 // TODO: What about AVX-512 (512-bit) accesses?
1958 // Misaligned accesses of any size are always allowed.
1962 /// Return the entry encoding for a jump table in the
1963 /// current function. The returned value is a member of the
1964 /// MachineJumpTableInfo::JTEntryKind enum.
1965 unsigned X86TargetLowering::getJumpTableEncoding() const {
1966 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1968 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1969 Subtarget->isPICStyleGOT())
1970 return MachineJumpTableInfo::EK_Custom32;
1972 // Otherwise, use the normal jump table encoding heuristics.
1973 return TargetLowering::getJumpTableEncoding();
1976 bool X86TargetLowering::useSoftFloat() const {
1977 return Subtarget->useSoftFloat();
1981 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1982 const MachineBasicBlock *MBB,
1983 unsigned uid,MCContext &Ctx) const{
1984 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1985 Subtarget->isPICStyleGOT());
1986 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1988 return MCSymbolRefExpr::create(MBB->getSymbol(),
1989 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1992 /// Returns relocation base for the given PIC jumptable.
1993 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1994 SelectionDAG &DAG) const {
1995 if (!Subtarget->is64Bit())
1996 // This doesn't have SDLoc associated with it, but is not really the
1997 // same as a Register.
1998 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
1999 getPointerTy(DAG.getDataLayout()));
2003 /// This returns the relocation base for the given PIC jumptable,
2004 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2005 const MCExpr *X86TargetLowering::
2006 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2007 MCContext &Ctx) const {
2008 // X86-64 uses RIP relative addressing based on the jump table label.
2009 if (Subtarget->isPICStyleRIPRel())
2010 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2012 // Otherwise, the reference is relative to the PIC base.
2013 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2016 std::pair<const TargetRegisterClass *, uint8_t>
2017 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2019 const TargetRegisterClass *RRC = nullptr;
2021 switch (VT.SimpleTy) {
2023 return TargetLowering::findRepresentativeClass(TRI, VT);
2024 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2025 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2028 RRC = &X86::VR64RegClass;
2030 case MVT::f32: case MVT::f64:
2031 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2032 case MVT::v4f32: case MVT::v2f64:
2033 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2035 RRC = &X86::VR128RegClass;
2038 return std::make_pair(RRC, Cost);
2041 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2042 unsigned &Offset) const {
2043 if (!Subtarget->isTargetLinux())
2046 if (Subtarget->is64Bit()) {
2047 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2049 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2061 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2062 unsigned DestAS) const {
2063 assert(SrcAS != DestAS && "Expected different address spaces!");
2065 return SrcAS < 256 && DestAS < 256;
2068 //===----------------------------------------------------------------------===//
2069 // Return Value Calling Convention Implementation
2070 //===----------------------------------------------------------------------===//
2072 #include "X86GenCallingConv.inc"
2075 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2076 MachineFunction &MF, bool isVarArg,
2077 const SmallVectorImpl<ISD::OutputArg> &Outs,
2078 LLVMContext &Context) const {
2079 SmallVector<CCValAssign, 16> RVLocs;
2080 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2081 return CCInfo.CheckReturn(Outs, RetCC_X86);
2084 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2085 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2090 X86TargetLowering::LowerReturn(SDValue Chain,
2091 CallingConv::ID CallConv, bool isVarArg,
2092 const SmallVectorImpl<ISD::OutputArg> &Outs,
2093 const SmallVectorImpl<SDValue> &OutVals,
2094 SDLoc dl, SelectionDAG &DAG) const {
2095 MachineFunction &MF = DAG.getMachineFunction();
2096 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2098 SmallVector<CCValAssign, 16> RVLocs;
2099 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2100 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2103 SmallVector<SDValue, 6> RetOps;
2104 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2105 // Operand #1 = Bytes To Pop
2106 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2109 // Copy the result values into the output registers.
2110 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2111 CCValAssign &VA = RVLocs[i];
2112 assert(VA.isRegLoc() && "Can only return in registers!");
2113 SDValue ValToCopy = OutVals[i];
2114 EVT ValVT = ValToCopy.getValueType();
2116 // Promote values to the appropriate types.
2117 if (VA.getLocInfo() == CCValAssign::SExt)
2118 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2119 else if (VA.getLocInfo() == CCValAssign::ZExt)
2120 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2121 else if (VA.getLocInfo() == CCValAssign::AExt) {
2122 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2123 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2125 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2127 else if (VA.getLocInfo() == CCValAssign::BCvt)
2128 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2130 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2131 "Unexpected FP-extend for return value.");
2133 // If this is x86-64, and we disabled SSE, we can't return FP values,
2134 // or SSE or MMX vectors.
2135 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2136 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2137 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2138 report_fatal_error("SSE register return with SSE disabled");
2140 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2141 // llvm-gcc has never done it right and no one has noticed, so this
2142 // should be OK for now.
2143 if (ValVT == MVT::f64 &&
2144 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2145 report_fatal_error("SSE2 register return with SSE2 disabled");
2147 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2148 // the RET instruction and handled by the FP Stackifier.
2149 if (VA.getLocReg() == X86::FP0 ||
2150 VA.getLocReg() == X86::FP1) {
2151 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2152 // change the value to the FP stack register class.
2153 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2154 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2155 RetOps.push_back(ValToCopy);
2156 // Don't emit a copytoreg.
2160 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2161 // which is returned in RAX / RDX.
2162 if (Subtarget->is64Bit()) {
2163 if (ValVT == MVT::x86mmx) {
2164 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2165 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2166 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2168 // If we don't have SSE2 available, convert to v4f32 so the generated
2169 // register is legal.
2170 if (!Subtarget->hasSSE2())
2171 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2176 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2177 Flag = Chain.getValue(1);
2178 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2181 // All x86 ABIs require that for returning structs by value we copy
2182 // the sret argument into %rax/%eax (depending on ABI) for the return.
2183 // We saved the argument into a virtual register in the entry block,
2184 // so now we copy the value out and into %rax/%eax.
2186 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2187 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2188 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2189 // either case FuncInfo->setSRetReturnReg() will have been called.
2190 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2191 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2192 getPointerTy(MF.getDataLayout()));
2195 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2196 X86::RAX : X86::EAX;
2197 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2198 Flag = Chain.getValue(1);
2200 // RAX/EAX now acts like a return value.
2202 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2205 RetOps[0] = Chain; // Update chain.
2207 // Add the flag if we have it.
2209 RetOps.push_back(Flag);
2211 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2214 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2215 if (N->getNumValues() != 1)
2217 if (!N->hasNUsesOfValue(1, 0))
2220 SDValue TCChain = Chain;
2221 SDNode *Copy = *N->use_begin();
2222 if (Copy->getOpcode() == ISD::CopyToReg) {
2223 // If the copy has a glue operand, we conservatively assume it isn't safe to
2224 // perform a tail call.
2225 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2227 TCChain = Copy->getOperand(0);
2228 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2231 bool HasRet = false;
2232 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2234 if (UI->getOpcode() != X86ISD::RET_FLAG)
2236 // If we are returning more than one value, we can definitely
2237 // not make a tail call see PR19530
2238 if (UI->getNumOperands() > 4)
2240 if (UI->getNumOperands() == 4 &&
2241 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2254 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2255 ISD::NodeType ExtendKind) const {
2257 // TODO: Is this also valid on 32-bit?
2258 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2259 ReturnMVT = MVT::i8;
2261 ReturnMVT = MVT::i32;
2263 EVT MinVT = getRegisterType(Context, ReturnMVT);
2264 return VT.bitsLT(MinVT) ? MinVT : VT;
2267 /// Lower the result values of a call into the
2268 /// appropriate copies out of appropriate physical registers.
2271 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2272 CallingConv::ID CallConv, bool isVarArg,
2273 const SmallVectorImpl<ISD::InputArg> &Ins,
2274 SDLoc dl, SelectionDAG &DAG,
2275 SmallVectorImpl<SDValue> &InVals) const {
2277 // Assign locations to each value returned by this call.
2278 SmallVector<CCValAssign, 16> RVLocs;
2279 bool Is64Bit = Subtarget->is64Bit();
2280 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2282 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2284 // Copy all of the result registers out of their specified physreg.
2285 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2286 CCValAssign &VA = RVLocs[i];
2287 EVT CopyVT = VA.getLocVT();
2289 // If this is x86-64, and we disabled SSE, we can't return FP values
2290 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2291 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2292 report_fatal_error("SSE register return with SSE disabled");
2295 // If we prefer to use the value in xmm registers, copy it out as f80 and
2296 // use a truncate to move it from fp stack reg to xmm reg.
2297 bool RoundAfterCopy = false;
2298 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2299 isScalarFPTypeInSSEReg(VA.getValVT())) {
2301 RoundAfterCopy = (CopyVT != VA.getLocVT());
2304 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2305 CopyVT, InFlag).getValue(1);
2306 SDValue Val = Chain.getValue(0);
2309 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2310 // This truncation won't change the value.
2311 DAG.getIntPtrConstant(1, dl));
2313 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2314 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2316 InFlag = Chain.getValue(2);
2317 InVals.push_back(Val);
2323 //===----------------------------------------------------------------------===//
2324 // C & StdCall & Fast Calling Convention implementation
2325 //===----------------------------------------------------------------------===//
2326 // StdCall calling convention seems to be standard for many Windows' API
2327 // routines and around. It differs from C calling convention just a little:
2328 // callee should clean up the stack, not caller. Symbols should be also
2329 // decorated in some fancy way :) It doesn't support any vector arguments.
2330 // For info on fast calling convention see Fast Calling Convention (tail call)
2331 // implementation LowerX86_32FastCCCallTo.
2333 /// CallIsStructReturn - Determines whether a call uses struct return
2335 enum StructReturnType {
2340 static StructReturnType
2341 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2343 return NotStructReturn;
2345 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2346 if (!Flags.isSRet())
2347 return NotStructReturn;
2348 if (Flags.isInReg())
2349 return RegStructReturn;
2350 return StackStructReturn;
2353 /// Determines whether a function uses struct return semantics.
2354 static StructReturnType
2355 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2357 return NotStructReturn;
2359 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2360 if (!Flags.isSRet())
2361 return NotStructReturn;
2362 if (Flags.isInReg())
2363 return RegStructReturn;
2364 return StackStructReturn;
2367 /// Make a copy of an aggregate at address specified by "Src" to address
2368 /// "Dst" with size and alignment information specified by the specific
2369 /// parameter attribute. The copy will be passed as a byval function parameter.
2371 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2372 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2374 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2376 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2377 /*isVolatile*/false, /*AlwaysInline=*/true,
2378 /*isTailCall*/false,
2379 MachinePointerInfo(), MachinePointerInfo());
2382 /// Return true if the calling convention is one that
2383 /// supports tail call optimization.
2384 static bool IsTailCallConvention(CallingConv::ID CC) {
2385 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2386 CC == CallingConv::HiPE);
2389 /// \brief Return true if the calling convention is a C calling convention.
2390 static bool IsCCallConvention(CallingConv::ID CC) {
2391 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2392 CC == CallingConv::X86_64_SysV);
2395 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2397 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2398 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2402 CallingConv::ID CalleeCC = CS.getCallingConv();
2403 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2409 /// Return true if the function is being made into
2410 /// a tailcall target by changing its ABI.
2411 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2412 bool GuaranteedTailCallOpt) {
2413 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2417 X86TargetLowering::LowerMemArgument(SDValue Chain,
2418 CallingConv::ID CallConv,
2419 const SmallVectorImpl<ISD::InputArg> &Ins,
2420 SDLoc dl, SelectionDAG &DAG,
2421 const CCValAssign &VA,
2422 MachineFrameInfo *MFI,
2424 // Create the nodes corresponding to a load from this parameter slot.
2425 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2426 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2427 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2428 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2431 // If value is passed by pointer we have address passed instead of the value
2433 bool ExtendedInMem = VA.isExtInLoc() &&
2434 VA.getValVT().getScalarType() == MVT::i1;
2436 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2437 ValVT = VA.getLocVT();
2439 ValVT = VA.getValVT();
2441 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2442 // changed with more analysis.
2443 // In case of tail call optimization mark all arguments mutable. Since they
2444 // could be overwritten by lowering of arguments in case of a tail call.
2445 if (Flags.isByVal()) {
2446 unsigned Bytes = Flags.getByValSize();
2447 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2448 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2449 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2451 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2452 VA.getLocMemOffset(), isImmutable);
2453 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2454 SDValue Val = DAG.getLoad(
2455 ValVT, dl, Chain, FIN,
2456 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2458 return ExtendedInMem ?
2459 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2463 // FIXME: Get this from tablegen.
2464 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2465 const X86Subtarget *Subtarget) {
2466 assert(Subtarget->is64Bit());
2468 if (Subtarget->isCallingConvWin64(CallConv)) {
2469 static const MCPhysReg GPR64ArgRegsWin64[] = {
2470 X86::RCX, X86::RDX, X86::R8, X86::R9
2472 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2475 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2476 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2478 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2481 // FIXME: Get this from tablegen.
2482 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2483 CallingConv::ID CallConv,
2484 const X86Subtarget *Subtarget) {
2485 assert(Subtarget->is64Bit());
2486 if (Subtarget->isCallingConvWin64(CallConv)) {
2487 // The XMM registers which might contain var arg parameters are shadowed
2488 // in their paired GPR. So we only need to save the GPR to their home
2490 // TODO: __vectorcall will change this.
2494 const Function *Fn = MF.getFunction();
2495 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2496 bool isSoftFloat = Subtarget->useSoftFloat();
2497 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2498 "SSE register cannot be used when SSE is disabled!");
2499 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2500 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2504 static const MCPhysReg XMMArgRegs64Bit[] = {
2505 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2506 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2508 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2512 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2513 CallingConv::ID CallConv,
2515 const SmallVectorImpl<ISD::InputArg> &Ins,
2518 SmallVectorImpl<SDValue> &InVals)
2520 MachineFunction &MF = DAG.getMachineFunction();
2521 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2522 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2524 const Function* Fn = MF.getFunction();
2525 if (Fn->hasExternalLinkage() &&
2526 Subtarget->isTargetCygMing() &&
2527 Fn->getName() == "main")
2528 FuncInfo->setForceFramePointer(true);
2530 MachineFrameInfo *MFI = MF.getFrameInfo();
2531 bool Is64Bit = Subtarget->is64Bit();
2532 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2534 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2535 "Var args not supported with calling convention fastcc, ghc or hipe");
2537 // Assign locations to all of the incoming arguments.
2538 SmallVector<CCValAssign, 16> ArgLocs;
2539 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2541 // Allocate shadow area for Win64
2543 CCInfo.AllocateStack(32, 8);
2545 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2547 unsigned LastVal = ~0U;
2549 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2550 CCValAssign &VA = ArgLocs[i];
2551 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2553 assert(VA.getValNo() != LastVal &&
2554 "Don't support value assigned to multiple locs yet");
2556 LastVal = VA.getValNo();
2558 if (VA.isRegLoc()) {
2559 EVT RegVT = VA.getLocVT();
2560 const TargetRegisterClass *RC;
2561 if (RegVT == MVT::i32)
2562 RC = &X86::GR32RegClass;
2563 else if (Is64Bit && RegVT == MVT::i64)
2564 RC = &X86::GR64RegClass;
2565 else if (RegVT == MVT::f32)
2566 RC = &X86::FR32RegClass;
2567 else if (RegVT == MVT::f64)
2568 RC = &X86::FR64RegClass;
2569 else if (RegVT.is512BitVector())
2570 RC = &X86::VR512RegClass;
2571 else if (RegVT.is256BitVector())
2572 RC = &X86::VR256RegClass;
2573 else if (RegVT.is128BitVector())
2574 RC = &X86::VR128RegClass;
2575 else if (RegVT == MVT::x86mmx)
2576 RC = &X86::VR64RegClass;
2577 else if (RegVT == MVT::i1)
2578 RC = &X86::VK1RegClass;
2579 else if (RegVT == MVT::v8i1)
2580 RC = &X86::VK8RegClass;
2581 else if (RegVT == MVT::v16i1)
2582 RC = &X86::VK16RegClass;
2583 else if (RegVT == MVT::v32i1)
2584 RC = &X86::VK32RegClass;
2585 else if (RegVT == MVT::v64i1)
2586 RC = &X86::VK64RegClass;
2588 llvm_unreachable("Unknown argument type!");
2590 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2591 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2593 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2594 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2596 if (VA.getLocInfo() == CCValAssign::SExt)
2597 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2598 DAG.getValueType(VA.getValVT()));
2599 else if (VA.getLocInfo() == CCValAssign::ZExt)
2600 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2601 DAG.getValueType(VA.getValVT()));
2602 else if (VA.getLocInfo() == CCValAssign::BCvt)
2603 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2605 if (VA.isExtInLoc()) {
2606 // Handle MMX values passed in XMM regs.
2607 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2608 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2610 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2613 assert(VA.isMemLoc());
2614 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2617 // If value is passed via pointer - do a load.
2618 if (VA.getLocInfo() == CCValAssign::Indirect)
2619 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2620 MachinePointerInfo(), false, false, false, 0);
2622 InVals.push_back(ArgValue);
2625 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2626 // All x86 ABIs require that for returning structs by value we copy the
2627 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2628 // the argument into a virtual register so that we can access it from the
2630 if (Ins[i].Flags.isSRet()) {
2631 unsigned Reg = FuncInfo->getSRetReturnReg();
2633 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2634 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2635 FuncInfo->setSRetReturnReg(Reg);
2637 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2638 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2643 unsigned StackSize = CCInfo.getNextStackOffset();
2644 // Align stack specially for tail calls.
2645 if (FuncIsMadeTailCallSafe(CallConv,
2646 MF.getTarget().Options.GuaranteedTailCallOpt))
2647 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2649 // If the function takes variable number of arguments, make a frame index for
2650 // the start of the first vararg value... for expansion of llvm.va_start. We
2651 // can skip this if there are no va_start calls.
2652 if (MFI->hasVAStart() &&
2653 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2654 CallConv != CallingConv::X86_ThisCall))) {
2655 FuncInfo->setVarArgsFrameIndex(
2656 MFI->CreateFixedObject(1, StackSize, true));
2659 MachineModuleInfo &MMI = MF.getMMI();
2660 const Function *WinEHParent = nullptr;
2661 if (MMI.hasWinEHFuncInfo(Fn))
2662 WinEHParent = MMI.getWinEHParent(Fn);
2663 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2665 // Figure out if XMM registers are in use.
2666 assert(!(Subtarget->useSoftFloat() &&
2667 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2668 "SSE register cannot be used when SSE is disabled!");
2670 // 64-bit calling conventions support varargs and register parameters, so we
2671 // have to do extra work to spill them in the prologue.
2672 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2673 // Find the first unallocated argument registers.
2674 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2675 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2676 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2677 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2678 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2679 "SSE register cannot be used when SSE is disabled!");
2681 // Gather all the live in physical registers.
2682 SmallVector<SDValue, 6> LiveGPRs;
2683 SmallVector<SDValue, 8> LiveXMMRegs;
2685 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2686 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2688 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2690 if (!ArgXMMs.empty()) {
2691 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2692 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2693 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2694 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2695 LiveXMMRegs.push_back(
2696 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2701 // Get to the caller-allocated home save location. Add 8 to account
2702 // for the return address.
2703 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2704 FuncInfo->setRegSaveFrameIndex(
2705 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2706 // Fixup to set vararg frame on shadow area (4 x i64).
2708 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2710 // For X86-64, if there are vararg parameters that are passed via
2711 // registers, then we must store them to their spots on the stack so
2712 // they may be loaded by deferencing the result of va_next.
2713 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2714 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2715 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2716 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2719 // Store the integer parameter registers.
2720 SmallVector<SDValue, 8> MemOps;
2721 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2722 getPointerTy(DAG.getDataLayout()));
2723 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2724 for (SDValue Val : LiveGPRs) {
2725 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2726 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2728 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2729 MachinePointerInfo::getFixedStack(
2730 DAG.getMachineFunction(),
2731 FuncInfo->getRegSaveFrameIndex(), Offset),
2733 MemOps.push_back(Store);
2737 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2738 // Now store the XMM (fp + vector) parameter registers.
2739 SmallVector<SDValue, 12> SaveXMMOps;
2740 SaveXMMOps.push_back(Chain);
2741 SaveXMMOps.push_back(ALVal);
2742 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2743 FuncInfo->getRegSaveFrameIndex(), dl));
2744 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2745 FuncInfo->getVarArgsFPOffset(), dl));
2746 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2748 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2749 MVT::Other, SaveXMMOps));
2752 if (!MemOps.empty())
2753 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2756 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2757 // Find the largest legal vector type.
2758 MVT VecVT = MVT::Other;
2759 // FIXME: Only some x86_32 calling conventions support AVX512.
2760 if (Subtarget->hasAVX512() &&
2761 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2762 CallConv == CallingConv::Intel_OCL_BI)))
2763 VecVT = MVT::v16f32;
2764 else if (Subtarget->hasAVX())
2766 else if (Subtarget->hasSSE2())
2769 // We forward some GPRs and some vector types.
2770 SmallVector<MVT, 2> RegParmTypes;
2771 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2772 RegParmTypes.push_back(IntVT);
2773 if (VecVT != MVT::Other)
2774 RegParmTypes.push_back(VecVT);
2776 // Compute the set of forwarded registers. The rest are scratch.
2777 SmallVectorImpl<ForwardedRegister> &Forwards =
2778 FuncInfo->getForwardedMustTailRegParms();
2779 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2781 // Conservatively forward AL on x86_64, since it might be used for varargs.
2782 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2783 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2784 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2787 // Copy all forwards from physical to virtual registers.
2788 for (ForwardedRegister &F : Forwards) {
2789 // FIXME: Can we use a less constrained schedule?
2790 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2791 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2792 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2796 // Some CCs need callee pop.
2797 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2798 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2799 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2801 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2802 // If this is an sret function, the return should pop the hidden pointer.
2803 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2804 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2805 argsAreStructReturn(Ins) == StackStructReturn)
2806 FuncInfo->setBytesToPopOnReturn(4);
2810 // RegSaveFrameIndex is X86-64 only.
2811 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2812 if (CallConv == CallingConv::X86_FastCall ||
2813 CallConv == CallingConv::X86_ThisCall)
2814 // fastcc functions can't have varargs.
2815 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2818 FuncInfo->setArgumentStackSize(StackSize);
2820 if (IsWinEHParent) {
2822 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2823 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2824 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2825 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2826 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2827 MachinePointerInfo::getFixedStack(
2828 DAG.getMachineFunction(), UnwindHelpFI),
2829 /*isVolatile=*/true,
2830 /*isNonTemporal=*/false, /*Alignment=*/0);
2832 // Functions using Win32 EH are considered to have opaque SP adjustments
2833 // to force local variables to be addressed from the frame or base
2835 MFI->setHasOpaqueSPAdjustment(true);
2843 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2844 SDValue StackPtr, SDValue Arg,
2845 SDLoc dl, SelectionDAG &DAG,
2846 const CCValAssign &VA,
2847 ISD::ArgFlagsTy Flags) const {
2848 unsigned LocMemOffset = VA.getLocMemOffset();
2849 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2850 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2852 if (Flags.isByVal())
2853 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2855 return DAG.getStore(
2856 Chain, dl, Arg, PtrOff,
2857 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2861 /// Emit a load of return address if tail call
2862 /// optimization is performed and it is required.
2864 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2865 SDValue &OutRetAddr, SDValue Chain,
2866 bool IsTailCall, bool Is64Bit,
2867 int FPDiff, SDLoc dl) const {
2868 // Adjust the Return address stack slot.
2869 EVT VT = getPointerTy(DAG.getDataLayout());
2870 OutRetAddr = getReturnAddressFrameIndex(DAG);
2872 // Load the "old" Return address.
2873 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2874 false, false, false, 0);
2875 return SDValue(OutRetAddr.getNode(), 1);
2878 /// Emit a store of the return address if tail call
2879 /// optimization is performed and it is required (FPDiff!=0).
2880 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2881 SDValue Chain, SDValue RetAddrFrIdx,
2882 EVT PtrVT, unsigned SlotSize,
2883 int FPDiff, SDLoc dl) {
2884 // Store the return address to the appropriate stack slot.
2885 if (!FPDiff) return Chain;
2886 // Calculate the new stack slot for the return address.
2887 int NewReturnAddrFI =
2888 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2890 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2891 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2892 MachinePointerInfo::getFixedStack(
2893 DAG.getMachineFunction(), NewReturnAddrFI),
2898 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2899 /// operation of specified width.
2900 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
2902 unsigned NumElems = VT.getVectorNumElements();
2903 SmallVector<int, 8> Mask;
2904 Mask.push_back(NumElems);
2905 for (unsigned i = 1; i != NumElems; ++i)
2907 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2911 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2912 SmallVectorImpl<SDValue> &InVals) const {
2913 SelectionDAG &DAG = CLI.DAG;
2915 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2916 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2917 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2918 SDValue Chain = CLI.Chain;
2919 SDValue Callee = CLI.Callee;
2920 CallingConv::ID CallConv = CLI.CallConv;
2921 bool &isTailCall = CLI.IsTailCall;
2922 bool isVarArg = CLI.IsVarArg;
2924 MachineFunction &MF = DAG.getMachineFunction();
2925 bool Is64Bit = Subtarget->is64Bit();
2926 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2927 StructReturnType SR = callIsStructReturn(Outs);
2928 bool IsSibcall = false;
2929 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2930 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2932 if (Attr.getValueAsString() == "true")
2935 if (Subtarget->isPICStyleGOT() &&
2936 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2937 // If we are using a GOT, disable tail calls to external symbols with
2938 // default visibility. Tail calling such a symbol requires using a GOT
2939 // relocation, which forces early binding of the symbol. This breaks code
2940 // that require lazy function symbol resolution. Using musttail or
2941 // GuaranteedTailCallOpt will override this.
2942 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2943 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2944 G->getGlobal()->hasDefaultVisibility()))
2948 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2950 // Force this to be a tail call. The verifier rules are enough to ensure
2951 // that we can lower this successfully without moving the return address
2954 } else if (isTailCall) {
2955 // Check if it's really possible to do a tail call.
2956 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2957 isVarArg, SR != NotStructReturn,
2958 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2959 Outs, OutVals, Ins, DAG);
2961 // Sibcalls are automatically detected tailcalls which do not require
2963 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2970 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2971 "Var args not supported with calling convention fastcc, ghc or hipe");
2973 // Analyze operands of the call, assigning locations to each operand.
2974 SmallVector<CCValAssign, 16> ArgLocs;
2975 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2977 // Allocate shadow area for Win64
2979 CCInfo.AllocateStack(32, 8);
2981 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2983 // Get a count of how many bytes are to be pushed on the stack.
2984 unsigned NumBytes = CCInfo.getNextStackOffset();
2986 // This is a sibcall. The memory operands are available in caller's
2987 // own caller's stack.
2989 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2990 IsTailCallConvention(CallConv))
2991 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2994 if (isTailCall && !IsSibcall && !IsMustTail) {
2995 // Lower arguments at fp - stackoffset + fpdiff.
2996 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2998 FPDiff = NumBytesCallerPushed - NumBytes;
3000 // Set the delta of movement of the returnaddr stackslot.
3001 // But only set if delta is greater than previous delta.
3002 if (FPDiff < X86Info->getTCReturnAddrDelta())
3003 X86Info->setTCReturnAddrDelta(FPDiff);
3006 unsigned NumBytesToPush = NumBytes;
3007 unsigned NumBytesToPop = NumBytes;
3009 // If we have an inalloca argument, all stack space has already been allocated
3010 // for us and be right at the top of the stack. We don't support multiple
3011 // arguments passed in memory when using inalloca.
3012 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3014 if (!ArgLocs.back().isMemLoc())
3015 report_fatal_error("cannot use inalloca attribute on a register "
3017 if (ArgLocs.back().getLocMemOffset() != 0)
3018 report_fatal_error("any parameter with the inalloca attribute must be "
3019 "the only memory argument");
3023 Chain = DAG.getCALLSEQ_START(
3024 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3026 SDValue RetAddrFrIdx;
3027 // Load return address for tail calls.
3028 if (isTailCall && FPDiff)
3029 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3030 Is64Bit, FPDiff, dl);
3032 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3033 SmallVector<SDValue, 8> MemOpChains;
3036 // Walk the register/memloc assignments, inserting copies/loads. In the case
3037 // of tail call optimization arguments are handle later.
3038 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3039 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3040 // Skip inalloca arguments, they have already been written.
3041 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3042 if (Flags.isInAlloca())
3045 CCValAssign &VA = ArgLocs[i];
3046 EVT RegVT = VA.getLocVT();
3047 SDValue Arg = OutVals[i];
3048 bool isByVal = Flags.isByVal();
3050 // Promote the value if needed.
3051 switch (VA.getLocInfo()) {
3052 default: llvm_unreachable("Unknown loc info!");
3053 case CCValAssign::Full: break;
3054 case CCValAssign::SExt:
3055 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3057 case CCValAssign::ZExt:
3058 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3060 case CCValAssign::AExt:
3061 if (Arg.getValueType().isVector() &&
3062 Arg.getValueType().getScalarType() == MVT::i1)
3063 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3064 else if (RegVT.is128BitVector()) {
3065 // Special case: passing MMX values in XMM registers.
3066 Arg = DAG.getBitcast(MVT::i64, Arg);
3067 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3068 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3070 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3072 case CCValAssign::BCvt:
3073 Arg = DAG.getBitcast(RegVT, Arg);
3075 case CCValAssign::Indirect: {
3076 // Store the argument.
3077 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3078 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3079 Chain = DAG.getStore(
3080 Chain, dl, Arg, SpillSlot,
3081 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3088 if (VA.isRegLoc()) {
3089 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3090 if (isVarArg && IsWin64) {
3091 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3092 // shadow reg if callee is a varargs function.
3093 unsigned ShadowReg = 0;
3094 switch (VA.getLocReg()) {
3095 case X86::XMM0: ShadowReg = X86::RCX; break;
3096 case X86::XMM1: ShadowReg = X86::RDX; break;
3097 case X86::XMM2: ShadowReg = X86::R8; break;
3098 case X86::XMM3: ShadowReg = X86::R9; break;
3101 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3103 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3104 assert(VA.isMemLoc());
3105 if (!StackPtr.getNode())
3106 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3107 getPointerTy(DAG.getDataLayout()));
3108 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3109 dl, DAG, VA, Flags));
3113 if (!MemOpChains.empty())
3114 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3116 if (Subtarget->isPICStyleGOT()) {
3117 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3120 RegsToPass.push_back(std::make_pair(
3121 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3122 getPointerTy(DAG.getDataLayout()))));
3124 // If we are tail calling and generating PIC/GOT style code load the
3125 // address of the callee into ECX. The value in ecx is used as target of
3126 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3127 // for tail calls on PIC/GOT architectures. Normally we would just put the
3128 // address of GOT into ebx and then call target@PLT. But for tail calls
3129 // ebx would be restored (since ebx is callee saved) before jumping to the
3132 // Note: The actual moving to ECX is done further down.
3133 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3134 if (G && !G->getGlobal()->hasLocalLinkage() &&
3135 G->getGlobal()->hasDefaultVisibility())
3136 Callee = LowerGlobalAddress(Callee, DAG);
3137 else if (isa<ExternalSymbolSDNode>(Callee))
3138 Callee = LowerExternalSymbol(Callee, DAG);
3142 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3143 // From AMD64 ABI document:
3144 // For calls that may call functions that use varargs or stdargs
3145 // (prototype-less calls or calls to functions containing ellipsis (...) in
3146 // the declaration) %al is used as hidden argument to specify the number
3147 // of SSE registers used. The contents of %al do not need to match exactly
3148 // the number of registers, but must be an ubound on the number of SSE
3149 // registers used and is in the range 0 - 8 inclusive.
3151 // Count the number of XMM registers allocated.
3152 static const MCPhysReg XMMArgRegs[] = {
3153 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3154 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3156 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3157 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3158 && "SSE registers cannot be used when SSE is disabled");
3160 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3161 DAG.getConstant(NumXMMRegs, dl,
3165 if (isVarArg && IsMustTail) {
3166 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3167 for (const auto &F : Forwards) {
3168 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3169 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3173 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3174 // don't need this because the eligibility check rejects calls that require
3175 // shuffling arguments passed in memory.
3176 if (!IsSibcall && isTailCall) {
3177 // Force all the incoming stack arguments to be loaded from the stack
3178 // before any new outgoing arguments are stored to the stack, because the
3179 // outgoing stack slots may alias the incoming argument stack slots, and
3180 // the alias isn't otherwise explicit. This is slightly more conservative
3181 // than necessary, because it means that each store effectively depends
3182 // on every argument instead of just those arguments it would clobber.
3183 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3185 SmallVector<SDValue, 8> MemOpChains2;
3188 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3189 CCValAssign &VA = ArgLocs[i];
3192 assert(VA.isMemLoc());
3193 SDValue Arg = OutVals[i];
3194 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3195 // Skip inalloca arguments. They don't require any work.
3196 if (Flags.isInAlloca())
3198 // Create frame index.
3199 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3200 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3201 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3202 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3204 if (Flags.isByVal()) {
3205 // Copy relative to framepointer.
3206 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3207 if (!StackPtr.getNode())
3208 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3209 getPointerTy(DAG.getDataLayout()));
3210 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3213 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3217 // Store relative to framepointer.
3218 MemOpChains2.push_back(DAG.getStore(
3219 ArgChain, dl, Arg, FIN,
3220 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3225 if (!MemOpChains2.empty())
3226 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3228 // Store the return address to the appropriate stack slot.
3229 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3230 getPointerTy(DAG.getDataLayout()),
3231 RegInfo->getSlotSize(), FPDiff, dl);
3234 // Build a sequence of copy-to-reg nodes chained together with token chain
3235 // and flag operands which copy the outgoing args into registers.
3237 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3238 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3239 RegsToPass[i].second, InFlag);
3240 InFlag = Chain.getValue(1);
3243 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3244 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3245 // In the 64-bit large code model, we have to make all calls
3246 // through a register, since the call instruction's 32-bit
3247 // pc-relative offset may not be large enough to hold the whole
3249 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3250 // If the callee is a GlobalAddress node (quite common, every direct call
3251 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3253 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3255 // We should use extra load for direct calls to dllimported functions in
3257 const GlobalValue *GV = G->getGlobal();
3258 if (!GV->hasDLLImportStorageClass()) {
3259 unsigned char OpFlags = 0;
3260 bool ExtraLoad = false;
3261 unsigned WrapperKind = ISD::DELETED_NODE;
3263 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3264 // external symbols most go through the PLT in PIC mode. If the symbol
3265 // has hidden or protected visibility, or if it is static or local, then
3266 // we don't need to use the PLT - we can directly call it.
3267 if (Subtarget->isTargetELF() &&
3268 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3269 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3270 OpFlags = X86II::MO_PLT;
3271 } else if (Subtarget->isPICStyleStubAny() &&
3272 !GV->isStrongDefinitionForLinker() &&
3273 (!Subtarget->getTargetTriple().isMacOSX() ||
3274 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3275 // PC-relative references to external symbols should go through $stub,
3276 // unless we're building with the leopard linker or later, which
3277 // automatically synthesizes these stubs.
3278 OpFlags = X86II::MO_DARWIN_STUB;
3279 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3280 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3281 // If the function is marked as non-lazy, generate an indirect call
3282 // which loads from the GOT directly. This avoids runtime overhead
3283 // at the cost of eager binding (and one extra byte of encoding).
3284 OpFlags = X86II::MO_GOTPCREL;
3285 WrapperKind = X86ISD::WrapperRIP;
3289 Callee = DAG.getTargetGlobalAddress(
3290 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3292 // Add a wrapper if needed.
3293 if (WrapperKind != ISD::DELETED_NODE)
3294 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3295 getPointerTy(DAG.getDataLayout()), Callee);
3296 // Add extra indirection if needed.
3298 Callee = DAG.getLoad(
3299 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3300 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3303 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3304 unsigned char OpFlags = 0;
3306 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3307 // external symbols should go through the PLT.
3308 if (Subtarget->isTargetELF() &&
3309 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3310 OpFlags = X86II::MO_PLT;
3311 } else if (Subtarget->isPICStyleStubAny() &&
3312 (!Subtarget->getTargetTriple().isMacOSX() ||
3313 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3314 // PC-relative references to external symbols should go through $stub,
3315 // unless we're building with the leopard linker or later, which
3316 // automatically synthesizes these stubs.
3317 OpFlags = X86II::MO_DARWIN_STUB;
3320 Callee = DAG.getTargetExternalSymbol(
3321 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3322 } else if (Subtarget->isTarget64BitILP32() &&
3323 Callee->getValueType(0) == MVT::i32) {
3324 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3325 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3328 // Returns a chain & a flag for retval copy to use.
3329 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3330 SmallVector<SDValue, 8> Ops;
3332 if (!IsSibcall && isTailCall) {
3333 Chain = DAG.getCALLSEQ_END(Chain,
3334 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3335 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3336 InFlag = Chain.getValue(1);
3339 Ops.push_back(Chain);
3340 Ops.push_back(Callee);
3343 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3345 // Add argument registers to the end of the list so that they are known live
3347 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3348 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3349 RegsToPass[i].second.getValueType()));
3351 // Add a register mask operand representing the call-preserved registers.
3352 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3353 assert(Mask && "Missing call preserved mask for calling convention");
3355 // If this is an invoke in a 32-bit function using an MSVC personality, assume
3356 // the function clobbers all registers. If an exception is thrown, the runtime
3357 // will not restore CSRs.
3358 // FIXME: Model this more precisely so that we can register allocate across
3359 // the normal edge and spill and fill across the exceptional edge.
3360 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3361 const Function *CallerFn = MF.getFunction();
3362 EHPersonality Pers =
3363 CallerFn->hasPersonalityFn()
3364 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3365 : EHPersonality::Unknown;
3366 if (isMSVCEHPersonality(Pers))
3367 Mask = RegInfo->getNoPreservedMask();
3370 Ops.push_back(DAG.getRegisterMask(Mask));
3372 if (InFlag.getNode())
3373 Ops.push_back(InFlag);
3377 //// If this is the first return lowered for this function, add the regs
3378 //// to the liveout set for the function.
3379 // This isn't right, although it's probably harmless on x86; liveouts
3380 // should be computed from returns not tail calls. Consider a void
3381 // function making a tail call to a function returning int.
3382 MF.getFrameInfo()->setHasTailCall();
3383 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3386 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3387 InFlag = Chain.getValue(1);
3389 // Create the CALLSEQ_END node.
3390 unsigned NumBytesForCalleeToPop;
3391 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3392 DAG.getTarget().Options.GuaranteedTailCallOpt))
3393 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3394 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3395 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3396 SR == StackStructReturn)
3397 // If this is a call to a struct-return function, the callee
3398 // pops the hidden struct pointer, so we have to push it back.
3399 // This is common for Darwin/X86, Linux & Mingw32 targets.
3400 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3401 NumBytesForCalleeToPop = 4;
3403 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3405 // Returns a flag for retval copy to use.
3407 Chain = DAG.getCALLSEQ_END(Chain,
3408 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3409 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3412 InFlag = Chain.getValue(1);
3415 // Handle result values, copying them out of physregs into vregs that we
3417 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3418 Ins, dl, DAG, InVals);
3421 //===----------------------------------------------------------------------===//
3422 // Fast Calling Convention (tail call) implementation
3423 //===----------------------------------------------------------------------===//
3425 // Like std call, callee cleans arguments, convention except that ECX is
3426 // reserved for storing the tail called function address. Only 2 registers are
3427 // free for argument passing (inreg). Tail call optimization is performed
3429 // * tailcallopt is enabled
3430 // * caller/callee are fastcc
3431 // On X86_64 architecture with GOT-style position independent code only local
3432 // (within module) calls are supported at the moment.
3433 // To keep the stack aligned according to platform abi the function
3434 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3435 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3436 // If a tail called function callee has more arguments than the caller the
3437 // caller needs to make sure that there is room to move the RETADDR to. This is
3438 // achieved by reserving an area the size of the argument delta right after the
3439 // original RETADDR, but before the saved framepointer or the spilled registers
3440 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3452 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3455 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3456 SelectionDAG& DAG) const {
3457 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3458 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3459 unsigned StackAlignment = TFI.getStackAlignment();
3460 uint64_t AlignMask = StackAlignment - 1;
3461 int64_t Offset = StackSize;
3462 unsigned SlotSize = RegInfo->getSlotSize();
3463 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3464 // Number smaller than 12 so just add the difference.
3465 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3467 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3468 Offset = ((~AlignMask) & Offset) + StackAlignment +
3469 (StackAlignment-SlotSize);
3474 /// Return true if the given stack call argument is already available in the
3475 /// same position (relatively) of the caller's incoming argument stack.
3477 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3478 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3479 const X86InstrInfo *TII) {
3480 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3482 if (Arg.getOpcode() == ISD::CopyFromReg) {
3483 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3484 if (!TargetRegisterInfo::isVirtualRegister(VR))
3486 MachineInstr *Def = MRI->getVRegDef(VR);
3489 if (!Flags.isByVal()) {
3490 if (!TII->isLoadFromStackSlot(Def, FI))
3493 unsigned Opcode = Def->getOpcode();
3494 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3495 Opcode == X86::LEA64_32r) &&
3496 Def->getOperand(1).isFI()) {
3497 FI = Def->getOperand(1).getIndex();
3498 Bytes = Flags.getByValSize();
3502 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3503 if (Flags.isByVal())
3504 // ByVal argument is passed in as a pointer but it's now being
3505 // dereferenced. e.g.
3506 // define @foo(%struct.X* %A) {
3507 // tail call @bar(%struct.X* byval %A)
3510 SDValue Ptr = Ld->getBasePtr();
3511 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3514 FI = FINode->getIndex();
3515 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3516 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3517 FI = FINode->getIndex();
3518 Bytes = Flags.getByValSize();
3522 assert(FI != INT_MAX);
3523 if (!MFI->isFixedObjectIndex(FI))
3525 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3528 /// Check whether the call is eligible for tail call optimization. Targets
3529 /// that want to do tail call optimization should implement this function.
3531 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3532 CallingConv::ID CalleeCC,
3534 bool isCalleeStructRet,
3535 bool isCallerStructRet,
3537 const SmallVectorImpl<ISD::OutputArg> &Outs,
3538 const SmallVectorImpl<SDValue> &OutVals,
3539 const SmallVectorImpl<ISD::InputArg> &Ins,
3540 SelectionDAG &DAG) const {
3541 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3544 // If -tailcallopt is specified, make fastcc functions tail-callable.
3545 const MachineFunction &MF = DAG.getMachineFunction();
3546 const Function *CallerF = MF.getFunction();
3548 // If the function return type is x86_fp80 and the callee return type is not,
3549 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3550 // perform a tailcall optimization here.
3551 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3554 CallingConv::ID CallerCC = CallerF->getCallingConv();
3555 bool CCMatch = CallerCC == CalleeCC;
3556 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3557 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3559 // Win64 functions have extra shadow space for argument homing. Don't do the
3560 // sibcall if the caller and callee have mismatched expectations for this
3562 if (IsCalleeWin64 != IsCallerWin64)
3565 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3566 if (IsTailCallConvention(CalleeCC) && CCMatch)
3571 // Look for obvious safe cases to perform tail call optimization that do not
3572 // require ABI changes. This is what gcc calls sibcall.
3574 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3575 // emit a special epilogue.
3576 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3577 if (RegInfo->needsStackRealignment(MF))
3580 // Also avoid sibcall optimization if either caller or callee uses struct
3581 // return semantics.
3582 if (isCalleeStructRet || isCallerStructRet)
3585 // An stdcall/thiscall caller is expected to clean up its arguments; the
3586 // callee isn't going to do that.
3587 // FIXME: this is more restrictive than needed. We could produce a tailcall
3588 // when the stack adjustment matches. For example, with a thiscall that takes
3589 // only one argument.
3590 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3591 CallerCC == CallingConv::X86_ThisCall))
3594 // Do not sibcall optimize vararg calls unless all arguments are passed via
3596 if (isVarArg && !Outs.empty()) {
3598 // Optimizing for varargs on Win64 is unlikely to be safe without
3599 // additional testing.
3600 if (IsCalleeWin64 || IsCallerWin64)
3603 SmallVector<CCValAssign, 16> ArgLocs;
3604 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3607 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3608 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3609 if (!ArgLocs[i].isRegLoc())
3613 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3614 // stack. Therefore, if it's not used by the call it is not safe to optimize
3615 // this into a sibcall.
3616 bool Unused = false;
3617 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3624 SmallVector<CCValAssign, 16> RVLocs;
3625 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3627 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3628 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3629 CCValAssign &VA = RVLocs[i];
3630 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3635 // If the calling conventions do not match, then we'd better make sure the
3636 // results are returned in the same way as what the caller expects.
3638 SmallVector<CCValAssign, 16> RVLocs1;
3639 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3641 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3643 SmallVector<CCValAssign, 16> RVLocs2;
3644 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3646 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3648 if (RVLocs1.size() != RVLocs2.size())
3650 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3651 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3653 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3655 if (RVLocs1[i].isRegLoc()) {
3656 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3659 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3665 // If the callee takes no arguments then go on to check the results of the
3667 if (!Outs.empty()) {
3668 // Check if stack adjustment is needed. For now, do not do this if any
3669 // argument is passed on the stack.
3670 SmallVector<CCValAssign, 16> ArgLocs;
3671 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3674 // Allocate shadow area for Win64
3676 CCInfo.AllocateStack(32, 8);
3678 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3679 if (CCInfo.getNextStackOffset()) {
3680 MachineFunction &MF = DAG.getMachineFunction();
3681 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3684 // Check if the arguments are already laid out in the right way as
3685 // the caller's fixed stack objects.
3686 MachineFrameInfo *MFI = MF.getFrameInfo();
3687 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3688 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3689 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3690 CCValAssign &VA = ArgLocs[i];
3691 SDValue Arg = OutVals[i];
3692 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3693 if (VA.getLocInfo() == CCValAssign::Indirect)
3695 if (!VA.isRegLoc()) {
3696 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3703 // If the tailcall address may be in a register, then make sure it's
3704 // possible to register allocate for it. In 32-bit, the call address can
3705 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3706 // callee-saved registers are restored. These happen to be the same
3707 // registers used to pass 'inreg' arguments so watch out for those.
3708 if (!Subtarget->is64Bit() &&
3709 ((!isa<GlobalAddressSDNode>(Callee) &&
3710 !isa<ExternalSymbolSDNode>(Callee)) ||
3711 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3712 unsigned NumInRegs = 0;
3713 // In PIC we need an extra register to formulate the address computation
3715 unsigned MaxInRegs =
3716 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3718 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3719 CCValAssign &VA = ArgLocs[i];
3722 unsigned Reg = VA.getLocReg();
3725 case X86::EAX: case X86::EDX: case X86::ECX:
3726 if (++NumInRegs == MaxInRegs)
3738 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3739 const TargetLibraryInfo *libInfo) const {
3740 return X86::createFastISel(funcInfo, libInfo);
3743 //===----------------------------------------------------------------------===//
3744 // Other Lowering Hooks
3745 //===----------------------------------------------------------------------===//
3747 static bool MayFoldLoad(SDValue Op) {
3748 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3751 static bool MayFoldIntoStore(SDValue Op) {
3752 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3755 static bool isTargetShuffle(unsigned Opcode) {
3757 default: return false;
3758 case X86ISD::BLENDI:
3759 case X86ISD::PSHUFB:
3760 case X86ISD::PSHUFD:
3761 case X86ISD::PSHUFHW:
3762 case X86ISD::PSHUFLW:
3764 case X86ISD::PALIGNR:
3765 case X86ISD::MOVLHPS:
3766 case X86ISD::MOVLHPD:
3767 case X86ISD::MOVHLPS:
3768 case X86ISD::MOVLPS:
3769 case X86ISD::MOVLPD:
3770 case X86ISD::MOVSHDUP:
3771 case X86ISD::MOVSLDUP:
3772 case X86ISD::MOVDDUP:
3775 case X86ISD::UNPCKL:
3776 case X86ISD::UNPCKH:
3777 case X86ISD::VPERMILPI:
3778 case X86ISD::VPERM2X128:
3779 case X86ISD::VPERMI:
3780 case X86ISD::VPERMV:
3781 case X86ISD::VPERMV3:
3786 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3787 SDValue V1, unsigned TargetMask,
3788 SelectionDAG &DAG) {
3790 default: llvm_unreachable("Unknown x86 shuffle node");
3791 case X86ISD::PSHUFD:
3792 case X86ISD::PSHUFHW:
3793 case X86ISD::PSHUFLW:
3794 case X86ISD::VPERMILPI:
3795 case X86ISD::VPERMI:
3796 return DAG.getNode(Opc, dl, VT, V1,
3797 DAG.getConstant(TargetMask, dl, MVT::i8));
3801 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3802 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3804 default: llvm_unreachable("Unknown x86 shuffle node");
3805 case X86ISD::MOVLHPS:
3806 case X86ISD::MOVLHPD:
3807 case X86ISD::MOVHLPS:
3808 case X86ISD::MOVLPS:
3809 case X86ISD::MOVLPD:
3812 case X86ISD::UNPCKL:
3813 case X86ISD::UNPCKH:
3814 return DAG.getNode(Opc, dl, VT, V1, V2);
3818 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3819 MachineFunction &MF = DAG.getMachineFunction();
3820 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3821 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3822 int ReturnAddrIndex = FuncInfo->getRAIndex();
3824 if (ReturnAddrIndex == 0) {
3825 // Set up a frame object for the return address.
3826 unsigned SlotSize = RegInfo->getSlotSize();
3827 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3830 FuncInfo->setRAIndex(ReturnAddrIndex);
3833 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3836 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3837 bool hasSymbolicDisplacement) {
3838 // Offset should fit into 32 bit immediate field.
3839 if (!isInt<32>(Offset))
3842 // If we don't have a symbolic displacement - we don't have any extra
3844 if (!hasSymbolicDisplacement)
3847 // FIXME: Some tweaks might be needed for medium code model.
3848 if (M != CodeModel::Small && M != CodeModel::Kernel)
3851 // For small code model we assume that latest object is 16MB before end of 31
3852 // bits boundary. We may also accept pretty large negative constants knowing
3853 // that all objects are in the positive half of address space.
3854 if (M == CodeModel::Small && Offset < 16*1024*1024)
3857 // For kernel code model we know that all object resist in the negative half
3858 // of 32bits address space. We may not accept negative offsets, since they may
3859 // be just off and we may accept pretty large positive ones.
3860 if (M == CodeModel::Kernel && Offset >= 0)
3866 /// Determines whether the callee is required to pop its own arguments.
3867 /// Callee pop is necessary to support tail calls.
3868 bool X86::isCalleePop(CallingConv::ID CallingConv,
3869 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3870 switch (CallingConv) {
3873 case CallingConv::X86_StdCall:
3874 case CallingConv::X86_FastCall:
3875 case CallingConv::X86_ThisCall:
3877 case CallingConv::Fast:
3878 case CallingConv::GHC:
3879 case CallingConv::HiPE:
3886 /// \brief Return true if the condition is an unsigned comparison operation.
3887 static bool isX86CCUnsigned(unsigned X86CC) {
3889 default: llvm_unreachable("Invalid integer condition!");
3890 case X86::COND_E: return true;
3891 case X86::COND_G: return false;
3892 case X86::COND_GE: return false;
3893 case X86::COND_L: return false;
3894 case X86::COND_LE: return false;
3895 case X86::COND_NE: return true;
3896 case X86::COND_B: return true;
3897 case X86::COND_A: return true;
3898 case X86::COND_BE: return true;
3899 case X86::COND_AE: return true;
3901 llvm_unreachable("covered switch fell through?!");
3904 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3905 /// condition code, returning the condition code and the LHS/RHS of the
3906 /// comparison to make.
3907 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3908 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3910 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3911 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3912 // X > -1 -> X == 0, jump !sign.
3913 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3914 return X86::COND_NS;
3916 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3917 // X < 0 -> X == 0, jump on sign.
3920 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3922 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3923 return X86::COND_LE;
3927 switch (SetCCOpcode) {
3928 default: llvm_unreachable("Invalid integer condition!");
3929 case ISD::SETEQ: return X86::COND_E;
3930 case ISD::SETGT: return X86::COND_G;
3931 case ISD::SETGE: return X86::COND_GE;
3932 case ISD::SETLT: return X86::COND_L;
3933 case ISD::SETLE: return X86::COND_LE;
3934 case ISD::SETNE: return X86::COND_NE;
3935 case ISD::SETULT: return X86::COND_B;
3936 case ISD::SETUGT: return X86::COND_A;
3937 case ISD::SETULE: return X86::COND_BE;
3938 case ISD::SETUGE: return X86::COND_AE;
3942 // First determine if it is required or is profitable to flip the operands.
3944 // If LHS is a foldable load, but RHS is not, flip the condition.
3945 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3946 !ISD::isNON_EXTLoad(RHS.getNode())) {
3947 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3948 std::swap(LHS, RHS);
3951 switch (SetCCOpcode) {
3957 std::swap(LHS, RHS);
3961 // On a floating point condition, the flags are set as follows:
3963 // 0 | 0 | 0 | X > Y
3964 // 0 | 0 | 1 | X < Y
3965 // 1 | 0 | 0 | X == Y
3966 // 1 | 1 | 1 | unordered
3967 switch (SetCCOpcode) {
3968 default: llvm_unreachable("Condcode should be pre-legalized away");
3970 case ISD::SETEQ: return X86::COND_E;
3971 case ISD::SETOLT: // flipped
3973 case ISD::SETGT: return X86::COND_A;
3974 case ISD::SETOLE: // flipped
3976 case ISD::SETGE: return X86::COND_AE;
3977 case ISD::SETUGT: // flipped
3979 case ISD::SETLT: return X86::COND_B;
3980 case ISD::SETUGE: // flipped
3982 case ISD::SETLE: return X86::COND_BE;
3984 case ISD::SETNE: return X86::COND_NE;
3985 case ISD::SETUO: return X86::COND_P;
3986 case ISD::SETO: return X86::COND_NP;
3988 case ISD::SETUNE: return X86::COND_INVALID;
3992 /// Is there a floating point cmov for the specific X86 condition code?
3993 /// Current x86 isa includes the following FP cmov instructions:
3994 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3995 static bool hasFPCMov(unsigned X86CC) {
4011 /// Returns true if the target can instruction select the
4012 /// specified FP immediate natively. If false, the legalizer will
4013 /// materialize the FP immediate as a load from a constant pool.
4014 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4015 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4016 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4022 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4023 ISD::LoadExtType ExtTy,
4025 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4026 // relocation target a movq or addq instruction: don't let the load shrink.
4027 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4028 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4029 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4030 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4034 /// \brief Returns true if it is beneficial to convert a load of a constant
4035 /// to just the constant itself.
4036 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4038 assert(Ty->isIntegerTy());
4040 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4041 if (BitSize == 0 || BitSize > 64)
4046 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4047 unsigned Index) const {
4048 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4051 return (Index == 0 || Index == ResVT.getVectorNumElements());
4054 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4055 // Speculate cttz only if we can directly use TZCNT.
4056 return Subtarget->hasBMI();
4059 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4060 // Speculate ctlz only if we can directly use LZCNT.
4061 return Subtarget->hasLZCNT();
4064 /// Return true if every element in Mask, beginning
4065 /// from position Pos and ending in Pos+Size is undef.
4066 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4067 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4073 /// Return true if Val is undef or if its value falls within the
4074 /// specified range (L, H].
4075 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4076 return (Val < 0) || (Val >= Low && Val < Hi);
4079 /// Val is either less than zero (undef) or equal to the specified value.
4080 static bool isUndefOrEqual(int Val, int CmpVal) {
4081 return (Val < 0 || Val == CmpVal);
4084 /// Return true if every element in Mask, beginning
4085 /// from position Pos and ending in Pos+Size, falls within the specified
4086 /// sequential range (Low, Low+Size]. or is undef.
4087 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4088 unsigned Pos, unsigned Size, int Low) {
4089 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4090 if (!isUndefOrEqual(Mask[i], Low))
4095 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4096 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4097 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4098 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4099 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4102 // The index should be aligned on a vecWidth-bit boundary.
4104 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4106 MVT VT = N->getSimpleValueType(0);
4107 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4108 bool Result = (Index * ElSize) % vecWidth == 0;
4113 /// Return true if the specified INSERT_SUBVECTOR
4114 /// operand specifies a subvector insert that is suitable for input to
4115 /// insertion of 128 or 256-bit subvectors
4116 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4117 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4118 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4120 // The index should be aligned on a vecWidth-bit boundary.
4122 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4124 MVT VT = N->getSimpleValueType(0);
4125 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4126 bool Result = (Index * ElSize) % vecWidth == 0;
4131 bool X86::isVINSERT128Index(SDNode *N) {
4132 return isVINSERTIndex(N, 128);
4135 bool X86::isVINSERT256Index(SDNode *N) {
4136 return isVINSERTIndex(N, 256);
4139 bool X86::isVEXTRACT128Index(SDNode *N) {
4140 return isVEXTRACTIndex(N, 128);
4143 bool X86::isVEXTRACT256Index(SDNode *N) {
4144 return isVEXTRACTIndex(N, 256);
4147 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4148 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4149 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4150 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4153 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4155 MVT VecVT = N->getOperand(0).getSimpleValueType();
4156 MVT ElVT = VecVT.getVectorElementType();
4158 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4159 return Index / NumElemsPerChunk;
4162 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4163 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4164 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4165 llvm_unreachable("Illegal insert subvector for VINSERT");
4168 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4170 MVT VecVT = N->getSimpleValueType(0);
4171 MVT ElVT = VecVT.getVectorElementType();
4173 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4174 return Index / NumElemsPerChunk;
4177 /// Return the appropriate immediate to extract the specified
4178 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4179 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4180 return getExtractVEXTRACTImmediate(N, 128);
4183 /// Return the appropriate immediate to extract the specified
4184 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4185 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4186 return getExtractVEXTRACTImmediate(N, 256);
4189 /// Return the appropriate immediate to insert at the specified
4190 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4191 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4192 return getInsertVINSERTImmediate(N, 128);
4195 /// Return the appropriate immediate to insert at the specified
4196 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4197 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4198 return getInsertVINSERTImmediate(N, 256);
4201 /// Returns true if Elt is a constant integer zero
4202 static bool isZero(SDValue V) {
4203 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4204 return C && C->isNullValue();
4207 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4208 bool X86::isZeroNode(SDValue Elt) {
4211 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4212 return CFP->getValueAPF().isPosZero();
4216 /// Returns a vector of specified type with all zero elements.
4217 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4218 SelectionDAG &DAG, SDLoc dl) {
4219 assert(VT.isVector() && "Expected a vector type");
4221 // Always build SSE zero vectors as <4 x i32> bitcasted
4222 // to their dest type. This ensures they get CSE'd.
4224 if (VT.is128BitVector()) { // SSE
4225 if (Subtarget->hasSSE2()) { // SSE2
4226 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4227 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4229 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4230 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4232 } else if (VT.is256BitVector()) { // AVX
4233 if (Subtarget->hasInt256()) { // AVX2
4234 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4235 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4236 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4238 // 256-bit logic and arithmetic instructions in AVX are all
4239 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4240 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4241 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4242 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4244 } else if (VT.is512BitVector()) { // AVX-512
4245 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4246 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4247 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4248 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4249 } else if (VT.getScalarType() == MVT::i1) {
4251 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4252 && "Unexpected vector type");
4253 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4254 && "Unexpected vector type");
4255 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4256 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4257 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4259 llvm_unreachable("Unexpected vector type");
4261 return DAG.getBitcast(VT, Vec);
4264 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4265 SelectionDAG &DAG, SDLoc dl,
4266 unsigned vectorWidth) {
4267 assert((vectorWidth == 128 || vectorWidth == 256) &&
4268 "Unsupported vector width");
4269 EVT VT = Vec.getValueType();
4270 EVT ElVT = VT.getVectorElementType();
4271 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4272 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4273 VT.getVectorNumElements()/Factor);
4275 // Extract from UNDEF is UNDEF.
4276 if (Vec.getOpcode() == ISD::UNDEF)
4277 return DAG.getUNDEF(ResultVT);
4279 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4280 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4282 // This is the index of the first element of the vectorWidth-bit chunk
4284 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4287 // If the input is a buildvector just emit a smaller one.
4288 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4289 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4290 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4293 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4294 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4297 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4298 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4299 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4300 /// instructions or a simple subregister reference. Idx is an index in the
4301 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4302 /// lowering EXTRACT_VECTOR_ELT operations easier.
4303 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4304 SelectionDAG &DAG, SDLoc dl) {
4305 assert((Vec.getValueType().is256BitVector() ||
4306 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4307 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4310 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4311 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4312 SelectionDAG &DAG, SDLoc dl) {
4313 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4314 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4317 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4318 unsigned IdxVal, SelectionDAG &DAG,
4319 SDLoc dl, unsigned vectorWidth) {
4320 assert((vectorWidth == 128 || vectorWidth == 256) &&
4321 "Unsupported vector width");
4322 // Inserting UNDEF is Result
4323 if (Vec.getOpcode() == ISD::UNDEF)
4325 EVT VT = Vec.getValueType();
4326 EVT ElVT = VT.getVectorElementType();
4327 EVT ResultVT = Result.getValueType();
4329 // Insert the relevant vectorWidth bits.
4330 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4332 // This is the index of the first element of the vectorWidth-bit chunk
4334 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4337 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4338 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4341 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4342 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4343 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4344 /// simple superregister reference. Idx is an index in the 128 bits
4345 /// we want. It need not be aligned to a 128-bit boundary. That makes
4346 /// lowering INSERT_VECTOR_ELT operations easier.
4347 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4348 SelectionDAG &DAG, SDLoc dl) {
4349 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4351 // For insertion into the zero index (low half) of a 256-bit vector, it is
4352 // more efficient to generate a blend with immediate instead of an insert*128.
4353 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4354 // extend the subvector to the size of the result vector. Make sure that
4355 // we are not recursing on that node by checking for undef here.
4356 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4357 Result.getOpcode() != ISD::UNDEF) {
4358 EVT ResultVT = Result.getValueType();
4359 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4360 SDValue Undef = DAG.getUNDEF(ResultVT);
4361 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4364 // The blend instruction, and therefore its mask, depend on the data type.
4365 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4366 if (ScalarType.isFloatingPoint()) {
4367 // Choose either vblendps (float) or vblendpd (double).
4368 unsigned ScalarSize = ScalarType.getSizeInBits();
4369 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4370 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4371 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4372 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4375 const X86Subtarget &Subtarget =
4376 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4378 // AVX2 is needed for 256-bit integer blend support.
4379 // Integers must be cast to 32-bit because there is only vpblendd;
4380 // vpblendw can't be used for this because it has a handicapped mask.
4382 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4383 // is still more efficient than using the wrong domain vinsertf128 that
4384 // will be created by InsertSubVector().
4385 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4387 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4388 Vec256 = DAG.getBitcast(CastVT, Vec256);
4389 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4390 return DAG.getBitcast(ResultVT, Vec256);
4393 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4396 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4397 SelectionDAG &DAG, SDLoc dl) {
4398 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4399 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4402 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4403 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4404 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4405 /// large BUILD_VECTORS.
4406 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4407 unsigned NumElems, SelectionDAG &DAG,
4409 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4410 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4413 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4414 unsigned NumElems, SelectionDAG &DAG,
4416 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4417 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4420 /// Returns a vector of specified type with all bits set.
4421 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4422 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4423 /// Then bitcast to their original type, ensuring they get CSE'd.
4424 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4425 SelectionDAG &DAG, SDLoc dl) {
4426 assert(VT.isVector() && "Expected a vector type");
4428 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4430 if (VT.is512BitVector()) {
4431 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4432 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4433 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4434 } else if (VT.is256BitVector()) {
4435 if (Subtarget->hasInt256()) { // AVX2
4436 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4437 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4439 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4440 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4442 } else if (VT.is128BitVector()) {
4443 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4445 llvm_unreachable("Unexpected vector type");
4447 return DAG.getBitcast(VT, Vec);
4450 /// Returns a vector_shuffle node for an unpackl operation.
4451 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4453 unsigned NumElems = VT.getVectorNumElements();
4454 SmallVector<int, 8> Mask;
4455 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4457 Mask.push_back(i + NumElems);
4459 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4462 /// Returns a vector_shuffle node for an unpackh operation.
4463 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4465 unsigned NumElems = VT.getVectorNumElements();
4466 SmallVector<int, 8> Mask;
4467 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4468 Mask.push_back(i + Half);
4469 Mask.push_back(i + NumElems + Half);
4471 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4474 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4475 /// This produces a shuffle where the low element of V2 is swizzled into the
4476 /// zero/undef vector, landing at element Idx.
4477 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4478 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4480 const X86Subtarget *Subtarget,
4481 SelectionDAG &DAG) {
4482 MVT VT = V2.getSimpleValueType();
4484 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4485 unsigned NumElems = VT.getVectorNumElements();
4486 SmallVector<int, 16> MaskVec;
4487 for (unsigned i = 0; i != NumElems; ++i)
4488 // If this is the insertion idx, put the low elt of V2 here.
4489 MaskVec.push_back(i == Idx ? NumElems : i);
4490 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4493 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4494 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4495 /// uses one source. Note that this will set IsUnary for shuffles which use a
4496 /// single input multiple times, and in those cases it will
4497 /// adjust the mask to only have indices within that single input.
4498 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4499 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4500 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4501 unsigned NumElems = VT.getVectorNumElements();
4505 bool IsFakeUnary = false;
4506 switch(N->getOpcode()) {
4507 case X86ISD::BLENDI:
4508 ImmN = N->getOperand(N->getNumOperands()-1);
4509 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4512 ImmN = N->getOperand(N->getNumOperands()-1);
4513 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4514 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4516 case X86ISD::UNPCKH:
4517 DecodeUNPCKHMask(VT, Mask);
4518 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4520 case X86ISD::UNPCKL:
4521 DecodeUNPCKLMask(VT, Mask);
4522 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4524 case X86ISD::MOVHLPS:
4525 DecodeMOVHLPSMask(NumElems, Mask);
4526 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4528 case X86ISD::MOVLHPS:
4529 DecodeMOVLHPSMask(NumElems, Mask);
4530 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4532 case X86ISD::PALIGNR:
4533 ImmN = N->getOperand(N->getNumOperands()-1);
4534 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4536 case X86ISD::PSHUFD:
4537 case X86ISD::VPERMILPI:
4538 ImmN = N->getOperand(N->getNumOperands()-1);
4539 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4542 case X86ISD::PSHUFHW:
4543 ImmN = N->getOperand(N->getNumOperands()-1);
4544 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4547 case X86ISD::PSHUFLW:
4548 ImmN = N->getOperand(N->getNumOperands()-1);
4549 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4552 case X86ISD::PSHUFB: {
4554 SDValue MaskNode = N->getOperand(1);
4555 while (MaskNode->getOpcode() == ISD::BITCAST)
4556 MaskNode = MaskNode->getOperand(0);
4558 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4559 // If we have a build-vector, then things are easy.
4560 EVT VT = MaskNode.getValueType();
4561 assert(VT.isVector() &&
4562 "Can't produce a non-vector with a build_vector!");
4563 if (!VT.isInteger())
4566 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4568 SmallVector<uint64_t, 32> RawMask;
4569 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4570 SDValue Op = MaskNode->getOperand(i);
4571 if (Op->getOpcode() == ISD::UNDEF) {
4572 RawMask.push_back((uint64_t)SM_SentinelUndef);
4575 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4578 APInt MaskElement = CN->getAPIntValue();
4580 // We now have to decode the element which could be any integer size and
4581 // extract each byte of it.
4582 for (int j = 0; j < NumBytesPerElement; ++j) {
4583 // Note that this is x86 and so always little endian: the low byte is
4584 // the first byte of the mask.
4585 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4586 MaskElement = MaskElement.lshr(8);
4589 DecodePSHUFBMask(RawMask, Mask);
4593 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4597 SDValue Ptr = MaskLoad->getBasePtr();
4598 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4599 Ptr->getOpcode() == X86ISD::WrapperRIP)
4600 Ptr = Ptr->getOperand(0);
4602 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4603 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4606 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4607 DecodePSHUFBMask(C, Mask);
4615 case X86ISD::VPERMI:
4616 ImmN = N->getOperand(N->getNumOperands()-1);
4617 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4622 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4624 case X86ISD::VPERM2X128:
4625 ImmN = N->getOperand(N->getNumOperands()-1);
4626 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4627 if (Mask.empty()) return false;
4628 // Mask only contains negative index if an element is zero.
4629 if (std::any_of(Mask.begin(), Mask.end(),
4630 [](int M){ return M == SM_SentinelZero; }))
4633 case X86ISD::MOVSLDUP:
4634 DecodeMOVSLDUPMask(VT, Mask);
4637 case X86ISD::MOVSHDUP:
4638 DecodeMOVSHDUPMask(VT, Mask);
4641 case X86ISD::MOVDDUP:
4642 DecodeMOVDDUPMask(VT, Mask);
4645 case X86ISD::MOVLHPD:
4646 case X86ISD::MOVLPD:
4647 case X86ISD::MOVLPS:
4648 // Not yet implemented
4650 case X86ISD::VPERMV: {
4652 SDValue MaskNode = N->getOperand(0);
4653 while (MaskNode->getOpcode() == ISD::BITCAST)
4654 MaskNode = MaskNode->getOperand(0);
4656 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4657 SmallVector<uint64_t, 32> RawMask;
4658 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4659 // If we have a build-vector, then things are easy.
4660 assert(MaskNode.getValueType().isInteger() &&
4661 MaskNode.getValueType().getVectorNumElements() ==
4662 VT.getVectorNumElements());
4664 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4665 SDValue Op = MaskNode->getOperand(i);
4666 if (Op->getOpcode() == ISD::UNDEF)
4667 RawMask.push_back((uint64_t)SM_SentinelUndef);
4668 else if (isa<ConstantSDNode>(Op)) {
4669 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4670 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4674 DecodeVPERMVMask(RawMask, Mask);
4677 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4678 unsigned NumEltsInMask = MaskNode->getNumOperands();
4679 MaskNode = MaskNode->getOperand(0);
4680 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4682 APInt MaskEltValue = CN->getAPIntValue();
4683 for (unsigned i = 0; i < NumEltsInMask; ++i)
4684 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4685 DecodeVPERMVMask(RawMask, Mask);
4688 // It may be a scalar load
4691 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4695 SDValue Ptr = MaskLoad->getBasePtr();
4696 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4697 Ptr->getOpcode() == X86ISD::WrapperRIP)
4698 Ptr = Ptr->getOperand(0);
4700 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4701 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4704 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4706 DecodeVPERMVMask(C, VT, Mask);
4713 case X86ISD::VPERMV3: {
4715 SDValue MaskNode = N->getOperand(1);
4716 while (MaskNode->getOpcode() == ISD::BITCAST)
4717 MaskNode = MaskNode->getOperand(1);
4719 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4720 // If we have a build-vector, then things are easy.
4721 assert(MaskNode.getValueType().isInteger() &&
4722 MaskNode.getValueType().getVectorNumElements() ==
4723 VT.getVectorNumElements());
4725 SmallVector<uint64_t, 32> RawMask;
4726 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4728 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4729 SDValue Op = MaskNode->getOperand(i);
4730 if (Op->getOpcode() == ISD::UNDEF)
4731 RawMask.push_back((uint64_t)SM_SentinelUndef);
4733 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4736 APInt MaskElement = CN->getAPIntValue();
4737 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4740 DecodeVPERMV3Mask(RawMask, Mask);
4744 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4748 SDValue Ptr = MaskLoad->getBasePtr();
4749 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4750 Ptr->getOpcode() == X86ISD::WrapperRIP)
4751 Ptr = Ptr->getOperand(0);
4753 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4754 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4757 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4759 DecodeVPERMV3Mask(C, VT, Mask);
4766 default: llvm_unreachable("unknown target shuffle node");
4769 // If we have a fake unary shuffle, the shuffle mask is spread across two
4770 // inputs that are actually the same node. Re-map the mask to always point
4771 // into the first input.
4774 if (M >= (int)Mask.size())
4780 /// Returns the scalar element that will make up the ith
4781 /// element of the result of the vector shuffle.
4782 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4785 return SDValue(); // Limit search depth.
4787 SDValue V = SDValue(N, 0);
4788 EVT VT = V.getValueType();
4789 unsigned Opcode = V.getOpcode();
4791 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4792 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4793 int Elt = SV->getMaskElt(Index);
4796 return DAG.getUNDEF(VT.getVectorElementType());
4798 unsigned NumElems = VT.getVectorNumElements();
4799 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4800 : SV->getOperand(1);
4801 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4804 // Recurse into target specific vector shuffles to find scalars.
4805 if (isTargetShuffle(Opcode)) {
4806 MVT ShufVT = V.getSimpleValueType();
4807 unsigned NumElems = ShufVT.getVectorNumElements();
4808 SmallVector<int, 16> ShuffleMask;
4811 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4814 int Elt = ShuffleMask[Index];
4816 return DAG.getUNDEF(ShufVT.getVectorElementType());
4818 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4820 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4824 // Actual nodes that may contain scalar elements
4825 if (Opcode == ISD::BITCAST) {
4826 V = V.getOperand(0);
4827 EVT SrcVT = V.getValueType();
4828 unsigned NumElems = VT.getVectorNumElements();
4830 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4834 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4835 return (Index == 0) ? V.getOperand(0)
4836 : DAG.getUNDEF(VT.getVectorElementType());
4838 if (V.getOpcode() == ISD::BUILD_VECTOR)
4839 return V.getOperand(Index);
4844 /// Custom lower build_vector of v16i8.
4845 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4846 unsigned NumNonZero, unsigned NumZero,
4848 const X86Subtarget* Subtarget,
4849 const TargetLowering &TLI) {
4857 // SSE4.1 - use PINSRB to insert each byte directly.
4858 if (Subtarget->hasSSE41()) {
4859 for (unsigned i = 0; i < 16; ++i) {
4860 bool isNonZero = (NonZeros & (1 << i)) != 0;
4864 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4866 V = DAG.getUNDEF(MVT::v16i8);
4869 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4870 MVT::v16i8, V, Op.getOperand(i),
4871 DAG.getIntPtrConstant(i, dl));
4878 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4879 for (unsigned i = 0; i < 16; ++i) {
4880 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4881 if (ThisIsNonZero && First) {
4883 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4885 V = DAG.getUNDEF(MVT::v8i16);
4890 SDValue ThisElt, LastElt;
4891 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4892 if (LastIsNonZero) {
4893 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4894 MVT::i16, Op.getOperand(i-1));
4896 if (ThisIsNonZero) {
4897 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4898 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4899 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4901 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4905 if (ThisElt.getNode())
4906 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4907 DAG.getIntPtrConstant(i/2, dl));
4911 return DAG.getBitcast(MVT::v16i8, V);
4914 /// Custom lower build_vector of v8i16.
4915 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4916 unsigned NumNonZero, unsigned NumZero,
4918 const X86Subtarget* Subtarget,
4919 const TargetLowering &TLI) {
4926 for (unsigned i = 0; i < 8; ++i) {
4927 bool isNonZero = (NonZeros & (1 << i)) != 0;
4931 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4933 V = DAG.getUNDEF(MVT::v8i16);
4936 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4937 MVT::v8i16, V, Op.getOperand(i),
4938 DAG.getIntPtrConstant(i, dl));
4945 /// Custom lower build_vector of v4i32 or v4f32.
4946 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4947 const X86Subtarget *Subtarget,
4948 const TargetLowering &TLI) {
4949 // Find all zeroable elements.
4950 std::bitset<4> Zeroable;
4951 for (int i=0; i < 4; ++i) {
4952 SDValue Elt = Op->getOperand(i);
4953 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4955 assert(Zeroable.size() - Zeroable.count() > 1 &&
4956 "We expect at least two non-zero elements!");
4958 // We only know how to deal with build_vector nodes where elements are either
4959 // zeroable or extract_vector_elt with constant index.
4960 SDValue FirstNonZero;
4961 unsigned FirstNonZeroIdx;
4962 for (unsigned i=0; i < 4; ++i) {
4965 SDValue Elt = Op->getOperand(i);
4966 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4967 !isa<ConstantSDNode>(Elt.getOperand(1)))
4969 // Make sure that this node is extracting from a 128-bit vector.
4970 MVT VT = Elt.getOperand(0).getSimpleValueType();
4971 if (!VT.is128BitVector())
4973 if (!FirstNonZero.getNode()) {
4975 FirstNonZeroIdx = i;
4979 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4980 SDValue V1 = FirstNonZero.getOperand(0);
4981 MVT VT = V1.getSimpleValueType();
4983 // See if this build_vector can be lowered as a blend with zero.
4985 unsigned EltMaskIdx, EltIdx;
4987 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4988 if (Zeroable[EltIdx]) {
4989 // The zero vector will be on the right hand side.
4990 Mask[EltIdx] = EltIdx+4;
4994 Elt = Op->getOperand(EltIdx);
4995 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4996 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4997 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4999 Mask[EltIdx] = EltIdx;
5003 // Let the shuffle legalizer deal with blend operations.
5004 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5005 if (V1.getSimpleValueType() != VT)
5006 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5007 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5010 // See if we can lower this build_vector to a INSERTPS.
5011 if (!Subtarget->hasSSE41())
5014 SDValue V2 = Elt.getOperand(0);
5015 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5018 bool CanFold = true;
5019 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5023 SDValue Current = Op->getOperand(i);
5024 SDValue SrcVector = Current->getOperand(0);
5027 CanFold = SrcVector == V1 &&
5028 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5034 assert(V1.getNode() && "Expected at least two non-zero elements!");
5035 if (V1.getSimpleValueType() != MVT::v4f32)
5036 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5037 if (V2.getSimpleValueType() != MVT::v4f32)
5038 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5040 // Ok, we can emit an INSERTPS instruction.
5041 unsigned ZMask = Zeroable.to_ulong();
5043 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5044 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5046 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5047 DAG.getIntPtrConstant(InsertPSMask, DL));
5048 return DAG.getBitcast(VT, Result);
5051 /// Return a vector logical shift node.
5052 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5053 unsigned NumBits, SelectionDAG &DAG,
5054 const TargetLowering &TLI, SDLoc dl) {
5055 assert(VT.is128BitVector() && "Unknown type for VShift");
5056 MVT ShVT = MVT::v2i64;
5057 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5058 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5059 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5060 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5061 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5062 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5066 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5068 // Check if the scalar load can be widened into a vector load. And if
5069 // the address is "base + cst" see if the cst can be "absorbed" into
5070 // the shuffle mask.
5071 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5072 SDValue Ptr = LD->getBasePtr();
5073 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5075 EVT PVT = LD->getValueType(0);
5076 if (PVT != MVT::i32 && PVT != MVT::f32)
5081 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5082 FI = FINode->getIndex();
5084 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5085 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5086 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5087 Offset = Ptr.getConstantOperandVal(1);
5088 Ptr = Ptr.getOperand(0);
5093 // FIXME: 256-bit vector instructions don't require a strict alignment,
5094 // improve this code to support it better.
5095 unsigned RequiredAlign = VT.getSizeInBits()/8;
5096 SDValue Chain = LD->getChain();
5097 // Make sure the stack object alignment is at least 16 or 32.
5098 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5099 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5100 if (MFI->isFixedObjectIndex(FI)) {
5101 // Can't change the alignment. FIXME: It's possible to compute
5102 // the exact stack offset and reference FI + adjust offset instead.
5103 // If someone *really* cares about this. That's the way to implement it.
5106 MFI->setObjectAlignment(FI, RequiredAlign);
5110 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5111 // Ptr + (Offset & ~15).
5114 if ((Offset % RequiredAlign) & 3)
5116 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5119 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5120 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5123 int EltNo = (Offset - StartOffset) >> 2;
5124 unsigned NumElems = VT.getVectorNumElements();
5126 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5127 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5128 LD->getPointerInfo().getWithOffset(StartOffset),
5129 false, false, false, 0);
5131 SmallVector<int, 8> Mask(NumElems, EltNo);
5133 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5139 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5140 /// elements can be replaced by a single large load which has the same value as
5141 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5143 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5145 /// FIXME: we'd also like to handle the case where the last elements are zero
5146 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5147 /// There's even a handy isZeroNode for that purpose.
5148 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5149 SDLoc &DL, SelectionDAG &DAG,
5150 bool isAfterLegalize) {
5151 unsigned NumElems = Elts.size();
5153 LoadSDNode *LDBase = nullptr;
5154 unsigned LastLoadedElt = -1U;
5156 // For each element in the initializer, see if we've found a load or an undef.
5157 // If we don't find an initial load element, or later load elements are
5158 // non-consecutive, bail out.
5159 for (unsigned i = 0; i < NumElems; ++i) {
5160 SDValue Elt = Elts[i];
5161 // Look through a bitcast.
5162 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5163 Elt = Elt.getOperand(0);
5164 if (!Elt.getNode() ||
5165 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5168 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5170 LDBase = cast<LoadSDNode>(Elt.getNode());
5174 if (Elt.getOpcode() == ISD::UNDEF)
5177 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5178 EVT LdVT = Elt.getValueType();
5179 // Each loaded element must be the correct fractional portion of the
5180 // requested vector load.
5181 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5183 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5188 // If we have found an entire vector of loads and undefs, then return a large
5189 // load of the entire vector width starting at the base pointer. If we found
5190 // consecutive loads for the low half, generate a vzext_load node.
5191 if (LastLoadedElt == NumElems - 1) {
5192 assert(LDBase && "Did not find base load for merging consecutive loads");
5193 EVT EltVT = LDBase->getValueType(0);
5194 // Ensure that the input vector size for the merged loads matches the
5195 // cumulative size of the input elements.
5196 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5199 if (isAfterLegalize &&
5200 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5203 SDValue NewLd = SDValue();
5205 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5206 LDBase->getPointerInfo(), LDBase->isVolatile(),
5207 LDBase->isNonTemporal(), LDBase->isInvariant(),
5208 LDBase->getAlignment());
5210 if (LDBase->hasAnyUseOfValue(1)) {
5211 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5213 SDValue(NewLd.getNode(), 1));
5214 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5215 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5216 SDValue(NewLd.getNode(), 1));
5222 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5223 //of a v4i32 / v4f32. It's probably worth generalizing.
5224 EVT EltVT = VT.getVectorElementType();
5225 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5226 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5227 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5228 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5230 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5231 LDBase->getPointerInfo(),
5232 LDBase->getAlignment(),
5233 false/*isVolatile*/, true/*ReadMem*/,
5236 // Make sure the newly-created LOAD is in the same position as LDBase in
5237 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5238 // update uses of LDBase's output chain to use the TokenFactor.
5239 if (LDBase->hasAnyUseOfValue(1)) {
5240 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5241 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5242 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5243 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5244 SDValue(ResNode.getNode(), 1));
5247 return DAG.getBitcast(VT, ResNode);
5252 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5253 /// to generate a splat value for the following cases:
5254 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5255 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5256 /// a scalar load, or a constant.
5257 /// The VBROADCAST node is returned when a pattern is found,
5258 /// or SDValue() otherwise.
5259 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5260 SelectionDAG &DAG) {
5261 // VBROADCAST requires AVX.
5262 // TODO: Splats could be generated for non-AVX CPUs using SSE
5263 // instructions, but there's less potential gain for only 128-bit vectors.
5264 if (!Subtarget->hasAVX())
5267 MVT VT = Op.getSimpleValueType();
5270 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5271 "Unsupported vector type for broadcast.");
5276 switch (Op.getOpcode()) {
5278 // Unknown pattern found.
5281 case ISD::BUILD_VECTOR: {
5282 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5283 BitVector UndefElements;
5284 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5286 // We need a splat of a single value to use broadcast, and it doesn't
5287 // make any sense if the value is only in one element of the vector.
5288 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5292 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5293 Ld.getOpcode() == ISD::ConstantFP);
5295 // Make sure that all of the users of a non-constant load are from the
5296 // BUILD_VECTOR node.
5297 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5302 case ISD::VECTOR_SHUFFLE: {
5303 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5305 // Shuffles must have a splat mask where the first element is
5307 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5310 SDValue Sc = Op.getOperand(0);
5311 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5312 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5314 if (!Subtarget->hasInt256())
5317 // Use the register form of the broadcast instruction available on AVX2.
5318 if (VT.getSizeInBits() >= 256)
5319 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5320 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5323 Ld = Sc.getOperand(0);
5324 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5325 Ld.getOpcode() == ISD::ConstantFP);
5327 // The scalar_to_vector node and the suspected
5328 // load node must have exactly one user.
5329 // Constants may have multiple users.
5331 // AVX-512 has register version of the broadcast
5332 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5333 Ld.getValueType().getSizeInBits() >= 32;
5334 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5341 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5342 bool IsGE256 = (VT.getSizeInBits() >= 256);
5344 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5345 // instruction to save 8 or more bytes of constant pool data.
5346 // TODO: If multiple splats are generated to load the same constant,
5347 // it may be detrimental to overall size. There needs to be a way to detect
5348 // that condition to know if this is truly a size win.
5349 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5351 // Handle broadcasting a single constant scalar from the constant pool
5353 // On Sandybridge (no AVX2), it is still better to load a constant vector
5354 // from the constant pool and not to broadcast it from a scalar.
5355 // But override that restriction when optimizing for size.
5356 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5357 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5358 EVT CVT = Ld.getValueType();
5359 assert(!CVT.isVector() && "Must not broadcast a vector type");
5361 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5362 // For size optimization, also splat v2f64 and v2i64, and for size opt
5363 // with AVX2, also splat i8 and i16.
5364 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5365 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5366 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5367 const Constant *C = nullptr;
5368 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5369 C = CI->getConstantIntValue();
5370 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5371 C = CF->getConstantFPValue();
5373 assert(C && "Invalid constant type");
5375 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5377 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5378 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5380 CVT, dl, DAG.getEntryNode(), CP,
5381 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5382 false, false, Alignment);
5384 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5388 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5390 // Handle AVX2 in-register broadcasts.
5391 if (!IsLoad && Subtarget->hasInt256() &&
5392 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5393 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5395 // The scalar source must be a normal load.
5399 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5400 (Subtarget->hasVLX() && ScalarSize == 64))
5401 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5403 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5404 // double since there is no vbroadcastsd xmm
5405 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5406 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5407 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5410 // Unsupported broadcast.
5414 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5415 /// underlying vector and index.
5417 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5419 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5421 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5422 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5425 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5427 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5429 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5430 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5433 // In this case the vector is the extract_subvector expression and the index
5434 // is 2, as specified by the shuffle.
5435 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5436 SDValue ShuffleVec = SVOp->getOperand(0);
5437 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5438 assert(ShuffleVecVT.getVectorElementType() ==
5439 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5441 int ShuffleIdx = SVOp->getMaskElt(Idx);
5442 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5443 ExtractedFromVec = ShuffleVec;
5449 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5450 MVT VT = Op.getSimpleValueType();
5452 // Skip if insert_vec_elt is not supported.
5453 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5454 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5458 unsigned NumElems = Op.getNumOperands();
5462 SmallVector<unsigned, 4> InsertIndices;
5463 SmallVector<int, 8> Mask(NumElems, -1);
5465 for (unsigned i = 0; i != NumElems; ++i) {
5466 unsigned Opc = Op.getOperand(i).getOpcode();
5468 if (Opc == ISD::UNDEF)
5471 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5472 // Quit if more than 1 elements need inserting.
5473 if (InsertIndices.size() > 1)
5476 InsertIndices.push_back(i);
5480 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5481 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5482 // Quit if non-constant index.
5483 if (!isa<ConstantSDNode>(ExtIdx))
5485 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5487 // Quit if extracted from vector of different type.
5488 if (ExtractedFromVec.getValueType() != VT)
5491 if (!VecIn1.getNode())
5492 VecIn1 = ExtractedFromVec;
5493 else if (VecIn1 != ExtractedFromVec) {
5494 if (!VecIn2.getNode())
5495 VecIn2 = ExtractedFromVec;
5496 else if (VecIn2 != ExtractedFromVec)
5497 // Quit if more than 2 vectors to shuffle
5501 if (ExtractedFromVec == VecIn1)
5503 else if (ExtractedFromVec == VecIn2)
5504 Mask[i] = Idx + NumElems;
5507 if (!VecIn1.getNode())
5510 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5511 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5512 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5513 unsigned Idx = InsertIndices[i];
5514 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5515 DAG.getIntPtrConstant(Idx, DL));
5521 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5522 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5523 Op.getScalarValueSizeInBits() == 1 &&
5524 "Can not convert non-constant vector");
5525 uint64_t Immediate = 0;
5526 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5527 SDValue In = Op.getOperand(idx);
5528 if (In.getOpcode() != ISD::UNDEF)
5529 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5533 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5534 return DAG.getConstant(Immediate, dl, VT);
5536 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5538 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5540 MVT VT = Op.getSimpleValueType();
5541 assert((VT.getVectorElementType() == MVT::i1) &&
5542 "Unexpected type in LowerBUILD_VECTORvXi1!");
5545 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5546 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5547 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5548 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5551 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5552 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5553 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5554 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5557 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5558 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5559 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5560 return DAG.getBitcast(VT, Imm);
5561 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5562 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5563 DAG.getIntPtrConstant(0, dl));
5566 // Vector has one or more non-const elements
5567 uint64_t Immediate = 0;
5568 SmallVector<unsigned, 16> NonConstIdx;
5569 bool IsSplat = true;
5570 bool HasConstElts = false;
5572 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5573 SDValue In = Op.getOperand(idx);
5574 if (In.getOpcode() == ISD::UNDEF)
5576 if (!isa<ConstantSDNode>(In))
5577 NonConstIdx.push_back(idx);
5579 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5580 HasConstElts = true;
5584 else if (In != Op.getOperand(SplatIdx))
5588 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5590 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5591 DAG.getConstant(1, dl, VT),
5592 DAG.getConstant(0, dl, VT));
5594 // insert elements one by one
5598 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5599 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5601 else if (HasConstElts)
5602 Imm = DAG.getConstant(0, dl, VT);
5604 Imm = DAG.getUNDEF(VT);
5605 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5606 DstVec = DAG.getBitcast(VT, Imm);
5608 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5609 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5610 DAG.getIntPtrConstant(0, dl));
5613 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5614 unsigned InsertIdx = NonConstIdx[i];
5615 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5616 Op.getOperand(InsertIdx),
5617 DAG.getIntPtrConstant(InsertIdx, dl));
5622 /// \brief Return true if \p N implements a horizontal binop and return the
5623 /// operands for the horizontal binop into V0 and V1.
5625 /// This is a helper function of LowerToHorizontalOp().
5626 /// This function checks that the build_vector \p N in input implements a
5627 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5628 /// operation to match.
5629 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5630 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5631 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5634 /// This function only analyzes elements of \p N whose indices are
5635 /// in range [BaseIdx, LastIdx).
5636 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5638 unsigned BaseIdx, unsigned LastIdx,
5639 SDValue &V0, SDValue &V1) {
5640 EVT VT = N->getValueType(0);
5642 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5643 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5644 "Invalid Vector in input!");
5646 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5647 bool CanFold = true;
5648 unsigned ExpectedVExtractIdx = BaseIdx;
5649 unsigned NumElts = LastIdx - BaseIdx;
5650 V0 = DAG.getUNDEF(VT);
5651 V1 = DAG.getUNDEF(VT);
5653 // Check if N implements a horizontal binop.
5654 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5655 SDValue Op = N->getOperand(i + BaseIdx);
5658 if (Op->getOpcode() == ISD::UNDEF) {
5659 // Update the expected vector extract index.
5660 if (i * 2 == NumElts)
5661 ExpectedVExtractIdx = BaseIdx;
5662 ExpectedVExtractIdx += 2;
5666 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5671 SDValue Op0 = Op.getOperand(0);
5672 SDValue Op1 = Op.getOperand(1);
5674 // Try to match the following pattern:
5675 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5676 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5677 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5678 Op0.getOperand(0) == Op1.getOperand(0) &&
5679 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5680 isa<ConstantSDNode>(Op1.getOperand(1)));
5684 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5685 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5687 if (i * 2 < NumElts) {
5688 if (V0.getOpcode() == ISD::UNDEF) {
5689 V0 = Op0.getOperand(0);
5690 if (V0.getValueType() != VT)
5694 if (V1.getOpcode() == ISD::UNDEF) {
5695 V1 = Op0.getOperand(0);
5696 if (V1.getValueType() != VT)
5699 if (i * 2 == NumElts)
5700 ExpectedVExtractIdx = BaseIdx;
5703 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5704 if (I0 == ExpectedVExtractIdx)
5705 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5706 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5707 // Try to match the following dag sequence:
5708 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5709 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5713 ExpectedVExtractIdx += 2;
5719 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5720 /// a concat_vector.
5722 /// This is a helper function of LowerToHorizontalOp().
5723 /// This function expects two 256-bit vectors called V0 and V1.
5724 /// At first, each vector is split into two separate 128-bit vectors.
5725 /// Then, the resulting 128-bit vectors are used to implement two
5726 /// horizontal binary operations.
5728 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5730 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5731 /// the two new horizontal binop.
5732 /// When Mode is set, the first horizontal binop dag node would take as input
5733 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5734 /// horizontal binop dag node would take as input the lower 128-bit of V1
5735 /// and the upper 128-bit of V1.
5737 /// HADD V0_LO, V0_HI
5738 /// HADD V1_LO, V1_HI
5740 /// Otherwise, the first horizontal binop dag node takes as input the lower
5741 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5742 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5744 /// HADD V0_LO, V1_LO
5745 /// HADD V0_HI, V1_HI
5747 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5748 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5749 /// the upper 128-bits of the result.
5750 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5751 SDLoc DL, SelectionDAG &DAG,
5752 unsigned X86Opcode, bool Mode,
5753 bool isUndefLO, bool isUndefHI) {
5754 EVT VT = V0.getValueType();
5755 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5756 "Invalid nodes in input!");
5758 unsigned NumElts = VT.getVectorNumElements();
5759 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5760 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5761 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5762 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5763 EVT NewVT = V0_LO.getValueType();
5765 SDValue LO = DAG.getUNDEF(NewVT);
5766 SDValue HI = DAG.getUNDEF(NewVT);
5769 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5770 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5771 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5772 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5773 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5775 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5776 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5777 V1_LO->getOpcode() != ISD::UNDEF))
5778 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5780 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5781 V1_HI->getOpcode() != ISD::UNDEF))
5782 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5785 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5788 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5790 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5791 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5792 EVT VT = BV->getValueType(0);
5793 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5794 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5798 unsigned NumElts = VT.getVectorNumElements();
5799 SDValue InVec0 = DAG.getUNDEF(VT);
5800 SDValue InVec1 = DAG.getUNDEF(VT);
5802 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5803 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5805 // Odd-numbered elements in the input build vector are obtained from
5806 // adding two integer/float elements.
5807 // Even-numbered elements in the input build vector are obtained from
5808 // subtracting two integer/float elements.
5809 unsigned ExpectedOpcode = ISD::FSUB;
5810 unsigned NextExpectedOpcode = ISD::FADD;
5811 bool AddFound = false;
5812 bool SubFound = false;
5814 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5815 SDValue Op = BV->getOperand(i);
5817 // Skip 'undef' values.
5818 unsigned Opcode = Op.getOpcode();
5819 if (Opcode == ISD::UNDEF) {
5820 std::swap(ExpectedOpcode, NextExpectedOpcode);
5824 // Early exit if we found an unexpected opcode.
5825 if (Opcode != ExpectedOpcode)
5828 SDValue Op0 = Op.getOperand(0);
5829 SDValue Op1 = Op.getOperand(1);
5831 // Try to match the following pattern:
5832 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5833 // Early exit if we cannot match that sequence.
5834 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5835 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5836 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5837 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5838 Op0.getOperand(1) != Op1.getOperand(1))
5841 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5845 // We found a valid add/sub node. Update the information accordingly.
5851 // Update InVec0 and InVec1.
5852 if (InVec0.getOpcode() == ISD::UNDEF) {
5853 InVec0 = Op0.getOperand(0);
5854 if (InVec0.getValueType() != VT)
5857 if (InVec1.getOpcode() == ISD::UNDEF) {
5858 InVec1 = Op1.getOperand(0);
5859 if (InVec1.getValueType() != VT)
5863 // Make sure that operands in input to each add/sub node always
5864 // come from a same pair of vectors.
5865 if (InVec0 != Op0.getOperand(0)) {
5866 if (ExpectedOpcode == ISD::FSUB)
5869 // FADD is commutable. Try to commute the operands
5870 // and then test again.
5871 std::swap(Op0, Op1);
5872 if (InVec0 != Op0.getOperand(0))
5876 if (InVec1 != Op1.getOperand(0))
5879 // Update the pair of expected opcodes.
5880 std::swap(ExpectedOpcode, NextExpectedOpcode);
5883 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5884 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5885 InVec1.getOpcode() != ISD::UNDEF)
5886 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5891 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5892 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5893 const X86Subtarget *Subtarget,
5894 SelectionDAG &DAG) {
5895 EVT VT = BV->getValueType(0);
5896 unsigned NumElts = VT.getVectorNumElements();
5897 unsigned NumUndefsLO = 0;
5898 unsigned NumUndefsHI = 0;
5899 unsigned Half = NumElts/2;
5901 // Count the number of UNDEF operands in the build_vector in input.
5902 for (unsigned i = 0, e = Half; i != e; ++i)
5903 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5906 for (unsigned i = Half, e = NumElts; i != e; ++i)
5907 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5910 // Early exit if this is either a build_vector of all UNDEFs or all the
5911 // operands but one are UNDEF.
5912 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5916 SDValue InVec0, InVec1;
5917 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5918 // Try to match an SSE3 float HADD/HSUB.
5919 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5920 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5922 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5923 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5924 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5925 // Try to match an SSSE3 integer HADD/HSUB.
5926 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5927 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5929 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5930 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5933 if (!Subtarget->hasAVX())
5936 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5937 // Try to match an AVX horizontal add/sub of packed single/double
5938 // precision floating point values from 256-bit vectors.
5939 SDValue InVec2, InVec3;
5940 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5941 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5942 ((InVec0.getOpcode() == ISD::UNDEF ||
5943 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5944 ((InVec1.getOpcode() == ISD::UNDEF ||
5945 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5946 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5948 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5949 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5950 ((InVec0.getOpcode() == ISD::UNDEF ||
5951 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5952 ((InVec1.getOpcode() == ISD::UNDEF ||
5953 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5954 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5955 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5956 // Try to match an AVX2 horizontal add/sub of signed integers.
5957 SDValue InVec2, InVec3;
5959 bool CanFold = true;
5961 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5962 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5963 ((InVec0.getOpcode() == ISD::UNDEF ||
5964 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5965 ((InVec1.getOpcode() == ISD::UNDEF ||
5966 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5967 X86Opcode = X86ISD::HADD;
5968 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5969 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5970 ((InVec0.getOpcode() == ISD::UNDEF ||
5971 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5972 ((InVec1.getOpcode() == ISD::UNDEF ||
5973 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5974 X86Opcode = X86ISD::HSUB;
5979 // Fold this build_vector into a single horizontal add/sub.
5980 // Do this only if the target has AVX2.
5981 if (Subtarget->hasAVX2())
5982 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5984 // Do not try to expand this build_vector into a pair of horizontal
5985 // add/sub if we can emit a pair of scalar add/sub.
5986 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5989 // Convert this build_vector into a pair of horizontal binop followed by
5991 bool isUndefLO = NumUndefsLO == Half;
5992 bool isUndefHI = NumUndefsHI == Half;
5993 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5994 isUndefLO, isUndefHI);
5998 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5999 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6001 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6002 X86Opcode = X86ISD::HADD;
6003 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6004 X86Opcode = X86ISD::HSUB;
6005 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6006 X86Opcode = X86ISD::FHADD;
6007 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6008 X86Opcode = X86ISD::FHSUB;
6012 // Don't try to expand this build_vector into a pair of horizontal add/sub
6013 // if we can simply emit a pair of scalar add/sub.
6014 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6017 // Convert this build_vector into two horizontal add/sub followed by
6019 bool isUndefLO = NumUndefsLO == Half;
6020 bool isUndefHI = NumUndefsHI == Half;
6021 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6022 isUndefLO, isUndefHI);
6029 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6032 MVT VT = Op.getSimpleValueType();
6033 MVT ExtVT = VT.getVectorElementType();
6034 unsigned NumElems = Op.getNumOperands();
6036 // Generate vectors for predicate vectors.
6037 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6038 return LowerBUILD_VECTORvXi1(Op, DAG);
6040 // Vectors containing all zeros can be matched by pxor and xorps later
6041 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6042 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6043 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6044 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6047 return getZeroVector(VT, Subtarget, DAG, dl);
6050 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6051 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6052 // vpcmpeqd on 256-bit vectors.
6053 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6054 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6057 if (!VT.is512BitVector())
6058 return getOnesVector(VT, Subtarget, DAG, dl);
6061 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6062 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6064 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6065 return HorizontalOp;
6066 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6069 unsigned EVTBits = ExtVT.getSizeInBits();
6071 unsigned NumZero = 0;
6072 unsigned NumNonZero = 0;
6073 unsigned NonZeros = 0;
6074 bool IsAllConstants = true;
6075 SmallSet<SDValue, 8> Values;
6076 for (unsigned i = 0; i < NumElems; ++i) {
6077 SDValue Elt = Op.getOperand(i);
6078 if (Elt.getOpcode() == ISD::UNDEF)
6081 if (Elt.getOpcode() != ISD::Constant &&
6082 Elt.getOpcode() != ISD::ConstantFP)
6083 IsAllConstants = false;
6084 if (X86::isZeroNode(Elt))
6087 NonZeros |= (1 << i);
6092 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6093 if (NumNonZero == 0)
6094 return DAG.getUNDEF(VT);
6096 // Special case for single non-zero, non-undef, element.
6097 if (NumNonZero == 1) {
6098 unsigned Idx = countTrailingZeros(NonZeros);
6099 SDValue Item = Op.getOperand(Idx);
6101 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6102 // the value are obviously zero, truncate the value to i32 and do the
6103 // insertion that way. Only do this if the value is non-constant or if the
6104 // value is a constant being inserted into element 0. It is cheaper to do
6105 // a constant pool load than it is to do a movd + shuffle.
6106 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6107 (!IsAllConstants || Idx == 0)) {
6108 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6110 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6111 EVT VecVT = MVT::v4i32;
6113 // Truncate the value (which may itself be a constant) to i32, and
6114 // convert it to a vector with movd (S2V+shuffle to zero extend).
6115 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6116 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6117 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6118 Item, Idx * 2, true, Subtarget, DAG));
6122 // If we have a constant or non-constant insertion into the low element of
6123 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6124 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6125 // depending on what the source datatype is.
6128 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6130 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6131 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6132 if (VT.is512BitVector()) {
6133 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6134 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6135 Item, DAG.getIntPtrConstant(0, dl));
6137 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6138 "Expected an SSE value type!");
6139 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6140 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6141 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6144 // We can't directly insert an i8 or i16 into a vector, so zero extend
6146 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6147 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6148 if (VT.is256BitVector()) {
6149 if (Subtarget->hasAVX()) {
6150 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6151 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6153 // Without AVX, we need to extend to a 128-bit vector and then
6154 // insert into the 256-bit vector.
6155 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6156 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6157 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6160 assert(VT.is128BitVector() && "Expected an SSE value type!");
6161 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6162 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6164 return DAG.getBitcast(VT, Item);
6168 // Is it a vector logical left shift?
6169 if (NumElems == 2 && Idx == 1 &&
6170 X86::isZeroNode(Op.getOperand(0)) &&
6171 !X86::isZeroNode(Op.getOperand(1))) {
6172 unsigned NumBits = VT.getSizeInBits();
6173 return getVShift(true, VT,
6174 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6175 VT, Op.getOperand(1)),
6176 NumBits/2, DAG, *this, dl);
6179 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6182 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6183 // is a non-constant being inserted into an element other than the low one,
6184 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6185 // movd/movss) to move this into the low element, then shuffle it into
6187 if (EVTBits == 32) {
6188 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6189 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6193 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6194 if (Values.size() == 1) {
6195 if (EVTBits == 32) {
6196 // Instead of a shuffle like this:
6197 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6198 // Check if it's possible to issue this instead.
6199 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6200 unsigned Idx = countTrailingZeros(NonZeros);
6201 SDValue Item = Op.getOperand(Idx);
6202 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6203 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6208 // A vector full of immediates; various special cases are already
6209 // handled, so this is best done with a single constant-pool load.
6213 // For AVX-length vectors, see if we can use a vector load to get all of the
6214 // elements, otherwise build the individual 128-bit pieces and use
6215 // shuffles to put them in place.
6216 if (VT.is256BitVector() || VT.is512BitVector()) {
6217 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6219 // Check for a build vector of consecutive loads.
6220 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6223 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6225 // Build both the lower and upper subvector.
6226 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6227 makeArrayRef(&V[0], NumElems/2));
6228 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6229 makeArrayRef(&V[NumElems / 2], NumElems/2));
6231 // Recreate the wider vector with the lower and upper part.
6232 if (VT.is256BitVector())
6233 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6234 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6237 // Let legalizer expand 2-wide build_vectors.
6238 if (EVTBits == 64) {
6239 if (NumNonZero == 1) {
6240 // One half is zero or undef.
6241 unsigned Idx = countTrailingZeros(NonZeros);
6242 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6243 Op.getOperand(Idx));
6244 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6249 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6250 if (EVTBits == 8 && NumElems == 16)
6251 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6255 if (EVTBits == 16 && NumElems == 8)
6256 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6260 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6261 if (EVTBits == 32 && NumElems == 4)
6262 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6265 // If element VT is == 32 bits, turn it into a number of shuffles.
6266 SmallVector<SDValue, 8> V(NumElems);
6267 if (NumElems == 4 && NumZero > 0) {
6268 for (unsigned i = 0; i < 4; ++i) {
6269 bool isZero = !(NonZeros & (1 << i));
6271 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6273 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6276 for (unsigned i = 0; i < 2; ++i) {
6277 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6280 V[i] = V[i*2]; // Must be a zero vector.
6283 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6286 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6289 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6294 bool Reverse1 = (NonZeros & 0x3) == 2;
6295 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6299 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6300 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6302 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6305 if (Values.size() > 1 && VT.is128BitVector()) {
6306 // Check for a build vector of consecutive loads.
6307 for (unsigned i = 0; i < NumElems; ++i)
6308 V[i] = Op.getOperand(i);
6310 // Check for elements which are consecutive loads.
6311 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6314 // Check for a build vector from mostly shuffle plus few inserting.
6315 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6318 // For SSE 4.1, use insertps to put the high elements into the low element.
6319 if (Subtarget->hasSSE41()) {
6321 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6322 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6324 Result = DAG.getUNDEF(VT);
6326 for (unsigned i = 1; i < NumElems; ++i) {
6327 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6328 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6329 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6334 // Otherwise, expand into a number of unpckl*, start by extending each of
6335 // our (non-undef) elements to the full vector width with the element in the
6336 // bottom slot of the vector (which generates no code for SSE).
6337 for (unsigned i = 0; i < NumElems; ++i) {
6338 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6339 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6341 V[i] = DAG.getUNDEF(VT);
6344 // Next, we iteratively mix elements, e.g. for v4f32:
6345 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6346 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6347 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6348 unsigned EltStride = NumElems >> 1;
6349 while (EltStride != 0) {
6350 for (unsigned i = 0; i < EltStride; ++i) {
6351 // If V[i+EltStride] is undef and this is the first round of mixing,
6352 // then it is safe to just drop this shuffle: V[i] is already in the
6353 // right place, the one element (since it's the first round) being
6354 // inserted as undef can be dropped. This isn't safe for successive
6355 // rounds because they will permute elements within both vectors.
6356 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6357 EltStride == NumElems/2)
6360 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6369 // 256-bit AVX can use the vinsertf128 instruction
6370 // to create 256-bit vectors from two other 128-bit ones.
6371 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6373 MVT ResVT = Op.getSimpleValueType();
6375 assert((ResVT.is256BitVector() ||
6376 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6378 SDValue V1 = Op.getOperand(0);
6379 SDValue V2 = Op.getOperand(1);
6380 unsigned NumElems = ResVT.getVectorNumElements();
6381 if (ResVT.is256BitVector())
6382 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6384 if (Op.getNumOperands() == 4) {
6385 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6386 ResVT.getVectorNumElements()/2);
6387 SDValue V3 = Op.getOperand(2);
6388 SDValue V4 = Op.getOperand(3);
6389 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6390 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6392 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6395 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6396 const X86Subtarget *Subtarget,
6397 SelectionDAG & DAG) {
6399 MVT ResVT = Op.getSimpleValueType();
6400 unsigned NumOfOperands = Op.getNumOperands();
6402 assert(isPowerOf2_32(NumOfOperands) &&
6403 "Unexpected number of operands in CONCAT_VECTORS");
6405 if (NumOfOperands > 2) {
6406 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6407 ResVT.getVectorNumElements()/2);
6408 SmallVector<SDValue, 2> Ops;
6409 for (unsigned i = 0; i < NumOfOperands/2; i++)
6410 Ops.push_back(Op.getOperand(i));
6411 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6413 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6414 Ops.push_back(Op.getOperand(i));
6415 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6416 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6419 SDValue V1 = Op.getOperand(0);
6420 SDValue V2 = Op.getOperand(1);
6421 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6422 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6424 if (IsZeroV1 && IsZeroV2)
6425 return getZeroVector(ResVT, Subtarget, DAG, dl);
6427 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6428 SDValue Undef = DAG.getUNDEF(ResVT);
6429 unsigned NumElems = ResVT.getVectorNumElements();
6430 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6432 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6433 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6437 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6438 // Zero the upper bits of V1
6439 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6440 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6443 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6446 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6447 const X86Subtarget *Subtarget,
6448 SelectionDAG &DAG) {
6449 MVT VT = Op.getSimpleValueType();
6450 if (VT.getVectorElementType() == MVT::i1)
6451 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6453 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6454 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6455 Op.getNumOperands() == 4)));
6457 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6458 // from two other 128-bit ones.
6460 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6461 return LowerAVXCONCAT_VECTORS(Op, DAG);
6465 //===----------------------------------------------------------------------===//
6466 // Vector shuffle lowering
6468 // This is an experimental code path for lowering vector shuffles on x86. It is
6469 // designed to handle arbitrary vector shuffles and blends, gracefully
6470 // degrading performance as necessary. It works hard to recognize idiomatic
6471 // shuffles and lower them to optimal instruction patterns without leaving
6472 // a framework that allows reasonably efficient handling of all vector shuffle
6474 //===----------------------------------------------------------------------===//
6476 /// \brief Tiny helper function to identify a no-op mask.
6478 /// This is a somewhat boring predicate function. It checks whether the mask
6479 /// array input, which is assumed to be a single-input shuffle mask of the kind
6480 /// used by the X86 shuffle instructions (not a fully general
6481 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6482 /// in-place shuffle are 'no-op's.
6483 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6484 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6485 if (Mask[i] != -1 && Mask[i] != i)
6490 /// \brief Helper function to classify a mask as a single-input mask.
6492 /// This isn't a generic single-input test because in the vector shuffle
6493 /// lowering we canonicalize single inputs to be the first input operand. This
6494 /// means we can more quickly test for a single input by only checking whether
6495 /// an input from the second operand exists. We also assume that the size of
6496 /// mask corresponds to the size of the input vectors which isn't true in the
6497 /// fully general case.
6498 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6500 if (M >= (int)Mask.size())
6505 /// \brief Test whether there are elements crossing 128-bit lanes in this
6508 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6509 /// and we routinely test for these.
6510 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6511 int LaneSize = 128 / VT.getScalarSizeInBits();
6512 int Size = Mask.size();
6513 for (int i = 0; i < Size; ++i)
6514 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6519 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6521 /// This checks a shuffle mask to see if it is performing the same
6522 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6523 /// that it is also not lane-crossing. It may however involve a blend from the
6524 /// same lane of a second vector.
6526 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6527 /// non-trivial to compute in the face of undef lanes. The representation is
6528 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6529 /// entries from both V1 and V2 inputs to the wider mask.
6531 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6532 SmallVectorImpl<int> &RepeatedMask) {
6533 int LaneSize = 128 / VT.getScalarSizeInBits();
6534 RepeatedMask.resize(LaneSize, -1);
6535 int Size = Mask.size();
6536 for (int i = 0; i < Size; ++i) {
6539 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6540 // This entry crosses lanes, so there is no way to model this shuffle.
6543 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6544 if (RepeatedMask[i % LaneSize] == -1)
6545 // This is the first non-undef entry in this slot of a 128-bit lane.
6546 RepeatedMask[i % LaneSize] =
6547 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6548 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6549 // Found a mismatch with the repeated mask.
6555 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6558 /// This is a fast way to test a shuffle mask against a fixed pattern:
6560 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6562 /// It returns true if the mask is exactly as wide as the argument list, and
6563 /// each element of the mask is either -1 (signifying undef) or the value given
6564 /// in the argument.
6565 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6566 ArrayRef<int> ExpectedMask) {
6567 if (Mask.size() != ExpectedMask.size())
6570 int Size = Mask.size();
6572 // If the values are build vectors, we can look through them to find
6573 // equivalent inputs that make the shuffles equivalent.
6574 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6575 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6577 for (int i = 0; i < Size; ++i)
6578 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6579 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6580 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6581 if (!MaskBV || !ExpectedBV ||
6582 MaskBV->getOperand(Mask[i] % Size) !=
6583 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6590 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6592 /// This helper function produces an 8-bit shuffle immediate corresponding to
6593 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6594 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6597 /// NB: We rely heavily on "undef" masks preserving the input lane.
6598 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6599 SelectionDAG &DAG) {
6600 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6601 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6602 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6603 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6604 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6607 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6608 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6609 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6610 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6611 return DAG.getConstant(Imm, DL, MVT::i8);
6614 /// \brief Compute whether each element of a shuffle is zeroable.
6616 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6617 /// Either it is an undef element in the shuffle mask, the element of the input
6618 /// referenced is undef, or the element of the input referenced is known to be
6619 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6620 /// as many lanes with this technique as possible to simplify the remaining
6622 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6623 SDValue V1, SDValue V2) {
6624 SmallBitVector Zeroable(Mask.size(), false);
6626 while (V1.getOpcode() == ISD::BITCAST)
6627 V1 = V1->getOperand(0);
6628 while (V2.getOpcode() == ISD::BITCAST)
6629 V2 = V2->getOperand(0);
6631 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6632 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6634 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6636 // Handle the easy cases.
6637 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6642 // If this is an index into a build_vector node (which has the same number
6643 // of elements), dig out the input value and use it.
6644 SDValue V = M < Size ? V1 : V2;
6645 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6648 SDValue Input = V.getOperand(M % Size);
6649 // The UNDEF opcode check really should be dead code here, but not quite
6650 // worth asserting on (it isn't invalid, just unexpected).
6651 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6658 // X86 has dedicated unpack instructions that can handle specific blend
6659 // operations: UNPCKH and UNPCKL.
6660 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6661 SDValue V1, SDValue V2,
6662 SelectionDAG &DAG) {
6663 int NumElts = VT.getVectorNumElements();
6666 bool UnpcklSwapped = true;
6667 bool UnpckhSwapped = true;
6668 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6670 for (int i = 0; i < NumElts; ++i) {
6671 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6673 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6674 int HiPos = LoPos + NumEltsInLane / 2;
6675 int LoPosSwapped = (LoPos + NumElts) % (NumElts * 2);
6676 int HiPosSwapped = (HiPos + NumElts) % (NumElts * 2);
6680 if (Mask[i] != LoPos)
6682 if (Mask[i] != HiPos)
6684 if (Mask[i] != LoPosSwapped)
6685 UnpcklSwapped = false;
6686 if (Mask[i] != HiPosSwapped)
6687 UnpckhSwapped = false;
6688 if (!Unpckl && !Unpckh && !UnpcklSwapped && !UnpckhSwapped)
6692 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6694 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6696 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6698 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6700 llvm_unreachable("Unexpected result of UNPCK mask analysis");
6704 /// \brief Try to emit a bitmask instruction for a shuffle.
6706 /// This handles cases where we can model a blend exactly as a bitmask due to
6707 /// one of the inputs being zeroable.
6708 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6709 SDValue V2, ArrayRef<int> Mask,
6710 SelectionDAG &DAG) {
6711 MVT EltVT = VT.getScalarType();
6712 int NumEltBits = EltVT.getSizeInBits();
6713 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6714 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6715 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6717 if (EltVT.isFloatingPoint()) {
6718 Zero = DAG.getBitcast(EltVT, Zero);
6719 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6721 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6722 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6724 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6727 if (Mask[i] % Size != i)
6728 return SDValue(); // Not a blend.
6730 V = Mask[i] < Size ? V1 : V2;
6731 else if (V != (Mask[i] < Size ? V1 : V2))
6732 return SDValue(); // Can only let one input through the mask.
6734 VMaskOps[i] = AllOnes;
6737 return SDValue(); // No non-zeroable elements!
6739 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6740 V = DAG.getNode(VT.isFloatingPoint()
6741 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6746 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6748 /// This is used as a fallback approach when first class blend instructions are
6749 /// unavailable. Currently it is only suitable for integer vectors, but could
6750 /// be generalized for floating point vectors if desirable.
6751 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6752 SDValue V2, ArrayRef<int> Mask,
6753 SelectionDAG &DAG) {
6754 assert(VT.isInteger() && "Only supports integer vector types!");
6755 MVT EltVT = VT.getScalarType();
6756 int NumEltBits = EltVT.getSizeInBits();
6757 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6758 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6760 SmallVector<SDValue, 16> MaskOps;
6761 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6762 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6763 return SDValue(); // Shuffled input!
6764 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6767 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6768 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6769 // We have to cast V2 around.
6770 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6771 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6772 DAG.getBitcast(MaskVT, V1Mask),
6773 DAG.getBitcast(MaskVT, V2)));
6774 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6777 /// \brief Try to emit a blend instruction for a shuffle.
6779 /// This doesn't do any checks for the availability of instructions for blending
6780 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6781 /// be matched in the backend with the type given. What it does check for is
6782 /// that the shuffle mask is in fact a blend.
6783 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6784 SDValue V2, ArrayRef<int> Mask,
6785 const X86Subtarget *Subtarget,
6786 SelectionDAG &DAG) {
6787 unsigned BlendMask = 0;
6788 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6789 if (Mask[i] >= Size) {
6790 if (Mask[i] != i + Size)
6791 return SDValue(); // Shuffled V2 input!
6792 BlendMask |= 1u << i;
6795 if (Mask[i] >= 0 && Mask[i] != i)
6796 return SDValue(); // Shuffled V1 input!
6798 switch (VT.SimpleTy) {
6803 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6804 DAG.getConstant(BlendMask, DL, MVT::i8));
6808 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6812 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6813 // that instruction.
6814 if (Subtarget->hasAVX2()) {
6815 // Scale the blend by the number of 32-bit dwords per element.
6816 int Scale = VT.getScalarSizeInBits() / 32;
6818 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6819 if (Mask[i] >= Size)
6820 for (int j = 0; j < Scale; ++j)
6821 BlendMask |= 1u << (i * Scale + j);
6823 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6824 V1 = DAG.getBitcast(BlendVT, V1);
6825 V2 = DAG.getBitcast(BlendVT, V2);
6826 return DAG.getBitcast(
6827 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6828 DAG.getConstant(BlendMask, DL, MVT::i8)));
6832 // For integer shuffles we need to expand the mask and cast the inputs to
6833 // v8i16s prior to blending.
6834 int Scale = 8 / VT.getVectorNumElements();
6836 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6837 if (Mask[i] >= Size)
6838 for (int j = 0; j < Scale; ++j)
6839 BlendMask |= 1u << (i * Scale + j);
6841 V1 = DAG.getBitcast(MVT::v8i16, V1);
6842 V2 = DAG.getBitcast(MVT::v8i16, V2);
6843 return DAG.getBitcast(VT,
6844 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6845 DAG.getConstant(BlendMask, DL, MVT::i8)));
6849 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6850 SmallVector<int, 8> RepeatedMask;
6851 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6852 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6853 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6855 for (int i = 0; i < 8; ++i)
6856 if (RepeatedMask[i] >= 16)
6857 BlendMask |= 1u << i;
6858 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6859 DAG.getConstant(BlendMask, DL, MVT::i8));
6865 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6866 "256-bit byte-blends require AVX2 support!");
6868 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6869 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6872 // Scale the blend by the number of bytes per element.
6873 int Scale = VT.getScalarSizeInBits() / 8;
6875 // This form of blend is always done on bytes. Compute the byte vector
6877 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6879 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6880 // mix of LLVM's code generator and the x86 backend. We tell the code
6881 // generator that boolean values in the elements of an x86 vector register
6882 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6883 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6884 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6885 // of the element (the remaining are ignored) and 0 in that high bit would
6886 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6887 // the LLVM model for boolean values in vector elements gets the relevant
6888 // bit set, it is set backwards and over constrained relative to x86's
6890 SmallVector<SDValue, 32> VSELECTMask;
6891 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6892 for (int j = 0; j < Scale; ++j)
6893 VSELECTMask.push_back(
6894 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6895 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6898 V1 = DAG.getBitcast(BlendVT, V1);
6899 V2 = DAG.getBitcast(BlendVT, V2);
6900 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6901 DAG.getNode(ISD::BUILD_VECTOR, DL,
6902 BlendVT, VSELECTMask),
6907 llvm_unreachable("Not a supported integer vector type!");
6911 /// \brief Try to lower as a blend of elements from two inputs followed by
6912 /// a single-input permutation.
6914 /// This matches the pattern where we can blend elements from two inputs and
6915 /// then reduce the shuffle to a single-input permutation.
6916 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6919 SelectionDAG &DAG) {
6920 // We build up the blend mask while checking whether a blend is a viable way
6921 // to reduce the shuffle.
6922 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6923 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6925 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6929 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6931 if (BlendMask[Mask[i] % Size] == -1)
6932 BlendMask[Mask[i] % Size] = Mask[i];
6933 else if (BlendMask[Mask[i] % Size] != Mask[i])
6934 return SDValue(); // Can't blend in the needed input!
6936 PermuteMask[i] = Mask[i] % Size;
6939 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6940 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6943 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6944 /// blends and permutes.
6946 /// This matches the extremely common pattern for handling combined
6947 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6948 /// operations. It will try to pick the best arrangement of shuffles and
6950 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6954 SelectionDAG &DAG) {
6955 // Shuffle the input elements into the desired positions in V1 and V2 and
6956 // blend them together.
6957 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6958 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6959 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6960 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6961 if (Mask[i] >= 0 && Mask[i] < Size) {
6962 V1Mask[i] = Mask[i];
6964 } else if (Mask[i] >= Size) {
6965 V2Mask[i] = Mask[i] - Size;
6966 BlendMask[i] = i + Size;
6969 // Try to lower with the simpler initial blend strategy unless one of the
6970 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6971 // shuffle may be able to fold with a load or other benefit. However, when
6972 // we'll have to do 2x as many shuffles in order to achieve this, blending
6973 // first is a better strategy.
6974 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6975 if (SDValue BlendPerm =
6976 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6979 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6980 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6981 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6984 /// \brief Try to lower a vector shuffle as a byte rotation.
6986 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6987 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6988 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6989 /// try to generically lower a vector shuffle through such an pattern. It
6990 /// does not check for the profitability of lowering either as PALIGNR or
6991 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6992 /// This matches shuffle vectors that look like:
6994 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6996 /// Essentially it concatenates V1 and V2, shifts right by some number of
6997 /// elements, and takes the low elements as the result. Note that while this is
6998 /// specified as a *right shift* because x86 is little-endian, it is a *left
6999 /// rotate* of the vector lanes.
7000 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7003 const X86Subtarget *Subtarget,
7004 SelectionDAG &DAG) {
7005 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7007 int NumElts = Mask.size();
7008 int NumLanes = VT.getSizeInBits() / 128;
7009 int NumLaneElts = NumElts / NumLanes;
7011 // We need to detect various ways of spelling a rotation:
7012 // [11, 12, 13, 14, 15, 0, 1, 2]
7013 // [-1, 12, 13, 14, -1, -1, 1, -1]
7014 // [-1, -1, -1, -1, -1, -1, 1, 2]
7015 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7016 // [-1, 4, 5, 6, -1, -1, 9, -1]
7017 // [-1, 4, 5, 6, -1, -1, -1, -1]
7020 for (int l = 0; l < NumElts; l += NumLaneElts) {
7021 for (int i = 0; i < NumLaneElts; ++i) {
7022 if (Mask[l + i] == -1)
7024 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7026 // Get the mod-Size index and lane correct it.
7027 int LaneIdx = (Mask[l + i] % NumElts) - l;
7028 // Make sure it was in this lane.
7029 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7032 // Determine where a rotated vector would have started.
7033 int StartIdx = i - LaneIdx;
7035 // The identity rotation isn't interesting, stop.
7038 // If we found the tail of a vector the rotation must be the missing
7039 // front. If we found the head of a vector, it must be how much of the
7041 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7044 Rotation = CandidateRotation;
7045 else if (Rotation != CandidateRotation)
7046 // The rotations don't match, so we can't match this mask.
7049 // Compute which value this mask is pointing at.
7050 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7052 // Compute which of the two target values this index should be assigned
7053 // to. This reflects whether the high elements are remaining or the low
7054 // elements are remaining.
7055 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7057 // Either set up this value if we've not encountered it before, or check
7058 // that it remains consistent.
7061 else if (TargetV != MaskV)
7062 // This may be a rotation, but it pulls from the inputs in some
7063 // unsupported interleaving.
7068 // Check that we successfully analyzed the mask, and normalize the results.
7069 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7070 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7076 // The actual rotate instruction rotates bytes, so we need to scale the
7077 // rotation based on how many bytes are in the vector lane.
7078 int Scale = 16 / NumLaneElts;
7080 // SSSE3 targets can use the palignr instruction.
7081 if (Subtarget->hasSSSE3()) {
7082 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7083 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7084 Lo = DAG.getBitcast(AlignVT, Lo);
7085 Hi = DAG.getBitcast(AlignVT, Hi);
7087 return DAG.getBitcast(
7088 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7089 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7092 assert(VT.getSizeInBits() == 128 &&
7093 "Rotate-based lowering only supports 128-bit lowering!");
7094 assert(Mask.size() <= 16 &&
7095 "Can shuffle at most 16 bytes in a 128-bit vector!");
7097 // Default SSE2 implementation
7098 int LoByteShift = 16 - Rotation * Scale;
7099 int HiByteShift = Rotation * Scale;
7101 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7102 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7103 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7105 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7106 DAG.getConstant(LoByteShift, DL, MVT::i8));
7107 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7108 DAG.getConstant(HiByteShift, DL, MVT::i8));
7109 return DAG.getBitcast(VT,
7110 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7113 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7115 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7116 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7117 /// matches elements from one of the input vectors shuffled to the left or
7118 /// right with zeroable elements 'shifted in'. It handles both the strictly
7119 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7122 /// PSHL : (little-endian) left bit shift.
7123 /// [ zz, 0, zz, 2 ]
7124 /// [ -1, 4, zz, -1 ]
7125 /// PSRL : (little-endian) right bit shift.
7127 /// [ -1, -1, 7, zz]
7128 /// PSLLDQ : (little-endian) left byte shift
7129 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7130 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7131 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7132 /// PSRLDQ : (little-endian) right byte shift
7133 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7134 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7135 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7136 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7137 SDValue V2, ArrayRef<int> Mask,
7138 SelectionDAG &DAG) {
7139 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7141 int Size = Mask.size();
7142 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7144 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7145 for (int i = 0; i < Size; i += Scale)
7146 for (int j = 0; j < Shift; ++j)
7147 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7153 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7154 for (int i = 0; i != Size; i += Scale) {
7155 unsigned Pos = Left ? i + Shift : i;
7156 unsigned Low = Left ? i : i + Shift;
7157 unsigned Len = Scale - Shift;
7158 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7159 Low + (V == V1 ? 0 : Size)))
7163 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7164 bool ByteShift = ShiftEltBits > 64;
7165 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7166 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7167 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7169 // Normalize the scale for byte shifts to still produce an i64 element
7171 Scale = ByteShift ? Scale / 2 : Scale;
7173 // We need to round trip through the appropriate type for the shift.
7174 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7175 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7176 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7177 "Illegal integer vector type");
7178 V = DAG.getBitcast(ShiftVT, V);
7180 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7181 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7182 return DAG.getBitcast(VT, V);
7185 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7186 // keep doubling the size of the integer elements up to that. We can
7187 // then shift the elements of the integer vector by whole multiples of
7188 // their width within the elements of the larger integer vector. Test each
7189 // multiple to see if we can find a match with the moved element indices
7190 // and that the shifted in elements are all zeroable.
7191 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7192 for (int Shift = 1; Shift != Scale; ++Shift)
7193 for (bool Left : {true, false})
7194 if (CheckZeros(Shift, Scale, Left))
7195 for (SDValue V : {V1, V2})
7196 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7203 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7204 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7205 SDValue V2, ArrayRef<int> Mask,
7206 SelectionDAG &DAG) {
7207 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7208 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7210 int Size = Mask.size();
7211 int HalfSize = Size / 2;
7212 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7214 // Upper half must be undefined.
7215 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7218 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7219 // Remainder of lower half result is zero and upper half is all undef.
7220 auto LowerAsEXTRQ = [&]() {
7221 // Determine the extraction length from the part of the
7222 // lower half that isn't zeroable.
7224 for (; Len >= 0; --Len)
7225 if (!Zeroable[Len - 1])
7227 assert(Len > 0 && "Zeroable shuffle mask");
7229 // Attempt to match first Len sequential elements from the lower half.
7232 for (int i = 0; i != Len; ++i) {
7236 SDValue &V = (M < Size ? V1 : V2);
7239 // All mask elements must be in the lower half.
7243 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7254 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7255 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7256 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7257 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7258 DAG.getConstant(BitLen, DL, MVT::i8),
7259 DAG.getConstant(BitIdx, DL, MVT::i8));
7262 if (SDValue ExtrQ = LowerAsEXTRQ())
7265 // INSERTQ: Extract lowest Len elements from lower half of second source and
7266 // insert over first source, starting at Idx.
7267 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7268 auto LowerAsInsertQ = [&]() {
7269 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7272 // Attempt to match first source from mask before insertion point.
7273 if (isUndefInRange(Mask, 0, Idx)) {
7275 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7277 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7283 // Extend the extraction length looking to match both the insertion of
7284 // the second source and the remaining elements of the first.
7285 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7290 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7292 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7298 // Match the remaining elements of the lower half.
7299 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7301 } else if ((!Base || (Base == V1)) &&
7302 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7304 } else if ((!Base || (Base == V2)) &&
7305 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7312 // We may not have a base (first source) - this can safely be undefined.
7314 Base = DAG.getUNDEF(VT);
7316 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7317 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7318 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7319 DAG.getConstant(BitLen, DL, MVT::i8),
7320 DAG.getConstant(BitIdx, DL, MVT::i8));
7327 if (SDValue InsertQ = LowerAsInsertQ())
7333 /// \brief Lower a vector shuffle as a zero or any extension.
7335 /// Given a specific number of elements, element bit width, and extension
7336 /// stride, produce either a zero or any extension based on the available
7337 /// features of the subtarget.
7338 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7339 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
7340 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7341 assert(Scale > 1 && "Need a scale to extend.");
7342 int NumElements = VT.getVectorNumElements();
7343 int EltBits = VT.getScalarSizeInBits();
7344 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7345 "Only 8, 16, and 32 bit elements can be extended.");
7346 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7348 // Found a valid zext mask! Try various lowering strategies based on the
7349 // input type and available ISA extensions.
7350 if (Subtarget->hasSSE41()) {
7351 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7352 NumElements / Scale);
7353 return DAG.getBitcast(VT, DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7356 // For any extends we can cheat for larger element sizes and use shuffle
7357 // instructions that can fold with a load and/or copy.
7358 if (AnyExt && EltBits == 32) {
7359 int PSHUFDMask[4] = {0, -1, 1, -1};
7360 return DAG.getBitcast(
7361 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7362 DAG.getBitcast(MVT::v4i32, InputV),
7363 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7365 if (AnyExt && EltBits == 16 && Scale > 2) {
7366 int PSHUFDMask[4] = {0, -1, 0, -1};
7367 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7368 DAG.getBitcast(MVT::v4i32, InputV),
7369 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7370 int PSHUFHWMask[4] = {1, -1, -1, -1};
7371 return DAG.getBitcast(
7372 VT, DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7373 DAG.getBitcast(MVT::v8i16, InputV),
7374 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
7377 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7379 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7380 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7381 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7383 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7384 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7385 DAG.getConstant(EltBits, DL, MVT::i8),
7386 DAG.getConstant(0, DL, MVT::i8)));
7387 if (isUndefInRange(Mask, NumElements/2, NumElements/2))
7388 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7391 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7392 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7393 DAG.getConstant(EltBits, DL, MVT::i8),
7394 DAG.getConstant(EltBits, DL, MVT::i8)));
7395 return DAG.getNode(ISD::BITCAST, DL, VT,
7396 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7399 // If this would require more than 2 unpack instructions to expand, use
7400 // pshufb when available. We can only use more than 2 unpack instructions
7401 // when zero extending i8 elements which also makes it easier to use pshufb.
7402 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7403 assert(NumElements == 16 && "Unexpected byte vector width!");
7404 SDValue PSHUFBMask[16];
7405 for (int i = 0; i < 16; ++i)
7407 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
7408 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7409 return DAG.getBitcast(VT,
7410 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7411 DAG.getNode(ISD::BUILD_VECTOR, DL,
7412 MVT::v16i8, PSHUFBMask)));
7415 // Otherwise emit a sequence of unpacks.
7417 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7418 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7419 : getZeroVector(InputVT, Subtarget, DAG, DL);
7420 InputV = DAG.getBitcast(InputVT, InputV);
7421 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7425 } while (Scale > 1);
7426 return DAG.getBitcast(VT, InputV);
7429 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7431 /// This routine will try to do everything in its power to cleverly lower
7432 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7433 /// check for the profitability of this lowering, it tries to aggressively
7434 /// match this pattern. It will use all of the micro-architectural details it
7435 /// can to emit an efficient lowering. It handles both blends with all-zero
7436 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7437 /// masking out later).
7439 /// The reason we have dedicated lowering for zext-style shuffles is that they
7440 /// are both incredibly common and often quite performance sensitive.
7441 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7442 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7443 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7444 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7446 int Bits = VT.getSizeInBits();
7447 int NumElements = VT.getVectorNumElements();
7448 assert(VT.getScalarSizeInBits() <= 32 &&
7449 "Exceeds 32-bit integer zero extension limit");
7450 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7452 // Define a helper function to check a particular ext-scale and lower to it if
7454 auto Lower = [&](int Scale) -> SDValue {
7457 for (int i = 0; i < NumElements; ++i) {
7459 continue; // Valid anywhere but doesn't tell us anything.
7460 if (i % Scale != 0) {
7461 // Each of the extended elements need to be zeroable.
7465 // We no longer are in the anyext case.
7470 // Each of the base elements needs to be consecutive indices into the
7471 // same input vector.
7472 SDValue V = Mask[i] < NumElements ? V1 : V2;
7475 else if (InputV != V)
7476 return SDValue(); // Flip-flopping inputs.
7478 if (Mask[i] % NumElements != i / Scale)
7479 return SDValue(); // Non-consecutive strided elements.
7482 // If we fail to find an input, we have a zero-shuffle which should always
7483 // have already been handled.
7484 // FIXME: Maybe handle this here in case during blending we end up with one?
7488 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7489 DL, VT, Scale, AnyExt, InputV, Mask, Subtarget, DAG);
7492 // The widest scale possible for extending is to a 64-bit integer.
7493 assert(Bits % 64 == 0 &&
7494 "The number of bits in a vector must be divisible by 64 on x86!");
7495 int NumExtElements = Bits / 64;
7497 // Each iteration, try extending the elements half as much, but into twice as
7499 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7500 assert(NumElements % NumExtElements == 0 &&
7501 "The input vector size must be divisible by the extended size.");
7502 if (SDValue V = Lower(NumElements / NumExtElements))
7506 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7510 // Returns one of the source operands if the shuffle can be reduced to a
7511 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7512 auto CanZExtLowHalf = [&]() {
7513 for (int i = NumElements / 2; i != NumElements; ++i)
7516 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7518 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7523 if (SDValue V = CanZExtLowHalf()) {
7524 V = DAG.getBitcast(MVT::v2i64, V);
7525 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7526 return DAG.getBitcast(VT, V);
7529 // No viable ext lowering found.
7533 /// \brief Try to get a scalar value for a specific element of a vector.
7535 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7536 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7537 SelectionDAG &DAG) {
7538 MVT VT = V.getSimpleValueType();
7539 MVT EltVT = VT.getVectorElementType();
7540 while (V.getOpcode() == ISD::BITCAST)
7541 V = V.getOperand(0);
7542 // If the bitcasts shift the element size, we can't extract an equivalent
7544 MVT NewVT = V.getSimpleValueType();
7545 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7548 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7549 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7550 // Ensure the scalar operand is the same size as the destination.
7551 // FIXME: Add support for scalar truncation where possible.
7552 SDValue S = V.getOperand(Idx);
7553 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7554 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7560 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7562 /// This is particularly important because the set of instructions varies
7563 /// significantly based on whether the operand is a load or not.
7564 static bool isShuffleFoldableLoad(SDValue V) {
7565 while (V.getOpcode() == ISD::BITCAST)
7566 V = V.getOperand(0);
7568 return ISD::isNON_EXTLoad(V.getNode());
7571 /// \brief Try to lower insertion of a single element into a zero vector.
7573 /// This is a common pattern that we have especially efficient patterns to lower
7574 /// across all subtarget feature sets.
7575 static SDValue lowerVectorShuffleAsElementInsertion(
7576 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7577 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7578 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7580 MVT EltVT = VT.getVectorElementType();
7582 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7583 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7585 bool IsV1Zeroable = true;
7586 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7587 if (i != V2Index && !Zeroable[i]) {
7588 IsV1Zeroable = false;
7592 // Check for a single input from a SCALAR_TO_VECTOR node.
7593 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7594 // all the smarts here sunk into that routine. However, the current
7595 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7596 // vector shuffle lowering is dead.
7597 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7599 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7600 // We need to zext the scalar if it is smaller than an i32.
7601 V2S = DAG.getBitcast(EltVT, V2S);
7602 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7603 // Using zext to expand a narrow element won't work for non-zero
7608 // Zero-extend directly to i32.
7610 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7612 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7613 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7614 EltVT == MVT::i16) {
7615 // Either not inserting from the low element of the input or the input
7616 // element size is too small to use VZEXT_MOVL to clear the high bits.
7620 if (!IsV1Zeroable) {
7621 // If V1 can't be treated as a zero vector we have fewer options to lower
7622 // this. We can't support integer vectors or non-zero targets cheaply, and
7623 // the V1 elements can't be permuted in any way.
7624 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7625 if (!VT.isFloatingPoint() || V2Index != 0)
7627 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7628 V1Mask[V2Index] = -1;
7629 if (!isNoopShuffleMask(V1Mask))
7631 // This is essentially a special case blend operation, but if we have
7632 // general purpose blend operations, they are always faster. Bail and let
7633 // the rest of the lowering handle these as blends.
7634 if (Subtarget->hasSSE41())
7637 // Otherwise, use MOVSD or MOVSS.
7638 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7639 "Only two types of floating point element types to handle!");
7640 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7644 // This lowering only works for the low element with floating point vectors.
7645 if (VT.isFloatingPoint() && V2Index != 0)
7648 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7650 V2 = DAG.getBitcast(VT, V2);
7653 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7654 // the desired position. Otherwise it is more efficient to do a vector
7655 // shift left. We know that we can do a vector shift left because all
7656 // the inputs are zero.
7657 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7658 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7659 V2Shuffle[V2Index] = 0;
7660 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7662 V2 = DAG.getBitcast(MVT::v2i64, V2);
7664 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7665 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7666 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7667 DAG.getDataLayout(), VT)));
7668 V2 = DAG.getBitcast(VT, V2);
7674 /// \brief Try to lower broadcast of a single element.
7676 /// For convenience, this code also bundles all of the subtarget feature set
7677 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7678 /// a convenient way to factor it out.
7679 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7681 const X86Subtarget *Subtarget,
7682 SelectionDAG &DAG) {
7683 if (!Subtarget->hasAVX())
7685 if (VT.isInteger() && !Subtarget->hasAVX2())
7688 // Check that the mask is a broadcast.
7689 int BroadcastIdx = -1;
7691 if (M >= 0 && BroadcastIdx == -1)
7693 else if (M >= 0 && M != BroadcastIdx)
7696 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7697 "a sorted mask where the broadcast "
7700 // Go up the chain of (vector) values to find a scalar load that we can
7701 // combine with the broadcast.
7703 switch (V.getOpcode()) {
7704 case ISD::CONCAT_VECTORS: {
7705 int OperandSize = Mask.size() / V.getNumOperands();
7706 V = V.getOperand(BroadcastIdx / OperandSize);
7707 BroadcastIdx %= OperandSize;
7711 case ISD::INSERT_SUBVECTOR: {
7712 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7713 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7717 int BeginIdx = (int)ConstantIdx->getZExtValue();
7719 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7720 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7721 BroadcastIdx -= BeginIdx;
7732 // Check if this is a broadcast of a scalar. We special case lowering
7733 // for scalars so that we can more effectively fold with loads.
7734 // First, look through bitcast: if the original value has a larger element
7735 // type than the shuffle, the broadcast element is in essence truncated.
7736 // Make that explicit to ease folding.
7737 if (V.getOpcode() == ISD::BITCAST && VT.isInteger()) {
7738 EVT EltVT = VT.getVectorElementType();
7739 SDValue V0 = V.getOperand(0);
7740 EVT V0VT = V0.getValueType();
7742 if (V0VT.isInteger() && V0VT.getVectorElementType().bitsGT(EltVT) &&
7743 ((V0.getOpcode() == ISD::BUILD_VECTOR ||
7744 (V0.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)))) {
7745 V = DAG.getNode(ISD::TRUNCATE, DL, EltVT, V0.getOperand(BroadcastIdx));
7750 // Also check the simpler case, where we can directly reuse the scalar.
7751 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7752 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7753 V = V.getOperand(BroadcastIdx);
7755 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7756 // Only AVX2 has register broadcasts.
7757 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7759 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7760 // We can't broadcast from a vector register without AVX2, and we can only
7761 // broadcast from the zero-element of a vector register.
7765 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7768 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7769 // INSERTPS when the V1 elements are already in the correct locations
7770 // because otherwise we can just always use two SHUFPS instructions which
7771 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7772 // perform INSERTPS if a single V1 element is out of place and all V2
7773 // elements are zeroable.
7774 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7776 SelectionDAG &DAG) {
7777 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7778 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7779 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7780 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7782 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7785 int V1DstIndex = -1;
7786 int V2DstIndex = -1;
7787 bool V1UsedInPlace = false;
7789 for (int i = 0; i < 4; ++i) {
7790 // Synthesize a zero mask from the zeroable elements (includes undefs).
7796 // Flag if we use any V1 inputs in place.
7798 V1UsedInPlace = true;
7802 // We can only insert a single non-zeroable element.
7803 if (V1DstIndex != -1 || V2DstIndex != -1)
7807 // V1 input out of place for insertion.
7810 // V2 input for insertion.
7815 // Don't bother if we have no (non-zeroable) element for insertion.
7816 if (V1DstIndex == -1 && V2DstIndex == -1)
7819 // Determine element insertion src/dst indices. The src index is from the
7820 // start of the inserted vector, not the start of the concatenated vector.
7821 unsigned V2SrcIndex = 0;
7822 if (V1DstIndex != -1) {
7823 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7824 // and don't use the original V2 at all.
7825 V2SrcIndex = Mask[V1DstIndex];
7826 V2DstIndex = V1DstIndex;
7829 V2SrcIndex = Mask[V2DstIndex] - 4;
7832 // If no V1 inputs are used in place, then the result is created only from
7833 // the zero mask and the V2 insertion - so remove V1 dependency.
7835 V1 = DAG.getUNDEF(MVT::v4f32);
7837 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7838 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7840 // Insert the V2 element into the desired position.
7842 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7843 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7846 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7847 /// UNPCK instruction.
7849 /// This specifically targets cases where we end up with alternating between
7850 /// the two inputs, and so can permute them into something that feeds a single
7851 /// UNPCK instruction. Note that this routine only targets integer vectors
7852 /// because for floating point vectors we have a generalized SHUFPS lowering
7853 /// strategy that handles everything that doesn't *exactly* match an unpack,
7854 /// making this clever lowering unnecessary.
7855 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
7856 SDValue V1, SDValue V2,
7858 SelectionDAG &DAG) {
7859 assert(!VT.isFloatingPoint() &&
7860 "This routine only supports integer vectors.");
7861 assert(!isSingleInputShuffleMask(Mask) &&
7862 "This routine should only be used when blending two inputs.");
7863 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7865 int Size = Mask.size();
7867 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7868 return M >= 0 && M % Size < Size / 2;
7870 int NumHiInputs = std::count_if(
7871 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7873 bool UnpackLo = NumLoInputs >= NumHiInputs;
7875 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7876 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7877 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7879 for (int i = 0; i < Size; ++i) {
7883 // Each element of the unpack contains Scale elements from this mask.
7884 int UnpackIdx = i / Scale;
7886 // We only handle the case where V1 feeds the first slots of the unpack.
7887 // We rely on canonicalization to ensure this is the case.
7888 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7891 // Setup the mask for this input. The indexing is tricky as we have to
7892 // handle the unpack stride.
7893 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7894 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7898 // If we will have to shuffle both inputs to use the unpack, check whether
7899 // we can just unpack first and shuffle the result. If so, skip this unpack.
7900 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7901 !isNoopShuffleMask(V2Mask))
7904 // Shuffle the inputs into place.
7905 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7906 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7908 // Cast the inputs to the type we will use to unpack them.
7909 V1 = DAG.getBitcast(UnpackVT, V1);
7910 V2 = DAG.getBitcast(UnpackVT, V2);
7912 // Unpack the inputs and cast the result back to the desired type.
7913 return DAG.getBitcast(
7914 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7918 // We try each unpack from the largest to the smallest to try and find one
7919 // that fits this mask.
7920 int OrigNumElements = VT.getVectorNumElements();
7921 int OrigScalarSize = VT.getScalarSizeInBits();
7922 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7923 int Scale = ScalarSize / OrigScalarSize;
7924 int NumElements = OrigNumElements / Scale;
7925 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7926 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7930 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7932 if (NumLoInputs == 0 || NumHiInputs == 0) {
7933 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7934 "We have to have *some* inputs!");
7935 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7937 // FIXME: We could consider the total complexity of the permute of each
7938 // possible unpacking. Or at the least we should consider how many
7939 // half-crossings are created.
7940 // FIXME: We could consider commuting the unpacks.
7942 SmallVector<int, 32> PermMask;
7943 PermMask.assign(Size, -1);
7944 for (int i = 0; i < Size; ++i) {
7948 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7951 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7953 return DAG.getVectorShuffle(
7954 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7956 DAG.getUNDEF(VT), PermMask);
7962 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7964 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7965 /// support for floating point shuffles but not integer shuffles. These
7966 /// instructions will incur a domain crossing penalty on some chips though so
7967 /// it is better to avoid lowering through this for integer vectors where
7969 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7970 const X86Subtarget *Subtarget,
7971 SelectionDAG &DAG) {
7973 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7974 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7975 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7976 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7977 ArrayRef<int> Mask = SVOp->getMask();
7978 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7980 if (isSingleInputShuffleMask(Mask)) {
7981 // Use low duplicate instructions for masks that match their pattern.
7982 if (Subtarget->hasSSE3())
7983 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7984 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7986 // Straight shuffle of a single input vector. Simulate this by using the
7987 // single input as both of the "inputs" to this instruction..
7988 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7990 if (Subtarget->hasAVX()) {
7991 // If we have AVX, we can use VPERMILPS which will allow folding a load
7992 // into the shuffle.
7993 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7994 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7997 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7998 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8000 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8001 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8003 // If we have a single input, insert that into V1 if we can do so cheaply.
8004 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8005 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8006 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8008 // Try inverting the insertion since for v2 masks it is easy to do and we
8009 // can't reliably sort the mask one way or the other.
8010 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8011 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8012 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8013 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8017 // Try to use one of the special instruction patterns to handle two common
8018 // blend patterns if a zero-blend above didn't work.
8019 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8020 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8021 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8022 // We can either use a special instruction to load over the low double or
8023 // to move just the low double.
8025 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8027 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8029 if (Subtarget->hasSSE41())
8030 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8034 // Use dedicated unpack instructions for masks that match their pattern.
8035 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8036 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8037 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8038 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8040 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8041 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8042 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8045 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8047 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8048 /// the integer unit to minimize domain crossing penalties. However, for blends
8049 /// it falls back to the floating point shuffle operation with appropriate bit
8051 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8052 const X86Subtarget *Subtarget,
8053 SelectionDAG &DAG) {
8055 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8056 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8057 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8058 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8059 ArrayRef<int> Mask = SVOp->getMask();
8060 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8062 if (isSingleInputShuffleMask(Mask)) {
8063 // Check for being able to broadcast a single element.
8064 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8065 Mask, Subtarget, DAG))
8068 // Straight shuffle of a single input vector. For everything from SSE2
8069 // onward this has a single fast instruction with no scary immediates.
8070 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8071 V1 = DAG.getBitcast(MVT::v4i32, V1);
8072 int WidenedMask[4] = {
8073 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8074 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8075 return DAG.getBitcast(
8077 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8078 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8080 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8081 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8082 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8083 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8085 // If we have a blend of two PACKUS operations an the blend aligns with the
8086 // low and half halves, we can just merge the PACKUS operations. This is
8087 // particularly important as it lets us merge shuffles that this routine itself
8089 auto GetPackNode = [](SDValue V) {
8090 while (V.getOpcode() == ISD::BITCAST)
8091 V = V.getOperand(0);
8093 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8095 if (SDValue V1Pack = GetPackNode(V1))
8096 if (SDValue V2Pack = GetPackNode(V2))
8097 return DAG.getBitcast(MVT::v2i64,
8098 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8099 Mask[0] == 0 ? V1Pack.getOperand(0)
8100 : V1Pack.getOperand(1),
8101 Mask[1] == 2 ? V2Pack.getOperand(0)
8102 : V2Pack.getOperand(1)));
8104 // Try to use shift instructions.
8106 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8109 // When loading a scalar and then shuffling it into a vector we can often do
8110 // the insertion cheaply.
8111 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8112 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8114 // Try inverting the insertion since for v2 masks it is easy to do and we
8115 // can't reliably sort the mask one way or the other.
8116 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8117 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8118 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8121 // We have different paths for blend lowering, but they all must use the
8122 // *exact* same predicate.
8123 bool IsBlendSupported = Subtarget->hasSSE41();
8124 if (IsBlendSupported)
8125 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8129 // Use dedicated unpack instructions for masks that match their pattern.
8130 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8131 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8132 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8133 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8135 // Try to use byte rotation instructions.
8136 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8137 if (Subtarget->hasSSSE3())
8138 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8139 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8142 // If we have direct support for blends, we should lower by decomposing into
8143 // a permute. That will be faster than the domain cross.
8144 if (IsBlendSupported)
8145 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8148 // We implement this with SHUFPD which is pretty lame because it will likely
8149 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8150 // However, all the alternatives are still more cycles and newer chips don't
8151 // have this problem. It would be really nice if x86 had better shuffles here.
8152 V1 = DAG.getBitcast(MVT::v2f64, V1);
8153 V2 = DAG.getBitcast(MVT::v2f64, V2);
8154 return DAG.getBitcast(MVT::v2i64,
8155 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8158 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8160 /// This is used to disable more specialized lowerings when the shufps lowering
8161 /// will happen to be efficient.
8162 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8163 // This routine only handles 128-bit shufps.
8164 assert(Mask.size() == 4 && "Unsupported mask size!");
8166 // To lower with a single SHUFPS we need to have the low half and high half
8167 // each requiring a single input.
8168 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8170 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8176 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8178 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8179 /// It makes no assumptions about whether this is the *best* lowering, it simply
8181 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8182 ArrayRef<int> Mask, SDValue V1,
8183 SDValue V2, SelectionDAG &DAG) {
8184 SDValue LowV = V1, HighV = V2;
8185 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8188 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8190 if (NumV2Elements == 1) {
8192 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8195 // Compute the index adjacent to V2Index and in the same half by toggling
8197 int V2AdjIndex = V2Index ^ 1;
8199 if (Mask[V2AdjIndex] == -1) {
8200 // Handles all the cases where we have a single V2 element and an undef.
8201 // This will only ever happen in the high lanes because we commute the
8202 // vector otherwise.
8204 std::swap(LowV, HighV);
8205 NewMask[V2Index] -= 4;
8207 // Handle the case where the V2 element ends up adjacent to a V1 element.
8208 // To make this work, blend them together as the first step.
8209 int V1Index = V2AdjIndex;
8210 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8211 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8212 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8214 // Now proceed to reconstruct the final blend as we have the necessary
8215 // high or low half formed.
8222 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8223 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8225 } else if (NumV2Elements == 2) {
8226 if (Mask[0] < 4 && Mask[1] < 4) {
8227 // Handle the easy case where we have V1 in the low lanes and V2 in the
8231 } else if (Mask[2] < 4 && Mask[3] < 4) {
8232 // We also handle the reversed case because this utility may get called
8233 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8234 // arrange things in the right direction.
8240 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8241 // trying to place elements directly, just blend them and set up the final
8242 // shuffle to place them.
8244 // The first two blend mask elements are for V1, the second two are for
8246 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8247 Mask[2] < 4 ? Mask[2] : Mask[3],
8248 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8249 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8250 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8251 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8253 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8256 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8257 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8258 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8259 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8262 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8263 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8266 /// \brief Lower 4-lane 32-bit floating point shuffles.
8268 /// Uses instructions exclusively from the floating point unit to minimize
8269 /// domain crossing penalties, as these are sufficient to implement all v4f32
8271 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8272 const X86Subtarget *Subtarget,
8273 SelectionDAG &DAG) {
8275 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8276 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8277 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8278 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8279 ArrayRef<int> Mask = SVOp->getMask();
8280 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8283 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8285 if (NumV2Elements == 0) {
8286 // Check for being able to broadcast a single element.
8287 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8288 Mask, Subtarget, DAG))
8291 // Use even/odd duplicate instructions for masks that match their pattern.
8292 if (Subtarget->hasSSE3()) {
8293 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8294 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8295 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8296 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8299 if (Subtarget->hasAVX()) {
8300 // If we have AVX, we can use VPERMILPS which will allow folding a load
8301 // into the shuffle.
8302 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8303 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8306 // Otherwise, use a straight shuffle of a single input vector. We pass the
8307 // input vector to both operands to simulate this with a SHUFPS.
8308 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8309 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8312 // There are special ways we can lower some single-element blends. However, we
8313 // have custom ways we can lower more complex single-element blends below that
8314 // we defer to if both this and BLENDPS fail to match, so restrict this to
8315 // when the V2 input is targeting element 0 of the mask -- that is the fast
8317 if (NumV2Elements == 1 && Mask[0] >= 4)
8318 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8319 Mask, Subtarget, DAG))
8322 if (Subtarget->hasSSE41()) {
8323 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8327 // Use INSERTPS if we can complete the shuffle efficiently.
8328 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8331 if (!isSingleSHUFPSMask(Mask))
8332 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8333 DL, MVT::v4f32, V1, V2, Mask, DAG))
8337 // Use dedicated unpack instructions for masks that match their pattern.
8338 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8339 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8340 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8341 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8342 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8343 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8344 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8345 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8347 // Otherwise fall back to a SHUFPS lowering strategy.
8348 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8351 /// \brief Lower 4-lane i32 vector shuffles.
8353 /// We try to handle these with integer-domain shuffles where we can, but for
8354 /// blends we use the floating point domain blend instructions.
8355 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8356 const X86Subtarget *Subtarget,
8357 SelectionDAG &DAG) {
8359 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8360 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8361 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8362 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8363 ArrayRef<int> Mask = SVOp->getMask();
8364 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8366 // Whenever we can lower this as a zext, that instruction is strictly faster
8367 // than any alternative. It also allows us to fold memory operands into the
8368 // shuffle in many cases.
8369 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8370 Mask, Subtarget, DAG))
8374 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8376 if (NumV2Elements == 0) {
8377 // Check for being able to broadcast a single element.
8378 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8379 Mask, Subtarget, DAG))
8382 // Straight shuffle of a single input vector. For everything from SSE2
8383 // onward this has a single fast instruction with no scary immediates.
8384 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8385 // but we aren't actually going to use the UNPCK instruction because doing
8386 // so prevents folding a load into this instruction or making a copy.
8387 const int UnpackLoMask[] = {0, 0, 1, 1};
8388 const int UnpackHiMask[] = {2, 2, 3, 3};
8389 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8390 Mask = UnpackLoMask;
8391 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8392 Mask = UnpackHiMask;
8394 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8395 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8398 // Try to use shift instructions.
8400 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8403 // There are special ways we can lower some single-element blends.
8404 if (NumV2Elements == 1)
8405 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8406 Mask, Subtarget, DAG))
8409 // We have different paths for blend lowering, but they all must use the
8410 // *exact* same predicate.
8411 bool IsBlendSupported = Subtarget->hasSSE41();
8412 if (IsBlendSupported)
8413 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8417 if (SDValue Masked =
8418 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8421 // Use dedicated unpack instructions for masks that match their pattern.
8422 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8423 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8424 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8425 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8426 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8427 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8428 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8429 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8431 // Try to use byte rotation instructions.
8432 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8433 if (Subtarget->hasSSSE3())
8434 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8435 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8438 // If we have direct support for blends, we should lower by decomposing into
8439 // a permute. That will be faster than the domain cross.
8440 if (IsBlendSupported)
8441 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8444 // Try to lower by permuting the inputs into an unpack instruction.
8445 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8449 // We implement this with SHUFPS because it can blend from two vectors.
8450 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8451 // up the inputs, bypassing domain shift penalties that we would encur if we
8452 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8454 return DAG.getBitcast(
8456 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8457 DAG.getBitcast(MVT::v4f32, V2), Mask));
8460 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8461 /// shuffle lowering, and the most complex part.
8463 /// The lowering strategy is to try to form pairs of input lanes which are
8464 /// targeted at the same half of the final vector, and then use a dword shuffle
8465 /// to place them onto the right half, and finally unpack the paired lanes into
8466 /// their final position.
8468 /// The exact breakdown of how to form these dword pairs and align them on the
8469 /// correct sides is really tricky. See the comments within the function for
8470 /// more of the details.
8472 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8473 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8474 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8475 /// vector, form the analogous 128-bit 8-element Mask.
8476 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8477 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8478 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8479 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8480 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8482 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8483 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8484 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8486 SmallVector<int, 4> LoInputs;
8487 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8488 [](int M) { return M >= 0; });
8489 std::sort(LoInputs.begin(), LoInputs.end());
8490 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8491 SmallVector<int, 4> HiInputs;
8492 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8493 [](int M) { return M >= 0; });
8494 std::sort(HiInputs.begin(), HiInputs.end());
8495 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8497 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8498 int NumHToL = LoInputs.size() - NumLToL;
8500 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8501 int NumHToH = HiInputs.size() - NumLToH;
8502 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8503 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8504 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8505 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8507 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8508 // such inputs we can swap two of the dwords across the half mark and end up
8509 // with <=2 inputs to each half in each half. Once there, we can fall through
8510 // to the generic code below. For example:
8512 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8513 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8515 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8516 // and an existing 2-into-2 on the other half. In this case we may have to
8517 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8518 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8519 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8520 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8521 // half than the one we target for fixing) will be fixed when we re-enter this
8522 // path. We will also combine away any sequence of PSHUFD instructions that
8523 // result into a single instruction. Here is an example of the tricky case:
8525 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8526 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8528 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8530 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8531 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8533 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8534 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8536 // The result is fine to be handled by the generic logic.
8537 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8538 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8539 int AOffset, int BOffset) {
8540 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8541 "Must call this with A having 3 or 1 inputs from the A half.");
8542 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8543 "Must call this with B having 1 or 3 inputs from the B half.");
8544 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8545 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8547 bool ThreeAInputs = AToAInputs.size() == 3;
8549 // Compute the index of dword with only one word among the three inputs in
8550 // a half by taking the sum of the half with three inputs and subtracting
8551 // the sum of the actual three inputs. The difference is the remaining
8554 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8555 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8556 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8557 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8558 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8559 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8560 int TripleNonInputIdx =
8561 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8562 TripleDWord = TripleNonInputIdx / 2;
8564 // We use xor with one to compute the adjacent DWord to whichever one the
8566 OneInputDWord = (OneInput / 2) ^ 1;
8568 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8569 // and BToA inputs. If there is also such a problem with the BToB and AToB
8570 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8571 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8572 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8573 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8574 // Compute how many inputs will be flipped by swapping these DWords. We
8576 // to balance this to ensure we don't form a 3-1 shuffle in the other
8578 int NumFlippedAToBInputs =
8579 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8580 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8581 int NumFlippedBToBInputs =
8582 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8583 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8584 if ((NumFlippedAToBInputs == 1 &&
8585 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8586 (NumFlippedBToBInputs == 1 &&
8587 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8588 // We choose whether to fix the A half or B half based on whether that
8589 // half has zero flipped inputs. At zero, we may not be able to fix it
8590 // with that half. We also bias towards fixing the B half because that
8591 // will more commonly be the high half, and we have to bias one way.
8592 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8593 ArrayRef<int> Inputs) {
8594 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8595 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8596 PinnedIdx ^ 1) != Inputs.end();
8597 // Determine whether the free index is in the flipped dword or the
8598 // unflipped dword based on where the pinned index is. We use this bit
8599 // in an xor to conditionally select the adjacent dword.
8600 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8601 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8602 FixFreeIdx) != Inputs.end();
8603 if (IsFixIdxInput == IsFixFreeIdxInput)
8605 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8606 FixFreeIdx) != Inputs.end();
8607 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8608 "We need to be changing the number of flipped inputs!");
8609 int PSHUFHalfMask[] = {0, 1, 2, 3};
8610 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8611 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8613 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8616 if (M != -1 && M == FixIdx)
8618 else if (M != -1 && M == FixFreeIdx)
8621 if (NumFlippedBToBInputs != 0) {
8623 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8624 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8626 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8627 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8628 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8633 int PSHUFDMask[] = {0, 1, 2, 3};
8634 PSHUFDMask[ADWord] = BDWord;
8635 PSHUFDMask[BDWord] = ADWord;
8638 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8639 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8641 // Adjust the mask to match the new locations of A and B.
8643 if (M != -1 && M/2 == ADWord)
8644 M = 2 * BDWord + M % 2;
8645 else if (M != -1 && M/2 == BDWord)
8646 M = 2 * ADWord + M % 2;
8648 // Recurse back into this routine to re-compute state now that this isn't
8649 // a 3 and 1 problem.
8650 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8653 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8654 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8655 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8656 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8658 // At this point there are at most two inputs to the low and high halves from
8659 // each half. That means the inputs can always be grouped into dwords and
8660 // those dwords can then be moved to the correct half with a dword shuffle.
8661 // We use at most one low and one high word shuffle to collect these paired
8662 // inputs into dwords, and finally a dword shuffle to place them.
8663 int PSHUFLMask[4] = {-1, -1, -1, -1};
8664 int PSHUFHMask[4] = {-1, -1, -1, -1};
8665 int PSHUFDMask[4] = {-1, -1, -1, -1};
8667 // First fix the masks for all the inputs that are staying in their
8668 // original halves. This will then dictate the targets of the cross-half
8670 auto fixInPlaceInputs =
8671 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8672 MutableArrayRef<int> SourceHalfMask,
8673 MutableArrayRef<int> HalfMask, int HalfOffset) {
8674 if (InPlaceInputs.empty())
8676 if (InPlaceInputs.size() == 1) {
8677 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8678 InPlaceInputs[0] - HalfOffset;
8679 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8682 if (IncomingInputs.empty()) {
8683 // Just fix all of the in place inputs.
8684 for (int Input : InPlaceInputs) {
8685 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8686 PSHUFDMask[Input / 2] = Input / 2;
8691 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8692 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8693 InPlaceInputs[0] - HalfOffset;
8694 // Put the second input next to the first so that they are packed into
8695 // a dword. We find the adjacent index by toggling the low bit.
8696 int AdjIndex = InPlaceInputs[0] ^ 1;
8697 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8698 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8699 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8701 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8702 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8704 // Now gather the cross-half inputs and place them into a free dword of
8705 // their target half.
8706 // FIXME: This operation could almost certainly be simplified dramatically to
8707 // look more like the 3-1 fixing operation.
8708 auto moveInputsToRightHalf = [&PSHUFDMask](
8709 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8710 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8711 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8713 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8714 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8716 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8718 int LowWord = Word & ~1;
8719 int HighWord = Word | 1;
8720 return isWordClobbered(SourceHalfMask, LowWord) ||
8721 isWordClobbered(SourceHalfMask, HighWord);
8724 if (IncomingInputs.empty())
8727 if (ExistingInputs.empty()) {
8728 // Map any dwords with inputs from them into the right half.
8729 for (int Input : IncomingInputs) {
8730 // If the source half mask maps over the inputs, turn those into
8731 // swaps and use the swapped lane.
8732 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8733 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8734 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8735 Input - SourceOffset;
8736 // We have to swap the uses in our half mask in one sweep.
8737 for (int &M : HalfMask)
8738 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8740 else if (M == Input)
8741 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8743 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8744 Input - SourceOffset &&
8745 "Previous placement doesn't match!");
8747 // Note that this correctly re-maps both when we do a swap and when
8748 // we observe the other side of the swap above. We rely on that to
8749 // avoid swapping the members of the input list directly.
8750 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8753 // Map the input's dword into the correct half.
8754 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8755 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8757 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8759 "Previous placement doesn't match!");
8762 // And just directly shift any other-half mask elements to be same-half
8763 // as we will have mirrored the dword containing the element into the
8764 // same position within that half.
8765 for (int &M : HalfMask)
8766 if (M >= SourceOffset && M < SourceOffset + 4) {
8767 M = M - SourceOffset + DestOffset;
8768 assert(M >= 0 && "This should never wrap below zero!");
8773 // Ensure we have the input in a viable dword of its current half. This
8774 // is particularly tricky because the original position may be clobbered
8775 // by inputs being moved and *staying* in that half.
8776 if (IncomingInputs.size() == 1) {
8777 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8778 int InputFixed = std::find(std::begin(SourceHalfMask),
8779 std::end(SourceHalfMask), -1) -
8780 std::begin(SourceHalfMask) + SourceOffset;
8781 SourceHalfMask[InputFixed - SourceOffset] =
8782 IncomingInputs[0] - SourceOffset;
8783 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8785 IncomingInputs[0] = InputFixed;
8787 } else if (IncomingInputs.size() == 2) {
8788 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8789 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8790 // We have two non-adjacent or clobbered inputs we need to extract from
8791 // the source half. To do this, we need to map them into some adjacent
8792 // dword slot in the source mask.
8793 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8794 IncomingInputs[1] - SourceOffset};
8796 // If there is a free slot in the source half mask adjacent to one of
8797 // the inputs, place the other input in it. We use (Index XOR 1) to
8798 // compute an adjacent index.
8799 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8800 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8801 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8802 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8803 InputsFixed[1] = InputsFixed[0] ^ 1;
8804 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8805 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8806 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8807 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8808 InputsFixed[0] = InputsFixed[1] ^ 1;
8809 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8810 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8811 // The two inputs are in the same DWord but it is clobbered and the
8812 // adjacent DWord isn't used at all. Move both inputs to the free
8814 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8815 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8816 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8817 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8819 // The only way we hit this point is if there is no clobbering
8820 // (because there are no off-half inputs to this half) and there is no
8821 // free slot adjacent to one of the inputs. In this case, we have to
8822 // swap an input with a non-input.
8823 for (int i = 0; i < 4; ++i)
8824 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8825 "We can't handle any clobbers here!");
8826 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8827 "Cannot have adjacent inputs here!");
8829 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8830 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8832 // We also have to update the final source mask in this case because
8833 // it may need to undo the above swap.
8834 for (int &M : FinalSourceHalfMask)
8835 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8836 M = InputsFixed[1] + SourceOffset;
8837 else if (M == InputsFixed[1] + SourceOffset)
8838 M = (InputsFixed[0] ^ 1) + SourceOffset;
8840 InputsFixed[1] = InputsFixed[0] ^ 1;
8843 // Point everything at the fixed inputs.
8844 for (int &M : HalfMask)
8845 if (M == IncomingInputs[0])
8846 M = InputsFixed[0] + SourceOffset;
8847 else if (M == IncomingInputs[1])
8848 M = InputsFixed[1] + SourceOffset;
8850 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8851 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8854 llvm_unreachable("Unhandled input size!");
8857 // Now hoist the DWord down to the right half.
8858 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8859 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8860 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8861 for (int &M : HalfMask)
8862 for (int Input : IncomingInputs)
8864 M = FreeDWord * 2 + Input % 2;
8866 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8867 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8868 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8869 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8871 // Now enact all the shuffles we've computed to move the inputs into their
8873 if (!isNoopShuffleMask(PSHUFLMask))
8874 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8875 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8876 if (!isNoopShuffleMask(PSHUFHMask))
8877 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8878 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8879 if (!isNoopShuffleMask(PSHUFDMask))
8882 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8883 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8885 // At this point, each half should contain all its inputs, and we can then
8886 // just shuffle them into their final position.
8887 assert(std::count_if(LoMask.begin(), LoMask.end(),
8888 [](int M) { return M >= 4; }) == 0 &&
8889 "Failed to lift all the high half inputs to the low mask!");
8890 assert(std::count_if(HiMask.begin(), HiMask.end(),
8891 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8892 "Failed to lift all the low half inputs to the high mask!");
8894 // Do a half shuffle for the low mask.
8895 if (!isNoopShuffleMask(LoMask))
8896 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8897 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8899 // Do a half shuffle with the high mask after shifting its values down.
8900 for (int &M : HiMask)
8903 if (!isNoopShuffleMask(HiMask))
8904 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8905 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8910 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8911 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8912 SDValue V2, ArrayRef<int> Mask,
8913 SelectionDAG &DAG, bool &V1InUse,
8915 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8921 int Size = Mask.size();
8922 int Scale = 16 / Size;
8923 for (int i = 0; i < 16; ++i) {
8924 if (Mask[i / Scale] == -1) {
8925 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8927 const int ZeroMask = 0x80;
8928 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8930 int V2Idx = Mask[i / Scale] < Size
8932 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8933 if (Zeroable[i / Scale])
8934 V1Idx = V2Idx = ZeroMask;
8935 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8936 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8937 V1InUse |= (ZeroMask != V1Idx);
8938 V2InUse |= (ZeroMask != V2Idx);
8943 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8944 DAG.getBitcast(MVT::v16i8, V1),
8945 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8947 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8948 DAG.getBitcast(MVT::v16i8, V2),
8949 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8951 // If we need shuffled inputs from both, blend the two.
8953 if (V1InUse && V2InUse)
8954 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8956 V = V1InUse ? V1 : V2;
8958 // Cast the result back to the correct type.
8959 return DAG.getBitcast(VT, V);
8962 /// \brief Generic lowering of 8-lane i16 shuffles.
8964 /// This handles both single-input shuffles and combined shuffle/blends with
8965 /// two inputs. The single input shuffles are immediately delegated to
8966 /// a dedicated lowering routine.
8968 /// The blends are lowered in one of three fundamental ways. If there are few
8969 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8970 /// of the input is significantly cheaper when lowered as an interleaving of
8971 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8972 /// halves of the inputs separately (making them have relatively few inputs)
8973 /// and then concatenate them.
8974 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8975 const X86Subtarget *Subtarget,
8976 SelectionDAG &DAG) {
8978 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8979 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8980 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8981 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8982 ArrayRef<int> OrigMask = SVOp->getMask();
8983 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8984 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8985 MutableArrayRef<int> Mask(MaskStorage);
8987 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8989 // Whenever we can lower this as a zext, that instruction is strictly faster
8990 // than any alternative.
8991 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8992 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8995 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8997 auto isV2 = [](int M) { return M >= 8; };
8999 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9001 if (NumV2Inputs == 0) {
9002 // Check for being able to broadcast a single element.
9003 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9004 Mask, Subtarget, DAG))
9007 // Try to use shift instructions.
9009 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9012 // Use dedicated unpack instructions for masks that match their pattern.
9013 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
9014 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
9015 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
9016 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
9018 // Try to use byte rotation instructions.
9019 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9020 Mask, Subtarget, DAG))
9023 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9027 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9028 "All single-input shuffles should be canonicalized to be V1-input "
9031 // Try to use shift instructions.
9033 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9036 // See if we can use SSE4A Extraction / Insertion.
9037 if (Subtarget->hasSSE4A())
9038 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9041 // There are special ways we can lower some single-element blends.
9042 if (NumV2Inputs == 1)
9043 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9044 Mask, Subtarget, DAG))
9047 // We have different paths for blend lowering, but they all must use the
9048 // *exact* same predicate.
9049 bool IsBlendSupported = Subtarget->hasSSE41();
9050 if (IsBlendSupported)
9051 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9055 if (SDValue Masked =
9056 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9059 // Use dedicated unpack instructions for masks that match their pattern.
9060 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
9061 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9062 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
9063 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9065 // Try to use byte rotation instructions.
9066 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9067 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9070 if (SDValue BitBlend =
9071 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9074 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9078 // If we can't directly blend but can use PSHUFB, that will be better as it
9079 // can both shuffle and set up the inefficient blend.
9080 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9081 bool V1InUse, V2InUse;
9082 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9086 // We can always bit-blend if we have to so the fallback strategy is to
9087 // decompose into single-input permutes and blends.
9088 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9092 /// \brief Check whether a compaction lowering can be done by dropping even
9093 /// elements and compute how many times even elements must be dropped.
9095 /// This handles shuffles which take every Nth element where N is a power of
9096 /// two. Example shuffle masks:
9098 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9099 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9100 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9101 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9102 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9103 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9105 /// Any of these lanes can of course be undef.
9107 /// This routine only supports N <= 3.
9108 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9111 /// \returns N above, or the number of times even elements must be dropped if
9112 /// there is such a number. Otherwise returns zero.
9113 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9114 // Figure out whether we're looping over two inputs or just one.
9115 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9117 // The modulus for the shuffle vector entries is based on whether this is
9118 // a single input or not.
9119 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9120 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9121 "We should only be called with masks with a power-of-2 size!");
9123 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9125 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9126 // and 2^3 simultaneously. This is because we may have ambiguity with
9127 // partially undef inputs.
9128 bool ViableForN[3] = {true, true, true};
9130 for (int i = 0, e = Mask.size(); i < e; ++i) {
9131 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9136 bool IsAnyViable = false;
9137 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9138 if (ViableForN[j]) {
9141 // The shuffle mask must be equal to (i * 2^N) % M.
9142 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9145 ViableForN[j] = false;
9147 // Early exit if we exhaust the possible powers of two.
9152 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9156 // Return 0 as there is no viable power of two.
9160 /// \brief Generic lowering of v16i8 shuffles.
9162 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9163 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9164 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9165 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9167 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9168 const X86Subtarget *Subtarget,
9169 SelectionDAG &DAG) {
9171 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9172 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9173 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9174 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9175 ArrayRef<int> Mask = SVOp->getMask();
9176 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9178 // Try to use shift instructions.
9180 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9183 // Try to use byte rotation instructions.
9184 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9185 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9188 // Try to use a zext lowering.
9189 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9190 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9193 // See if we can use SSE4A Extraction / Insertion.
9194 if (Subtarget->hasSSE4A())
9195 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9199 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9201 // For single-input shuffles, there are some nicer lowering tricks we can use.
9202 if (NumV2Elements == 0) {
9203 // Check for being able to broadcast a single element.
9204 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9205 Mask, Subtarget, DAG))
9208 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9209 // Notably, this handles splat and partial-splat shuffles more efficiently.
9210 // However, it only makes sense if the pre-duplication shuffle simplifies
9211 // things significantly. Currently, this means we need to be able to
9212 // express the pre-duplication shuffle as an i16 shuffle.
9214 // FIXME: We should check for other patterns which can be widened into an
9215 // i16 shuffle as well.
9216 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9217 for (int i = 0; i < 16; i += 2)
9218 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9223 auto tryToWidenViaDuplication = [&]() -> SDValue {
9224 if (!canWidenViaDuplication(Mask))
9226 SmallVector<int, 4> LoInputs;
9227 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9228 [](int M) { return M >= 0 && M < 8; });
9229 std::sort(LoInputs.begin(), LoInputs.end());
9230 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9232 SmallVector<int, 4> HiInputs;
9233 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9234 [](int M) { return M >= 8; });
9235 std::sort(HiInputs.begin(), HiInputs.end());
9236 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9239 bool TargetLo = LoInputs.size() >= HiInputs.size();
9240 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9241 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9243 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9244 SmallDenseMap<int, int, 8> LaneMap;
9245 for (int I : InPlaceInputs) {
9246 PreDupI16Shuffle[I/2] = I/2;
9249 int j = TargetLo ? 0 : 4, je = j + 4;
9250 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9251 // Check if j is already a shuffle of this input. This happens when
9252 // there are two adjacent bytes after we move the low one.
9253 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9254 // If we haven't yet mapped the input, search for a slot into which
9256 while (j < je && PreDupI16Shuffle[j] != -1)
9260 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9263 // Map this input with the i16 shuffle.
9264 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9267 // Update the lane map based on the mapping we ended up with.
9268 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9270 V1 = DAG.getBitcast(
9272 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9273 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9275 // Unpack the bytes to form the i16s that will be shuffled into place.
9276 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9277 MVT::v16i8, V1, V1);
9279 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9280 for (int i = 0; i < 16; ++i)
9281 if (Mask[i] != -1) {
9282 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9283 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9284 if (PostDupI16Shuffle[i / 2] == -1)
9285 PostDupI16Shuffle[i / 2] = MappedMask;
9287 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9288 "Conflicting entrties in the original shuffle!");
9290 return DAG.getBitcast(
9292 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9293 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9295 if (SDValue V = tryToWidenViaDuplication())
9299 if (SDValue Masked =
9300 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9303 // Use dedicated unpack instructions for masks that match their pattern.
9304 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9305 0, 16, 1, 17, 2, 18, 3, 19,
9307 4, 20, 5, 21, 6, 22, 7, 23}))
9308 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9309 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9310 8, 24, 9, 25, 10, 26, 11, 27,
9312 12, 28, 13, 29, 14, 30, 15, 31}))
9313 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9315 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9316 // with PSHUFB. It is important to do this before we attempt to generate any
9317 // blends but after all of the single-input lowerings. If the single input
9318 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9319 // want to preserve that and we can DAG combine any longer sequences into
9320 // a PSHUFB in the end. But once we start blending from multiple inputs,
9321 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9322 // and there are *very* few patterns that would actually be faster than the
9323 // PSHUFB approach because of its ability to zero lanes.
9325 // FIXME: The only exceptions to the above are blends which are exact
9326 // interleavings with direct instructions supporting them. We currently don't
9327 // handle those well here.
9328 if (Subtarget->hasSSSE3()) {
9329 bool V1InUse = false;
9330 bool V2InUse = false;
9332 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9333 DAG, V1InUse, V2InUse);
9335 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9336 // do so. This avoids using them to handle blends-with-zero which is
9337 // important as a single pshufb is significantly faster for that.
9338 if (V1InUse && V2InUse) {
9339 if (Subtarget->hasSSE41())
9340 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9341 Mask, Subtarget, DAG))
9344 // We can use an unpack to do the blending rather than an or in some
9345 // cases. Even though the or may be (very minorly) more efficient, we
9346 // preference this lowering because there are common cases where part of
9347 // the complexity of the shuffles goes away when we do the final blend as
9349 // FIXME: It might be worth trying to detect if the unpack-feeding
9350 // shuffles will both be pshufb, in which case we shouldn't bother with
9352 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9353 DL, MVT::v16i8, V1, V2, Mask, DAG))
9360 // There are special ways we can lower some single-element blends.
9361 if (NumV2Elements == 1)
9362 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9363 Mask, Subtarget, DAG))
9366 if (SDValue BitBlend =
9367 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9370 // Check whether a compaction lowering can be done. This handles shuffles
9371 // which take every Nth element for some even N. See the helper function for
9374 // We special case these as they can be particularly efficiently handled with
9375 // the PACKUSB instruction on x86 and they show up in common patterns of
9376 // rearranging bytes to truncate wide elements.
9377 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9378 // NumEvenDrops is the power of two stride of the elements. Another way of
9379 // thinking about it is that we need to drop the even elements this many
9380 // times to get the original input.
9381 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9383 // First we need to zero all the dropped bytes.
9384 assert(NumEvenDrops <= 3 &&
9385 "No support for dropping even elements more than 3 times.");
9386 // We use the mask type to pick which bytes are preserved based on how many
9387 // elements are dropped.
9388 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9389 SDValue ByteClearMask = DAG.getBitcast(
9390 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9391 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9393 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9395 // Now pack things back together.
9396 V1 = DAG.getBitcast(MVT::v8i16, V1);
9397 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9398 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9399 for (int i = 1; i < NumEvenDrops; ++i) {
9400 Result = DAG.getBitcast(MVT::v8i16, Result);
9401 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9407 // Handle multi-input cases by blending single-input shuffles.
9408 if (NumV2Elements > 0)
9409 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9412 // The fallback path for single-input shuffles widens this into two v8i16
9413 // vectors with unpacks, shuffles those, and then pulls them back together
9417 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9418 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9419 for (int i = 0; i < 16; ++i)
9421 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9423 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9425 SDValue VLoHalf, VHiHalf;
9426 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9427 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9429 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9430 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9431 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9432 [](int M) { return M >= 0 && M % 2 == 1; })) {
9433 // Use a mask to drop the high bytes.
9434 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9435 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9436 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9438 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9439 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9441 // Squash the masks to point directly into VLoHalf.
9442 for (int &M : LoBlendMask)
9445 for (int &M : HiBlendMask)
9449 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9450 // VHiHalf so that we can blend them as i16s.
9451 VLoHalf = DAG.getBitcast(
9452 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9453 VHiHalf = DAG.getBitcast(
9454 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9457 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9458 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9460 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9463 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9465 /// This routine breaks down the specific type of 128-bit shuffle and
9466 /// dispatches to the lowering routines accordingly.
9467 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9468 MVT VT, const X86Subtarget *Subtarget,
9469 SelectionDAG &DAG) {
9470 switch (VT.SimpleTy) {
9472 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9474 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9476 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9478 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9480 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9482 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9485 llvm_unreachable("Unimplemented!");
9489 /// \brief Helper function to test whether a shuffle mask could be
9490 /// simplified by widening the elements being shuffled.
9492 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9493 /// leaves it in an unspecified state.
9495 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9496 /// shuffle masks. The latter have the special property of a '-2' representing
9497 /// a zero-ed lane of a vector.
9498 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9499 SmallVectorImpl<int> &WidenedMask) {
9500 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9501 // If both elements are undef, its trivial.
9502 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9503 WidenedMask.push_back(SM_SentinelUndef);
9507 // Check for an undef mask and a mask value properly aligned to fit with
9508 // a pair of values. If we find such a case, use the non-undef mask's value.
9509 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9510 WidenedMask.push_back(Mask[i + 1] / 2);
9513 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9514 WidenedMask.push_back(Mask[i] / 2);
9518 // When zeroing, we need to spread the zeroing across both lanes to widen.
9519 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9520 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9521 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9522 WidenedMask.push_back(SM_SentinelZero);
9528 // Finally check if the two mask values are adjacent and aligned with
9530 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9531 WidenedMask.push_back(Mask[i] / 2);
9535 // Otherwise we can't safely widen the elements used in this shuffle.
9538 assert(WidenedMask.size() == Mask.size() / 2 &&
9539 "Incorrect size of mask after widening the elements!");
9544 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9546 /// This routine just extracts two subvectors, shuffles them independently, and
9547 /// then concatenates them back together. This should work effectively with all
9548 /// AVX vector shuffle types.
9549 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9550 SDValue V2, ArrayRef<int> Mask,
9551 SelectionDAG &DAG) {
9552 assert(VT.getSizeInBits() >= 256 &&
9553 "Only for 256-bit or wider vector shuffles!");
9554 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9555 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9557 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9558 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9560 int NumElements = VT.getVectorNumElements();
9561 int SplitNumElements = NumElements / 2;
9562 MVT ScalarVT = VT.getScalarType();
9563 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9565 // Rather than splitting build-vectors, just build two narrower build
9566 // vectors. This helps shuffling with splats and zeros.
9567 auto SplitVector = [&](SDValue V) {
9568 while (V.getOpcode() == ISD::BITCAST)
9569 V = V->getOperand(0);
9571 MVT OrigVT = V.getSimpleValueType();
9572 int OrigNumElements = OrigVT.getVectorNumElements();
9573 int OrigSplitNumElements = OrigNumElements / 2;
9574 MVT OrigScalarVT = OrigVT.getScalarType();
9575 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9579 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9581 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9582 DAG.getIntPtrConstant(0, DL));
9583 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9584 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9587 SmallVector<SDValue, 16> LoOps, HiOps;
9588 for (int i = 0; i < OrigSplitNumElements; ++i) {
9589 LoOps.push_back(BV->getOperand(i));
9590 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9592 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9593 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9595 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9596 DAG.getBitcast(SplitVT, HiV));
9599 SDValue LoV1, HiV1, LoV2, HiV2;
9600 std::tie(LoV1, HiV1) = SplitVector(V1);
9601 std::tie(LoV2, HiV2) = SplitVector(V2);
9603 // Now create two 4-way blends of these half-width vectors.
9604 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9605 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9606 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9607 for (int i = 0; i < SplitNumElements; ++i) {
9608 int M = HalfMask[i];
9609 if (M >= NumElements) {
9610 if (M >= NumElements + SplitNumElements)
9614 V2BlendMask.push_back(M - NumElements);
9615 V1BlendMask.push_back(-1);
9616 BlendMask.push_back(SplitNumElements + i);
9617 } else if (M >= 0) {
9618 if (M >= SplitNumElements)
9622 V2BlendMask.push_back(-1);
9623 V1BlendMask.push_back(M);
9624 BlendMask.push_back(i);
9626 V2BlendMask.push_back(-1);
9627 V1BlendMask.push_back(-1);
9628 BlendMask.push_back(-1);
9632 // Because the lowering happens after all combining takes place, we need to
9633 // manually combine these blend masks as much as possible so that we create
9634 // a minimal number of high-level vector shuffle nodes.
9636 // First try just blending the halves of V1 or V2.
9637 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9638 return DAG.getUNDEF(SplitVT);
9639 if (!UseLoV2 && !UseHiV2)
9640 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9641 if (!UseLoV1 && !UseHiV1)
9642 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9644 SDValue V1Blend, V2Blend;
9645 if (UseLoV1 && UseHiV1) {
9647 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9649 // We only use half of V1 so map the usage down into the final blend mask.
9650 V1Blend = UseLoV1 ? LoV1 : HiV1;
9651 for (int i = 0; i < SplitNumElements; ++i)
9652 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9653 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9655 if (UseLoV2 && UseHiV2) {
9657 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9659 // We only use half of V2 so map the usage down into the final blend mask.
9660 V2Blend = UseLoV2 ? LoV2 : HiV2;
9661 for (int i = 0; i < SplitNumElements; ++i)
9662 if (BlendMask[i] >= SplitNumElements)
9663 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9665 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9667 SDValue Lo = HalfBlend(LoMask);
9668 SDValue Hi = HalfBlend(HiMask);
9669 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9672 /// \brief Either split a vector in halves or decompose the shuffles and the
9675 /// This is provided as a good fallback for many lowerings of non-single-input
9676 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9677 /// between splitting the shuffle into 128-bit components and stitching those
9678 /// back together vs. extracting the single-input shuffles and blending those
9680 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9681 SDValue V2, ArrayRef<int> Mask,
9682 SelectionDAG &DAG) {
9683 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9684 "lower single-input shuffles as it "
9685 "could then recurse on itself.");
9686 int Size = Mask.size();
9688 // If this can be modeled as a broadcast of two elements followed by a blend,
9689 // prefer that lowering. This is especially important because broadcasts can
9690 // often fold with memory operands.
9691 auto DoBothBroadcast = [&] {
9692 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9695 if (V2BroadcastIdx == -1)
9696 V2BroadcastIdx = M - Size;
9697 else if (M - Size != V2BroadcastIdx)
9699 } else if (M >= 0) {
9700 if (V1BroadcastIdx == -1)
9702 else if (M != V1BroadcastIdx)
9707 if (DoBothBroadcast())
9708 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9711 // If the inputs all stem from a single 128-bit lane of each input, then we
9712 // split them rather than blending because the split will decompose to
9713 // unusually few instructions.
9714 int LaneCount = VT.getSizeInBits() / 128;
9715 int LaneSize = Size / LaneCount;
9716 SmallBitVector LaneInputs[2];
9717 LaneInputs[0].resize(LaneCount, false);
9718 LaneInputs[1].resize(LaneCount, false);
9719 for (int i = 0; i < Size; ++i)
9721 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9722 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9723 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9725 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9726 // that the decomposed single-input shuffles don't end up here.
9727 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9730 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9731 /// a permutation and blend of those lanes.
9733 /// This essentially blends the out-of-lane inputs to each lane into the lane
9734 /// from a permuted copy of the vector. This lowering strategy results in four
9735 /// instructions in the worst case for a single-input cross lane shuffle which
9736 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9737 /// of. Special cases for each particular shuffle pattern should be handled
9738 /// prior to trying this lowering.
9739 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9740 SDValue V1, SDValue V2,
9742 SelectionDAG &DAG) {
9743 // FIXME: This should probably be generalized for 512-bit vectors as well.
9744 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9745 int LaneSize = Mask.size() / 2;
9747 // If there are only inputs from one 128-bit lane, splitting will in fact be
9748 // less expensive. The flags track whether the given lane contains an element
9749 // that crosses to another lane.
9750 bool LaneCrossing[2] = {false, false};
9751 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9752 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9753 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9754 if (!LaneCrossing[0] || !LaneCrossing[1])
9755 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9757 if (isSingleInputShuffleMask(Mask)) {
9758 SmallVector<int, 32> FlippedBlendMask;
9759 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9760 FlippedBlendMask.push_back(
9761 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9763 : Mask[i] % LaneSize +
9764 (i / LaneSize) * LaneSize + Size));
9766 // Flip the vector, and blend the results which should now be in-lane. The
9767 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9768 // 5 for the high source. The value 3 selects the high half of source 2 and
9769 // the value 2 selects the low half of source 2. We only use source 2 to
9770 // allow folding it into a memory operand.
9771 unsigned PERMMask = 3 | 2 << 4;
9772 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9773 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9774 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9777 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9778 // will be handled by the above logic and a blend of the results, much like
9779 // other patterns in AVX.
9780 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9783 /// \brief Handle lowering 2-lane 128-bit shuffles.
9784 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9785 SDValue V2, ArrayRef<int> Mask,
9786 const X86Subtarget *Subtarget,
9787 SelectionDAG &DAG) {
9788 // TODO: If minimizing size and one of the inputs is a zero vector and the
9789 // the zero vector has only one use, we could use a VPERM2X128 to save the
9790 // instruction bytes needed to explicitly generate the zero vector.
9792 // Blends are faster and handle all the non-lane-crossing cases.
9793 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9797 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9798 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9800 // If either input operand is a zero vector, use VPERM2X128 because its mask
9801 // allows us to replace the zero input with an implicit zero.
9802 if (!IsV1Zero && !IsV2Zero) {
9803 // Check for patterns which can be matched with a single insert of a 128-bit
9805 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9806 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9807 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9808 VT.getVectorNumElements() / 2);
9809 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9810 DAG.getIntPtrConstant(0, DL));
9811 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9812 OnlyUsesV1 ? V1 : V2,
9813 DAG.getIntPtrConstant(0, DL));
9814 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9818 // Otherwise form a 128-bit permutation. After accounting for undefs,
9819 // convert the 64-bit shuffle mask selection values into 128-bit
9820 // selection bits by dividing the indexes by 2 and shifting into positions
9821 // defined by a vperm2*128 instruction's immediate control byte.
9823 // The immediate permute control byte looks like this:
9824 // [1:0] - select 128 bits from sources for low half of destination
9826 // [3] - zero low half of destination
9827 // [5:4] - select 128 bits from sources for high half of destination
9829 // [7] - zero high half of destination
9831 int MaskLO = Mask[0];
9832 if (MaskLO == SM_SentinelUndef)
9833 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9835 int MaskHI = Mask[2];
9836 if (MaskHI == SM_SentinelUndef)
9837 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9839 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9841 // If either input is a zero vector, replace it with an undef input.
9842 // Shuffle mask values < 4 are selecting elements of V1.
9843 // Shuffle mask values >= 4 are selecting elements of V2.
9844 // Adjust each half of the permute mask by clearing the half that was
9845 // selecting the zero vector and setting the zero mask bit.
9847 V1 = DAG.getUNDEF(VT);
9849 PermMask = (PermMask & 0xf0) | 0x08;
9851 PermMask = (PermMask & 0x0f) | 0x80;
9854 V2 = DAG.getUNDEF(VT);
9856 PermMask = (PermMask & 0xf0) | 0x08;
9858 PermMask = (PermMask & 0x0f) | 0x80;
9861 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9862 DAG.getConstant(PermMask, DL, MVT::i8));
9865 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9866 /// shuffling each lane.
9868 /// This will only succeed when the result of fixing the 128-bit lanes results
9869 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9870 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9871 /// the lane crosses early and then use simpler shuffles within each lane.
9873 /// FIXME: It might be worthwhile at some point to support this without
9874 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9875 /// in x86 only floating point has interesting non-repeating shuffles, and even
9876 /// those are still *marginally* more expensive.
9877 static SDValue lowerVectorShuffleByMerging128BitLanes(
9878 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9879 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9880 assert(!isSingleInputShuffleMask(Mask) &&
9881 "This is only useful with multiple inputs.");
9883 int Size = Mask.size();
9884 int LaneSize = 128 / VT.getScalarSizeInBits();
9885 int NumLanes = Size / LaneSize;
9886 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9888 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9889 // check whether the in-128-bit lane shuffles share a repeating pattern.
9890 SmallVector<int, 4> Lanes;
9891 Lanes.resize(NumLanes, -1);
9892 SmallVector<int, 4> InLaneMask;
9893 InLaneMask.resize(LaneSize, -1);
9894 for (int i = 0; i < Size; ++i) {
9898 int j = i / LaneSize;
9901 // First entry we've seen for this lane.
9902 Lanes[j] = Mask[i] / LaneSize;
9903 } else if (Lanes[j] != Mask[i] / LaneSize) {
9904 // This doesn't match the lane selected previously!
9908 // Check that within each lane we have a consistent shuffle mask.
9909 int k = i % LaneSize;
9910 if (InLaneMask[k] < 0) {
9911 InLaneMask[k] = Mask[i] % LaneSize;
9912 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9913 // This doesn't fit a repeating in-lane mask.
9918 // First shuffle the lanes into place.
9919 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9920 VT.getSizeInBits() / 64);
9921 SmallVector<int, 8> LaneMask;
9922 LaneMask.resize(NumLanes * 2, -1);
9923 for (int i = 0; i < NumLanes; ++i)
9924 if (Lanes[i] >= 0) {
9925 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9926 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9929 V1 = DAG.getBitcast(LaneVT, V1);
9930 V2 = DAG.getBitcast(LaneVT, V2);
9931 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9933 // Cast it back to the type we actually want.
9934 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
9936 // Now do a simple shuffle that isn't lane crossing.
9937 SmallVector<int, 8> NewMask;
9938 NewMask.resize(Size, -1);
9939 for (int i = 0; i < Size; ++i)
9941 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9942 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9943 "Must not introduce lane crosses at this point!");
9945 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9948 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9951 /// This returns true if the elements from a particular input are already in the
9952 /// slot required by the given mask and require no permutation.
9953 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9954 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9955 int Size = Mask.size();
9956 for (int i = 0; i < Size; ++i)
9957 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9963 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
9964 ArrayRef<int> Mask, SDValue V1,
9965 SDValue V2, SelectionDAG &DAG) {
9967 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
9968 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
9969 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
9970 int NumElts = VT.getVectorNumElements();
9971 bool ShufpdMask = true;
9972 bool CommutableMask = true;
9973 unsigned Immediate = 0;
9974 for (int i = 0; i < NumElts; ++i) {
9977 int Val = (i & 6) + NumElts * (i & 1);
9978 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
9979 if (Mask[i] < Val || Mask[i] > Val + 1)
9981 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
9982 CommutableMask = false;
9983 Immediate |= (Mask[i] % 2) << i;
9986 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
9987 DAG.getConstant(Immediate, DL, MVT::i8));
9989 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
9990 DAG.getConstant(Immediate, DL, MVT::i8));
9994 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9996 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9997 /// isn't available.
9998 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9999 const X86Subtarget *Subtarget,
10000 SelectionDAG &DAG) {
10002 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10003 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10004 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10005 ArrayRef<int> Mask = SVOp->getMask();
10006 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10008 SmallVector<int, 4> WidenedMask;
10009 if (canWidenShuffleElements(Mask, WidenedMask))
10010 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10013 if (isSingleInputShuffleMask(Mask)) {
10014 // Check for being able to broadcast a single element.
10015 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10016 Mask, Subtarget, DAG))
10019 // Use low duplicate instructions for masks that match their pattern.
10020 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10021 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10023 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10024 // Non-half-crossing single input shuffles can be lowerid with an
10025 // interleaved permutation.
10026 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10027 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10028 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10029 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10032 // With AVX2 we have direct support for this permutation.
10033 if (Subtarget->hasAVX2())
10034 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10035 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10037 // Otherwise, fall back.
10038 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10042 // X86 has dedicated unpack instructions that can handle specific blend
10043 // operations: UNPCKH and UNPCKL.
10044 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10045 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10046 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10047 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10048 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10049 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
10050 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10051 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
10053 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10057 // Check if the blend happens to exactly fit that of SHUFPD.
10059 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10062 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10063 // shuffle. However, if we have AVX2 and either inputs are already in place,
10064 // we will be able to shuffle even across lanes the other input in a single
10065 // instruction so skip this pattern.
10066 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10067 isShuffleMaskInputInPlace(1, Mask))))
10068 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10069 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10072 // If we have AVX2 then we always want to lower with a blend because an v4 we
10073 // can fully permute the elements.
10074 if (Subtarget->hasAVX2())
10075 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10078 // Otherwise fall back on generic lowering.
10079 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10082 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10084 /// This routine is only called when we have AVX2 and thus a reasonable
10085 /// instruction set for v4i64 shuffling..
10086 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10087 const X86Subtarget *Subtarget,
10088 SelectionDAG &DAG) {
10090 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10091 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10092 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10093 ArrayRef<int> Mask = SVOp->getMask();
10094 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10095 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10097 SmallVector<int, 4> WidenedMask;
10098 if (canWidenShuffleElements(Mask, WidenedMask))
10099 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10102 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10106 // Check for being able to broadcast a single element.
10107 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10108 Mask, Subtarget, DAG))
10111 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10112 // use lower latency instructions that will operate on both 128-bit lanes.
10113 SmallVector<int, 2> RepeatedMask;
10114 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10115 if (isSingleInputShuffleMask(Mask)) {
10116 int PSHUFDMask[] = {-1, -1, -1, -1};
10117 for (int i = 0; i < 2; ++i)
10118 if (RepeatedMask[i] >= 0) {
10119 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10120 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10122 return DAG.getBitcast(
10124 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10125 DAG.getBitcast(MVT::v8i32, V1),
10126 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10130 // AVX2 provides a direct instruction for permuting a single input across
10132 if (isSingleInputShuffleMask(Mask))
10133 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10134 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10136 // Try to use shift instructions.
10137 if (SDValue Shift =
10138 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10141 // Use dedicated unpack instructions for masks that match their pattern.
10142 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10143 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10144 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10145 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10146 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10147 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
10148 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10149 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
10151 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10152 // shuffle. However, if we have AVX2 and either inputs are already in place,
10153 // we will be able to shuffle even across lanes the other input in a single
10154 // instruction so skip this pattern.
10155 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10156 isShuffleMaskInputInPlace(1, Mask))))
10157 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10158 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10161 // Otherwise fall back on generic blend lowering.
10162 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10166 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10168 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10169 /// isn't available.
10170 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10171 const X86Subtarget *Subtarget,
10172 SelectionDAG &DAG) {
10174 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10175 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10176 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10177 ArrayRef<int> Mask = SVOp->getMask();
10178 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10180 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10184 // Check for being able to broadcast a single element.
10185 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10186 Mask, Subtarget, DAG))
10189 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10190 // options to efficiently lower the shuffle.
10191 SmallVector<int, 4> RepeatedMask;
10192 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10193 assert(RepeatedMask.size() == 4 &&
10194 "Repeated masks must be half the mask width!");
10196 // Use even/odd duplicate instructions for masks that match their pattern.
10197 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10198 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10199 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10200 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10202 if (isSingleInputShuffleMask(Mask))
10203 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10204 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10206 // Use dedicated unpack instructions for masks that match their pattern.
10207 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10208 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10209 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10210 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10211 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10212 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
10213 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10214 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
10216 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10217 // have already handled any direct blends. We also need to squash the
10218 // repeated mask into a simulated v4f32 mask.
10219 for (int i = 0; i < 4; ++i)
10220 if (RepeatedMask[i] >= 8)
10221 RepeatedMask[i] -= 4;
10222 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10225 // If we have a single input shuffle with different shuffle patterns in the
10226 // two 128-bit lanes use the variable mask to VPERMILPS.
10227 if (isSingleInputShuffleMask(Mask)) {
10228 SDValue VPermMask[8];
10229 for (int i = 0; i < 8; ++i)
10230 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10231 : DAG.getConstant(Mask[i], DL, MVT::i32);
10232 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10233 return DAG.getNode(
10234 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10235 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10237 if (Subtarget->hasAVX2())
10238 return DAG.getNode(
10239 X86ISD::VPERMV, DL, MVT::v8f32,
10240 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10241 MVT::v8i32, VPermMask)),
10244 // Otherwise, fall back.
10245 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10249 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10251 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10252 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10255 // If we have AVX2 then we always want to lower with a blend because at v8 we
10256 // can fully permute the elements.
10257 if (Subtarget->hasAVX2())
10258 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10261 // Otherwise fall back on generic lowering.
10262 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10265 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10267 /// This routine is only called when we have AVX2 and thus a reasonable
10268 /// instruction set for v8i32 shuffling..
10269 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10270 const X86Subtarget *Subtarget,
10271 SelectionDAG &DAG) {
10273 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10274 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10275 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10276 ArrayRef<int> Mask = SVOp->getMask();
10277 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10278 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10280 // Whenever we can lower this as a zext, that instruction is strictly faster
10281 // than any alternative. It also allows us to fold memory operands into the
10282 // shuffle in many cases.
10283 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10284 Mask, Subtarget, DAG))
10287 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10291 // Check for being able to broadcast a single element.
10292 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10293 Mask, Subtarget, DAG))
10296 // If the shuffle mask is repeated in each 128-bit lane we can use more
10297 // efficient instructions that mirror the shuffles across the two 128-bit
10299 SmallVector<int, 4> RepeatedMask;
10300 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10301 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10302 if (isSingleInputShuffleMask(Mask))
10303 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10304 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10306 // Use dedicated unpack instructions for masks that match their pattern.
10307 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10308 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10309 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10310 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10311 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10312 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10313 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10314 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10317 // Try to use shift instructions.
10318 if (SDValue Shift =
10319 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10322 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10323 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10326 // If the shuffle patterns aren't repeated but it is a single input, directly
10327 // generate a cross-lane VPERMD instruction.
10328 if (isSingleInputShuffleMask(Mask)) {
10329 SDValue VPermMask[8];
10330 for (int i = 0; i < 8; ++i)
10331 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10332 : DAG.getConstant(Mask[i], DL, MVT::i32);
10333 return DAG.getNode(
10334 X86ISD::VPERMV, DL, MVT::v8i32,
10335 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10338 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10340 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10341 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10344 // Otherwise fall back on generic blend lowering.
10345 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10349 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10351 /// This routine is only called when we have AVX2 and thus a reasonable
10352 /// instruction set for v16i16 shuffling..
10353 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10354 const X86Subtarget *Subtarget,
10355 SelectionDAG &DAG) {
10357 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10358 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10359 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10360 ArrayRef<int> Mask = SVOp->getMask();
10361 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10362 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10364 // Whenever we can lower this as a zext, that instruction is strictly faster
10365 // than any alternative. It also allows us to fold memory operands into the
10366 // shuffle in many cases.
10367 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10368 Mask, Subtarget, DAG))
10371 // Check for being able to broadcast a single element.
10372 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10373 Mask, Subtarget, DAG))
10376 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10380 // Use dedicated unpack instructions for masks that match their pattern.
10381 if (isShuffleEquivalent(V1, V2, Mask,
10382 {// First 128-bit lane:
10383 0, 16, 1, 17, 2, 18, 3, 19,
10384 // Second 128-bit lane:
10385 8, 24, 9, 25, 10, 26, 11, 27}))
10386 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10387 if (isShuffleEquivalent(V1, V2, Mask,
10388 {// First 128-bit lane:
10389 4, 20, 5, 21, 6, 22, 7, 23,
10390 // Second 128-bit lane:
10391 12, 28, 13, 29, 14, 30, 15, 31}))
10392 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10394 // Try to use shift instructions.
10395 if (SDValue Shift =
10396 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10399 // Try to use byte rotation instructions.
10400 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10401 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10404 if (isSingleInputShuffleMask(Mask)) {
10405 // There are no generalized cross-lane shuffle operations available on i16
10407 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10408 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10411 SmallVector<int, 8> RepeatedMask;
10412 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10413 // As this is a single-input shuffle, the repeated mask should be
10414 // a strictly valid v8i16 mask that we can pass through to the v8i16
10415 // lowering to handle even the v16 case.
10416 return lowerV8I16GeneralSingleInputVectorShuffle(
10417 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10420 SDValue PSHUFBMask[32];
10421 for (int i = 0; i < 16; ++i) {
10422 if (Mask[i] == -1) {
10423 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10427 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10428 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10429 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10430 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10432 return DAG.getBitcast(MVT::v16i16,
10433 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10434 DAG.getBitcast(MVT::v32i8, V1),
10435 DAG.getNode(ISD::BUILD_VECTOR, DL,
10436 MVT::v32i8, PSHUFBMask)));
10439 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10441 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10442 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10445 // Otherwise fall back on generic lowering.
10446 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10449 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10451 /// This routine is only called when we have AVX2 and thus a reasonable
10452 /// instruction set for v32i8 shuffling..
10453 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10454 const X86Subtarget *Subtarget,
10455 SelectionDAG &DAG) {
10457 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10458 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10459 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10460 ArrayRef<int> Mask = SVOp->getMask();
10461 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10462 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10464 // Whenever we can lower this as a zext, that instruction is strictly faster
10465 // than any alternative. It also allows us to fold memory operands into the
10466 // shuffle in many cases.
10467 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10468 Mask, Subtarget, DAG))
10471 // Check for being able to broadcast a single element.
10472 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10473 Mask, Subtarget, DAG))
10476 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10480 // Use dedicated unpack instructions for masks that match their pattern.
10481 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10483 if (isShuffleEquivalent(
10485 {// First 128-bit lane:
10486 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10487 // Second 128-bit lane:
10488 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10489 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10490 if (isShuffleEquivalent(
10492 {// First 128-bit lane:
10493 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10494 // Second 128-bit lane:
10495 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10496 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10498 // Try to use shift instructions.
10499 if (SDValue Shift =
10500 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10503 // Try to use byte rotation instructions.
10504 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10505 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10508 if (isSingleInputShuffleMask(Mask)) {
10509 // There are no generalized cross-lane shuffle operations available on i8
10511 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10512 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10515 SDValue PSHUFBMask[32];
10516 for (int i = 0; i < 32; ++i)
10519 ? DAG.getUNDEF(MVT::i8)
10520 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10523 return DAG.getNode(
10524 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10525 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10528 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10530 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10531 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10534 // Otherwise fall back on generic lowering.
10535 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10538 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10540 /// This routine either breaks down the specific type of a 256-bit x86 vector
10541 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10542 /// together based on the available instructions.
10543 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10544 MVT VT, const X86Subtarget *Subtarget,
10545 SelectionDAG &DAG) {
10547 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10548 ArrayRef<int> Mask = SVOp->getMask();
10550 // If we have a single input to the zero element, insert that into V1 if we
10551 // can do so cheaply.
10552 int NumElts = VT.getVectorNumElements();
10553 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10554 return M >= NumElts;
10557 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10558 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10559 DL, VT, V1, V2, Mask, Subtarget, DAG))
10562 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10563 // check for those subtargets here and avoid much of the subtarget querying in
10564 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10565 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10566 // floating point types there eventually, just immediately cast everything to
10567 // a float and operate entirely in that domain.
10568 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10569 int ElementBits = VT.getScalarSizeInBits();
10570 if (ElementBits < 32)
10571 // No floating point type available, decompose into 128-bit vectors.
10572 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10574 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10575 VT.getVectorNumElements());
10576 V1 = DAG.getBitcast(FpVT, V1);
10577 V2 = DAG.getBitcast(FpVT, V2);
10578 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10581 switch (VT.SimpleTy) {
10583 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10585 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10587 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10589 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10591 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10593 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10596 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10600 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10601 ArrayRef<int> Mask, SDValue V1,
10602 SDValue V2, SelectionDAG &DAG) {
10604 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10606 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10607 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10609 SmallVector<SDValue, 32> VPermMask;
10610 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i)
10611 VPermMask.push_back(Mask[i] < 0 ? DAG.getUNDEF(MaskEltVT) :
10612 DAG.getConstant(Mask[i], DL, MaskEltVT));
10613 SDValue MaskNode = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecVT,
10615 if (isSingleInputShuffleMask(Mask))
10616 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10618 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10621 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10622 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10623 const X86Subtarget *Subtarget,
10624 SelectionDAG &DAG) {
10626 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10627 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10628 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10629 ArrayRef<int> Mask = SVOp->getMask();
10630 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10632 if (SDValue Unpck =
10633 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10636 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10639 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10640 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10641 const X86Subtarget *Subtarget,
10642 SelectionDAG &DAG) {
10644 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10645 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10646 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10647 ArrayRef<int> Mask = SVOp->getMask();
10648 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10650 if (SDValue Unpck =
10651 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10654 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10657 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10658 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10659 const X86Subtarget *Subtarget,
10660 SelectionDAG &DAG) {
10662 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10663 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10664 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10665 ArrayRef<int> Mask = SVOp->getMask();
10666 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10668 if (SDValue Unpck =
10669 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10672 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10675 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10676 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10677 const X86Subtarget *Subtarget,
10678 SelectionDAG &DAG) {
10680 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10681 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10682 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10683 ArrayRef<int> Mask = SVOp->getMask();
10684 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10686 if (SDValue Unpck =
10687 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
10690 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
10693 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10694 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10695 const X86Subtarget *Subtarget,
10696 SelectionDAG &DAG) {
10698 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10699 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10700 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10701 ArrayRef<int> Mask = SVOp->getMask();
10702 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10703 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10705 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
10708 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10709 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10710 const X86Subtarget *Subtarget,
10711 SelectionDAG &DAG) {
10713 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10714 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10715 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10716 ArrayRef<int> Mask = SVOp->getMask();
10717 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10718 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10720 // FIXME: Implement direct support for this type!
10721 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10724 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10726 /// This routine either breaks down the specific type of a 512-bit x86 vector
10727 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10728 /// together based on the available instructions.
10729 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10730 MVT VT, const X86Subtarget *Subtarget,
10731 SelectionDAG &DAG) {
10733 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10734 ArrayRef<int> Mask = SVOp->getMask();
10735 assert(Subtarget->hasAVX512() &&
10736 "Cannot lower 512-bit vectors w/ basic ISA!");
10738 // Check for being able to broadcast a single element.
10739 if (SDValue Broadcast =
10740 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10743 // Dispatch to each element type for lowering. If we don't have supprot for
10744 // specific element type shuffles at 512 bits, immediately split them and
10745 // lower them. Each lowering routine of a given type is allowed to assume that
10746 // the requisite ISA extensions for that element type are available.
10747 switch (VT.SimpleTy) {
10749 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10751 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10753 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10755 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10757 if (Subtarget->hasBWI())
10758 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10761 if (Subtarget->hasBWI())
10762 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10766 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10769 // Otherwise fall back on splitting.
10770 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10773 // Lower vXi1 vector shuffles.
10774 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
10775 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
10776 // vector, shuffle and then truncate it back.
10777 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10778 MVT VT, const X86Subtarget *Subtarget,
10779 SelectionDAG &DAG) {
10781 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10782 ArrayRef<int> Mask = SVOp->getMask();
10783 assert(Subtarget->hasAVX512() &&
10784 "Cannot lower 512-bit vectors w/o basic ISA!");
10786 switch (VT.SimpleTy) {
10788 assert(false && "Expected a vector of i1 elements");
10791 ExtVT = MVT::v2i64;
10794 ExtVT = MVT::v4i32;
10797 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
10800 ExtVT = MVT::v16i32;
10803 ExtVT = MVT::v32i16;
10806 ExtVT = MVT::v64i8;
10810 if (ISD::isBuildVectorAllZeros(V1.getNode()))
10811 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10812 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
10813 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10815 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
10818 V2 = DAG.getUNDEF(ExtVT);
10819 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
10820 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10821 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
10822 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10824 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
10825 return DAG.getNode(ISD::TRUNCATE, DL, VT,
10826 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
10828 /// \brief Top-level lowering for x86 vector shuffles.
10830 /// This handles decomposition, canonicalization, and lowering of all x86
10831 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10832 /// above in helper routines. The canonicalization attempts to widen shuffles
10833 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10834 /// s.t. only one of the two inputs needs to be tested, etc.
10835 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10836 SelectionDAG &DAG) {
10837 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10838 ArrayRef<int> Mask = SVOp->getMask();
10839 SDValue V1 = Op.getOperand(0);
10840 SDValue V2 = Op.getOperand(1);
10841 MVT VT = Op.getSimpleValueType();
10842 int NumElements = VT.getVectorNumElements();
10844 bool Is1BitVector = (VT.getScalarType() == MVT::i1);
10846 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
10847 "Can't lower MMX shuffles");
10849 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10850 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10851 if (V1IsUndef && V2IsUndef)
10852 return DAG.getUNDEF(VT);
10854 // When we create a shuffle node we put the UNDEF node to second operand,
10855 // but in some cases the first operand may be transformed to UNDEF.
10856 // In this case we should just commute the node.
10858 return DAG.getCommutedVectorShuffle(*SVOp);
10860 // Check for non-undef masks pointing at an undef vector and make the masks
10861 // undef as well. This makes it easier to match the shuffle based solely on
10865 if (M >= NumElements) {
10866 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10867 for (int &M : NewMask)
10868 if (M >= NumElements)
10870 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10873 // We actually see shuffles that are entirely re-arrangements of a set of
10874 // zero inputs. This mostly happens while decomposing complex shuffles into
10875 // simple ones. Directly lower these as a buildvector of zeros.
10876 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10877 if (Zeroable.all())
10878 return getZeroVector(VT, Subtarget, DAG, dl);
10880 // Try to collapse shuffles into using a vector type with fewer elements but
10881 // wider element types. We cap this to not form integers or floating point
10882 // elements wider than 64 bits, but it might be interesting to form i128
10883 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10884 SmallVector<int, 16> WidenedMask;
10885 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
10886 canWidenShuffleElements(Mask, WidenedMask)) {
10887 MVT NewEltVT = VT.isFloatingPoint()
10888 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10889 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10890 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10891 // Make sure that the new vector type is legal. For example, v2f64 isn't
10893 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10894 V1 = DAG.getBitcast(NewVT, V1);
10895 V2 = DAG.getBitcast(NewVT, V2);
10896 return DAG.getBitcast(
10897 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10901 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10902 for (int M : SVOp->getMask())
10904 ++NumUndefElements;
10905 else if (M < NumElements)
10910 // Commute the shuffle as needed such that more elements come from V1 than
10911 // V2. This allows us to match the shuffle pattern strictly on how many
10912 // elements come from V1 without handling the symmetric cases.
10913 if (NumV2Elements > NumV1Elements)
10914 return DAG.getCommutedVectorShuffle(*SVOp);
10916 // When the number of V1 and V2 elements are the same, try to minimize the
10917 // number of uses of V2 in the low half of the vector. When that is tied,
10918 // ensure that the sum of indices for V1 is equal to or lower than the sum
10919 // indices for V2. When those are equal, try to ensure that the number of odd
10920 // indices for V1 is lower than the number of odd indices for V2.
10921 if (NumV1Elements == NumV2Elements) {
10922 int LowV1Elements = 0, LowV2Elements = 0;
10923 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10924 if (M >= NumElements)
10928 if (LowV2Elements > LowV1Elements) {
10929 return DAG.getCommutedVectorShuffle(*SVOp);
10930 } else if (LowV2Elements == LowV1Elements) {
10931 int SumV1Indices = 0, SumV2Indices = 0;
10932 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10933 if (SVOp->getMask()[i] >= NumElements)
10935 else if (SVOp->getMask()[i] >= 0)
10937 if (SumV2Indices < SumV1Indices) {
10938 return DAG.getCommutedVectorShuffle(*SVOp);
10939 } else if (SumV2Indices == SumV1Indices) {
10940 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10941 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10942 if (SVOp->getMask()[i] >= NumElements)
10943 NumV2OddIndices += i % 2;
10944 else if (SVOp->getMask()[i] >= 0)
10945 NumV1OddIndices += i % 2;
10946 if (NumV2OddIndices < NumV1OddIndices)
10947 return DAG.getCommutedVectorShuffle(*SVOp);
10952 // For each vector width, delegate to a specialized lowering routine.
10953 if (VT.getSizeInBits() == 128)
10954 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10956 if (VT.getSizeInBits() == 256)
10957 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10959 if (VT.getSizeInBits() == 512)
10960 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10963 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10964 llvm_unreachable("Unimplemented!");
10967 // This function assumes its argument is a BUILD_VECTOR of constants or
10968 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10970 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10971 unsigned &MaskValue) {
10973 unsigned NumElems = BuildVector->getNumOperands();
10974 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10975 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10976 unsigned NumElemsInLane = NumElems / NumLanes;
10978 // Blend for v16i16 should be symmetric for the both lanes.
10979 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10980 SDValue EltCond = BuildVector->getOperand(i);
10981 SDValue SndLaneEltCond =
10982 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10984 int Lane1Cond = -1, Lane2Cond = -1;
10985 if (isa<ConstantSDNode>(EltCond))
10986 Lane1Cond = !isZero(EltCond);
10987 if (isa<ConstantSDNode>(SndLaneEltCond))
10988 Lane2Cond = !isZero(SndLaneEltCond);
10990 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10991 // Lane1Cond != 0, means we want the first argument.
10992 // Lane1Cond == 0, means we want the second argument.
10993 // The encoding of this argument is 0 for the first argument, 1
10994 // for the second. Therefore, invert the condition.
10995 MaskValue |= !Lane1Cond << i;
10996 else if (Lane1Cond < 0)
10997 MaskValue |= !Lane2Cond << i;
11004 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11005 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11006 const X86Subtarget *Subtarget,
11007 SelectionDAG &DAG) {
11008 SDValue Cond = Op.getOperand(0);
11009 SDValue LHS = Op.getOperand(1);
11010 SDValue RHS = Op.getOperand(2);
11012 MVT VT = Op.getSimpleValueType();
11014 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11016 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11018 // Only non-legal VSELECTs reach this lowering, convert those into generic
11019 // shuffles and re-use the shuffle lowering path for blends.
11020 SmallVector<int, 32> Mask;
11021 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11022 SDValue CondElt = CondBV->getOperand(i);
11024 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11026 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11029 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11030 // A vselect where all conditions and data are constants can be optimized into
11031 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11032 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11033 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11034 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11037 // Try to lower this to a blend-style vector shuffle. This can handle all
11038 // constant condition cases.
11039 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11042 // Variable blends are only legal from SSE4.1 onward.
11043 if (!Subtarget->hasSSE41())
11046 // Only some types will be legal on some subtargets. If we can emit a legal
11047 // VSELECT-matching blend, return Op, and but if we need to expand, return
11049 switch (Op.getSimpleValueType().SimpleTy) {
11051 // Most of the vector types have blends past SSE4.1.
11055 // The byte blends for AVX vectors were introduced only in AVX2.
11056 if (Subtarget->hasAVX2())
11063 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11064 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11067 // FIXME: We should custom lower this by fixing the condition and using i8
11073 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11074 MVT VT = Op.getSimpleValueType();
11077 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11080 if (VT.getSizeInBits() == 8) {
11081 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11082 Op.getOperand(0), Op.getOperand(1));
11083 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11084 DAG.getValueType(VT));
11085 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11088 if (VT.getSizeInBits() == 16) {
11089 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11090 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11092 return DAG.getNode(
11093 ISD::TRUNCATE, dl, MVT::i16,
11094 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11095 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11096 Op.getOperand(1)));
11097 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11098 Op.getOperand(0), Op.getOperand(1));
11099 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11100 DAG.getValueType(VT));
11101 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11104 if (VT == MVT::f32) {
11105 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11106 // the result back to FR32 register. It's only worth matching if the
11107 // result has a single use which is a store or a bitcast to i32. And in
11108 // the case of a store, it's not worth it if the index is a constant 0,
11109 // because a MOVSSmr can be used instead, which is smaller and faster.
11110 if (!Op.hasOneUse())
11112 SDNode *User = *Op.getNode()->use_begin();
11113 if ((User->getOpcode() != ISD::STORE ||
11114 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11115 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11116 (User->getOpcode() != ISD::BITCAST ||
11117 User->getValueType(0) != MVT::i32))
11119 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11120 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11122 return DAG.getBitcast(MVT::f32, Extract);
11125 if (VT == MVT::i32 || VT == MVT::i64) {
11126 // ExtractPS/pextrq works with constant index.
11127 if (isa<ConstantSDNode>(Op.getOperand(1)))
11133 /// Extract one bit from mask vector, like v16i1 or v8i1.
11134 /// AVX-512 feature.
11136 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11137 SDValue Vec = Op.getOperand(0);
11139 MVT VecVT = Vec.getSimpleValueType();
11140 SDValue Idx = Op.getOperand(1);
11141 MVT EltVT = Op.getSimpleValueType();
11143 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11144 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11145 "Unexpected vector type in ExtractBitFromMaskVector");
11147 // variable index can't be handled in mask registers,
11148 // extend vector to VR512
11149 if (!isa<ConstantSDNode>(Idx)) {
11150 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11151 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11152 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11153 ExtVT.getVectorElementType(), Ext, Idx);
11154 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11157 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11158 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11159 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11160 rc = getRegClassFor(MVT::v16i1);
11161 unsigned MaxSift = rc->getSize()*8 - 1;
11162 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11163 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11164 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11165 DAG.getConstant(MaxSift, dl, MVT::i8));
11166 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11167 DAG.getIntPtrConstant(0, dl));
11171 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11172 SelectionDAG &DAG) const {
11174 SDValue Vec = Op.getOperand(0);
11175 MVT VecVT = Vec.getSimpleValueType();
11176 SDValue Idx = Op.getOperand(1);
11178 if (Op.getSimpleValueType() == MVT::i1)
11179 return ExtractBitFromMaskVector(Op, DAG);
11181 if (!isa<ConstantSDNode>(Idx)) {
11182 if (VecVT.is512BitVector() ||
11183 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11184 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11187 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11188 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11189 MaskEltVT.getSizeInBits());
11191 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11192 auto PtrVT = getPointerTy(DAG.getDataLayout());
11193 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11194 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11195 DAG.getConstant(0, dl, PtrVT));
11196 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11197 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11198 DAG.getConstant(0, dl, PtrVT));
11203 // If this is a 256-bit vector result, first extract the 128-bit vector and
11204 // then extract the element from the 128-bit vector.
11205 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11207 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11208 // Get the 128-bit vector.
11209 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11210 MVT EltVT = VecVT.getVectorElementType();
11212 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11214 //if (IdxVal >= NumElems/2)
11215 // IdxVal -= NumElems/2;
11216 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11217 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11218 DAG.getConstant(IdxVal, dl, MVT::i32));
11221 assert(VecVT.is128BitVector() && "Unexpected vector length");
11223 if (Subtarget->hasSSE41())
11224 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11227 MVT VT = Op.getSimpleValueType();
11228 // TODO: handle v16i8.
11229 if (VT.getSizeInBits() == 16) {
11230 SDValue Vec = Op.getOperand(0);
11231 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11233 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11234 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11235 DAG.getBitcast(MVT::v4i32, Vec),
11236 Op.getOperand(1)));
11237 // Transform it so it match pextrw which produces a 32-bit result.
11238 MVT EltVT = MVT::i32;
11239 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11240 Op.getOperand(0), Op.getOperand(1));
11241 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11242 DAG.getValueType(VT));
11243 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11246 if (VT.getSizeInBits() == 32) {
11247 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11251 // SHUFPS the element to the lowest double word, then movss.
11252 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11253 MVT VVT = Op.getOperand(0).getSimpleValueType();
11254 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11255 DAG.getUNDEF(VVT), Mask);
11256 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11257 DAG.getIntPtrConstant(0, dl));
11260 if (VT.getSizeInBits() == 64) {
11261 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11262 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11263 // to match extract_elt for f64.
11264 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11268 // UNPCKHPD the element to the lowest double word, then movsd.
11269 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11270 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11271 int Mask[2] = { 1, -1 };
11272 MVT VVT = Op.getOperand(0).getSimpleValueType();
11273 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11274 DAG.getUNDEF(VVT), Mask);
11275 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11276 DAG.getIntPtrConstant(0, dl));
11282 /// Insert one bit to mask vector, like v16i1 or v8i1.
11283 /// AVX-512 feature.
11285 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11287 SDValue Vec = Op.getOperand(0);
11288 SDValue Elt = Op.getOperand(1);
11289 SDValue Idx = Op.getOperand(2);
11290 MVT VecVT = Vec.getSimpleValueType();
11292 if (!isa<ConstantSDNode>(Idx)) {
11293 // Non constant index. Extend source and destination,
11294 // insert element and then truncate the result.
11295 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11296 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11297 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11298 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11299 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11300 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11303 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11304 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11306 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11307 DAG.getConstant(IdxVal, dl, MVT::i8));
11308 if (Vec.getOpcode() == ISD::UNDEF)
11310 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11313 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11314 SelectionDAG &DAG) const {
11315 MVT VT = Op.getSimpleValueType();
11316 MVT EltVT = VT.getVectorElementType();
11318 if (EltVT == MVT::i1)
11319 return InsertBitToMaskVector(Op, DAG);
11322 SDValue N0 = Op.getOperand(0);
11323 SDValue N1 = Op.getOperand(1);
11324 SDValue N2 = Op.getOperand(2);
11325 if (!isa<ConstantSDNode>(N2))
11327 auto *N2C = cast<ConstantSDNode>(N2);
11328 unsigned IdxVal = N2C->getZExtValue();
11330 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11331 // into that, and then insert the subvector back into the result.
11332 if (VT.is256BitVector() || VT.is512BitVector()) {
11333 // With a 256-bit vector, we can insert into the zero element efficiently
11334 // using a blend if we have AVX or AVX2 and the right data type.
11335 if (VT.is256BitVector() && IdxVal == 0) {
11336 // TODO: It is worthwhile to cast integer to floating point and back
11337 // and incur a domain crossing penalty if that's what we'll end up
11338 // doing anyway after extracting to a 128-bit vector.
11339 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11340 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11341 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11342 N2 = DAG.getIntPtrConstant(1, dl);
11343 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11347 // Get the desired 128-bit vector chunk.
11348 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11350 // Insert the element into the desired chunk.
11351 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11352 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11354 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11355 DAG.getConstant(IdxIn128, dl, MVT::i32));
11357 // Insert the changed part back into the bigger vector
11358 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11360 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11362 if (Subtarget->hasSSE41()) {
11363 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11365 if (VT == MVT::v8i16) {
11366 Opc = X86ISD::PINSRW;
11368 assert(VT == MVT::v16i8);
11369 Opc = X86ISD::PINSRB;
11372 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11374 if (N1.getValueType() != MVT::i32)
11375 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11376 if (N2.getValueType() != MVT::i32)
11377 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11378 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11381 if (EltVT == MVT::f32) {
11382 // Bits [7:6] of the constant are the source select. This will always be
11383 // zero here. The DAG Combiner may combine an extract_elt index into
11384 // these bits. For example (insert (extract, 3), 2) could be matched by
11385 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11386 // Bits [5:4] of the constant are the destination select. This is the
11387 // value of the incoming immediate.
11388 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11389 // combine either bitwise AND or insert of float 0.0 to set these bits.
11391 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11392 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11393 // If this is an insertion of 32-bits into the low 32-bits of
11394 // a vector, we prefer to generate a blend with immediate rather
11395 // than an insertps. Blends are simpler operations in hardware and so
11396 // will always have equal or better performance than insertps.
11397 // But if optimizing for size and there's a load folding opportunity,
11398 // generate insertps because blendps does not have a 32-bit memory
11400 N2 = DAG.getIntPtrConstant(1, dl);
11401 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11402 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11404 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11405 // Create this as a scalar to vector..
11406 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11407 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11410 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11411 // PINSR* works with constant index.
11416 if (EltVT == MVT::i8)
11419 if (EltVT.getSizeInBits() == 16) {
11420 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11421 // as its second argument.
11422 if (N1.getValueType() != MVT::i32)
11423 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11424 if (N2.getValueType() != MVT::i32)
11425 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11426 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11431 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11433 MVT OpVT = Op.getSimpleValueType();
11435 // If this is a 256-bit vector result, first insert into a 128-bit
11436 // vector and then insert into the 256-bit vector.
11437 if (!OpVT.is128BitVector()) {
11438 // Insert into a 128-bit vector.
11439 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11440 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11441 OpVT.getVectorNumElements() / SizeFactor);
11443 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11445 // Insert the 128-bit vector.
11446 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11449 if (OpVT == MVT::v1i64 &&
11450 Op.getOperand(0).getValueType() == MVT::i64)
11451 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11453 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11454 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11455 return DAG.getBitcast(
11456 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11459 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11460 // a simple subregister reference or explicit instructions to grab
11461 // upper bits of a vector.
11462 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11463 SelectionDAG &DAG) {
11465 SDValue In = Op.getOperand(0);
11466 SDValue Idx = Op.getOperand(1);
11467 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11468 MVT ResVT = Op.getSimpleValueType();
11469 MVT InVT = In.getSimpleValueType();
11471 if (Subtarget->hasFp256()) {
11472 if (ResVT.is128BitVector() &&
11473 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11474 isa<ConstantSDNode>(Idx)) {
11475 return Extract128BitVector(In, IdxVal, DAG, dl);
11477 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11478 isa<ConstantSDNode>(Idx)) {
11479 return Extract256BitVector(In, IdxVal, DAG, dl);
11485 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11486 // simple superregister reference or explicit instructions to insert
11487 // the upper bits of a vector.
11488 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11489 SelectionDAG &DAG) {
11490 if (!Subtarget->hasAVX())
11494 SDValue Vec = Op.getOperand(0);
11495 SDValue SubVec = Op.getOperand(1);
11496 SDValue Idx = Op.getOperand(2);
11498 if (!isa<ConstantSDNode>(Idx))
11501 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11502 MVT OpVT = Op.getSimpleValueType();
11503 MVT SubVecVT = SubVec.getSimpleValueType();
11505 // Fold two 16-byte subvector loads into one 32-byte load:
11506 // (insert_subvector (insert_subvector undef, (load addr), 0),
11507 // (load addr + 16), Elts/2)
11509 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11510 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11511 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11512 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11513 if (Idx2 && Idx2->getZExtValue() == 0) {
11514 SDValue SubVec2 = Vec.getOperand(1);
11515 // If needed, look through a bitcast to get to the load.
11516 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11517 SubVec2 = SubVec2.getOperand(0);
11519 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11521 unsigned Alignment = FirstLd->getAlignment();
11522 unsigned AS = FirstLd->getAddressSpace();
11523 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11524 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11525 OpVT, AS, Alignment, &Fast) && Fast) {
11526 SDValue Ops[] = { SubVec2, SubVec };
11527 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11534 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11535 SubVecVT.is128BitVector())
11536 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11538 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11539 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11541 if (OpVT.getVectorElementType() == MVT::i1) {
11542 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11544 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11545 SDValue Undef = DAG.getUNDEF(OpVT);
11546 unsigned NumElems = OpVT.getVectorNumElements();
11547 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11549 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11550 // Zero upper bits of the Vec
11551 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11552 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11554 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11556 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11557 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11560 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11562 // Zero upper bits of the Vec2
11563 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11564 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11565 // Zero lower bits of the Vec
11566 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11567 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11568 // Merge them together
11569 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11575 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11576 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11577 // one of the above mentioned nodes. It has to be wrapped because otherwise
11578 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11579 // be used to form addressing mode. These wrapped nodes will be selected
11582 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11583 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11585 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11586 // global base reg.
11587 unsigned char OpFlag = 0;
11588 unsigned WrapperKind = X86ISD::Wrapper;
11589 CodeModel::Model M = DAG.getTarget().getCodeModel();
11591 if (Subtarget->isPICStyleRIPRel() &&
11592 (M == CodeModel::Small || M == CodeModel::Kernel))
11593 WrapperKind = X86ISD::WrapperRIP;
11594 else if (Subtarget->isPICStyleGOT())
11595 OpFlag = X86II::MO_GOTOFF;
11596 else if (Subtarget->isPICStyleStubPIC())
11597 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11599 auto PtrVT = getPointerTy(DAG.getDataLayout());
11600 SDValue Result = DAG.getTargetConstantPool(
11601 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11603 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11604 // With PIC, the address is actually $g + Offset.
11607 DAG.getNode(ISD::ADD, DL, PtrVT,
11608 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11614 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11615 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11617 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11618 // global base reg.
11619 unsigned char OpFlag = 0;
11620 unsigned WrapperKind = X86ISD::Wrapper;
11621 CodeModel::Model M = DAG.getTarget().getCodeModel();
11623 if (Subtarget->isPICStyleRIPRel() &&
11624 (M == CodeModel::Small || M == CodeModel::Kernel))
11625 WrapperKind = X86ISD::WrapperRIP;
11626 else if (Subtarget->isPICStyleGOT())
11627 OpFlag = X86II::MO_GOTOFF;
11628 else if (Subtarget->isPICStyleStubPIC())
11629 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11631 auto PtrVT = getPointerTy(DAG.getDataLayout());
11632 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11634 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11636 // With PIC, the address is actually $g + Offset.
11639 DAG.getNode(ISD::ADD, DL, PtrVT,
11640 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11646 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11647 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11649 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11650 // global base reg.
11651 unsigned char OpFlag = 0;
11652 unsigned WrapperKind = X86ISD::Wrapper;
11653 CodeModel::Model M = DAG.getTarget().getCodeModel();
11655 if (Subtarget->isPICStyleRIPRel() &&
11656 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11657 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11658 OpFlag = X86II::MO_GOTPCREL;
11659 WrapperKind = X86ISD::WrapperRIP;
11660 } else if (Subtarget->isPICStyleGOT()) {
11661 OpFlag = X86II::MO_GOT;
11662 } else if (Subtarget->isPICStyleStubPIC()) {
11663 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11664 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11665 OpFlag = X86II::MO_DARWIN_NONLAZY;
11668 auto PtrVT = getPointerTy(DAG.getDataLayout());
11669 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11672 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11674 // With PIC, the address is actually $g + Offset.
11675 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11676 !Subtarget->is64Bit()) {
11678 DAG.getNode(ISD::ADD, DL, PtrVT,
11679 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11682 // For symbols that require a load from a stub to get the address, emit the
11684 if (isGlobalStubReference(OpFlag))
11685 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11686 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11687 false, false, false, 0);
11693 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11694 // Create the TargetBlockAddressAddress node.
11695 unsigned char OpFlags =
11696 Subtarget->ClassifyBlockAddressReference();
11697 CodeModel::Model M = DAG.getTarget().getCodeModel();
11698 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11699 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11701 auto PtrVT = getPointerTy(DAG.getDataLayout());
11702 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11704 if (Subtarget->isPICStyleRIPRel() &&
11705 (M == CodeModel::Small || M == CodeModel::Kernel))
11706 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11708 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11710 // With PIC, the address is actually $g + Offset.
11711 if (isGlobalRelativeToPICBase(OpFlags)) {
11712 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11713 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11720 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11721 int64_t Offset, SelectionDAG &DAG) const {
11722 // Create the TargetGlobalAddress node, folding in the constant
11723 // offset if it is legal.
11724 unsigned char OpFlags =
11725 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11726 CodeModel::Model M = DAG.getTarget().getCodeModel();
11727 auto PtrVT = getPointerTy(DAG.getDataLayout());
11729 if (OpFlags == X86II::MO_NO_FLAG &&
11730 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11731 // A direct static reference to a global.
11732 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11735 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11738 if (Subtarget->isPICStyleRIPRel() &&
11739 (M == CodeModel::Small || M == CodeModel::Kernel))
11740 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11742 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11744 // With PIC, the address is actually $g + Offset.
11745 if (isGlobalRelativeToPICBase(OpFlags)) {
11746 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11747 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11750 // For globals that require a load from a stub to get the address, emit the
11752 if (isGlobalStubReference(OpFlags))
11753 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11754 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11755 false, false, false, 0);
11757 // If there was a non-zero offset that we didn't fold, create an explicit
11758 // addition for it.
11760 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11761 DAG.getConstant(Offset, dl, PtrVT));
11767 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11768 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11769 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11770 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11774 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11775 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11776 unsigned char OperandFlags, bool LocalDynamic = false) {
11777 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11778 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11780 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11781 GA->getValueType(0),
11785 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11789 SDValue Ops[] = { Chain, TGA, *InFlag };
11790 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11792 SDValue Ops[] = { Chain, TGA };
11793 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11796 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11797 MFI->setAdjustsStack(true);
11798 MFI->setHasCalls(true);
11800 SDValue Flag = Chain.getValue(1);
11801 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11804 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11806 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11809 SDLoc dl(GA); // ? function entry point might be better
11810 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11811 DAG.getNode(X86ISD::GlobalBaseReg,
11812 SDLoc(), PtrVT), InFlag);
11813 InFlag = Chain.getValue(1);
11815 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11818 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11820 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11822 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11823 X86::RAX, X86II::MO_TLSGD);
11826 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11832 // Get the start address of the TLS block for this module.
11833 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11834 .getInfo<X86MachineFunctionInfo>();
11835 MFI->incNumLocalDynamicTLSAccesses();
11839 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11840 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11843 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11844 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11845 InFlag = Chain.getValue(1);
11846 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11847 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11850 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11854 unsigned char OperandFlags = X86II::MO_DTPOFF;
11855 unsigned WrapperKind = X86ISD::Wrapper;
11856 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11857 GA->getValueType(0),
11858 GA->getOffset(), OperandFlags);
11859 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11861 // Add x@dtpoff with the base.
11862 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11865 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11866 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11867 const EVT PtrVT, TLSModel::Model model,
11868 bool is64Bit, bool isPIC) {
11871 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11872 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11873 is64Bit ? 257 : 256));
11875 SDValue ThreadPointer =
11876 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11877 MachinePointerInfo(Ptr), false, false, false, 0);
11879 unsigned char OperandFlags = 0;
11880 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11882 unsigned WrapperKind = X86ISD::Wrapper;
11883 if (model == TLSModel::LocalExec) {
11884 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11885 } else if (model == TLSModel::InitialExec) {
11887 OperandFlags = X86II::MO_GOTTPOFF;
11888 WrapperKind = X86ISD::WrapperRIP;
11890 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11893 llvm_unreachable("Unexpected model");
11896 // emit "addl x@ntpoff,%eax" (local exec)
11897 // or "addl x@indntpoff,%eax" (initial exec)
11898 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11900 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11901 GA->getOffset(), OperandFlags);
11902 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11904 if (model == TLSModel::InitialExec) {
11905 if (isPIC && !is64Bit) {
11906 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11907 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11911 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11912 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11913 false, false, false, 0);
11916 // The address of the thread local variable is the add of the thread
11917 // pointer with the offset of the variable.
11918 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11922 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11924 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11925 const GlobalValue *GV = GA->getGlobal();
11926 auto PtrVT = getPointerTy(DAG.getDataLayout());
11928 if (Subtarget->isTargetELF()) {
11929 if (DAG.getTarget().Options.EmulatedTLS)
11930 return LowerToTLSEmulatedModel(GA, DAG);
11931 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11933 case TLSModel::GeneralDynamic:
11934 if (Subtarget->is64Bit())
11935 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
11936 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
11937 case TLSModel::LocalDynamic:
11938 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
11939 Subtarget->is64Bit());
11940 case TLSModel::InitialExec:
11941 case TLSModel::LocalExec:
11942 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
11943 DAG.getTarget().getRelocationModel() ==
11946 llvm_unreachable("Unknown TLS model.");
11949 if (Subtarget->isTargetDarwin()) {
11950 // Darwin only has one model of TLS. Lower to that.
11951 unsigned char OpFlag = 0;
11952 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11953 X86ISD::WrapperRIP : X86ISD::Wrapper;
11955 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11956 // global base reg.
11957 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11958 !Subtarget->is64Bit();
11960 OpFlag = X86II::MO_TLVP_PIC_BASE;
11962 OpFlag = X86II::MO_TLVP;
11964 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11965 GA->getValueType(0),
11966 GA->getOffset(), OpFlag);
11967 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11969 // With PIC32, the address is actually $g + Offset.
11971 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
11972 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11975 // Lowering the machine isd will make sure everything is in the right
11977 SDValue Chain = DAG.getEntryNode();
11978 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11979 SDValue Args[] = { Chain, Offset };
11980 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11982 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11983 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11984 MFI->setAdjustsStack(true);
11986 // And our return value (tls address) is in the standard call return value
11988 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11989 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
11992 if (Subtarget->isTargetKnownWindowsMSVC() ||
11993 Subtarget->isTargetWindowsGNU()) {
11994 // Just use the implicit TLS architecture
11995 // Need to generate someting similar to:
11996 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11998 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11999 // mov rcx, qword [rdx+rcx*8]
12000 // mov eax, .tls$:tlsvar
12001 // [rax+rcx] contains the address
12002 // Windows 64bit: gs:0x58
12003 // Windows 32bit: fs:__tls_array
12006 SDValue Chain = DAG.getEntryNode();
12008 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12009 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12010 // use its literal value of 0x2C.
12011 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12012 ? Type::getInt8PtrTy(*DAG.getContext(),
12014 : Type::getInt32PtrTy(*DAG.getContext(),
12017 SDValue TlsArray = Subtarget->is64Bit()
12018 ? DAG.getIntPtrConstant(0x58, dl)
12019 : (Subtarget->isTargetWindowsGNU()
12020 ? DAG.getIntPtrConstant(0x2C, dl)
12021 : DAG.getExternalSymbol("_tls_array", PtrVT));
12023 SDValue ThreadPointer =
12024 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12028 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12029 res = ThreadPointer;
12031 // Load the _tls_index variable
12032 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12033 if (Subtarget->is64Bit())
12034 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12035 MachinePointerInfo(), MVT::i32, false, false,
12038 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12041 auto &DL = DAG.getDataLayout();
12043 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12044 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12046 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12049 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12052 // Get the offset of start of .tls section
12053 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12054 GA->getValueType(0),
12055 GA->getOffset(), X86II::MO_SECREL);
12056 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12058 // The address of the thread local variable is the add of the thread
12059 // pointer with the offset of the variable.
12060 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12063 llvm_unreachable("TLS not implemented for this target.");
12066 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12067 /// and take a 2 x i32 value to shift plus a shift amount.
12068 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12069 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12070 MVT VT = Op.getSimpleValueType();
12071 unsigned VTBits = VT.getSizeInBits();
12073 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12074 SDValue ShOpLo = Op.getOperand(0);
12075 SDValue ShOpHi = Op.getOperand(1);
12076 SDValue ShAmt = Op.getOperand(2);
12077 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12078 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12080 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12081 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12082 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12083 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12084 : DAG.getConstant(0, dl, VT);
12086 SDValue Tmp2, Tmp3;
12087 if (Op.getOpcode() == ISD::SHL_PARTS) {
12088 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12089 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12091 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12092 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12095 // If the shift amount is larger or equal than the width of a part we can't
12096 // rely on the results of shld/shrd. Insert a test and select the appropriate
12097 // values for large shift amounts.
12098 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12099 DAG.getConstant(VTBits, dl, MVT::i8));
12100 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12101 AndNode, DAG.getConstant(0, dl, MVT::i8));
12104 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12105 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12106 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12108 if (Op.getOpcode() == ISD::SHL_PARTS) {
12109 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12110 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12112 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12113 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12116 SDValue Ops[2] = { Lo, Hi };
12117 return DAG.getMergeValues(Ops, dl);
12120 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12121 SelectionDAG &DAG) const {
12122 SDValue Src = Op.getOperand(0);
12123 MVT SrcVT = Src.getSimpleValueType();
12124 MVT VT = Op.getSimpleValueType();
12127 if (SrcVT.isVector()) {
12128 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12129 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12130 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12131 DAG.getUNDEF(SrcVT)));
12133 if (SrcVT.getVectorElementType() == MVT::i1) {
12134 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12135 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12136 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12141 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12142 "Unknown SINT_TO_FP to lower!");
12144 // These are really Legal; return the operand so the caller accepts it as
12146 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12148 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12149 Subtarget->is64Bit()) {
12153 unsigned Size = SrcVT.getSizeInBits()/8;
12154 MachineFunction &MF = DAG.getMachineFunction();
12155 auto PtrVT = getPointerTy(MF.getDataLayout());
12156 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12157 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12158 SDValue Chain = DAG.getStore(
12159 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12160 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12162 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12165 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12167 SelectionDAG &DAG) const {
12171 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12173 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12175 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12177 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12179 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12180 MachineMemOperand *MMO;
12182 int SSFI = FI->getIndex();
12183 MMO = DAG.getMachineFunction().getMachineMemOperand(
12184 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12185 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12187 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12188 StackSlot = StackSlot.getOperand(1);
12190 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12191 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12193 Tys, Ops, SrcVT, MMO);
12196 Chain = Result.getValue(1);
12197 SDValue InFlag = Result.getValue(2);
12199 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12200 // shouldn't be necessary except that RFP cannot be live across
12201 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12202 MachineFunction &MF = DAG.getMachineFunction();
12203 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12204 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12205 auto PtrVT = getPointerTy(MF.getDataLayout());
12206 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12207 Tys = DAG.getVTList(MVT::Other);
12209 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12211 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12212 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12213 MachineMemOperand::MOStore, SSFISize, SSFISize);
12215 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12216 Ops, Op.getValueType(), MMO);
12217 Result = DAG.getLoad(
12218 Op.getValueType(), DL, Chain, StackSlot,
12219 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12220 false, false, false, 0);
12226 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12227 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12228 SelectionDAG &DAG) const {
12229 // This algorithm is not obvious. Here it is what we're trying to output:
12232 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12233 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12235 haddpd %xmm0, %xmm0
12237 pshufd $0x4e, %xmm0, %xmm1
12243 LLVMContext *Context = DAG.getContext();
12245 // Build some magic constants.
12246 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12247 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12248 auto PtrVT = getPointerTy(DAG.getDataLayout());
12249 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12251 SmallVector<Constant*,2> CV1;
12253 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12254 APInt(64, 0x4330000000000000ULL))));
12256 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12257 APInt(64, 0x4530000000000000ULL))));
12258 Constant *C1 = ConstantVector::get(CV1);
12259 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12261 // Load the 64-bit value into an XMM register.
12262 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12265 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12266 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12267 false, false, false, 16);
12269 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12272 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12273 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12274 false, false, false, 16);
12275 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12276 // TODO: Are there any fast-math-flags to propagate here?
12277 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12280 if (Subtarget->hasSSE3()) {
12281 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12282 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12284 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12285 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12287 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12288 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12291 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12292 DAG.getIntPtrConstant(0, dl));
12295 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12296 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12297 SelectionDAG &DAG) const {
12299 // FP constant to bias correct the final result.
12300 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12303 // Load the 32-bit value into an XMM register.
12304 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12307 // Zero out the upper parts of the register.
12308 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12310 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12311 DAG.getBitcast(MVT::v2f64, Load),
12312 DAG.getIntPtrConstant(0, dl));
12314 // Or the load with the bias.
12315 SDValue Or = DAG.getNode(
12316 ISD::OR, dl, MVT::v2i64,
12317 DAG.getBitcast(MVT::v2i64,
12318 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12319 DAG.getBitcast(MVT::v2i64,
12320 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12322 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12323 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12325 // Subtract the bias.
12326 // TODO: Are there any fast-math-flags to propagate here?
12327 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12329 // Handle final rounding.
12330 EVT DestVT = Op.getValueType();
12332 if (DestVT.bitsLT(MVT::f64))
12333 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12334 DAG.getIntPtrConstant(0, dl));
12335 if (DestVT.bitsGT(MVT::f64))
12336 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12338 // Handle final rounding.
12342 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12343 const X86Subtarget &Subtarget) {
12344 // The algorithm is the following:
12345 // #ifdef __SSE4_1__
12346 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12347 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12348 // (uint4) 0x53000000, 0xaa);
12350 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12351 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12353 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12354 // return (float4) lo + fhi;
12357 SDValue V = Op->getOperand(0);
12358 EVT VecIntVT = V.getValueType();
12359 bool Is128 = VecIntVT == MVT::v4i32;
12360 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12361 // If we convert to something else than the supported type, e.g., to v4f64,
12363 if (VecFloatVT != Op->getValueType(0))
12366 unsigned NumElts = VecIntVT.getVectorNumElements();
12367 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12368 "Unsupported custom type");
12369 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12371 // In the #idef/#else code, we have in common:
12372 // - The vector of constants:
12378 // Create the splat vector for 0x4b000000.
12379 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12380 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12381 CstLow, CstLow, CstLow, CstLow};
12382 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12383 makeArrayRef(&CstLowArray[0], NumElts));
12384 // Create the splat vector for 0x53000000.
12385 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12386 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12387 CstHigh, CstHigh, CstHigh, CstHigh};
12388 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12389 makeArrayRef(&CstHighArray[0], NumElts));
12391 // Create the right shift.
12392 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12393 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12394 CstShift, CstShift, CstShift, CstShift};
12395 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12396 makeArrayRef(&CstShiftArray[0], NumElts));
12397 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12400 if (Subtarget.hasSSE41()) {
12401 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12402 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12403 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12404 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12405 // Low will be bitcasted right away, so do not bother bitcasting back to its
12407 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12408 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12409 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12410 // (uint4) 0x53000000, 0xaa);
12411 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12412 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12413 // High will be bitcasted right away, so do not bother bitcasting back to
12414 // its original type.
12415 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12416 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12418 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12419 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12420 CstMask, CstMask, CstMask);
12421 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12422 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12423 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12425 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12426 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12429 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12430 SDValue CstFAdd = DAG.getConstantFP(
12431 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12432 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12433 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12434 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12435 makeArrayRef(&CstFAddArray[0], NumElts));
12437 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12438 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12439 // TODO: Are there any fast-math-flags to propagate here?
12441 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12442 // return (float4) lo + fhi;
12443 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12444 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12447 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12448 SelectionDAG &DAG) const {
12449 SDValue N0 = Op.getOperand(0);
12450 MVT SVT = N0.getSimpleValueType();
12453 switch (SVT.SimpleTy) {
12455 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12460 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12461 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12462 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12466 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12469 if (Subtarget->hasAVX512())
12470 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12471 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12473 llvm_unreachable(nullptr);
12476 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12477 SelectionDAG &DAG) const {
12478 SDValue N0 = Op.getOperand(0);
12480 auto PtrVT = getPointerTy(DAG.getDataLayout());
12482 if (Op.getValueType().isVector())
12483 return lowerUINT_TO_FP_vec(Op, DAG);
12485 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12486 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12487 // the optimization here.
12488 if (DAG.SignBitIsZero(N0))
12489 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12491 MVT SrcVT = N0.getSimpleValueType();
12492 MVT DstVT = Op.getSimpleValueType();
12493 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12494 return LowerUINT_TO_FP_i64(Op, DAG);
12495 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12496 return LowerUINT_TO_FP_i32(Op, DAG);
12497 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12500 // Make a 64-bit buffer, and use it to build an FILD.
12501 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12502 if (SrcVT == MVT::i32) {
12503 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12504 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12505 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12506 StackSlot, MachinePointerInfo(),
12508 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12509 OffsetSlot, MachinePointerInfo(),
12511 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12515 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12516 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12517 StackSlot, MachinePointerInfo(),
12519 // For i64 source, we need to add the appropriate power of 2 if the input
12520 // was negative. This is the same as the optimization in
12521 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12522 // we must be careful to do the computation in x87 extended precision, not
12523 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12524 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12525 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12526 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12527 MachineMemOperand::MOLoad, 8, 8);
12529 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12530 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12531 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12534 APInt FF(32, 0x5F800000ULL);
12536 // Check whether the sign bit is set.
12537 SDValue SignSet = DAG.getSetCC(
12538 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12539 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12541 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12542 SDValue FudgePtr = DAG.getConstantPool(
12543 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12545 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12546 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12547 SDValue Four = DAG.getIntPtrConstant(4, dl);
12548 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12550 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12552 // Load the value out, extending it from f32 to f80.
12553 // FIXME: Avoid the extend by constructing the right constant pool?
12554 SDValue Fudge = DAG.getExtLoad(
12555 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12556 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12557 false, false, false, 4);
12558 // Extend everything to 80 bits to force it to be done on x87.
12559 // TODO: Are there any fast-math-flags to propagate here?
12560 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12561 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12562 DAG.getIntPtrConstant(0, dl));
12565 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12566 // is legal, or has an f16 source (which needs to be promoted to f32),
12567 // just return an <SDValue(), SDValue()> pair.
12568 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12569 // to i16, i32 or i64, and we lower it to a legal sequence.
12570 // If lowered to the final integer result we return a <result, SDValue()> pair.
12571 // Otherwise we lower it to a sequence ending with a FIST, return a
12572 // <FIST, StackSlot> pair, and the caller is responsible for loading
12573 // the final integer result from StackSlot.
12574 std::pair<SDValue,SDValue>
12575 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12576 bool IsSigned, bool IsReplace) const {
12579 EVT DstTy = Op.getValueType();
12580 EVT TheVT = Op.getOperand(0).getValueType();
12581 auto PtrVT = getPointerTy(DAG.getDataLayout());
12583 if (TheVT == MVT::f16)
12584 // We need to promote the f16 to f32 before using the lowering
12585 // in this routine.
12586 return std::make_pair(SDValue(), SDValue());
12588 assert((TheVT == MVT::f32 ||
12589 TheVT == MVT::f64 ||
12590 TheVT == MVT::f80) &&
12591 "Unexpected FP operand type in FP_TO_INTHelper");
12593 // If using FIST to compute an unsigned i64, we'll need some fixup
12594 // to handle values above the maximum signed i64. A FIST is always
12595 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12596 bool UnsignedFixup = !IsSigned &&
12597 DstTy == MVT::i64 &&
12598 (!Subtarget->is64Bit() ||
12599 !isScalarFPTypeInSSEReg(TheVT));
12601 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12602 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12603 // The low 32 bits of the fist result will have the correct uint32 result.
12604 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12608 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12609 DstTy.getSimpleVT() >= MVT::i16 &&
12610 "Unknown FP_TO_INT to lower!");
12612 // These are really Legal.
12613 if (DstTy == MVT::i32 &&
12614 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12615 return std::make_pair(SDValue(), SDValue());
12616 if (Subtarget->is64Bit() &&
12617 DstTy == MVT::i64 &&
12618 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12619 return std::make_pair(SDValue(), SDValue());
12621 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12623 MachineFunction &MF = DAG.getMachineFunction();
12624 unsigned MemSize = DstTy.getSizeInBits()/8;
12625 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12626 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12629 switch (DstTy.getSimpleVT().SimpleTy) {
12630 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12631 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12632 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12633 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12636 SDValue Chain = DAG.getEntryNode();
12637 SDValue Value = Op.getOperand(0);
12638 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12640 if (UnsignedFixup) {
12642 // Conversion to unsigned i64 is implemented with a select,
12643 // depending on whether the source value fits in the range
12644 // of a signed i64. Let Thresh be the FP equivalent of
12645 // 0x8000000000000000ULL.
12647 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12648 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12649 // Fist-to-mem64 FistSrc
12650 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12651 // to XOR'ing the high 32 bits with Adjust.
12653 // Being a power of 2, Thresh is exactly representable in all FP formats.
12654 // For X87 we'd like to use the smallest FP type for this constant, but
12655 // for DAG type consistency we have to match the FP operand type.
12657 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12658 APFloat::opStatus Status = APFloat::opOK;
12659 bool LosesInfo = false;
12660 if (TheVT == MVT::f64)
12661 // The rounding mode is irrelevant as the conversion should be exact.
12662 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12664 else if (TheVT == MVT::f80)
12665 Status = Thresh.convert(APFloat::x87DoubleExtended,
12666 APFloat::rmNearestTiesToEven, &LosesInfo);
12668 assert(Status == APFloat::opOK && !LosesInfo &&
12669 "FP conversion should have been exact");
12671 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12673 SDValue Cmp = DAG.getSetCC(DL,
12674 getSetCCResultType(DAG.getDataLayout(),
12675 *DAG.getContext(), TheVT),
12676 Value, ThreshVal, ISD::SETLT);
12677 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12678 DAG.getConstant(0, DL, MVT::i32),
12679 DAG.getConstant(0x80000000, DL, MVT::i32));
12680 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12681 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12682 *DAG.getContext(), TheVT),
12683 Value, ThreshVal, ISD::SETLT);
12684 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12687 // FIXME This causes a redundant load/store if the SSE-class value is already
12688 // in memory, such as if it is on the callstack.
12689 if (isScalarFPTypeInSSEReg(TheVT)) {
12690 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12691 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12692 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12694 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12696 Chain, StackSlot, DAG.getValueType(TheVT)
12699 MachineMemOperand *MMO =
12700 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12701 MachineMemOperand::MOLoad, MemSize, MemSize);
12702 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12703 Chain = Value.getValue(1);
12704 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12705 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12708 MachineMemOperand *MMO =
12709 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12710 MachineMemOperand::MOStore, MemSize, MemSize);
12712 if (UnsignedFixup) {
12714 // Insert the FIST, load its result as two i32's,
12715 // and XOR the high i32 with Adjust.
12717 SDValue FistOps[] = { Chain, Value, StackSlot };
12718 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12719 FistOps, DstTy, MMO);
12721 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
12722 MachinePointerInfo(),
12723 false, false, false, 0);
12724 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
12725 DAG.getConstant(4, DL, PtrVT));
12727 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
12728 MachinePointerInfo(),
12729 false, false, false, 0);
12730 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
12732 if (Subtarget->is64Bit()) {
12733 // Join High32 and Low32 into a 64-bit result.
12734 // (High32 << 32) | Low32
12735 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
12736 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
12737 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
12738 DAG.getConstant(32, DL, MVT::i8));
12739 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
12740 return std::make_pair(Result, SDValue());
12743 SDValue ResultOps[] = { Low32, High32 };
12745 SDValue pair = IsReplace
12746 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
12747 : DAG.getMergeValues(ResultOps, DL);
12748 return std::make_pair(pair, SDValue());
12750 // Build the FP_TO_INT*_IN_MEM
12751 SDValue Ops[] = { Chain, Value, StackSlot };
12752 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12754 return std::make_pair(FIST, StackSlot);
12758 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12759 const X86Subtarget *Subtarget) {
12760 MVT VT = Op->getSimpleValueType(0);
12761 SDValue In = Op->getOperand(0);
12762 MVT InVT = In.getSimpleValueType();
12765 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12766 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12768 // Optimize vectors in AVX mode:
12771 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12772 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12773 // Concat upper and lower parts.
12776 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12777 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12778 // Concat upper and lower parts.
12781 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12782 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12783 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12786 if (Subtarget->hasInt256())
12787 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12789 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12790 SDValue Undef = DAG.getUNDEF(InVT);
12791 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12792 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12793 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12795 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12796 VT.getVectorNumElements()/2);
12798 OpLo = DAG.getBitcast(HVT, OpLo);
12799 OpHi = DAG.getBitcast(HVT, OpHi);
12801 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12804 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12805 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12806 MVT VT = Op->getSimpleValueType(0);
12807 SDValue In = Op->getOperand(0);
12808 MVT InVT = In.getSimpleValueType();
12810 unsigned int NumElts = VT.getVectorNumElements();
12811 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12814 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12815 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12817 assert(InVT.getVectorElementType() == MVT::i1);
12818 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12820 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12822 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12824 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12825 if (VT.is512BitVector())
12827 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12830 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12831 SelectionDAG &DAG) {
12832 if (Subtarget->hasFp256())
12833 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12839 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12840 SelectionDAG &DAG) {
12842 MVT VT = Op.getSimpleValueType();
12843 SDValue In = Op.getOperand(0);
12844 MVT SVT = In.getSimpleValueType();
12846 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12847 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12849 if (Subtarget->hasFp256())
12850 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12853 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12854 VT.getVectorNumElements() != SVT.getVectorNumElements());
12858 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12860 MVT VT = Op.getSimpleValueType();
12861 SDValue In = Op.getOperand(0);
12862 MVT InVT = In.getSimpleValueType();
12864 if (VT == MVT::i1) {
12865 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12866 "Invalid scalar TRUNCATE operation");
12867 if (InVT.getSizeInBits() >= 32)
12869 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12870 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12872 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12873 "Invalid TRUNCATE operation");
12875 // move vector to mask - truncate solution for SKX
12876 if (VT.getVectorElementType() == MVT::i1) {
12877 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12878 Subtarget->hasBWI())
12879 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12880 if ((InVT.is256BitVector() || InVT.is128BitVector())
12881 && InVT.getScalarSizeInBits() <= 16 &&
12882 Subtarget->hasBWI() && Subtarget->hasVLX())
12883 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12884 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12885 Subtarget->hasDQI())
12886 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12887 if ((InVT.is256BitVector() || InVT.is128BitVector())
12888 && InVT.getScalarSizeInBits() >= 32 &&
12889 Subtarget->hasDQI() && Subtarget->hasVLX())
12890 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12893 if (VT.getVectorElementType() == MVT::i1) {
12894 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12895 unsigned NumElts = InVT.getVectorNumElements();
12896 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12897 if (InVT.getSizeInBits() < 512) {
12898 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12899 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12904 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12905 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12906 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12909 // vpmovqb/w/d, vpmovdb/w, vpmovwb
12910 if (((!InVT.is512BitVector() && Subtarget->hasVLX()) || InVT.is512BitVector()) &&
12911 (InVT.getVectorElementType() != MVT::i16 || Subtarget->hasBWI()))
12912 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12914 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12915 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12916 if (Subtarget->hasInt256()) {
12917 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12918 In = DAG.getBitcast(MVT::v8i32, In);
12919 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12921 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12922 DAG.getIntPtrConstant(0, DL));
12925 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12926 DAG.getIntPtrConstant(0, DL));
12927 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12928 DAG.getIntPtrConstant(2, DL));
12929 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12930 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12931 static const int ShufMask[] = {0, 2, 4, 6};
12932 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12935 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12936 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12937 if (Subtarget->hasInt256()) {
12938 In = DAG.getBitcast(MVT::v32i8, In);
12940 SmallVector<SDValue,32> pshufbMask;
12941 for (unsigned i = 0; i < 2; ++i) {
12942 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12943 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12944 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12945 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12946 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12947 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12948 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12949 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12950 for (unsigned j = 0; j < 8; ++j)
12951 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12953 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12954 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12955 In = DAG.getBitcast(MVT::v4i64, In);
12957 static const int ShufMask[] = {0, 2, -1, -1};
12958 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12960 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12961 DAG.getIntPtrConstant(0, DL));
12962 return DAG.getBitcast(VT, In);
12965 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12966 DAG.getIntPtrConstant(0, DL));
12968 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12969 DAG.getIntPtrConstant(4, DL));
12971 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
12972 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
12974 // The PSHUFB mask:
12975 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12976 -1, -1, -1, -1, -1, -1, -1, -1};
12978 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12979 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12980 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12982 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12983 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12985 // The MOVLHPS Mask:
12986 static const int ShufMask2[] = {0, 1, 4, 5};
12987 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12988 return DAG.getBitcast(MVT::v8i16, res);
12991 // Handle truncation of V256 to V128 using shuffles.
12992 if (!VT.is128BitVector() || !InVT.is256BitVector())
12995 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12997 unsigned NumElems = VT.getVectorNumElements();
12998 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13000 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13001 // Prepare truncation shuffle mask
13002 for (unsigned i = 0; i != NumElems; ++i)
13003 MaskVec[i] = i * 2;
13004 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13005 DAG.getUNDEF(NVT), &MaskVec[0]);
13006 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13007 DAG.getIntPtrConstant(0, DL));
13010 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13011 SelectionDAG &DAG) const {
13012 assert(!Op.getSimpleValueType().isVector());
13014 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13015 /*IsSigned=*/ true, /*IsReplace=*/ false);
13016 SDValue FIST = Vals.first, StackSlot = Vals.second;
13017 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13018 if (!FIST.getNode())
13021 if (StackSlot.getNode())
13022 // Load the result.
13023 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13024 FIST, StackSlot, MachinePointerInfo(),
13025 false, false, false, 0);
13027 // The node is the result.
13031 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13032 SelectionDAG &DAG) const {
13033 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13034 /*IsSigned=*/ false, /*IsReplace=*/ false);
13035 SDValue FIST = Vals.first, StackSlot = Vals.second;
13036 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13037 if (!FIST.getNode())
13040 if (StackSlot.getNode())
13041 // Load the result.
13042 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13043 FIST, StackSlot, MachinePointerInfo(),
13044 false, false, false, 0);
13046 // The node is the result.
13050 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13052 MVT VT = Op.getSimpleValueType();
13053 SDValue In = Op.getOperand(0);
13054 MVT SVT = In.getSimpleValueType();
13056 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13058 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13059 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13060 In, DAG.getUNDEF(SVT)));
13063 /// The only differences between FABS and FNEG are the mask and the logic op.
13064 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13065 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13066 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13067 "Wrong opcode for lowering FABS or FNEG.");
13069 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13071 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13072 // into an FNABS. We'll lower the FABS after that if it is still in use.
13074 for (SDNode *User : Op->uses())
13075 if (User->getOpcode() == ISD::FNEG)
13079 MVT VT = Op.getSimpleValueType();
13081 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13082 // decide if we should generate a 16-byte constant mask when we only need 4 or
13083 // 8 bytes for the scalar case.
13089 if (VT.isVector()) {
13091 EltVT = VT.getVectorElementType();
13092 NumElts = VT.getVectorNumElements();
13094 // There are no scalar bitwise logical SSE/AVX instructions, so we
13095 // generate a 16-byte vector constant and logic op even for the scalar case.
13096 // Using a 16-byte mask allows folding the load of the mask with
13097 // the logic op, so it can save (~4 bytes) on code size.
13098 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13100 NumElts = (VT == MVT::f64) ? 2 : 4;
13103 unsigned EltBits = EltVT.getSizeInBits();
13104 LLVMContext *Context = DAG.getContext();
13105 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13107 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13108 Constant *C = ConstantInt::get(*Context, MaskElt);
13109 C = ConstantVector::getSplat(NumElts, C);
13110 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13111 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13112 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13114 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13115 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13116 false, false, false, Alignment);
13118 SDValue Op0 = Op.getOperand(0);
13119 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13121 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13122 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13125 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13127 // For the scalar case extend to a 128-bit vector, perform the logic op,
13128 // and extract the scalar result back out.
13129 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13130 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13131 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13132 DAG.getIntPtrConstant(0, dl));
13135 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13136 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13137 LLVMContext *Context = DAG.getContext();
13138 SDValue Op0 = Op.getOperand(0);
13139 SDValue Op1 = Op.getOperand(1);
13141 MVT VT = Op.getSimpleValueType();
13142 MVT SrcVT = Op1.getSimpleValueType();
13144 // If second operand is smaller, extend it first.
13145 if (SrcVT.bitsLT(VT)) {
13146 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13149 // And if it is bigger, shrink it first.
13150 if (SrcVT.bitsGT(VT)) {
13151 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13155 // At this point the operands and the result should have the same
13156 // type, and that won't be f80 since that is not custom lowered.
13158 const fltSemantics &Sem =
13159 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13160 const unsigned SizeInBits = VT.getSizeInBits();
13162 SmallVector<Constant *, 4> CV(
13163 VT == MVT::f64 ? 2 : 4,
13164 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13166 // First, clear all bits but the sign bit from the second operand (sign).
13167 CV[0] = ConstantFP::get(*Context,
13168 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13169 Constant *C = ConstantVector::get(CV);
13170 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13171 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13173 // Perform all logic operations as 16-byte vectors because there are no
13174 // scalar FP logic instructions in SSE. This allows load folding of the
13175 // constants into the logic instructions.
13176 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13178 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13179 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13180 false, false, false, 16);
13181 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13182 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13184 // Next, clear the sign bit from the first operand (magnitude).
13185 // If it's a constant, we can clear it here.
13186 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13187 APFloat APF = Op0CN->getValueAPF();
13188 // If the magnitude is a positive zero, the sign bit alone is enough.
13189 if (APF.isPosZero())
13190 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13191 DAG.getIntPtrConstant(0, dl));
13193 CV[0] = ConstantFP::get(*Context, APF);
13195 CV[0] = ConstantFP::get(
13197 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13199 C = ConstantVector::get(CV);
13200 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13202 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13203 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13204 false, false, false, 16);
13205 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13206 if (!isa<ConstantFPSDNode>(Op0)) {
13207 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13208 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13210 // OR the magnitude value with the sign bit.
13211 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13212 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13213 DAG.getIntPtrConstant(0, dl));
13216 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13217 SDValue N0 = Op.getOperand(0);
13219 MVT VT = Op.getSimpleValueType();
13221 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13222 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13223 DAG.getConstant(1, dl, VT));
13224 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13227 // Check whether an OR'd tree is PTEST-able.
13228 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13229 SelectionDAG &DAG) {
13230 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13232 if (!Subtarget->hasSSE41())
13235 if (!Op->hasOneUse())
13238 SDNode *N = Op.getNode();
13241 SmallVector<SDValue, 8> Opnds;
13242 DenseMap<SDValue, unsigned> VecInMap;
13243 SmallVector<SDValue, 8> VecIns;
13244 EVT VT = MVT::Other;
13246 // Recognize a special case where a vector is casted into wide integer to
13248 Opnds.push_back(N->getOperand(0));
13249 Opnds.push_back(N->getOperand(1));
13251 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13252 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13253 // BFS traverse all OR'd operands.
13254 if (I->getOpcode() == ISD::OR) {
13255 Opnds.push_back(I->getOperand(0));
13256 Opnds.push_back(I->getOperand(1));
13257 // Re-evaluate the number of nodes to be traversed.
13258 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13262 // Quit if a non-EXTRACT_VECTOR_ELT
13263 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13266 // Quit if without a constant index.
13267 SDValue Idx = I->getOperand(1);
13268 if (!isa<ConstantSDNode>(Idx))
13271 SDValue ExtractedFromVec = I->getOperand(0);
13272 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13273 if (M == VecInMap.end()) {
13274 VT = ExtractedFromVec.getValueType();
13275 // Quit if not 128/256-bit vector.
13276 if (!VT.is128BitVector() && !VT.is256BitVector())
13278 // Quit if not the same type.
13279 if (VecInMap.begin() != VecInMap.end() &&
13280 VT != VecInMap.begin()->first.getValueType())
13282 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13283 VecIns.push_back(ExtractedFromVec);
13285 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13288 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13289 "Not extracted from 128-/256-bit vector.");
13291 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13293 for (DenseMap<SDValue, unsigned>::const_iterator
13294 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13295 // Quit if not all elements are used.
13296 if (I->second != FullMask)
13300 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13302 // Cast all vectors into TestVT for PTEST.
13303 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13304 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13306 // If more than one full vectors are evaluated, OR them first before PTEST.
13307 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13308 // Each iteration will OR 2 nodes and append the result until there is only
13309 // 1 node left, i.e. the final OR'd value of all vectors.
13310 SDValue LHS = VecIns[Slot];
13311 SDValue RHS = VecIns[Slot + 1];
13312 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13315 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13316 VecIns.back(), VecIns.back());
13319 /// \brief return true if \c Op has a use that doesn't just read flags.
13320 static bool hasNonFlagsUse(SDValue Op) {
13321 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13323 SDNode *User = *UI;
13324 unsigned UOpNo = UI.getOperandNo();
13325 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13326 // Look pass truncate.
13327 UOpNo = User->use_begin().getOperandNo();
13328 User = *User->use_begin();
13331 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13332 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13338 /// Emit nodes that will be selected as "test Op0,Op0", or something
13340 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13341 SelectionDAG &DAG) const {
13342 if (Op.getValueType() == MVT::i1) {
13343 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13344 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13345 DAG.getConstant(0, dl, MVT::i8));
13347 // CF and OF aren't always set the way we want. Determine which
13348 // of these we need.
13349 bool NeedCF = false;
13350 bool NeedOF = false;
13353 case X86::COND_A: case X86::COND_AE:
13354 case X86::COND_B: case X86::COND_BE:
13357 case X86::COND_G: case X86::COND_GE:
13358 case X86::COND_L: case X86::COND_LE:
13359 case X86::COND_O: case X86::COND_NO: {
13360 // Check if we really need to set the
13361 // Overflow flag. If NoSignedWrap is present
13362 // that is not actually needed.
13363 switch (Op->getOpcode()) {
13368 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13369 if (BinNode->Flags.hasNoSignedWrap())
13379 // See if we can use the EFLAGS value from the operand instead of
13380 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13381 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13382 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13383 // Emit a CMP with 0, which is the TEST pattern.
13384 //if (Op.getValueType() == MVT::i1)
13385 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13386 // DAG.getConstant(0, MVT::i1));
13387 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13388 DAG.getConstant(0, dl, Op.getValueType()));
13390 unsigned Opcode = 0;
13391 unsigned NumOperands = 0;
13393 // Truncate operations may prevent the merge of the SETCC instruction
13394 // and the arithmetic instruction before it. Attempt to truncate the operands
13395 // of the arithmetic instruction and use a reduced bit-width instruction.
13396 bool NeedTruncation = false;
13397 SDValue ArithOp = Op;
13398 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13399 SDValue Arith = Op->getOperand(0);
13400 // Both the trunc and the arithmetic op need to have one user each.
13401 if (Arith->hasOneUse())
13402 switch (Arith.getOpcode()) {
13409 NeedTruncation = true;
13415 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13416 // which may be the result of a CAST. We use the variable 'Op', which is the
13417 // non-casted variable when we check for possible users.
13418 switch (ArithOp.getOpcode()) {
13420 // Due to an isel shortcoming, be conservative if this add is likely to be
13421 // selected as part of a load-modify-store instruction. When the root node
13422 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13423 // uses of other nodes in the match, such as the ADD in this case. This
13424 // leads to the ADD being left around and reselected, with the result being
13425 // two adds in the output. Alas, even if none our users are stores, that
13426 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13427 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13428 // climbing the DAG back to the root, and it doesn't seem to be worth the
13430 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13431 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13432 if (UI->getOpcode() != ISD::CopyToReg &&
13433 UI->getOpcode() != ISD::SETCC &&
13434 UI->getOpcode() != ISD::STORE)
13437 if (ConstantSDNode *C =
13438 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13439 // An add of one will be selected as an INC.
13440 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13441 Opcode = X86ISD::INC;
13446 // An add of negative one (subtract of one) will be selected as a DEC.
13447 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13448 Opcode = X86ISD::DEC;
13454 // Otherwise use a regular EFLAGS-setting add.
13455 Opcode = X86ISD::ADD;
13460 // If we have a constant logical shift that's only used in a comparison
13461 // against zero turn it into an equivalent AND. This allows turning it into
13462 // a TEST instruction later.
13463 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13464 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13465 EVT VT = Op.getValueType();
13466 unsigned BitWidth = VT.getSizeInBits();
13467 unsigned ShAmt = Op->getConstantOperandVal(1);
13468 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13470 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13471 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13472 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13473 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13475 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13476 DAG.getConstant(Mask, dl, VT));
13477 DAG.ReplaceAllUsesWith(Op, New);
13483 // If the primary and result isn't used, don't bother using X86ISD::AND,
13484 // because a TEST instruction will be better.
13485 if (!hasNonFlagsUse(Op))
13491 // Due to the ISEL shortcoming noted above, be conservative if this op is
13492 // likely to be selected as part of a load-modify-store instruction.
13493 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13494 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13495 if (UI->getOpcode() == ISD::STORE)
13498 // Otherwise use a regular EFLAGS-setting instruction.
13499 switch (ArithOp.getOpcode()) {
13500 default: llvm_unreachable("unexpected operator!");
13501 case ISD::SUB: Opcode = X86ISD::SUB; break;
13502 case ISD::XOR: Opcode = X86ISD::XOR; break;
13503 case ISD::AND: Opcode = X86ISD::AND; break;
13505 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13506 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13507 if (EFLAGS.getNode())
13510 Opcode = X86ISD::OR;
13524 return SDValue(Op.getNode(), 1);
13530 // If we found that truncation is beneficial, perform the truncation and
13532 if (NeedTruncation) {
13533 EVT VT = Op.getValueType();
13534 SDValue WideVal = Op->getOperand(0);
13535 EVT WideVT = WideVal.getValueType();
13536 unsigned ConvertedOp = 0;
13537 // Use a target machine opcode to prevent further DAGCombine
13538 // optimizations that may separate the arithmetic operations
13539 // from the setcc node.
13540 switch (WideVal.getOpcode()) {
13542 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13543 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13544 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13545 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13546 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13550 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13551 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13552 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13553 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13554 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13560 // Emit a CMP with 0, which is the TEST pattern.
13561 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13562 DAG.getConstant(0, dl, Op.getValueType()));
13564 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13565 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13567 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13568 DAG.ReplaceAllUsesWith(Op, New);
13569 return SDValue(New.getNode(), 1);
13572 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13574 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13575 SDLoc dl, SelectionDAG &DAG) const {
13576 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13577 if (C->getAPIntValue() == 0)
13578 return EmitTest(Op0, X86CC, dl, DAG);
13580 if (Op0.getValueType() == MVT::i1)
13581 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13584 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13585 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13586 // Do the comparison at i32 if it's smaller, besides the Atom case.
13587 // This avoids subregister aliasing issues. Keep the smaller reference
13588 // if we're optimizing for size, however, as that'll allow better folding
13589 // of memory operations.
13590 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13591 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13592 !Subtarget->isAtom()) {
13593 unsigned ExtendOp =
13594 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13595 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13596 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13598 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13599 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13600 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13602 return SDValue(Sub.getNode(), 1);
13604 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13607 /// Convert a comparison if required by the subtarget.
13608 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13609 SelectionDAG &DAG) const {
13610 // If the subtarget does not support the FUCOMI instruction, floating-point
13611 // comparisons have to be converted.
13612 if (Subtarget->hasCMov() ||
13613 Cmp.getOpcode() != X86ISD::CMP ||
13614 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13615 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13618 // The instruction selector will select an FUCOM instruction instead of
13619 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13620 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13621 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13623 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13624 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13625 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13626 DAG.getConstant(8, dl, MVT::i8));
13627 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13628 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13631 /// The minimum architected relative accuracy is 2^-12. We need one
13632 /// Newton-Raphson step to have a good float result (24 bits of precision).
13633 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13634 DAGCombinerInfo &DCI,
13635 unsigned &RefinementSteps,
13636 bool &UseOneConstNR) const {
13637 EVT VT = Op.getValueType();
13638 const char *RecipOp;
13640 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13641 // TODO: Add support for AVX512 (v16f32).
13642 // It is likely not profitable to do this for f64 because a double-precision
13643 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13644 // instructions: convert to single, rsqrtss, convert back to double, refine
13645 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13646 // along with FMA, this could be a throughput win.
13647 if (VT == MVT::f32 && Subtarget->hasSSE1())
13649 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13650 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13651 RecipOp = "vec-sqrtf";
13655 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13656 if (!Recips.isEnabled(RecipOp))
13659 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13660 UseOneConstNR = false;
13661 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13664 /// The minimum architected relative accuracy is 2^-12. We need one
13665 /// Newton-Raphson step to have a good float result (24 bits of precision).
13666 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13667 DAGCombinerInfo &DCI,
13668 unsigned &RefinementSteps) const {
13669 EVT VT = Op.getValueType();
13670 const char *RecipOp;
13672 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13673 // TODO: Add support for AVX512 (v16f32).
13674 // It is likely not profitable to do this for f64 because a double-precision
13675 // reciprocal estimate with refinement on x86 prior to FMA requires
13676 // 15 instructions: convert to single, rcpss, convert back to double, refine
13677 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13678 // along with FMA, this could be a throughput win.
13679 if (VT == MVT::f32 && Subtarget->hasSSE1())
13681 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13682 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13683 RecipOp = "vec-divf";
13687 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13688 if (!Recips.isEnabled(RecipOp))
13691 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13692 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13695 /// If we have at least two divisions that use the same divisor, convert to
13696 /// multplication by a reciprocal. This may need to be adjusted for a given
13697 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13698 /// This is because we still need one division to calculate the reciprocal and
13699 /// then we need two multiplies by that reciprocal as replacements for the
13700 /// original divisions.
13701 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13705 static bool isAllOnes(SDValue V) {
13706 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13707 return C && C->isAllOnesValue();
13710 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13711 /// if it's possible.
13712 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13713 SDLoc dl, SelectionDAG &DAG) const {
13714 SDValue Op0 = And.getOperand(0);
13715 SDValue Op1 = And.getOperand(1);
13716 if (Op0.getOpcode() == ISD::TRUNCATE)
13717 Op0 = Op0.getOperand(0);
13718 if (Op1.getOpcode() == ISD::TRUNCATE)
13719 Op1 = Op1.getOperand(0);
13722 if (Op1.getOpcode() == ISD::SHL)
13723 std::swap(Op0, Op1);
13724 if (Op0.getOpcode() == ISD::SHL) {
13725 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13726 if (And00C->getZExtValue() == 1) {
13727 // If we looked past a truncate, check that it's only truncating away
13729 unsigned BitWidth = Op0.getValueSizeInBits();
13730 unsigned AndBitWidth = And.getValueSizeInBits();
13731 if (BitWidth > AndBitWidth) {
13733 DAG.computeKnownBits(Op0, Zeros, Ones);
13734 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13738 RHS = Op0.getOperand(1);
13740 } else if (Op1.getOpcode() == ISD::Constant) {
13741 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13742 uint64_t AndRHSVal = AndRHS->getZExtValue();
13743 SDValue AndLHS = Op0;
13745 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13746 LHS = AndLHS.getOperand(0);
13747 RHS = AndLHS.getOperand(1);
13750 // Use BT if the immediate can't be encoded in a TEST instruction.
13751 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13753 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13757 if (LHS.getNode()) {
13758 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13759 // instruction. Since the shift amount is in-range-or-undefined, we know
13760 // that doing a bittest on the i32 value is ok. We extend to i32 because
13761 // the encoding for the i16 version is larger than the i32 version.
13762 // Also promote i16 to i32 for performance / code size reason.
13763 if (LHS.getValueType() == MVT::i8 ||
13764 LHS.getValueType() == MVT::i16)
13765 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13767 // If the operand types disagree, extend the shift amount to match. Since
13768 // BT ignores high bits (like shifts) we can use anyextend.
13769 if (LHS.getValueType() != RHS.getValueType())
13770 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13772 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13773 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13774 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13775 DAG.getConstant(Cond, dl, MVT::i8), BT);
13781 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13783 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13788 // SSE Condition code mapping:
13797 switch (SetCCOpcode) {
13798 default: llvm_unreachable("Unexpected SETCC condition");
13800 case ISD::SETEQ: SSECC = 0; break;
13802 case ISD::SETGT: Swap = true; // Fallthrough
13804 case ISD::SETOLT: SSECC = 1; break;
13806 case ISD::SETGE: Swap = true; // Fallthrough
13808 case ISD::SETOLE: SSECC = 2; break;
13809 case ISD::SETUO: SSECC = 3; break;
13811 case ISD::SETNE: SSECC = 4; break;
13812 case ISD::SETULE: Swap = true; // Fallthrough
13813 case ISD::SETUGE: SSECC = 5; break;
13814 case ISD::SETULT: Swap = true; // Fallthrough
13815 case ISD::SETUGT: SSECC = 6; break;
13816 case ISD::SETO: SSECC = 7; break;
13818 case ISD::SETONE: SSECC = 8; break;
13821 std::swap(Op0, Op1);
13826 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13827 // ones, and then concatenate the result back.
13828 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13829 MVT VT = Op.getSimpleValueType();
13831 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13832 "Unsupported value type for operation");
13834 unsigned NumElems = VT.getVectorNumElements();
13836 SDValue CC = Op.getOperand(2);
13838 // Extract the LHS vectors
13839 SDValue LHS = Op.getOperand(0);
13840 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13841 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13843 // Extract the RHS vectors
13844 SDValue RHS = Op.getOperand(1);
13845 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13846 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13848 // Issue the operation on the smaller types and concatenate the result back
13849 MVT EltVT = VT.getVectorElementType();
13850 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13851 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13852 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13853 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13856 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13857 SDValue Op0 = Op.getOperand(0);
13858 SDValue Op1 = Op.getOperand(1);
13859 SDValue CC = Op.getOperand(2);
13860 MVT VT = Op.getSimpleValueType();
13863 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13864 "Unexpected type for boolean compare operation");
13865 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13866 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13867 DAG.getConstant(-1, dl, VT));
13868 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13869 DAG.getConstant(-1, dl, VT));
13870 switch (SetCCOpcode) {
13871 default: llvm_unreachable("Unexpected SETCC condition");
13873 // (x == y) -> ~(x ^ y)
13874 return DAG.getNode(ISD::XOR, dl, VT,
13875 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13876 DAG.getConstant(-1, dl, VT));
13878 // (x != y) -> (x ^ y)
13879 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13882 // (x > y) -> (x & ~y)
13883 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13886 // (x < y) -> (~x & y)
13887 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13890 // (x <= y) -> (~x | y)
13891 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13894 // (x >=y) -> (x | ~y)
13895 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13899 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13900 const X86Subtarget *Subtarget) {
13901 SDValue Op0 = Op.getOperand(0);
13902 SDValue Op1 = Op.getOperand(1);
13903 SDValue CC = Op.getOperand(2);
13904 MVT VT = Op.getSimpleValueType();
13907 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13908 Op.getValueType().getScalarType() == MVT::i1 &&
13909 "Cannot set masked compare for this operation");
13911 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13913 bool Unsigned = false;
13916 switch (SetCCOpcode) {
13917 default: llvm_unreachable("Unexpected SETCC condition");
13918 case ISD::SETNE: SSECC = 4; break;
13919 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13920 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13921 case ISD::SETLT: Swap = true; //fall-through
13922 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13923 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13924 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13925 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13926 case ISD::SETULE: Unsigned = true; //fall-through
13927 case ISD::SETLE: SSECC = 2; break;
13931 std::swap(Op0, Op1);
13933 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13934 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13935 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13936 DAG.getConstant(SSECC, dl, MVT::i8));
13939 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13940 /// operand \p Op1. If non-trivial (for example because it's not constant)
13941 /// return an empty value.
13942 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13944 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13948 MVT VT = Op1.getSimpleValueType();
13949 MVT EVT = VT.getVectorElementType();
13950 unsigned n = VT.getVectorNumElements();
13951 SmallVector<SDValue, 8> ULTOp1;
13953 for (unsigned i = 0; i < n; ++i) {
13954 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13955 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13958 // Avoid underflow.
13959 APInt Val = Elt->getAPIntValue();
13963 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13966 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13969 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13970 SelectionDAG &DAG) {
13971 SDValue Op0 = Op.getOperand(0);
13972 SDValue Op1 = Op.getOperand(1);
13973 SDValue CC = Op.getOperand(2);
13974 MVT VT = Op.getSimpleValueType();
13975 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13976 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13981 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13982 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13985 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13986 unsigned Opc = X86ISD::CMPP;
13987 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13988 assert(VT.getVectorNumElements() <= 16);
13989 Opc = X86ISD::CMPM;
13991 // In the two special cases we can't handle, emit two comparisons.
13994 unsigned CombineOpc;
13995 if (SetCCOpcode == ISD::SETUEQ) {
13996 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13998 assert(SetCCOpcode == ISD::SETONE);
13999 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14002 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14003 DAG.getConstant(CC0, dl, MVT::i8));
14004 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14005 DAG.getConstant(CC1, dl, MVT::i8));
14006 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14008 // Handle all other FP comparisons here.
14009 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14010 DAG.getConstant(SSECC, dl, MVT::i8));
14013 // Break 256-bit integer vector compare into smaller ones.
14014 if (VT.is256BitVector() && !Subtarget->hasInt256())
14015 return Lower256IntVSETCC(Op, DAG);
14017 EVT OpVT = Op1.getValueType();
14018 if (OpVT.getVectorElementType() == MVT::i1)
14019 return LowerBoolVSETCC_AVX512(Op, DAG);
14021 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14022 if (Subtarget->hasAVX512()) {
14023 if (Op1.getValueType().is512BitVector() ||
14024 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14025 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14026 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14028 // In AVX-512 architecture setcc returns mask with i1 elements,
14029 // But there is no compare instruction for i8 and i16 elements in KNL.
14030 // We are not talking about 512-bit operands in this case, these
14031 // types are illegal.
14033 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14034 OpVT.getVectorElementType().getSizeInBits() >= 8))
14035 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14036 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14039 // We are handling one of the integer comparisons here. Since SSE only has
14040 // GT and EQ comparisons for integer, swapping operands and multiple
14041 // operations may be required for some comparisons.
14043 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14044 bool Subus = false;
14046 switch (SetCCOpcode) {
14047 default: llvm_unreachable("Unexpected SETCC condition");
14048 case ISD::SETNE: Invert = true;
14049 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14050 case ISD::SETLT: Swap = true;
14051 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14052 case ISD::SETGE: Swap = true;
14053 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14054 Invert = true; break;
14055 case ISD::SETULT: Swap = true;
14056 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14057 FlipSigns = true; break;
14058 case ISD::SETUGE: Swap = true;
14059 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14060 FlipSigns = true; Invert = true; break;
14063 // Special case: Use min/max operations for SETULE/SETUGE
14064 MVT VET = VT.getVectorElementType();
14066 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14067 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14070 switch (SetCCOpcode) {
14072 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14073 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14076 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14079 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14080 if (!MinMax && hasSubus) {
14081 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14083 // t = psubus Op0, Op1
14084 // pcmpeq t, <0..0>
14085 switch (SetCCOpcode) {
14087 case ISD::SETULT: {
14088 // If the comparison is against a constant we can turn this into a
14089 // setule. With psubus, setule does not require a swap. This is
14090 // beneficial because the constant in the register is no longer
14091 // destructed as the destination so it can be hoisted out of a loop.
14092 // Only do this pre-AVX since vpcmp* is no longer destructive.
14093 if (Subtarget->hasAVX())
14095 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14096 if (ULEOp1.getNode()) {
14098 Subus = true; Invert = false; Swap = false;
14102 // Psubus is better than flip-sign because it requires no inversion.
14103 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14104 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14108 Opc = X86ISD::SUBUS;
14114 std::swap(Op0, Op1);
14116 // Check that the operation in question is available (most are plain SSE2,
14117 // but PCMPGTQ and PCMPEQQ have different requirements).
14118 if (VT == MVT::v2i64) {
14119 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14120 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14122 // First cast everything to the right type.
14123 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14124 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14126 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14127 // bits of the inputs before performing those operations. The lower
14128 // compare is always unsigned.
14131 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14133 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14134 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14135 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14136 Sign, Zero, Sign, Zero);
14138 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14139 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14141 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14142 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14143 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14145 // Create masks for only the low parts/high parts of the 64 bit integers.
14146 static const int MaskHi[] = { 1, 1, 3, 3 };
14147 static const int MaskLo[] = { 0, 0, 2, 2 };
14148 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14149 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14150 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14152 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14153 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14156 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14158 return DAG.getBitcast(VT, Result);
14161 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14162 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14163 // pcmpeqd + pshufd + pand.
14164 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14166 // First cast everything to the right type.
14167 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14168 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14171 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14173 // Make sure the lower and upper halves are both all-ones.
14174 static const int Mask[] = { 1, 0, 3, 2 };
14175 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14176 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14179 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14181 return DAG.getBitcast(VT, Result);
14185 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14186 // bits of the inputs before performing those operations.
14188 EVT EltVT = VT.getVectorElementType();
14189 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14191 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14192 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14195 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14197 // If the logical-not of the result is required, perform that now.
14199 Result = DAG.getNOT(dl, Result, VT);
14202 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14205 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14206 getZeroVector(VT, Subtarget, DAG, dl));
14211 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14213 MVT VT = Op.getSimpleValueType();
14215 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14217 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14218 && "SetCC type must be 8-bit or 1-bit integer");
14219 SDValue Op0 = Op.getOperand(0);
14220 SDValue Op1 = Op.getOperand(1);
14222 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14224 // Optimize to BT if possible.
14225 // Lower (X & (1 << N)) == 0 to BT(X, N).
14226 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14227 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14228 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14229 Op1.getOpcode() == ISD::Constant &&
14230 cast<ConstantSDNode>(Op1)->isNullValue() &&
14231 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14232 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14233 if (NewSetCC.getNode()) {
14235 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14240 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14242 if (Op1.getOpcode() == ISD::Constant &&
14243 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14244 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14245 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14247 // If the input is a setcc, then reuse the input setcc or use a new one with
14248 // the inverted condition.
14249 if (Op0.getOpcode() == X86ISD::SETCC) {
14250 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14251 bool Invert = (CC == ISD::SETNE) ^
14252 cast<ConstantSDNode>(Op1)->isNullValue();
14256 CCode = X86::GetOppositeBranchCondition(CCode);
14257 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14258 DAG.getConstant(CCode, dl, MVT::i8),
14259 Op0.getOperand(1));
14261 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14265 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14266 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14267 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14269 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14270 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14273 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14274 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14275 if (X86CC == X86::COND_INVALID)
14278 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14279 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14280 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14281 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14283 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14287 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14288 static bool isX86LogicalCmp(SDValue Op) {
14289 unsigned Opc = Op.getNode()->getOpcode();
14290 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14291 Opc == X86ISD::SAHF)
14293 if (Op.getResNo() == 1 &&
14294 (Opc == X86ISD::ADD ||
14295 Opc == X86ISD::SUB ||
14296 Opc == X86ISD::ADC ||
14297 Opc == X86ISD::SBB ||
14298 Opc == X86ISD::SMUL ||
14299 Opc == X86ISD::UMUL ||
14300 Opc == X86ISD::INC ||
14301 Opc == X86ISD::DEC ||
14302 Opc == X86ISD::OR ||
14303 Opc == X86ISD::XOR ||
14304 Opc == X86ISD::AND))
14307 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14313 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14314 if (V.getOpcode() != ISD::TRUNCATE)
14317 SDValue VOp0 = V.getOperand(0);
14318 unsigned InBits = VOp0.getValueSizeInBits();
14319 unsigned Bits = V.getValueSizeInBits();
14320 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14323 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14324 bool addTest = true;
14325 SDValue Cond = Op.getOperand(0);
14326 SDValue Op1 = Op.getOperand(1);
14327 SDValue Op2 = Op.getOperand(2);
14329 EVT VT = Op1.getValueType();
14332 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14333 // are available or VBLENDV if AVX is available.
14334 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14335 if (Cond.getOpcode() == ISD::SETCC &&
14336 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14337 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14338 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14339 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14340 int SSECC = translateX86FSETCC(
14341 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14344 if (Subtarget->hasAVX512()) {
14345 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14346 DAG.getConstant(SSECC, DL, MVT::i8));
14347 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14350 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14351 DAG.getConstant(SSECC, DL, MVT::i8));
14353 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14354 // of 3 logic instructions for size savings and potentially speed.
14355 // Unfortunately, there is no scalar form of VBLENDV.
14357 // If either operand is a constant, don't try this. We can expect to
14358 // optimize away at least one of the logic instructions later in that
14359 // case, so that sequence would be faster than a variable blend.
14361 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14362 // uses XMM0 as the selection register. That may need just as many
14363 // instructions as the AND/ANDN/OR sequence due to register moves, so
14366 if (Subtarget->hasAVX() &&
14367 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14369 // Convert to vectors, do a VSELECT, and convert back to scalar.
14370 // All of the conversions should be optimized away.
14372 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14373 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14374 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14375 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14377 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14378 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14380 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14382 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14383 VSel, DAG.getIntPtrConstant(0, DL));
14385 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14386 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14387 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14391 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
14393 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14394 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14395 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14396 Op1Scalar = Op1.getOperand(0);
14398 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14399 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14400 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14401 Op2Scalar = Op2.getOperand(0);
14402 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14403 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14404 Op1Scalar.getValueType(),
14405 Cond, Op1Scalar, Op2Scalar);
14406 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14407 return DAG.getBitcast(VT, newSelect);
14408 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14409 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14410 DAG.getIntPtrConstant(0, DL));
14414 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14415 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14416 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14417 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14418 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14419 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14420 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14422 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14425 if (Cond.getOpcode() == ISD::SETCC) {
14426 SDValue NewCond = LowerSETCC(Cond, DAG);
14427 if (NewCond.getNode())
14431 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14432 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14433 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14434 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14435 if (Cond.getOpcode() == X86ISD::SETCC &&
14436 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14437 isZero(Cond.getOperand(1).getOperand(1))) {
14438 SDValue Cmp = Cond.getOperand(1);
14440 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14442 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14443 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14444 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14446 SDValue CmpOp0 = Cmp.getOperand(0);
14447 // Apply further optimizations for special cases
14448 // (select (x != 0), -1, 0) -> neg & sbb
14449 // (select (x == 0), 0, -1) -> neg & sbb
14450 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14451 if (YC->isNullValue() &&
14452 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14453 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14454 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14455 DAG.getConstant(0, DL,
14456 CmpOp0.getValueType()),
14458 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14459 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14460 SDValue(Neg.getNode(), 1));
14464 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14465 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14466 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14468 SDValue Res = // Res = 0 or -1.
14469 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14470 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14472 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14473 Res = DAG.getNOT(DL, Res, Res.getValueType());
14475 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14476 if (!N2C || !N2C->isNullValue())
14477 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14482 // Look past (and (setcc_carry (cmp ...)), 1).
14483 if (Cond.getOpcode() == ISD::AND &&
14484 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14485 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14486 if (C && C->getAPIntValue() == 1)
14487 Cond = Cond.getOperand(0);
14490 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14491 // setting operand in place of the X86ISD::SETCC.
14492 unsigned CondOpcode = Cond.getOpcode();
14493 if (CondOpcode == X86ISD::SETCC ||
14494 CondOpcode == X86ISD::SETCC_CARRY) {
14495 CC = Cond.getOperand(0);
14497 SDValue Cmp = Cond.getOperand(1);
14498 unsigned Opc = Cmp.getOpcode();
14499 MVT VT = Op.getSimpleValueType();
14501 bool IllegalFPCMov = false;
14502 if (VT.isFloatingPoint() && !VT.isVector() &&
14503 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14504 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14506 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14507 Opc == X86ISD::BT) { // FIXME
14511 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14512 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14513 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14514 Cond.getOperand(0).getValueType() != MVT::i8)) {
14515 SDValue LHS = Cond.getOperand(0);
14516 SDValue RHS = Cond.getOperand(1);
14517 unsigned X86Opcode;
14520 switch (CondOpcode) {
14521 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14522 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14523 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14524 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14525 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14526 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14527 default: llvm_unreachable("unexpected overflowing operator");
14529 if (CondOpcode == ISD::UMULO)
14530 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14533 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14535 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14537 if (CondOpcode == ISD::UMULO)
14538 Cond = X86Op.getValue(2);
14540 Cond = X86Op.getValue(1);
14542 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14547 // Look past the truncate if the high bits are known zero.
14548 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14549 Cond = Cond.getOperand(0);
14551 // We know the result of AND is compared against zero. Try to match
14553 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14554 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14555 if (NewSetCC.getNode()) {
14556 CC = NewSetCC.getOperand(0);
14557 Cond = NewSetCC.getOperand(1);
14564 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14565 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14568 // a < b ? -1 : 0 -> RES = ~setcc_carry
14569 // a < b ? 0 : -1 -> RES = setcc_carry
14570 // a >= b ? -1 : 0 -> RES = setcc_carry
14571 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14572 if (Cond.getOpcode() == X86ISD::SUB) {
14573 Cond = ConvertCmpIfNecessary(Cond, DAG);
14574 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14576 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14577 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14578 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14579 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14581 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14582 return DAG.getNOT(DL, Res, Res.getValueType());
14587 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14588 // widen the cmov and push the truncate through. This avoids introducing a new
14589 // branch during isel and doesn't add any extensions.
14590 if (Op.getValueType() == MVT::i8 &&
14591 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14592 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14593 if (T1.getValueType() == T2.getValueType() &&
14594 // Blacklist CopyFromReg to avoid partial register stalls.
14595 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14596 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14597 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14598 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14602 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14603 // condition is true.
14604 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14605 SDValue Ops[] = { Op2, Op1, CC, Cond };
14606 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14609 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14610 const X86Subtarget *Subtarget,
14611 SelectionDAG &DAG) {
14612 MVT VT = Op->getSimpleValueType(0);
14613 SDValue In = Op->getOperand(0);
14614 MVT InVT = In.getSimpleValueType();
14615 MVT VTElt = VT.getVectorElementType();
14616 MVT InVTElt = InVT.getVectorElementType();
14620 if ((InVTElt == MVT::i1) &&
14621 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14622 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14624 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14625 VTElt.getSizeInBits() <= 16)) ||
14627 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14628 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14630 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14631 VTElt.getSizeInBits() >= 32))))
14632 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14634 unsigned int NumElts = VT.getVectorNumElements();
14636 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14639 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14640 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14641 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14642 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14645 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14646 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14648 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14651 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14653 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14654 if (VT.is512BitVector())
14656 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14659 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14660 const X86Subtarget *Subtarget,
14661 SelectionDAG &DAG) {
14662 SDValue In = Op->getOperand(0);
14663 MVT VT = Op->getSimpleValueType(0);
14664 MVT InVT = In.getSimpleValueType();
14665 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14667 MVT InSVT = InVT.getScalarType();
14668 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14670 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14672 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14677 // SSE41 targets can use the pmovsx* instructions directly.
14678 if (Subtarget->hasSSE41())
14679 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14681 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14685 // As SRAI is only available on i16/i32 types, we expand only up to i32
14686 // and handle i64 separately.
14687 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14688 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14689 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14690 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14691 Curr = DAG.getBitcast(CurrVT, Curr);
14694 SDValue SignExt = Curr;
14695 if (CurrVT != InVT) {
14696 unsigned SignExtShift =
14697 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14698 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14699 DAG.getConstant(SignExtShift, dl, MVT::i8));
14705 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14706 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14707 DAG.getConstant(31, dl, MVT::i8));
14708 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14709 return DAG.getBitcast(VT, Ext);
14715 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14716 SelectionDAG &DAG) {
14717 MVT VT = Op->getSimpleValueType(0);
14718 SDValue In = Op->getOperand(0);
14719 MVT InVT = In.getSimpleValueType();
14722 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14723 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14725 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14726 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14727 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14730 if (Subtarget->hasInt256())
14731 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14733 // Optimize vectors in AVX mode
14734 // Sign extend v8i16 to v8i32 and
14737 // Divide input vector into two parts
14738 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14739 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14740 // concat the vectors to original VT
14742 unsigned NumElems = InVT.getVectorNumElements();
14743 SDValue Undef = DAG.getUNDEF(InVT);
14745 SmallVector<int,8> ShufMask1(NumElems, -1);
14746 for (unsigned i = 0; i != NumElems/2; ++i)
14749 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14751 SmallVector<int,8> ShufMask2(NumElems, -1);
14752 for (unsigned i = 0; i != NumElems/2; ++i)
14753 ShufMask2[i] = i + NumElems/2;
14755 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14757 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14758 VT.getVectorNumElements()/2);
14760 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14761 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14763 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14766 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14767 // may emit an illegal shuffle but the expansion is still better than scalar
14768 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14769 // we'll emit a shuffle and a arithmetic shift.
14770 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14771 // TODO: It is possible to support ZExt by zeroing the undef values during
14772 // the shuffle phase or after the shuffle.
14773 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14774 SelectionDAG &DAG) {
14775 MVT RegVT = Op.getSimpleValueType();
14776 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14777 assert(RegVT.isInteger() &&
14778 "We only custom lower integer vector sext loads.");
14780 // Nothing useful we can do without SSE2 shuffles.
14781 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14783 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14785 EVT MemVT = Ld->getMemoryVT();
14786 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14787 unsigned RegSz = RegVT.getSizeInBits();
14789 ISD::LoadExtType Ext = Ld->getExtensionType();
14791 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14792 && "Only anyext and sext are currently implemented.");
14793 assert(MemVT != RegVT && "Cannot extend to the same type");
14794 assert(MemVT.isVector() && "Must load a vector from memory");
14796 unsigned NumElems = RegVT.getVectorNumElements();
14797 unsigned MemSz = MemVT.getSizeInBits();
14798 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14800 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14801 // The only way in which we have a legal 256-bit vector result but not the
14802 // integer 256-bit operations needed to directly lower a sextload is if we
14803 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14804 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14805 // correctly legalized. We do this late to allow the canonical form of
14806 // sextload to persist throughout the rest of the DAG combiner -- it wants
14807 // to fold together any extensions it can, and so will fuse a sign_extend
14808 // of an sextload into a sextload targeting a wider value.
14810 if (MemSz == 128) {
14811 // Just switch this to a normal load.
14812 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14813 "it must be a legal 128-bit vector "
14815 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14816 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14817 Ld->isInvariant(), Ld->getAlignment());
14819 assert(MemSz < 128 &&
14820 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14821 // Do an sext load to a 128-bit vector type. We want to use the same
14822 // number of elements, but elements half as wide. This will end up being
14823 // recursively lowered by this routine, but will succeed as we definitely
14824 // have all the necessary features if we're using AVX1.
14826 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14827 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14829 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14830 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14831 Ld->isNonTemporal(), Ld->isInvariant(),
14832 Ld->getAlignment());
14835 // Replace chain users with the new chain.
14836 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14837 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14839 // Finally, do a normal sign-extend to the desired register.
14840 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14843 // All sizes must be a power of two.
14844 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14845 "Non-power-of-two elements are not custom lowered!");
14847 // Attempt to load the original value using scalar loads.
14848 // Find the largest scalar type that divides the total loaded size.
14849 MVT SclrLoadTy = MVT::i8;
14850 for (MVT Tp : MVT::integer_valuetypes()) {
14851 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14856 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14857 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14859 SclrLoadTy = MVT::f64;
14861 // Calculate the number of scalar loads that we need to perform
14862 // in order to load our vector from memory.
14863 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14865 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14866 "Can only lower sext loads with a single scalar load!");
14868 unsigned loadRegZize = RegSz;
14869 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14872 // Represent our vector as a sequence of elements which are the
14873 // largest scalar that we can load.
14874 EVT LoadUnitVecVT = EVT::getVectorVT(
14875 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14877 // Represent the data using the same element type that is stored in
14878 // memory. In practice, we ''widen'' MemVT.
14880 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14881 loadRegZize / MemVT.getScalarType().getSizeInBits());
14883 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14884 "Invalid vector type");
14886 // We can't shuffle using an illegal type.
14887 assert(TLI.isTypeLegal(WideVecVT) &&
14888 "We only lower types that form legal widened vector types");
14890 SmallVector<SDValue, 8> Chains;
14891 SDValue Ptr = Ld->getBasePtr();
14892 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
14893 TLI.getPointerTy(DAG.getDataLayout()));
14894 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14896 for (unsigned i = 0; i < NumLoads; ++i) {
14897 // Perform a single load.
14898 SDValue ScalarLoad =
14899 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14900 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14901 Ld->getAlignment());
14902 Chains.push_back(ScalarLoad.getValue(1));
14903 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14904 // another round of DAGCombining.
14906 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14908 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14909 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14911 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14914 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14916 // Bitcast the loaded value to a vector of the original element type, in
14917 // the size of the target vector type.
14918 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
14919 unsigned SizeRatio = RegSz / MemSz;
14921 if (Ext == ISD::SEXTLOAD) {
14922 // If we have SSE4.1, we can directly emit a VSEXT node.
14923 if (Subtarget->hasSSE41()) {
14924 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14925 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14929 // Otherwise we'll shuffle the small elements in the high bits of the
14930 // larger type and perform an arithmetic shift. If the shift is not legal
14931 // it's better to scalarize.
14932 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14933 "We can't implement a sext load without an arithmetic right shift!");
14935 // Redistribute the loaded elements into the different locations.
14936 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14937 for (unsigned i = 0; i != NumElems; ++i)
14938 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14940 SDValue Shuff = DAG.getVectorShuffle(
14941 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14943 Shuff = DAG.getBitcast(RegVT, Shuff);
14945 // Build the arithmetic shift.
14946 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14947 MemVT.getVectorElementType().getSizeInBits();
14949 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14950 DAG.getConstant(Amt, dl, RegVT));
14952 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14956 // Redistribute the loaded elements into the different locations.
14957 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14958 for (unsigned i = 0; i != NumElems; ++i)
14959 ShuffleVec[i * SizeRatio] = i;
14961 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14962 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14964 // Bitcast to the requested type.
14965 Shuff = DAG.getBitcast(RegVT, Shuff);
14966 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14970 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14971 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14972 // from the AND / OR.
14973 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14974 Opc = Op.getOpcode();
14975 if (Opc != ISD::OR && Opc != ISD::AND)
14977 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14978 Op.getOperand(0).hasOneUse() &&
14979 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14980 Op.getOperand(1).hasOneUse());
14983 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14984 // 1 and that the SETCC node has a single use.
14985 static bool isXor1OfSetCC(SDValue Op) {
14986 if (Op.getOpcode() != ISD::XOR)
14988 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14989 if (N1C && N1C->getAPIntValue() == 1) {
14990 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14991 Op.getOperand(0).hasOneUse();
14996 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14997 bool addTest = true;
14998 SDValue Chain = Op.getOperand(0);
14999 SDValue Cond = Op.getOperand(1);
15000 SDValue Dest = Op.getOperand(2);
15003 bool Inverted = false;
15005 if (Cond.getOpcode() == ISD::SETCC) {
15006 // Check for setcc([su]{add,sub,mul}o == 0).
15007 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15008 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15009 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15010 Cond.getOperand(0).getResNo() == 1 &&
15011 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15012 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15013 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15014 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15015 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15016 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15018 Cond = Cond.getOperand(0);
15020 SDValue NewCond = LowerSETCC(Cond, DAG);
15021 if (NewCond.getNode())
15026 // FIXME: LowerXALUO doesn't handle these!!
15027 else if (Cond.getOpcode() == X86ISD::ADD ||
15028 Cond.getOpcode() == X86ISD::SUB ||
15029 Cond.getOpcode() == X86ISD::SMUL ||
15030 Cond.getOpcode() == X86ISD::UMUL)
15031 Cond = LowerXALUO(Cond, DAG);
15034 // Look pass (and (setcc_carry (cmp ...)), 1).
15035 if (Cond.getOpcode() == ISD::AND &&
15036 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15037 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15038 if (C && C->getAPIntValue() == 1)
15039 Cond = Cond.getOperand(0);
15042 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15043 // setting operand in place of the X86ISD::SETCC.
15044 unsigned CondOpcode = Cond.getOpcode();
15045 if (CondOpcode == X86ISD::SETCC ||
15046 CondOpcode == X86ISD::SETCC_CARRY) {
15047 CC = Cond.getOperand(0);
15049 SDValue Cmp = Cond.getOperand(1);
15050 unsigned Opc = Cmp.getOpcode();
15051 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15052 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15056 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15060 // These can only come from an arithmetic instruction with overflow,
15061 // e.g. SADDO, UADDO.
15062 Cond = Cond.getNode()->getOperand(1);
15068 CondOpcode = Cond.getOpcode();
15069 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15070 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15071 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15072 Cond.getOperand(0).getValueType() != MVT::i8)) {
15073 SDValue LHS = Cond.getOperand(0);
15074 SDValue RHS = Cond.getOperand(1);
15075 unsigned X86Opcode;
15078 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15079 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15081 switch (CondOpcode) {
15082 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15084 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15086 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15089 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15090 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15092 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15094 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15097 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15098 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15099 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15100 default: llvm_unreachable("unexpected overflowing operator");
15103 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15104 if (CondOpcode == ISD::UMULO)
15105 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15108 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15110 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15112 if (CondOpcode == ISD::UMULO)
15113 Cond = X86Op.getValue(2);
15115 Cond = X86Op.getValue(1);
15117 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15121 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15122 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15123 if (CondOpc == ISD::OR) {
15124 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15125 // two branches instead of an explicit OR instruction with a
15127 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15128 isX86LogicalCmp(Cmp)) {
15129 CC = Cond.getOperand(0).getOperand(0);
15130 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15131 Chain, Dest, CC, Cmp);
15132 CC = Cond.getOperand(1).getOperand(0);
15136 } else { // ISD::AND
15137 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15138 // two branches instead of an explicit AND instruction with a
15139 // separate test. However, we only do this if this block doesn't
15140 // have a fall-through edge, because this requires an explicit
15141 // jmp when the condition is false.
15142 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15143 isX86LogicalCmp(Cmp) &&
15144 Op.getNode()->hasOneUse()) {
15145 X86::CondCode CCode =
15146 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15147 CCode = X86::GetOppositeBranchCondition(CCode);
15148 CC = DAG.getConstant(CCode, dl, MVT::i8);
15149 SDNode *User = *Op.getNode()->use_begin();
15150 // Look for an unconditional branch following this conditional branch.
15151 // We need this because we need to reverse the successors in order
15152 // to implement FCMP_OEQ.
15153 if (User->getOpcode() == ISD::BR) {
15154 SDValue FalseBB = User->getOperand(1);
15156 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15157 assert(NewBR == User);
15161 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15162 Chain, Dest, CC, Cmp);
15163 X86::CondCode CCode =
15164 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15165 CCode = X86::GetOppositeBranchCondition(CCode);
15166 CC = DAG.getConstant(CCode, dl, MVT::i8);
15172 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15173 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15174 // It should be transformed during dag combiner except when the condition
15175 // is set by a arithmetics with overflow node.
15176 X86::CondCode CCode =
15177 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15178 CCode = X86::GetOppositeBranchCondition(CCode);
15179 CC = DAG.getConstant(CCode, dl, MVT::i8);
15180 Cond = Cond.getOperand(0).getOperand(1);
15182 } else if (Cond.getOpcode() == ISD::SETCC &&
15183 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15184 // For FCMP_OEQ, we can emit
15185 // two branches instead of an explicit AND instruction with a
15186 // separate test. However, we only do this if this block doesn't
15187 // have a fall-through edge, because this requires an explicit
15188 // jmp when the condition is false.
15189 if (Op.getNode()->hasOneUse()) {
15190 SDNode *User = *Op.getNode()->use_begin();
15191 // Look for an unconditional branch following this conditional branch.
15192 // We need this because we need to reverse the successors in order
15193 // to implement FCMP_OEQ.
15194 if (User->getOpcode() == ISD::BR) {
15195 SDValue FalseBB = User->getOperand(1);
15197 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15198 assert(NewBR == User);
15202 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15203 Cond.getOperand(0), Cond.getOperand(1));
15204 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15205 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15206 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15207 Chain, Dest, CC, Cmp);
15208 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15213 } else if (Cond.getOpcode() == ISD::SETCC &&
15214 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15215 // For FCMP_UNE, we can emit
15216 // two branches instead of an explicit AND instruction with a
15217 // separate test. However, we only do this if this block doesn't
15218 // have a fall-through edge, because this requires an explicit
15219 // jmp when the condition is false.
15220 if (Op.getNode()->hasOneUse()) {
15221 SDNode *User = *Op.getNode()->use_begin();
15222 // Look for an unconditional branch following this conditional branch.
15223 // We need this because we need to reverse the successors in order
15224 // to implement FCMP_UNE.
15225 if (User->getOpcode() == ISD::BR) {
15226 SDValue FalseBB = User->getOperand(1);
15228 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15229 assert(NewBR == User);
15232 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15233 Cond.getOperand(0), Cond.getOperand(1));
15234 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15235 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15236 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15237 Chain, Dest, CC, Cmp);
15238 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15248 // Look pass the truncate if the high bits are known zero.
15249 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15250 Cond = Cond.getOperand(0);
15252 // We know the result of AND is compared against zero. Try to match
15254 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15255 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15256 if (NewSetCC.getNode()) {
15257 CC = NewSetCC.getOperand(0);
15258 Cond = NewSetCC.getOperand(1);
15265 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15266 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15267 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15269 Cond = ConvertCmpIfNecessary(Cond, DAG);
15270 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15271 Chain, Dest, CC, Cond);
15274 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15275 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15276 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15277 // that the guard pages used by the OS virtual memory manager are allocated in
15278 // correct sequence.
15280 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15281 SelectionDAG &DAG) const {
15282 MachineFunction &MF = DAG.getMachineFunction();
15283 bool SplitStack = MF.shouldSplitStack();
15284 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15289 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15290 SDNode* Node = Op.getNode();
15292 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15293 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15294 " not tell us which reg is the stack pointer!");
15295 EVT VT = Node->getValueType(0);
15296 SDValue Tmp1 = SDValue(Node, 0);
15297 SDValue Tmp2 = SDValue(Node, 1);
15298 SDValue Tmp3 = Node->getOperand(2);
15299 SDValue Chain = Tmp1.getOperand(0);
15301 // Chain the dynamic stack allocation so that it doesn't modify the stack
15302 // pointer when other instructions are using the stack.
15303 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15306 SDValue Size = Tmp2.getOperand(1);
15307 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15308 Chain = SP.getValue(1);
15309 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15310 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15311 unsigned StackAlign = TFI.getStackAlignment();
15312 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15313 if (Align > StackAlign)
15314 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15315 DAG.getConstant(-(uint64_t)Align, dl, VT));
15316 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15318 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15319 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15322 SDValue Ops[2] = { Tmp1, Tmp2 };
15323 return DAG.getMergeValues(Ops, dl);
15327 SDValue Chain = Op.getOperand(0);
15328 SDValue Size = Op.getOperand(1);
15329 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15330 EVT VT = Op.getNode()->getValueType(0);
15332 bool Is64Bit = Subtarget->is64Bit();
15333 MVT SPTy = getPointerTy(DAG.getDataLayout());
15336 MachineRegisterInfo &MRI = MF.getRegInfo();
15339 // The 64 bit implementation of segmented stacks needs to clobber both r10
15340 // r11. This makes it impossible to use it along with nested parameters.
15341 const Function *F = MF.getFunction();
15343 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15345 if (I->hasNestAttr())
15346 report_fatal_error("Cannot use segmented stacks with functions that "
15347 "have nested arguments.");
15350 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15351 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15352 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15353 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15354 DAG.getRegister(Vreg, SPTy));
15355 SDValue Ops1[2] = { Value, Chain };
15356 return DAG.getMergeValues(Ops1, dl);
15359 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15361 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15362 Flag = Chain.getValue(1);
15363 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15365 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15367 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15368 unsigned SPReg = RegInfo->getStackRegister();
15369 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15370 Chain = SP.getValue(1);
15373 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15374 DAG.getConstant(-(uint64_t)Align, dl, VT));
15375 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15378 SDValue Ops1[2] = { SP, Chain };
15379 return DAG.getMergeValues(Ops1, dl);
15383 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15384 MachineFunction &MF = DAG.getMachineFunction();
15385 auto PtrVT = getPointerTy(MF.getDataLayout());
15386 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15388 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15391 if (!Subtarget->is64Bit() ||
15392 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15393 // vastart just stores the address of the VarArgsFrameIndex slot into the
15394 // memory location argument.
15395 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15396 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15397 MachinePointerInfo(SV), false, false, 0);
15401 // gp_offset (0 - 6 * 8)
15402 // fp_offset (48 - 48 + 8 * 16)
15403 // overflow_arg_area (point to parameters coming in memory).
15405 SmallVector<SDValue, 8> MemOps;
15406 SDValue FIN = Op.getOperand(1);
15408 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15409 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15411 FIN, MachinePointerInfo(SV), false, false, 0);
15412 MemOps.push_back(Store);
15415 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15416 Store = DAG.getStore(Op.getOperand(0), DL,
15417 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15419 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15420 MemOps.push_back(Store);
15422 // Store ptr to overflow_arg_area
15423 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15424 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15425 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15426 MachinePointerInfo(SV, 8),
15428 MemOps.push_back(Store);
15430 // Store ptr to reg_save_area.
15431 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15432 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15433 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15434 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15435 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15436 MemOps.push_back(Store);
15437 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15440 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15441 assert(Subtarget->is64Bit() &&
15442 "LowerVAARG only handles 64-bit va_arg!");
15443 assert(Op.getNode()->getNumOperands() == 4);
15445 MachineFunction &MF = DAG.getMachineFunction();
15446 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15447 // The Win64 ABI uses char* instead of a structure.
15448 return DAG.expandVAArg(Op.getNode());
15450 SDValue Chain = Op.getOperand(0);
15451 SDValue SrcPtr = Op.getOperand(1);
15452 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15453 unsigned Align = Op.getConstantOperandVal(3);
15456 EVT ArgVT = Op.getNode()->getValueType(0);
15457 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15458 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15461 // Decide which area this value should be read from.
15462 // TODO: Implement the AMD64 ABI in its entirety. This simple
15463 // selection mechanism works only for the basic types.
15464 if (ArgVT == MVT::f80) {
15465 llvm_unreachable("va_arg for f80 not yet implemented");
15466 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15467 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15468 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15469 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15471 llvm_unreachable("Unhandled argument type in LowerVAARG");
15474 if (ArgMode == 2) {
15475 // Sanity Check: Make sure using fp_offset makes sense.
15476 assert(!Subtarget->useSoftFloat() &&
15477 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15478 Subtarget->hasSSE1());
15481 // Insert VAARG_64 node into the DAG
15482 // VAARG_64 returns two values: Variable Argument Address, Chain
15483 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15484 DAG.getConstant(ArgMode, dl, MVT::i8),
15485 DAG.getConstant(Align, dl, MVT::i32)};
15486 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15487 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15488 VTs, InstOps, MVT::i64,
15489 MachinePointerInfo(SV),
15491 /*Volatile=*/false,
15493 /*WriteMem=*/true);
15494 Chain = VAARG.getValue(1);
15496 // Load the next argument and return it
15497 return DAG.getLoad(ArgVT, dl,
15500 MachinePointerInfo(),
15501 false, false, false, 0);
15504 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15505 SelectionDAG &DAG) {
15506 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15507 // where a va_list is still an i8*.
15508 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15509 if (Subtarget->isCallingConvWin64(
15510 DAG.getMachineFunction().getFunction()->getCallingConv()))
15511 // Probably a Win64 va_copy.
15512 return DAG.expandVACopy(Op.getNode());
15514 SDValue Chain = Op.getOperand(0);
15515 SDValue DstPtr = Op.getOperand(1);
15516 SDValue SrcPtr = Op.getOperand(2);
15517 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15518 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15521 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15522 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15524 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15527 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15528 // amount is a constant. Takes immediate version of shift as input.
15529 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15530 SDValue SrcOp, uint64_t ShiftAmt,
15531 SelectionDAG &DAG) {
15532 MVT ElementType = VT.getVectorElementType();
15534 // Fold this packed shift into its first operand if ShiftAmt is 0.
15538 // Check for ShiftAmt >= element width
15539 if (ShiftAmt >= ElementType.getSizeInBits()) {
15540 if (Opc == X86ISD::VSRAI)
15541 ShiftAmt = ElementType.getSizeInBits() - 1;
15543 return DAG.getConstant(0, dl, VT);
15546 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15547 && "Unknown target vector shift-by-constant node");
15549 // Fold this packed vector shift into a build vector if SrcOp is a
15550 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15551 if (VT == SrcOp.getSimpleValueType() &&
15552 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15553 SmallVector<SDValue, 8> Elts;
15554 unsigned NumElts = SrcOp->getNumOperands();
15555 ConstantSDNode *ND;
15558 default: llvm_unreachable(nullptr);
15559 case X86ISD::VSHLI:
15560 for (unsigned i=0; i!=NumElts; ++i) {
15561 SDValue CurrentOp = SrcOp->getOperand(i);
15562 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15563 Elts.push_back(CurrentOp);
15566 ND = cast<ConstantSDNode>(CurrentOp);
15567 const APInt &C = ND->getAPIntValue();
15568 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15571 case X86ISD::VSRLI:
15572 for (unsigned i=0; i!=NumElts; ++i) {
15573 SDValue CurrentOp = SrcOp->getOperand(i);
15574 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15575 Elts.push_back(CurrentOp);
15578 ND = cast<ConstantSDNode>(CurrentOp);
15579 const APInt &C = ND->getAPIntValue();
15580 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15583 case X86ISD::VSRAI:
15584 for (unsigned i=0; i!=NumElts; ++i) {
15585 SDValue CurrentOp = SrcOp->getOperand(i);
15586 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15587 Elts.push_back(CurrentOp);
15590 ND = cast<ConstantSDNode>(CurrentOp);
15591 const APInt &C = ND->getAPIntValue();
15592 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15597 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15600 return DAG.getNode(Opc, dl, VT, SrcOp,
15601 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15604 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15605 // may or may not be a constant. Takes immediate version of shift as input.
15606 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15607 SDValue SrcOp, SDValue ShAmt,
15608 SelectionDAG &DAG) {
15609 MVT SVT = ShAmt.getSimpleValueType();
15610 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15612 // Catch shift-by-constant.
15613 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15614 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15615 CShAmt->getZExtValue(), DAG);
15617 // Change opcode to non-immediate version
15619 default: llvm_unreachable("Unknown target vector shift node");
15620 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15621 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15622 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15625 const X86Subtarget &Subtarget =
15626 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15627 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15628 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15629 // Let the shuffle legalizer expand this shift amount node.
15630 SDValue Op0 = ShAmt.getOperand(0);
15631 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15632 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15634 // Need to build a vector containing shift amount.
15635 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15636 SmallVector<SDValue, 4> ShOps;
15637 ShOps.push_back(ShAmt);
15638 if (SVT == MVT::i32) {
15639 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15640 ShOps.push_back(DAG.getUNDEF(SVT));
15642 ShOps.push_back(DAG.getUNDEF(SVT));
15644 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15645 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15648 // The return type has to be a 128-bit type with the same element
15649 // type as the input type.
15650 MVT EltVT = VT.getVectorElementType();
15651 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15653 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15654 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15657 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15658 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15659 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15660 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15661 SDValue PreservedSrc,
15662 const X86Subtarget *Subtarget,
15663 SelectionDAG &DAG) {
15664 EVT VT = Op.getValueType();
15665 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15666 MVT::i1, VT.getVectorNumElements());
15667 SDValue VMask = SDValue();
15668 unsigned OpcodeSelect = ISD::VSELECT;
15671 assert(MaskVT.isSimple() && "invalid mask type");
15673 if (isAllOnes(Mask))
15676 if (MaskVT.bitsGT(Mask.getValueType())) {
15677 EVT newMaskVT = EVT::getIntegerVT(*DAG.getContext(),
15678 MaskVT.getSizeInBits());
15679 VMask = DAG.getBitcast(MaskVT,
15680 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15682 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15683 Mask.getValueType().getSizeInBits());
15684 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15685 // are extracted by EXTRACT_SUBVECTOR.
15686 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15687 DAG.getBitcast(BitcastVT, Mask),
15688 DAG.getIntPtrConstant(0, dl));
15691 switch (Op.getOpcode()) {
15693 case X86ISD::PCMPEQM:
15694 case X86ISD::PCMPGTM:
15696 case X86ISD::CMPMU:
15697 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15698 case X86ISD::VTRUNC:
15699 case X86ISD::VTRUNCS:
15700 case X86ISD::VTRUNCUS:
15701 // We can't use ISD::VSELECT here because it is not always "Legal"
15702 // for the destination type. For example vpmovqb require only AVX512
15703 // and vselect that can operate on byte element type require BWI
15704 OpcodeSelect = X86ISD::SELECT;
15707 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15708 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15709 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
15712 /// \brief Creates an SDNode for a predicated scalar operation.
15713 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15714 /// The mask is coming as MVT::i8 and it should be truncated
15715 /// to MVT::i1 while lowering masking intrinsics.
15716 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15717 /// "X86select" instead of "vselect". We just can't create the "vselect" node
15718 /// for a scalar instruction.
15719 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15720 SDValue PreservedSrc,
15721 const X86Subtarget *Subtarget,
15722 SelectionDAG &DAG) {
15723 if (isAllOnes(Mask))
15726 EVT VT = Op.getValueType();
15728 // The mask should be of type MVT::i1
15729 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15731 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15732 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15733 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15736 static int getSEHRegistrationNodeSize(const Function *Fn) {
15737 if (!Fn->hasPersonalityFn())
15738 report_fatal_error(
15739 "querying registration node size for function without personality");
15740 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
15741 // WinEHStatePass for the full struct definition.
15742 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
15743 case EHPersonality::MSVC_X86SEH: return 24;
15744 case EHPersonality::MSVC_CXX: return 16;
15747 report_fatal_error("can only recover FP for MSVC EH personality functions");
15750 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
15751 /// function or when returning to a parent frame after catching an exception, we
15752 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
15753 /// Here's the math:
15754 /// RegNodeBase = EntryEBP - RegNodeSize
15755 /// ParentFP = RegNodeBase - RegNodeFrameOffset
15756 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
15757 /// subtracting the offset (negative on x86) takes us back to the parent FP.
15758 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
15759 SDValue EntryEBP) {
15760 MachineFunction &MF = DAG.getMachineFunction();
15763 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15764 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
15766 // It's possible that the parent function no longer has a personality function
15767 // if the exceptional code was optimized away, in which case we just return
15768 // the incoming EBP.
15769 if (!Fn->hasPersonalityFn())
15772 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
15774 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
15776 MCSymbol *OffsetSym =
15777 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15778 GlobalValue::getRealLinkageName(Fn->getName()));
15779 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
15780 SDValue RegNodeFrameOffset =
15781 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
15783 // RegNodeBase = EntryEBP - RegNodeSize
15784 // ParentFP = RegNodeBase - RegNodeFrameOffset
15785 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
15786 DAG.getConstant(RegNodeSize, dl, PtrVT));
15787 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
15790 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15791 SelectionDAG &DAG) {
15793 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15794 EVT VT = Op.getValueType();
15795 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15797 switch(IntrData->Type) {
15798 case INTR_TYPE_1OP:
15799 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15800 case INTR_TYPE_2OP:
15801 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15803 case INTR_TYPE_2OP_IMM8:
15804 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15805 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
15806 case INTR_TYPE_3OP:
15807 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15808 Op.getOperand(2), Op.getOperand(3));
15809 case INTR_TYPE_4OP:
15810 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15811 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
15812 case INTR_TYPE_1OP_MASK_RM: {
15813 SDValue Src = Op.getOperand(1);
15814 SDValue PassThru = Op.getOperand(2);
15815 SDValue Mask = Op.getOperand(3);
15816 SDValue RoundingMode;
15817 // We allways add rounding mode to the Node.
15818 // If the rounding mode is not specified, we add the
15819 // "current direction" mode.
15820 if (Op.getNumOperands() == 4)
15822 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15824 RoundingMode = Op.getOperand(4);
15825 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15826 if (IntrWithRoundingModeOpcode != 0)
15827 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
15828 X86::STATIC_ROUNDING::CUR_DIRECTION)
15829 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15830 dl, Op.getValueType(), Src, RoundingMode),
15831 Mask, PassThru, Subtarget, DAG);
15832 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15834 Mask, PassThru, Subtarget, DAG);
15836 case INTR_TYPE_1OP_MASK: {
15837 SDValue Src = Op.getOperand(1);
15838 SDValue PassThru = Op.getOperand(2);
15839 SDValue Mask = Op.getOperand(3);
15840 // We add rounding mode to the Node when
15841 // - RM Opcode is specified and
15842 // - RM is not "current direction".
15843 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15844 if (IntrWithRoundingModeOpcode != 0) {
15845 SDValue Rnd = Op.getOperand(4);
15846 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15847 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15848 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15849 dl, Op.getValueType(),
15851 Mask, PassThru, Subtarget, DAG);
15854 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
15855 Mask, PassThru, Subtarget, DAG);
15857 case INTR_TYPE_SCALAR_MASK_RM: {
15858 SDValue Src1 = Op.getOperand(1);
15859 SDValue Src2 = Op.getOperand(2);
15860 SDValue Src0 = Op.getOperand(3);
15861 SDValue Mask = Op.getOperand(4);
15862 // There are 2 kinds of intrinsics in this group:
15863 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
15864 // (2) With rounding mode and sae - 7 operands.
15865 if (Op.getNumOperands() == 6) {
15866 SDValue Sae = Op.getOperand(5);
15867 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
15868 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
15870 Mask, Src0, Subtarget, DAG);
15872 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
15873 SDValue RoundingMode = Op.getOperand(5);
15874 SDValue Sae = Op.getOperand(6);
15875 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
15876 RoundingMode, Sae),
15877 Mask, Src0, Subtarget, DAG);
15879 case INTR_TYPE_2OP_MASK: {
15880 SDValue Src1 = Op.getOperand(1);
15881 SDValue Src2 = Op.getOperand(2);
15882 SDValue PassThru = Op.getOperand(3);
15883 SDValue Mask = Op.getOperand(4);
15884 // We specify 2 possible opcodes for intrinsics with rounding modes.
15885 // First, we check if the intrinsic may have non-default rounding mode,
15886 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15887 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15888 if (IntrWithRoundingModeOpcode != 0) {
15889 SDValue Rnd = Op.getOperand(5);
15890 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15891 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15892 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15893 dl, Op.getValueType(),
15895 Mask, PassThru, Subtarget, DAG);
15898 // TODO: Intrinsics should have fast-math-flags to propagate.
15899 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
15900 Mask, PassThru, Subtarget, DAG);
15902 case INTR_TYPE_2OP_MASK_RM: {
15903 SDValue Src1 = Op.getOperand(1);
15904 SDValue Src2 = Op.getOperand(2);
15905 SDValue PassThru = Op.getOperand(3);
15906 SDValue Mask = Op.getOperand(4);
15907 // We specify 2 possible modes for intrinsics, with/without rounding modes.
15908 // First, we check if the intrinsic have rounding mode (6 operands),
15909 // if not, we set rounding mode to "current".
15911 if (Op.getNumOperands() == 6)
15912 Rnd = Op.getOperand(5);
15914 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15915 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15917 Mask, PassThru, Subtarget, DAG);
15919 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
15920 SDValue Src1 = Op.getOperand(1);
15921 SDValue Src2 = Op.getOperand(2);
15922 SDValue Src3 = Op.getOperand(3);
15923 SDValue PassThru = Op.getOperand(4);
15924 SDValue Mask = Op.getOperand(5);
15925 SDValue Sae = Op.getOperand(6);
15927 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
15929 Mask, PassThru, Subtarget, DAG);
15931 case INTR_TYPE_3OP_MASK_RM: {
15932 SDValue Src1 = Op.getOperand(1);
15933 SDValue Src2 = Op.getOperand(2);
15934 SDValue Imm = Op.getOperand(3);
15935 SDValue PassThru = Op.getOperand(4);
15936 SDValue Mask = Op.getOperand(5);
15937 // We specify 2 possible modes for intrinsics, with/without rounding modes.
15938 // First, we check if the intrinsic have rounding mode (7 operands),
15939 // if not, we set rounding mode to "current".
15941 if (Op.getNumOperands() == 7)
15942 Rnd = Op.getOperand(6);
15944 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15945 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15946 Src1, Src2, Imm, Rnd),
15947 Mask, PassThru, Subtarget, DAG);
15949 case INTR_TYPE_3OP_IMM8_MASK:
15950 case INTR_TYPE_3OP_MASK: {
15951 SDValue Src1 = Op.getOperand(1);
15952 SDValue Src2 = Op.getOperand(2);
15953 SDValue Src3 = Op.getOperand(3);
15954 SDValue PassThru = Op.getOperand(4);
15955 SDValue Mask = Op.getOperand(5);
15957 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
15958 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
15959 // We specify 2 possible opcodes for intrinsics with rounding modes.
15960 // First, we check if the intrinsic may have non-default rounding mode,
15961 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15962 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15963 if (IntrWithRoundingModeOpcode != 0) {
15964 SDValue Rnd = Op.getOperand(6);
15965 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15966 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15967 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15968 dl, Op.getValueType(),
15969 Src1, Src2, Src3, Rnd),
15970 Mask, PassThru, Subtarget, DAG);
15973 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15975 Mask, PassThru, Subtarget, DAG);
15977 case VPERM_3OP_MASKZ:
15978 case VPERM_3OP_MASK:
15981 case FMA_OP_MASK: {
15982 SDValue Src1 = Op.getOperand(1);
15983 SDValue Src2 = Op.getOperand(2);
15984 SDValue Src3 = Op.getOperand(3);
15985 SDValue Mask = Op.getOperand(4);
15986 EVT VT = Op.getValueType();
15987 SDValue PassThru = SDValue();
15989 // set PassThru element
15990 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
15991 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
15992 else if (IntrData->Type == FMA_OP_MASK3)
15997 // We specify 2 possible opcodes for intrinsics with rounding modes.
15998 // First, we check if the intrinsic may have non-default rounding mode,
15999 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16000 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16001 if (IntrWithRoundingModeOpcode != 0) {
16002 SDValue Rnd = Op.getOperand(5);
16003 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16004 X86::STATIC_ROUNDING::CUR_DIRECTION)
16005 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16006 dl, Op.getValueType(),
16007 Src1, Src2, Src3, Rnd),
16008 Mask, PassThru, Subtarget, DAG);
16010 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16011 dl, Op.getValueType(),
16013 Mask, PassThru, Subtarget, DAG);
16016 case CMP_MASK_CC: {
16017 // Comparison intrinsics with masks.
16018 // Example of transformation:
16019 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16020 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16022 // (v8i1 (insert_subvector undef,
16023 // (v2i1 (and (PCMPEQM %a, %b),
16024 // (extract_subvector
16025 // (v8i1 (bitcast %mask)), 0))), 0))))
16026 EVT VT = Op.getOperand(1).getValueType();
16027 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16028 VT.getVectorNumElements());
16029 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16030 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16031 Mask.getValueType().getSizeInBits());
16033 if (IntrData->Type == CMP_MASK_CC) {
16034 SDValue CC = Op.getOperand(3);
16035 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16036 // We specify 2 possible opcodes for intrinsics with rounding modes.
16037 // First, we check if the intrinsic may have non-default rounding mode,
16038 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16039 if (IntrData->Opc1 != 0) {
16040 SDValue Rnd = Op.getOperand(5);
16041 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16042 X86::STATIC_ROUNDING::CUR_DIRECTION)
16043 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16044 Op.getOperand(2), CC, Rnd);
16046 //default rounding mode
16048 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16049 Op.getOperand(2), CC);
16052 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16053 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16056 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16057 DAG.getTargetConstant(0, dl,
16060 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16061 DAG.getUNDEF(BitcastVT), CmpMask,
16062 DAG.getIntPtrConstant(0, dl));
16063 return DAG.getBitcast(Op.getValueType(), Res);
16065 case COMI: { // Comparison intrinsics
16066 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16067 SDValue LHS = Op.getOperand(1);
16068 SDValue RHS = Op.getOperand(2);
16069 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16070 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16071 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16072 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16073 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16074 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16077 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16078 Op.getOperand(1), Op.getOperand(2), DAG);
16080 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16081 Op.getSimpleValueType(),
16083 Op.getOperand(2), DAG),
16084 Op.getOperand(4), Op.getOperand(3), Subtarget,
16086 case COMPRESS_EXPAND_IN_REG: {
16087 SDValue Mask = Op.getOperand(3);
16088 SDValue DataToCompress = Op.getOperand(1);
16089 SDValue PassThru = Op.getOperand(2);
16090 if (isAllOnes(Mask)) // return data as is
16091 return Op.getOperand(1);
16093 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16095 Mask, PassThru, Subtarget, DAG);
16098 SDValue Mask = Op.getOperand(3);
16099 EVT VT = Op.getValueType();
16100 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16101 VT.getVectorNumElements());
16102 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16103 Mask.getValueType().getSizeInBits());
16105 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16106 DAG.getBitcast(BitcastVT, Mask),
16107 DAG.getIntPtrConstant(0, dl));
16108 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16117 default: return SDValue(); // Don't custom lower most intrinsics.
16119 case Intrinsic::x86_avx2_permd:
16120 case Intrinsic::x86_avx2_permps:
16121 // Operands intentionally swapped. Mask is last operand to intrinsic,
16122 // but second operand for node/instruction.
16123 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16124 Op.getOperand(2), Op.getOperand(1));
16126 // ptest and testp intrinsics. The intrinsic these come from are designed to
16127 // return an integer value, not just an instruction so lower it to the ptest
16128 // or testp pattern and a setcc for the result.
16129 case Intrinsic::x86_sse41_ptestz:
16130 case Intrinsic::x86_sse41_ptestc:
16131 case Intrinsic::x86_sse41_ptestnzc:
16132 case Intrinsic::x86_avx_ptestz_256:
16133 case Intrinsic::x86_avx_ptestc_256:
16134 case Intrinsic::x86_avx_ptestnzc_256:
16135 case Intrinsic::x86_avx_vtestz_ps:
16136 case Intrinsic::x86_avx_vtestc_ps:
16137 case Intrinsic::x86_avx_vtestnzc_ps:
16138 case Intrinsic::x86_avx_vtestz_pd:
16139 case Intrinsic::x86_avx_vtestc_pd:
16140 case Intrinsic::x86_avx_vtestnzc_pd:
16141 case Intrinsic::x86_avx_vtestz_ps_256:
16142 case Intrinsic::x86_avx_vtestc_ps_256:
16143 case Intrinsic::x86_avx_vtestnzc_ps_256:
16144 case Intrinsic::x86_avx_vtestz_pd_256:
16145 case Intrinsic::x86_avx_vtestc_pd_256:
16146 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16147 bool IsTestPacked = false;
16150 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16151 case Intrinsic::x86_avx_vtestz_ps:
16152 case Intrinsic::x86_avx_vtestz_pd:
16153 case Intrinsic::x86_avx_vtestz_ps_256:
16154 case Intrinsic::x86_avx_vtestz_pd_256:
16155 IsTestPacked = true; // Fallthrough
16156 case Intrinsic::x86_sse41_ptestz:
16157 case Intrinsic::x86_avx_ptestz_256:
16159 X86CC = X86::COND_E;
16161 case Intrinsic::x86_avx_vtestc_ps:
16162 case Intrinsic::x86_avx_vtestc_pd:
16163 case Intrinsic::x86_avx_vtestc_ps_256:
16164 case Intrinsic::x86_avx_vtestc_pd_256:
16165 IsTestPacked = true; // Fallthrough
16166 case Intrinsic::x86_sse41_ptestc:
16167 case Intrinsic::x86_avx_ptestc_256:
16169 X86CC = X86::COND_B;
16171 case Intrinsic::x86_avx_vtestnzc_ps:
16172 case Intrinsic::x86_avx_vtestnzc_pd:
16173 case Intrinsic::x86_avx_vtestnzc_ps_256:
16174 case Intrinsic::x86_avx_vtestnzc_pd_256:
16175 IsTestPacked = true; // Fallthrough
16176 case Intrinsic::x86_sse41_ptestnzc:
16177 case Intrinsic::x86_avx_ptestnzc_256:
16179 X86CC = X86::COND_A;
16183 SDValue LHS = Op.getOperand(1);
16184 SDValue RHS = Op.getOperand(2);
16185 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16186 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16187 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16188 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16189 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16191 case Intrinsic::x86_avx512_kortestz_w:
16192 case Intrinsic::x86_avx512_kortestc_w: {
16193 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16194 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16195 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16196 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16197 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16198 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16199 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16202 case Intrinsic::x86_sse42_pcmpistria128:
16203 case Intrinsic::x86_sse42_pcmpestria128:
16204 case Intrinsic::x86_sse42_pcmpistric128:
16205 case Intrinsic::x86_sse42_pcmpestric128:
16206 case Intrinsic::x86_sse42_pcmpistrio128:
16207 case Intrinsic::x86_sse42_pcmpestrio128:
16208 case Intrinsic::x86_sse42_pcmpistris128:
16209 case Intrinsic::x86_sse42_pcmpestris128:
16210 case Intrinsic::x86_sse42_pcmpistriz128:
16211 case Intrinsic::x86_sse42_pcmpestriz128: {
16215 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16216 case Intrinsic::x86_sse42_pcmpistria128:
16217 Opcode = X86ISD::PCMPISTRI;
16218 X86CC = X86::COND_A;
16220 case Intrinsic::x86_sse42_pcmpestria128:
16221 Opcode = X86ISD::PCMPESTRI;
16222 X86CC = X86::COND_A;
16224 case Intrinsic::x86_sse42_pcmpistric128:
16225 Opcode = X86ISD::PCMPISTRI;
16226 X86CC = X86::COND_B;
16228 case Intrinsic::x86_sse42_pcmpestric128:
16229 Opcode = X86ISD::PCMPESTRI;
16230 X86CC = X86::COND_B;
16232 case Intrinsic::x86_sse42_pcmpistrio128:
16233 Opcode = X86ISD::PCMPISTRI;
16234 X86CC = X86::COND_O;
16236 case Intrinsic::x86_sse42_pcmpestrio128:
16237 Opcode = X86ISD::PCMPESTRI;
16238 X86CC = X86::COND_O;
16240 case Intrinsic::x86_sse42_pcmpistris128:
16241 Opcode = X86ISD::PCMPISTRI;
16242 X86CC = X86::COND_S;
16244 case Intrinsic::x86_sse42_pcmpestris128:
16245 Opcode = X86ISD::PCMPESTRI;
16246 X86CC = X86::COND_S;
16248 case Intrinsic::x86_sse42_pcmpistriz128:
16249 Opcode = X86ISD::PCMPISTRI;
16250 X86CC = X86::COND_E;
16252 case Intrinsic::x86_sse42_pcmpestriz128:
16253 Opcode = X86ISD::PCMPESTRI;
16254 X86CC = X86::COND_E;
16257 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16258 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16259 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16260 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16261 DAG.getConstant(X86CC, dl, MVT::i8),
16262 SDValue(PCMP.getNode(), 1));
16263 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16266 case Intrinsic::x86_sse42_pcmpistri128:
16267 case Intrinsic::x86_sse42_pcmpestri128: {
16269 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16270 Opcode = X86ISD::PCMPISTRI;
16272 Opcode = X86ISD::PCMPESTRI;
16274 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16275 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16276 return DAG.getNode(Opcode, dl, VTs, NewOps);
16279 case Intrinsic::x86_seh_lsda: {
16280 // Compute the symbol for the LSDA. We know it'll get emitted later.
16281 MachineFunction &MF = DAG.getMachineFunction();
16282 SDValue Op1 = Op.getOperand(1);
16283 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16284 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16285 GlobalValue::getRealLinkageName(Fn->getName()));
16287 // Generate a simple absolute symbol reference. This intrinsic is only
16288 // supported on 32-bit Windows, which isn't PIC.
16289 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16290 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16293 case Intrinsic::x86_seh_recoverfp: {
16294 SDValue FnOp = Op.getOperand(1);
16295 SDValue IncomingFPOp = Op.getOperand(2);
16296 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16297 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16299 report_fatal_error(
16300 "llvm.x86.seh.recoverfp must take a function as the first argument");
16301 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16304 case Intrinsic::localaddress: {
16305 // Returns one of the stack, base, or frame pointer registers, depending on
16306 // which is used to reference local variables.
16307 MachineFunction &MF = DAG.getMachineFunction();
16308 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16310 if (RegInfo->hasBasePointer(MF))
16311 Reg = RegInfo->getBaseRegister();
16312 else // This function handles the SP or FP case.
16313 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16314 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16319 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16320 SDValue Src, SDValue Mask, SDValue Base,
16321 SDValue Index, SDValue ScaleOp, SDValue Chain,
16322 const X86Subtarget * Subtarget) {
16324 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16326 llvm_unreachable("Invalid scale type");
16327 unsigned ScaleVal = C->getZExtValue();
16328 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16329 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16331 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16332 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16333 Index.getSimpleValueType().getVectorNumElements());
16335 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16337 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16339 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16340 Mask.getValueType().getSizeInBits());
16342 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16343 // are extracted by EXTRACT_SUBVECTOR.
16344 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16345 DAG.getBitcast(BitcastVT, Mask),
16346 DAG.getIntPtrConstant(0, dl));
16348 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16349 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16350 SDValue Segment = DAG.getRegister(0, MVT::i32);
16351 if (Src.getOpcode() == ISD::UNDEF)
16352 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16353 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16354 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16355 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16356 return DAG.getMergeValues(RetOps, dl);
16359 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16360 SDValue Src, SDValue Mask, SDValue Base,
16361 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16363 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16365 llvm_unreachable("Invalid scale type");
16366 unsigned ScaleVal = C->getZExtValue();
16367 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16368 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16370 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16371 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16372 SDValue Segment = DAG.getRegister(0, MVT::i32);
16373 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16374 Index.getSimpleValueType().getVectorNumElements());
16376 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16378 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16380 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16381 Mask.getValueType().getSizeInBits());
16383 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16384 // are extracted by EXTRACT_SUBVECTOR.
16385 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16386 DAG.getBitcast(BitcastVT, Mask),
16387 DAG.getIntPtrConstant(0, dl));
16389 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16390 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16391 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16392 return SDValue(Res, 1);
16395 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16396 SDValue Mask, SDValue Base, SDValue Index,
16397 SDValue ScaleOp, SDValue Chain) {
16399 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16400 assert(C && "Invalid scale type");
16401 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16402 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16403 SDValue Segment = DAG.getRegister(0, MVT::i32);
16405 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16407 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16409 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16411 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16412 //SDVTList VTs = DAG.getVTList(MVT::Other);
16413 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16414 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16415 return SDValue(Res, 0);
16418 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16419 // read performance monitor counters (x86_rdpmc).
16420 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16421 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16422 SmallVectorImpl<SDValue> &Results) {
16423 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16424 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16427 // The ECX register is used to select the index of the performance counter
16429 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16431 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16433 // Reads the content of a 64-bit performance counter and returns it in the
16434 // registers EDX:EAX.
16435 if (Subtarget->is64Bit()) {
16436 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16437 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16440 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16441 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16444 Chain = HI.getValue(1);
16446 if (Subtarget->is64Bit()) {
16447 // The EAX register is loaded with the low-order 32 bits. The EDX register
16448 // is loaded with the supported high-order bits of the counter.
16449 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16450 DAG.getConstant(32, DL, MVT::i8));
16451 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16452 Results.push_back(Chain);
16456 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16457 SDValue Ops[] = { LO, HI };
16458 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16459 Results.push_back(Pair);
16460 Results.push_back(Chain);
16463 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16464 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16465 // also used to custom lower READCYCLECOUNTER nodes.
16466 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16467 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16468 SmallVectorImpl<SDValue> &Results) {
16469 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16470 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16473 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16474 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16475 // and the EAX register is loaded with the low-order 32 bits.
16476 if (Subtarget->is64Bit()) {
16477 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16478 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16481 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16482 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16485 SDValue Chain = HI.getValue(1);
16487 if (Opcode == X86ISD::RDTSCP_DAG) {
16488 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16490 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16491 // the ECX register. Add 'ecx' explicitly to the chain.
16492 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16494 // Explicitly store the content of ECX at the location passed in input
16495 // to the 'rdtscp' intrinsic.
16496 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16497 MachinePointerInfo(), false, false, 0);
16500 if (Subtarget->is64Bit()) {
16501 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16502 // the EAX register is loaded with the low-order 32 bits.
16503 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16504 DAG.getConstant(32, DL, MVT::i8));
16505 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16506 Results.push_back(Chain);
16510 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16511 SDValue Ops[] = { LO, HI };
16512 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16513 Results.push_back(Pair);
16514 Results.push_back(Chain);
16517 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16518 SelectionDAG &DAG) {
16519 SmallVector<SDValue, 2> Results;
16521 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16523 return DAG.getMergeValues(Results, DL);
16526 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16527 SelectionDAG &DAG) {
16528 MachineFunction &MF = DAG.getMachineFunction();
16529 const Function *Fn = MF.getFunction();
16531 SDValue Chain = Op.getOperand(0);
16533 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16534 "using llvm.x86.seh.restoreframe requires a frame pointer");
16536 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16537 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16539 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16540 unsigned FrameReg =
16541 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16542 unsigned SPReg = RegInfo->getStackRegister();
16543 unsigned SlotSize = RegInfo->getSlotSize();
16545 // Get incoming EBP.
16546 SDValue IncomingEBP =
16547 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16549 // SP is saved in the first field of every registration node, so load
16550 // [EBP-RegNodeSize] into SP.
16551 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16552 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16553 DAG.getConstant(-RegNodeSize, dl, VT));
16555 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16556 false, VT.getScalarSizeInBits() / 8);
16557 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16559 if (!RegInfo->needsStackRealignment(MF)) {
16560 // Adjust EBP to point back to the original frame position.
16561 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16562 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16564 assert(RegInfo->hasBasePointer(MF) &&
16565 "functions with Win32 EH must use frame or base pointer register");
16567 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16568 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16569 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16571 // Reload the spilled EBP value, now that the stack and base pointers are
16573 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16574 X86FI->setHasSEHFramePtrSave(true);
16575 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16576 X86FI->setSEHFramePtrSaveIndex(FI);
16577 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16578 MachinePointerInfo(), false, false, false,
16579 VT.getScalarSizeInBits() / 8);
16580 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16586 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16587 /// return truncate Store/MaskedStore Node
16588 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16592 SDValue Mask = Op.getOperand(4);
16593 SDValue DataToTruncate = Op.getOperand(3);
16594 SDValue Addr = Op.getOperand(2);
16595 SDValue Chain = Op.getOperand(0);
16597 EVT VT = DataToTruncate.getValueType();
16598 EVT SVT = EVT::getVectorVT(*DAG.getContext(),
16599 ElementType, VT.getVectorNumElements());
16601 if (isAllOnes(Mask)) // return just a truncate store
16602 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
16603 MachinePointerInfo(), SVT, false, false,
16604 SVT.getScalarSizeInBits()/8);
16606 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16607 MVT::i1, VT.getVectorNumElements());
16608 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16609 Mask.getValueType().getSizeInBits());
16610 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16611 // are extracted by EXTRACT_SUBVECTOR.
16612 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16613 DAG.getBitcast(BitcastVT, Mask),
16614 DAG.getIntPtrConstant(0, dl));
16616 MachineMemOperand *MMO = DAG.getMachineFunction().
16617 getMachineMemOperand(MachinePointerInfo(),
16618 MachineMemOperand::MOStore, SVT.getStoreSize(),
16619 SVT.getScalarSizeInBits()/8);
16621 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
16622 VMask, SVT, MMO, true);
16625 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16626 SelectionDAG &DAG) {
16627 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16629 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16631 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
16632 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16637 switch(IntrData->Type) {
16639 llvm_unreachable("Unknown Intrinsic Type");
16643 // Emit the node with the right value type.
16644 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16645 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16647 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16648 // Otherwise return the value from Rand, which is always 0, casted to i32.
16649 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16650 DAG.getConstant(1, dl, Op->getValueType(1)),
16651 DAG.getConstant(X86::COND_B, dl, MVT::i32),
16652 SDValue(Result.getNode(), 1) };
16653 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16654 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16657 // Return { result, isValid, chain }.
16658 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16659 SDValue(Result.getNode(), 2));
16662 //gather(v1, mask, index, base, scale);
16663 SDValue Chain = Op.getOperand(0);
16664 SDValue Src = Op.getOperand(2);
16665 SDValue Base = Op.getOperand(3);
16666 SDValue Index = Op.getOperand(4);
16667 SDValue Mask = Op.getOperand(5);
16668 SDValue Scale = Op.getOperand(6);
16669 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
16673 //scatter(base, mask, index, v1, scale);
16674 SDValue Chain = Op.getOperand(0);
16675 SDValue Base = Op.getOperand(2);
16676 SDValue Mask = Op.getOperand(3);
16677 SDValue Index = Op.getOperand(4);
16678 SDValue Src = Op.getOperand(5);
16679 SDValue Scale = Op.getOperand(6);
16680 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
16684 SDValue Hint = Op.getOperand(6);
16685 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
16686 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
16687 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16688 SDValue Chain = Op.getOperand(0);
16689 SDValue Mask = Op.getOperand(2);
16690 SDValue Index = Op.getOperand(3);
16691 SDValue Base = Op.getOperand(4);
16692 SDValue Scale = Op.getOperand(5);
16693 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16695 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16697 SmallVector<SDValue, 2> Results;
16698 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
16700 return DAG.getMergeValues(Results, dl);
16702 // Read Performance Monitoring Counters.
16704 SmallVector<SDValue, 2> Results;
16705 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16706 return DAG.getMergeValues(Results, dl);
16708 // XTEST intrinsics.
16710 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16711 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16712 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16713 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
16715 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16716 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16717 Ret, SDValue(InTrans.getNode(), 1));
16721 SmallVector<SDValue, 2> Results;
16722 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16723 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16724 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16725 DAG.getConstant(-1, dl, MVT::i8));
16726 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16727 Op.getOperand(4), GenCF.getValue(1));
16728 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16729 Op.getOperand(5), MachinePointerInfo(),
16731 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16732 DAG.getConstant(X86::COND_B, dl, MVT::i8),
16734 Results.push_back(SetCC);
16735 Results.push_back(Store);
16736 return DAG.getMergeValues(Results, dl);
16738 case COMPRESS_TO_MEM: {
16740 SDValue Mask = Op.getOperand(4);
16741 SDValue DataToCompress = Op.getOperand(3);
16742 SDValue Addr = Op.getOperand(2);
16743 SDValue Chain = Op.getOperand(0);
16745 EVT VT = DataToCompress.getValueType();
16746 if (isAllOnes(Mask)) // return just a store
16747 return DAG.getStore(Chain, dl, DataToCompress, Addr,
16748 MachinePointerInfo(), false, false,
16749 VT.getScalarSizeInBits()/8);
16751 SDValue Compressed =
16752 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
16753 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
16754 return DAG.getStore(Chain, dl, Compressed, Addr,
16755 MachinePointerInfo(), false, false,
16756 VT.getScalarSizeInBits()/8);
16758 case TRUNCATE_TO_MEM_VI8:
16759 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
16760 case TRUNCATE_TO_MEM_VI16:
16761 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
16762 case TRUNCATE_TO_MEM_VI32:
16763 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
16764 case EXPAND_FROM_MEM: {
16766 SDValue Mask = Op.getOperand(4);
16767 SDValue PassThru = Op.getOperand(3);
16768 SDValue Addr = Op.getOperand(2);
16769 SDValue Chain = Op.getOperand(0);
16770 EVT VT = Op.getValueType();
16772 if (isAllOnes(Mask)) // return just a load
16773 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
16774 false, VT.getScalarSizeInBits()/8);
16776 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
16777 false, false, false,
16778 VT.getScalarSizeInBits()/8);
16780 SDValue Results[] = {
16781 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
16782 Mask, PassThru, Subtarget, DAG), Chain};
16783 return DAG.getMergeValues(Results, dl);
16788 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16789 SelectionDAG &DAG) const {
16790 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16791 MFI->setReturnAddressIsTaken(true);
16793 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16796 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16798 EVT PtrVT = getPointerTy(DAG.getDataLayout());
16801 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16802 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16803 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
16804 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16805 DAG.getNode(ISD::ADD, dl, PtrVT,
16806 FrameAddr, Offset),
16807 MachinePointerInfo(), false, false, false, 0);
16810 // Just load the return address.
16811 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16812 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16813 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16816 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16817 MachineFunction &MF = DAG.getMachineFunction();
16818 MachineFrameInfo *MFI = MF.getFrameInfo();
16819 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16820 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16821 EVT VT = Op.getValueType();
16823 MFI->setFrameAddressIsTaken(true);
16825 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
16826 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
16827 // is not possible to crawl up the stack without looking at the unwind codes
16829 int FrameAddrIndex = FuncInfo->getFAIndex();
16830 if (!FrameAddrIndex) {
16831 // Set up a frame object for the return address.
16832 unsigned SlotSize = RegInfo->getSlotSize();
16833 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
16834 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
16835 FuncInfo->setFAIndex(FrameAddrIndex);
16837 return DAG.getFrameIndex(FrameAddrIndex, VT);
16840 unsigned FrameReg =
16841 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16842 SDLoc dl(Op); // FIXME probably not meaningful
16843 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16844 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16845 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16846 "Invalid Frame Register!");
16847 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16849 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16850 MachinePointerInfo(),
16851 false, false, false, 0);
16855 // FIXME? Maybe this could be a TableGen attribute on some registers and
16856 // this table could be generated automatically from RegInfo.
16857 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
16858 SelectionDAG &DAG) const {
16859 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
16860 const MachineFunction &MF = DAG.getMachineFunction();
16862 unsigned Reg = StringSwitch<unsigned>(RegName)
16863 .Case("esp", X86::ESP)
16864 .Case("rsp", X86::RSP)
16865 .Case("ebp", X86::EBP)
16866 .Case("rbp", X86::RBP)
16869 if (Reg == X86::EBP || Reg == X86::RBP) {
16870 if (!TFI.hasFP(MF))
16871 report_fatal_error("register " + StringRef(RegName) +
16872 " is allocatable: function has no frame pointer");
16875 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16876 unsigned FrameReg =
16877 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16878 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
16879 "Invalid Frame Register!");
16887 report_fatal_error("Invalid register name global variable");
16890 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16891 SelectionDAG &DAG) const {
16892 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16893 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
16896 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16897 SDValue Chain = Op.getOperand(0);
16898 SDValue Offset = Op.getOperand(1);
16899 SDValue Handler = Op.getOperand(2);
16902 EVT PtrVT = getPointerTy(DAG.getDataLayout());
16903 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16904 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16905 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16906 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16907 "Invalid Frame Register!");
16908 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16909 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16911 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16912 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
16914 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16915 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16917 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16919 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16920 DAG.getRegister(StoreAddrReg, PtrVT));
16923 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16924 SelectionDAG &DAG) const {
16926 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16927 DAG.getVTList(MVT::i32, MVT::Other),
16928 Op.getOperand(0), Op.getOperand(1));
16931 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16932 SelectionDAG &DAG) const {
16934 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16935 Op.getOperand(0), Op.getOperand(1));
16938 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16939 return Op.getOperand(0);
16942 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16943 SelectionDAG &DAG) const {
16944 SDValue Root = Op.getOperand(0);
16945 SDValue Trmp = Op.getOperand(1); // trampoline
16946 SDValue FPtr = Op.getOperand(2); // nested function
16947 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16950 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16951 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
16953 if (Subtarget->is64Bit()) {
16954 SDValue OutChains[6];
16956 // Large code-model.
16957 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16958 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16960 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16961 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16963 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16965 // Load the pointer to the nested function into R11.
16966 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16967 SDValue Addr = Trmp;
16968 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16969 Addr, MachinePointerInfo(TrmpAddr),
16972 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16973 DAG.getConstant(2, dl, MVT::i64));
16974 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16975 MachinePointerInfo(TrmpAddr, 2),
16978 // Load the 'nest' parameter value into R10.
16979 // R10 is specified in X86CallingConv.td
16980 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16981 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16982 DAG.getConstant(10, dl, MVT::i64));
16983 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16984 Addr, MachinePointerInfo(TrmpAddr, 10),
16987 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16988 DAG.getConstant(12, dl, MVT::i64));
16989 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16990 MachinePointerInfo(TrmpAddr, 12),
16993 // Jump to the nested function.
16994 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16995 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16996 DAG.getConstant(20, dl, MVT::i64));
16997 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16998 Addr, MachinePointerInfo(TrmpAddr, 20),
17001 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17002 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17003 DAG.getConstant(22, dl, MVT::i64));
17004 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17005 Addr, MachinePointerInfo(TrmpAddr, 22),
17008 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17010 const Function *Func =
17011 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17012 CallingConv::ID CC = Func->getCallingConv();
17017 llvm_unreachable("Unsupported calling convention");
17018 case CallingConv::C:
17019 case CallingConv::X86_StdCall: {
17020 // Pass 'nest' parameter in ECX.
17021 // Must be kept in sync with X86CallingConv.td
17022 NestReg = X86::ECX;
17024 // Check that ECX wasn't needed by an 'inreg' parameter.
17025 FunctionType *FTy = Func->getFunctionType();
17026 const AttributeSet &Attrs = Func->getAttributes();
17028 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17029 unsigned InRegCount = 0;
17032 for (FunctionType::param_iterator I = FTy->param_begin(),
17033 E = FTy->param_end(); I != E; ++I, ++Idx)
17034 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17035 auto &DL = DAG.getDataLayout();
17036 // FIXME: should only count parameters that are lowered to integers.
17037 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17040 if (InRegCount > 2) {
17041 report_fatal_error("Nest register in use - reduce number of inreg"
17047 case CallingConv::X86_FastCall:
17048 case CallingConv::X86_ThisCall:
17049 case CallingConv::Fast:
17050 // Pass 'nest' parameter in EAX.
17051 // Must be kept in sync with X86CallingConv.td
17052 NestReg = X86::EAX;
17056 SDValue OutChains[4];
17057 SDValue Addr, Disp;
17059 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17060 DAG.getConstant(10, dl, MVT::i32));
17061 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17063 // This is storing the opcode for MOV32ri.
17064 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17065 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17066 OutChains[0] = DAG.getStore(Root, dl,
17067 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17068 Trmp, MachinePointerInfo(TrmpAddr),
17071 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17072 DAG.getConstant(1, dl, MVT::i32));
17073 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17074 MachinePointerInfo(TrmpAddr, 1),
17077 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17078 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17079 DAG.getConstant(5, dl, MVT::i32));
17080 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17081 Addr, MachinePointerInfo(TrmpAddr, 5),
17084 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17085 DAG.getConstant(6, dl, MVT::i32));
17086 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17087 MachinePointerInfo(TrmpAddr, 6),
17090 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17094 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17095 SelectionDAG &DAG) const {
17097 The rounding mode is in bits 11:10 of FPSR, and has the following
17099 00 Round to nearest
17104 FLT_ROUNDS, on the other hand, expects the following:
17111 To perform the conversion, we do:
17112 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17115 MachineFunction &MF = DAG.getMachineFunction();
17116 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17117 unsigned StackAlignment = TFI.getStackAlignment();
17118 MVT VT = Op.getSimpleValueType();
17121 // Save FP Control Word to stack slot
17122 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17123 SDValue StackSlot =
17124 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17126 MachineMemOperand *MMO =
17127 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17128 MachineMemOperand::MOStore, 2, 2);
17130 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17131 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17132 DAG.getVTList(MVT::Other),
17133 Ops, MVT::i16, MMO);
17135 // Load FP Control Word from stack slot
17136 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17137 MachinePointerInfo(), false, false, false, 0);
17139 // Transform as necessary
17141 DAG.getNode(ISD::SRL, DL, MVT::i16,
17142 DAG.getNode(ISD::AND, DL, MVT::i16,
17143 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17144 DAG.getConstant(11, DL, MVT::i8));
17146 DAG.getNode(ISD::SRL, DL, MVT::i16,
17147 DAG.getNode(ISD::AND, DL, MVT::i16,
17148 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17149 DAG.getConstant(9, DL, MVT::i8));
17152 DAG.getNode(ISD::AND, DL, MVT::i16,
17153 DAG.getNode(ISD::ADD, DL, MVT::i16,
17154 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17155 DAG.getConstant(1, DL, MVT::i16)),
17156 DAG.getConstant(3, DL, MVT::i16));
17158 return DAG.getNode((VT.getSizeInBits() < 16 ?
17159 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17162 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17163 MVT VT = Op.getSimpleValueType();
17165 unsigned NumBits = VT.getSizeInBits();
17168 Op = Op.getOperand(0);
17169 if (VT == MVT::i8) {
17170 // Zero extend to i32 since there is not an i8 bsr.
17172 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17175 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17176 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17177 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17179 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17182 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17183 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17186 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17188 // Finally xor with NumBits-1.
17189 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17190 DAG.getConstant(NumBits - 1, dl, OpVT));
17193 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17197 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17198 MVT VT = Op.getSimpleValueType();
17200 unsigned NumBits = VT.getSizeInBits();
17203 Op = Op.getOperand(0);
17204 if (VT == MVT::i8) {
17205 // Zero extend to i32 since there is not an i8 bsr.
17207 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17210 // Issue a bsr (scan bits in reverse).
17211 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17212 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17214 // And xor with NumBits-1.
17215 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17216 DAG.getConstant(NumBits - 1, dl, OpVT));
17219 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17223 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17224 MVT VT = Op.getSimpleValueType();
17225 unsigned NumBits = VT.getSizeInBits();
17227 Op = Op.getOperand(0);
17229 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17230 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17231 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17233 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17236 DAG.getConstant(NumBits, dl, VT),
17237 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17240 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17243 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17244 // ones, and then concatenate the result back.
17245 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17246 MVT VT = Op.getSimpleValueType();
17248 assert(VT.is256BitVector() && VT.isInteger() &&
17249 "Unsupported value type for operation");
17251 unsigned NumElems = VT.getVectorNumElements();
17254 // Extract the LHS vectors
17255 SDValue LHS = Op.getOperand(0);
17256 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17257 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17259 // Extract the RHS vectors
17260 SDValue RHS = Op.getOperand(1);
17261 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17262 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17264 MVT EltVT = VT.getVectorElementType();
17265 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17267 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17268 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17269 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17272 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17273 if (Op.getValueType() == MVT::i1)
17274 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17275 Op.getOperand(0), Op.getOperand(1));
17276 assert(Op.getSimpleValueType().is256BitVector() &&
17277 Op.getSimpleValueType().isInteger() &&
17278 "Only handle AVX 256-bit vector integer operation");
17279 return Lower256IntArith(Op, DAG);
17282 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17283 if (Op.getValueType() == MVT::i1)
17284 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17285 Op.getOperand(0), Op.getOperand(1));
17286 assert(Op.getSimpleValueType().is256BitVector() &&
17287 Op.getSimpleValueType().isInteger() &&
17288 "Only handle AVX 256-bit vector integer operation");
17289 return Lower256IntArith(Op, DAG);
17292 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17293 assert(Op.getSimpleValueType().is256BitVector() &&
17294 Op.getSimpleValueType().isInteger() &&
17295 "Only handle AVX 256-bit vector integer operation");
17296 return Lower256IntArith(Op, DAG);
17299 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17300 SelectionDAG &DAG) {
17302 MVT VT = Op.getSimpleValueType();
17305 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17307 // Decompose 256-bit ops into smaller 128-bit ops.
17308 if (VT.is256BitVector() && !Subtarget->hasInt256())
17309 return Lower256IntArith(Op, DAG);
17311 SDValue A = Op.getOperand(0);
17312 SDValue B = Op.getOperand(1);
17314 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17315 // pairs, multiply and truncate.
17316 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17317 if (Subtarget->hasInt256()) {
17318 if (VT == MVT::v32i8) {
17319 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17320 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17321 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17322 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17323 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17324 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17325 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17326 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17327 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17328 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17331 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17332 return DAG.getNode(
17333 ISD::TRUNCATE, dl, VT,
17334 DAG.getNode(ISD::MUL, dl, ExVT,
17335 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17336 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17339 assert(VT == MVT::v16i8 &&
17340 "Pre-AVX2 support only supports v16i8 multiplication");
17341 MVT ExVT = MVT::v8i16;
17343 // Extract the lo parts and sign extend to i16
17345 if (Subtarget->hasSSE41()) {
17346 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17347 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17349 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17350 -1, 4, -1, 5, -1, 6, -1, 7};
17351 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17352 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17353 ALo = DAG.getBitcast(ExVT, ALo);
17354 BLo = DAG.getBitcast(ExVT, BLo);
17355 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17356 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17359 // Extract the hi parts and sign extend to i16
17361 if (Subtarget->hasSSE41()) {
17362 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17363 -1, -1, -1, -1, -1, -1, -1, -1};
17364 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17365 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17366 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17367 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17369 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17370 -1, 12, -1, 13, -1, 14, -1, 15};
17371 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17372 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17373 AHi = DAG.getBitcast(ExVT, AHi);
17374 BHi = DAG.getBitcast(ExVT, BHi);
17375 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17376 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17379 // Multiply, mask the lower 8bits of the lo/hi results and pack
17380 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17381 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17382 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17383 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17384 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17387 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17388 if (VT == MVT::v4i32) {
17389 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17390 "Should not custom lower when pmuldq is available!");
17392 // Extract the odd parts.
17393 static const int UnpackMask[] = { 1, -1, 3, -1 };
17394 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17395 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17397 // Multiply the even parts.
17398 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17399 // Now multiply odd parts.
17400 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17402 Evens = DAG.getBitcast(VT, Evens);
17403 Odds = DAG.getBitcast(VT, Odds);
17405 // Merge the two vectors back together with a shuffle. This expands into 2
17407 static const int ShufMask[] = { 0, 4, 2, 6 };
17408 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17411 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17412 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17414 // Ahi = psrlqi(a, 32);
17415 // Bhi = psrlqi(b, 32);
17417 // AloBlo = pmuludq(a, b);
17418 // AloBhi = pmuludq(a, Bhi);
17419 // AhiBlo = pmuludq(Ahi, b);
17421 // AloBhi = psllqi(AloBhi, 32);
17422 // AhiBlo = psllqi(AhiBlo, 32);
17423 // return AloBlo + AloBhi + AhiBlo;
17425 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17426 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17428 SDValue AhiBlo = Ahi;
17429 SDValue AloBhi = Bhi;
17430 // Bit cast to 32-bit vectors for MULUDQ
17431 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17432 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17433 A = DAG.getBitcast(MulVT, A);
17434 B = DAG.getBitcast(MulVT, B);
17435 Ahi = DAG.getBitcast(MulVT, Ahi);
17436 Bhi = DAG.getBitcast(MulVT, Bhi);
17438 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17439 // After shifting right const values the result may be all-zero.
17440 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17441 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17442 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17444 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17445 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17446 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17449 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17450 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17453 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17454 assert(Subtarget->isTargetWin64() && "Unexpected target");
17455 EVT VT = Op.getValueType();
17456 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17457 "Unexpected return type for lowering");
17461 switch (Op->getOpcode()) {
17462 default: llvm_unreachable("Unexpected request for libcall!");
17463 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17464 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17465 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17466 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17467 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17468 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17472 SDValue InChain = DAG.getEntryNode();
17474 TargetLowering::ArgListTy Args;
17475 TargetLowering::ArgListEntry Entry;
17476 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17477 EVT ArgVT = Op->getOperand(i).getValueType();
17478 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17479 "Unexpected argument type for lowering");
17480 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17481 Entry.Node = StackPtr;
17482 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17484 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17485 Entry.Ty = PointerType::get(ArgTy,0);
17486 Entry.isSExt = false;
17487 Entry.isZExt = false;
17488 Args.push_back(Entry);
17491 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17492 getPointerTy(DAG.getDataLayout()));
17494 TargetLowering::CallLoweringInfo CLI(DAG);
17495 CLI.setDebugLoc(dl).setChain(InChain)
17496 .setCallee(getLibcallCallingConv(LC),
17497 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17498 Callee, std::move(Args), 0)
17499 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17501 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17502 return DAG.getBitcast(VT, CallInfo.first);
17505 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17506 SelectionDAG &DAG) {
17507 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17508 EVT VT = Op0.getValueType();
17511 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17512 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17514 // PMULxD operations multiply each even value (starting at 0) of LHS with
17515 // the related value of RHS and produce a widen result.
17516 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17517 // => <2 x i64> <ae|cg>
17519 // In other word, to have all the results, we need to perform two PMULxD:
17520 // 1. one with the even values.
17521 // 2. one with the odd values.
17522 // To achieve #2, with need to place the odd values at an even position.
17524 // Place the odd value at an even position (basically, shift all values 1
17525 // step to the left):
17526 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17527 // <a|b|c|d> => <b|undef|d|undef>
17528 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17529 // <e|f|g|h> => <f|undef|h|undef>
17530 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17532 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17534 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17535 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17537 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17538 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17539 // => <2 x i64> <ae|cg>
17540 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17541 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17542 // => <2 x i64> <bf|dh>
17543 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17545 // Shuffle it back into the right order.
17546 SDValue Highs, Lows;
17547 if (VT == MVT::v8i32) {
17548 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17549 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17550 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17551 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17553 const int HighMask[] = {1, 5, 3, 7};
17554 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17555 const int LowMask[] = {0, 4, 2, 6};
17556 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17559 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17560 // unsigned multiply.
17561 if (IsSigned && !Subtarget->hasSSE41()) {
17562 SDValue ShAmt = DAG.getConstant(
17564 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
17565 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17566 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17567 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17568 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17570 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17571 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17574 // The first result of MUL_LOHI is actually the low value, followed by the
17576 SDValue Ops[] = {Lows, Highs};
17577 return DAG.getMergeValues(Ops, dl);
17580 // Return true if the required (according to Opcode) shift-imm form is natively
17581 // supported by the Subtarget
17582 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
17584 if (VT.getScalarSizeInBits() < 16)
17587 if (VT.is512BitVector() &&
17588 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
17591 bool LShift = VT.is128BitVector() ||
17592 (VT.is256BitVector() && Subtarget->hasInt256());
17594 bool AShift = LShift && (Subtarget->hasVLX() ||
17595 (VT != MVT::v2i64 && VT != MVT::v4i64));
17596 return (Opcode == ISD::SRA) ? AShift : LShift;
17599 // The shift amount is a variable, but it is the same for all vector lanes.
17600 // These instructions are defined together with shift-immediate.
17602 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
17604 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
17607 // Return true if the required (according to Opcode) variable-shift form is
17608 // natively supported by the Subtarget
17609 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
17612 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
17615 // vXi16 supported only on AVX-512, BWI
17616 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
17619 if (VT.is512BitVector() || Subtarget->hasVLX())
17622 bool LShift = VT.is128BitVector() || VT.is256BitVector();
17623 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
17624 return (Opcode == ISD::SRA) ? AShift : LShift;
17627 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17628 const X86Subtarget *Subtarget) {
17629 MVT VT = Op.getSimpleValueType();
17631 SDValue R = Op.getOperand(0);
17632 SDValue Amt = Op.getOperand(1);
17634 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17635 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17637 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
17638 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
17639 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
17640 SDValue Ex = DAG.getBitcast(ExVT, R);
17642 if (ShiftAmt >= 32) {
17643 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
17645 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
17646 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17647 ShiftAmt - 32, DAG);
17648 if (VT == MVT::v2i64)
17649 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
17650 if (VT == MVT::v4i64)
17651 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17652 {9, 1, 11, 3, 13, 5, 15, 7});
17654 // SRA upper i32, SHL whole i64 and select lower i32.
17655 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17658 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
17659 Lower = DAG.getBitcast(ExVT, Lower);
17660 if (VT == MVT::v2i64)
17661 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
17662 if (VT == MVT::v4i64)
17663 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17664 {8, 1, 10, 3, 12, 5, 14, 7});
17666 return DAG.getBitcast(VT, Ex);
17669 // Optimize shl/srl/sra with constant shift amount.
17670 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17671 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17672 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17674 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17675 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17677 // i64 SRA needs to be performed as partial shifts.
17678 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17679 Op.getOpcode() == ISD::SRA)
17680 return ArithmeticShiftRight64(ShiftAmt);
17682 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
17683 unsigned NumElts = VT.getVectorNumElements();
17684 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
17686 if (Op.getOpcode() == ISD::SHL) {
17687 // Simple i8 add case
17689 return DAG.getNode(ISD::ADD, dl, VT, R, R);
17691 // Make a large shift.
17692 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
17694 SHL = DAG.getBitcast(VT, SHL);
17695 // Zero out the rightmost bits.
17696 SmallVector<SDValue, 32> V(
17697 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
17698 return DAG.getNode(ISD::AND, dl, VT, SHL,
17699 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17701 if (Op.getOpcode() == ISD::SRL) {
17702 // Make a large shift.
17703 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
17705 SRL = DAG.getBitcast(VT, SRL);
17706 // Zero out the leftmost bits.
17707 SmallVector<SDValue, 32> V(
17708 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
17709 return DAG.getNode(ISD::AND, dl, VT, SRL,
17710 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17712 if (Op.getOpcode() == ISD::SRA) {
17713 if (ShiftAmt == 7) {
17714 // ashr(R, 7) === cmp_slt(R, 0)
17715 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17716 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17719 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
17720 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17721 SmallVector<SDValue, 32> V(NumElts,
17722 DAG.getConstant(128 >> ShiftAmt, dl,
17724 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17725 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17726 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17729 llvm_unreachable("Unknown shift opcode.");
17734 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17735 if (!Subtarget->is64Bit() &&
17736 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
17738 // Peek through any splat that was introduced for i64 shift vectorization.
17739 int SplatIndex = -1;
17740 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
17741 if (SVN->isSplat()) {
17742 SplatIndex = SVN->getSplatIndex();
17743 Amt = Amt.getOperand(0);
17744 assert(SplatIndex < (int)VT.getVectorNumElements() &&
17745 "Splat shuffle referencing second operand");
17748 if (Amt.getOpcode() != ISD::BITCAST ||
17749 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
17752 Amt = Amt.getOperand(0);
17753 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17754 VT.getVectorNumElements();
17755 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17756 uint64_t ShiftAmt = 0;
17757 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
17758 for (unsigned i = 0; i != Ratio; ++i) {
17759 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
17763 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17766 // Check remaining shift amounts (if not a splat).
17767 if (SplatIndex < 0) {
17768 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17769 uint64_t ShAmt = 0;
17770 for (unsigned j = 0; j != Ratio; ++j) {
17771 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17775 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17777 if (ShAmt != ShiftAmt)
17782 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17783 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17785 if (Op.getOpcode() == ISD::SRA)
17786 return ArithmeticShiftRight64(ShiftAmt);
17792 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17793 const X86Subtarget* Subtarget) {
17794 MVT VT = Op.getSimpleValueType();
17796 SDValue R = Op.getOperand(0);
17797 SDValue Amt = Op.getOperand(1);
17799 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17800 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17802 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
17803 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
17805 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
17807 EVT EltVT = VT.getVectorElementType();
17809 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
17810 // Check if this build_vector node is doing a splat.
17811 // If so, then set BaseShAmt equal to the splat value.
17812 BaseShAmt = BV->getSplatValue();
17813 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
17814 BaseShAmt = SDValue();
17816 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17817 Amt = Amt.getOperand(0);
17819 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
17820 if (SVN && SVN->isSplat()) {
17821 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
17822 SDValue InVec = Amt.getOperand(0);
17823 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17824 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
17825 "Unexpected shuffle index found!");
17826 BaseShAmt = InVec.getOperand(SplatIdx);
17827 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17828 if (ConstantSDNode *C =
17829 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17830 if (C->getZExtValue() == SplatIdx)
17831 BaseShAmt = InVec.getOperand(1);
17836 // Avoid introducing an extract element from a shuffle.
17837 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
17838 DAG.getIntPtrConstant(SplatIdx, dl));
17842 if (BaseShAmt.getNode()) {
17843 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
17844 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
17845 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
17846 else if (EltVT.bitsLT(MVT::i32))
17847 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17849 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
17853 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17854 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
17855 Amt.getOpcode() == ISD::BITCAST &&
17856 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17857 Amt = Amt.getOperand(0);
17858 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17859 VT.getVectorNumElements();
17860 std::vector<SDValue> Vals(Ratio);
17861 for (unsigned i = 0; i != Ratio; ++i)
17862 Vals[i] = Amt.getOperand(i);
17863 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17864 for (unsigned j = 0; j != Ratio; ++j)
17865 if (Vals[j] != Amt.getOperand(i + j))
17869 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
17870 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
17875 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17876 SelectionDAG &DAG) {
17877 MVT VT = Op.getSimpleValueType();
17879 SDValue R = Op.getOperand(0);
17880 SDValue Amt = Op.getOperand(1);
17882 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17883 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17885 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
17888 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
17891 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
17894 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
17895 // shifts per-lane and then shuffle the partial results back together.
17896 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
17897 // Splat the shift amounts so the scalar shifts above will catch it.
17898 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
17899 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
17900 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
17901 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
17902 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
17905 // i64 vector arithmetic shift can be emulated with the transform:
17906 // M = lshr(SIGN_BIT, Amt)
17907 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
17908 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
17909 Op.getOpcode() == ISD::SRA) {
17910 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
17911 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
17912 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17913 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
17914 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
17918 // If possible, lower this packed shift into a vector multiply instead of
17919 // expanding it into a sequence of scalar shifts.
17920 // Do this only if the vector shift count is a constant build_vector.
17921 if (Op.getOpcode() == ISD::SHL &&
17922 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17923 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17924 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17925 SmallVector<SDValue, 8> Elts;
17926 EVT SVT = VT.getScalarType();
17927 unsigned SVTBits = SVT.getSizeInBits();
17928 const APInt &One = APInt(SVTBits, 1);
17929 unsigned NumElems = VT.getVectorNumElements();
17931 for (unsigned i=0; i !=NumElems; ++i) {
17932 SDValue Op = Amt->getOperand(i);
17933 if (Op->getOpcode() == ISD::UNDEF) {
17934 Elts.push_back(Op);
17938 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17939 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17940 uint64_t ShAmt = C.getZExtValue();
17941 if (ShAmt >= SVTBits) {
17942 Elts.push_back(DAG.getUNDEF(SVT));
17945 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
17947 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17948 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17951 // Lower SHL with variable shift amount.
17952 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17953 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
17955 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
17956 DAG.getConstant(0x3f800000U, dl, VT));
17957 Op = DAG.getBitcast(MVT::v4f32, Op);
17958 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17959 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17962 // If possible, lower this shift as a sequence of two shifts by
17963 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17965 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17967 // Could be rewritten as:
17968 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17970 // The advantage is that the two shifts from the example would be
17971 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17972 // the vector shift into four scalar shifts plus four pairs of vector
17974 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17975 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17976 unsigned TargetOpcode = X86ISD::MOVSS;
17977 bool CanBeSimplified;
17978 // The splat value for the first packed shift (the 'X' from the example).
17979 SDValue Amt1 = Amt->getOperand(0);
17980 // The splat value for the second packed shift (the 'Y' from the example).
17981 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17982 Amt->getOperand(2);
17984 // See if it is possible to replace this node with a sequence of
17985 // two shifts followed by a MOVSS/MOVSD
17986 if (VT == MVT::v4i32) {
17987 // Check if it is legal to use a MOVSS.
17988 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17989 Amt2 == Amt->getOperand(3);
17990 if (!CanBeSimplified) {
17991 // Otherwise, check if we can still simplify this node using a MOVSD.
17992 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17993 Amt->getOperand(2) == Amt->getOperand(3);
17994 TargetOpcode = X86ISD::MOVSD;
17995 Amt2 = Amt->getOperand(2);
17998 // Do similar checks for the case where the machine value type
18000 CanBeSimplified = Amt1 == Amt->getOperand(1);
18001 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18002 CanBeSimplified = Amt2 == Amt->getOperand(i);
18004 if (!CanBeSimplified) {
18005 TargetOpcode = X86ISD::MOVSD;
18006 CanBeSimplified = true;
18007 Amt2 = Amt->getOperand(4);
18008 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18009 CanBeSimplified = Amt1 == Amt->getOperand(i);
18010 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18011 CanBeSimplified = Amt2 == Amt->getOperand(j);
18015 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18016 isa<ConstantSDNode>(Amt2)) {
18017 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18018 EVT CastVT = MVT::v4i32;
18020 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18021 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18023 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18024 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18025 if (TargetOpcode == X86ISD::MOVSD)
18026 CastVT = MVT::v2i64;
18027 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18028 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18029 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18031 return DAG.getBitcast(VT, Result);
18035 // v4i32 Non Uniform Shifts.
18036 // If the shift amount is constant we can shift each lane using the SSE2
18037 // immediate shifts, else we need to zero-extend each lane to the lower i64
18038 // and shift using the SSE2 variable shifts.
18039 // The separate results can then be blended together.
18040 if (VT == MVT::v4i32) {
18041 unsigned Opc = Op.getOpcode();
18042 SDValue Amt0, Amt1, Amt2, Amt3;
18043 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18044 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18045 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18046 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18047 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18049 // ISD::SHL is handled above but we include it here for completeness.
18052 llvm_unreachable("Unknown target vector shift node");
18054 Opc = X86ISD::VSHL;
18057 Opc = X86ISD::VSRL;
18060 Opc = X86ISD::VSRA;
18063 // The SSE2 shifts use the lower i64 as the same shift amount for
18064 // all lanes and the upper i64 is ignored. These shuffle masks
18065 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18066 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18067 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18068 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18069 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18070 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18073 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18074 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18075 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18076 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18077 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18078 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18079 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18082 if (VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget->hasInt256())) {
18083 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18084 unsigned ShiftOpcode = Op->getOpcode();
18086 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18087 // On SSE41 targets we make use of the fact that VSELECT lowers
18088 // to PBLENDVB which selects bytes based just on the sign bit.
18089 if (Subtarget->hasSSE41()) {
18090 V0 = DAG.getBitcast(VT, V0);
18091 V1 = DAG.getBitcast(VT, V1);
18092 Sel = DAG.getBitcast(VT, Sel);
18093 return DAG.getBitcast(SelVT,
18094 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18096 // On pre-SSE41 targets we test for the sign bit by comparing to
18097 // zero - a negative value will set all bits of the lanes to true
18098 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18099 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18100 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18101 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18104 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18105 // We can safely do this using i16 shifts as we're only interested in
18106 // the 3 lower bits of each byte.
18107 Amt = DAG.getBitcast(ExtVT, Amt);
18108 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18109 Amt = DAG.getBitcast(VT, Amt);
18111 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18112 // r = VSELECT(r, shift(r, 4), a);
18114 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18115 R = SignBitSelect(VT, Amt, M, R);
18118 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18120 // r = VSELECT(r, shift(r, 2), a);
18121 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18122 R = SignBitSelect(VT, Amt, M, R);
18125 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18127 // return VSELECT(r, shift(r, 1), a);
18128 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18129 R = SignBitSelect(VT, Amt, M, R);
18133 if (Op->getOpcode() == ISD::SRA) {
18134 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18135 // so we can correctly sign extend. We don't care what happens to the
18137 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18138 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18139 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18140 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18141 ALo = DAG.getBitcast(ExtVT, ALo);
18142 AHi = DAG.getBitcast(ExtVT, AHi);
18143 RLo = DAG.getBitcast(ExtVT, RLo);
18144 RHi = DAG.getBitcast(ExtVT, RHi);
18146 // r = VSELECT(r, shift(r, 4), a);
18147 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18148 DAG.getConstant(4, dl, ExtVT));
18149 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18150 DAG.getConstant(4, dl, ExtVT));
18151 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18152 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18155 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18156 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18158 // r = VSELECT(r, shift(r, 2), a);
18159 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18160 DAG.getConstant(2, dl, ExtVT));
18161 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18162 DAG.getConstant(2, dl, ExtVT));
18163 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18164 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18167 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18168 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18170 // r = VSELECT(r, shift(r, 1), a);
18171 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18172 DAG.getConstant(1, dl, ExtVT));
18173 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18174 DAG.getConstant(1, dl, ExtVT));
18175 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18176 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18178 // Logical shift the result back to the lower byte, leaving a zero upper
18180 // meaning that we can safely pack with PACKUSWB.
18182 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18184 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18185 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18189 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18190 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18191 // solution better.
18192 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18193 MVT ExtVT = MVT::v8i32;
18195 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18196 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18197 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18198 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18199 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18202 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
18203 MVT ExtVT = MVT::v8i32;
18204 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18205 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18206 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18207 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18208 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18209 ALo = DAG.getBitcast(ExtVT, ALo);
18210 AHi = DAG.getBitcast(ExtVT, AHi);
18211 RLo = DAG.getBitcast(ExtVT, RLo);
18212 RHi = DAG.getBitcast(ExtVT, RHi);
18213 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18214 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18215 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18216 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18217 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18220 if (VT == MVT::v8i16) {
18221 unsigned ShiftOpcode = Op->getOpcode();
18223 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18224 // On SSE41 targets we make use of the fact that VSELECT lowers
18225 // to PBLENDVB which selects bytes based just on the sign bit.
18226 if (Subtarget->hasSSE41()) {
18227 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18228 V0 = DAG.getBitcast(ExtVT, V0);
18229 V1 = DAG.getBitcast(ExtVT, V1);
18230 Sel = DAG.getBitcast(ExtVT, Sel);
18231 return DAG.getBitcast(
18232 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18234 // On pre-SSE41 targets we splat the sign bit - a negative value will
18235 // set all bits of the lanes to true and VSELECT uses that in
18236 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18238 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18239 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18242 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18243 if (Subtarget->hasSSE41()) {
18244 // On SSE41 targets we need to replicate the shift mask in both
18245 // bytes for PBLENDVB.
18248 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18249 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18251 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18254 // r = VSELECT(r, shift(r, 8), a);
18255 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18256 R = SignBitSelect(Amt, M, R);
18259 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18261 // r = VSELECT(r, shift(r, 4), a);
18262 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18263 R = SignBitSelect(Amt, M, R);
18266 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18268 // r = VSELECT(r, shift(r, 2), a);
18269 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18270 R = SignBitSelect(Amt, M, R);
18273 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18275 // return VSELECT(r, shift(r, 1), a);
18276 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18277 R = SignBitSelect(Amt, M, R);
18281 // Decompose 256-bit shifts into smaller 128-bit shifts.
18282 if (VT.is256BitVector()) {
18283 unsigned NumElems = VT.getVectorNumElements();
18284 MVT EltVT = VT.getVectorElementType();
18285 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18287 // Extract the two vectors
18288 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18289 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18291 // Recreate the shift amount vectors
18292 SDValue Amt1, Amt2;
18293 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18294 // Constant shift amount
18295 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18296 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18297 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18299 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18300 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18302 // Variable shift amount
18303 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18304 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18307 // Issue new vector shifts for the smaller types
18308 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18309 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18311 // Concatenate the result back
18312 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18318 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18319 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18320 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18321 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18322 // has only one use.
18323 SDNode *N = Op.getNode();
18324 SDValue LHS = N->getOperand(0);
18325 SDValue RHS = N->getOperand(1);
18326 unsigned BaseOp = 0;
18329 switch (Op.getOpcode()) {
18330 default: llvm_unreachable("Unknown ovf instruction!");
18332 // A subtract of one will be selected as a INC. Note that INC doesn't
18333 // set CF, so we can't do this for UADDO.
18334 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18336 BaseOp = X86ISD::INC;
18337 Cond = X86::COND_O;
18340 BaseOp = X86ISD::ADD;
18341 Cond = X86::COND_O;
18344 BaseOp = X86ISD::ADD;
18345 Cond = X86::COND_B;
18348 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18349 // set CF, so we can't do this for USUBO.
18350 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18352 BaseOp = X86ISD::DEC;
18353 Cond = X86::COND_O;
18356 BaseOp = X86ISD::SUB;
18357 Cond = X86::COND_O;
18360 BaseOp = X86ISD::SUB;
18361 Cond = X86::COND_B;
18364 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18365 Cond = X86::COND_O;
18367 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18368 if (N->getValueType(0) == MVT::i8) {
18369 BaseOp = X86ISD::UMUL8;
18370 Cond = X86::COND_O;
18373 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18375 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18378 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18379 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18380 SDValue(Sum.getNode(), 2));
18382 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18386 // Also sets EFLAGS.
18387 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18388 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18391 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18392 DAG.getConstant(Cond, DL, MVT::i32),
18393 SDValue(Sum.getNode(), 1));
18395 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18398 /// Returns true if the operand type is exactly twice the native width, and
18399 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18400 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18401 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18402 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18403 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18406 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18407 else if (OpWidth == 128)
18408 return Subtarget->hasCmpxchg16b();
18413 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18414 return needsCmpXchgNb(SI->getValueOperand()->getType());
18417 // Note: this turns large loads into lock cmpxchg8b/16b.
18418 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18419 TargetLowering::AtomicExpansionKind
18420 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18421 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18422 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
18423 : AtomicExpansionKind::None;
18426 TargetLowering::AtomicExpansionKind
18427 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18428 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18429 Type *MemType = AI->getType();
18431 // If the operand is too big, we must see if cmpxchg8/16b is available
18432 // and default to library calls otherwise.
18433 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18434 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
18435 : AtomicExpansionKind::None;
18438 AtomicRMWInst::BinOp Op = AI->getOperation();
18441 llvm_unreachable("Unknown atomic operation");
18442 case AtomicRMWInst::Xchg:
18443 case AtomicRMWInst::Add:
18444 case AtomicRMWInst::Sub:
18445 // It's better to use xadd, xsub or xchg for these in all cases.
18446 return AtomicExpansionKind::None;
18447 case AtomicRMWInst::Or:
18448 case AtomicRMWInst::And:
18449 case AtomicRMWInst::Xor:
18450 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18451 // prefix to a normal instruction for these operations.
18452 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
18453 : AtomicExpansionKind::None;
18454 case AtomicRMWInst::Nand:
18455 case AtomicRMWInst::Max:
18456 case AtomicRMWInst::Min:
18457 case AtomicRMWInst::UMax:
18458 case AtomicRMWInst::UMin:
18459 // These always require a non-trivial set of data operations on x86. We must
18460 // use a cmpxchg loop.
18461 return AtomicExpansionKind::CmpXChg;
18465 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18466 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18467 // no-sse2). There isn't any reason to disable it if the target processor
18469 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18473 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18474 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18475 Type *MemType = AI->getType();
18476 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18477 // there is no benefit in turning such RMWs into loads, and it is actually
18478 // harmful as it introduces a mfence.
18479 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18482 auto Builder = IRBuilder<>(AI);
18483 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18484 auto SynchScope = AI->getSynchScope();
18485 // We must restrict the ordering to avoid generating loads with Release or
18486 // ReleaseAcquire orderings.
18487 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18488 auto Ptr = AI->getPointerOperand();
18490 // Before the load we need a fence. Here is an example lifted from
18491 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18494 // x.store(1, relaxed);
18495 // r1 = y.fetch_add(0, release);
18497 // y.fetch_add(42, acquire);
18498 // r2 = x.load(relaxed);
18499 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18500 // lowered to just a load without a fence. A mfence flushes the store buffer,
18501 // making the optimization clearly correct.
18502 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18503 // otherwise, we might be able to be more aggressive on relaxed idempotent
18504 // rmw. In practice, they do not look useful, so we don't try to be
18505 // especially clever.
18506 if (SynchScope == SingleThread)
18507 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18508 // the IR level, so we must wrap it in an intrinsic.
18511 if (!hasMFENCE(*Subtarget))
18512 // FIXME: it might make sense to use a locked operation here but on a
18513 // different cache-line to prevent cache-line bouncing. In practice it
18514 // is probably a small win, and x86 processors without mfence are rare
18515 // enough that we do not bother.
18519 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
18520 Builder.CreateCall(MFence, {});
18522 // Finally we can emit the atomic load.
18523 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18524 AI->getType()->getPrimitiveSizeInBits());
18525 Loaded->setAtomic(Order, SynchScope);
18526 AI->replaceAllUsesWith(Loaded);
18527 AI->eraseFromParent();
18531 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18532 SelectionDAG &DAG) {
18534 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18535 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18536 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18537 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18539 // The only fence that needs an instruction is a sequentially-consistent
18540 // cross-thread fence.
18541 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18542 if (hasMFENCE(*Subtarget))
18543 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18545 SDValue Chain = Op.getOperand(0);
18546 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
18548 DAG.getRegister(X86::ESP, MVT::i32), // Base
18549 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
18550 DAG.getRegister(0, MVT::i32), // Index
18551 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
18552 DAG.getRegister(0, MVT::i32), // Segment.
18556 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18557 return SDValue(Res, 0);
18560 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18561 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18564 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18565 SelectionDAG &DAG) {
18566 MVT T = Op.getSimpleValueType();
18570 switch(T.SimpleTy) {
18571 default: llvm_unreachable("Invalid value type!");
18572 case MVT::i8: Reg = X86::AL; size = 1; break;
18573 case MVT::i16: Reg = X86::AX; size = 2; break;
18574 case MVT::i32: Reg = X86::EAX; size = 4; break;
18576 assert(Subtarget->is64Bit() && "Node not type legal!");
18577 Reg = X86::RAX; size = 8;
18580 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18581 Op.getOperand(2), SDValue());
18582 SDValue Ops[] = { cpIn.getValue(0),
18585 DAG.getTargetConstant(size, DL, MVT::i8),
18586 cpIn.getValue(1) };
18587 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18588 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18589 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18593 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18594 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18595 MVT::i32, cpOut.getValue(2));
18596 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18597 DAG.getConstant(X86::COND_E, DL, MVT::i8),
18600 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18601 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18602 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18606 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18607 SelectionDAG &DAG) {
18608 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18609 MVT DstVT = Op.getSimpleValueType();
18611 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18612 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18613 if (DstVT != MVT::f64)
18614 // This conversion needs to be expanded.
18617 SDValue InVec = Op->getOperand(0);
18619 unsigned NumElts = SrcVT.getVectorNumElements();
18620 EVT SVT = SrcVT.getVectorElementType();
18622 // Widen the vector in input in the case of MVT::v2i32.
18623 // Example: from MVT::v2i32 to MVT::v4i32.
18624 SmallVector<SDValue, 16> Elts;
18625 for (unsigned i = 0, e = NumElts; i != e; ++i)
18626 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18627 DAG.getIntPtrConstant(i, dl)));
18629 // Explicitly mark the extra elements as Undef.
18630 Elts.append(NumElts, DAG.getUNDEF(SVT));
18632 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18633 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18634 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
18635 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18636 DAG.getIntPtrConstant(0, dl));
18639 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18640 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18641 assert((DstVT == MVT::i64 ||
18642 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18643 "Unexpected custom BITCAST");
18644 // i64 <=> MMX conversions are Legal.
18645 if (SrcVT==MVT::i64 && DstVT.isVector())
18647 if (DstVT==MVT::i64 && SrcVT.isVector())
18649 // MMX <=> MMX conversions are Legal.
18650 if (SrcVT.isVector() && DstVT.isVector())
18652 // All other conversions need to be expanded.
18656 /// Compute the horizontal sum of bytes in V for the elements of VT.
18658 /// Requires V to be a byte vector and VT to be an integer vector type with
18659 /// wider elements than V's type. The width of the elements of VT determines
18660 /// how many bytes of V are summed horizontally to produce each element of the
18662 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
18663 const X86Subtarget *Subtarget,
18664 SelectionDAG &DAG) {
18666 MVT ByteVecVT = V.getSimpleValueType();
18667 MVT EltVT = VT.getVectorElementType();
18668 int NumElts = VT.getVectorNumElements();
18669 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
18670 "Expected value to have byte element type.");
18671 assert(EltVT != MVT::i8 &&
18672 "Horizontal byte sum only makes sense for wider elements!");
18673 unsigned VecSize = VT.getSizeInBits();
18674 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
18676 // PSADBW instruction horizontally add all bytes and leave the result in i64
18677 // chunks, thus directly computes the pop count for v2i64 and v4i64.
18678 if (EltVT == MVT::i64) {
18679 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18680 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
18681 return DAG.getBitcast(VT, V);
18684 if (EltVT == MVT::i32) {
18685 // We unpack the low half and high half into i32s interleaved with zeros so
18686 // that we can use PSADBW to horizontally sum them. The most useful part of
18687 // this is that it lines up the results of two PSADBW instructions to be
18688 // two v2i64 vectors which concatenated are the 4 population counts. We can
18689 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
18690 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
18691 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
18692 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
18694 // Do the horizontal sums into two v2i64s.
18695 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18696 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18697 DAG.getBitcast(ByteVecVT, Low), Zeros);
18698 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18699 DAG.getBitcast(ByteVecVT, High), Zeros);
18701 // Merge them together.
18702 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
18703 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
18704 DAG.getBitcast(ShortVecVT, Low),
18705 DAG.getBitcast(ShortVecVT, High));
18707 return DAG.getBitcast(VT, V);
18710 // The only element type left is i16.
18711 assert(EltVT == MVT::i16 && "Unknown how to handle type");
18713 // To obtain pop count for each i16 element starting from the pop count for
18714 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
18715 // right by 8. It is important to shift as i16s as i8 vector shift isn't
18716 // directly supported.
18717 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
18718 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
18719 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18720 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
18721 DAG.getBitcast(ByteVecVT, V));
18722 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18725 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
18726 const X86Subtarget *Subtarget,
18727 SelectionDAG &DAG) {
18728 MVT VT = Op.getSimpleValueType();
18729 MVT EltVT = VT.getVectorElementType();
18730 unsigned VecSize = VT.getSizeInBits();
18732 // Implement a lookup table in register by using an algorithm based on:
18733 // http://wm.ite.pl/articles/sse-popcount.html
18735 // The general idea is that every lower byte nibble in the input vector is an
18736 // index into a in-register pre-computed pop count table. We then split up the
18737 // input vector in two new ones: (1) a vector with only the shifted-right
18738 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
18739 // masked out higher ones) for each byte. PSHUB is used separately with both
18740 // to index the in-register table. Next, both are added and the result is a
18741 // i8 vector where each element contains the pop count for input byte.
18743 // To obtain the pop count for elements != i8, we follow up with the same
18744 // approach and use additional tricks as described below.
18746 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
18747 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
18748 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
18749 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
18751 int NumByteElts = VecSize / 8;
18752 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
18753 SDValue In = DAG.getBitcast(ByteVecVT, Op);
18754 SmallVector<SDValue, 16> LUTVec;
18755 for (int i = 0; i < NumByteElts; ++i)
18756 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
18757 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
18758 SmallVector<SDValue, 16> Mask0F(NumByteElts,
18759 DAG.getConstant(0x0F, DL, MVT::i8));
18760 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
18763 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
18764 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
18765 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
18768 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
18770 // The input vector is used as the shuffle mask that index elements into the
18771 // LUT. After counting low and high nibbles, add the vector to obtain the
18772 // final pop count per i8 element.
18773 SDValue HighPopCnt =
18774 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
18775 SDValue LowPopCnt =
18776 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
18777 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
18779 if (EltVT == MVT::i8)
18782 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
18785 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
18786 const X86Subtarget *Subtarget,
18787 SelectionDAG &DAG) {
18788 MVT VT = Op.getSimpleValueType();
18789 assert(VT.is128BitVector() &&
18790 "Only 128-bit vector bitmath lowering supported.");
18792 int VecSize = VT.getSizeInBits();
18793 MVT EltVT = VT.getVectorElementType();
18794 int Len = EltVT.getSizeInBits();
18796 // This is the vectorized version of the "best" algorithm from
18797 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
18798 // with a minor tweak to use a series of adds + shifts instead of vector
18799 // multiplications. Implemented for all integer vector types. We only use
18800 // this when we don't have SSSE3 which allows a LUT-based lowering that is
18801 // much faster, even faster than using native popcnt instructions.
18803 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
18804 MVT VT = V.getSimpleValueType();
18805 SmallVector<SDValue, 32> Shifters(
18806 VT.getVectorNumElements(),
18807 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
18808 return DAG.getNode(OpCode, DL, VT, V,
18809 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
18811 auto GetMask = [&](SDValue V, APInt Mask) {
18812 MVT VT = V.getSimpleValueType();
18813 SmallVector<SDValue, 32> Masks(
18814 VT.getVectorNumElements(),
18815 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
18816 return DAG.getNode(ISD::AND, DL, VT, V,
18817 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
18820 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
18821 // x86, so set the SRL type to have elements at least i16 wide. This is
18822 // correct because all of our SRLs are followed immediately by a mask anyways
18823 // that handles any bits that sneak into the high bits of the byte elements.
18824 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
18828 // v = v - ((v >> 1) & 0x55555555...)
18830 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
18831 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
18832 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
18834 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
18835 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
18836 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
18837 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
18838 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
18840 // v = (v + (v >> 4)) & 0x0F0F0F0F...
18841 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
18842 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
18843 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
18845 // At this point, V contains the byte-wise population count, and we are
18846 // merely doing a horizontal sum if necessary to get the wider element
18848 if (EltVT == MVT::i8)
18851 return LowerHorizontalByteSum(
18852 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
18856 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
18857 SelectionDAG &DAG) {
18858 MVT VT = Op.getSimpleValueType();
18859 // FIXME: Need to add AVX-512 support here!
18860 assert((VT.is256BitVector() || VT.is128BitVector()) &&
18861 "Unknown CTPOP type to handle");
18862 SDLoc DL(Op.getNode());
18863 SDValue Op0 = Op.getOperand(0);
18865 if (!Subtarget->hasSSSE3()) {
18866 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
18867 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
18868 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
18871 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
18872 unsigned NumElems = VT.getVectorNumElements();
18874 // Extract each 128-bit vector, compute pop count and concat the result.
18875 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
18876 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
18878 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
18879 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
18880 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
18883 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
18886 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
18887 SelectionDAG &DAG) {
18888 assert(Op.getValueType().isVector() &&
18889 "We only do custom lowering for vector population count.");
18890 return LowerVectorCTPOP(Op, Subtarget, DAG);
18893 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18894 SDNode *Node = Op.getNode();
18896 EVT T = Node->getValueType(0);
18897 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18898 DAG.getConstant(0, dl, T), Node->getOperand(2));
18899 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18900 cast<AtomicSDNode>(Node)->getMemoryVT(),
18901 Node->getOperand(0),
18902 Node->getOperand(1), negOp,
18903 cast<AtomicSDNode>(Node)->getMemOperand(),
18904 cast<AtomicSDNode>(Node)->getOrdering(),
18905 cast<AtomicSDNode>(Node)->getSynchScope());
18908 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18909 SDNode *Node = Op.getNode();
18911 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18913 // Convert seq_cst store -> xchg
18914 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18915 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18916 // (The only way to get a 16-byte store is cmpxchg16b)
18917 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18918 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18919 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18920 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18921 cast<AtomicSDNode>(Node)->getMemoryVT(),
18922 Node->getOperand(0),
18923 Node->getOperand(1), Node->getOperand(2),
18924 cast<AtomicSDNode>(Node)->getMemOperand(),
18925 cast<AtomicSDNode>(Node)->getOrdering(),
18926 cast<AtomicSDNode>(Node)->getSynchScope());
18927 return Swap.getValue(1);
18929 // Other atomic stores have a simple pattern.
18933 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18934 EVT VT = Op.getNode()->getSimpleValueType(0);
18936 // Let legalize expand this if it isn't a legal type yet.
18937 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18940 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18943 bool ExtraOp = false;
18944 switch (Op.getOpcode()) {
18945 default: llvm_unreachable("Invalid code");
18946 case ISD::ADDC: Opc = X86ISD::ADD; break;
18947 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18948 case ISD::SUBC: Opc = X86ISD::SUB; break;
18949 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18953 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18955 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18956 Op.getOperand(1), Op.getOperand(2));
18959 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18960 SelectionDAG &DAG) {
18961 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18963 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18964 // which returns the values as { float, float } (in XMM0) or
18965 // { double, double } (which is returned in XMM0, XMM1).
18967 SDValue Arg = Op.getOperand(0);
18968 EVT ArgVT = Arg.getValueType();
18969 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18971 TargetLowering::ArgListTy Args;
18972 TargetLowering::ArgListEntry Entry;
18976 Entry.isSExt = false;
18977 Entry.isZExt = false;
18978 Args.push_back(Entry);
18980 bool isF64 = ArgVT == MVT::f64;
18981 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18982 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18983 // the results are returned via SRet in memory.
18984 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18985 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18987 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
18989 Type *RetTy = isF64
18990 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
18991 : (Type*)VectorType::get(ArgTy, 4);
18993 TargetLowering::CallLoweringInfo CLI(DAG);
18994 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18995 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18997 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19000 // Returned in xmm0 and xmm1.
19001 return CallResult.first;
19003 // Returned in bits 0:31 and 32:64 xmm0.
19004 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19005 CallResult.first, DAG.getIntPtrConstant(0, dl));
19006 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19007 CallResult.first, DAG.getIntPtrConstant(1, dl));
19008 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19009 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19012 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19013 SelectionDAG &DAG) {
19014 assert(Subtarget->hasAVX512() &&
19015 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19017 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19018 EVT VT = N->getValue().getValueType();
19019 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19022 // X86 scatter kills mask register, so its type should be added to
19023 // the list of return values
19024 if (N->getNumValues() == 1) {
19025 SDValue Index = N->getIndex();
19026 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19027 !Index.getValueType().is512BitVector())
19028 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19030 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19031 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19032 N->getOperand(3), Index };
19034 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19035 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19036 return SDValue(NewScatter.getNode(), 0);
19041 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19042 SelectionDAG &DAG) {
19043 assert(Subtarget->hasAVX512() &&
19044 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19046 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19047 EVT VT = Op.getValueType();
19048 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19051 SDValue Index = N->getIndex();
19052 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19053 !Index.getValueType().is512BitVector()) {
19054 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19055 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19056 N->getOperand(3), Index };
19057 DAG.UpdateNodeOperands(N, Ops);
19062 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19063 SelectionDAG &DAG) const {
19064 // TODO: Eventually, the lowering of these nodes should be informed by or
19065 // deferred to the GC strategy for the function in which they appear. For
19066 // now, however, they must be lowered to something. Since they are logically
19067 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19068 // require special handling for these nodes), lower them as literal NOOPs for
19070 SmallVector<SDValue, 2> Ops;
19072 Ops.push_back(Op.getOperand(0));
19073 if (Op->getGluedNode())
19074 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19077 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19078 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19083 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19084 SelectionDAG &DAG) const {
19085 // TODO: Eventually, the lowering of these nodes should be informed by or
19086 // deferred to the GC strategy for the function in which they appear. For
19087 // now, however, they must be lowered to something. Since they are logically
19088 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19089 // require special handling for these nodes), lower them as literal NOOPs for
19091 SmallVector<SDValue, 2> Ops;
19093 Ops.push_back(Op.getOperand(0));
19094 if (Op->getGluedNode())
19095 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19098 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19099 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19104 /// LowerOperation - Provide custom lowering hooks for some operations.
19106 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19107 switch (Op.getOpcode()) {
19108 default: llvm_unreachable("Should not custom lower this!");
19109 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19110 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19111 return LowerCMP_SWAP(Op, Subtarget, DAG);
19112 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19113 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19114 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19115 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19116 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19117 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19118 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19119 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19120 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19121 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19122 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19123 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19124 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19125 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19126 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19127 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19128 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19129 case ISD::SHL_PARTS:
19130 case ISD::SRA_PARTS:
19131 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19132 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19133 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19134 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19135 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19136 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19137 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19138 case ISD::SIGN_EXTEND_VECTOR_INREG:
19139 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19140 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19141 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19142 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19143 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19145 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19146 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19147 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19148 case ISD::SETCC: return LowerSETCC(Op, DAG);
19149 case ISD::SELECT: return LowerSELECT(Op, DAG);
19150 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19151 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19152 case ISD::VASTART: return LowerVASTART(Op, DAG);
19153 case ISD::VAARG: return LowerVAARG(Op, DAG);
19154 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19155 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19156 case ISD::INTRINSIC_VOID:
19157 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19158 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19159 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19160 case ISD::FRAME_TO_ARGS_OFFSET:
19161 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19162 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19163 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19164 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19165 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19166 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19167 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19168 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19169 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19170 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19171 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19172 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19173 case ISD::UMUL_LOHI:
19174 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19177 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19183 case ISD::UMULO: return LowerXALUO(Op, DAG);
19184 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19185 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19189 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19190 case ISD::ADD: return LowerADD(Op, DAG);
19191 case ISD::SUB: return LowerSUB(Op, DAG);
19195 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19196 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19197 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19198 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19199 case ISD::GC_TRANSITION_START:
19200 return LowerGC_TRANSITION_START(Op, DAG);
19201 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19205 /// ReplaceNodeResults - Replace a node with an illegal result type
19206 /// with a new node built out of custom code.
19207 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19208 SmallVectorImpl<SDValue>&Results,
19209 SelectionDAG &DAG) const {
19211 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19212 switch (N->getOpcode()) {
19214 llvm_unreachable("Do not know how to custom type legalize this operation!");
19215 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19216 case X86ISD::FMINC:
19218 case X86ISD::FMAXC:
19219 case X86ISD::FMAX: {
19220 EVT VT = N->getValueType(0);
19221 if (VT != MVT::v2f32)
19222 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
19223 SDValue UNDEF = DAG.getUNDEF(VT);
19224 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19225 N->getOperand(0), UNDEF);
19226 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19227 N->getOperand(1), UNDEF);
19228 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19231 case ISD::SIGN_EXTEND_INREG:
19236 // We don't want to expand or promote these.
19243 case ISD::UDIVREM: {
19244 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19245 Results.push_back(V);
19248 case ISD::FP_TO_SINT:
19249 case ISD::FP_TO_UINT: {
19250 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19252 std::pair<SDValue,SDValue> Vals =
19253 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19254 SDValue FIST = Vals.first, StackSlot = Vals.second;
19255 if (FIST.getNode()) {
19256 EVT VT = N->getValueType(0);
19257 // Return a load from the stack slot.
19258 if (StackSlot.getNode())
19259 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19260 MachinePointerInfo(),
19261 false, false, false, 0));
19263 Results.push_back(FIST);
19267 case ISD::UINT_TO_FP: {
19268 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19269 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19270 N->getValueType(0) != MVT::v2f32)
19272 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19274 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19276 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19277 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19278 DAG.getBitcast(MVT::v2i64, VBias));
19279 Or = DAG.getBitcast(MVT::v2f64, Or);
19280 // TODO: Are there any fast-math-flags to propagate here?
19281 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19282 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19285 case ISD::FP_ROUND: {
19286 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19288 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19289 Results.push_back(V);
19292 case ISD::FP_EXTEND: {
19293 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19294 // No other ValueType for FP_EXTEND should reach this point.
19295 assert(N->getValueType(0) == MVT::v2f32 &&
19296 "Do not know how to legalize this Node");
19299 case ISD::INTRINSIC_W_CHAIN: {
19300 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19302 default : llvm_unreachable("Do not know how to custom type "
19303 "legalize this intrinsic operation!");
19304 case Intrinsic::x86_rdtsc:
19305 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19307 case Intrinsic::x86_rdtscp:
19308 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19310 case Intrinsic::x86_rdpmc:
19311 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19314 case ISD::READCYCLECOUNTER: {
19315 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19318 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19319 EVT T = N->getValueType(0);
19320 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19321 bool Regs64bit = T == MVT::i128;
19322 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19323 SDValue cpInL, cpInH;
19324 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19325 DAG.getConstant(0, dl, HalfT));
19326 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19327 DAG.getConstant(1, dl, HalfT));
19328 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19329 Regs64bit ? X86::RAX : X86::EAX,
19331 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19332 Regs64bit ? X86::RDX : X86::EDX,
19333 cpInH, cpInL.getValue(1));
19334 SDValue swapInL, swapInH;
19335 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19336 DAG.getConstant(0, dl, HalfT));
19337 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19338 DAG.getConstant(1, dl, HalfT));
19339 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19340 Regs64bit ? X86::RBX : X86::EBX,
19341 swapInL, cpInH.getValue(1));
19342 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19343 Regs64bit ? X86::RCX : X86::ECX,
19344 swapInH, swapInL.getValue(1));
19345 SDValue Ops[] = { swapInH.getValue(0),
19347 swapInH.getValue(1) };
19348 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19349 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19350 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19351 X86ISD::LCMPXCHG8_DAG;
19352 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19353 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19354 Regs64bit ? X86::RAX : X86::EAX,
19355 HalfT, Result.getValue(1));
19356 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19357 Regs64bit ? X86::RDX : X86::EDX,
19358 HalfT, cpOutL.getValue(2));
19359 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19361 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19362 MVT::i32, cpOutH.getValue(2));
19364 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19365 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19366 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19368 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19369 Results.push_back(Success);
19370 Results.push_back(EFLAGS.getValue(1));
19373 case ISD::ATOMIC_SWAP:
19374 case ISD::ATOMIC_LOAD_ADD:
19375 case ISD::ATOMIC_LOAD_SUB:
19376 case ISD::ATOMIC_LOAD_AND:
19377 case ISD::ATOMIC_LOAD_OR:
19378 case ISD::ATOMIC_LOAD_XOR:
19379 case ISD::ATOMIC_LOAD_NAND:
19380 case ISD::ATOMIC_LOAD_MIN:
19381 case ISD::ATOMIC_LOAD_MAX:
19382 case ISD::ATOMIC_LOAD_UMIN:
19383 case ISD::ATOMIC_LOAD_UMAX:
19384 case ISD::ATOMIC_LOAD: {
19385 // Delegate to generic TypeLegalization. Situations we can really handle
19386 // should have already been dealt with by AtomicExpandPass.cpp.
19389 case ISD::BITCAST: {
19390 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19391 EVT DstVT = N->getValueType(0);
19392 EVT SrcVT = N->getOperand(0)->getValueType(0);
19394 if (SrcVT != MVT::f64 ||
19395 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19398 unsigned NumElts = DstVT.getVectorNumElements();
19399 EVT SVT = DstVT.getVectorElementType();
19400 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19401 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19402 MVT::v2f64, N->getOperand(0));
19403 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19405 if (ExperimentalVectorWideningLegalization) {
19406 // If we are legalizing vectors by widening, we already have the desired
19407 // legal vector type, just return it.
19408 Results.push_back(ToVecInt);
19412 SmallVector<SDValue, 8> Elts;
19413 for (unsigned i = 0, e = NumElts; i != e; ++i)
19414 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19415 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19417 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19422 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19423 switch ((X86ISD::NodeType)Opcode) {
19424 case X86ISD::FIRST_NUMBER: break;
19425 case X86ISD::BSF: return "X86ISD::BSF";
19426 case X86ISD::BSR: return "X86ISD::BSR";
19427 case X86ISD::SHLD: return "X86ISD::SHLD";
19428 case X86ISD::SHRD: return "X86ISD::SHRD";
19429 case X86ISD::FAND: return "X86ISD::FAND";
19430 case X86ISD::FANDN: return "X86ISD::FANDN";
19431 case X86ISD::FOR: return "X86ISD::FOR";
19432 case X86ISD::FXOR: return "X86ISD::FXOR";
19433 case X86ISD::FILD: return "X86ISD::FILD";
19434 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19435 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19436 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19437 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19438 case X86ISD::FLD: return "X86ISD::FLD";
19439 case X86ISD::FST: return "X86ISD::FST";
19440 case X86ISD::CALL: return "X86ISD::CALL";
19441 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19442 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19443 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19444 case X86ISD::BT: return "X86ISD::BT";
19445 case X86ISD::CMP: return "X86ISD::CMP";
19446 case X86ISD::COMI: return "X86ISD::COMI";
19447 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19448 case X86ISD::CMPM: return "X86ISD::CMPM";
19449 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19450 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
19451 case X86ISD::SETCC: return "X86ISD::SETCC";
19452 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19453 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19454 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
19455 case X86ISD::CMOV: return "X86ISD::CMOV";
19456 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19457 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19458 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19459 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19460 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19461 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19462 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19463 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
19464 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
19465 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
19466 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19467 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19468 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19469 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19470 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19471 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
19472 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19473 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19474 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19475 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19476 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19477 case X86ISD::ADDUS: return "X86ISD::ADDUS";
19478 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19479 case X86ISD::HADD: return "X86ISD::HADD";
19480 case X86ISD::HSUB: return "X86ISD::HSUB";
19481 case X86ISD::FHADD: return "X86ISD::FHADD";
19482 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19483 case X86ISD::ABS: return "X86ISD::ABS";
19484 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
19485 case X86ISD::FMAX: return "X86ISD::FMAX";
19486 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
19487 case X86ISD::FMIN: return "X86ISD::FMIN";
19488 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
19489 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19490 case X86ISD::FMINC: return "X86ISD::FMINC";
19491 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19492 case X86ISD::FRCP: return "X86ISD::FRCP";
19493 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
19494 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
19495 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19496 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19497 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19498 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19499 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19500 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19501 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19502 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19503 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19504 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19505 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19506 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19507 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19508 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19509 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19510 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19511 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19512 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
19513 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
19514 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19515 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19516 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19517 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
19518 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
19519 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19520 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19521 case X86ISD::VSHL: return "X86ISD::VSHL";
19522 case X86ISD::VSRL: return "X86ISD::VSRL";
19523 case X86ISD::VSRA: return "X86ISD::VSRA";
19524 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19525 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19526 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19527 case X86ISD::CMPP: return "X86ISD::CMPP";
19528 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19529 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19530 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19531 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19532 case X86ISD::ADD: return "X86ISD::ADD";
19533 case X86ISD::SUB: return "X86ISD::SUB";
19534 case X86ISD::ADC: return "X86ISD::ADC";
19535 case X86ISD::SBB: return "X86ISD::SBB";
19536 case X86ISD::SMUL: return "X86ISD::SMUL";
19537 case X86ISD::UMUL: return "X86ISD::UMUL";
19538 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19539 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19540 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19541 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19542 case X86ISD::INC: return "X86ISD::INC";
19543 case X86ISD::DEC: return "X86ISD::DEC";
19544 case X86ISD::OR: return "X86ISD::OR";
19545 case X86ISD::XOR: return "X86ISD::XOR";
19546 case X86ISD::AND: return "X86ISD::AND";
19547 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19548 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19549 case X86ISD::PTEST: return "X86ISD::PTEST";
19550 case X86ISD::TESTP: return "X86ISD::TESTP";
19551 case X86ISD::TESTM: return "X86ISD::TESTM";
19552 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19553 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19554 case X86ISD::KTEST: return "X86ISD::KTEST";
19555 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19556 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19557 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19558 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19559 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19560 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19561 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19562 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19563 case X86ISD::SHUF128: return "X86ISD::SHUF128";
19564 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19565 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19566 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19567 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19568 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19569 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19570 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19571 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19572 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19573 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19574 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19575 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19576 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19577 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
19578 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19579 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
19580 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19581 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19582 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19583 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19584 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19585 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19586 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
19587 case X86ISD::VRANGE: return "X86ISD::VRANGE";
19588 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19589 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19590 case X86ISD::PSADBW: return "X86ISD::PSADBW";
19591 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
19592 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19593 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19594 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19595 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19596 case X86ISD::MFENCE: return "X86ISD::MFENCE";
19597 case X86ISD::SFENCE: return "X86ISD::SFENCE";
19598 case X86ISD::LFENCE: return "X86ISD::LFENCE";
19599 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19600 case X86ISD::SAHF: return "X86ISD::SAHF";
19601 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19602 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19603 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
19604 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
19605 case X86ISD::FMADD: return "X86ISD::FMADD";
19606 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19607 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19608 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19609 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19610 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19611 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
19612 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
19613 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
19614 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
19615 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
19616 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
19617 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
19618 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
19619 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
19620 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19621 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19622 case X86ISD::XTEST: return "X86ISD::XTEST";
19623 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19624 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19625 case X86ISD::SELECT: return "X86ISD::SELECT";
19626 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
19627 case X86ISD::RCP28: return "X86ISD::RCP28";
19628 case X86ISD::EXP2: return "X86ISD::EXP2";
19629 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
19630 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
19631 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
19632 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
19633 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
19634 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
19635 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
19636 case X86ISD::SCALEF: return "X86ISD::SCALEF";
19637 case X86ISD::ADDS: return "X86ISD::ADDS";
19638 case X86ISD::SUBS: return "X86ISD::SUBS";
19639 case X86ISD::AVG: return "X86ISD::AVG";
19640 case X86ISD::MULHRS: return "X86ISD::MULHRS";
19641 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
19642 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
19643 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
19644 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
19649 // isLegalAddressingMode - Return true if the addressing mode represented
19650 // by AM is legal for this target, for a load/store of the specified type.
19651 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
19652 const AddrMode &AM, Type *Ty,
19653 unsigned AS) const {
19654 // X86 supports extremely general addressing modes.
19655 CodeModel::Model M = getTargetMachine().getCodeModel();
19656 Reloc::Model R = getTargetMachine().getRelocationModel();
19658 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19659 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19664 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19666 // If a reference to this global requires an extra load, we can't fold it.
19667 if (isGlobalStubReference(GVFlags))
19670 // If BaseGV requires a register for the PIC base, we cannot also have a
19671 // BaseReg specified.
19672 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19675 // If lower 4G is not available, then we must use rip-relative addressing.
19676 if ((M != CodeModel::Small || R != Reloc::Static) &&
19677 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19681 switch (AM.Scale) {
19687 // These scales always work.
19692 // These scales are formed with basereg+scalereg. Only accept if there is
19697 default: // Other stuff never works.
19704 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19705 unsigned Bits = Ty->getScalarSizeInBits();
19707 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19708 // particularly cheaper than those without.
19712 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19713 // variable shifts just as cheap as scalar ones.
19714 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19717 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19718 // fully general vector.
19722 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19723 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19725 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19726 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19727 return NumBits1 > NumBits2;
19730 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19731 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19734 if (!isTypeLegal(EVT::getEVT(Ty1)))
19737 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19739 // Assuming the caller doesn't have a zeroext or signext return parameter,
19740 // truncation all the way down to i1 is valid.
19744 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19745 return isInt<32>(Imm);
19748 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19749 // Can also use sub to handle negated immediates.
19750 return isInt<32>(Imm);
19753 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19754 if (!VT1.isInteger() || !VT2.isInteger())
19756 unsigned NumBits1 = VT1.getSizeInBits();
19757 unsigned NumBits2 = VT2.getSizeInBits();
19758 return NumBits1 > NumBits2;
19761 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19762 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19763 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19766 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19767 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19768 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19771 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19772 EVT VT1 = Val.getValueType();
19773 if (isZExtFree(VT1, VT2))
19776 if (Val.getOpcode() != ISD::LOAD)
19779 if (!VT1.isSimple() || !VT1.isInteger() ||
19780 !VT2.isSimple() || !VT2.isInteger())
19783 switch (VT1.getSimpleVT().SimpleTy) {
19788 // X86 has 8, 16, and 32-bit zero-extending loads.
19795 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
19798 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19799 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
19802 VT = VT.getScalarType();
19804 if (!VT.isSimple())
19807 switch (VT.getSimpleVT().SimpleTy) {
19818 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19819 // i16 instructions are longer (0x66 prefix) and potentially slower.
19820 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19823 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19824 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19825 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19826 /// are assumed to be legal.
19828 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19830 if (!VT.isSimple())
19833 // Not for i1 vectors
19834 if (VT.getScalarType() == MVT::i1)
19837 // Very little shuffling can be done for 64-bit vectors right now.
19838 if (VT.getSizeInBits() == 64)
19841 // We only care that the types being shuffled are legal. The lowering can
19842 // handle any possible shuffle mask that results.
19843 return isTypeLegal(VT.getSimpleVT());
19847 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19849 // Just delegate to the generic legality, clear masks aren't special.
19850 return isShuffleMaskLegal(Mask, VT);
19853 //===----------------------------------------------------------------------===//
19854 // X86 Scheduler Hooks
19855 //===----------------------------------------------------------------------===//
19857 /// Utility function to emit xbegin specifying the start of an RTM region.
19858 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19859 const TargetInstrInfo *TII) {
19860 DebugLoc DL = MI->getDebugLoc();
19862 const BasicBlock *BB = MBB->getBasicBlock();
19863 MachineFunction::iterator I = MBB;
19866 // For the v = xbegin(), we generate
19877 MachineBasicBlock *thisMBB = MBB;
19878 MachineFunction *MF = MBB->getParent();
19879 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19880 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19881 MF->insert(I, mainMBB);
19882 MF->insert(I, sinkMBB);
19884 // Transfer the remainder of BB and its successor edges to sinkMBB.
19885 sinkMBB->splice(sinkMBB->begin(), MBB,
19886 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19887 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19891 // # fallthrough to mainMBB
19892 // # abortion to sinkMBB
19893 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19894 thisMBB->addSuccessor(mainMBB);
19895 thisMBB->addSuccessor(sinkMBB);
19899 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19900 mainMBB->addSuccessor(sinkMBB);
19903 // EAX is live into the sinkMBB
19904 sinkMBB->addLiveIn(X86::EAX);
19905 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19906 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19909 MI->eraseFromParent();
19913 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19914 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19915 // in the .td file.
19916 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19917 const TargetInstrInfo *TII) {
19919 switch (MI->getOpcode()) {
19920 default: llvm_unreachable("illegal opcode!");
19921 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19922 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19923 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19924 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19925 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19926 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19927 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19928 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19931 DebugLoc dl = MI->getDebugLoc();
19932 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19934 unsigned NumArgs = MI->getNumOperands();
19935 for (unsigned i = 1; i < NumArgs; ++i) {
19936 MachineOperand &Op = MI->getOperand(i);
19937 if (!(Op.isReg() && Op.isImplicit()))
19938 MIB.addOperand(Op);
19940 if (MI->hasOneMemOperand())
19941 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19943 BuildMI(*BB, MI, dl,
19944 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19945 .addReg(X86::XMM0);
19947 MI->eraseFromParent();
19951 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19952 // defs in an instruction pattern
19953 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19954 const TargetInstrInfo *TII) {
19956 switch (MI->getOpcode()) {
19957 default: llvm_unreachable("illegal opcode!");
19958 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19959 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19960 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19961 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19962 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19963 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19964 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19965 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19968 DebugLoc dl = MI->getDebugLoc();
19969 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19971 unsigned NumArgs = MI->getNumOperands(); // remove the results
19972 for (unsigned i = 1; i < NumArgs; ++i) {
19973 MachineOperand &Op = MI->getOperand(i);
19974 if (!(Op.isReg() && Op.isImplicit()))
19975 MIB.addOperand(Op);
19977 if (MI->hasOneMemOperand())
19978 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19980 BuildMI(*BB, MI, dl,
19981 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19984 MI->eraseFromParent();
19988 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19989 const X86Subtarget *Subtarget) {
19990 DebugLoc dl = MI->getDebugLoc();
19991 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19992 // Address into RAX/EAX, other two args into ECX, EDX.
19993 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19994 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19995 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19996 for (int i = 0; i < X86::AddrNumOperands; ++i)
19997 MIB.addOperand(MI->getOperand(i));
19999 unsigned ValOps = X86::AddrNumOperands;
20000 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20001 .addReg(MI->getOperand(ValOps).getReg());
20002 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20003 .addReg(MI->getOperand(ValOps+1).getReg());
20005 // The instruction doesn't actually take any operands though.
20006 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20008 MI->eraseFromParent(); // The pseudo is gone now.
20012 MachineBasicBlock *
20013 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20014 MachineBasicBlock *MBB) const {
20015 // Emit va_arg instruction on X86-64.
20017 // Operands to this pseudo-instruction:
20018 // 0 ) Output : destination address (reg)
20019 // 1-5) Input : va_list address (addr, i64mem)
20020 // 6 ) ArgSize : Size (in bytes) of vararg type
20021 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20022 // 8 ) Align : Alignment of type
20023 // 9 ) EFLAGS (implicit-def)
20025 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20026 static_assert(X86::AddrNumOperands == 5,
20027 "VAARG_64 assumes 5 address operands");
20029 unsigned DestReg = MI->getOperand(0).getReg();
20030 MachineOperand &Base = MI->getOperand(1);
20031 MachineOperand &Scale = MI->getOperand(2);
20032 MachineOperand &Index = MI->getOperand(3);
20033 MachineOperand &Disp = MI->getOperand(4);
20034 MachineOperand &Segment = MI->getOperand(5);
20035 unsigned ArgSize = MI->getOperand(6).getImm();
20036 unsigned ArgMode = MI->getOperand(7).getImm();
20037 unsigned Align = MI->getOperand(8).getImm();
20039 // Memory Reference
20040 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20041 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20042 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20044 // Machine Information
20045 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20046 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20047 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20048 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20049 DebugLoc DL = MI->getDebugLoc();
20051 // struct va_list {
20054 // i64 overflow_area (address)
20055 // i64 reg_save_area (address)
20057 // sizeof(va_list) = 24
20058 // alignment(va_list) = 8
20060 unsigned TotalNumIntRegs = 6;
20061 unsigned TotalNumXMMRegs = 8;
20062 bool UseGPOffset = (ArgMode == 1);
20063 bool UseFPOffset = (ArgMode == 2);
20064 unsigned MaxOffset = TotalNumIntRegs * 8 +
20065 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20067 /* Align ArgSize to a multiple of 8 */
20068 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20069 bool NeedsAlign = (Align > 8);
20071 MachineBasicBlock *thisMBB = MBB;
20072 MachineBasicBlock *overflowMBB;
20073 MachineBasicBlock *offsetMBB;
20074 MachineBasicBlock *endMBB;
20076 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20077 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20078 unsigned OffsetReg = 0;
20080 if (!UseGPOffset && !UseFPOffset) {
20081 // If we only pull from the overflow region, we don't create a branch.
20082 // We don't need to alter control flow.
20083 OffsetDestReg = 0; // unused
20084 OverflowDestReg = DestReg;
20086 offsetMBB = nullptr;
20087 overflowMBB = thisMBB;
20090 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20091 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20092 // If not, pull from overflow_area. (branch to overflowMBB)
20097 // offsetMBB overflowMBB
20102 // Registers for the PHI in endMBB
20103 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20104 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20106 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20107 MachineFunction *MF = MBB->getParent();
20108 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20109 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20110 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20112 MachineFunction::iterator MBBIter = MBB;
20115 // Insert the new basic blocks
20116 MF->insert(MBBIter, offsetMBB);
20117 MF->insert(MBBIter, overflowMBB);
20118 MF->insert(MBBIter, endMBB);
20120 // Transfer the remainder of MBB and its successor edges to endMBB.
20121 endMBB->splice(endMBB->begin(), thisMBB,
20122 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20123 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20125 // Make offsetMBB and overflowMBB successors of thisMBB
20126 thisMBB->addSuccessor(offsetMBB);
20127 thisMBB->addSuccessor(overflowMBB);
20129 // endMBB is a successor of both offsetMBB and overflowMBB
20130 offsetMBB->addSuccessor(endMBB);
20131 overflowMBB->addSuccessor(endMBB);
20133 // Load the offset value into a register
20134 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20135 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20139 .addDisp(Disp, UseFPOffset ? 4 : 0)
20140 .addOperand(Segment)
20141 .setMemRefs(MMOBegin, MMOEnd);
20143 // Check if there is enough room left to pull this argument.
20144 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20146 .addImm(MaxOffset + 8 - ArgSizeA8);
20148 // Branch to "overflowMBB" if offset >= max
20149 // Fall through to "offsetMBB" otherwise
20150 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20151 .addMBB(overflowMBB);
20154 // In offsetMBB, emit code to use the reg_save_area.
20156 assert(OffsetReg != 0);
20158 // Read the reg_save_area address.
20159 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20160 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20165 .addOperand(Segment)
20166 .setMemRefs(MMOBegin, MMOEnd);
20168 // Zero-extend the offset
20169 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20170 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20173 .addImm(X86::sub_32bit);
20175 // Add the offset to the reg_save_area to get the final address.
20176 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20177 .addReg(OffsetReg64)
20178 .addReg(RegSaveReg);
20180 // Compute the offset for the next argument
20181 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20182 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20184 .addImm(UseFPOffset ? 16 : 8);
20186 // Store it back into the va_list.
20187 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20191 .addDisp(Disp, UseFPOffset ? 4 : 0)
20192 .addOperand(Segment)
20193 .addReg(NextOffsetReg)
20194 .setMemRefs(MMOBegin, MMOEnd);
20197 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20202 // Emit code to use overflow area
20205 // Load the overflow_area address into a register.
20206 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20207 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20212 .addOperand(Segment)
20213 .setMemRefs(MMOBegin, MMOEnd);
20215 // If we need to align it, do so. Otherwise, just copy the address
20216 // to OverflowDestReg.
20218 // Align the overflow address
20219 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20220 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20222 // aligned_addr = (addr + (align-1)) & ~(align-1)
20223 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20224 .addReg(OverflowAddrReg)
20227 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20229 .addImm(~(uint64_t)(Align-1));
20231 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20232 .addReg(OverflowAddrReg);
20235 // Compute the next overflow address after this argument.
20236 // (the overflow address should be kept 8-byte aligned)
20237 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20238 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20239 .addReg(OverflowDestReg)
20240 .addImm(ArgSizeA8);
20242 // Store the new overflow address.
20243 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20248 .addOperand(Segment)
20249 .addReg(NextAddrReg)
20250 .setMemRefs(MMOBegin, MMOEnd);
20252 // If we branched, emit the PHI to the front of endMBB.
20254 BuildMI(*endMBB, endMBB->begin(), DL,
20255 TII->get(X86::PHI), DestReg)
20256 .addReg(OffsetDestReg).addMBB(offsetMBB)
20257 .addReg(OverflowDestReg).addMBB(overflowMBB);
20260 // Erase the pseudo instruction
20261 MI->eraseFromParent();
20266 MachineBasicBlock *
20267 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20269 MachineBasicBlock *MBB) const {
20270 // Emit code to save XMM registers to the stack. The ABI says that the
20271 // number of registers to save is given in %al, so it's theoretically
20272 // possible to do an indirect jump trick to avoid saving all of them,
20273 // however this code takes a simpler approach and just executes all
20274 // of the stores if %al is non-zero. It's less code, and it's probably
20275 // easier on the hardware branch predictor, and stores aren't all that
20276 // expensive anyway.
20278 // Create the new basic blocks. One block contains all the XMM stores,
20279 // and one block is the final destination regardless of whether any
20280 // stores were performed.
20281 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20282 MachineFunction *F = MBB->getParent();
20283 MachineFunction::iterator MBBIter = MBB;
20285 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20286 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20287 F->insert(MBBIter, XMMSaveMBB);
20288 F->insert(MBBIter, EndMBB);
20290 // Transfer the remainder of MBB and its successor edges to EndMBB.
20291 EndMBB->splice(EndMBB->begin(), MBB,
20292 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20293 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20295 // The original block will now fall through to the XMM save block.
20296 MBB->addSuccessor(XMMSaveMBB);
20297 // The XMMSaveMBB will fall through to the end block.
20298 XMMSaveMBB->addSuccessor(EndMBB);
20300 // Now add the instructions.
20301 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20302 DebugLoc DL = MI->getDebugLoc();
20304 unsigned CountReg = MI->getOperand(0).getReg();
20305 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20306 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20308 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20309 // If %al is 0, branch around the XMM save block.
20310 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20311 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20312 MBB->addSuccessor(EndMBB);
20315 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20316 // that was just emitted, but clearly shouldn't be "saved".
20317 assert((MI->getNumOperands() <= 3 ||
20318 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20319 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20320 && "Expected last argument to be EFLAGS");
20321 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20322 // In the XMM save block, save all the XMM argument registers.
20323 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20324 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20325 MachineMemOperand *MMO = F->getMachineMemOperand(
20326 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20327 MachineMemOperand::MOStore,
20328 /*Size=*/16, /*Align=*/16);
20329 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20330 .addFrameIndex(RegSaveFrameIndex)
20331 .addImm(/*Scale=*/1)
20332 .addReg(/*IndexReg=*/0)
20333 .addImm(/*Disp=*/Offset)
20334 .addReg(/*Segment=*/0)
20335 .addReg(MI->getOperand(i).getReg())
20336 .addMemOperand(MMO);
20339 MI->eraseFromParent(); // The pseudo instruction is gone now.
20344 // The EFLAGS operand of SelectItr might be missing a kill marker
20345 // because there were multiple uses of EFLAGS, and ISel didn't know
20346 // which to mark. Figure out whether SelectItr should have had a
20347 // kill marker, and set it if it should. Returns the correct kill
20349 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20350 MachineBasicBlock* BB,
20351 const TargetRegisterInfo* TRI) {
20352 // Scan forward through BB for a use/def of EFLAGS.
20353 MachineBasicBlock::iterator miI(std::next(SelectItr));
20354 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20355 const MachineInstr& mi = *miI;
20356 if (mi.readsRegister(X86::EFLAGS))
20358 if (mi.definesRegister(X86::EFLAGS))
20359 break; // Should have kill-flag - update below.
20362 // If we hit the end of the block, check whether EFLAGS is live into a
20364 if (miI == BB->end()) {
20365 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20366 sEnd = BB->succ_end();
20367 sItr != sEnd; ++sItr) {
20368 MachineBasicBlock* succ = *sItr;
20369 if (succ->isLiveIn(X86::EFLAGS))
20374 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20375 // out. SelectMI should have a kill flag on EFLAGS.
20376 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20380 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20381 // together with other CMOV pseudo-opcodes into a single basic-block with
20382 // conditional jump around it.
20383 static bool isCMOVPseudo(MachineInstr *MI) {
20384 switch (MI->getOpcode()) {
20385 case X86::CMOV_FR32:
20386 case X86::CMOV_FR64:
20387 case X86::CMOV_GR8:
20388 case X86::CMOV_GR16:
20389 case X86::CMOV_GR32:
20390 case X86::CMOV_RFP32:
20391 case X86::CMOV_RFP64:
20392 case X86::CMOV_RFP80:
20393 case X86::CMOV_V2F64:
20394 case X86::CMOV_V2I64:
20395 case X86::CMOV_V4F32:
20396 case X86::CMOV_V4F64:
20397 case X86::CMOV_V4I64:
20398 case X86::CMOV_V16F32:
20399 case X86::CMOV_V8F32:
20400 case X86::CMOV_V8F64:
20401 case X86::CMOV_V8I64:
20402 case X86::CMOV_V8I1:
20403 case X86::CMOV_V16I1:
20404 case X86::CMOV_V32I1:
20405 case X86::CMOV_V64I1:
20413 MachineBasicBlock *
20414 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20415 MachineBasicBlock *BB) const {
20416 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20417 DebugLoc DL = MI->getDebugLoc();
20419 // To "insert" a SELECT_CC instruction, we actually have to insert the
20420 // diamond control-flow pattern. The incoming instruction knows the
20421 // destination vreg to set, the condition code register to branch on, the
20422 // true/false values to select between, and a branch opcode to use.
20423 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20424 MachineFunction::iterator It = BB;
20430 // cmpTY ccX, r1, r2
20432 // fallthrough --> copy0MBB
20433 MachineBasicBlock *thisMBB = BB;
20434 MachineFunction *F = BB->getParent();
20436 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20437 // as described above, by inserting a BB, and then making a PHI at the join
20438 // point to select the true and false operands of the CMOV in the PHI.
20440 // The code also handles two different cases of multiple CMOV opcodes
20444 // In this case, there are multiple CMOVs in a row, all which are based on
20445 // the same condition setting (or the exact opposite condition setting).
20446 // In this case we can lower all the CMOVs using a single inserted BB, and
20447 // then make a number of PHIs at the join point to model the CMOVs. The only
20448 // trickiness here, is that in a case like:
20450 // t2 = CMOV cond1 t1, f1
20451 // t3 = CMOV cond1 t2, f2
20453 // when rewriting this into PHIs, we have to perform some renaming on the
20454 // temps since you cannot have a PHI operand refer to a PHI result earlier
20455 // in the same block. The "simple" but wrong lowering would be:
20457 // t2 = PHI t1(BB1), f1(BB2)
20458 // t3 = PHI t2(BB1), f2(BB2)
20460 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
20461 // renaming is to note that on the path through BB1, t2 is really just a
20462 // copy of t1, and do that renaming, properly generating:
20464 // t2 = PHI t1(BB1), f1(BB2)
20465 // t3 = PHI t1(BB1), f2(BB2)
20467 // Case 2, we lower cascaded CMOVs such as
20469 // (CMOV (CMOV F, T, cc1), T, cc2)
20471 // to two successives branches. For that, we look for another CMOV as the
20472 // following instruction.
20474 // Without this, we would add a PHI between the two jumps, which ends up
20475 // creating a few copies all around. For instance, for
20477 // (sitofp (zext (fcmp une)))
20479 // we would generate:
20481 // ucomiss %xmm1, %xmm0
20482 // movss <1.0f>, %xmm0
20483 // movaps %xmm0, %xmm1
20485 // xorps %xmm1, %xmm1
20488 // movaps %xmm1, %xmm0
20492 // because this custom-inserter would have generated:
20504 // A: X = ...; Y = ...
20506 // C: Z = PHI [X, A], [Y, B]
20508 // E: PHI [X, C], [Z, D]
20510 // If we lower both CMOVs in a single step, we can instead generate:
20522 // A: X = ...; Y = ...
20524 // E: PHI [X, A], [X, C], [Y, D]
20526 // Which, in our sitofp/fcmp example, gives us something like:
20528 // ucomiss %xmm1, %xmm0
20529 // movss <1.0f>, %xmm0
20532 // xorps %xmm0, %xmm0
20536 MachineInstr *CascadedCMOV = nullptr;
20537 MachineInstr *LastCMOV = MI;
20538 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
20539 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
20540 MachineBasicBlock::iterator NextMIIt =
20541 std::next(MachineBasicBlock::iterator(MI));
20543 // Check for case 1, where there are multiple CMOVs with the same condition
20544 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
20545 // number of jumps the most.
20547 if (isCMOVPseudo(MI)) {
20548 // See if we have a string of CMOVS with the same condition.
20549 while (NextMIIt != BB->end() &&
20550 isCMOVPseudo(NextMIIt) &&
20551 (NextMIIt->getOperand(3).getImm() == CC ||
20552 NextMIIt->getOperand(3).getImm() == OppCC)) {
20553 LastCMOV = &*NextMIIt;
20558 // This checks for case 2, but only do this if we didn't already find
20559 // case 1, as indicated by LastCMOV == MI.
20560 if (LastCMOV == MI &&
20561 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
20562 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
20563 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
20564 CascadedCMOV = &*NextMIIt;
20567 MachineBasicBlock *jcc1MBB = nullptr;
20569 // If we have a cascaded CMOV, we lower it to two successive branches to
20570 // the same block. EFLAGS is used by both, so mark it as live in the second.
20571 if (CascadedCMOV) {
20572 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
20573 F->insert(It, jcc1MBB);
20574 jcc1MBB->addLiveIn(X86::EFLAGS);
20577 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20578 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20579 F->insert(It, copy0MBB);
20580 F->insert(It, sinkMBB);
20582 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20583 // live into the sink and copy blocks.
20584 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
20586 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
20587 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
20588 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
20589 copy0MBB->addLiveIn(X86::EFLAGS);
20590 sinkMBB->addLiveIn(X86::EFLAGS);
20593 // Transfer the remainder of BB and its successor edges to sinkMBB.
20594 sinkMBB->splice(sinkMBB->begin(), BB,
20595 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
20596 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20598 // Add the true and fallthrough blocks as its successors.
20599 if (CascadedCMOV) {
20600 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
20601 BB->addSuccessor(jcc1MBB);
20603 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
20604 // jump to the sinkMBB.
20605 jcc1MBB->addSuccessor(copy0MBB);
20606 jcc1MBB->addSuccessor(sinkMBB);
20608 BB->addSuccessor(copy0MBB);
20611 // The true block target of the first (or only) branch is always sinkMBB.
20612 BB->addSuccessor(sinkMBB);
20614 // Create the conditional branch instruction.
20615 unsigned Opc = X86::GetCondBranchFromCond(CC);
20616 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20618 if (CascadedCMOV) {
20619 unsigned Opc2 = X86::GetCondBranchFromCond(
20620 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
20621 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
20625 // %FalseValue = ...
20626 // # fallthrough to sinkMBB
20627 copy0MBB->addSuccessor(sinkMBB);
20630 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20632 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
20633 MachineBasicBlock::iterator MIItEnd =
20634 std::next(MachineBasicBlock::iterator(LastCMOV));
20635 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
20636 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
20637 MachineInstrBuilder MIB;
20639 // As we are creating the PHIs, we have to be careful if there is more than
20640 // one. Later CMOVs may reference the results of earlier CMOVs, but later
20641 // PHIs have to reference the individual true/false inputs from earlier PHIs.
20642 // That also means that PHI construction must work forward from earlier to
20643 // later, and that the code must maintain a mapping from earlier PHI's
20644 // destination registers, and the registers that went into the PHI.
20646 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
20647 unsigned DestReg = MIIt->getOperand(0).getReg();
20648 unsigned Op1Reg = MIIt->getOperand(1).getReg();
20649 unsigned Op2Reg = MIIt->getOperand(2).getReg();
20651 // If this CMOV we are generating is the opposite condition from
20652 // the jump we generated, then we have to swap the operands for the
20653 // PHI that is going to be generated.
20654 if (MIIt->getOperand(3).getImm() == OppCC)
20655 std::swap(Op1Reg, Op2Reg);
20657 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
20658 Op1Reg = RegRewriteTable[Op1Reg].first;
20660 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
20661 Op2Reg = RegRewriteTable[Op2Reg].second;
20663 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
20664 TII->get(X86::PHI), DestReg)
20665 .addReg(Op1Reg).addMBB(copy0MBB)
20666 .addReg(Op2Reg).addMBB(thisMBB);
20668 // Add this PHI to the rewrite table.
20669 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
20672 // If we have a cascaded CMOV, the second Jcc provides the same incoming
20673 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
20674 if (CascadedCMOV) {
20675 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
20676 // Copy the PHI result to the register defined by the second CMOV.
20677 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
20678 DL, TII->get(TargetOpcode::COPY),
20679 CascadedCMOV->getOperand(0).getReg())
20680 .addReg(MI->getOperand(0).getReg());
20681 CascadedCMOV->eraseFromParent();
20684 // Now remove the CMOV(s).
20685 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
20686 (MIIt++)->eraseFromParent();
20691 MachineBasicBlock *
20692 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
20693 MachineBasicBlock *BB) const {
20694 // Combine the following atomic floating-point modification pattern:
20695 // a.store(reg OP a.load(acquire), release)
20696 // Transform them into:
20697 // OPss (%gpr), %xmm
20698 // movss %xmm, (%gpr)
20699 // Or sd equivalent for 64-bit operations.
20701 switch (MI->getOpcode()) {
20702 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
20703 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
20704 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
20706 const X86InstrInfo *TII = Subtarget->getInstrInfo();
20707 DebugLoc DL = MI->getDebugLoc();
20708 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
20709 unsigned MSrc = MI->getOperand(0).getReg();
20710 unsigned VSrc = MI->getOperand(5).getReg();
20711 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
20712 .addReg(/*Base=*/MSrc)
20713 .addImm(/*Scale=*/1)
20714 .addReg(/*Index=*/0)
20717 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
20718 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
20720 .addReg(/*Base=*/MSrc)
20721 .addImm(/*Scale=*/1)
20722 .addReg(/*Index=*/0)
20723 .addImm(/*Disp=*/0)
20724 .addReg(/*Segment=*/0);
20725 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
20726 MI->eraseFromParent(); // The pseudo instruction is gone now.
20730 MachineBasicBlock *
20731 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20732 MachineBasicBlock *BB) const {
20733 MachineFunction *MF = BB->getParent();
20734 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20735 DebugLoc DL = MI->getDebugLoc();
20736 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20738 assert(MF->shouldSplitStack());
20740 const bool Is64Bit = Subtarget->is64Bit();
20741 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20743 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20744 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20747 // ... [Till the alloca]
20748 // If stacklet is not large enough, jump to mallocMBB
20751 // Allocate by subtracting from RSP
20752 // Jump to continueMBB
20755 // Allocate by call to runtime
20759 // [rest of original BB]
20762 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20763 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20764 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20766 MachineRegisterInfo &MRI = MF->getRegInfo();
20767 const TargetRegisterClass *AddrRegClass =
20768 getRegClassFor(getPointerTy(MF->getDataLayout()));
20770 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20771 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20772 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20773 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20774 sizeVReg = MI->getOperand(1).getReg(),
20775 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20777 MachineFunction::iterator MBBIter = BB;
20780 MF->insert(MBBIter, bumpMBB);
20781 MF->insert(MBBIter, mallocMBB);
20782 MF->insert(MBBIter, continueMBB);
20784 continueMBB->splice(continueMBB->begin(), BB,
20785 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20786 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20788 // Add code to the main basic block to check if the stack limit has been hit,
20789 // and if so, jump to mallocMBB otherwise to bumpMBB.
20790 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20791 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20792 .addReg(tmpSPVReg).addReg(sizeVReg);
20793 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20794 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20795 .addReg(SPLimitVReg);
20796 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
20798 // bumpMBB simply decreases the stack pointer, since we know the current
20799 // stacklet has enough space.
20800 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20801 .addReg(SPLimitVReg);
20802 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20803 .addReg(SPLimitVReg);
20804 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20806 // Calls into a routine in libgcc to allocate more space from the heap.
20807 const uint32_t *RegMask =
20808 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
20810 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20812 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20813 .addExternalSymbol("__morestack_allocate_stack_space")
20814 .addRegMask(RegMask)
20815 .addReg(X86::RDI, RegState::Implicit)
20816 .addReg(X86::RAX, RegState::ImplicitDefine);
20817 } else if (Is64Bit) {
20818 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20820 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20821 .addExternalSymbol("__morestack_allocate_stack_space")
20822 .addRegMask(RegMask)
20823 .addReg(X86::EDI, RegState::Implicit)
20824 .addReg(X86::EAX, RegState::ImplicitDefine);
20826 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20828 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20829 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20830 .addExternalSymbol("__morestack_allocate_stack_space")
20831 .addRegMask(RegMask)
20832 .addReg(X86::EAX, RegState::ImplicitDefine);
20836 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20839 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20840 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20841 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20843 // Set up the CFG correctly.
20844 BB->addSuccessor(bumpMBB);
20845 BB->addSuccessor(mallocMBB);
20846 mallocMBB->addSuccessor(continueMBB);
20847 bumpMBB->addSuccessor(continueMBB);
20849 // Take care of the PHI nodes.
20850 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20851 MI->getOperand(0).getReg())
20852 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20853 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20855 // Delete the original pseudo instruction.
20856 MI->eraseFromParent();
20859 return continueMBB;
20862 MachineBasicBlock *
20863 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20864 MachineBasicBlock *BB) const {
20865 DebugLoc DL = MI->getDebugLoc();
20867 assert(!Subtarget->isTargetMachO());
20869 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
20872 MI->eraseFromParent(); // The pseudo instruction is gone now.
20876 MachineBasicBlock *
20877 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20878 MachineBasicBlock *BB) const {
20879 // This is pretty easy. We're taking the value that we received from
20880 // our load from the relocation, sticking it in either RDI (x86-64)
20881 // or EAX and doing an indirect call. The return value will then
20882 // be in the normal return register.
20883 MachineFunction *F = BB->getParent();
20884 const X86InstrInfo *TII = Subtarget->getInstrInfo();
20885 DebugLoc DL = MI->getDebugLoc();
20887 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20888 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20890 // Get a register mask for the lowered call.
20891 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20892 // proper register mask.
20893 const uint32_t *RegMask =
20894 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
20895 if (Subtarget->is64Bit()) {
20896 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20897 TII->get(X86::MOV64rm), X86::RDI)
20899 .addImm(0).addReg(0)
20900 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20901 MI->getOperand(3).getTargetFlags())
20903 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20904 addDirectMem(MIB, X86::RDI);
20905 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20906 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20907 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20908 TII->get(X86::MOV32rm), X86::EAX)
20910 .addImm(0).addReg(0)
20911 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20912 MI->getOperand(3).getTargetFlags())
20914 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20915 addDirectMem(MIB, X86::EAX);
20916 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20918 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20919 TII->get(X86::MOV32rm), X86::EAX)
20920 .addReg(TII->getGlobalBaseReg(F))
20921 .addImm(0).addReg(0)
20922 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20923 MI->getOperand(3).getTargetFlags())
20925 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20926 addDirectMem(MIB, X86::EAX);
20927 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20930 MI->eraseFromParent(); // The pseudo instruction is gone now.
20934 MachineBasicBlock *
20935 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20936 MachineBasicBlock *MBB) const {
20937 DebugLoc DL = MI->getDebugLoc();
20938 MachineFunction *MF = MBB->getParent();
20939 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20940 MachineRegisterInfo &MRI = MF->getRegInfo();
20942 const BasicBlock *BB = MBB->getBasicBlock();
20943 MachineFunction::iterator I = MBB;
20946 // Memory Reference
20947 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20948 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20951 unsigned MemOpndSlot = 0;
20953 unsigned CurOp = 0;
20955 DstReg = MI->getOperand(CurOp++).getReg();
20956 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20957 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20958 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20959 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20961 MemOpndSlot = CurOp;
20963 MVT PVT = getPointerTy(MF->getDataLayout());
20964 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20965 "Invalid Pointer Size!");
20967 // For v = setjmp(buf), we generate
20970 // buf[LabelOffset] = restoreMBB
20971 // SjLjSetup restoreMBB
20977 // v = phi(main, restore)
20980 // if base pointer being used, load it from frame
20983 MachineBasicBlock *thisMBB = MBB;
20984 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20985 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20986 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20987 MF->insert(I, mainMBB);
20988 MF->insert(I, sinkMBB);
20989 MF->push_back(restoreMBB);
20991 MachineInstrBuilder MIB;
20993 // Transfer the remainder of BB and its successor edges to sinkMBB.
20994 sinkMBB->splice(sinkMBB->begin(), MBB,
20995 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20996 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20999 unsigned PtrStoreOpc = 0;
21000 unsigned LabelReg = 0;
21001 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21002 Reloc::Model RM = MF->getTarget().getRelocationModel();
21003 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21004 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21006 // Prepare IP either in reg or imm.
21007 if (!UseImmLabel) {
21008 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21009 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21010 LabelReg = MRI.createVirtualRegister(PtrRC);
21011 if (Subtarget->is64Bit()) {
21012 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21016 .addMBB(restoreMBB)
21019 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21020 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21021 .addReg(XII->getGlobalBaseReg(MF))
21024 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21028 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21030 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21031 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21032 if (i == X86::AddrDisp)
21033 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21035 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21038 MIB.addReg(LabelReg);
21040 MIB.addMBB(restoreMBB);
21041 MIB.setMemRefs(MMOBegin, MMOEnd);
21043 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21044 .addMBB(restoreMBB);
21046 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21047 MIB.addRegMask(RegInfo->getNoPreservedMask());
21048 thisMBB->addSuccessor(mainMBB);
21049 thisMBB->addSuccessor(restoreMBB);
21053 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21054 mainMBB->addSuccessor(sinkMBB);
21057 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21058 TII->get(X86::PHI), DstReg)
21059 .addReg(mainDstReg).addMBB(mainMBB)
21060 .addReg(restoreDstReg).addMBB(restoreMBB);
21063 if (RegInfo->hasBasePointer(*MF)) {
21064 const bool Uses64BitFramePtr =
21065 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21066 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21067 X86FI->setRestoreBasePointer(MF);
21068 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21069 unsigned BasePtr = RegInfo->getBaseRegister();
21070 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21071 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21072 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21073 .setMIFlag(MachineInstr::FrameSetup);
21075 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21076 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21077 restoreMBB->addSuccessor(sinkMBB);
21079 MI->eraseFromParent();
21083 MachineBasicBlock *
21084 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21085 MachineBasicBlock *MBB) const {
21086 DebugLoc DL = MI->getDebugLoc();
21087 MachineFunction *MF = MBB->getParent();
21088 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21089 MachineRegisterInfo &MRI = MF->getRegInfo();
21091 // Memory Reference
21092 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21093 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21095 MVT PVT = getPointerTy(MF->getDataLayout());
21096 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21097 "Invalid Pointer Size!");
21099 const TargetRegisterClass *RC =
21100 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21101 unsigned Tmp = MRI.createVirtualRegister(RC);
21102 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21103 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21104 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21105 unsigned SP = RegInfo->getStackRegister();
21107 MachineInstrBuilder MIB;
21109 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21110 const int64_t SPOffset = 2 * PVT.getStoreSize();
21112 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21113 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21116 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21117 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21118 MIB.addOperand(MI->getOperand(i));
21119 MIB.setMemRefs(MMOBegin, MMOEnd);
21121 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21122 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21123 if (i == X86::AddrDisp)
21124 MIB.addDisp(MI->getOperand(i), LabelOffset);
21126 MIB.addOperand(MI->getOperand(i));
21128 MIB.setMemRefs(MMOBegin, MMOEnd);
21130 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21131 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21132 if (i == X86::AddrDisp)
21133 MIB.addDisp(MI->getOperand(i), SPOffset);
21135 MIB.addOperand(MI->getOperand(i));
21137 MIB.setMemRefs(MMOBegin, MMOEnd);
21139 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21141 MI->eraseFromParent();
21145 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21146 // accumulator loops. Writing back to the accumulator allows the coalescer
21147 // to remove extra copies in the loop.
21148 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21149 MachineBasicBlock *
21150 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21151 MachineBasicBlock *MBB) const {
21152 MachineOperand &AddendOp = MI->getOperand(3);
21154 // Bail out early if the addend isn't a register - we can't switch these.
21155 if (!AddendOp.isReg())
21158 MachineFunction &MF = *MBB->getParent();
21159 MachineRegisterInfo &MRI = MF.getRegInfo();
21161 // Check whether the addend is defined by a PHI:
21162 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21163 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21164 if (!AddendDef.isPHI())
21167 // Look for the following pattern:
21169 // %addend = phi [%entry, 0], [%loop, %result]
21171 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21175 // %addend = phi [%entry, 0], [%loop, %result]
21177 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21179 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21180 assert(AddendDef.getOperand(i).isReg());
21181 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21182 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21183 if (&PHISrcInst == MI) {
21184 // Found a matching instruction.
21185 unsigned NewFMAOpc = 0;
21186 switch (MI->getOpcode()) {
21187 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21188 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21189 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21190 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21191 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21192 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21193 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21194 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21195 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21196 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21197 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21198 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21199 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21200 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21201 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21202 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21203 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21204 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21205 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21206 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21208 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21209 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21210 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21211 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21212 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21213 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21214 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21215 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21216 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21217 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21218 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21219 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21220 default: llvm_unreachable("Unrecognized FMA variant.");
21223 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21224 MachineInstrBuilder MIB =
21225 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21226 .addOperand(MI->getOperand(0))
21227 .addOperand(MI->getOperand(3))
21228 .addOperand(MI->getOperand(2))
21229 .addOperand(MI->getOperand(1));
21230 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21231 MI->eraseFromParent();
21238 MachineBasicBlock *
21239 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21240 MachineBasicBlock *BB) const {
21241 switch (MI->getOpcode()) {
21242 default: llvm_unreachable("Unexpected instr type to insert");
21243 case X86::TAILJMPd64:
21244 case X86::TAILJMPr64:
21245 case X86::TAILJMPm64:
21246 case X86::TAILJMPd64_REX:
21247 case X86::TAILJMPr64_REX:
21248 case X86::TAILJMPm64_REX:
21249 llvm_unreachable("TAILJMP64 would not be touched here.");
21250 case X86::TCRETURNdi64:
21251 case X86::TCRETURNri64:
21252 case X86::TCRETURNmi64:
21254 case X86::WIN_ALLOCA:
21255 return EmitLoweredWinAlloca(MI, BB);
21256 case X86::SEG_ALLOCA_32:
21257 case X86::SEG_ALLOCA_64:
21258 return EmitLoweredSegAlloca(MI, BB);
21259 case X86::TLSCall_32:
21260 case X86::TLSCall_64:
21261 return EmitLoweredTLSCall(MI, BB);
21262 case X86::CMOV_FR32:
21263 case X86::CMOV_FR64:
21264 case X86::CMOV_GR8:
21265 case X86::CMOV_GR16:
21266 case X86::CMOV_GR32:
21267 case X86::CMOV_RFP32:
21268 case X86::CMOV_RFP64:
21269 case X86::CMOV_RFP80:
21270 case X86::CMOV_V2F64:
21271 case X86::CMOV_V2I64:
21272 case X86::CMOV_V4F32:
21273 case X86::CMOV_V4F64:
21274 case X86::CMOV_V4I64:
21275 case X86::CMOV_V16F32:
21276 case X86::CMOV_V8F32:
21277 case X86::CMOV_V8F64:
21278 case X86::CMOV_V8I64:
21279 case X86::CMOV_V8I1:
21280 case X86::CMOV_V16I1:
21281 case X86::CMOV_V32I1:
21282 case X86::CMOV_V64I1:
21283 return EmitLoweredSelect(MI, BB);
21285 case X86::RELEASE_FADD32mr:
21286 case X86::RELEASE_FADD64mr:
21287 return EmitLoweredAtomicFP(MI, BB);
21289 case X86::FP32_TO_INT16_IN_MEM:
21290 case X86::FP32_TO_INT32_IN_MEM:
21291 case X86::FP32_TO_INT64_IN_MEM:
21292 case X86::FP64_TO_INT16_IN_MEM:
21293 case X86::FP64_TO_INT32_IN_MEM:
21294 case X86::FP64_TO_INT64_IN_MEM:
21295 case X86::FP80_TO_INT16_IN_MEM:
21296 case X86::FP80_TO_INT32_IN_MEM:
21297 case X86::FP80_TO_INT64_IN_MEM: {
21298 MachineFunction *F = BB->getParent();
21299 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21300 DebugLoc DL = MI->getDebugLoc();
21302 // Change the floating point control register to use "round towards zero"
21303 // mode when truncating to an integer value.
21304 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21305 addFrameReference(BuildMI(*BB, MI, DL,
21306 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21308 // Load the old value of the high byte of the control word...
21310 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21311 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21314 // Set the high part to be round to zero...
21315 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21318 // Reload the modified control word now...
21319 addFrameReference(BuildMI(*BB, MI, DL,
21320 TII->get(X86::FLDCW16m)), CWFrameIdx);
21322 // Restore the memory image of control word to original value
21323 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21326 // Get the X86 opcode to use.
21328 switch (MI->getOpcode()) {
21329 default: llvm_unreachable("illegal opcode!");
21330 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21331 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21332 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21333 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21334 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21335 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21336 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21337 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21338 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21342 MachineOperand &Op = MI->getOperand(0);
21344 AM.BaseType = X86AddressMode::RegBase;
21345 AM.Base.Reg = Op.getReg();
21347 AM.BaseType = X86AddressMode::FrameIndexBase;
21348 AM.Base.FrameIndex = Op.getIndex();
21350 Op = MI->getOperand(1);
21352 AM.Scale = Op.getImm();
21353 Op = MI->getOperand(2);
21355 AM.IndexReg = Op.getImm();
21356 Op = MI->getOperand(3);
21357 if (Op.isGlobal()) {
21358 AM.GV = Op.getGlobal();
21360 AM.Disp = Op.getImm();
21362 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21363 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21365 // Reload the original control word now.
21366 addFrameReference(BuildMI(*BB, MI, DL,
21367 TII->get(X86::FLDCW16m)), CWFrameIdx);
21369 MI->eraseFromParent(); // The pseudo instruction is gone now.
21372 // String/text processing lowering.
21373 case X86::PCMPISTRM128REG:
21374 case X86::VPCMPISTRM128REG:
21375 case X86::PCMPISTRM128MEM:
21376 case X86::VPCMPISTRM128MEM:
21377 case X86::PCMPESTRM128REG:
21378 case X86::VPCMPESTRM128REG:
21379 case X86::PCMPESTRM128MEM:
21380 case X86::VPCMPESTRM128MEM:
21381 assert(Subtarget->hasSSE42() &&
21382 "Target must have SSE4.2 or AVX features enabled");
21383 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21385 // String/text processing lowering.
21386 case X86::PCMPISTRIREG:
21387 case X86::VPCMPISTRIREG:
21388 case X86::PCMPISTRIMEM:
21389 case X86::VPCMPISTRIMEM:
21390 case X86::PCMPESTRIREG:
21391 case X86::VPCMPESTRIREG:
21392 case X86::PCMPESTRIMEM:
21393 case X86::VPCMPESTRIMEM:
21394 assert(Subtarget->hasSSE42() &&
21395 "Target must have SSE4.2 or AVX features enabled");
21396 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21398 // Thread synchronization.
21400 return EmitMonitor(MI, BB, Subtarget);
21404 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21406 case X86::VASTART_SAVE_XMM_REGS:
21407 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21409 case X86::VAARG_64:
21410 return EmitVAARG64WithCustomInserter(MI, BB);
21412 case X86::EH_SjLj_SetJmp32:
21413 case X86::EH_SjLj_SetJmp64:
21414 return emitEHSjLjSetJmp(MI, BB);
21416 case X86::EH_SjLj_LongJmp32:
21417 case X86::EH_SjLj_LongJmp64:
21418 return emitEHSjLjLongJmp(MI, BB);
21420 case TargetOpcode::STATEPOINT:
21421 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21422 // this point in the process. We diverge later.
21423 return emitPatchPoint(MI, BB);
21425 case TargetOpcode::STACKMAP:
21426 case TargetOpcode::PATCHPOINT:
21427 return emitPatchPoint(MI, BB);
21429 case X86::VFMADDPDr213r:
21430 case X86::VFMADDPSr213r:
21431 case X86::VFMADDSDr213r:
21432 case X86::VFMADDSSr213r:
21433 case X86::VFMSUBPDr213r:
21434 case X86::VFMSUBPSr213r:
21435 case X86::VFMSUBSDr213r:
21436 case X86::VFMSUBSSr213r:
21437 case X86::VFNMADDPDr213r:
21438 case X86::VFNMADDPSr213r:
21439 case X86::VFNMADDSDr213r:
21440 case X86::VFNMADDSSr213r:
21441 case X86::VFNMSUBPDr213r:
21442 case X86::VFNMSUBPSr213r:
21443 case X86::VFNMSUBSDr213r:
21444 case X86::VFNMSUBSSr213r:
21445 case X86::VFMADDSUBPDr213r:
21446 case X86::VFMADDSUBPSr213r:
21447 case X86::VFMSUBADDPDr213r:
21448 case X86::VFMSUBADDPSr213r:
21449 case X86::VFMADDPDr213rY:
21450 case X86::VFMADDPSr213rY:
21451 case X86::VFMSUBPDr213rY:
21452 case X86::VFMSUBPSr213rY:
21453 case X86::VFNMADDPDr213rY:
21454 case X86::VFNMADDPSr213rY:
21455 case X86::VFNMSUBPDr213rY:
21456 case X86::VFNMSUBPSr213rY:
21457 case X86::VFMADDSUBPDr213rY:
21458 case X86::VFMADDSUBPSr213rY:
21459 case X86::VFMSUBADDPDr213rY:
21460 case X86::VFMSUBADDPSr213rY:
21461 return emitFMA3Instr(MI, BB);
21465 //===----------------------------------------------------------------------===//
21466 // X86 Optimization Hooks
21467 //===----------------------------------------------------------------------===//
21469 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21472 const SelectionDAG &DAG,
21473 unsigned Depth) const {
21474 unsigned BitWidth = KnownZero.getBitWidth();
21475 unsigned Opc = Op.getOpcode();
21476 assert((Opc >= ISD::BUILTIN_OP_END ||
21477 Opc == ISD::INTRINSIC_WO_CHAIN ||
21478 Opc == ISD::INTRINSIC_W_CHAIN ||
21479 Opc == ISD::INTRINSIC_VOID) &&
21480 "Should use MaskedValueIsZero if you don't know whether Op"
21481 " is a target node!");
21483 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21497 // These nodes' second result is a boolean.
21498 if (Op.getResNo() == 0)
21501 case X86ISD::SETCC:
21502 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21504 case ISD::INTRINSIC_WO_CHAIN: {
21505 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21506 unsigned NumLoBits = 0;
21509 case Intrinsic::x86_sse_movmsk_ps:
21510 case Intrinsic::x86_avx_movmsk_ps_256:
21511 case Intrinsic::x86_sse2_movmsk_pd:
21512 case Intrinsic::x86_avx_movmsk_pd_256:
21513 case Intrinsic::x86_mmx_pmovmskb:
21514 case Intrinsic::x86_sse2_pmovmskb_128:
21515 case Intrinsic::x86_avx2_pmovmskb: {
21516 // High bits of movmskp{s|d}, pmovmskb are known zero.
21518 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21519 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21520 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21521 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21522 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21523 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21524 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21525 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21527 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21536 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21538 const SelectionDAG &,
21539 unsigned Depth) const {
21540 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21541 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21542 return Op.getValueType().getScalarType().getSizeInBits();
21548 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21549 /// node is a GlobalAddress + offset.
21550 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21551 const GlobalValue* &GA,
21552 int64_t &Offset) const {
21553 if (N->getOpcode() == X86ISD::Wrapper) {
21554 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21555 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21556 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21560 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21563 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21564 /// same as extracting the high 128-bit part of 256-bit vector and then
21565 /// inserting the result into the low part of a new 256-bit vector
21566 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21567 EVT VT = SVOp->getValueType(0);
21568 unsigned NumElems = VT.getVectorNumElements();
21570 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21571 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21572 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21573 SVOp->getMaskElt(j) >= 0)
21579 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21580 /// same as extracting the low 128-bit part of 256-bit vector and then
21581 /// inserting the result into the high part of a new 256-bit vector
21582 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21583 EVT VT = SVOp->getValueType(0);
21584 unsigned NumElems = VT.getVectorNumElements();
21586 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21587 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21588 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21589 SVOp->getMaskElt(j) >= 0)
21595 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21596 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21597 TargetLowering::DAGCombinerInfo &DCI,
21598 const X86Subtarget* Subtarget) {
21600 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21601 SDValue V1 = SVOp->getOperand(0);
21602 SDValue V2 = SVOp->getOperand(1);
21603 EVT VT = SVOp->getValueType(0);
21604 unsigned NumElems = VT.getVectorNumElements();
21606 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21607 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21611 // V UNDEF BUILD_VECTOR UNDEF
21613 // CONCAT_VECTOR CONCAT_VECTOR
21616 // RESULT: V + zero extended
21618 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21619 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21620 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21623 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21626 // To match the shuffle mask, the first half of the mask should
21627 // be exactly the first vector, and all the rest a splat with the
21628 // first element of the second one.
21629 for (unsigned i = 0; i != NumElems/2; ++i)
21630 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21631 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21634 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21635 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21636 if (Ld->hasNUsesOfValue(1, 0)) {
21637 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21638 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21640 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21642 Ld->getPointerInfo(),
21643 Ld->getAlignment(),
21644 false/*isVolatile*/, true/*ReadMem*/,
21645 false/*WriteMem*/);
21647 // Make sure the newly-created LOAD is in the same position as Ld in
21648 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21649 // and update uses of Ld's output chain to use the TokenFactor.
21650 if (Ld->hasAnyUseOfValue(1)) {
21651 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21652 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21653 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21654 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21655 SDValue(ResNode.getNode(), 1));
21658 return DAG.getBitcast(VT, ResNode);
21662 // Emit a zeroed vector and insert the desired subvector on its
21664 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21665 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21666 return DCI.CombineTo(N, InsV);
21669 //===--------------------------------------------------------------------===//
21670 // Combine some shuffles into subvector extracts and inserts:
21673 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21674 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21675 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21676 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21677 return DCI.CombineTo(N, InsV);
21680 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21681 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21682 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21683 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21684 return DCI.CombineTo(N, InsV);
21690 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21693 /// This is the leaf of the recursive combinine below. When we have found some
21694 /// chain of single-use x86 shuffle instructions and accumulated the combined
21695 /// shuffle mask represented by them, this will try to pattern match that mask
21696 /// into either a single instruction if there is a special purpose instruction
21697 /// for this operation, or into a PSHUFB instruction which is a fully general
21698 /// instruction but should only be used to replace chains over a certain depth.
21699 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21700 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21701 TargetLowering::DAGCombinerInfo &DCI,
21702 const X86Subtarget *Subtarget) {
21703 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21705 // Find the operand that enters the chain. Note that multiple uses are OK
21706 // here, we're not going to remove the operand we find.
21707 SDValue Input = Op.getOperand(0);
21708 while (Input.getOpcode() == ISD::BITCAST)
21709 Input = Input.getOperand(0);
21711 MVT VT = Input.getSimpleValueType();
21712 MVT RootVT = Root.getSimpleValueType();
21715 // Just remove no-op shuffle masks.
21716 if (Mask.size() == 1) {
21717 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
21722 // Use the float domain if the operand type is a floating point type.
21723 bool FloatDomain = VT.isFloatingPoint();
21725 // For floating point shuffles, we don't have free copies in the shuffle
21726 // instructions or the ability to load as part of the instruction, so
21727 // canonicalize their shuffles to UNPCK or MOV variants.
21729 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21730 // vectors because it can have a load folded into it that UNPCK cannot. This
21731 // doesn't preclude something switching to the shorter encoding post-RA.
21733 // FIXME: Should teach these routines about AVX vector widths.
21734 if (FloatDomain && VT.getSizeInBits() == 128) {
21735 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
21736 bool Lo = Mask.equals({0, 0});
21739 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21740 // is no slower than UNPCKLPD but has the option to fold the input operand
21741 // into even an unaligned memory load.
21742 if (Lo && Subtarget->hasSSE3()) {
21743 Shuffle = X86ISD::MOVDDUP;
21744 ShuffleVT = MVT::v2f64;
21746 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21747 // than the UNPCK variants.
21748 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21749 ShuffleVT = MVT::v4f32;
21751 if (Depth == 1 && Root->getOpcode() == Shuffle)
21752 return false; // Nothing to do!
21753 Op = DAG.getBitcast(ShuffleVT, Input);
21754 DCI.AddToWorklist(Op.getNode());
21755 if (Shuffle == X86ISD::MOVDDUP)
21756 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21758 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21759 DCI.AddToWorklist(Op.getNode());
21760 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21764 if (Subtarget->hasSSE3() &&
21765 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
21766 bool Lo = Mask.equals({0, 0, 2, 2});
21767 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21768 MVT ShuffleVT = MVT::v4f32;
21769 if (Depth == 1 && Root->getOpcode() == Shuffle)
21770 return false; // Nothing to do!
21771 Op = DAG.getBitcast(ShuffleVT, Input);
21772 DCI.AddToWorklist(Op.getNode());
21773 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21774 DCI.AddToWorklist(Op.getNode());
21775 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21779 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
21780 bool Lo = Mask.equals({0, 0, 1, 1});
21781 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21782 MVT ShuffleVT = MVT::v4f32;
21783 if (Depth == 1 && Root->getOpcode() == Shuffle)
21784 return false; // Nothing to do!
21785 Op = DAG.getBitcast(ShuffleVT, Input);
21786 DCI.AddToWorklist(Op.getNode());
21787 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21788 DCI.AddToWorklist(Op.getNode());
21789 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21795 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21796 // variants as none of these have single-instruction variants that are
21797 // superior to the UNPCK formulation.
21798 if (!FloatDomain && VT.getSizeInBits() == 128 &&
21799 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
21800 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
21801 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
21803 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
21804 bool Lo = Mask[0] == 0;
21805 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21806 if (Depth == 1 && Root->getOpcode() == Shuffle)
21807 return false; // Nothing to do!
21809 switch (Mask.size()) {
21811 ShuffleVT = MVT::v8i16;
21814 ShuffleVT = MVT::v16i8;
21817 llvm_unreachable("Impossible mask size!");
21819 Op = DAG.getBitcast(ShuffleVT, Input);
21820 DCI.AddToWorklist(Op.getNode());
21821 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21822 DCI.AddToWorklist(Op.getNode());
21823 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21828 // Don't try to re-form single instruction chains under any circumstances now
21829 // that we've done encoding canonicalization for them.
21833 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21834 // can replace them with a single PSHUFB instruction profitably. Intel's
21835 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21836 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21837 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21838 SmallVector<SDValue, 16> PSHUFBMask;
21839 int NumBytes = VT.getSizeInBits() / 8;
21840 int Ratio = NumBytes / Mask.size();
21841 for (int i = 0; i < NumBytes; ++i) {
21842 if (Mask[i / Ratio] == SM_SentinelUndef) {
21843 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21846 int M = Mask[i / Ratio] != SM_SentinelZero
21847 ? Ratio * Mask[i / Ratio] + i % Ratio
21849 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
21851 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
21852 Op = DAG.getBitcast(ByteVT, Input);
21853 DCI.AddToWorklist(Op.getNode());
21854 SDValue PSHUFBMaskOp =
21855 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
21856 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21857 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
21858 DCI.AddToWorklist(Op.getNode());
21859 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21864 // Failed to find any combines.
21868 /// \brief Fully generic combining of x86 shuffle instructions.
21870 /// This should be the last combine run over the x86 shuffle instructions. Once
21871 /// they have been fully optimized, this will recursively consider all chains
21872 /// of single-use shuffle instructions, build a generic model of the cumulative
21873 /// shuffle operation, and check for simpler instructions which implement this
21874 /// operation. We use this primarily for two purposes:
21876 /// 1) Collapse generic shuffles to specialized single instructions when
21877 /// equivalent. In most cases, this is just an encoding size win, but
21878 /// sometimes we will collapse multiple generic shuffles into a single
21879 /// special-purpose shuffle.
21880 /// 2) Look for sequences of shuffle instructions with 3 or more total
21881 /// instructions, and replace them with the slightly more expensive SSSE3
21882 /// PSHUFB instruction if available. We do this as the last combining step
21883 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21884 /// a suitable short sequence of other instructions. The PHUFB will either
21885 /// use a register or have to read from memory and so is slightly (but only
21886 /// slightly) more expensive than the other shuffle instructions.
21888 /// Because this is inherently a quadratic operation (for each shuffle in
21889 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21890 /// This should never be an issue in practice as the shuffle lowering doesn't
21891 /// produce sequences of more than 8 instructions.
21893 /// FIXME: We will currently miss some cases where the redundant shuffling
21894 /// would simplify under the threshold for PSHUFB formation because of
21895 /// combine-ordering. To fix this, we should do the redundant instruction
21896 /// combining in this recursive walk.
21897 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21898 ArrayRef<int> RootMask,
21899 int Depth, bool HasPSHUFB,
21901 TargetLowering::DAGCombinerInfo &DCI,
21902 const X86Subtarget *Subtarget) {
21903 // Bound the depth of our recursive combine because this is ultimately
21904 // quadratic in nature.
21908 // Directly rip through bitcasts to find the underlying operand.
21909 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21910 Op = Op.getOperand(0);
21912 MVT VT = Op.getSimpleValueType();
21913 if (!VT.isVector())
21914 return false; // Bail if we hit a non-vector.
21916 assert(Root.getSimpleValueType().isVector() &&
21917 "Shuffles operate on vector types!");
21918 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21919 "Can only combine shuffles of the same vector register size.");
21921 if (!isTargetShuffle(Op.getOpcode()))
21923 SmallVector<int, 16> OpMask;
21925 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21926 // We only can combine unary shuffles which we can decode the mask for.
21927 if (!HaveMask || !IsUnary)
21930 assert(VT.getVectorNumElements() == OpMask.size() &&
21931 "Different mask size from vector size!");
21932 assert(((RootMask.size() > OpMask.size() &&
21933 RootMask.size() % OpMask.size() == 0) ||
21934 (OpMask.size() > RootMask.size() &&
21935 OpMask.size() % RootMask.size() == 0) ||
21936 OpMask.size() == RootMask.size()) &&
21937 "The smaller number of elements must divide the larger.");
21938 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21939 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21940 assert(((RootRatio == 1 && OpRatio == 1) ||
21941 (RootRatio == 1) != (OpRatio == 1)) &&
21942 "Must not have a ratio for both incoming and op masks!");
21944 SmallVector<int, 16> Mask;
21945 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21947 // Merge this shuffle operation's mask into our accumulated mask. Note that
21948 // this shuffle's mask will be the first applied to the input, followed by the
21949 // root mask to get us all the way to the root value arrangement. The reason
21950 // for this order is that we are recursing up the operation chain.
21951 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21952 int RootIdx = i / RootRatio;
21953 if (RootMask[RootIdx] < 0) {
21954 // This is a zero or undef lane, we're done.
21955 Mask.push_back(RootMask[RootIdx]);
21959 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21960 int OpIdx = RootMaskedIdx / OpRatio;
21961 if (OpMask[OpIdx] < 0) {
21962 // The incoming lanes are zero or undef, it doesn't matter which ones we
21964 Mask.push_back(OpMask[OpIdx]);
21968 // Ok, we have non-zero lanes, map them through.
21969 Mask.push_back(OpMask[OpIdx] * OpRatio +
21970 RootMaskedIdx % OpRatio);
21973 // See if we can recurse into the operand to combine more things.
21974 switch (Op.getOpcode()) {
21975 case X86ISD::PSHUFB:
21977 case X86ISD::PSHUFD:
21978 case X86ISD::PSHUFHW:
21979 case X86ISD::PSHUFLW:
21980 if (Op.getOperand(0).hasOneUse() &&
21981 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21982 HasPSHUFB, DAG, DCI, Subtarget))
21986 case X86ISD::UNPCKL:
21987 case X86ISD::UNPCKH:
21988 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21989 // We can't check for single use, we have to check that this shuffle is the only user.
21990 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21991 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21992 HasPSHUFB, DAG, DCI, Subtarget))
21997 // Minor canonicalization of the accumulated shuffle mask to make it easier
21998 // to match below. All this does is detect masks with squential pairs of
21999 // elements, and shrink them to the half-width mask. It does this in a loop
22000 // so it will reduce the size of the mask to the minimal width mask which
22001 // performs an equivalent shuffle.
22002 SmallVector<int, 16> WidenedMask;
22003 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22004 Mask = std::move(WidenedMask);
22005 WidenedMask.clear();
22008 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22012 /// \brief Get the PSHUF-style mask from PSHUF node.
22014 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22015 /// PSHUF-style masks that can be reused with such instructions.
22016 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22017 MVT VT = N.getSimpleValueType();
22018 SmallVector<int, 4> Mask;
22020 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22024 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22025 // matter. Check that the upper masks are repeats and remove them.
22026 if (VT.getSizeInBits() > 128) {
22027 int LaneElts = 128 / VT.getScalarSizeInBits();
22029 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22030 for (int j = 0; j < LaneElts; ++j)
22031 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22032 "Mask doesn't repeat in high 128-bit lanes!");
22034 Mask.resize(LaneElts);
22037 switch (N.getOpcode()) {
22038 case X86ISD::PSHUFD:
22040 case X86ISD::PSHUFLW:
22043 case X86ISD::PSHUFHW:
22044 Mask.erase(Mask.begin(), Mask.begin() + 4);
22045 for (int &M : Mask)
22049 llvm_unreachable("No valid shuffle instruction found!");
22053 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22055 /// We walk up the chain and look for a combinable shuffle, skipping over
22056 /// shuffles that we could hoist this shuffle's transformation past without
22057 /// altering anything.
22059 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22061 TargetLowering::DAGCombinerInfo &DCI) {
22062 assert(N.getOpcode() == X86ISD::PSHUFD &&
22063 "Called with something other than an x86 128-bit half shuffle!");
22066 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22067 // of the shuffles in the chain so that we can form a fresh chain to replace
22069 SmallVector<SDValue, 8> Chain;
22070 SDValue V = N.getOperand(0);
22071 for (; V.hasOneUse(); V = V.getOperand(0)) {
22072 switch (V.getOpcode()) {
22074 return SDValue(); // Nothing combined!
22077 // Skip bitcasts as we always know the type for the target specific
22081 case X86ISD::PSHUFD:
22082 // Found another dword shuffle.
22085 case X86ISD::PSHUFLW:
22086 // Check that the low words (being shuffled) are the identity in the
22087 // dword shuffle, and the high words are self-contained.
22088 if (Mask[0] != 0 || Mask[1] != 1 ||
22089 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22092 Chain.push_back(V);
22095 case X86ISD::PSHUFHW:
22096 // Check that the high words (being shuffled) are the identity in the
22097 // dword shuffle, and the low words are self-contained.
22098 if (Mask[2] != 2 || Mask[3] != 3 ||
22099 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22102 Chain.push_back(V);
22105 case X86ISD::UNPCKL:
22106 case X86ISD::UNPCKH:
22107 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22108 // shuffle into a preceding word shuffle.
22109 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
22110 V.getSimpleValueType().getScalarType() != MVT::i16)
22113 // Search for a half-shuffle which we can combine with.
22114 unsigned CombineOp =
22115 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22116 if (V.getOperand(0) != V.getOperand(1) ||
22117 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22119 Chain.push_back(V);
22120 V = V.getOperand(0);
22122 switch (V.getOpcode()) {
22124 return SDValue(); // Nothing to combine.
22126 case X86ISD::PSHUFLW:
22127 case X86ISD::PSHUFHW:
22128 if (V.getOpcode() == CombineOp)
22131 Chain.push_back(V);
22135 V = V.getOperand(0);
22139 } while (V.hasOneUse());
22142 // Break out of the loop if we break out of the switch.
22146 if (!V.hasOneUse())
22147 // We fell out of the loop without finding a viable combining instruction.
22150 // Merge this node's mask and our incoming mask.
22151 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22152 for (int &M : Mask)
22154 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22155 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22157 // Rebuild the chain around this new shuffle.
22158 while (!Chain.empty()) {
22159 SDValue W = Chain.pop_back_val();
22161 if (V.getValueType() != W.getOperand(0).getValueType())
22162 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22164 switch (W.getOpcode()) {
22166 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22168 case X86ISD::UNPCKL:
22169 case X86ISD::UNPCKH:
22170 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22173 case X86ISD::PSHUFD:
22174 case X86ISD::PSHUFLW:
22175 case X86ISD::PSHUFHW:
22176 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22180 if (V.getValueType() != N.getValueType())
22181 V = DAG.getBitcast(N.getValueType(), V);
22183 // Return the new chain to replace N.
22187 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22189 /// We walk up the chain, skipping shuffles of the other half and looking
22190 /// through shuffles which switch halves trying to find a shuffle of the same
22191 /// pair of dwords.
22192 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22194 TargetLowering::DAGCombinerInfo &DCI) {
22196 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22197 "Called with something other than an x86 128-bit half shuffle!");
22199 unsigned CombineOpcode = N.getOpcode();
22201 // Walk up a single-use chain looking for a combinable shuffle.
22202 SDValue V = N.getOperand(0);
22203 for (; V.hasOneUse(); V = V.getOperand(0)) {
22204 switch (V.getOpcode()) {
22206 return false; // Nothing combined!
22209 // Skip bitcasts as we always know the type for the target specific
22213 case X86ISD::PSHUFLW:
22214 case X86ISD::PSHUFHW:
22215 if (V.getOpcode() == CombineOpcode)
22218 // Other-half shuffles are no-ops.
22221 // Break out of the loop if we break out of the switch.
22225 if (!V.hasOneUse())
22226 // We fell out of the loop without finding a viable combining instruction.
22229 // Combine away the bottom node as its shuffle will be accumulated into
22230 // a preceding shuffle.
22231 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22233 // Record the old value.
22236 // Merge this node's mask and our incoming mask (adjusted to account for all
22237 // the pshufd instructions encountered).
22238 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22239 for (int &M : Mask)
22241 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22242 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22244 // Check that the shuffles didn't cancel each other out. If not, we need to
22245 // combine to the new one.
22247 // Replace the combinable shuffle with the combined one, updating all users
22248 // so that we re-evaluate the chain here.
22249 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22254 /// \brief Try to combine x86 target specific shuffles.
22255 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22256 TargetLowering::DAGCombinerInfo &DCI,
22257 const X86Subtarget *Subtarget) {
22259 MVT VT = N.getSimpleValueType();
22260 SmallVector<int, 4> Mask;
22262 switch (N.getOpcode()) {
22263 case X86ISD::PSHUFD:
22264 case X86ISD::PSHUFLW:
22265 case X86ISD::PSHUFHW:
22266 Mask = getPSHUFShuffleMask(N);
22267 assert(Mask.size() == 4);
22273 // Nuke no-op shuffles that show up after combining.
22274 if (isNoopShuffleMask(Mask))
22275 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22277 // Look for simplifications involving one or two shuffle instructions.
22278 SDValue V = N.getOperand(0);
22279 switch (N.getOpcode()) {
22282 case X86ISD::PSHUFLW:
22283 case X86ISD::PSHUFHW:
22284 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
22286 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22287 return SDValue(); // We combined away this shuffle, so we're done.
22289 // See if this reduces to a PSHUFD which is no more expensive and can
22290 // combine with more operations. Note that it has to at least flip the
22291 // dwords as otherwise it would have been removed as a no-op.
22292 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
22293 int DMask[] = {0, 1, 2, 3};
22294 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22295 DMask[DOffset + 0] = DOffset + 1;
22296 DMask[DOffset + 1] = DOffset + 0;
22297 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
22298 V = DAG.getBitcast(DVT, V);
22299 DCI.AddToWorklist(V.getNode());
22300 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
22301 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
22302 DCI.AddToWorklist(V.getNode());
22303 return DAG.getBitcast(VT, V);
22306 // Look for shuffle patterns which can be implemented as a single unpack.
22307 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22308 // only works when we have a PSHUFD followed by two half-shuffles.
22309 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22310 (V.getOpcode() == X86ISD::PSHUFLW ||
22311 V.getOpcode() == X86ISD::PSHUFHW) &&
22312 V.getOpcode() != N.getOpcode() &&
22314 SDValue D = V.getOperand(0);
22315 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22316 D = D.getOperand(0);
22317 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22318 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22319 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22320 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22321 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22323 for (int i = 0; i < 4; ++i) {
22324 WordMask[i + NOffset] = Mask[i] + NOffset;
22325 WordMask[i + VOffset] = VMask[i] + VOffset;
22327 // Map the word mask through the DWord mask.
22329 for (int i = 0; i < 8; ++i)
22330 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22331 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22332 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
22333 // We can replace all three shuffles with an unpack.
22334 V = DAG.getBitcast(VT, D.getOperand(0));
22335 DCI.AddToWorklist(V.getNode());
22336 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22345 case X86ISD::PSHUFD:
22346 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22355 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22357 /// We combine this directly on the abstract vector shuffle nodes so it is
22358 /// easier to generically match. We also insert dummy vector shuffle nodes for
22359 /// the operands which explicitly discard the lanes which are unused by this
22360 /// operation to try to flow through the rest of the combiner the fact that
22361 /// they're unused.
22362 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22364 EVT VT = N->getValueType(0);
22366 // We only handle target-independent shuffles.
22367 // FIXME: It would be easy and harmless to use the target shuffle mask
22368 // extraction tool to support more.
22369 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22372 auto *SVN = cast<ShuffleVectorSDNode>(N);
22373 ArrayRef<int> Mask = SVN->getMask();
22374 SDValue V1 = N->getOperand(0);
22375 SDValue V2 = N->getOperand(1);
22377 // We require the first shuffle operand to be the SUB node, and the second to
22378 // be the ADD node.
22379 // FIXME: We should support the commuted patterns.
22380 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22383 // If there are other uses of these operations we can't fold them.
22384 if (!V1->hasOneUse() || !V2->hasOneUse())
22387 // Ensure that both operations have the same operands. Note that we can
22388 // commute the FADD operands.
22389 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22390 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22391 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22394 // We're looking for blends between FADD and FSUB nodes. We insist on these
22395 // nodes being lined up in a specific expected pattern.
22396 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22397 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22398 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22401 // Only specific types are legal at this point, assert so we notice if and
22402 // when these change.
22403 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22404 VT == MVT::v4f64) &&
22405 "Unknown vector type encountered!");
22407 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22410 /// PerformShuffleCombine - Performs several different shuffle combines.
22411 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22412 TargetLowering::DAGCombinerInfo &DCI,
22413 const X86Subtarget *Subtarget) {
22415 SDValue N0 = N->getOperand(0);
22416 SDValue N1 = N->getOperand(1);
22417 EVT VT = N->getValueType(0);
22419 // Don't create instructions with illegal types after legalize types has run.
22420 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22421 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22424 // If we have legalized the vector types, look for blends of FADD and FSUB
22425 // nodes that we can fuse into an ADDSUB node.
22426 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22427 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22430 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22431 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22432 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22433 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22435 // During Type Legalization, when promoting illegal vector types,
22436 // the backend might introduce new shuffle dag nodes and bitcasts.
22438 // This code performs the following transformation:
22439 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22440 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22442 // We do this only if both the bitcast and the BINOP dag nodes have
22443 // one use. Also, perform this transformation only if the new binary
22444 // operation is legal. This is to avoid introducing dag nodes that
22445 // potentially need to be further expanded (or custom lowered) into a
22446 // less optimal sequence of dag nodes.
22447 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22448 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22449 N0.getOpcode() == ISD::BITCAST) {
22450 SDValue BC0 = N0.getOperand(0);
22451 EVT SVT = BC0.getValueType();
22452 unsigned Opcode = BC0.getOpcode();
22453 unsigned NumElts = VT.getVectorNumElements();
22455 if (BC0.hasOneUse() && SVT.isVector() &&
22456 SVT.getVectorNumElements() * 2 == NumElts &&
22457 TLI.isOperationLegal(Opcode, VT)) {
22458 bool CanFold = false;
22470 unsigned SVTNumElts = SVT.getVectorNumElements();
22471 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22472 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22473 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22474 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22475 CanFold = SVOp->getMaskElt(i) < 0;
22478 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
22479 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
22480 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22481 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22486 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22487 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22488 // consecutive, non-overlapping, and in the right order.
22489 SmallVector<SDValue, 16> Elts;
22490 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22491 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22493 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
22496 if (isTargetShuffle(N->getOpcode())) {
22498 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22499 if (Shuffle.getNode())
22502 // Try recursively combining arbitrary sequences of x86 shuffle
22503 // instructions into higher-order shuffles. We do this after combining
22504 // specific PSHUF instruction sequences into their minimal form so that we
22505 // can evaluate how many specialized shuffle instructions are involved in
22506 // a particular chain.
22507 SmallVector<int, 1> NonceMask; // Just a placeholder.
22508 NonceMask.push_back(0);
22509 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22510 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22512 return SDValue(); // This routine will use CombineTo to replace N.
22518 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22519 /// specific shuffle of a load can be folded into a single element load.
22520 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22521 /// shuffles have been custom lowered so we need to handle those here.
22522 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22523 TargetLowering::DAGCombinerInfo &DCI) {
22524 if (DCI.isBeforeLegalizeOps())
22527 SDValue InVec = N->getOperand(0);
22528 SDValue EltNo = N->getOperand(1);
22530 if (!isa<ConstantSDNode>(EltNo))
22533 EVT OriginalVT = InVec.getValueType();
22535 if (InVec.getOpcode() == ISD::BITCAST) {
22536 // Don't duplicate a load with other uses.
22537 if (!InVec.hasOneUse())
22539 EVT BCVT = InVec.getOperand(0).getValueType();
22540 if (!BCVT.isVector() ||
22541 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22543 InVec = InVec.getOperand(0);
22546 EVT CurrentVT = InVec.getValueType();
22548 if (!isTargetShuffle(InVec.getOpcode()))
22551 // Don't duplicate a load with other uses.
22552 if (!InVec.hasOneUse())
22555 SmallVector<int, 16> ShuffleMask;
22557 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22558 ShuffleMask, UnaryShuffle))
22561 // Select the input vector, guarding against out of range extract vector.
22562 unsigned NumElems = CurrentVT.getVectorNumElements();
22563 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22564 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22565 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22566 : InVec.getOperand(1);
22568 // If inputs to shuffle are the same for both ops, then allow 2 uses
22569 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
22570 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22572 if (LdNode.getOpcode() == ISD::BITCAST) {
22573 // Don't duplicate a load with other uses.
22574 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22577 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22578 LdNode = LdNode.getOperand(0);
22581 if (!ISD::isNormalLoad(LdNode.getNode()))
22584 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22586 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22589 EVT EltVT = N->getValueType(0);
22590 // If there's a bitcast before the shuffle, check if the load type and
22591 // alignment is valid.
22592 unsigned Align = LN0->getAlignment();
22593 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22594 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
22595 EltVT.getTypeForEVT(*DAG.getContext()));
22597 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22600 // All checks match so transform back to vector_shuffle so that DAG combiner
22601 // can finish the job
22604 // Create shuffle node taking into account the case that its a unary shuffle
22605 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22606 : InVec.getOperand(1);
22607 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22608 InVec.getOperand(0), Shuffle,
22610 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
22611 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22615 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
22616 /// special and don't usually play with other vector types, it's better to
22617 /// handle them early to be sure we emit efficient code by avoiding
22618 /// store-load conversions.
22619 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
22620 if (N->getValueType(0) != MVT::x86mmx ||
22621 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
22622 N->getOperand(0)->getValueType(0) != MVT::v2i32)
22625 SDValue V = N->getOperand(0);
22626 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
22627 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
22628 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
22629 N->getValueType(0), V.getOperand(0));
22634 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22635 /// generation and convert it from being a bunch of shuffles and extracts
22636 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22637 /// storing the value and loading scalars back, while for x64 we should
22638 /// use 64-bit extracts and shifts.
22639 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22640 TargetLowering::DAGCombinerInfo &DCI) {
22641 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
22644 SDValue InputVector = N->getOperand(0);
22645 SDLoc dl(InputVector);
22646 // Detect mmx to i32 conversion through a v2i32 elt extract.
22647 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
22648 N->getValueType(0) == MVT::i32 &&
22649 InputVector.getValueType() == MVT::v2i32) {
22651 // The bitcast source is a direct mmx result.
22652 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
22653 if (MMXSrc.getValueType() == MVT::x86mmx)
22654 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22655 N->getValueType(0),
22656 InputVector.getNode()->getOperand(0));
22658 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
22659 SDValue MMXSrcOp = MMXSrc.getOperand(0);
22660 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
22661 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
22662 MMXSrcOp.getOpcode() == ISD::BITCAST &&
22663 MMXSrcOp.getValueType() == MVT::v1i64 &&
22664 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
22665 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22666 N->getValueType(0),
22667 MMXSrcOp.getOperand(0));
22670 EVT VT = N->getValueType(0);
22672 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
22673 InputVector.getOpcode() == ISD::BITCAST &&
22674 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
22675 uint64_t ExtractedElt =
22676 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
22677 uint64_t InputValue =
22678 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
22679 uint64_t Res = (InputValue >> ExtractedElt) & 1;
22680 return DAG.getConstant(Res, dl, MVT::i1);
22682 // Only operate on vectors of 4 elements, where the alternative shuffling
22683 // gets to be more expensive.
22684 if (InputVector.getValueType() != MVT::v4i32)
22687 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22688 // single use which is a sign-extend or zero-extend, and all elements are
22690 SmallVector<SDNode *, 4> Uses;
22691 unsigned ExtractedElements = 0;
22692 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22693 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22694 if (UI.getUse().getResNo() != InputVector.getResNo())
22697 SDNode *Extract = *UI;
22698 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22701 if (Extract->getValueType(0) != MVT::i32)
22703 if (!Extract->hasOneUse())
22705 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22706 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22708 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22711 // Record which element was extracted.
22712 ExtractedElements |=
22713 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22715 Uses.push_back(Extract);
22718 // If not all the elements were used, this may not be worthwhile.
22719 if (ExtractedElements != 15)
22722 // Ok, we've now decided to do the transformation.
22723 // If 64-bit shifts are legal, use the extract-shift sequence,
22724 // otherwise bounce the vector off the cache.
22725 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22728 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22729 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
22730 auto &DL = DAG.getDataLayout();
22731 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
22732 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22733 DAG.getConstant(0, dl, VecIdxTy));
22734 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22735 DAG.getConstant(1, dl, VecIdxTy));
22737 SDValue ShAmt = DAG.getConstant(
22738 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
22739 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22740 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22741 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22742 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22743 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22744 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22746 // Store the value to a temporary stack slot.
22747 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22748 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22749 MachinePointerInfo(), false, false, 0);
22751 EVT ElementType = InputVector.getValueType().getVectorElementType();
22752 unsigned EltSize = ElementType.getSizeInBits() / 8;
22754 // Replace each use (extract) with a load of the appropriate element.
22755 for (unsigned i = 0; i < 4; ++i) {
22756 uint64_t Offset = EltSize * i;
22757 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
22758 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
22760 SDValue ScalarAddr =
22761 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
22763 // Load the scalar.
22764 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22765 ScalarAddr, MachinePointerInfo(),
22766 false, false, false, 0);
22771 // Replace the extracts
22772 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22773 UE = Uses.end(); UI != UE; ++UI) {
22774 SDNode *Extract = *UI;
22776 SDValue Idx = Extract->getOperand(1);
22777 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22778 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22781 // The replacement was made in place; don't return anything.
22786 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22787 const X86Subtarget *Subtarget) {
22789 SDValue Cond = N->getOperand(0);
22790 SDValue LHS = N->getOperand(1);
22791 SDValue RHS = N->getOperand(2);
22793 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22794 SDValue CondSrc = Cond->getOperand(0);
22795 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22796 Cond = CondSrc->getOperand(0);
22799 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22802 // A vselect where all conditions and data are constants can be optimized into
22803 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22804 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22805 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22808 unsigned MaskValue = 0;
22809 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22812 MVT VT = N->getSimpleValueType(0);
22813 unsigned NumElems = VT.getVectorNumElements();
22814 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22815 for (unsigned i = 0; i < NumElems; ++i) {
22816 // Be sure we emit undef where we can.
22817 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22818 ShuffleMask[i] = -1;
22820 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22823 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22824 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22826 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22829 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22831 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22832 TargetLowering::DAGCombinerInfo &DCI,
22833 const X86Subtarget *Subtarget) {
22835 SDValue Cond = N->getOperand(0);
22836 // Get the LHS/RHS of the select.
22837 SDValue LHS = N->getOperand(1);
22838 SDValue RHS = N->getOperand(2);
22839 EVT VT = LHS.getValueType();
22840 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22842 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22843 // instructions match the semantics of the common C idiom x<y?x:y but not
22844 // x<=y?x:y, because of how they handle negative zero (which can be
22845 // ignored in unsafe-math mode).
22846 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
22847 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22848 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
22849 (Subtarget->hasSSE2() ||
22850 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22851 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22853 unsigned Opcode = 0;
22854 // Check for x CC y ? x : y.
22855 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22856 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22860 // Converting this to a min would handle NaNs incorrectly, and swapping
22861 // the operands would cause it to handle comparisons between positive
22862 // and negative zero incorrectly.
22863 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22864 if (!DAG.getTarget().Options.UnsafeFPMath &&
22865 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22867 std::swap(LHS, RHS);
22869 Opcode = X86ISD::FMIN;
22872 // Converting this to a min would handle comparisons between positive
22873 // and negative zero incorrectly.
22874 if (!DAG.getTarget().Options.UnsafeFPMath &&
22875 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22877 Opcode = X86ISD::FMIN;
22880 // Converting this to a min would handle both negative zeros and NaNs
22881 // incorrectly, but we can swap the operands to fix both.
22882 std::swap(LHS, RHS);
22886 Opcode = X86ISD::FMIN;
22890 // Converting this to a max would handle comparisons between positive
22891 // and negative zero incorrectly.
22892 if (!DAG.getTarget().Options.UnsafeFPMath &&
22893 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22895 Opcode = X86ISD::FMAX;
22898 // Converting this to a max would handle NaNs incorrectly, and swapping
22899 // the operands would cause it to handle comparisons between positive
22900 // and negative zero incorrectly.
22901 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22902 if (!DAG.getTarget().Options.UnsafeFPMath &&
22903 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22905 std::swap(LHS, RHS);
22907 Opcode = X86ISD::FMAX;
22910 // Converting this to a max would handle both negative zeros and NaNs
22911 // incorrectly, but we can swap the operands to fix both.
22912 std::swap(LHS, RHS);
22916 Opcode = X86ISD::FMAX;
22919 // Check for x CC y ? y : x -- a min/max with reversed arms.
22920 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22921 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22925 // Converting this to a min would handle comparisons between positive
22926 // and negative zero incorrectly, and swapping the operands would
22927 // cause it to handle NaNs incorrectly.
22928 if (!DAG.getTarget().Options.UnsafeFPMath &&
22929 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22930 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22932 std::swap(LHS, RHS);
22934 Opcode = X86ISD::FMIN;
22937 // Converting this to a min would handle NaNs incorrectly.
22938 if (!DAG.getTarget().Options.UnsafeFPMath &&
22939 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22941 Opcode = X86ISD::FMIN;
22944 // Converting this to a min would handle both negative zeros and NaNs
22945 // incorrectly, but we can swap the operands to fix both.
22946 std::swap(LHS, RHS);
22950 Opcode = X86ISD::FMIN;
22954 // Converting this to a max would handle NaNs incorrectly.
22955 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22957 Opcode = X86ISD::FMAX;
22960 // Converting this to a max would handle comparisons between positive
22961 // and negative zero incorrectly, and swapping the operands would
22962 // cause it to handle NaNs incorrectly.
22963 if (!DAG.getTarget().Options.UnsafeFPMath &&
22964 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22965 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22967 std::swap(LHS, RHS);
22969 Opcode = X86ISD::FMAX;
22972 // Converting this to a max would handle both negative zeros and NaNs
22973 // incorrectly, but we can swap the operands to fix both.
22974 std::swap(LHS, RHS);
22978 Opcode = X86ISD::FMAX;
22984 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22987 EVT CondVT = Cond.getValueType();
22988 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22989 CondVT.getVectorElementType() == MVT::i1) {
22990 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22991 // lowering on KNL. In this case we convert it to
22992 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22993 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22994 // Since SKX these selects have a proper lowering.
22995 EVT OpVT = LHS.getValueType();
22996 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22997 (OpVT.getVectorElementType() == MVT::i8 ||
22998 OpVT.getVectorElementType() == MVT::i16) &&
22999 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23000 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23001 DCI.AddToWorklist(Cond.getNode());
23002 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23005 // If this is a select between two integer constants, try to do some
23007 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23008 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23009 // Don't do this for crazy integer types.
23010 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23011 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23012 // so that TrueC (the true value) is larger than FalseC.
23013 bool NeedsCondInvert = false;
23015 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23016 // Efficiently invertible.
23017 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23018 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23019 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23020 NeedsCondInvert = true;
23021 std::swap(TrueC, FalseC);
23024 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23025 if (FalseC->getAPIntValue() == 0 &&
23026 TrueC->getAPIntValue().isPowerOf2()) {
23027 if (NeedsCondInvert) // Invert the condition if needed.
23028 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23029 DAG.getConstant(1, DL, Cond.getValueType()));
23031 // Zero extend the condition if needed.
23032 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23034 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23035 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23036 DAG.getConstant(ShAmt, DL, MVT::i8));
23039 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23040 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23041 if (NeedsCondInvert) // Invert the condition if needed.
23042 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23043 DAG.getConstant(1, DL, Cond.getValueType()));
23045 // Zero extend the condition if needed.
23046 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23047 FalseC->getValueType(0), Cond);
23048 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23049 SDValue(FalseC, 0));
23052 // Optimize cases that will turn into an LEA instruction. This requires
23053 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23054 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23055 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23056 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23058 bool isFastMultiplier = false;
23060 switch ((unsigned char)Diff) {
23062 case 1: // result = add base, cond
23063 case 2: // result = lea base( , cond*2)
23064 case 3: // result = lea base(cond, cond*2)
23065 case 4: // result = lea base( , cond*4)
23066 case 5: // result = lea base(cond, cond*4)
23067 case 8: // result = lea base( , cond*8)
23068 case 9: // result = lea base(cond, cond*8)
23069 isFastMultiplier = true;
23074 if (isFastMultiplier) {
23075 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23076 if (NeedsCondInvert) // Invert the condition if needed.
23077 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23078 DAG.getConstant(1, DL, Cond.getValueType()));
23080 // Zero extend the condition if needed.
23081 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23083 // Scale the condition by the difference.
23085 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23086 DAG.getConstant(Diff, DL,
23087 Cond.getValueType()));
23089 // Add the base if non-zero.
23090 if (FalseC->getAPIntValue() != 0)
23091 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23092 SDValue(FalseC, 0));
23099 // Canonicalize max and min:
23100 // (x > y) ? x : y -> (x >= y) ? x : y
23101 // (x < y) ? x : y -> (x <= y) ? x : y
23102 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23103 // the need for an extra compare
23104 // against zero. e.g.
23105 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23107 // testl %edi, %edi
23109 // cmovgl %edi, %eax
23113 // cmovsl %eax, %edi
23114 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23115 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23116 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23117 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23122 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23123 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23124 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23125 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23130 // Early exit check
23131 if (!TLI.isTypeLegal(VT))
23134 // Match VSELECTs into subs with unsigned saturation.
23135 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23136 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23137 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23138 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23139 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23141 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23142 // left side invert the predicate to simplify logic below.
23144 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23146 CC = ISD::getSetCCInverse(CC, true);
23147 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23151 if (Other.getNode() && Other->getNumOperands() == 2 &&
23152 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23153 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23154 SDValue CondRHS = Cond->getOperand(1);
23156 // Look for a general sub with unsigned saturation first.
23157 // x >= y ? x-y : 0 --> subus x, y
23158 // x > y ? x-y : 0 --> subus x, y
23159 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23160 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23161 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23163 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23164 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23165 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23166 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23167 // If the RHS is a constant we have to reverse the const
23168 // canonicalization.
23169 // x > C-1 ? x+-C : 0 --> subus x, C
23170 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23171 CondRHSConst->getAPIntValue() ==
23172 (-OpRHSConst->getAPIntValue() - 1))
23173 return DAG.getNode(
23174 X86ISD::SUBUS, DL, VT, OpLHS,
23175 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23177 // Another special case: If C was a sign bit, the sub has been
23178 // canonicalized into a xor.
23179 // FIXME: Would it be better to use computeKnownBits to determine
23180 // whether it's safe to decanonicalize the xor?
23181 // x s< 0 ? x^C : 0 --> subus x, C
23182 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23183 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23184 OpRHSConst->getAPIntValue().isSignBit())
23185 // Note that we have to rebuild the RHS constant here to ensure we
23186 // don't rely on particular values of undef lanes.
23187 return DAG.getNode(
23188 X86ISD::SUBUS, DL, VT, OpLHS,
23189 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23194 // Simplify vector selection if condition value type matches vselect
23196 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23197 assert(Cond.getValueType().isVector() &&
23198 "vector select expects a vector selector!");
23200 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23201 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23203 // Try invert the condition if true value is not all 1s and false value
23205 if (!TValIsAllOnes && !FValIsAllZeros &&
23206 // Check if the selector will be produced by CMPP*/PCMP*
23207 Cond.getOpcode() == ISD::SETCC &&
23208 // Check if SETCC has already been promoted
23209 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23211 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23212 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23214 if (TValIsAllZeros || FValIsAllOnes) {
23215 SDValue CC = Cond.getOperand(2);
23216 ISD::CondCode NewCC =
23217 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23218 Cond.getOperand(0).getValueType().isInteger());
23219 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23220 std::swap(LHS, RHS);
23221 TValIsAllOnes = FValIsAllOnes;
23222 FValIsAllZeros = TValIsAllZeros;
23226 if (TValIsAllOnes || FValIsAllZeros) {
23229 if (TValIsAllOnes && FValIsAllZeros)
23231 else if (TValIsAllOnes)
23233 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
23234 else if (FValIsAllZeros)
23235 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23236 DAG.getBitcast(CondVT, LHS));
23238 return DAG.getBitcast(VT, Ret);
23242 // We should generate an X86ISD::BLENDI from a vselect if its argument
23243 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23244 // constants. This specific pattern gets generated when we split a
23245 // selector for a 512 bit vector in a machine without AVX512 (but with
23246 // 256-bit vectors), during legalization:
23248 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23250 // Iff we find this pattern and the build_vectors are built from
23251 // constants, we translate the vselect into a shuffle_vector that we
23252 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23253 if ((N->getOpcode() == ISD::VSELECT ||
23254 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23255 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
23256 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23257 if (Shuffle.getNode())
23261 // If this is a *dynamic* select (non-constant condition) and we can match
23262 // this node with one of the variable blend instructions, restructure the
23263 // condition so that the blends can use the high bit of each element and use
23264 // SimplifyDemandedBits to simplify the condition operand.
23265 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23266 !DCI.isBeforeLegalize() &&
23267 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23268 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23270 // Don't optimize vector selects that map to mask-registers.
23274 // We can only handle the cases where VSELECT is directly legal on the
23275 // subtarget. We custom lower VSELECT nodes with constant conditions and
23276 // this makes it hard to see whether a dynamic VSELECT will correctly
23277 // lower, so we both check the operation's status and explicitly handle the
23278 // cases where a *dynamic* blend will fail even though a constant-condition
23279 // blend could be custom lowered.
23280 // FIXME: We should find a better way to handle this class of problems.
23281 // Potentially, we should combine constant-condition vselect nodes
23282 // pre-legalization into shuffles and not mark as many types as custom
23284 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
23286 // FIXME: We don't support i16-element blends currently. We could and
23287 // should support them by making *all* the bits in the condition be set
23288 // rather than just the high bit and using an i8-element blend.
23289 if (VT.getScalarType() == MVT::i16)
23291 // Dynamic blending was only available from SSE4.1 onward.
23292 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
23294 // Byte blends are only available in AVX2
23295 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
23296 !Subtarget->hasAVX2())
23299 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23300 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23302 APInt KnownZero, KnownOne;
23303 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23304 DCI.isBeforeLegalizeOps());
23305 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23306 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23308 // If we changed the computation somewhere in the DAG, this change
23309 // will affect all users of Cond.
23310 // Make sure it is fine and update all the nodes so that we do not
23311 // use the generic VSELECT anymore. Otherwise, we may perform
23312 // wrong optimizations as we messed up with the actual expectation
23313 // for the vector boolean values.
23314 if (Cond != TLO.Old) {
23315 // Check all uses of that condition operand to check whether it will be
23316 // consumed by non-BLEND instructions, which may depend on all bits are
23318 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23320 if (I->getOpcode() != ISD::VSELECT)
23321 // TODO: Add other opcodes eventually lowered into BLEND.
23324 // Update all the users of the condition, before committing the change,
23325 // so that the VSELECT optimizations that expect the correct vector
23326 // boolean value will not be triggered.
23327 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23329 DAG.ReplaceAllUsesOfValueWith(
23331 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23332 Cond, I->getOperand(1), I->getOperand(2)));
23333 DCI.CommitTargetLoweringOpt(TLO);
23336 // At this point, only Cond is changed. Change the condition
23337 // just for N to keep the opportunity to optimize all other
23338 // users their own way.
23339 DAG.ReplaceAllUsesOfValueWith(
23341 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23342 TLO.New, N->getOperand(1), N->getOperand(2)));
23350 // Check whether a boolean test is testing a boolean value generated by
23351 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23354 // Simplify the following patterns:
23355 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23356 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23357 // to (Op EFLAGS Cond)
23359 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23360 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23361 // to (Op EFLAGS !Cond)
23363 // where Op could be BRCOND or CMOV.
23365 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23366 // Quit if not CMP and SUB with its value result used.
23367 if (Cmp.getOpcode() != X86ISD::CMP &&
23368 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23371 // Quit if not used as a boolean value.
23372 if (CC != X86::COND_E && CC != X86::COND_NE)
23375 // Check CMP operands. One of them should be 0 or 1 and the other should be
23376 // an SetCC or extended from it.
23377 SDValue Op1 = Cmp.getOperand(0);
23378 SDValue Op2 = Cmp.getOperand(1);
23381 const ConstantSDNode* C = nullptr;
23382 bool needOppositeCond = (CC == X86::COND_E);
23383 bool checkAgainstTrue = false; // Is it a comparison against 1?
23385 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23387 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23389 else // Quit if all operands are not constants.
23392 if (C->getZExtValue() == 1) {
23393 needOppositeCond = !needOppositeCond;
23394 checkAgainstTrue = true;
23395 } else if (C->getZExtValue() != 0)
23396 // Quit if the constant is neither 0 or 1.
23399 bool truncatedToBoolWithAnd = false;
23400 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23401 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23402 SetCC.getOpcode() == ISD::TRUNCATE ||
23403 SetCC.getOpcode() == ISD::AND) {
23404 if (SetCC.getOpcode() == ISD::AND) {
23406 ConstantSDNode *CS;
23407 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23408 CS->getZExtValue() == 1)
23410 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23411 CS->getZExtValue() == 1)
23415 SetCC = SetCC.getOperand(OpIdx);
23416 truncatedToBoolWithAnd = true;
23418 SetCC = SetCC.getOperand(0);
23421 switch (SetCC.getOpcode()) {
23422 case X86ISD::SETCC_CARRY:
23423 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23424 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23425 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23426 // truncated to i1 using 'and'.
23427 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23429 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23430 "Invalid use of SETCC_CARRY!");
23432 case X86ISD::SETCC:
23433 // Set the condition code or opposite one if necessary.
23434 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23435 if (needOppositeCond)
23436 CC = X86::GetOppositeBranchCondition(CC);
23437 return SetCC.getOperand(1);
23438 case X86ISD::CMOV: {
23439 // Check whether false/true value has canonical one, i.e. 0 or 1.
23440 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23441 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23442 // Quit if true value is not a constant.
23445 // Quit if false value is not a constant.
23447 SDValue Op = SetCC.getOperand(0);
23448 // Skip 'zext' or 'trunc' node.
23449 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23450 Op.getOpcode() == ISD::TRUNCATE)
23451 Op = Op.getOperand(0);
23452 // A special case for rdrand/rdseed, where 0 is set if false cond is
23454 if ((Op.getOpcode() != X86ISD::RDRAND &&
23455 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23458 // Quit if false value is not the constant 0 or 1.
23459 bool FValIsFalse = true;
23460 if (FVal && FVal->getZExtValue() != 0) {
23461 if (FVal->getZExtValue() != 1)
23463 // If FVal is 1, opposite cond is needed.
23464 needOppositeCond = !needOppositeCond;
23465 FValIsFalse = false;
23467 // Quit if TVal is not the constant opposite of FVal.
23468 if (FValIsFalse && TVal->getZExtValue() != 1)
23470 if (!FValIsFalse && TVal->getZExtValue() != 0)
23472 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23473 if (needOppositeCond)
23474 CC = X86::GetOppositeBranchCondition(CC);
23475 return SetCC.getOperand(3);
23482 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
23484 /// (X86or (X86setcc) (X86setcc))
23485 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
23486 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
23487 X86::CondCode &CC1, SDValue &Flags,
23489 if (Cond->getOpcode() == X86ISD::CMP) {
23490 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
23491 if (!CondOp1C || !CondOp1C->isNullValue())
23494 Cond = Cond->getOperand(0);
23499 SDValue SetCC0, SetCC1;
23500 switch (Cond->getOpcode()) {
23501 default: return false;
23508 SetCC0 = Cond->getOperand(0);
23509 SetCC1 = Cond->getOperand(1);
23513 // Make sure we have SETCC nodes, using the same flags value.
23514 if (SetCC0.getOpcode() != X86ISD::SETCC ||
23515 SetCC1.getOpcode() != X86ISD::SETCC ||
23516 SetCC0->getOperand(1) != SetCC1->getOperand(1))
23519 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
23520 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
23521 Flags = SetCC0->getOperand(1);
23525 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23526 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23527 TargetLowering::DAGCombinerInfo &DCI,
23528 const X86Subtarget *Subtarget) {
23531 // If the flag operand isn't dead, don't touch this CMOV.
23532 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23535 SDValue FalseOp = N->getOperand(0);
23536 SDValue TrueOp = N->getOperand(1);
23537 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23538 SDValue Cond = N->getOperand(3);
23540 if (CC == X86::COND_E || CC == X86::COND_NE) {
23541 switch (Cond.getOpcode()) {
23545 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23546 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23547 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23553 Flags = checkBoolTestSetCCCombine(Cond, CC);
23554 if (Flags.getNode() &&
23555 // Extra check as FCMOV only supports a subset of X86 cond.
23556 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23557 SDValue Ops[] = { FalseOp, TrueOp,
23558 DAG.getConstant(CC, DL, MVT::i8), Flags };
23559 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23562 // If this is a select between two integer constants, try to do some
23563 // optimizations. Note that the operands are ordered the opposite of SELECT
23565 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23566 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23567 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23568 // larger than FalseC (the false value).
23569 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23570 CC = X86::GetOppositeBranchCondition(CC);
23571 std::swap(TrueC, FalseC);
23572 std::swap(TrueOp, FalseOp);
23575 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23576 // This is efficient for any integer data type (including i8/i16) and
23578 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23579 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23580 DAG.getConstant(CC, DL, MVT::i8), Cond);
23582 // Zero extend the condition if needed.
23583 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23585 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23586 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23587 DAG.getConstant(ShAmt, DL, MVT::i8));
23588 if (N->getNumValues() == 2) // Dead flag value?
23589 return DCI.CombineTo(N, Cond, SDValue());
23593 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23594 // for any integer data type, including i8/i16.
23595 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23596 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23597 DAG.getConstant(CC, DL, MVT::i8), Cond);
23599 // Zero extend the condition if needed.
23600 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23601 FalseC->getValueType(0), Cond);
23602 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23603 SDValue(FalseC, 0));
23605 if (N->getNumValues() == 2) // Dead flag value?
23606 return DCI.CombineTo(N, Cond, SDValue());
23610 // Optimize cases that will turn into an LEA instruction. This requires
23611 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23612 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23613 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23614 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23616 bool isFastMultiplier = false;
23618 switch ((unsigned char)Diff) {
23620 case 1: // result = add base, cond
23621 case 2: // result = lea base( , cond*2)
23622 case 3: // result = lea base(cond, cond*2)
23623 case 4: // result = lea base( , cond*4)
23624 case 5: // result = lea base(cond, cond*4)
23625 case 8: // result = lea base( , cond*8)
23626 case 9: // result = lea base(cond, cond*8)
23627 isFastMultiplier = true;
23632 if (isFastMultiplier) {
23633 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23634 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23635 DAG.getConstant(CC, DL, MVT::i8), Cond);
23636 // Zero extend the condition if needed.
23637 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23639 // Scale the condition by the difference.
23641 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23642 DAG.getConstant(Diff, DL, Cond.getValueType()));
23644 // Add the base if non-zero.
23645 if (FalseC->getAPIntValue() != 0)
23646 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23647 SDValue(FalseC, 0));
23648 if (N->getNumValues() == 2) // Dead flag value?
23649 return DCI.CombineTo(N, Cond, SDValue());
23656 // Handle these cases:
23657 // (select (x != c), e, c) -> select (x != c), e, x),
23658 // (select (x == c), c, e) -> select (x == c), x, e)
23659 // where the c is an integer constant, and the "select" is the combination
23660 // of CMOV and CMP.
23662 // The rationale for this change is that the conditional-move from a constant
23663 // needs two instructions, however, conditional-move from a register needs
23664 // only one instruction.
23666 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23667 // some instruction-combining opportunities. This opt needs to be
23668 // postponed as late as possible.
23670 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23671 // the DCI.xxxx conditions are provided to postpone the optimization as
23672 // late as possible.
23674 ConstantSDNode *CmpAgainst = nullptr;
23675 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23676 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23677 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23679 if (CC == X86::COND_NE &&
23680 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23681 CC = X86::GetOppositeBranchCondition(CC);
23682 std::swap(TrueOp, FalseOp);
23685 if (CC == X86::COND_E &&
23686 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23687 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23688 DAG.getConstant(CC, DL, MVT::i8), Cond };
23689 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23694 // Fold and/or of setcc's to double CMOV:
23695 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
23696 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
23698 // This combine lets us generate:
23699 // cmovcc1 (jcc1 if we don't have CMOV)
23705 // cmovne (jne if we don't have CMOV)
23706 // When we can't use the CMOV instruction, it might increase branch
23708 // When we can use CMOV, or when there is no mispredict, this improves
23709 // throughput and reduces register pressure.
23711 if (CC == X86::COND_NE) {
23713 X86::CondCode CC0, CC1;
23715 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
23717 std::swap(FalseOp, TrueOp);
23718 CC0 = X86::GetOppositeBranchCondition(CC0);
23719 CC1 = X86::GetOppositeBranchCondition(CC1);
23722 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
23724 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
23725 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
23726 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23727 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
23735 /// PerformMulCombine - Optimize a single multiply with constant into two
23736 /// in order to implement it with two cheaper instructions, e.g.
23737 /// LEA + SHL, LEA + LEA.
23738 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23739 TargetLowering::DAGCombinerInfo &DCI) {
23740 // An imul is usually smaller than the alternative sequence.
23741 if (DAG.getMachineFunction().getFunction()->optForMinSize())
23744 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23747 EVT VT = N->getValueType(0);
23748 if (VT != MVT::i64 && VT != MVT::i32)
23751 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23754 uint64_t MulAmt = C->getZExtValue();
23755 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23758 uint64_t MulAmt1 = 0;
23759 uint64_t MulAmt2 = 0;
23760 if ((MulAmt % 9) == 0) {
23762 MulAmt2 = MulAmt / 9;
23763 } else if ((MulAmt % 5) == 0) {
23765 MulAmt2 = MulAmt / 5;
23766 } else if ((MulAmt % 3) == 0) {
23768 MulAmt2 = MulAmt / 3;
23771 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23774 if (isPowerOf2_64(MulAmt2) &&
23775 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23776 // If second multiplifer is pow2, issue it first. We want the multiply by
23777 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23779 std::swap(MulAmt1, MulAmt2);
23782 if (isPowerOf2_64(MulAmt1))
23783 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23784 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
23786 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23787 DAG.getConstant(MulAmt1, DL, VT));
23789 if (isPowerOf2_64(MulAmt2))
23790 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23791 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
23793 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23794 DAG.getConstant(MulAmt2, DL, VT));
23796 // Do not add new nodes to DAG combiner worklist.
23797 DCI.CombineTo(N, NewMul, false);
23802 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23803 SDValue N0 = N->getOperand(0);
23804 SDValue N1 = N->getOperand(1);
23805 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23806 EVT VT = N0.getValueType();
23808 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23809 // since the result of setcc_c is all zero's or all ones.
23810 if (VT.isInteger() && !VT.isVector() &&
23811 N1C && N0.getOpcode() == ISD::AND &&
23812 N0.getOperand(1).getOpcode() == ISD::Constant) {
23813 SDValue N00 = N0.getOperand(0);
23814 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23815 APInt ShAmt = N1C->getAPIntValue();
23816 Mask = Mask.shl(ShAmt);
23817 bool MaskOK = false;
23818 // We can handle cases concerning bit-widening nodes containing setcc_c if
23819 // we carefully interrogate the mask to make sure we are semantics
23821 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
23822 // of the underlying setcc_c operation if the setcc_c was zero extended.
23823 // Consider the following example:
23824 // zext(setcc_c) -> i32 0x0000FFFF
23825 // c1 -> i32 0x0000FFFF
23826 // c2 -> i32 0x00000001
23827 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
23828 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
23829 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23831 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
23832 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
23834 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
23835 N00.getOpcode() == ISD::ANY_EXTEND) &&
23836 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
23837 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
23839 if (MaskOK && Mask != 0) {
23841 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
23845 // Hardware support for vector shifts is sparse which makes us scalarize the
23846 // vector operations in many cases. Also, on sandybridge ADD is faster than
23848 // (shl V, 1) -> add V,V
23849 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23850 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23851 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23852 // We shift all of the values by one. In many cases we do not have
23853 // hardware support for this operation. This is better expressed as an ADD
23855 if (N1SplatC->getAPIntValue() == 1)
23856 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23862 /// \brief Returns a vector of 0s if the node in input is a vector logical
23863 /// shift by a constant amount which is known to be bigger than or equal
23864 /// to the vector element size in bits.
23865 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23866 const X86Subtarget *Subtarget) {
23867 EVT VT = N->getValueType(0);
23869 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23870 (!Subtarget->hasInt256() ||
23871 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23874 SDValue Amt = N->getOperand(1);
23876 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23877 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23878 APInt ShiftAmt = AmtSplat->getAPIntValue();
23879 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23881 // SSE2/AVX2 logical shifts always return a vector of 0s
23882 // if the shift amount is bigger than or equal to
23883 // the element size. The constant shift amount will be
23884 // encoded as a 8-bit immediate.
23885 if (ShiftAmt.trunc(8).uge(MaxAmount))
23886 return getZeroVector(VT, Subtarget, DAG, DL);
23892 /// PerformShiftCombine - Combine shifts.
23893 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23894 TargetLowering::DAGCombinerInfo &DCI,
23895 const X86Subtarget *Subtarget) {
23896 if (N->getOpcode() == ISD::SHL)
23897 if (SDValue V = PerformSHLCombine(N, DAG))
23900 // Try to fold this logical shift into a zero vector.
23901 if (N->getOpcode() != ISD::SRA)
23902 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
23908 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23909 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23910 // and friends. Likewise for OR -> CMPNEQSS.
23911 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23912 TargetLowering::DAGCombinerInfo &DCI,
23913 const X86Subtarget *Subtarget) {
23916 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23917 // we're requiring SSE2 for both.
23918 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23919 SDValue N0 = N->getOperand(0);
23920 SDValue N1 = N->getOperand(1);
23921 SDValue CMP0 = N0->getOperand(1);
23922 SDValue CMP1 = N1->getOperand(1);
23925 // The SETCCs should both refer to the same CMP.
23926 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23929 SDValue CMP00 = CMP0->getOperand(0);
23930 SDValue CMP01 = CMP0->getOperand(1);
23931 EVT VT = CMP00.getValueType();
23933 if (VT == MVT::f32 || VT == MVT::f64) {
23934 bool ExpectingFlags = false;
23935 // Check for any users that want flags:
23936 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23937 !ExpectingFlags && UI != UE; ++UI)
23938 switch (UI->getOpcode()) {
23943 ExpectingFlags = true;
23945 case ISD::CopyToReg:
23946 case ISD::SIGN_EXTEND:
23947 case ISD::ZERO_EXTEND:
23948 case ISD::ANY_EXTEND:
23952 if (!ExpectingFlags) {
23953 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23954 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23956 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23957 X86::CondCode tmp = cc0;
23962 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23963 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23964 // FIXME: need symbolic constants for these magic numbers.
23965 // See X86ATTInstPrinter.cpp:printSSECC().
23966 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23967 if (Subtarget->hasAVX512()) {
23968 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23970 DAG.getConstant(x86cc, DL, MVT::i8));
23971 if (N->getValueType(0) != MVT::i1)
23972 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23976 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23977 CMP00.getValueType(), CMP00, CMP01,
23978 DAG.getConstant(x86cc, DL,
23981 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23982 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23984 if (is64BitFP && !Subtarget->is64Bit()) {
23985 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23986 // 64-bit integer, since that's not a legal type. Since
23987 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23988 // bits, but can do this little dance to extract the lowest 32 bits
23989 // and work with those going forward.
23990 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23992 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
23993 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23994 Vector32, DAG.getIntPtrConstant(0, DL));
23998 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
23999 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24000 DAG.getConstant(1, DL, IntVT));
24001 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24003 return OneBitOfTruth;
24011 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24012 /// so it can be folded inside ANDNP.
24013 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24014 EVT VT = N->getValueType(0);
24016 // Match direct AllOnes for 128 and 256-bit vectors
24017 if (ISD::isBuildVectorAllOnes(N))
24020 // Look through a bit convert.
24021 if (N->getOpcode() == ISD::BITCAST)
24022 N = N->getOperand(0).getNode();
24024 // Sometimes the operand may come from a insert_subvector building a 256-bit
24026 if (VT.is256BitVector() &&
24027 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24028 SDValue V1 = N->getOperand(0);
24029 SDValue V2 = N->getOperand(1);
24031 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24032 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24033 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24034 ISD::isBuildVectorAllOnes(V2.getNode()))
24041 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24042 // register. In most cases we actually compare or select YMM-sized registers
24043 // and mixing the two types creates horrible code. This method optimizes
24044 // some of the transition sequences.
24045 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24046 TargetLowering::DAGCombinerInfo &DCI,
24047 const X86Subtarget *Subtarget) {
24048 EVT VT = N->getValueType(0);
24049 if (!VT.is256BitVector())
24052 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24053 N->getOpcode() == ISD::ZERO_EXTEND ||
24054 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24056 SDValue Narrow = N->getOperand(0);
24057 EVT NarrowVT = Narrow->getValueType(0);
24058 if (!NarrowVT.is128BitVector())
24061 if (Narrow->getOpcode() != ISD::XOR &&
24062 Narrow->getOpcode() != ISD::AND &&
24063 Narrow->getOpcode() != ISD::OR)
24066 SDValue N0 = Narrow->getOperand(0);
24067 SDValue N1 = Narrow->getOperand(1);
24070 // The Left side has to be a trunc.
24071 if (N0.getOpcode() != ISD::TRUNCATE)
24074 // The type of the truncated inputs.
24075 EVT WideVT = N0->getOperand(0)->getValueType(0);
24079 // The right side has to be a 'trunc' or a constant vector.
24080 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24081 ConstantSDNode *RHSConstSplat = nullptr;
24082 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24083 RHSConstSplat = RHSBV->getConstantSplatNode();
24084 if (!RHSTrunc && !RHSConstSplat)
24087 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24089 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24092 // Set N0 and N1 to hold the inputs to the new wide operation.
24093 N0 = N0->getOperand(0);
24094 if (RHSConstSplat) {
24095 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24096 SDValue(RHSConstSplat, 0));
24097 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24098 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24099 } else if (RHSTrunc) {
24100 N1 = N1->getOperand(0);
24103 // Generate the wide operation.
24104 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24105 unsigned Opcode = N->getOpcode();
24107 case ISD::ANY_EXTEND:
24109 case ISD::ZERO_EXTEND: {
24110 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24111 APInt Mask = APInt::getAllOnesValue(InBits);
24112 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24113 return DAG.getNode(ISD::AND, DL, VT,
24114 Op, DAG.getConstant(Mask, DL, VT));
24116 case ISD::SIGN_EXTEND:
24117 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24118 Op, DAG.getValueType(NarrowVT));
24120 llvm_unreachable("Unexpected opcode");
24124 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24125 TargetLowering::DAGCombinerInfo &DCI,
24126 const X86Subtarget *Subtarget) {
24127 SDValue N0 = N->getOperand(0);
24128 SDValue N1 = N->getOperand(1);
24131 // A vector zext_in_reg may be represented as a shuffle,
24132 // feeding into a bitcast (this represents anyext) feeding into
24133 // an and with a mask.
24134 // We'd like to try to combine that into a shuffle with zero
24135 // plus a bitcast, removing the and.
24136 if (N0.getOpcode() != ISD::BITCAST ||
24137 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24140 // The other side of the AND should be a splat of 2^C, where C
24141 // is the number of bits in the source type.
24142 if (N1.getOpcode() == ISD::BITCAST)
24143 N1 = N1.getOperand(0);
24144 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24146 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24148 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24149 EVT SrcType = Shuffle->getValueType(0);
24151 // We expect a single-source shuffle
24152 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24155 unsigned SrcSize = SrcType.getScalarSizeInBits();
24157 APInt SplatValue, SplatUndef;
24158 unsigned SplatBitSize;
24160 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24161 SplatBitSize, HasAnyUndefs))
24164 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24165 // Make sure the splat matches the mask we expect
24166 if (SplatBitSize > ResSize ||
24167 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24170 // Make sure the input and output size make sense
24171 if (SrcSize >= ResSize || ResSize % SrcSize)
24174 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24175 // The number of u's between each two values depends on the ratio between
24176 // the source and dest type.
24177 unsigned ZextRatio = ResSize / SrcSize;
24178 bool IsZext = true;
24179 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24180 if (i % ZextRatio) {
24181 if (Shuffle->getMaskElt(i) > 0) {
24187 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24188 // Expected element number
24198 // Ok, perform the transformation - replace the shuffle with
24199 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24200 // (instead of undef) where the k elements come from the zero vector.
24201 SmallVector<int, 8> Mask;
24202 unsigned NumElems = SrcType.getVectorNumElements();
24203 for (unsigned i = 0; i < NumElems; ++i)
24205 Mask.push_back(NumElems);
24207 Mask.push_back(i / ZextRatio);
24209 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24210 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24211 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24214 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24215 TargetLowering::DAGCombinerInfo &DCI,
24216 const X86Subtarget *Subtarget) {
24217 if (DCI.isBeforeLegalizeOps())
24220 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
24223 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24226 EVT VT = N->getValueType(0);
24227 SDValue N0 = N->getOperand(0);
24228 SDValue N1 = N->getOperand(1);
24231 // Create BEXTR instructions
24232 // BEXTR is ((X >> imm) & (2**size-1))
24233 if (VT == MVT::i32 || VT == MVT::i64) {
24234 // Check for BEXTR.
24235 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24236 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24237 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24238 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24239 if (MaskNode && ShiftNode) {
24240 uint64_t Mask = MaskNode->getZExtValue();
24241 uint64_t Shift = ShiftNode->getZExtValue();
24242 if (isMask_64(Mask)) {
24243 uint64_t MaskSize = countPopulation(Mask);
24244 if (Shift + MaskSize <= VT.getSizeInBits())
24245 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24246 DAG.getConstant(Shift | (MaskSize << 8), DL,
24255 // Want to form ANDNP nodes:
24256 // 1) In the hopes of then easily combining them with OR and AND nodes
24257 // to form PBLEND/PSIGN.
24258 // 2) To match ANDN packed intrinsics
24259 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24262 // Check LHS for vnot
24263 if (N0.getOpcode() == ISD::XOR &&
24264 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24265 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24266 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24268 // Check RHS for vnot
24269 if (N1.getOpcode() == ISD::XOR &&
24270 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24271 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24272 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24277 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24278 TargetLowering::DAGCombinerInfo &DCI,
24279 const X86Subtarget *Subtarget) {
24280 if (DCI.isBeforeLegalizeOps())
24283 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24286 SDValue N0 = N->getOperand(0);
24287 SDValue N1 = N->getOperand(1);
24288 EVT VT = N->getValueType(0);
24290 // look for psign/blend
24291 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24292 if (!Subtarget->hasSSSE3() ||
24293 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24296 // Canonicalize pandn to RHS
24297 if (N0.getOpcode() == X86ISD::ANDNP)
24299 // or (and (m, y), (pandn m, x))
24300 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24301 SDValue Mask = N1.getOperand(0);
24302 SDValue X = N1.getOperand(1);
24304 if (N0.getOperand(0) == Mask)
24305 Y = N0.getOperand(1);
24306 if (N0.getOperand(1) == Mask)
24307 Y = N0.getOperand(0);
24309 // Check to see if the mask appeared in both the AND and ANDNP and
24313 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24314 // Look through mask bitcast.
24315 if (Mask.getOpcode() == ISD::BITCAST)
24316 Mask = Mask.getOperand(0);
24317 if (X.getOpcode() == ISD::BITCAST)
24318 X = X.getOperand(0);
24319 if (Y.getOpcode() == ISD::BITCAST)
24320 Y = Y.getOperand(0);
24322 EVT MaskVT = Mask.getValueType();
24324 // Validate that the Mask operand is a vector sra node.
24325 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24326 // there is no psrai.b
24327 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24328 unsigned SraAmt = ~0;
24329 if (Mask.getOpcode() == ISD::SRA) {
24330 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24331 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24332 SraAmt = AmtConst->getZExtValue();
24333 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24334 SDValue SraC = Mask.getOperand(1);
24335 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24337 if ((SraAmt + 1) != EltBits)
24342 // Now we know we at least have a plendvb with the mask val. See if
24343 // we can form a psignb/w/d.
24344 // psign = x.type == y.type == mask.type && y = sub(0, x);
24345 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24346 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24347 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24348 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24349 "Unsupported VT for PSIGN");
24350 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24351 return DAG.getBitcast(VT, Mask);
24353 // PBLENDVB only available on SSE 4.1
24354 if (!Subtarget->hasSSE41())
24357 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24359 X = DAG.getBitcast(BlendVT, X);
24360 Y = DAG.getBitcast(BlendVT, Y);
24361 Mask = DAG.getBitcast(BlendVT, Mask);
24362 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24363 return DAG.getBitcast(VT, Mask);
24367 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24370 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24371 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
24373 // SHLD/SHRD instructions have lower register pressure, but on some
24374 // platforms they have higher latency than the equivalent
24375 // series of shifts/or that would otherwise be generated.
24376 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24377 // have higher latencies and we are not optimizing for size.
24378 if (!OptForSize && Subtarget->isSHLDSlow())
24381 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24383 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24385 if (!N0.hasOneUse() || !N1.hasOneUse())
24388 SDValue ShAmt0 = N0.getOperand(1);
24389 if (ShAmt0.getValueType() != MVT::i8)
24391 SDValue ShAmt1 = N1.getOperand(1);
24392 if (ShAmt1.getValueType() != MVT::i8)
24394 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24395 ShAmt0 = ShAmt0.getOperand(0);
24396 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24397 ShAmt1 = ShAmt1.getOperand(0);
24400 unsigned Opc = X86ISD::SHLD;
24401 SDValue Op0 = N0.getOperand(0);
24402 SDValue Op1 = N1.getOperand(0);
24403 if (ShAmt0.getOpcode() == ISD::SUB) {
24404 Opc = X86ISD::SHRD;
24405 std::swap(Op0, Op1);
24406 std::swap(ShAmt0, ShAmt1);
24409 unsigned Bits = VT.getSizeInBits();
24410 if (ShAmt1.getOpcode() == ISD::SUB) {
24411 SDValue Sum = ShAmt1.getOperand(0);
24412 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24413 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24414 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24415 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24416 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24417 return DAG.getNode(Opc, DL, VT,
24419 DAG.getNode(ISD::TRUNCATE, DL,
24422 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24423 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24425 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24426 return DAG.getNode(Opc, DL, VT,
24427 N0.getOperand(0), N1.getOperand(0),
24428 DAG.getNode(ISD::TRUNCATE, DL,
24435 // Generate NEG and CMOV for integer abs.
24436 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24437 EVT VT = N->getValueType(0);
24439 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24440 // 8-bit integer abs to NEG and CMOV.
24441 if (VT.isInteger() && VT.getSizeInBits() == 8)
24444 SDValue N0 = N->getOperand(0);
24445 SDValue N1 = N->getOperand(1);
24448 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24449 // and change it to SUB and CMOV.
24450 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24451 N0.getOpcode() == ISD::ADD &&
24452 N0.getOperand(1) == N1 &&
24453 N1.getOpcode() == ISD::SRA &&
24454 N1.getOperand(0) == N0.getOperand(0))
24455 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24456 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24457 // Generate SUB & CMOV.
24458 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24459 DAG.getConstant(0, DL, VT), N0.getOperand(0));
24461 SDValue Ops[] = { N0.getOperand(0), Neg,
24462 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
24463 SDValue(Neg.getNode(), 1) };
24464 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24469 // Try to turn tests against the signbit in the form of:
24470 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
24473 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
24474 // This is only worth doing if the output type is i8.
24475 if (N->getValueType(0) != MVT::i8)
24478 SDValue N0 = N->getOperand(0);
24479 SDValue N1 = N->getOperand(1);
24481 // We should be performing an xor against a truncated shift.
24482 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
24485 // Make sure we are performing an xor against one.
24486 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
24489 // SetCC on x86 zero extends so only act on this if it's a logical shift.
24490 SDValue Shift = N0.getOperand(0);
24491 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
24494 // Make sure we are truncating from one of i16, i32 or i64.
24495 EVT ShiftTy = Shift.getValueType();
24496 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
24499 // Make sure the shift amount extracts the sign bit.
24500 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
24501 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
24504 // Create a greater-than comparison against -1.
24505 // N.B. Using SETGE against 0 works but we want a canonical looking
24506 // comparison, using SETGT matches up with what TranslateX86CC.
24508 SDValue ShiftOp = Shift.getOperand(0);
24509 EVT ShiftOpTy = ShiftOp.getValueType();
24510 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
24511 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
24515 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24516 TargetLowering::DAGCombinerInfo &DCI,
24517 const X86Subtarget *Subtarget) {
24518 if (DCI.isBeforeLegalizeOps())
24521 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
24524 if (Subtarget->hasCMov())
24525 if (SDValue RV = performIntegerAbsCombine(N, DAG))
24531 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24532 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24533 TargetLowering::DAGCombinerInfo &DCI,
24534 const X86Subtarget *Subtarget) {
24535 LoadSDNode *Ld = cast<LoadSDNode>(N);
24536 EVT RegVT = Ld->getValueType(0);
24537 EVT MemVT = Ld->getMemoryVT();
24539 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24541 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24542 // into two 16-byte operations.
24543 ISD::LoadExtType Ext = Ld->getExtensionType();
24545 unsigned AddressSpace = Ld->getAddressSpace();
24546 unsigned Alignment = Ld->getAlignment();
24547 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
24548 Ext == ISD::NON_EXTLOAD &&
24549 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
24550 AddressSpace, Alignment, &Fast) && !Fast) {
24551 unsigned NumElems = RegVT.getVectorNumElements();
24555 SDValue Ptr = Ld->getBasePtr();
24556 SDValue Increment =
24557 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
24559 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24561 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24562 Ld->getPointerInfo(), Ld->isVolatile(),
24563 Ld->isNonTemporal(), Ld->isInvariant(),
24565 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24566 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24567 Ld->getPointerInfo(), Ld->isVolatile(),
24568 Ld->isNonTemporal(), Ld->isInvariant(),
24569 std::min(16U, Alignment));
24570 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24572 Load2.getValue(1));
24574 SDValue NewVec = DAG.getUNDEF(RegVT);
24575 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24576 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24577 return DCI.CombineTo(N, NewVec, TF, true);
24583 /// PerformMLOADCombine - Resolve extending loads
24584 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
24585 TargetLowering::DAGCombinerInfo &DCI,
24586 const X86Subtarget *Subtarget) {
24587 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
24588 if (Mld->getExtensionType() != ISD::SEXTLOAD)
24591 EVT VT = Mld->getValueType(0);
24592 unsigned NumElems = VT.getVectorNumElements();
24593 EVT LdVT = Mld->getMemoryVT();
24596 assert(LdVT != VT && "Cannot extend to the same type");
24597 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
24598 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
24599 // From, To sizes and ElemCount must be pow of two
24600 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24601 "Unexpected size for extending masked load");
24603 unsigned SizeRatio = ToSz / FromSz;
24604 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
24606 // Create a type on which we perform the shuffle
24607 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24608 LdVT.getScalarType(), NumElems*SizeRatio);
24609 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24611 // Convert Src0 value
24612 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
24613 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
24614 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24615 for (unsigned i = 0; i != NumElems; ++i)
24616 ShuffleVec[i] = i * SizeRatio;
24618 // Can't shuffle using an illegal type.
24619 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
24620 && "WideVecVT should be legal");
24621 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
24622 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
24624 // Prepare the new mask
24626 SDValue Mask = Mld->getMask();
24627 if (Mask.getValueType() == VT) {
24628 // Mask and original value have the same type
24629 NewMask = DAG.getBitcast(WideVecVT, Mask);
24630 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24631 for (unsigned i = 0; i != NumElems; ++i)
24632 ShuffleVec[i] = i * SizeRatio;
24633 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
24634 ShuffleVec[i] = NumElems*SizeRatio;
24635 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
24636 DAG.getConstant(0, dl, WideVecVT),
24640 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
24641 unsigned WidenNumElts = NumElems*SizeRatio;
24642 unsigned MaskNumElts = VT.getVectorNumElements();
24643 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
24646 unsigned NumConcat = WidenNumElts / MaskNumElts;
24647 SmallVector<SDValue, 16> Ops(NumConcat);
24648 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
24650 for (unsigned i = 1; i != NumConcat; ++i)
24653 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
24656 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
24657 Mld->getBasePtr(), NewMask, WideSrc0,
24658 Mld->getMemoryVT(), Mld->getMemOperand(),
24660 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
24661 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
24664 /// PerformMSTORECombine - Resolve truncating stores
24665 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
24666 const X86Subtarget *Subtarget) {
24667 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
24668 if (!Mst->isTruncatingStore())
24671 EVT VT = Mst->getValue().getValueType();
24672 unsigned NumElems = VT.getVectorNumElements();
24673 EVT StVT = Mst->getMemoryVT();
24676 assert(StVT != VT && "Cannot truncate to the same type");
24677 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24678 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24680 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24682 // The truncating store is legal in some cases. For example
24683 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
24684 // are designated for truncate store.
24685 // In this case we don't need any further transformations.
24686 if (TLI.isTruncStoreLegal(VT, StVT))
24689 // From, To sizes and ElemCount must be pow of two
24690 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24691 "Unexpected size for truncating masked store");
24692 // We are going to use the original vector elt for storing.
24693 // Accumulated smaller vector elements must be a multiple of the store size.
24694 assert (((NumElems * FromSz) % ToSz) == 0 &&
24695 "Unexpected ratio for truncating masked store");
24697 unsigned SizeRatio = FromSz / ToSz;
24698 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24700 // Create a type on which we perform the shuffle
24701 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24702 StVT.getScalarType(), NumElems*SizeRatio);
24704 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24706 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
24707 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24708 for (unsigned i = 0; i != NumElems; ++i)
24709 ShuffleVec[i] = i * SizeRatio;
24711 // Can't shuffle using an illegal type.
24712 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
24713 && "WideVecVT should be legal");
24715 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24716 DAG.getUNDEF(WideVecVT),
24720 SDValue Mask = Mst->getMask();
24721 if (Mask.getValueType() == VT) {
24722 // Mask and original value have the same type
24723 NewMask = DAG.getBitcast(WideVecVT, Mask);
24724 for (unsigned i = 0; i != NumElems; ++i)
24725 ShuffleVec[i] = i * SizeRatio;
24726 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
24727 ShuffleVec[i] = NumElems*SizeRatio;
24728 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
24729 DAG.getConstant(0, dl, WideVecVT),
24733 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
24734 unsigned WidenNumElts = NumElems*SizeRatio;
24735 unsigned MaskNumElts = VT.getVectorNumElements();
24736 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
24739 unsigned NumConcat = WidenNumElts / MaskNumElts;
24740 SmallVector<SDValue, 16> Ops(NumConcat);
24741 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
24743 for (unsigned i = 1; i != NumConcat; ++i)
24746 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
24749 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
24750 NewMask, StVT, Mst->getMemOperand(), false);
24752 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24753 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24754 const X86Subtarget *Subtarget) {
24755 StoreSDNode *St = cast<StoreSDNode>(N);
24756 EVT VT = St->getValue().getValueType();
24757 EVT StVT = St->getMemoryVT();
24759 SDValue StoredVal = St->getOperand(1);
24760 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24762 // If we are saving a concatenation of two XMM registers and 32-byte stores
24763 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24765 unsigned AddressSpace = St->getAddressSpace();
24766 unsigned Alignment = St->getAlignment();
24767 if (VT.is256BitVector() && StVT == VT &&
24768 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
24769 AddressSpace, Alignment, &Fast) && !Fast) {
24770 unsigned NumElems = VT.getVectorNumElements();
24774 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24775 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24778 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
24779 SDValue Ptr0 = St->getBasePtr();
24780 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24782 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24783 St->getPointerInfo(), St->isVolatile(),
24784 St->isNonTemporal(), Alignment);
24785 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24786 St->getPointerInfo(), St->isVolatile(),
24787 St->isNonTemporal(),
24788 std::min(16U, Alignment));
24789 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24792 // Optimize trunc store (of multiple scalars) to shuffle and store.
24793 // First, pack all of the elements in one place. Next, store to memory
24794 // in fewer chunks.
24795 if (St->isTruncatingStore() && VT.isVector()) {
24796 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24797 unsigned NumElems = VT.getVectorNumElements();
24798 assert(StVT != VT && "Cannot truncate to the same type");
24799 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24800 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24802 // The truncating store is legal in some cases. For example
24803 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
24804 // are designated for truncate store.
24805 // In this case we don't need any further transformations.
24806 if (TLI.isTruncStoreLegal(VT, StVT))
24809 // From, To sizes and ElemCount must be pow of two
24810 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24811 // We are going to use the original vector elt for storing.
24812 // Accumulated smaller vector elements must be a multiple of the store size.
24813 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24815 unsigned SizeRatio = FromSz / ToSz;
24817 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24819 // Create a type on which we perform the shuffle
24820 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24821 StVT.getScalarType(), NumElems*SizeRatio);
24823 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24825 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
24826 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24827 for (unsigned i = 0; i != NumElems; ++i)
24828 ShuffleVec[i] = i * SizeRatio;
24830 // Can't shuffle using an illegal type.
24831 if (!TLI.isTypeLegal(WideVecVT))
24834 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24835 DAG.getUNDEF(WideVecVT),
24837 // At this point all of the data is stored at the bottom of the
24838 // register. We now need to save it to mem.
24840 // Find the largest store unit
24841 MVT StoreType = MVT::i8;
24842 for (MVT Tp : MVT::integer_valuetypes()) {
24843 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24847 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24848 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24849 (64 <= NumElems * ToSz))
24850 StoreType = MVT::f64;
24852 // Bitcast the original vector into a vector of store-size units
24853 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24854 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24855 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24856 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
24857 SmallVector<SDValue, 8> Chains;
24858 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
24859 TLI.getPointerTy(DAG.getDataLayout()));
24860 SDValue Ptr = St->getBasePtr();
24862 // Perform one or more big stores into memory.
24863 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24864 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24865 StoreType, ShuffWide,
24866 DAG.getIntPtrConstant(i, dl));
24867 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24868 St->getPointerInfo(), St->isVolatile(),
24869 St->isNonTemporal(), St->getAlignment());
24870 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24871 Chains.push_back(Ch);
24874 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24877 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24878 // the FP state in cases where an emms may be missing.
24879 // A preferable solution to the general problem is to figure out the right
24880 // places to insert EMMS. This qualifies as a quick hack.
24882 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24883 if (VT.getSizeInBits() != 64)
24886 const Function *F = DAG.getMachineFunction().getFunction();
24887 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
24889 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
24890 if ((VT.isVector() ||
24891 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24892 isa<LoadSDNode>(St->getValue()) &&
24893 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24894 St->getChain().hasOneUse() && !St->isVolatile()) {
24895 SDNode* LdVal = St->getValue().getNode();
24896 LoadSDNode *Ld = nullptr;
24897 int TokenFactorIndex = -1;
24898 SmallVector<SDValue, 8> Ops;
24899 SDNode* ChainVal = St->getChain().getNode();
24900 // Must be a store of a load. We currently handle two cases: the load
24901 // is a direct child, and it's under an intervening TokenFactor. It is
24902 // possible to dig deeper under nested TokenFactors.
24903 if (ChainVal == LdVal)
24904 Ld = cast<LoadSDNode>(St->getChain());
24905 else if (St->getValue().hasOneUse() &&
24906 ChainVal->getOpcode() == ISD::TokenFactor) {
24907 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24908 if (ChainVal->getOperand(i).getNode() == LdVal) {
24909 TokenFactorIndex = i;
24910 Ld = cast<LoadSDNode>(St->getValue());
24912 Ops.push_back(ChainVal->getOperand(i));
24916 if (!Ld || !ISD::isNormalLoad(Ld))
24919 // If this is not the MMX case, i.e. we are just turning i64 load/store
24920 // into f64 load/store, avoid the transformation if there are multiple
24921 // uses of the loaded value.
24922 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24927 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24928 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24930 if (Subtarget->is64Bit() || F64IsLegal) {
24931 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24932 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24933 Ld->getPointerInfo(), Ld->isVolatile(),
24934 Ld->isNonTemporal(), Ld->isInvariant(),
24935 Ld->getAlignment());
24936 SDValue NewChain = NewLd.getValue(1);
24937 if (TokenFactorIndex != -1) {
24938 Ops.push_back(NewChain);
24939 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24941 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24942 St->getPointerInfo(),
24943 St->isVolatile(), St->isNonTemporal(),
24944 St->getAlignment());
24947 // Otherwise, lower to two pairs of 32-bit loads / stores.
24948 SDValue LoAddr = Ld->getBasePtr();
24949 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24950 DAG.getConstant(4, LdDL, MVT::i32));
24952 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24953 Ld->getPointerInfo(),
24954 Ld->isVolatile(), Ld->isNonTemporal(),
24955 Ld->isInvariant(), Ld->getAlignment());
24956 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24957 Ld->getPointerInfo().getWithOffset(4),
24958 Ld->isVolatile(), Ld->isNonTemporal(),
24960 MinAlign(Ld->getAlignment(), 4));
24962 SDValue NewChain = LoLd.getValue(1);
24963 if (TokenFactorIndex != -1) {
24964 Ops.push_back(LoLd);
24965 Ops.push_back(HiLd);
24966 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24969 LoAddr = St->getBasePtr();
24970 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24971 DAG.getConstant(4, StDL, MVT::i32));
24973 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24974 St->getPointerInfo(),
24975 St->isVolatile(), St->isNonTemporal(),
24976 St->getAlignment());
24977 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24978 St->getPointerInfo().getWithOffset(4),
24980 St->isNonTemporal(),
24981 MinAlign(St->getAlignment(), 4));
24982 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24985 // This is similar to the above case, but here we handle a scalar 64-bit
24986 // integer store that is extracted from a vector on a 32-bit target.
24987 // If we have SSE2, then we can treat it like a floating-point double
24988 // to get past legalization. The execution dependencies fixup pass will
24989 // choose the optimal machine instruction for the store if this really is
24990 // an integer or v2f32 rather than an f64.
24991 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
24992 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
24993 SDValue OldExtract = St->getOperand(1);
24994 SDValue ExtOp0 = OldExtract.getOperand(0);
24995 unsigned VecSize = ExtOp0.getValueSizeInBits();
24996 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
24997 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
24998 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
24999 BitCast, OldExtract.getOperand(1));
25000 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25001 St->getPointerInfo(), St->isVolatile(),
25002 St->isNonTemporal(), St->getAlignment());
25008 /// Return 'true' if this vector operation is "horizontal"
25009 /// and return the operands for the horizontal operation in LHS and RHS. A
25010 /// horizontal operation performs the binary operation on successive elements
25011 /// of its first operand, then on successive elements of its second operand,
25012 /// returning the resulting values in a vector. For example, if
25013 /// A = < float a0, float a1, float a2, float a3 >
25015 /// B = < float b0, float b1, float b2, float b3 >
25016 /// then the result of doing a horizontal operation on A and B is
25017 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25018 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25019 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25020 /// set to A, RHS to B, and the routine returns 'true'.
25021 /// Note that the binary operation should have the property that if one of the
25022 /// operands is UNDEF then the result is UNDEF.
25023 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25024 // Look for the following pattern: if
25025 // A = < float a0, float a1, float a2, float a3 >
25026 // B = < float b0, float b1, float b2, float b3 >
25028 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25029 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25030 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25031 // which is A horizontal-op B.
25033 // At least one of the operands should be a vector shuffle.
25034 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25035 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25038 MVT VT = LHS.getSimpleValueType();
25040 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25041 "Unsupported vector type for horizontal add/sub");
25043 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25044 // operate independently on 128-bit lanes.
25045 unsigned NumElts = VT.getVectorNumElements();
25046 unsigned NumLanes = VT.getSizeInBits()/128;
25047 unsigned NumLaneElts = NumElts / NumLanes;
25048 assert((NumLaneElts % 2 == 0) &&
25049 "Vector type should have an even number of elements in each lane");
25050 unsigned HalfLaneElts = NumLaneElts/2;
25052 // View LHS in the form
25053 // LHS = VECTOR_SHUFFLE A, B, LMask
25054 // If LHS is not a shuffle then pretend it is the shuffle
25055 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25056 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25059 SmallVector<int, 16> LMask(NumElts);
25060 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25061 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25062 A = LHS.getOperand(0);
25063 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25064 B = LHS.getOperand(1);
25065 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25066 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25068 if (LHS.getOpcode() != ISD::UNDEF)
25070 for (unsigned i = 0; i != NumElts; ++i)
25074 // Likewise, view RHS in the form
25075 // RHS = VECTOR_SHUFFLE C, D, RMask
25077 SmallVector<int, 16> RMask(NumElts);
25078 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25079 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25080 C = RHS.getOperand(0);
25081 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25082 D = RHS.getOperand(1);
25083 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25084 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25086 if (RHS.getOpcode() != ISD::UNDEF)
25088 for (unsigned i = 0; i != NumElts; ++i)
25092 // Check that the shuffles are both shuffling the same vectors.
25093 if (!(A == C && B == D) && !(A == D && B == C))
25096 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25097 if (!A.getNode() && !B.getNode())
25100 // If A and B occur in reverse order in RHS, then "swap" them (which means
25101 // rewriting the mask).
25103 ShuffleVectorSDNode::commuteMask(RMask);
25105 // At this point LHS and RHS are equivalent to
25106 // LHS = VECTOR_SHUFFLE A, B, LMask
25107 // RHS = VECTOR_SHUFFLE A, B, RMask
25108 // Check that the masks correspond to performing a horizontal operation.
25109 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25110 for (unsigned i = 0; i != NumLaneElts; ++i) {
25111 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25113 // Ignore any UNDEF components.
25114 if (LIdx < 0 || RIdx < 0 ||
25115 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25116 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25119 // Check that successive elements are being operated on. If not, this is
25120 // not a horizontal operation.
25121 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25122 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25123 if (!(LIdx == Index && RIdx == Index + 1) &&
25124 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25129 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25130 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25134 /// Do target-specific dag combines on floating point adds.
25135 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25136 const X86Subtarget *Subtarget) {
25137 EVT VT = N->getValueType(0);
25138 SDValue LHS = N->getOperand(0);
25139 SDValue RHS = N->getOperand(1);
25141 // Try to synthesize horizontal adds from adds of shuffles.
25142 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25143 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25144 isHorizontalBinOp(LHS, RHS, true))
25145 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25149 /// Do target-specific dag combines on floating point subs.
25150 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25151 const X86Subtarget *Subtarget) {
25152 EVT VT = N->getValueType(0);
25153 SDValue LHS = N->getOperand(0);
25154 SDValue RHS = N->getOperand(1);
25156 // Try to synthesize horizontal subs from subs of shuffles.
25157 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25158 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25159 isHorizontalBinOp(LHS, RHS, false))
25160 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25164 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25165 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
25166 const X86Subtarget *Subtarget) {
25167 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25169 // F[X]OR(0.0, x) -> x
25170 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25171 if (C->getValueAPF().isPosZero())
25172 return N->getOperand(1);
25174 // F[X]OR(x, 0.0) -> x
25175 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25176 if (C->getValueAPF().isPosZero())
25177 return N->getOperand(0);
25179 EVT VT = N->getValueType(0);
25180 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
25182 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
25183 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
25185 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
25186 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
25187 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
25188 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
25189 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
25194 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25195 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25196 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25198 // Only perform optimizations if UnsafeMath is used.
25199 if (!DAG.getTarget().Options.UnsafeFPMath)
25202 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25203 // into FMINC and FMAXC, which are Commutative operations.
25204 unsigned NewOp = 0;
25205 switch (N->getOpcode()) {
25206 default: llvm_unreachable("unknown opcode");
25207 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25208 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25211 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25212 N->getOperand(0), N->getOperand(1));
25215 /// Do target-specific dag combines on X86ISD::FAND nodes.
25216 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25217 // FAND(0.0, x) -> 0.0
25218 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25219 if (C->getValueAPF().isPosZero())
25220 return N->getOperand(0);
25222 // FAND(x, 0.0) -> 0.0
25223 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25224 if (C->getValueAPF().isPosZero())
25225 return N->getOperand(1);
25230 /// Do target-specific dag combines on X86ISD::FANDN nodes
25231 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25232 // FANDN(0.0, x) -> x
25233 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25234 if (C->getValueAPF().isPosZero())
25235 return N->getOperand(1);
25237 // FANDN(x, 0.0) -> 0.0
25238 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25239 if (C->getValueAPF().isPosZero())
25240 return N->getOperand(1);
25245 static SDValue PerformBTCombine(SDNode *N,
25247 TargetLowering::DAGCombinerInfo &DCI) {
25248 // BT ignores high bits in the bit index operand.
25249 SDValue Op1 = N->getOperand(1);
25250 if (Op1.hasOneUse()) {
25251 unsigned BitWidth = Op1.getValueSizeInBits();
25252 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25253 APInt KnownZero, KnownOne;
25254 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25255 !DCI.isBeforeLegalizeOps());
25256 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25257 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25258 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25259 DCI.CommitTargetLoweringOpt(TLO);
25264 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25265 SDValue Op = N->getOperand(0);
25266 if (Op.getOpcode() == ISD::BITCAST)
25267 Op = Op.getOperand(0);
25268 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25269 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25270 VT.getVectorElementType().getSizeInBits() ==
25271 OpVT.getVectorElementType().getSizeInBits()) {
25272 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25277 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25278 const X86Subtarget *Subtarget) {
25279 EVT VT = N->getValueType(0);
25280 if (!VT.isVector())
25283 SDValue N0 = N->getOperand(0);
25284 SDValue N1 = N->getOperand(1);
25285 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25288 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25289 // both SSE and AVX2 since there is no sign-extended shift right
25290 // operation on a vector with 64-bit elements.
25291 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25292 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25293 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25294 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25295 SDValue N00 = N0.getOperand(0);
25297 // EXTLOAD has a better solution on AVX2,
25298 // it may be replaced with X86ISD::VSEXT node.
25299 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25300 if (!ISD::isNormalLoad(N00.getNode()))
25303 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25304 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25306 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25312 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25313 TargetLowering::DAGCombinerInfo &DCI,
25314 const X86Subtarget *Subtarget) {
25315 SDValue N0 = N->getOperand(0);
25316 EVT VT = N->getValueType(0);
25317 EVT SVT = VT.getScalarType();
25318 EVT InVT = N0.getValueType();
25319 EVT InSVT = InVT.getScalarType();
25322 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25323 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25324 // This exposes the sext to the sdivrem lowering, so that it directly extends
25325 // from AH (which we otherwise need to do contortions to access).
25326 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25327 InVT == MVT::i8 && VT == MVT::i32) {
25328 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25329 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
25330 N0.getOperand(0), N0.getOperand(1));
25331 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25332 return R.getValue(1);
25335 if (!DCI.isBeforeLegalizeOps()) {
25336 if (InVT == MVT::i1) {
25337 SDValue Zero = DAG.getConstant(0, DL, VT);
25339 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
25340 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
25345 if (VT.isVector() && Subtarget->hasSSE2()) {
25346 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
25347 EVT InVT = N.getValueType();
25348 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
25349 Size / InVT.getScalarSizeInBits());
25350 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
25351 DAG.getUNDEF(InVT));
25353 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
25356 // If target-size is less than 128-bits, extend to a type that would extend
25357 // to 128 bits, extend that and extract the original target vector.
25358 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
25359 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25360 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25361 unsigned Scale = 128 / VT.getSizeInBits();
25363 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
25364 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
25365 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
25366 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
25367 DAG.getIntPtrConstant(0, DL));
25370 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
25371 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
25372 if (VT.getSizeInBits() == 128 &&
25373 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25374 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25375 SDValue ExOp = ExtendVecSize(DL, N0, 128);
25376 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
25379 // On pre-AVX2 targets, split into 128-bit nodes of
25380 // ISD::SIGN_EXTEND_VECTOR_INREG.
25381 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
25382 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25383 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25384 unsigned NumVecs = VT.getSizeInBits() / 128;
25385 unsigned NumSubElts = 128 / SVT.getSizeInBits();
25386 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
25387 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
25389 SmallVector<SDValue, 8> Opnds;
25390 for (unsigned i = 0, Offset = 0; i != NumVecs;
25391 ++i, Offset += NumSubElts) {
25392 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
25393 DAG.getIntPtrConstant(Offset, DL));
25394 SrcVec = ExtendVecSize(DL, SrcVec, 128);
25395 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
25396 Opnds.push_back(SrcVec);
25398 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
25402 if (!Subtarget->hasFp256())
25405 if (VT.isVector() && VT.getSizeInBits() == 256)
25406 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25412 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25413 const X86Subtarget* Subtarget) {
25415 EVT VT = N->getValueType(0);
25417 // Let legalize expand this if it isn't a legal type yet.
25418 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25421 EVT ScalarVT = VT.getScalarType();
25422 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25423 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
25424 !Subtarget->hasAVX512()))
25427 SDValue A = N->getOperand(0);
25428 SDValue B = N->getOperand(1);
25429 SDValue C = N->getOperand(2);
25431 bool NegA = (A.getOpcode() == ISD::FNEG);
25432 bool NegB = (B.getOpcode() == ISD::FNEG);
25433 bool NegC = (C.getOpcode() == ISD::FNEG);
25435 // Negative multiplication when NegA xor NegB
25436 bool NegMul = (NegA != NegB);
25438 A = A.getOperand(0);
25440 B = B.getOperand(0);
25442 C = C.getOperand(0);
25446 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25448 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25450 return DAG.getNode(Opcode, dl, VT, A, B, C);
25453 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25454 TargetLowering::DAGCombinerInfo &DCI,
25455 const X86Subtarget *Subtarget) {
25456 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25457 // (and (i32 x86isd::setcc_carry), 1)
25458 // This eliminates the zext. This transformation is necessary because
25459 // ISD::SETCC is always legalized to i8.
25461 SDValue N0 = N->getOperand(0);
25462 EVT VT = N->getValueType(0);
25464 if (N0.getOpcode() == ISD::AND &&
25466 N0.getOperand(0).hasOneUse()) {
25467 SDValue N00 = N0.getOperand(0);
25468 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25469 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25470 if (!C || C->getZExtValue() != 1)
25472 return DAG.getNode(ISD::AND, dl, VT,
25473 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25474 N00.getOperand(0), N00.getOperand(1)),
25475 DAG.getConstant(1, dl, VT));
25479 if (N0.getOpcode() == ISD::TRUNCATE &&
25481 N0.getOperand(0).hasOneUse()) {
25482 SDValue N00 = N0.getOperand(0);
25483 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25484 return DAG.getNode(ISD::AND, dl, VT,
25485 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25486 N00.getOperand(0), N00.getOperand(1)),
25487 DAG.getConstant(1, dl, VT));
25491 if (VT.is256BitVector())
25492 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25495 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25496 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25497 // This exposes the zext to the udivrem lowering, so that it directly extends
25498 // from AH (which we otherwise need to do contortions to access).
25499 if (N0.getOpcode() == ISD::UDIVREM &&
25500 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25501 (VT == MVT::i32 || VT == MVT::i64)) {
25502 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25503 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25504 N0.getOperand(0), N0.getOperand(1));
25505 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25506 return R.getValue(1);
25512 // Optimize x == -y --> x+y == 0
25513 // x != -y --> x+y != 0
25514 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25515 const X86Subtarget* Subtarget) {
25516 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25517 SDValue LHS = N->getOperand(0);
25518 SDValue RHS = N->getOperand(1);
25519 EVT VT = N->getValueType(0);
25522 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25523 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25524 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25525 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
25526 LHS.getOperand(1));
25527 return DAG.getSetCC(DL, N->getValueType(0), addV,
25528 DAG.getConstant(0, DL, addV.getValueType()), CC);
25530 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25531 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25532 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25533 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
25534 RHS.getOperand(1));
25535 return DAG.getSetCC(DL, N->getValueType(0), addV,
25536 DAG.getConstant(0, DL, addV.getValueType()), CC);
25539 if (VT.getScalarType() == MVT::i1 &&
25540 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
25542 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25543 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25544 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25546 if (!IsSEXT0 || !IsVZero1) {
25547 // Swap the operands and update the condition code.
25548 std::swap(LHS, RHS);
25549 CC = ISD::getSetCCSwappedOperands(CC);
25551 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25552 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25553 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25556 if (IsSEXT0 && IsVZero1) {
25557 assert(VT == LHS.getOperand(0).getValueType() &&
25558 "Uexpected operand type");
25559 if (CC == ISD::SETGT)
25560 return DAG.getConstant(0, DL, VT);
25561 if (CC == ISD::SETLE)
25562 return DAG.getConstant(1, DL, VT);
25563 if (CC == ISD::SETEQ || CC == ISD::SETGE)
25564 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25566 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
25567 "Unexpected condition code!");
25568 return LHS.getOperand(0);
25575 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
25576 SelectionDAG &DAG) {
25578 MVT VT = Load->getSimpleValueType(0);
25579 MVT EVT = VT.getVectorElementType();
25580 SDValue Addr = Load->getOperand(1);
25581 SDValue NewAddr = DAG.getNode(
25582 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
25583 DAG.getConstant(Index * EVT.getStoreSize(), dl,
25584 Addr.getSimpleValueType()));
25587 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
25588 DAG.getMachineFunction().getMachineMemOperand(
25589 Load->getMemOperand(), 0, EVT.getStoreSize()));
25593 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25594 const X86Subtarget *Subtarget) {
25596 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25597 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25598 "X86insertps is only defined for v4x32");
25600 SDValue Ld = N->getOperand(1);
25601 if (MayFoldLoad(Ld)) {
25602 // Extract the countS bits from the immediate so we can get the proper
25603 // address when narrowing the vector load to a specific element.
25604 // When the second source op is a memory address, insertps doesn't use
25605 // countS and just gets an f32 from that address.
25606 unsigned DestIndex =
25607 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25609 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25611 // Create this as a scalar to vector to match the instruction pattern.
25612 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25613 // countS bits are ignored when loading from memory on insertps, which
25614 // means we don't need to explicitly set them to 0.
25615 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25616 LoadScalarToVector, N->getOperand(2));
25621 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
25622 SDValue V0 = N->getOperand(0);
25623 SDValue V1 = N->getOperand(1);
25625 EVT VT = N->getValueType(0);
25627 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
25628 // operands and changing the mask to 1. This saves us a bunch of
25629 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
25630 // x86InstrInfo knows how to commute this back after instruction selection
25631 // if it would help register allocation.
25633 // TODO: If optimizing for size or a processor that doesn't suffer from
25634 // partial register update stalls, this should be transformed into a MOVSD
25635 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
25637 if (VT == MVT::v2f64)
25638 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
25639 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
25640 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
25641 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
25647 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25648 // as "sbb reg,reg", since it can be extended without zext and produces
25649 // an all-ones bit which is more useful than 0/1 in some cases.
25650 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25653 return DAG.getNode(ISD::AND, DL, VT,
25654 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25655 DAG.getConstant(X86::COND_B, DL, MVT::i8),
25657 DAG.getConstant(1, DL, VT));
25658 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25659 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25660 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25661 DAG.getConstant(X86::COND_B, DL, MVT::i8),
25665 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25666 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25667 TargetLowering::DAGCombinerInfo &DCI,
25668 const X86Subtarget *Subtarget) {
25670 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25671 SDValue EFLAGS = N->getOperand(1);
25673 if (CC == X86::COND_A) {
25674 // Try to convert COND_A into COND_B in an attempt to facilitate
25675 // materializing "setb reg".
25677 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25678 // cannot take an immediate as its first operand.
25680 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25681 EFLAGS.getValueType().isInteger() &&
25682 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25683 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25684 EFLAGS.getNode()->getVTList(),
25685 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25686 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25687 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25691 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25692 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25694 if (CC == X86::COND_B)
25695 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25697 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
25698 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
25699 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25705 // Optimize branch condition evaluation.
25707 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25708 TargetLowering::DAGCombinerInfo &DCI,
25709 const X86Subtarget *Subtarget) {
25711 SDValue Chain = N->getOperand(0);
25712 SDValue Dest = N->getOperand(1);
25713 SDValue EFLAGS = N->getOperand(3);
25714 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25716 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
25717 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
25718 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25725 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25726 SelectionDAG &DAG) {
25727 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25728 // optimize away operation when it's from a constant.
25730 // The general transformation is:
25731 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25732 // AND(VECTOR_CMP(x,y), constant2)
25733 // constant2 = UNARYOP(constant)
25735 // Early exit if this isn't a vector operation, the operand of the
25736 // unary operation isn't a bitwise AND, or if the sizes of the operations
25737 // aren't the same.
25738 EVT VT = N->getValueType(0);
25739 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25740 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25741 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25744 // Now check that the other operand of the AND is a constant. We could
25745 // make the transformation for non-constant splats as well, but it's unclear
25746 // that would be a benefit as it would not eliminate any operations, just
25747 // perform one more step in scalar code before moving to the vector unit.
25748 if (BuildVectorSDNode *BV =
25749 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25750 // Bail out if the vector isn't a constant.
25751 if (!BV->isConstant())
25754 // Everything checks out. Build up the new and improved node.
25756 EVT IntVT = BV->getValueType(0);
25757 // Create a new constant of the appropriate type for the transformed
25759 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25760 // The AND node needs bitcasts to/from an integer vector type around it.
25761 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
25762 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25763 N->getOperand(0)->getOperand(0), MaskConst);
25764 SDValue Res = DAG.getBitcast(VT, NewAnd);
25771 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25772 const X86Subtarget *Subtarget) {
25773 SDValue Op0 = N->getOperand(0);
25774 EVT VT = N->getValueType(0);
25775 EVT InVT = Op0.getValueType();
25776 EVT InSVT = InVT.getScalarType();
25777 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25779 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
25780 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
25781 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
25783 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
25784 InVT.getVectorNumElements());
25785 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
25787 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
25788 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
25790 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
25796 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25797 const X86Subtarget *Subtarget) {
25798 // First try to optimize away the conversion entirely when it's
25799 // conditionally from a constant. Vectors only.
25800 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
25803 // Now move on to more general possibilities.
25804 SDValue Op0 = N->getOperand(0);
25805 EVT VT = N->getValueType(0);
25806 EVT InVT = Op0.getValueType();
25807 EVT InSVT = InVT.getScalarType();
25809 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
25810 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
25811 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
25813 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
25814 InVT.getVectorNumElements());
25815 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25816 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
25819 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25820 // a 32-bit target where SSE doesn't support i64->FP operations.
25821 if (Op0.getOpcode() == ISD::LOAD) {
25822 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25823 EVT LdVT = Ld->getValueType(0);
25825 // This transformation is not supported if the result type is f16
25826 if (VT == MVT::f16)
25829 if (!Ld->isVolatile() && !VT.isVector() &&
25830 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25831 !Subtarget->is64Bit() && LdVT == MVT::i64) {
25832 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
25833 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
25834 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25841 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25842 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25843 X86TargetLowering::DAGCombinerInfo &DCI) {
25844 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25845 // the result is either zero or one (depending on the input carry bit).
25846 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25847 if (X86::isZeroNode(N->getOperand(0)) &&
25848 X86::isZeroNode(N->getOperand(1)) &&
25849 // We don't have a good way to replace an EFLAGS use, so only do this when
25851 SDValue(N, 1).use_empty()) {
25853 EVT VT = N->getValueType(0);
25854 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
25855 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25856 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25857 DAG.getConstant(X86::COND_B, DL,
25860 DAG.getConstant(1, DL, VT));
25861 return DCI.CombineTo(N, Res1, CarryOut);
25867 // fold (add Y, (sete X, 0)) -> adc 0, Y
25868 // (add Y, (setne X, 0)) -> sbb -1, Y
25869 // (sub (sete X, 0), Y) -> sbb 0, Y
25870 // (sub (setne X, 0), Y) -> adc -1, Y
25871 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25874 // Look through ZExts.
25875 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25876 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25879 SDValue SetCC = Ext.getOperand(0);
25880 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25883 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25884 if (CC != X86::COND_E && CC != X86::COND_NE)
25887 SDValue Cmp = SetCC.getOperand(1);
25888 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25889 !X86::isZeroNode(Cmp.getOperand(1)) ||
25890 !Cmp.getOperand(0).getValueType().isInteger())
25893 SDValue CmpOp0 = Cmp.getOperand(0);
25894 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25895 DAG.getConstant(1, DL, CmpOp0.getValueType()));
25897 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25898 if (CC == X86::COND_NE)
25899 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25900 DL, OtherVal.getValueType(), OtherVal,
25901 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
25903 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25904 DL, OtherVal.getValueType(), OtherVal,
25905 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
25908 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25909 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25910 const X86Subtarget *Subtarget) {
25911 EVT VT = N->getValueType(0);
25912 SDValue Op0 = N->getOperand(0);
25913 SDValue Op1 = N->getOperand(1);
25915 // Try to synthesize horizontal adds from adds of shuffles.
25916 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25917 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25918 isHorizontalBinOp(Op0, Op1, true))
25919 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25921 return OptimizeConditionalInDecrement(N, DAG);
25924 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25925 const X86Subtarget *Subtarget) {
25926 SDValue Op0 = N->getOperand(0);
25927 SDValue Op1 = N->getOperand(1);
25929 // X86 can't encode an immediate LHS of a sub. See if we can push the
25930 // negation into a preceding instruction.
25931 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25932 // If the RHS of the sub is a XOR with one use and a constant, invert the
25933 // immediate. Then add one to the LHS of the sub so we can turn
25934 // X-Y -> X+~Y+1, saving one register.
25935 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25936 isa<ConstantSDNode>(Op1.getOperand(1))) {
25937 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25938 EVT VT = Op0.getValueType();
25939 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25941 DAG.getConstant(~XorC, SDLoc(Op1), VT));
25942 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25943 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
25947 // Try to synthesize horizontal adds from adds of shuffles.
25948 EVT VT = N->getValueType(0);
25949 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25950 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25951 isHorizontalBinOp(Op0, Op1, true))
25952 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25954 return OptimizeConditionalInDecrement(N, DAG);
25957 /// performVZEXTCombine - Performs build vector combines
25958 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25959 TargetLowering::DAGCombinerInfo &DCI,
25960 const X86Subtarget *Subtarget) {
25962 MVT VT = N->getSimpleValueType(0);
25963 SDValue Op = N->getOperand(0);
25964 MVT OpVT = Op.getSimpleValueType();
25965 MVT OpEltVT = OpVT.getVectorElementType();
25966 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25968 // (vzext (bitcast (vzext (x)) -> (vzext x)
25970 while (V.getOpcode() == ISD::BITCAST)
25971 V = V.getOperand(0);
25973 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25974 MVT InnerVT = V.getSimpleValueType();
25975 MVT InnerEltVT = InnerVT.getVectorElementType();
25977 // If the element sizes match exactly, we can just do one larger vzext. This
25978 // is always an exact type match as vzext operates on integer types.
25979 if (OpEltVT == InnerEltVT) {
25980 assert(OpVT == InnerVT && "Types must match for vzext!");
25981 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25984 // The only other way we can combine them is if only a single element of the
25985 // inner vzext is used in the input to the outer vzext.
25986 if (InnerEltVT.getSizeInBits() < InputBits)
25989 // In this case, the inner vzext is completely dead because we're going to
25990 // only look at bits inside of the low element. Just do the outer vzext on
25991 // a bitcast of the input to the inner.
25992 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
25995 // Check if we can bypass extracting and re-inserting an element of an input
25996 // vector. Essentially:
25997 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25998 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25999 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
26000 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
26001 SDValue ExtractedV = V.getOperand(0);
26002 SDValue OrigV = ExtractedV.getOperand(0);
26003 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
26004 if (ExtractIdx->getZExtValue() == 0) {
26005 MVT OrigVT = OrigV.getSimpleValueType();
26006 // Extract a subvector if necessary...
26007 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
26008 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
26009 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
26010 OrigVT.getVectorNumElements() / Ratio);
26011 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
26012 DAG.getIntPtrConstant(0, DL));
26014 Op = DAG.getBitcast(OpVT, OrigV);
26015 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
26022 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
26023 DAGCombinerInfo &DCI) const {
26024 SelectionDAG &DAG = DCI.DAG;
26025 switch (N->getOpcode()) {
26027 case ISD::EXTRACT_VECTOR_ELT:
26028 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
26031 case X86ISD::SHRUNKBLEND:
26032 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
26033 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
26034 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
26035 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
26036 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
26037 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
26038 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26041 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26042 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26043 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26044 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26045 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26046 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26047 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26048 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26049 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26050 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26051 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26052 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26054 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
26056 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26057 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26058 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26059 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26060 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26061 case ISD::ANY_EXTEND:
26062 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26063 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26064 case ISD::SIGN_EXTEND_INREG:
26065 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26066 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26067 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26068 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26069 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26070 case X86ISD::SHUFP: // Handle all target specific shuffles
26071 case X86ISD::PALIGNR:
26072 case X86ISD::UNPCKH:
26073 case X86ISD::UNPCKL:
26074 case X86ISD::MOVHLPS:
26075 case X86ISD::MOVLHPS:
26076 case X86ISD::PSHUFB:
26077 case X86ISD::PSHUFD:
26078 case X86ISD::PSHUFHW:
26079 case X86ISD::PSHUFLW:
26080 case X86ISD::MOVSS:
26081 case X86ISD::MOVSD:
26082 case X86ISD::VPERMILPI:
26083 case X86ISD::VPERM2X128:
26084 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26085 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26086 case X86ISD::INSERTPS: {
26087 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
26088 return PerformINSERTPSCombine(N, DAG, Subtarget);
26091 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26097 /// isTypeDesirableForOp - Return true if the target has native support for
26098 /// the specified value type and it is 'desirable' to use the type for the
26099 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26100 /// instruction encodings are longer and some i16 instructions are slow.
26101 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26102 if (!isTypeLegal(VT))
26104 if (VT != MVT::i16)
26111 case ISD::SIGN_EXTEND:
26112 case ISD::ZERO_EXTEND:
26113 case ISD::ANY_EXTEND:
26126 /// IsDesirableToPromoteOp - This method query the target whether it is
26127 /// beneficial for dag combiner to promote the specified node. If true, it
26128 /// should return the desired promotion type by reference.
26129 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26130 EVT VT = Op.getValueType();
26131 if (VT != MVT::i16)
26134 bool Promote = false;
26135 bool Commute = false;
26136 switch (Op.getOpcode()) {
26139 LoadSDNode *LD = cast<LoadSDNode>(Op);
26140 // If the non-extending load has a single use and it's not live out, then it
26141 // might be folded.
26142 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26143 Op.hasOneUse()*/) {
26144 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26145 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26146 // The only case where we'd want to promote LOAD (rather then it being
26147 // promoted as an operand is when it's only use is liveout.
26148 if (UI->getOpcode() != ISD::CopyToReg)
26155 case ISD::SIGN_EXTEND:
26156 case ISD::ZERO_EXTEND:
26157 case ISD::ANY_EXTEND:
26162 SDValue N0 = Op.getOperand(0);
26163 // Look out for (store (shl (load), x)).
26164 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26177 SDValue N0 = Op.getOperand(0);
26178 SDValue N1 = Op.getOperand(1);
26179 if (!Commute && MayFoldLoad(N1))
26181 // Avoid disabling potential load folding opportunities.
26182 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26184 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26194 //===----------------------------------------------------------------------===//
26195 // X86 Inline Assembly Support
26196 //===----------------------------------------------------------------------===//
26198 // Helper to match a string separated by whitespace.
26199 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
26200 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
26202 for (StringRef Piece : Pieces) {
26203 if (!S.startswith(Piece)) // Check if the piece matches.
26206 S = S.substr(Piece.size());
26207 StringRef::size_type Pos = S.find_first_not_of(" \t");
26208 if (Pos == 0) // We matched a prefix.
26217 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26219 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26220 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26221 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26222 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26224 if (AsmPieces.size() == 3)
26226 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26233 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26234 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26236 std::string AsmStr = IA->getAsmString();
26238 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26239 if (!Ty || Ty->getBitWidth() % 16 != 0)
26242 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26243 SmallVector<StringRef, 4> AsmPieces;
26244 SplitString(AsmStr, AsmPieces, ";\n");
26246 switch (AsmPieces.size()) {
26247 default: return false;
26249 // FIXME: this should verify that we are targeting a 486 or better. If not,
26250 // we will turn this bswap into something that will be lowered to logical
26251 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26252 // lower so don't worry about this.
26254 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
26255 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
26256 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
26257 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
26258 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
26259 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
26260 // No need to check constraints, nothing other than the equivalent of
26261 // "=r,0" would be valid here.
26262 return IntrinsicLowering::LowerToByteSwap(CI);
26265 // rorw $$8, ${0:w} --> llvm.bswap.i16
26266 if (CI->getType()->isIntegerTy(16) &&
26267 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26268 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
26269 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
26271 StringRef ConstraintsStr = IA->getConstraintString();
26272 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26273 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26274 if (clobbersFlagRegisters(AsmPieces))
26275 return IntrinsicLowering::LowerToByteSwap(CI);
26279 if (CI->getType()->isIntegerTy(32) &&
26280 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26281 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
26282 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
26283 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
26285 StringRef ConstraintsStr = IA->getConstraintString();
26286 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26287 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26288 if (clobbersFlagRegisters(AsmPieces))
26289 return IntrinsicLowering::LowerToByteSwap(CI);
26292 if (CI->getType()->isIntegerTy(64)) {
26293 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26294 if (Constraints.size() >= 2 &&
26295 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26296 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26297 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26298 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
26299 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
26300 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
26301 return IntrinsicLowering::LowerToByteSwap(CI);
26309 /// getConstraintType - Given a constraint letter, return the type of
26310 /// constraint it is for this target.
26311 X86TargetLowering::ConstraintType
26312 X86TargetLowering::getConstraintType(StringRef Constraint) const {
26313 if (Constraint.size() == 1) {
26314 switch (Constraint[0]) {
26325 return C_RegisterClass;
26349 return TargetLowering::getConstraintType(Constraint);
26352 /// Examine constraint type and operand type and determine a weight value.
26353 /// This object must already have been set up with the operand type
26354 /// and the current alternative constraint selected.
26355 TargetLowering::ConstraintWeight
26356 X86TargetLowering::getSingleConstraintMatchWeight(
26357 AsmOperandInfo &info, const char *constraint) const {
26358 ConstraintWeight weight = CW_Invalid;
26359 Value *CallOperandVal = info.CallOperandVal;
26360 // If we don't have a value, we can't do a match,
26361 // but allow it at the lowest weight.
26362 if (!CallOperandVal)
26364 Type *type = CallOperandVal->getType();
26365 // Look at the constraint type.
26366 switch (*constraint) {
26368 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26379 if (CallOperandVal->getType()->isIntegerTy())
26380 weight = CW_SpecificReg;
26385 if (type->isFloatingPointTy())
26386 weight = CW_SpecificReg;
26389 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26390 weight = CW_SpecificReg;
26394 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26395 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26396 weight = CW_Register;
26399 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26400 if (C->getZExtValue() <= 31)
26401 weight = CW_Constant;
26405 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26406 if (C->getZExtValue() <= 63)
26407 weight = CW_Constant;
26411 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26412 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26413 weight = CW_Constant;
26417 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26418 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26419 weight = CW_Constant;
26423 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26424 if (C->getZExtValue() <= 3)
26425 weight = CW_Constant;
26429 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26430 if (C->getZExtValue() <= 0xff)
26431 weight = CW_Constant;
26436 if (isa<ConstantFP>(CallOperandVal)) {
26437 weight = CW_Constant;
26441 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26442 if ((C->getSExtValue() >= -0x80000000LL) &&
26443 (C->getSExtValue() <= 0x7fffffffLL))
26444 weight = CW_Constant;
26448 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26449 if (C->getZExtValue() <= 0xffffffff)
26450 weight = CW_Constant;
26457 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26458 /// with another that has more specific requirements based on the type of the
26459 /// corresponding operand.
26460 const char *X86TargetLowering::
26461 LowerXConstraint(EVT ConstraintVT) const {
26462 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26463 // 'f' like normal targets.
26464 if (ConstraintVT.isFloatingPoint()) {
26465 if (Subtarget->hasSSE2())
26467 if (Subtarget->hasSSE1())
26471 return TargetLowering::LowerXConstraint(ConstraintVT);
26474 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26475 /// vector. If it is invalid, don't add anything to Ops.
26476 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26477 std::string &Constraint,
26478 std::vector<SDValue>&Ops,
26479 SelectionDAG &DAG) const {
26482 // Only support length 1 constraints for now.
26483 if (Constraint.length() > 1) return;
26485 char ConstraintLetter = Constraint[0];
26486 switch (ConstraintLetter) {
26489 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26490 if (C->getZExtValue() <= 31) {
26491 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26492 Op.getValueType());
26498 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26499 if (C->getZExtValue() <= 63) {
26500 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26501 Op.getValueType());
26507 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26508 if (isInt<8>(C->getSExtValue())) {
26509 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26510 Op.getValueType());
26516 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26517 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
26518 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
26519 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
26520 Op.getValueType());
26526 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26527 if (C->getZExtValue() <= 3) {
26528 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26529 Op.getValueType());
26535 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26536 if (C->getZExtValue() <= 255) {
26537 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26538 Op.getValueType());
26544 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26545 if (C->getZExtValue() <= 127) {
26546 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26547 Op.getValueType());
26553 // 32-bit signed value
26554 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26555 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26556 C->getSExtValue())) {
26557 // Widen to 64 bits here to get it sign extended.
26558 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
26561 // FIXME gcc accepts some relocatable values here too, but only in certain
26562 // memory models; it's complicated.
26567 // 32-bit unsigned value
26568 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26569 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26570 C->getZExtValue())) {
26571 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26572 Op.getValueType());
26576 // FIXME gcc accepts some relocatable values here too, but only in certain
26577 // memory models; it's complicated.
26581 // Literal immediates are always ok.
26582 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26583 // Widen to 64 bits here to get it sign extended.
26584 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
26588 // In any sort of PIC mode addresses need to be computed at runtime by
26589 // adding in a register or some sort of table lookup. These can't
26590 // be used as immediates.
26591 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26594 // If we are in non-pic codegen mode, we allow the address of a global (with
26595 // an optional displacement) to be used with 'i'.
26596 GlobalAddressSDNode *GA = nullptr;
26597 int64_t Offset = 0;
26599 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26601 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26602 Offset += GA->getOffset();
26604 } else if (Op.getOpcode() == ISD::ADD) {
26605 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26606 Offset += C->getZExtValue();
26607 Op = Op.getOperand(0);
26610 } else if (Op.getOpcode() == ISD::SUB) {
26611 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26612 Offset += -C->getZExtValue();
26613 Op = Op.getOperand(0);
26618 // Otherwise, this isn't something we can handle, reject it.
26622 const GlobalValue *GV = GA->getGlobal();
26623 // If we require an extra load to get this address, as in PIC mode, we
26624 // can't accept it.
26625 if (isGlobalStubReference(
26626 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26629 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26630 GA->getValueType(0), Offset);
26635 if (Result.getNode()) {
26636 Ops.push_back(Result);
26639 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26642 std::pair<unsigned, const TargetRegisterClass *>
26643 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
26644 StringRef Constraint,
26646 // First, see if this is a constraint that directly corresponds to an LLVM
26648 if (Constraint.size() == 1) {
26649 // GCC Constraint Letters
26650 switch (Constraint[0]) {
26652 // TODO: Slight differences here in allocation order and leaving
26653 // RIP in the class. Do they matter any more here than they do
26654 // in the normal allocation?
26655 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26656 if (Subtarget->is64Bit()) {
26657 if (VT == MVT::i32 || VT == MVT::f32)
26658 return std::make_pair(0U, &X86::GR32RegClass);
26659 if (VT == MVT::i16)
26660 return std::make_pair(0U, &X86::GR16RegClass);
26661 if (VT == MVT::i8 || VT == MVT::i1)
26662 return std::make_pair(0U, &X86::GR8RegClass);
26663 if (VT == MVT::i64 || VT == MVT::f64)
26664 return std::make_pair(0U, &X86::GR64RegClass);
26667 // 32-bit fallthrough
26668 case 'Q': // Q_REGS
26669 if (VT == MVT::i32 || VT == MVT::f32)
26670 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26671 if (VT == MVT::i16)
26672 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26673 if (VT == MVT::i8 || VT == MVT::i1)
26674 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26675 if (VT == MVT::i64)
26676 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26678 case 'r': // GENERAL_REGS
26679 case 'l': // INDEX_REGS
26680 if (VT == MVT::i8 || VT == MVT::i1)
26681 return std::make_pair(0U, &X86::GR8RegClass);
26682 if (VT == MVT::i16)
26683 return std::make_pair(0U, &X86::GR16RegClass);
26684 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26685 return std::make_pair(0U, &X86::GR32RegClass);
26686 return std::make_pair(0U, &X86::GR64RegClass);
26687 case 'R': // LEGACY_REGS
26688 if (VT == MVT::i8 || VT == MVT::i1)
26689 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26690 if (VT == MVT::i16)
26691 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26692 if (VT == MVT::i32 || !Subtarget->is64Bit())
26693 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26694 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26695 case 'f': // FP Stack registers.
26696 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26697 // value to the correct fpstack register class.
26698 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26699 return std::make_pair(0U, &X86::RFP32RegClass);
26700 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26701 return std::make_pair(0U, &X86::RFP64RegClass);
26702 return std::make_pair(0U, &X86::RFP80RegClass);
26703 case 'y': // MMX_REGS if MMX allowed.
26704 if (!Subtarget->hasMMX()) break;
26705 return std::make_pair(0U, &X86::VR64RegClass);
26706 case 'Y': // SSE_REGS if SSE2 allowed
26707 if (!Subtarget->hasSSE2()) break;
26709 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26710 if (!Subtarget->hasSSE1()) break;
26712 switch (VT.SimpleTy) {
26714 // Scalar SSE types.
26717 return std::make_pair(0U, &X86::FR32RegClass);
26720 return std::make_pair(0U, &X86::FR64RegClass);
26728 return std::make_pair(0U, &X86::VR128RegClass);
26736 return std::make_pair(0U, &X86::VR256RegClass);
26741 return std::make_pair(0U, &X86::VR512RegClass);
26747 // Use the default implementation in TargetLowering to convert the register
26748 // constraint into a member of a register class.
26749 std::pair<unsigned, const TargetRegisterClass*> Res;
26750 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
26752 // Not found as a standard register?
26754 // Map st(0) -> st(7) -> ST0
26755 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26756 tolower(Constraint[1]) == 's' &&
26757 tolower(Constraint[2]) == 't' &&
26758 Constraint[3] == '(' &&
26759 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26760 Constraint[5] == ')' &&
26761 Constraint[6] == '}') {
26763 Res.first = X86::FP0+Constraint[4]-'0';
26764 Res.second = &X86::RFP80RegClass;
26768 // GCC allows "st(0)" to be called just plain "st".
26769 if (StringRef("{st}").equals_lower(Constraint)) {
26770 Res.first = X86::FP0;
26771 Res.second = &X86::RFP80RegClass;
26776 if (StringRef("{flags}").equals_lower(Constraint)) {
26777 Res.first = X86::EFLAGS;
26778 Res.second = &X86::CCRRegClass;
26782 // 'A' means EAX + EDX.
26783 if (Constraint == "A") {
26784 Res.first = X86::EAX;
26785 Res.second = &X86::GR32_ADRegClass;
26791 // Otherwise, check to see if this is a register class of the wrong value
26792 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26793 // turn into {ax},{dx}.
26794 // MVT::Other is used to specify clobber names.
26795 if (Res.second->hasType(VT) || VT == MVT::Other)
26796 return Res; // Correct type already, nothing to do.
26798 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
26799 // return "eax". This should even work for things like getting 64bit integer
26800 // registers when given an f64 type.
26801 const TargetRegisterClass *Class = Res.second;
26802 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
26803 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
26804 unsigned Size = VT.getSizeInBits();
26805 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
26806 : Size == 16 ? MVT::i16
26807 : Size == 32 ? MVT::i32
26808 : Size == 64 ? MVT::i64
26810 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
26812 Res.first = DestReg;
26813 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
26814 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
26815 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
26816 : &X86::GR64RegClass;
26817 assert(Res.second->contains(Res.first) && "Register in register class");
26819 // No register found/type mismatch.
26821 Res.second = nullptr;
26823 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
26824 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
26825 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
26826 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
26827 Class == &X86::VR512RegClass) {
26828 // Handle references to XMM physical registers that got mapped into the
26829 // wrong class. This can happen with constraints like {xmm0} where the
26830 // target independent register mapper will just pick the first match it can
26831 // find, ignoring the required type.
26833 if (VT == MVT::f32 || VT == MVT::i32)
26834 Res.second = &X86::FR32RegClass;
26835 else if (VT == MVT::f64 || VT == MVT::i64)
26836 Res.second = &X86::FR64RegClass;
26837 else if (X86::VR128RegClass.hasType(VT))
26838 Res.second = &X86::VR128RegClass;
26839 else if (X86::VR256RegClass.hasType(VT))
26840 Res.second = &X86::VR256RegClass;
26841 else if (X86::VR512RegClass.hasType(VT))
26842 Res.second = &X86::VR512RegClass;
26844 // Type mismatch and not a clobber: Return an error;
26846 Res.second = nullptr;
26853 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
26854 const AddrMode &AM, Type *Ty,
26855 unsigned AS) const {
26856 // Scaling factors are not free at all.
26857 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26858 // will take 2 allocations in the out of order engine instead of 1
26859 // for plain addressing mode, i.e. inst (reg1).
26861 // vaddps (%rsi,%drx), %ymm0, %ymm1
26862 // Requires two allocations (one for the load, one for the computation)
26864 // vaddps (%rsi), %ymm0, %ymm1
26865 // Requires just 1 allocation, i.e., freeing allocations for other operations
26866 // and having less micro operations to execute.
26868 // For some X86 architectures, this is even worse because for instance for
26869 // stores, the complex addressing mode forces the instruction to use the
26870 // "load" ports instead of the dedicated "store" port.
26871 // E.g., on Haswell:
26872 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26873 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26874 if (isLegalAddressingMode(DL, AM, Ty, AS))
26875 // Scale represents reg2 * scale, thus account for 1
26876 // as soon as we use a second register.
26877 return AM.Scale != 0;
26881 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
26882 // Integer division on x86 is expensive. However, when aggressively optimizing
26883 // for code size, we prefer to use a div instruction, as it is usually smaller
26884 // than the alternative sequence.
26885 // The exception to this is vector division. Since x86 doesn't have vector
26886 // integer division, leaving the division as-is is a loss even in terms of
26887 // size, because it will have to be scalarized, while the alternative code
26888 // sequence can be performed in vector form.
26889 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
26890 Attribute::MinSize);
26891 return OptSize && !VT.isVector();