1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
29 // X86 Specific DAG Nodes
31 // Start the numbering where the builtin ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 /// BSF - Bit scan forward.
35 /// BSR - Bit scan reverse.
39 /// SHLD, SHRD - Double shift instructions. These correspond to
40 /// X86::SHLDxx and X86::SHRDxx instructions.
44 /// FAND - Bitwise logical AND of floating point values. This corresponds
45 /// to X86::ANDPS or X86::ANDPD.
48 /// FOR - Bitwise logical OR of floating point values. This corresponds
49 /// to X86::ORPS or X86::ORPD.
52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
53 /// to X86::XORPS or X86::XORPD.
56 /// FSRL - Bitwise logical right shift of floating point values. These
57 /// corresponds to X86::PSRLDQ.
60 /// CALL - These operations represent an abstract X86 call
61 /// instruction, which includes a bunch of information. In particular the
62 /// operands of these node are:
64 /// #0 - The incoming token chain
66 /// #2 - The number of arg bytes the caller pushes on the stack.
67 /// #3 - The number of arg bytes the callee pops off the stack.
68 /// #4 - The value to pass in AL/AX/EAX (optional)
69 /// #5 - The value to pass in DL/DX/EDX (optional)
71 /// The result values of these nodes are:
73 /// #0 - The outgoing token chain
74 /// #1 - The first register result value (optional)
75 /// #2 - The second register result value (optional)
79 /// RDTSC_DAG - This operation implements the lowering for
83 /// X86 compare and logical compare instructions.
86 /// X86 bit-test instructions.
89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
90 /// operand, usually produced by a CMP instruction.
93 // Same as SETCC except it's materialized with a sbb and the value is all
94 // one's or all zero's.
95 SETCC_CARRY, // R = carry_bit ? ~0 : 0
97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
98 /// Operands are two FP values to compare; result is a mask of
99 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
102 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
103 /// result in an integer GPR. Needs masking for scalar result.
106 /// X86 conditional moves. Operand 0 and operand 1 are the two values
107 /// to select from. Operand 2 is the condition code, and operand 3 is the
108 /// flag operand produced by a CMP or TEST instruction. It also writes a
112 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
113 /// is the block to branch if condition is true, operand 2 is the
114 /// condition code, and operand 3 is the flag operand produced by a CMP
115 /// or TEST instruction.
118 /// Return with a flag operand. Operand 0 is the chain operand, operand
119 /// 1 is the number of bytes of stack to pop.
122 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
125 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
128 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
129 /// at function entry, used for PIC code.
132 /// Wrapper - A wrapper node for TargetConstantPool,
133 /// TargetExternalSymbol, and TargetGlobalAddress.
136 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
137 /// relative displacements.
140 /// MOVQ2DQ - Copies a 64-bit value from an MMX vector to the low word
141 /// of an XMM vector, with the high word zero filled.
144 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
145 /// to an MMX vector. If you think this is too close to the previous
146 /// mnemonic, so do I; blame Intel.
149 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
150 /// i32, corresponds to X86::PEXTRB.
153 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
154 /// i32, corresponds to X86::PEXTRW.
157 /// INSERTPS - Insert any element of a 4 x float vector into any element
158 /// of a destination 4 x floatvector.
161 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
162 /// corresponds to X86::PINSRB.
165 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
166 /// corresponds to X86::PINSRW.
169 /// PSHUFB - Shuffle 16 8-bit values within a vector.
172 /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
175 /// PSIGN - Copy integer sign.
178 /// BLEND family of opcodes
181 /// HADD - Integer horizontal add.
184 /// HSUB - Integer horizontal sub.
187 /// FHADD - Floating point horizontal add.
190 /// FHSUB - Floating point horizontal sub.
193 /// FMAX, FMIN - Floating point max and min.
197 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
198 /// approximation. Note that these typically require refinement
199 /// in order to obtain suitable precision.
202 // TLSADDR - Thread Local Storage.
205 // TLSCALL - Thread Local Storage. When calling to an OS provided
206 // thunk at the address from an earlier relocation.
209 // EH_RETURN - Exception Handling helpers.
212 /// TC_RETURN - Tail call return.
214 /// operand #1 callee (register or absolute)
215 /// operand #2 stack adjustment
216 /// operand #3 optional in flag
219 // VZEXT_MOVL - Vector move low and zero extend.
222 // VSHL, VSRL - 128-bit vector logical left / right shift
225 // VSHL, VSRL, VSRA - Vector shift elements
228 // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate
231 // CMPPD, CMPPS - Vector double/float comparison.
232 // CMPPD, CMPPS - Vector double/float comparison.
235 // PCMP* - Vector integer comparisons.
238 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
239 ADD, SUB, ADC, SBB, SMUL,
240 INC, DEC, OR, XOR, AND,
242 ANDN, // ANDN - Bitwise AND NOT with FLAGS results.
244 BLSI, // BLSI - Extract lowest set isolated bit
245 BLSMSK, // BLSMSK - Get mask up to lowest set bit
246 BLSR, // BLSR - Reset lowest set bit
248 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
250 // MUL_IMM - X86 specific multiply by immediate.
253 // PTEST - Vector bitwise comparisons
256 // TESTP - Vector packed fp sign bitwise comparisons
259 // Several flavors of instructions with vector shuffle behaviors.
281 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
282 // according to %al. An operator is needed so that this can be expanded
283 // with control flow.
284 VASTART_SAVE_XMM_REGS,
286 // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
289 // SEG_ALLOCA - For allocating variable amounts of stack space when using
290 // segmented stacks. Check if the current stacklet has enough space, and
291 // falls back to heap allocation if not.
300 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
301 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
302 // Atomic 64-bit binary operations.
303 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
311 // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
316 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
319 // FNSTCW16m - Store FP control world into i16 memory.
322 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
323 /// integer destination in memory and a FP reg source. This corresponds
324 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
325 /// has two inputs (token chain and address) and two outputs (int value
326 /// and token chain).
331 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
332 /// integer source in memory and FP reg result. This corresponds to the
333 /// X86::FILD*m instructions. It has three inputs (token chain, address,
334 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
335 /// also produces a flag).
339 /// FLD - This instruction implements an extending load to FP stack slots.
340 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
341 /// operand, ptr to load from, and a ValueType node indicating the type
345 /// FST - This instruction implements a truncating store to FP stack
346 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
347 /// chain operand, value to store, address, and a ValueType to store it
351 /// VAARG_64 - This instruction grabs the address of the next argument
352 /// from a va_list. (reads and modifies the va_list in memory)
355 // WARNING: Do not add anything in the end unless you want the node to
356 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
357 // thought as target memory ops!
361 /// Define some predicates that are used for node matching.
363 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
364 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
365 bool isPSHUFDMask(ShuffleVectorSDNode *N);
367 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
368 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
369 bool isPSHUFHWMask(ShuffleVectorSDNode *N);
371 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
372 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
373 bool isPSHUFLWMask(ShuffleVectorSDNode *N);
375 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
376 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
377 bool isSHUFPMask(ShuffleVectorSDNode *N, bool HasAVX);
379 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
380 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
381 bool isMOVHLPSMask(ShuffleVectorSDNode *N);
383 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
384 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
386 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N);
388 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
389 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}.
390 bool isMOVLPMask(ShuffleVectorSDNode *N);
392 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
393 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}.
394 /// as well as MOVLHPS.
395 bool isMOVLHPSMask(ShuffleVectorSDNode *N);
397 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
398 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
399 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool HasAVX2,
400 bool V2IsSplat = false);
402 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
403 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
404 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool HasAVX2,
405 bool V2IsSplat = false);
407 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
408 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
410 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2);
412 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
413 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
415 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2);
417 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
418 /// specifies a shuffle of elements that is suitable for input to MOVSS,
419 /// MOVSD, and MOVD, i.e. setting the lowest element.
420 bool isMOVLMask(ShuffleVectorSDNode *N);
422 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
423 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
424 bool isMOVSHDUPMask(ShuffleVectorSDNode *N, const X86Subtarget *Subtarget);
426 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
427 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
428 bool isMOVSLDUPMask(ShuffleVectorSDNode *N, const X86Subtarget *Subtarget);
430 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
431 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
432 bool isMOVDDUPMask(ShuffleVectorSDNode *N);
434 /// isVEXTRACTF128Index - Return true if the specified
435 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
436 /// suitable for input to VEXTRACTF128.
437 bool isVEXTRACTF128Index(SDNode *N);
439 /// isVINSERTF128Index - Return true if the specified
440 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
441 /// suitable for input to VINSERTF128.
442 bool isVINSERTF128Index(SDNode *N);
444 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
445 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
446 /// instructions. Handles 128-bit and 256-bit.
447 unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N);
449 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
450 /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction.
451 unsigned getShufflePSHUFHWImmediate(SDNode *N);
453 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
454 /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction.
455 unsigned getShufflePSHUFLWImmediate(SDNode *N);
457 /// getExtractVEXTRACTF128Immediate - Return the appropriate
458 /// immediate to extract the specified EXTRACT_SUBVECTOR index
459 /// with VEXTRACTF128 instructions.
460 unsigned getExtractVEXTRACTF128Immediate(SDNode *N);
462 /// getInsertVINSERTF128Immediate - Return the appropriate
463 /// immediate to insert at the specified INSERT_SUBVECTOR index
464 /// with VINSERTF128 instructions.
465 unsigned getInsertVINSERTF128Immediate(SDNode *N);
467 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
469 bool isZeroNode(SDValue Elt);
471 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
472 /// fit into displacement field of the instruction.
473 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
474 bool hasSymbolicDisplacement = true);
477 /// isCalleePop - Determines whether the callee is required to pop its
478 /// own arguments. Callee pop is necessary to support tail calls.
479 bool isCalleePop(CallingConv::ID CallingConv,
480 bool is64Bit, bool IsVarArg, bool TailCallOpt);
483 //===--------------------------------------------------------------------===//
484 // X86TargetLowering - X86 Implementation of the TargetLowering interface
485 class X86TargetLowering : public TargetLowering {
487 explicit X86TargetLowering(X86TargetMachine &TM);
489 virtual unsigned getJumpTableEncoding() const;
491 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
493 virtual const MCExpr *
494 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
495 const MachineBasicBlock *MBB, unsigned uid,
496 MCContext &Ctx) const;
498 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
500 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
501 SelectionDAG &DAG) const;
502 virtual const MCExpr *
503 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
504 unsigned JTI, MCContext &Ctx) const;
506 /// getStackPtrReg - Return the stack pointer register we are using: either
508 unsigned getStackPtrReg() const { return X86StackPtr; }
510 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
511 /// function arguments in the caller parameter area. For X86, aggregates
512 /// that contains are placed at 16-byte boundaries while the rest are at
513 /// 4-byte boundaries.
514 virtual unsigned getByValTypeAlignment(Type *Ty) const;
516 /// getOptimalMemOpType - Returns the target specific optimal type for load
517 /// and store operations as a result of memset, memcpy, and memmove
518 /// lowering. If DstAlign is zero that means it's safe to destination
519 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
520 /// means there isn't a need to check it against alignment requirement,
521 /// probably because the source does not need to be loaded. If
522 /// 'IsZeroVal' is true, that means it's safe to return a
523 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
524 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
525 /// constant so it does not need to be loaded.
526 /// It returns EVT::Other if the type should be determined using generic
527 /// target-independent logic.
529 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
530 bool IsZeroVal, bool MemcpyStrSrc,
531 MachineFunction &MF) const;
533 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
534 /// unaligned memory accesses. of the specified type.
535 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
539 /// LowerOperation - Provide custom lowering hooks for some operations.
541 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
543 /// ReplaceNodeResults - Replace the results of node with an illegal result
544 /// type with new values built out of custom code.
546 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
547 SelectionDAG &DAG) const;
550 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
552 /// isTypeDesirableForOp - Return true if the target has native support for
553 /// the specified value type and it is 'desirable' to use the type for the
554 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
555 /// instruction encodings are longer and some i16 instructions are slow.
556 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
558 /// isTypeDesirable - Return true if the target has native support for the
559 /// specified value type and it is 'desirable' to use the type. e.g. On x86
560 /// i16 is legal, but undesirable since i16 instruction encodings are longer
561 /// and some i16 instructions are slow.
562 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
564 virtual MachineBasicBlock *
565 EmitInstrWithCustomInserter(MachineInstr *MI,
566 MachineBasicBlock *MBB) const;
569 /// getTargetNodeName - This method returns the name of a target specific
571 virtual const char *getTargetNodeName(unsigned Opcode) const;
573 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
574 virtual EVT getSetCCResultType(EVT VT) const;
576 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
577 /// in Mask are known to be either zero or one and return them in the
578 /// KnownZero/KnownOne bitsets.
579 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
583 const SelectionDAG &DAG,
584 unsigned Depth = 0) const;
586 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
587 // operation that are sign bits.
588 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
589 unsigned Depth) const;
592 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
594 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
596 virtual bool ExpandInlineAsm(CallInst *CI) const;
598 ConstraintType getConstraintType(const std::string &Constraint) const;
600 /// Examine constraint string and operand type and determine a weight value.
601 /// The operand object must already have been set up with the operand type.
602 virtual ConstraintWeight getSingleConstraintMatchWeight(
603 AsmOperandInfo &info, const char *constraint) const;
605 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
607 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
608 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
609 /// true it means one of the asm constraint of the inline asm instruction
610 /// being processed is 'm'.
611 virtual void LowerAsmOperandForConstraint(SDValue Op,
612 std::string &Constraint,
613 std::vector<SDValue> &Ops,
614 SelectionDAG &DAG) const;
616 /// getRegForInlineAsmConstraint - Given a physical register constraint
617 /// (e.g. {edx}), return the register number and the register class for the
618 /// register. This should only be used for C_Register constraints. On
619 /// error, this returns a register number of 0.
620 std::pair<unsigned, const TargetRegisterClass*>
621 getRegForInlineAsmConstraint(const std::string &Constraint,
624 /// isLegalAddressingMode - Return true if the addressing mode represented
625 /// by AM is legal for this target, for a load/store of the specified type.
626 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
628 /// isTruncateFree - Return true if it's free to truncate a value of
629 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
630 /// register EAX to i16 by referencing its sub-register AX.
631 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
632 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
634 /// isZExtFree - Return true if any actual instruction that defines a
635 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
636 /// register. This does not necessarily include registers defined in
637 /// unknown ways, such as incoming arguments, or copies from unknown
638 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
639 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
640 /// all instructions that define 32-bit values implicit zero-extend the
641 /// result out to 64 bits.
642 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
643 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
645 /// isNarrowingProfitable - Return true if it's profitable to narrow
646 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
647 /// from i32 to i8 but not from i32 to i16.
648 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
650 /// isFPImmLegal - Returns true if the target can instruction select the
651 /// specified FP immediate natively. If false, the legalizer will
652 /// materialize the FP immediate as a load from a constant pool.
653 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
655 /// isShuffleMaskLegal - Targets can use this to indicate that they only
656 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
657 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
658 /// values are assumed to be legal.
659 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
662 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
663 /// used by Targets can use this to indicate if there is a suitable
664 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
666 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
669 /// ShouldShrinkFPConstant - If true, then instruction selection should
670 /// seek to shrink the FP constant of the specified type to a smaller type
671 /// in order to save space and / or reduce runtime.
672 virtual bool ShouldShrinkFPConstant(EVT VT) const {
673 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
674 // expensive than a straight movsd. On the other hand, it's important to
675 // shrink long double fp constant since fldt is very slow.
676 return !X86ScalarSSEf64 || VT == MVT::f80;
679 const X86Subtarget* getSubtarget() const {
683 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
684 /// computed in an SSE register, not on the X87 floating point stack.
685 bool isScalarFPTypeInSSEReg(EVT VT) const {
686 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
687 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
690 /// createFastISel - This method returns a target specific FastISel object,
691 /// or null if the target does not support "fast" ISel.
692 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
694 /// getStackCookieLocation - Return true if the target stores stack
695 /// protector cookies at a fixed offset in some non-standard address
696 /// space, and populates the address space and offset as
698 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
700 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
701 SelectionDAG &DAG) const;
704 std::pair<const TargetRegisterClass*, uint8_t>
705 findRepresentativeClass(EVT VT) const;
708 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
709 /// make the right decision when generating code for different targets.
710 const X86Subtarget *Subtarget;
711 const X86RegisterInfo *RegInfo;
712 const TargetData *TD;
714 /// X86StackPtr - X86 physical register used as stack ptr.
715 unsigned X86StackPtr;
717 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
718 /// floating point ops.
719 /// When SSE is available, use it for f32 operations.
720 /// When SSE2 is available, use it for f64 operations.
721 bool X86ScalarSSEf32;
722 bool X86ScalarSSEf64;
724 /// LegalFPImmediates - A list of legal fp immediates.
725 std::vector<APFloat> LegalFPImmediates;
727 /// addLegalFPImmediate - Indicate that this x86 target can instruction
728 /// select the specified FP immediate natively.
729 void addLegalFPImmediate(const APFloat& Imm) {
730 LegalFPImmediates.push_back(Imm);
733 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
734 CallingConv::ID CallConv, bool isVarArg,
735 const SmallVectorImpl<ISD::InputArg> &Ins,
736 DebugLoc dl, SelectionDAG &DAG,
737 SmallVectorImpl<SDValue> &InVals) const;
738 SDValue LowerMemArgument(SDValue Chain,
739 CallingConv::ID CallConv,
740 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
741 DebugLoc dl, SelectionDAG &DAG,
742 const CCValAssign &VA, MachineFrameInfo *MFI,
744 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
745 DebugLoc dl, SelectionDAG &DAG,
746 const CCValAssign &VA,
747 ISD::ArgFlagsTy Flags) const;
749 // Call lowering helpers.
751 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
752 /// for tail call optimization. Targets which want to do tail call
753 /// optimization should implement this function.
754 bool IsEligibleForTailCallOptimization(SDValue Callee,
755 CallingConv::ID CalleeCC,
757 bool isCalleeStructRet,
758 bool isCallerStructRet,
759 const SmallVectorImpl<ISD::OutputArg> &Outs,
760 const SmallVectorImpl<SDValue> &OutVals,
761 const SmallVectorImpl<ISD::InputArg> &Ins,
762 SelectionDAG& DAG) const;
763 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
764 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
765 SDValue Chain, bool IsTailCall, bool Is64Bit,
766 int FPDiff, DebugLoc dl) const;
768 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
769 SelectionDAG &DAG) const;
771 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
772 bool isSigned) const;
774 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
775 SelectionDAG &DAG) const;
776 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
777 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
778 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
779 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
780 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
781 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
782 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
783 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
784 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
785 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
786 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
787 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
788 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
789 int64_t Offset, SelectionDAG &DAG) const;
790 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
791 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
792 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
793 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
794 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const;
795 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
796 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
797 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
798 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
799 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
800 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
801 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
802 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
803 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
804 SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const;
805 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
806 DebugLoc dl, SelectionDAG &DAG) const;
807 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
808 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
809 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
810 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
811 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
812 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
813 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
814 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
815 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
816 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
817 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
818 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
819 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
820 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
821 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
822 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
823 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
824 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
825 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
826 SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const;
827 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
828 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
829 SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) const;
830 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
831 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
832 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
834 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
835 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
836 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
837 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const;
838 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
839 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
841 // Utility functions to help LowerVECTOR_SHUFFLE
842 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const;
845 LowerFormalArguments(SDValue Chain,
846 CallingConv::ID CallConv, bool isVarArg,
847 const SmallVectorImpl<ISD::InputArg> &Ins,
848 DebugLoc dl, SelectionDAG &DAG,
849 SmallVectorImpl<SDValue> &InVals) const;
851 LowerCall(SDValue Chain, SDValue Callee,
852 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
853 const SmallVectorImpl<ISD::OutputArg> &Outs,
854 const SmallVectorImpl<SDValue> &OutVals,
855 const SmallVectorImpl<ISD::InputArg> &Ins,
856 DebugLoc dl, SelectionDAG &DAG,
857 SmallVectorImpl<SDValue> &InVals) const;
860 LowerReturn(SDValue Chain,
861 CallingConv::ID CallConv, bool isVarArg,
862 const SmallVectorImpl<ISD::OutputArg> &Outs,
863 const SmallVectorImpl<SDValue> &OutVals,
864 DebugLoc dl, SelectionDAG &DAG) const;
866 virtual bool isUsedByReturnOnly(SDNode *N) const;
868 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
871 getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
872 ISD::NodeType ExtendKind) const;
875 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
877 const SmallVectorImpl<ISD::OutputArg> &Outs,
878 LLVMContext &Context) const;
880 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
881 SelectionDAG &DAG, unsigned NewOp) const;
883 /// Utility function to emit string processing sse4.2 instructions
884 /// that return in xmm0.
885 /// This takes the instruction to expand, the associated machine basic
886 /// block, the number of args, and whether or not the second arg is
887 /// in memory or not.
888 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
889 unsigned argNum, bool inMem) const;
891 /// Utility functions to emit monitor and mwait instructions. These
892 /// need to make sure that the arguments to the intrinsic are in the
893 /// correct registers.
894 MachineBasicBlock *EmitMonitor(MachineInstr *MI,
895 MachineBasicBlock *BB) const;
896 MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const;
898 /// Utility function to emit atomic bitwise operations (and, or, xor).
899 /// It takes the bitwise instruction to expand, the associated machine basic
900 /// block, and the associated X86 opcodes for reg/reg and reg/imm.
901 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
902 MachineInstr *BInstr,
903 MachineBasicBlock *BB,
910 TargetRegisterClass *RC,
911 bool invSrc = false) const;
913 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
914 MachineInstr *BInstr,
915 MachineBasicBlock *BB,
920 bool invSrc = false) const;
922 /// Utility function to emit atomic min and max. It takes the min/max
923 /// instruction to expand, the associated basic block, and the associated
924 /// cmov opcode for moving the min or max value.
925 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
926 MachineBasicBlock *BB,
927 unsigned cmovOpc) const;
929 // Utility function to emit the low-level va_arg code for X86-64.
930 MachineBasicBlock *EmitVAARG64WithCustomInserter(
932 MachineBasicBlock *MBB) const;
934 /// Utility function to emit the xmm reg save portion of va_start.
935 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
936 MachineInstr *BInstr,
937 MachineBasicBlock *BB) const;
939 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
940 MachineBasicBlock *BB) const;
942 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
943 MachineBasicBlock *BB) const;
945 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
946 MachineBasicBlock *BB,
949 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
950 MachineBasicBlock *BB) const;
952 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
953 MachineBasicBlock *BB) const;
955 /// Emit nodes that will be selected as "test Op0,Op0", or something
956 /// equivalent, for use with the given x86 condition code.
957 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
959 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
960 /// equivalent, for use with the given x86 condition code.
961 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
962 SelectionDAG &DAG) const;
966 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
970 #endif // X86ISELLOWERING_H