1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
27 // X86 Specific DAG Nodes
29 // Start the numbering where the builtin ops leave off.
30 FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
32 /// BSF - Bit scan forward.
33 /// BSR - Bit scan reverse.
37 /// SHLD, SHRD - Double shift instructions. These correspond to
38 /// X86::SHLDxx and X86::SHRDxx instructions.
42 /// FAND - Bitwise logical AND of floating point values. This corresponds
43 /// to X86::ANDPS or X86::ANDPD.
46 /// FOR - Bitwise logical OR of floating point values. This corresponds
47 /// to X86::ORPS or X86::ORPD.
50 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
51 /// to X86::XORPS or X86::XORPD.
54 /// FSRL - Bitwise logical right shift of floating point values. These
55 /// corresponds to X86::PSRLDQ.
58 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
59 /// integer source in memory and FP reg result. This corresponds to the
60 /// X86::FILD*m instructions. It has three inputs (token chain, address,
61 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
62 /// also produces a flag).
66 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
67 /// integer destination in memory and a FP reg source. This corresponds
68 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
69 /// has two inputs (token chain and address) and two outputs (int value
75 /// FLD - This instruction implements an extending load to FP stack slots.
76 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
77 /// operand, ptr to load from, and a ValueType node indicating the type
81 /// FST - This instruction implements a truncating store to FP stack
82 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
83 /// chain operand, value to store, address, and a ValueType to store it
87 /// CALL/TAILCALL - These operations represent an abstract X86 call
88 /// instruction, which includes a bunch of information. In particular the
89 /// operands of these node are:
91 /// #0 - The incoming token chain
93 /// #2 - The number of arg bytes the caller pushes on the stack.
94 /// #3 - The number of arg bytes the callee pops off the stack.
95 /// #4 - The value to pass in AL/AX/EAX (optional)
96 /// #5 - The value to pass in DL/DX/EDX (optional)
98 /// The result values of these nodes are:
100 /// #0 - The outgoing token chain
101 /// #1 - The first register result value (optional)
102 /// #2 - The second register result value (optional)
104 /// The CALL vs TAILCALL distinction boils down to whether the callee is
105 /// known not to modify the caller's stack frame, as is standard with
110 /// RDTSC_DAG - This operation implements the lowering for
114 /// X86 compare and logical compare instructions.
117 /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
118 /// operand produced by a CMP instruction.
121 /// X86 conditional moves. Operand 1 and operand 2 are the two values
122 /// to select from (operand 1 is a R/W operand). Operand 3 is the
123 /// condition code, and operand 4 is the flag operand produced by a CMP
124 /// or TEST instruction. It also writes a flag result.
127 /// X86 conditional branches. Operand 1 is the chain operand, operand 2
128 /// is the block to branch if condition is true, operand 3 is the
129 /// condition code, and operand 4 is the flag operand produced by a CMP
130 /// or TEST instruction.
133 /// Return with a flag operand. Operand 1 is the chain operand, operand
134 /// 2 is the number of bytes of stack to pop.
137 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
140 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
143 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
144 /// at function entry, used for PIC code.
147 /// Wrapper - A wrapper node for TargetConstantPool,
148 /// TargetExternalSymbol, and TargetGlobalAddress.
151 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
152 /// relative displacements.
155 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
156 /// i32, corresponds to X86::PEXTRB.
159 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
160 /// i32, corresponds to X86::PEXTRW.
163 /// INSERTPS - Insert any element of a 4 x float vector into any element
164 /// of a destination 4 x floatvector.
167 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
168 /// corresponds to X86::PINSRB.
171 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
172 /// corresponds to X86::PINSRW.
175 /// FMAX, FMIN - Floating point max and min.
179 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
180 /// approximation. Note that these typically require refinement
181 /// in order to obtain suitable precision.
184 // TLSADDR, THREAThread - Thread Local Storage.
185 TLSADDR, THREAD_POINTER,
187 // EH_RETURN - Exception Handling helpers.
190 /// TC_RETURN - Tail call return.
192 /// operand #1 callee (register or absolute)
193 /// operand #2 stack adjustment
194 /// operand #3 optional in flag
197 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
201 // FNSTCW16m - Store FP control world into i16 memory.
204 // VZEXT_MOVL - Vector move low and zero extend.
207 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
210 // VSHL, VSRL - Vector logical left / right shift.
215 /// Define some predicates that are used for node matching.
217 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
218 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
219 bool isPSHUFDMask(SDNode *N);
221 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
222 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
223 bool isPSHUFHWMask(SDNode *N);
225 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
226 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
227 bool isPSHUFLWMask(SDNode *N);
229 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
230 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
231 bool isSHUFPMask(SDNode *N);
233 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
234 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
235 bool isMOVHLPSMask(SDNode *N);
237 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
238 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
240 bool isMOVHLPS_v_undef_Mask(SDNode *N);
242 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
243 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
244 bool isMOVLPMask(SDNode *N);
246 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
247 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
248 /// as well as MOVLHPS.
249 bool isMOVHPMask(SDNode *N);
251 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
252 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
253 bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false);
255 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
256 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
257 bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false);
259 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
260 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
262 bool isUNPCKL_v_undef_Mask(SDNode *N);
264 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
265 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
267 bool isUNPCKH_v_undef_Mask(SDNode *N);
269 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
270 /// specifies a shuffle of elements that is suitable for input to MOVSS,
271 /// MOVSD, and MOVD, i.e. setting the lowest element.
272 bool isMOVLMask(SDNode *N);
274 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
275 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
276 bool isMOVSHDUPMask(SDNode *N);
278 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
279 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
280 bool isMOVSLDUPMask(SDNode *N);
282 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
283 /// specifies a splat of a single element.
284 bool isSplatMask(SDNode *N);
286 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
287 /// specifies a splat of zero element.
288 bool isSplatLoMask(SDNode *N);
290 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
291 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
293 unsigned getShuffleSHUFImmediate(SDNode *N);
295 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
296 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
298 unsigned getShufflePSHUFHWImmediate(SDNode *N);
300 /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
301 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
303 unsigned getShufflePSHUFLWImmediate(SDNode *N);
306 //===--------------------------------------------------------------------===//
307 // X86TargetLowering - X86 Implementation of the TargetLowering interface
308 class X86TargetLowering : public TargetLowering {
309 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
310 int RegSaveFrameIndex; // X86-64 vararg func register save area.
311 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
312 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
313 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
314 int BytesCallerReserves; // Number of arg bytes caller makes.
317 explicit X86TargetLowering(X86TargetMachine &TM);
319 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
321 SDOperand getPICJumpTableRelocBase(SDOperand Table,
322 SelectionDAG &DAG) const;
324 // Return the number of bytes that a function should pop when it returns (in
325 // addition to the space used by the return address).
327 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
329 // Return the number of bytes that the caller reserves for arguments passed
331 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
333 /// getStackPtrReg - Return the stack pointer register we are using: either
335 unsigned getStackPtrReg() const { return X86StackPtr; }
337 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
338 /// function arguments in the caller parameter area. For X86, aggregates
339 /// that contains are placed at 16-byte boundaries while the rest are at
340 /// 4-byte boundaries.
341 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
343 /// getOptimalMemOpType - Returns the target specific optimal type for load
344 /// and store operations as a result of memset, memcpy, and memmove
345 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
348 MVT::ValueType getOptimalMemOpType(uint64_t Size, unsigned Align,
349 bool isSrcConst, bool isSrcStr) const;
351 /// LowerOperation - Provide custom lowering hooks for some operations.
353 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
355 /// ExpandOperation - Custom lower the specified operation, splitting the
356 /// value into two pieces.
358 virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG);
361 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
363 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
364 MachineBasicBlock *MBB);
367 /// getTargetNodeName - This method returns the name of a target specific
369 virtual const char *getTargetNodeName(unsigned Opcode) const;
371 /// getSetCCResultType - Return the ISD::SETCC ValueType
372 virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
374 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
375 /// in Mask are known to be either zero or one and return them in the
376 /// KnownZero/KnownOne bitsets.
377 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
381 const SelectionDAG &DAG,
382 unsigned Depth = 0) const;
385 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
387 SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
389 ConstraintType getConstraintType(const std::string &Constraint) const;
391 std::vector<unsigned>
392 getRegClassForInlineAsmConstraint(const std::string &Constraint,
393 MVT::ValueType VT) const;
395 virtual const char *LowerXConstraint(MVT::ValueType ConstraintVT) const;
397 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
398 /// vector. If it is invalid, don't add anything to Ops.
399 virtual void LowerAsmOperandForConstraint(SDOperand Op,
400 char ConstraintLetter,
401 std::vector<SDOperand> &Ops,
402 SelectionDAG &DAG) const;
404 /// getRegForInlineAsmConstraint - Given a physical register constraint
405 /// (e.g. {edx}), return the register number and the register class for the
406 /// register. This should only be used for C_Register constraints. On
407 /// error, this returns a register number of 0.
408 std::pair<unsigned, const TargetRegisterClass*>
409 getRegForInlineAsmConstraint(const std::string &Constraint,
410 MVT::ValueType VT) const;
412 /// isLegalAddressingMode - Return true if the addressing mode represented
413 /// by AM is legal for this target, for a load/store of the specified type.
414 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
416 /// isTruncateFree - Return true if it's free to truncate a value of
417 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
418 /// register EAX to i16 by referencing its sub-register AX.
419 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
420 virtual bool isTruncateFree(MVT::ValueType VT1, MVT::ValueType VT2) const;
422 /// isShuffleMaskLegal - Targets can use this to indicate that they only
423 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
424 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
425 /// values are assumed to be legal.
426 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
428 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
429 /// used by Targets can use this to indicate if there is a suitable
430 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
432 virtual bool isVectorClearMaskLegal(const std::vector<SDOperand> &BVOps,
434 SelectionDAG &DAG) const;
436 /// ShouldShrinkFPConstant - If true, then instruction selection should
437 /// seek to shrink the FP constant of the specified type to a smaller type
438 /// in order to save space and / or reduce runtime.
439 virtual bool ShouldShrinkFPConstant(MVT::ValueType VT) const {
440 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
441 // expensive than a straight movsd. On the other hand, it's important to
442 // shrink long double fp constant since fldt is very slow.
443 return !X86ScalarSSEf64 || VT == MVT::f80;
446 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
447 /// for tail call optimization. Target which want to do tail call
448 /// optimization should implement this function.
449 virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
451 SelectionDAG &DAG) const;
453 virtual const X86Subtarget* getSubtarget() {
457 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
458 /// computed in an SSE register, not on the X87 floating point stack.
459 bool isScalarFPTypeInSSEReg(MVT::ValueType VT) const {
460 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
461 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
465 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
466 /// make the right decision when generating code for different targets.
467 const X86Subtarget *Subtarget;
468 const X86RegisterInfo *RegInfo;
470 /// X86StackPtr - X86 physical register used as stack ptr.
471 unsigned X86StackPtr;
473 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
474 /// floating point ops.
475 /// When SSE is available, use it for f32 operations.
476 /// When SSE2 is available, use it for f64 operations.
477 bool X86ScalarSSEf32;
478 bool X86ScalarSSEf64;
480 SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall,
481 unsigned CallingConv, SelectionDAG &DAG);
483 SDOperand LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
484 const CCValAssign &VA, MachineFrameInfo *MFI,
485 unsigned CC, SDOperand Root, unsigned i);
487 SDOperand LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
488 const SDOperand &StackPtr,
489 const CCValAssign &VA, SDOperand Chain,
492 // Call lowering helpers.
493 bool IsCalleePop(SDOperand Op);
494 bool CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall);
495 bool CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall);
496 SDOperand EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDOperand &OutRetAddr,
497 SDOperand Chain, bool IsTailCall, bool Is64Bit,
500 CCAssignFn *CCAssignFnForNode(SDOperand Op) const;
501 NameDecorationStyle NameDecorationForFORMAL_ARGUMENTS(SDOperand Op);
502 unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG);
504 std::pair<SDOperand,SDOperand> FP_TO_SINTHelper(SDOperand Op,
507 SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
508 SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
509 SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
510 SDOperand LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG);
511 SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
512 SDOperand LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG);
513 SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
514 SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
515 SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
516 SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
517 SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG);
518 SDOperand LowerShift(SDOperand Op, SelectionDAG &DAG);
519 SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
520 SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
521 SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
522 SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
523 SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG);
524 SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
525 SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
526 SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
527 SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
528 SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
529 SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
530 SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
531 SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG);
532 SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
533 SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
534 SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG);
535 SDOperand LowerVACOPY(SDOperand Op, SelectionDAG &DAG);
536 SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
537 SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
538 SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
539 SDOperand LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, SelectionDAG &DAG);
540 SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG);
541 SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG);
542 SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG);
543 SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG);
544 SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG);
545 SDOperand LowerLCS(SDOperand Op, SelectionDAG &DAG);
546 SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
547 SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG);
548 SDNode *ExpandATOMIC_LCS(SDNode *N, SelectionDAG &DAG);
549 SDNode *ExpandATOMIC_LSS(SDNode *N, SelectionDAG &DAG);
551 SDOperand EmitTargetCodeForMemset(SelectionDAG &DAG,
553 SDOperand Dst, SDOperand Src,
554 SDOperand Size, unsigned Align,
555 const Value *DstSV, uint64_t DstSVOff);
556 SDOperand EmitTargetCodeForMemcpy(SelectionDAG &DAG,
558 SDOperand Dst, SDOperand Src,
559 SDOperand Size, unsigned Align,
561 const Value *DstSV, uint64_t DstSVOff,
562 const Value *SrcSV, uint64_t SrcSVOff);
564 /// Utility function to emit atomic bitwise operations (and, or, xor).
565 // It takes the bitwise instruction to expand, the associated machine basic
566 // block, and the associated X86 opcodes for reg/reg and reg/imm.
567 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
568 MachineInstr *BInstr,
569 MachineBasicBlock *BB,
573 /// Utility function to emit atomic min and max. It takes the min/max
574 // instruction to expand, the associated basic block, and the associated
575 // cmov opcode for moving the min or max value.
576 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
577 MachineBasicBlock *BB,
582 #endif // X86ISELLOWERING_H