1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
29 // X86 Specific DAG Nodes
31 // Start the numbering where the builtin ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 /// BSF - Bit scan forward.
35 /// BSR - Bit scan reverse.
39 /// SHLD, SHRD - Double shift instructions. These correspond to
40 /// X86::SHLDxx and X86::SHRDxx instructions.
44 /// FAND - Bitwise logical AND of floating point values. This corresponds
45 /// to X86::ANDPS or X86::ANDPD.
48 /// FOR - Bitwise logical OR of floating point values. This corresponds
49 /// to X86::ORPS or X86::ORPD.
52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
53 /// to X86::XORPS or X86::XORPD.
56 /// FSRL - Bitwise logical right shift of floating point values. These
57 /// corresponds to X86::PSRLDQ.
60 /// CALL - These operations represent an abstract X86 call
61 /// instruction, which includes a bunch of information. In particular the
62 /// operands of these node are:
64 /// #0 - The incoming token chain
66 /// #2 - The number of arg bytes the caller pushes on the stack.
67 /// #3 - The number of arg bytes the callee pops off the stack.
68 /// #4 - The value to pass in AL/AX/EAX (optional)
69 /// #5 - The value to pass in DL/DX/EDX (optional)
71 /// The result values of these nodes are:
73 /// #0 - The outgoing token chain
74 /// #1 - The first register result value (optional)
75 /// #2 - The second register result value (optional)
79 /// RDTSC_DAG - This operation implements the lowering for
83 /// X86 compare and logical compare instructions.
86 /// X86 bit-test instructions.
89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
90 /// operand, usually produced by a CMP instruction.
93 // Same as SETCC except it's materialized with a sbb and the value is all
94 // one's or all zero's.
95 SETCC_CARRY, // R = carry_bit ? ~0 : 0
97 /// X86 conditional moves. Operand 0 and operand 1 are the two values
98 /// to select from. Operand 2 is the condition code, and operand 3 is the
99 /// flag operand produced by a CMP or TEST instruction. It also writes a
103 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
104 /// is the block to branch if condition is true, operand 2 is the
105 /// condition code, and operand 3 is the flag operand produced by a CMP
106 /// or TEST instruction.
109 /// Return with a flag operand. Operand 0 is the chain operand, operand
110 /// 1 is the number of bytes of stack to pop.
113 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
116 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
119 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
120 /// at function entry, used for PIC code.
123 /// Wrapper - A wrapper node for TargetConstantPool,
124 /// TargetExternalSymbol, and TargetGlobalAddress.
127 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
128 /// relative displacements.
131 /// MOVQ2DQ - Copies a 64-bit value from an MMX vector to the low word
132 /// of an XMM vector, with the high word zero filled.
135 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
136 /// to an MMX vector. If you think this is too close to the previous
137 /// mnemonic, so do I; blame Intel.
140 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
141 /// i32, corresponds to X86::PEXTRB.
144 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
145 /// i32, corresponds to X86::PEXTRW.
148 /// INSERTPS - Insert any element of a 4 x float vector into any element
149 /// of a destination 4 x floatvector.
152 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
153 /// corresponds to X86::PINSRB.
156 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
157 /// corresponds to X86::PINSRW.
160 /// PSHUFB - Shuffle 16 8-bit values within a vector.
163 /// PANDN - and with not'd value.
166 /// PSIGNB/W/D - Copy integer sign.
167 PSIGNB, PSIGNW, PSIGND,
169 /// PBLENDVB - Variable blend
172 /// FMAX, FMIN - Floating point max and min.
176 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
177 /// approximation. Note that these typically require refinement
178 /// in order to obtain suitable precision.
181 // TLSADDR - Thread Local Storage.
184 // TLSCALL - Thread Local Storage. When calling to an OS provided
185 // thunk at the address from an earlier relocation.
188 // EH_RETURN - Exception Handling helpers.
191 /// TC_RETURN - Tail call return.
193 /// operand #1 callee (register or absolute)
194 /// operand #2 stack adjustment
195 /// operand #3 optional in flag
198 // VZEXT_MOVL - Vector move low and zero extend.
201 // VSHL, VSRL - Vector logical left / right shift.
204 // CMPPD, CMPPS - Vector double/float comparison.
205 // CMPPD, CMPPS - Vector double/float comparison.
208 // PCMP* - Vector integer comparisons.
209 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
210 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
212 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
213 ADD, SUB, ADC, SBB, SMUL,
214 INC, DEC, OR, XOR, AND,
216 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
218 // MUL_IMM - X86 specific multiply by immediate.
221 // PTEST - Vector bitwise comparisons
224 // TESTP - Vector packed fp sign bitwise comparisons
227 // Several flavors of instructions with vector shuffle behaviors.
262 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
263 // according to %al. An operator is needed so that this can be expanded
264 // with control flow.
265 VASTART_SAVE_XMM_REGS,
267 // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
276 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
277 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
278 // Atomic 64-bit binary operations.
279 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
287 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
291 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
294 // FNSTCW16m - Store FP control world into i16 memory.
297 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
298 /// integer destination in memory and a FP reg source. This corresponds
299 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
300 /// has two inputs (token chain and address) and two outputs (int value
301 /// and token chain).
306 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
307 /// integer source in memory and FP reg result. This corresponds to the
308 /// X86::FILD*m instructions. It has three inputs (token chain, address,
309 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
310 /// also produces a flag).
314 /// FLD - This instruction implements an extending load to FP stack slots.
315 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
316 /// operand, ptr to load from, and a ValueType node indicating the type
320 /// FST - This instruction implements a truncating store to FP stack
321 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
322 /// chain operand, value to store, address, and a ValueType to store it
326 /// VAARG_64 - This instruction grabs the address of the next argument
327 /// from a va_list. (reads and modifies the va_list in memory)
330 // WARNING: Do not add anything in the end unless you want the node to
331 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
332 // thought as target memory ops!
336 /// Define some predicates that are used for node matching.
338 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
339 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
340 bool isPSHUFDMask(ShuffleVectorSDNode *N);
342 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
343 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
344 bool isPSHUFHWMask(ShuffleVectorSDNode *N);
346 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
347 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
348 bool isPSHUFLWMask(ShuffleVectorSDNode *N);
350 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
351 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
352 bool isSHUFPMask(ShuffleVectorSDNode *N);
354 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
355 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
356 bool isMOVHLPSMask(ShuffleVectorSDNode *N);
358 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
359 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
361 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N);
363 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
364 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}.
365 bool isMOVLPMask(ShuffleVectorSDNode *N);
367 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
368 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}.
369 /// as well as MOVLHPS.
370 bool isMOVLHPSMask(ShuffleVectorSDNode *N);
372 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
373 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
374 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
376 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
377 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
378 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
380 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
381 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
383 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N);
385 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
386 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
388 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N);
390 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
391 /// specifies a shuffle of elements that is suitable for input to MOVSS,
392 /// MOVSD, and MOVD, i.e. setting the lowest element.
393 bool isMOVLMask(ShuffleVectorSDNode *N);
395 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
396 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
397 bool isMOVSHDUPMask(ShuffleVectorSDNode *N);
399 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
400 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
401 bool isMOVSLDUPMask(ShuffleVectorSDNode *N);
403 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
404 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
405 bool isMOVDDUPMask(ShuffleVectorSDNode *N);
407 /// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand
408 /// specifies a shuffle of elements that is suitable for input to PALIGNR.
409 bool isPALIGNRMask(ShuffleVectorSDNode *N);
411 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
412 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
414 unsigned getShuffleSHUFImmediate(SDNode *N);
416 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
417 /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction.
418 unsigned getShufflePSHUFHWImmediate(SDNode *N);
420 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
421 /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction.
422 unsigned getShufflePSHUFLWImmediate(SDNode *N);
424 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
425 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
426 unsigned getShufflePALIGNRImmediate(SDNode *N);
428 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
430 bool isZeroNode(SDValue Elt);
432 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
433 /// fit into displacement field of the instruction.
434 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
435 bool hasSymbolicDisplacement = true);
438 //===--------------------------------------------------------------------===//
439 // X86TargetLowering - X86 Implementation of the TargetLowering interface
440 class X86TargetLowering : public TargetLowering {
442 explicit X86TargetLowering(X86TargetMachine &TM);
444 virtual unsigned getJumpTableEncoding() const;
446 virtual const MCExpr *
447 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
448 const MachineBasicBlock *MBB, unsigned uid,
449 MCContext &Ctx) const;
451 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
453 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
454 SelectionDAG &DAG) const;
455 virtual const MCExpr *
456 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
457 unsigned JTI, MCContext &Ctx) const;
459 /// getStackPtrReg - Return the stack pointer register we are using: either
461 unsigned getStackPtrReg() const { return X86StackPtr; }
463 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
464 /// function arguments in the caller parameter area. For X86, aggregates
465 /// that contains are placed at 16-byte boundaries while the rest are at
466 /// 4-byte boundaries.
467 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
469 /// getOptimalMemOpType - Returns the target specific optimal type for load
470 /// and store operations as a result of memset, memcpy, and memmove
471 /// lowering. If DstAlign is zero that means it's safe to destination
472 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
473 /// means there isn't a need to check it against alignment requirement,
474 /// probably because the source does not need to be loaded. If
475 /// 'NonScalarIntSafe' is true, that means it's safe to return a
476 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
477 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
478 /// constant so it does not need to be loaded.
479 /// It returns EVT::Other if the type should be determined using generic
480 /// target-independent logic.
482 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
483 bool NonScalarIntSafe, bool MemcpyStrSrc,
484 MachineFunction &MF) const;
486 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
487 /// unaligned memory accesses. of the specified type.
488 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
492 /// LowerOperation - Provide custom lowering hooks for some operations.
494 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
496 /// ReplaceNodeResults - Replace the results of node with an illegal result
497 /// type with new values built out of custom code.
499 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
500 SelectionDAG &DAG) const;
503 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
505 /// isTypeDesirableForOp - Return true if the target has native support for
506 /// the specified value type and it is 'desirable' to use the type for the
507 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
508 /// instruction encodings are longer and some i16 instructions are slow.
509 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
511 /// isTypeDesirable - Return true if the target has native support for the
512 /// specified value type and it is 'desirable' to use the type. e.g. On x86
513 /// i16 is legal, but undesirable since i16 instruction encodings are longer
514 /// and some i16 instructions are slow.
515 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
517 virtual MachineBasicBlock *
518 EmitInstrWithCustomInserter(MachineInstr *MI,
519 MachineBasicBlock *MBB) const;
522 /// getTargetNodeName - This method returns the name of a target specific
524 virtual const char *getTargetNodeName(unsigned Opcode) const;
526 /// getSetCCResultType - Return the ISD::SETCC ValueType
527 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
529 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
530 /// in Mask are known to be either zero or one and return them in the
531 /// KnownZero/KnownOne bitsets.
532 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
536 const SelectionDAG &DAG,
537 unsigned Depth = 0) const;
539 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
540 // operation that are sign bits.
541 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
542 unsigned Depth) const;
545 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
547 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
549 virtual bool ExpandInlineAsm(CallInst *CI) const;
551 ConstraintType getConstraintType(const std::string &Constraint) const;
553 /// Examine constraint string and operand type and determine a weight value.
554 /// The operand object must already have been set up with the operand type.
555 virtual ConstraintWeight getSingleConstraintMatchWeight(
556 AsmOperandInfo &info, const char *constraint) const;
558 std::vector<unsigned>
559 getRegClassForInlineAsmConstraint(const std::string &Constraint,
562 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
564 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
565 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
566 /// true it means one of the asm constraint of the inline asm instruction
567 /// being processed is 'm'.
568 virtual void LowerAsmOperandForConstraint(SDValue Op,
569 char ConstraintLetter,
570 std::vector<SDValue> &Ops,
571 SelectionDAG &DAG) const;
573 /// getRegForInlineAsmConstraint - Given a physical register constraint
574 /// (e.g. {edx}), return the register number and the register class for the
575 /// register. This should only be used for C_Register constraints. On
576 /// error, this returns a register number of 0.
577 std::pair<unsigned, const TargetRegisterClass*>
578 getRegForInlineAsmConstraint(const std::string &Constraint,
581 /// isLegalAddressingMode - Return true if the addressing mode represented
582 /// by AM is legal for this target, for a load/store of the specified type.
583 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
585 /// isTruncateFree - Return true if it's free to truncate a value of
586 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
587 /// register EAX to i16 by referencing its sub-register AX.
588 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
589 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
591 /// isZExtFree - Return true if any actual instruction that defines a
592 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
593 /// register. This does not necessarily include registers defined in
594 /// unknown ways, such as incoming arguments, or copies from unknown
595 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
596 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
597 /// all instructions that define 32-bit values implicit zero-extend the
598 /// result out to 64 bits.
599 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const;
600 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
602 /// isNarrowingProfitable - Return true if it's profitable to narrow
603 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
604 /// from i32 to i8 but not from i32 to i16.
605 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
607 /// isFPImmLegal - Returns true if the target can instruction select the
608 /// specified FP immediate natively. If false, the legalizer will
609 /// materialize the FP immediate as a load from a constant pool.
610 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
612 /// isShuffleMaskLegal - Targets can use this to indicate that they only
613 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
614 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
615 /// values are assumed to be legal.
616 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
619 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
620 /// used by Targets can use this to indicate if there is a suitable
621 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
623 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
626 /// ShouldShrinkFPConstant - If true, then instruction selection should
627 /// seek to shrink the FP constant of the specified type to a smaller type
628 /// in order to save space and / or reduce runtime.
629 virtual bool ShouldShrinkFPConstant(EVT VT) const {
630 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
631 // expensive than a straight movsd. On the other hand, it's important to
632 // shrink long double fp constant since fldt is very slow.
633 return !X86ScalarSSEf64 || VT == MVT::f80;
636 const X86Subtarget* getSubtarget() const {
640 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
641 /// computed in an SSE register, not on the X87 floating point stack.
642 bool isScalarFPTypeInSSEReg(EVT VT) const {
643 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
644 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
647 /// createFastISel - This method returns a target specific FastISel object,
648 /// or null if the target does not support "fast" ISel.
649 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
651 /// getFunctionAlignment - Return the Log2 alignment of this function.
652 virtual unsigned getFunctionAlignment(const Function *F) const;
654 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
655 MachineFunction &MF) const;
657 /// getStackCookieLocation - Return true if the target stores stack
658 /// protector cookies at a fixed offset in some non-standard address
659 /// space, and populates the address space and offset as
661 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
664 std::pair<const TargetRegisterClass*, uint8_t>
665 findRepresentativeClass(EVT VT) const;
668 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
669 /// make the right decision when generating code for different targets.
670 const X86Subtarget *Subtarget;
671 const X86RegisterInfo *RegInfo;
672 const TargetData *TD;
674 /// X86StackPtr - X86 physical register used as stack ptr.
675 unsigned X86StackPtr;
677 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
678 /// floating point ops.
679 /// When SSE is available, use it for f32 operations.
680 /// When SSE2 is available, use it for f64 operations.
681 bool X86ScalarSSEf32;
682 bool X86ScalarSSEf64;
684 /// LegalFPImmediates - A list of legal fp immediates.
685 std::vector<APFloat> LegalFPImmediates;
687 /// addLegalFPImmediate - Indicate that this x86 target can instruction
688 /// select the specified FP immediate natively.
689 void addLegalFPImmediate(const APFloat& Imm) {
690 LegalFPImmediates.push_back(Imm);
693 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
694 CallingConv::ID CallConv, bool isVarArg,
695 const SmallVectorImpl<ISD::InputArg> &Ins,
696 DebugLoc dl, SelectionDAG &DAG,
697 SmallVectorImpl<SDValue> &InVals) const;
698 SDValue LowerMemArgument(SDValue Chain,
699 CallingConv::ID CallConv,
700 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
701 DebugLoc dl, SelectionDAG &DAG,
702 const CCValAssign &VA, MachineFrameInfo *MFI,
704 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
705 DebugLoc dl, SelectionDAG &DAG,
706 const CCValAssign &VA,
707 ISD::ArgFlagsTy Flags) const;
709 // Call lowering helpers.
711 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
712 /// for tail call optimization. Targets which want to do tail call
713 /// optimization should implement this function.
714 bool IsEligibleForTailCallOptimization(SDValue Callee,
715 CallingConv::ID CalleeCC,
717 bool isCalleeStructRet,
718 bool isCallerStructRet,
719 const SmallVectorImpl<ISD::OutputArg> &Outs,
720 const SmallVectorImpl<SDValue> &OutVals,
721 const SmallVectorImpl<ISD::InputArg> &Ins,
722 SelectionDAG& DAG) const;
723 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
724 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
725 SDValue Chain, bool IsTailCall, bool Is64Bit,
726 int FPDiff, DebugLoc dl) const;
728 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
729 SelectionDAG &DAG) const;
731 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
732 bool isSigned) const;
734 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
735 SelectionDAG &DAG) const;
736 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
737 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
738 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
739 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
740 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
741 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
742 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
743 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
744 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
745 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
746 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
747 int64_t Offset, SelectionDAG &DAG) const;
748 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
749 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
750 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
751 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
752 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
753 SelectionDAG &DAG) const;
754 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const;
755 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
756 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
757 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
758 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
759 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
760 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
761 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
762 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
763 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
764 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
765 DebugLoc dl, SelectionDAG &DAG) const;
766 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
767 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
768 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
769 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
770 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
771 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
772 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
773 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
774 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
775 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
776 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
777 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
778 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
779 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
780 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
781 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
782 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
783 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
784 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
785 SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const;
786 SDValue LowerSHL(SDValue Op, SelectionDAG &DAG) const;
787 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
789 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
790 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
791 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
792 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const;
794 // Utility functions to help LowerVECTOR_SHUFFLE
795 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const;
798 LowerFormalArguments(SDValue Chain,
799 CallingConv::ID CallConv, bool isVarArg,
800 const SmallVectorImpl<ISD::InputArg> &Ins,
801 DebugLoc dl, SelectionDAG &DAG,
802 SmallVectorImpl<SDValue> &InVals) const;
804 LowerCall(SDValue Chain, SDValue Callee,
805 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
806 const SmallVectorImpl<ISD::OutputArg> &Outs,
807 const SmallVectorImpl<SDValue> &OutVals,
808 const SmallVectorImpl<ISD::InputArg> &Ins,
809 DebugLoc dl, SelectionDAG &DAG,
810 SmallVectorImpl<SDValue> &InVals) const;
813 LowerReturn(SDValue Chain,
814 CallingConv::ID CallConv, bool isVarArg,
815 const SmallVectorImpl<ISD::OutputArg> &Outs,
816 const SmallVectorImpl<SDValue> &OutVals,
817 DebugLoc dl, SelectionDAG &DAG) const;
819 virtual bool isUsedByReturnOnly(SDNode *N) const;
822 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
823 const SmallVectorImpl<ISD::OutputArg> &Outs,
824 LLVMContext &Context) const;
826 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
827 SelectionDAG &DAG, unsigned NewOp) const;
829 /// Utility function to emit string processing sse4.2 instructions
830 /// that return in xmm0.
831 /// This takes the instruction to expand, the associated machine basic
832 /// block, the number of args, and whether or not the second arg is
833 /// in memory or not.
834 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
835 unsigned argNum, bool inMem) const;
837 /// Utility functions to emit monitor and mwait instructions. These
838 /// need to make sure that the arguments to the intrinsic are in the
839 /// correct registers.
840 MachineBasicBlock *EmitMonitor(MachineInstr *MI,
841 MachineBasicBlock *BB) const;
842 MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const;
844 /// Utility function to emit atomic bitwise operations (and, or, xor).
845 /// It takes the bitwise instruction to expand, the associated machine basic
846 /// block, and the associated X86 opcodes for reg/reg and reg/imm.
847 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
848 MachineInstr *BInstr,
849 MachineBasicBlock *BB,
856 TargetRegisterClass *RC,
857 bool invSrc = false) const;
859 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
860 MachineInstr *BInstr,
861 MachineBasicBlock *BB,
866 bool invSrc = false) const;
868 /// Utility function to emit atomic min and max. It takes the min/max
869 /// instruction to expand, the associated basic block, and the associated
870 /// cmov opcode for moving the min or max value.
871 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
872 MachineBasicBlock *BB,
873 unsigned cmovOpc) const;
875 // Utility function to emit the low-level va_arg code for X86-64.
876 MachineBasicBlock *EmitVAARG64WithCustomInserter(
878 MachineBasicBlock *MBB) const;
880 /// Utility function to emit the xmm reg save portion of va_start.
881 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
882 MachineInstr *BInstr,
883 MachineBasicBlock *BB) const;
885 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
886 MachineBasicBlock *BB) const;
888 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
889 MachineBasicBlock *BB) const;
891 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
892 MachineBasicBlock *BB) const;
894 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
895 MachineBasicBlock *BB) const;
897 /// Emit nodes that will be selected as "test Op0,Op0", or something
898 /// equivalent, for use with the given x86 condition code.
899 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
901 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
902 /// equivalent, for use with the given x86 condition code.
903 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
904 SelectionDAG &DAG) const;
908 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
912 #endif // X86ISELLOWERING_H