1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetOptions.h"
25 class X86TargetMachine;
28 // X86 Specific DAG Nodes
29 enum NodeType : unsigned {
30 // Start the numbering where the builtin ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
38 /// Double shift instructions. These correspond to
39 /// X86::SHLDxx and X86::SHRDxx instructions.
43 /// Bitwise logical AND of floating point values. This corresponds
44 /// to X86::ANDPS or X86::ANDPD.
47 /// Bitwise logical OR of floating point values. This corresponds
48 /// to X86::ORPS or X86::ORPD.
51 /// Bitwise logical XOR of floating point values. This corresponds
52 /// to X86::XORPS or X86::XORPD.
55 /// Bitwise logical ANDNOT of floating point values. This
56 /// corresponds to X86::ANDNPS or X86::ANDNPD.
59 /// These operations represent an abstract X86 call
60 /// instruction, which includes a bunch of information. In particular the
61 /// operands of these node are:
63 /// #0 - The incoming token chain
65 /// #2 - The number of arg bytes the caller pushes on the stack.
66 /// #3 - The number of arg bytes the callee pops off the stack.
67 /// #4 - The value to pass in AL/AX/EAX (optional)
68 /// #5 - The value to pass in DL/DX/EDX (optional)
70 /// The result values of these nodes are:
72 /// #0 - The outgoing token chain
73 /// #1 - The first register result value (optional)
74 /// #2 - The second register result value (optional)
78 /// This operation implements the lowering for readcyclecounter
81 /// X86 Read Time-Stamp Counter and Processor ID.
84 /// X86 Read Performance Monitoring Counters.
87 /// X86 compare and logical compare instructions.
90 /// X86 bit-test instructions.
93 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
94 /// operand, usually produced by a CMP instruction.
100 // Same as SETCC except it's materialized with a sbb and the value is all
101 // one's or all zero's.
102 SETCC_CARRY, // R = carry_bit ? ~0 : 0
104 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
105 /// Operands are two FP values to compare; result is a mask of
106 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
109 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
110 /// result in an integer GPR. Needs masking for scalar result.
113 /// X86 conditional moves. Operand 0 and operand 1 are the two values
114 /// to select from. Operand 2 is the condition code, and operand 3 is the
115 /// flag operand produced by a CMP or TEST instruction. It also writes a
119 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
120 /// is the block to branch if condition is true, operand 2 is the
121 /// condition code, and operand 3 is the flag operand produced by a CMP
122 /// or TEST instruction.
125 /// Return with a flag operand. Operand 0 is the chain operand, operand
126 /// 1 is the number of bytes of stack to pop.
129 /// Repeat fill, corresponds to X86::REP_STOSx.
132 /// Repeat move, corresponds to X86::REP_MOVSx.
135 /// On Darwin, this node represents the result of the popl
136 /// at function entry, used for PIC code.
139 /// A wrapper node for TargetConstantPool,
140 /// TargetExternalSymbol, and TargetGlobalAddress.
143 /// Special wrapper used under X86-64 PIC mode for RIP
144 /// relative displacements.
147 /// Copies a 64-bit value from the low word of an XMM vector
148 /// to an MMX vector. If you think this is too close to the previous
149 /// mnemonic, so do I; blame Intel.
152 /// Copies a 32-bit value from the low word of a MMX
156 /// Copies a GPR into the low 32-bit word of a MMX vector
157 /// and zero out the high word.
160 /// Extract an 8-bit value from a vector and zero extend it to
161 /// i32, corresponds to X86::PEXTRB.
164 /// Extract a 16-bit value from a vector and zero extend it to
165 /// i32, corresponds to X86::PEXTRW.
168 /// Insert any element of a 4 x float vector into any element
169 /// of a destination 4 x floatvector.
172 /// Insert the lower 8-bits of a 32-bit value to a vector,
173 /// corresponds to X86::PINSRB.
176 /// Insert the lower 16-bits of a 32-bit value to a vector,
177 /// corresponds to X86::PINSRW.
180 /// Shuffle 16 8-bit values within a vector.
183 /// Compute Sum of Absolute Differences.
185 /// Compute Double Block Packed Sum-Absolute-Differences
188 /// Bitwise Logical AND NOT of Packed FP values.
191 /// Copy integer sign.
194 /// Blend where the selector is an immediate.
197 /// Blend where the condition has been shrunk.
198 /// This is used to emphasize that the condition mask is
199 /// no more valid for generic VSELECT optimizations.
202 /// Combined add and sub on an FP vector.
205 // FP vector ops with rounding mode.
214 // FP vector get exponent
216 // Extract Normalized Mantissas
220 // Integer add/sub with unsigned saturation.
223 // Integer add/sub with signed saturation.
226 // Unsigned Integer average
228 /// Integer horizontal add.
231 /// Integer horizontal sub.
234 /// Floating point horizontal add.
237 /// Floating point horizontal sub.
240 // Integer absolute value
243 // Detect Conflicts Within a Vector
246 /// Floating point max and min.
249 /// Commutative FMIN and FMAX.
252 /// Floating point reciprocal-sqrt and reciprocal approximation.
253 /// Note that these typically require refinement
254 /// in order to obtain suitable precision.
257 // Thread Local Storage.
260 // Thread Local Storage. A call to get the start address
261 // of the TLS block for the current module.
264 // Thread Local Storage. When calling to an OS provided
265 // thunk at the address from an earlier relocation.
268 // Exception Handling helpers.
271 // SjLj exception handling setjmp.
274 // SjLj exception handling longjmp.
277 /// Tail call return. See X86TargetLowering::LowerCall for
278 /// the list of operands.
281 // Vector move to low scalar and zero higher vector elements.
284 // Vector integer zero-extend.
287 // Vector integer signed-extend.
290 // Vector integer truncate.
292 // Vector integer truncate with unsigned/signed saturation.
301 // Vector signed/unsigned integer to double.
304 // 128-bit vector logical left / right shift
307 // Vector shift elements
310 // Vector shift elements by immediate
313 // Vector packed double/float comparison.
316 // Vector integer comparisons.
318 // Vector integer comparisons, the result is in a mask vector.
321 /// Vector comparison generating mask bits for fp and
322 /// integer signed and unsigned data types.
325 // Vector comparison with rounding mode for FP values
328 // Arithmetic operations with FLAGS results.
329 ADD, SUB, ADC, SBB, SMUL,
330 INC, DEC, OR, XOR, AND,
332 BEXTR, // Bit field extract
334 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
336 // 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS
339 // 8-bit divrem that zero-extend the high result (AH).
343 // X86-specific multiply by immediate.
346 // Vector bitwise comparisons.
349 // Vector packed fp sign bitwise comparisons.
352 // Vector "test" in AVX-512, the result is in a mask vector.
356 // OR/AND test for masks
360 // Several flavors of instructions with vector shuffle behaviors.
365 // AVX512 inter-lane alignr
371 //Shuffle Packed Values at 128-bit granularity
392 // Bitwise ternary logic
394 // Fix Up Special Packed Float32/64 values
396 // Range Restriction Calculation For Packed Pairs of Float32/64 values
398 // Reduce - Perform Reduction Transformation on scalar\packed FP
400 // RndScale - Round FP Values To Include A Given Number Of Fraction Bits
402 // VFPCLASS - Tests Types Of a FP Values for packed types.
404 // VFPCLASSS - Tests Types Of a FP Values for scalar types.
406 // Broadcast scalar to vector
408 // Broadcast mask to vector
410 // Broadcast subvector to vector
412 // Insert/Extract vector element
416 /// SSE4A Extraction and Insertion.
419 // XOP variable/immediate rotations
421 // XOP arithmetic/logical shifts
423 // XOP signed/unsigned integer comparisons
426 // Vector multiply packed unsigned doubleword integers
428 // Vector multiply packed signed doubleword integers
430 // Vector Multiply Packed UnsignedIntegers with Round and Scale
432 // Multiply and Add Packed Integers
433 VPMADDUBSW, VPMADDWD,
441 // FMA with rounding mode
449 // Compress and expand
453 //Convert Unsigned/Integer to Scalar Floating-Point Value
458 // Vector float/double to signed/unsigned integer.
459 FP_TO_SINT_RND, FP_TO_UINT_RND,
460 // Save xmm argument registers to the stack, according to %al. An operator
461 // is needed so that this can be expanded with control flow.
462 VASTART_SAVE_XMM_REGS,
464 // Windows's _chkstk call to do stack probing.
467 // For allocating variable amounts of stack space when using
468 // segmented stacks. Check if the current stacklet has enough space, and
469 // falls back to heap allocation if not.
478 // Store FP status word into i16 register.
481 // Store contents of %ah into %eflags.
484 // Get a random integer and indicate whether it is valid in CF.
487 // Get a NIST SP800-90B & C compliant random integer and
488 // indicate whether it is valid in CF.
494 // Test if in transactional execution.
498 RSQRT28, RCP28, EXP2,
501 LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
505 // Load, scalar_to_vector, and zero extend.
508 // Store FP control world into i16 memory.
511 /// This instruction implements FP_TO_SINT with the
512 /// integer destination in memory and a FP reg source. This corresponds
513 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
514 /// has two inputs (token chain and address) and two outputs (int value
515 /// and token chain).
520 /// This instruction implements SINT_TO_FP with the
521 /// integer source in memory and FP reg result. This corresponds to the
522 /// X86::FILD*m instructions. It has three inputs (token chain, address,
523 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
524 /// also produces a flag).
528 /// This instruction implements an extending load to FP stack slots.
529 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
530 /// operand, ptr to load from, and a ValueType node indicating the type
534 /// This instruction implements a truncating store to FP stack
535 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
536 /// chain operand, value to store, address, and a ValueType to store it
540 /// This instruction grabs the address of the next argument
541 /// from a va_list. (reads and modifies the va_list in memory)
544 // WARNING: Do not add anything in the end unless you want the node to
545 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
546 // thought as target memory ops!
550 /// Define some predicates that are used for node matching.
552 /// Return true if the specified
553 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
554 /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
555 bool isVEXTRACT128Index(SDNode *N);
557 /// Return true if the specified
558 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
559 /// suitable for input to VINSERTF128, VINSERTI128 instructions.
560 bool isVINSERT128Index(SDNode *N);
562 /// Return true if the specified
563 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
564 /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
565 bool isVEXTRACT256Index(SDNode *N);
567 /// Return true if the specified
568 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
569 /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
570 bool isVINSERT256Index(SDNode *N);
572 /// Return the appropriate
573 /// immediate to extract the specified EXTRACT_SUBVECTOR index
574 /// with VEXTRACTF128, VEXTRACTI128 instructions.
575 unsigned getExtractVEXTRACT128Immediate(SDNode *N);
577 /// Return the appropriate
578 /// immediate to insert at the specified INSERT_SUBVECTOR index
579 /// with VINSERTF128, VINSERT128 instructions.
580 unsigned getInsertVINSERT128Immediate(SDNode *N);
582 /// Return the appropriate
583 /// immediate to extract the specified EXTRACT_SUBVECTOR index
584 /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
585 unsigned getExtractVEXTRACT256Immediate(SDNode *N);
587 /// Return the appropriate
588 /// immediate to insert at the specified INSERT_SUBVECTOR index
589 /// with VINSERTF64x4, VINSERTI64x4 instructions.
590 unsigned getInsertVINSERT256Immediate(SDNode *N);
592 /// Returns true if Elt is a constant zero or floating point constant +0.0.
593 bool isZeroNode(SDValue Elt);
595 /// Returns true of the given offset can be
596 /// fit into displacement field of the instruction.
597 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
598 bool hasSymbolicDisplacement = true);
601 /// Determines whether the callee is required to pop its
602 /// own arguments. Callee pop is necessary to support tail calls.
603 bool isCalleePop(CallingConv::ID CallingConv,
604 bool is64Bit, bool IsVarArg, bool TailCallOpt);
606 /// AVX512 static rounding constants. These need to match the values in
608 enum STATIC_ROUNDING {
617 //===--------------------------------------------------------------------===//
618 // X86 Implementation of the TargetLowering interface
619 class X86TargetLowering final : public TargetLowering {
621 explicit X86TargetLowering(const X86TargetMachine &TM,
622 const X86Subtarget &STI);
624 unsigned getJumpTableEncoding() const override;
625 bool useSoftFloat() const override;
627 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
632 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
633 const MachineBasicBlock *MBB, unsigned uid,
634 MCContext &Ctx) const override;
636 /// Returns relocation base for the given PIC jumptable.
637 SDValue getPICJumpTableRelocBase(SDValue Table,
638 SelectionDAG &DAG) const override;
640 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
641 unsigned JTI, MCContext &Ctx) const override;
643 /// Return the desired alignment for ByVal aggregate
644 /// function arguments in the caller parameter area. For X86, aggregates
645 /// that contains are placed at 16-byte boundaries while the rest are at
646 /// 4-byte boundaries.
647 unsigned getByValTypeAlignment(Type *Ty,
648 const DataLayout &DL) const override;
650 /// Returns the target specific optimal type for load
651 /// and store operations as a result of memset, memcpy, and memmove
652 /// lowering. If DstAlign is zero that means it's safe to destination
653 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
654 /// means there isn't a need to check it against alignment requirement,
655 /// probably because the source does not need to be loaded. If 'IsMemset' is
656 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
657 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
658 /// source is constant so it does not need to be loaded.
659 /// It returns EVT::Other if the type should be determined using generic
660 /// target-independent logic.
661 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
662 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
663 MachineFunction &MF) const override;
665 /// Returns true if it's safe to use load / store of the
666 /// specified type to expand memcpy / memset inline. This is mostly true
667 /// for all types except for some special cases. For example, on X86
668 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
669 /// also does type conversion. Note the specified type doesn't have to be
670 /// legal as the hook is used before type legalization.
671 bool isSafeMemOpType(MVT VT) const override;
673 /// Returns true if the target allows unaligned memory accesses of the
674 /// specified type. Returns whether it is "fast" in the last argument.
675 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
676 bool *Fast) const override;
678 /// Provide custom lowering hooks for some operations.
680 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
682 /// Replace the results of node with an illegal result
683 /// type with new values built out of custom code.
685 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
686 SelectionDAG &DAG) const override;
689 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
691 /// Return true if the target has native support for
692 /// the specified value type and it is 'desirable' to use the type for the
693 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
694 /// instruction encodings are longer and some i16 instructions are slow.
695 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
697 /// Return true if the target has native support for the
698 /// specified value type and it is 'desirable' to use the type. e.g. On x86
699 /// i16 is legal, but undesirable since i16 instruction encodings are longer
700 /// and some i16 instructions are slow.
701 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
704 EmitInstrWithCustomInserter(MachineInstr *MI,
705 MachineBasicBlock *MBB) const override;
708 /// This method returns the name of a target specific DAG node.
709 const char *getTargetNodeName(unsigned Opcode) const override;
711 bool isCheapToSpeculateCttz() const override;
713 bool isCheapToSpeculateCtlz() const override;
715 /// Return the value type to use for ISD::SETCC.
716 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
717 EVT VT) const override;
719 /// Determine which of the bits specified in Mask are known to be either
720 /// zero or one and return them in the KnownZero/KnownOne bitsets.
721 void computeKnownBitsForTargetNode(const SDValue Op,
724 const SelectionDAG &DAG,
725 unsigned Depth = 0) const override;
727 /// Determine the number of bits in the operation that are sign bits.
728 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
729 const SelectionDAG &DAG,
730 unsigned Depth) const override;
732 bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
733 int64_t &Offset) const override;
735 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
737 bool ExpandInlineAsm(CallInst *CI) const override;
739 ConstraintType getConstraintType(StringRef Constraint) const override;
741 /// Examine constraint string and operand type and determine a weight value.
742 /// The operand object must already have been set up with the operand type.
744 getSingleConstraintMatchWeight(AsmOperandInfo &info,
745 const char *constraint) const override;
747 const char *LowerXConstraint(EVT ConstraintVT) const override;
749 /// Lower the specified operand into the Ops vector. If it is invalid, don't
750 /// add anything to Ops. If hasMemory is true it means one of the asm
751 /// constraint of the inline asm instruction being processed is 'm'.
752 void LowerAsmOperandForConstraint(SDValue Op,
753 std::string &Constraint,
754 std::vector<SDValue> &Ops,
755 SelectionDAG &DAG) const override;
758 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
759 if (ConstraintCode == "i")
760 return InlineAsm::Constraint_i;
761 else if (ConstraintCode == "o")
762 return InlineAsm::Constraint_o;
763 else if (ConstraintCode == "v")
764 return InlineAsm::Constraint_v;
765 else if (ConstraintCode == "X")
766 return InlineAsm::Constraint_X;
767 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
770 /// Given a physical register constraint
771 /// (e.g. {edx}), return the register number and the register class for the
772 /// register. This should only be used for C_Register constraints. On
773 /// error, this returns a register number of 0.
774 std::pair<unsigned, const TargetRegisterClass *>
775 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
776 StringRef Constraint, MVT VT) const override;
778 /// Return true if the addressing mode represented
779 /// by AM is legal for this target, for a load/store of the specified type.
780 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
781 Type *Ty, unsigned AS) const override;
783 /// Return true if the specified immediate is legal
784 /// icmp immediate, that is the target has icmp instructions which can
785 /// compare a register against the immediate without having to materialize
786 /// the immediate into a register.
787 bool isLegalICmpImmediate(int64_t Imm) const override;
789 /// Return true if the specified immediate is legal
790 /// add immediate, that is the target has add instructions which can
791 /// add a register and the immediate without having to materialize
792 /// the immediate into a register.
793 bool isLegalAddImmediate(int64_t Imm) const override;
795 /// \brief Return the cost of the scaling factor used in the addressing
796 /// mode represented by AM for this target, for a load/store
797 /// of the specified type.
798 /// If the AM is supported, the return value must be >= 0.
799 /// If the AM is not supported, it returns a negative value.
800 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
801 unsigned AS) const override;
803 bool isVectorShiftByScalarCheap(Type *Ty) const override;
805 /// Return true if it's free to truncate a value of
806 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
807 /// register EAX to i16 by referencing its sub-register AX.
808 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
809 bool isTruncateFree(EVT VT1, EVT VT2) const override;
811 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
813 /// Return true if any actual instruction that defines a
814 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
815 /// register. This does not necessarily include registers defined in
816 /// unknown ways, such as incoming arguments, or copies from unknown
817 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
818 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
819 /// all instructions that define 32-bit values implicit zero-extend the
820 /// result out to 64 bits.
821 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
822 bool isZExtFree(EVT VT1, EVT VT2) const override;
823 bool isZExtFree(SDValue Val, EVT VT2) const override;
825 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
826 /// extend node) is profitable.
827 bool isVectorLoadExtDesirable(SDValue) const override;
829 /// Return true if an FMA operation is faster than a pair of fmul and fadd
830 /// instructions. fmuladd intrinsics will be expanded to FMAs when this
831 /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
832 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
834 /// Return true if it's profitable to narrow
835 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
836 /// from i32 to i8 but not from i32 to i16.
837 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
839 /// Returns true if the target can instruction select the
840 /// specified FP immediate natively. If false, the legalizer will
841 /// materialize the FP immediate as a load from a constant pool.
842 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
844 /// Targets can use this to indicate that they only support *some*
845 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
846 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
848 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
849 EVT VT) const override;
851 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
852 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to
853 /// replace a VAND with a constant pool entry.
854 bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
855 EVT VT) const override;
857 /// If true, then instruction selection should
858 /// seek to shrink the FP constant of the specified type to a smaller type
859 /// in order to save space and / or reduce runtime.
860 bool ShouldShrinkFPConstant(EVT VT) const override {
861 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
862 // expensive than a straight movsd. On the other hand, it's important to
863 // shrink long double fp constant since fldt is very slow.
864 return !X86ScalarSSEf64 || VT == MVT::f80;
867 /// Return true if we believe it is correct and profitable to reduce the
868 /// load node to a smaller type.
869 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
870 EVT NewVT) const override;
872 /// Return true if the specified scalar FP type is computed in an SSE
873 /// register, not on the X87 floating point stack.
874 bool isScalarFPTypeInSSEReg(EVT VT) const {
875 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
876 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
879 /// \brief Returns true if it is beneficial to convert a load of a constant
880 /// to just the constant itself.
881 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
882 Type *Ty) const override;
884 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
886 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
888 /// Intel processors have a unified instruction and data cache
889 const char * getClearCacheBuiltinName() const override {
890 return nullptr; // nothing to do, move along.
893 unsigned getRegisterByName(const char* RegName, EVT VT,
894 SelectionDAG &DAG) const override;
896 /// If a physical register, this returns the register that receives the
897 /// exception address on entry to an EH pad.
899 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
901 /// If a physical register, this returns the register that receives the
902 /// exception typeid on entry to a landing pad.
904 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
906 /// This method returns a target specific FastISel object,
907 /// or null if the target does not support "fast" ISel.
908 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
909 const TargetLibraryInfo *libInfo) const override;
911 /// Return true if the target stores stack protector cookies at a fixed
912 /// offset in some non-standard address space, and populates the address
913 /// space and offset as appropriate.
914 bool getStackCookieLocation(unsigned &AddressSpace,
915 unsigned &Offset) const override;
917 /// Return true if the target stores SafeStack pointer at a fixed offset in
918 /// some non-standard address space, and populates the address space and
919 /// offset as appropriate.
920 Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
922 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
923 SelectionDAG &DAG) const;
925 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
927 bool useLoadStackGuardNode() const override;
928 /// \brief Customize the preferred legalization strategy for certain types.
929 LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
931 bool isIntDivCheap(EVT VT, AttributeSet Attr) const override;
933 void markInRegArguments(SelectionDAG &DAG, TargetLowering::ArgListTy& Args)
937 std::pair<const TargetRegisterClass *, uint8_t>
938 findRepresentativeClass(const TargetRegisterInfo *TRI,
939 MVT VT) const override;
942 /// Keep a pointer to the X86Subtarget around so that we can
943 /// make the right decision when generating code for different targets.
944 const X86Subtarget *Subtarget;
946 /// Select between SSE or x87 floating point ops.
947 /// When SSE is available, use it for f32 operations.
948 /// When SSE2 is available, use it for f64 operations.
949 bool X86ScalarSSEf32;
950 bool X86ScalarSSEf64;
952 /// A list of legal FP immediates.
953 std::vector<APFloat> LegalFPImmediates;
955 /// Indicate that this x86 target can instruction
956 /// select the specified FP immediate natively.
957 void addLegalFPImmediate(const APFloat& Imm) {
958 LegalFPImmediates.push_back(Imm);
961 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
962 CallingConv::ID CallConv, bool isVarArg,
963 const SmallVectorImpl<ISD::InputArg> &Ins,
964 SDLoc dl, SelectionDAG &DAG,
965 SmallVectorImpl<SDValue> &InVals) const;
966 SDValue LowerMemArgument(SDValue Chain,
967 CallingConv::ID CallConv,
968 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
969 SDLoc dl, SelectionDAG &DAG,
970 const CCValAssign &VA, MachineFrameInfo *MFI,
972 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
973 SDLoc dl, SelectionDAG &DAG,
974 const CCValAssign &VA,
975 ISD::ArgFlagsTy Flags) const;
977 // Call lowering helpers.
979 /// Check whether the call is eligible for tail call optimization. Targets
980 /// that want to do tail call optimization should implement this function.
981 bool IsEligibleForTailCallOptimization(SDValue Callee,
982 CallingConv::ID CalleeCC,
984 bool isCalleeStructRet,
985 bool isCallerStructRet,
987 const SmallVectorImpl<ISD::OutputArg> &Outs,
988 const SmallVectorImpl<SDValue> &OutVals,
989 const SmallVectorImpl<ISD::InputArg> &Ins,
990 SelectionDAG& DAG) const;
991 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
992 SDValue Chain, bool IsTailCall, bool Is64Bit,
993 int FPDiff, SDLoc dl) const;
995 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
996 SelectionDAG &DAG) const;
998 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
1000 bool isReplace) const;
1002 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1003 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
1004 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
1005 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1006 SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const;
1007 SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const;
1009 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1010 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1011 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1012 SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
1013 int64_t Offset, SelectionDAG &DAG) const;
1014 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1015 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1016 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
1017 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1018 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1019 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
1020 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
1021 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
1022 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1023 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
1024 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
1025 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
1026 SDLoc dl, SelectionDAG &DAG) const;
1027 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1028 SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) const;
1029 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
1030 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
1031 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1032 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1033 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1034 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1035 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1036 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1037 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1038 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
1039 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1040 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1041 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1042 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1043 SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
1044 SDValue LowerGC_TRANSITION_START(SDValue Op, SelectionDAG &DAG) const;
1045 SDValue LowerGC_TRANSITION_END(SDValue Op, SelectionDAG &DAG) const;
1048 LowerFormalArguments(SDValue Chain,
1049 CallingConv::ID CallConv, bool isVarArg,
1050 const SmallVectorImpl<ISD::InputArg> &Ins,
1051 SDLoc dl, SelectionDAG &DAG,
1052 SmallVectorImpl<SDValue> &InVals) const override;
1053 SDValue LowerCall(CallLoweringInfo &CLI,
1054 SmallVectorImpl<SDValue> &InVals) const override;
1056 SDValue LowerReturn(SDValue Chain,
1057 CallingConv::ID CallConv, bool isVarArg,
1058 const SmallVectorImpl<ISD::OutputArg> &Outs,
1059 const SmallVectorImpl<SDValue> &OutVals,
1060 SDLoc dl, SelectionDAG &DAG) const override;
1062 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1064 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
1066 EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1067 ISD::NodeType ExtendKind) const override;
1069 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1071 const SmallVectorImpl<ISD::OutputArg> &Outs,
1072 LLVMContext &Context) const override;
1074 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1076 TargetLoweringBase::AtomicExpansionKind
1077 shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
1078 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
1079 TargetLoweringBase::AtomicExpansionKind
1080 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
1083 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
1085 bool needsCmpXchgNb(Type *MemType) const;
1087 // Utility function to emit the low-level va_arg code for X86-64.
1088 MachineBasicBlock *EmitVAARG64WithCustomInserter(
1090 MachineBasicBlock *MBB) const;
1092 /// Utility function to emit the xmm reg save portion of va_start.
1093 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
1094 MachineInstr *BInstr,
1095 MachineBasicBlock *BB) const;
1097 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
1098 MachineBasicBlock *BB) const;
1100 MachineBasicBlock *EmitLoweredAtomicFP(MachineInstr *I,
1101 MachineBasicBlock *BB) const;
1103 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
1104 MachineBasicBlock *BB) const;
1106 MachineBasicBlock *EmitLoweredCatchRet(MachineInstr *MI,
1107 MachineBasicBlock *BB) const;
1109 MachineBasicBlock *EmitLoweredCatchPad(MachineInstr *MI,
1110 MachineBasicBlock *BB) const;
1112 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
1113 MachineBasicBlock *BB) const;
1115 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
1116 MachineBasicBlock *BB) const;
1118 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
1119 MachineBasicBlock *MBB) const;
1121 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
1122 MachineBasicBlock *MBB) const;
1124 MachineBasicBlock *emitFMA3Instr(MachineInstr *MI,
1125 MachineBasicBlock *MBB) const;
1127 /// Emit nodes that will be selected as "test Op0,Op0", or something
1128 /// equivalent, for use with the given x86 condition code.
1129 SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl,
1130 SelectionDAG &DAG) const;
1132 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
1133 /// equivalent, for use with the given x86 condition code.
1134 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl,
1135 SelectionDAG &DAG) const;
1137 /// Convert a comparison if required by the subtarget.
1138 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
1140 /// Use rsqrt* to speed up sqrt calculations.
1141 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1142 unsigned &RefinementSteps,
1143 bool &UseOneConstNR) const override;
1145 /// Use rcp* to speed up fdiv calculations.
1146 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1147 unsigned &RefinementSteps) const override;
1149 /// Reassociate floating point divisions into multiply by reciprocal.
1150 unsigned combineRepeatedFPDivisors() const override;
1154 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1155 const TargetLibraryInfo *libInfo);
1159 #endif // X86ISELLOWERING_H