1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
28 // X86 Specific DAG Nodes
30 // Start the numbering where the builtin ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 /// BSF - Bit scan forward.
34 /// BSR - Bit scan reverse.
38 /// SHLD, SHRD - Double shift instructions. These correspond to
39 /// X86::SHLDxx and X86::SHRDxx instructions.
43 /// FAND - Bitwise logical AND of floating point values. This corresponds
44 /// to X86::ANDPS or X86::ANDPD.
47 /// FOR - Bitwise logical OR of floating point values. This corresponds
48 /// to X86::ORPS or X86::ORPD.
51 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
52 /// to X86::XORPS or X86::XORPD.
55 /// FSRL - Bitwise logical right shift of floating point values. These
56 /// corresponds to X86::PSRLDQ.
59 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
60 /// integer source in memory and FP reg result. This corresponds to the
61 /// X86::FILD*m instructions. It has three inputs (token chain, address,
62 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
63 /// also produces a flag).
67 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
68 /// integer destination in memory and a FP reg source. This corresponds
69 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
70 /// has two inputs (token chain and address) and two outputs (int value
76 /// FLD - This instruction implements an extending load to FP stack slots.
77 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
78 /// operand, ptr to load from, and a ValueType node indicating the type
82 /// FST - This instruction implements a truncating store to FP stack
83 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
84 /// chain operand, value to store, address, and a ValueType to store it
88 /// CALL/TAILCALL - These operations represent an abstract X86 call
89 /// instruction, which includes a bunch of information. In particular the
90 /// operands of these node are:
92 /// #0 - The incoming token chain
94 /// #2 - The number of arg bytes the caller pushes on the stack.
95 /// #3 - The number of arg bytes the callee pops off the stack.
96 /// #4 - The value to pass in AL/AX/EAX (optional)
97 /// #5 - The value to pass in DL/DX/EDX (optional)
99 /// The result values of these nodes are:
101 /// #0 - The outgoing token chain
102 /// #1 - The first register result value (optional)
103 /// #2 - The second register result value (optional)
105 /// The CALL vs TAILCALL distinction boils down to whether the callee is
106 /// known not to modify the caller's stack frame, as is standard with
111 /// RDTSC_DAG - This operation implements the lowering for
115 /// X86 compare and logical compare instructions.
118 /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
119 /// operand produced by a CMP instruction.
122 /// X86 conditional moves. Operand 1 and operand 2 are the two values
123 /// to select from (operand 1 is a R/W operand). Operand 3 is the
124 /// condition code, and operand 4 is the flag operand produced by a CMP
125 /// or TEST instruction. It also writes a flag result.
128 /// X86 conditional branches. Operand 1 is the chain operand, operand 2
129 /// is the block to branch if condition is true, operand 3 is the
130 /// condition code, and operand 4 is the flag operand produced by a CMP
131 /// or TEST instruction.
134 /// Return with a flag operand. Operand 1 is the chain operand, operand
135 /// 2 is the number of bytes of stack to pop.
138 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
141 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
144 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
145 /// at function entry, used for PIC code.
148 /// Wrapper - A wrapper node for TargetConstantPool,
149 /// TargetExternalSymbol, and TargetGlobalAddress.
152 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
153 /// relative displacements.
156 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
157 /// i32, corresponds to X86::PEXTRB.
160 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
161 /// i32, corresponds to X86::PEXTRW.
164 /// INSERTPS - Insert any element of a 4 x float vector into any element
165 /// of a destination 4 x floatvector.
168 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
169 /// corresponds to X86::PINSRB.
172 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
173 /// corresponds to X86::PINSRW.
176 /// FMAX, FMIN - Floating point max and min.
180 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
181 /// approximation. Note that these typically require refinement
182 /// in order to obtain suitable precision.
185 // TLSADDR, THREAThread - Thread Local Storage.
186 TLSADDR, THREAD_POINTER,
188 // EH_RETURN - Exception Handling helpers.
191 /// TC_RETURN - Tail call return.
193 /// operand #1 callee (register or absolute)
194 /// operand #2 stack adjustment
195 /// operand #3 optional in flag
198 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
202 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
203 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
204 // Atomic 64-bit binary operations.
213 // FNSTCW16m - Store FP control world into i16 memory.
216 // VZEXT_MOVL - Vector move low and zero extend.
219 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
222 // VSHL, VSRL - Vector logical left / right shift.
225 // CMPPD, CMPPS - Vector double/float comparison.
228 // PCMP* - Vector integer comparisons.
229 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
230 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ
234 /// Define some predicates that are used for node matching.
236 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
237 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
238 bool isPSHUFDMask(SDNode *N);
240 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
241 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
242 bool isPSHUFHWMask(SDNode *N);
244 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
245 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
246 bool isPSHUFLWMask(SDNode *N);
248 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
249 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
250 bool isSHUFPMask(SDNode *N);
252 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
253 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
254 bool isMOVHLPSMask(SDNode *N);
256 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
257 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
259 bool isMOVHLPS_v_undef_Mask(SDNode *N);
261 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
262 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
263 bool isMOVLPMask(SDNode *N);
265 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
266 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
267 /// as well as MOVLHPS.
268 bool isMOVHPMask(SDNode *N);
270 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
271 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
272 bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false);
274 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
275 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
276 bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false);
278 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
279 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
281 bool isUNPCKL_v_undef_Mask(SDNode *N);
283 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
284 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
286 bool isUNPCKH_v_undef_Mask(SDNode *N);
288 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
289 /// specifies a shuffle of elements that is suitable for input to MOVSS,
290 /// MOVSD, and MOVD, i.e. setting the lowest element.
291 bool isMOVLMask(SDNode *N);
293 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
294 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
295 bool isMOVSHDUPMask(SDNode *N);
297 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
298 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
299 bool isMOVSLDUPMask(SDNode *N);
301 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
302 /// specifies a splat of a single element.
303 bool isSplatMask(SDNode *N);
305 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
306 /// specifies a splat of zero element.
307 bool isSplatLoMask(SDNode *N);
309 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
310 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
311 bool isMOVDDUPMask(SDNode *N);
313 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
314 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
316 unsigned getShuffleSHUFImmediate(SDNode *N);
318 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
319 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
321 unsigned getShufflePSHUFHWImmediate(SDNode *N);
323 /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
324 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
326 unsigned getShufflePSHUFLWImmediate(SDNode *N);
329 //===--------------------------------------------------------------------===//
330 // X86TargetLowering - X86 Implementation of the TargetLowering interface
331 class X86TargetLowering : public TargetLowering {
332 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
333 int RegSaveFrameIndex; // X86-64 vararg func register save area.
334 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
335 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
336 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
337 int BytesCallerReserves; // Number of arg bytes caller makes.
340 explicit X86TargetLowering(X86TargetMachine &TM);
342 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
344 SDValue getPICJumpTableRelocBase(SDValue Table,
345 SelectionDAG &DAG) const;
347 // Return the number of bytes that a function should pop when it returns (in
348 // addition to the space used by the return address).
350 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
352 // Return the number of bytes that the caller reserves for arguments passed
354 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
356 /// getStackPtrReg - Return the stack pointer register we are using: either
358 unsigned getStackPtrReg() const { return X86StackPtr; }
360 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
361 /// function arguments in the caller parameter area. For X86, aggregates
362 /// that contains are placed at 16-byte boundaries while the rest are at
363 /// 4-byte boundaries.
364 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
366 /// getOptimalMemOpType - Returns the target specific optimal type for load
367 /// and store operations as a result of memset, memcpy, and memmove
368 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
371 MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
372 bool isSrcConst, bool isSrcStr) const;
374 /// LowerOperation - Provide custom lowering hooks for some operations.
376 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
378 /// ReplaceNodeResults - Replace a node with an illegal result type
379 /// with a new node built out of custom code.
381 virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG);
384 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
386 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
387 MachineBasicBlock *MBB);
390 /// getTargetNodeName - This method returns the name of a target specific
392 virtual const char *getTargetNodeName(unsigned Opcode) const;
394 /// getSetCCResultType - Return the ISD::SETCC ValueType
395 virtual MVT getSetCCResultType(const SDValue &) const;
397 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
398 /// in Mask are known to be either zero or one and return them in the
399 /// KnownZero/KnownOne bitsets.
400 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
404 const SelectionDAG &DAG,
405 unsigned Depth = 0) const;
408 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
410 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG);
412 ConstraintType getConstraintType(const std::string &Constraint) const;
414 std::vector<unsigned>
415 getRegClassForInlineAsmConstraint(const std::string &Constraint,
418 virtual const char *LowerXConstraint(MVT ConstraintVT) const;
420 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
421 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
422 /// true it means one of the asm constraint of the inline asm instruction
423 /// being processed is 'm'.
424 virtual void LowerAsmOperandForConstraint(SDValue Op,
425 char ConstraintLetter,
427 std::vector<SDValue> &Ops,
428 SelectionDAG &DAG) const;
430 /// getRegForInlineAsmConstraint - Given a physical register constraint
431 /// (e.g. {edx}), return the register number and the register class for the
432 /// register. This should only be used for C_Register constraints. On
433 /// error, this returns a register number of 0.
434 std::pair<unsigned, const TargetRegisterClass*>
435 getRegForInlineAsmConstraint(const std::string &Constraint,
438 /// isLegalAddressingMode - Return true if the addressing mode represented
439 /// by AM is legal for this target, for a load/store of the specified type.
440 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
442 /// isTruncateFree - Return true if it's free to truncate a value of
443 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
444 /// register EAX to i16 by referencing its sub-register AX.
445 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
446 virtual bool isTruncateFree(MVT VT1, MVT VT2) const;
448 /// isShuffleMaskLegal - Targets can use this to indicate that they only
449 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
450 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
451 /// values are assumed to be legal.
452 virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const;
454 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
455 /// used by Targets can use this to indicate if there is a suitable
456 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
458 virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
459 MVT EVT, SelectionDAG &DAG) const;
461 /// ShouldShrinkFPConstant - If true, then instruction selection should
462 /// seek to shrink the FP constant of the specified type to a smaller type
463 /// in order to save space and / or reduce runtime.
464 virtual bool ShouldShrinkFPConstant(MVT VT) const {
465 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
466 // expensive than a straight movsd. On the other hand, it's important to
467 // shrink long double fp constant since fldt is very slow.
468 return !X86ScalarSSEf64 || VT == MVT::f80;
471 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
472 /// for tail call optimization. Target which want to do tail call
473 /// optimization should implement this function.
474 virtual bool IsEligibleForTailCallOptimization(CallSDNode *TheCall,
476 SelectionDAG &DAG) const;
478 virtual const X86Subtarget* getSubtarget() {
482 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
483 /// computed in an SSE register, not on the X87 floating point stack.
484 bool isScalarFPTypeInSSEReg(MVT VT) const {
485 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
486 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
489 /// getWidenVectorType: given a vector type, returns the type to widen
490 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
491 /// If there is no vector type that we want to widen to, returns MVT::Other
492 /// When and were to widen is target dependent based on the cost of
493 /// scalarizing vs using the wider vector type.
494 virtual MVT getWidenVectorType(MVT VT);
496 /// createFastISel - This method returns a target specific FastISel object,
497 /// or null if the target does not support "fast" ISel.
499 createFastISel(MachineFunction &mf,
500 MachineModuleInfo *mmi,
501 DenseMap<const Value *, unsigned> &,
502 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
503 DenseMap<const AllocaInst *, int> &
505 , SmallSet<Instruction*, 8> &
510 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
511 /// make the right decision when generating code for different targets.
512 const X86Subtarget *Subtarget;
513 const X86RegisterInfo *RegInfo;
514 const TargetData *TD;
516 /// X86StackPtr - X86 physical register used as stack ptr.
517 unsigned X86StackPtr;
519 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
520 /// floating point ops.
521 /// When SSE is available, use it for f32 operations.
522 /// When SSE2 is available, use it for f64 operations.
523 bool X86ScalarSSEf32;
524 bool X86ScalarSSEf64;
526 SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
527 unsigned CallingConv, SelectionDAG &DAG);
529 SDValue LowerMemArgument(SDValue Op, SelectionDAG &DAG,
530 const CCValAssign &VA, MachineFrameInfo *MFI,
531 unsigned CC, SDValue Root, unsigned i);
533 SDValue LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
534 const SDValue &StackPtr,
535 const CCValAssign &VA, SDValue Chain,
536 SDValue Arg, ISD::ArgFlagsTy Flags);
538 // Call lowering helpers.
539 bool IsCalleePop(bool isVarArg, unsigned CallingConv);
540 bool CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall);
541 bool CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall);
542 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
543 SDValue Chain, bool IsTailCall, bool Is64Bit,
546 CCAssignFn *CCAssignFnForNode(unsigned CallingConv) const;
547 NameDecorationStyle NameDecorationForFORMAL_ARGUMENTS(SDValue Op);
548 unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG);
550 std::pair<SDValue,SDValue> FP_TO_SINTHelper(SDValue Op,
553 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG);
554 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG);
555 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG);
556 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
557 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG);
558 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
559 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
560 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
561 SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
562 SelectionDAG &DAG) const;
563 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
564 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
565 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG);
566 SDValue LowerShift(SDValue Op, SelectionDAG &DAG);
567 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
568 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG);
569 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG);
570 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG);
571 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG);
572 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG);
573 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
574 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG);
575 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG);
576 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG);
577 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG);
578 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
579 SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
580 SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
581 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
582 SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
583 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG);
584 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG);
585 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG);
586 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
587 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
588 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
589 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG);
590 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG);
591 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG);
592 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
593 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG);
594 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG);
595 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG);
596 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG);
597 SDValue LowerATOMIC_BINARY_64(SDValue Op, SelectionDAG &DAG,
599 SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
600 SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG);
601 SDNode *ExpandATOMIC_CMP_SWAP(SDNode *N, SelectionDAG &DAG);
603 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG,
605 SDValue Dst, SDValue Src,
606 SDValue Size, unsigned Align,
607 const Value *DstSV, uint64_t DstSVOff);
608 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG,
610 SDValue Dst, SDValue Src,
611 SDValue Size, unsigned Align,
613 const Value *DstSV, uint64_t DstSVOff,
614 const Value *SrcSV, uint64_t SrcSVOff);
616 /// Utility function to emit atomic bitwise operations (and, or, xor).
617 // It takes the bitwise instruction to expand, the associated machine basic
618 // block, and the associated X86 opcodes for reg/reg and reg/imm.
619 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
620 MachineInstr *BInstr,
621 MachineBasicBlock *BB,
629 TargetRegisterClass *RC,
630 bool invSrc = false);
632 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
633 MachineInstr *BInstr,
634 MachineBasicBlock *BB,
639 bool invSrc = false);
641 /// Utility function to emit atomic min and max. It takes the min/max
642 // instruction to expand, the associated basic block, and the associated
643 // cmov opcode for moving the min or max value.
644 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
645 MachineBasicBlock *BB,
650 FastISel *createFastISel(MachineFunction &mf,
651 MachineModuleInfo *mmi,
652 DenseMap<const Value *, unsigned> &,
653 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
654 DenseMap<const AllocaInst *, int> &
656 , SmallSet<Instruction*, 8> &
662 #endif // X86ISELLOWERING_H