1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetOptions.h"
25 class X86TargetMachine;
28 // X86 Specific DAG Nodes
30 // Start the numbering where the builtin ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 /// BSF - Bit scan forward.
34 /// BSR - Bit scan reverse.
38 /// SHLD, SHRD - Double shift instructions. These correspond to
39 /// X86::SHLDxx and X86::SHRDxx instructions.
43 /// FAND - Bitwise logical AND of floating point values. This corresponds
44 /// to X86::ANDPS or X86::ANDPD.
47 /// FOR - Bitwise logical OR of floating point values. This corresponds
48 /// to X86::ORPS or X86::ORPD.
51 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
52 /// to X86::XORPS or X86::XORPD.
55 /// FANDN - Bitwise logical ANDNOT of floating point values. This
56 /// corresponds to X86::ANDNPS or X86::ANDNPD.
59 /// FSRL - Bitwise logical right shift of floating point values. These
60 /// corresponds to X86::PSRLDQ.
63 /// CALL - These operations represent an abstract X86 call
64 /// instruction, which includes a bunch of information. In particular the
65 /// operands of these node are:
67 /// #0 - The incoming token chain
69 /// #2 - The number of arg bytes the caller pushes on the stack.
70 /// #3 - The number of arg bytes the callee pops off the stack.
71 /// #4 - The value to pass in AL/AX/EAX (optional)
72 /// #5 - The value to pass in DL/DX/EDX (optional)
74 /// The result values of these nodes are:
76 /// #0 - The outgoing token chain
77 /// #1 - The first register result value (optional)
78 /// #2 - The second register result value (optional)
82 /// RDTSC_DAG - This operation implements the lowering for
86 /// X86 Read Time-Stamp Counter and Processor ID.
89 /// X86 Read Performance Monitoring Counters.
92 /// X86 compare and logical compare instructions.
95 /// X86 bit-test instructions.
98 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
99 /// operand, usually produced by a CMP instruction.
105 // Same as SETCC except it's materialized with a sbb and the value is all
106 // one's or all zero's.
107 SETCC_CARRY, // R = carry_bit ? ~0 : 0
109 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
110 /// Operands are two FP values to compare; result is a mask of
111 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
114 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
115 /// result in an integer GPR. Needs masking for scalar result.
118 /// X86 conditional moves. Operand 0 and operand 1 are the two values
119 /// to select from. Operand 2 is the condition code, and operand 3 is the
120 /// flag operand produced by a CMP or TEST instruction. It also writes a
124 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
125 /// is the block to branch if condition is true, operand 2 is the
126 /// condition code, and operand 3 is the flag operand produced by a CMP
127 /// or TEST instruction.
130 /// Return with a flag operand. Operand 0 is the chain operand, operand
131 /// 1 is the number of bytes of stack to pop.
134 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
137 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
140 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
141 /// at function entry, used for PIC code.
144 /// Wrapper - A wrapper node for TargetConstantPool,
145 /// TargetExternalSymbol, and TargetGlobalAddress.
148 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
149 /// relative displacements.
152 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
153 /// to an MMX vector. If you think this is too close to the previous
154 /// mnemonic, so do I; blame Intel.
157 /// MMX_MOVD2W - Copies a 32-bit value from the low word of a MMX
161 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
162 /// i32, corresponds to X86::PEXTRB.
165 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
166 /// i32, corresponds to X86::PEXTRW.
169 /// INSERTPS - Insert any element of a 4 x float vector into any element
170 /// of a destination 4 x floatvector.
173 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
174 /// corresponds to X86::PINSRB.
177 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
178 /// corresponds to X86::PINSRW.
181 /// PSHUFB - Shuffle 16 8-bit values within a vector.
184 /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
187 /// PSIGN - Copy integer sign.
190 /// BLENDI - Blend where the selector is an immediate.
193 /// SHRUNKBLEND - Blend where the condition has been shrunk.
194 /// This is used to emphasize that the condition mask is
195 /// no more valid for generic VSELECT optimizations.
198 /// ADDSUB - Combined add and sub on an FP vector.
201 // SUBUS - Integer sub with unsigned saturation.
204 /// HADD - Integer horizontal add.
207 /// HSUB - Integer horizontal sub.
210 /// FHADD - Floating point horizontal add.
213 /// FHSUB - Floating point horizontal sub.
216 /// UMAX, UMIN - Unsigned integer max and min.
219 /// SMAX, SMIN - Signed integer max and min.
222 /// FMAX, FMIN - Floating point max and min.
226 /// FMAXC, FMINC - Commutative FMIN and FMAX.
229 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
230 /// approximation. Note that these typically require refinement
231 /// in order to obtain suitable precision.
234 // TLSADDR - Thread Local Storage.
237 // TLSBASEADDR - Thread Local Storage. A call to get the start address
238 // of the TLS block for the current module.
241 // TLSCALL - Thread Local Storage. When calling to an OS provided
242 // thunk at the address from an earlier relocation.
245 // EH_RETURN - Exception Handling helpers.
248 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
251 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
254 /// TC_RETURN - Tail call return. See X86TargetLowering::LowerCall for
255 /// the list of operands.
258 // VZEXT_MOVL - Vector move to low scalar and zero higher vector elements.
261 // VZEXT - Vector integer zero-extend.
264 // VSEXT - Vector integer signed-extend.
267 // VTRUNC - Vector integer truncate.
270 // VTRUNC - Vector integer truncate with mask.
273 // VFPEXT - Vector FP extend.
276 // VFPROUND - Vector FP round.
279 // VSHL, VSRL - 128-bit vector logical left / right shift
282 // VSHL, VSRL, VSRA - Vector shift elements
285 // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate
288 // CMPP - Vector packed double/float comparison.
291 // PCMP* - Vector integer comparisons.
293 // PCMP*M - Vector integer comparisons, the result is in a mask vector.
296 /// CMPM, CMPMU - Vector comparison generating mask bits for fp and
297 /// integer signed and unsigned data types.
301 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
302 ADD, SUB, ADC, SBB, SMUL,
303 INC, DEC, OR, XOR, AND,
305 BEXTR, // BEXTR - Bit field extract
307 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
309 // 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS
312 // 8-bit divrem that zero-extend the high result (AH).
316 // MUL_IMM - X86 specific multiply by immediate.
319 // PTEST - Vector bitwise comparisons.
322 // TESTP - Vector packed fp sign bitwise comparisons.
325 // TESTM, TESTNM - Vector "test" in AVX-512, the result is in a mask vector.
329 // OR/AND test for masks
332 // Several flavors of instructions with vector shuffle behaviors.
337 // AVX512 inter-lane alignr
365 // Insert/Extract vector element
369 // Vector multiply packed unsigned doubleword integers
371 // Vector multiply packed signed doubleword integers
382 // Save xmm argument registers to the stack, according to %al. An operator
383 // is needed so that this can be expanded with control flow.
384 VASTART_SAVE_XMM_REGS,
386 // Windows's _chkstk call to do stack probing.
389 // For allocating variable amounts of stack space when using
390 // segmented stacks. Check if the current stacklet has enough space, and
391 // falls back to heap allocation if not.
394 // Windows's _ftol2 runtime routine to do fptoui.
403 // Store FP status word into i16 register.
406 // Store contents of %ah into %eflags.
409 // Get a random integer and indicate whether it is valid in CF.
412 // Get a NIST SP800-90B & C compliant random integer and
413 // indicate whether it is valid in CF.
419 // Test if in transactional execution.
423 LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
427 // Load, scalar_to_vector, and zero extend.
430 // Store FP control world into i16 memory.
433 /// This instruction implements FP_TO_SINT with the
434 /// integer destination in memory and a FP reg source. This corresponds
435 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
436 /// has two inputs (token chain and address) and two outputs (int value
437 /// and token chain).
442 /// This instruction implements SINT_TO_FP with the
443 /// integer source in memory and FP reg result. This corresponds to the
444 /// X86::FILD*m instructions. It has three inputs (token chain, address,
445 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
446 /// also produces a flag).
450 /// This instruction implements an extending load to FP stack slots.
451 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
452 /// operand, ptr to load from, and a ValueType node indicating the type
456 /// This instruction implements a truncating store to FP stack
457 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
458 /// chain operand, value to store, address, and a ValueType to store it
462 /// This instruction grabs the address of the next argument
463 /// from a va_list. (reads and modifies the va_list in memory)
466 // WARNING: Do not add anything in the end unless you want the node to
467 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
468 // thought as target memory ops!
472 /// Define some predicates that are used for node matching.
474 /// Return true if the specified
475 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
476 /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
477 bool isVEXTRACT128Index(SDNode *N);
479 /// Return true if the specified
480 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
481 /// suitable for input to VINSERTF128, VINSERTI128 instructions.
482 bool isVINSERT128Index(SDNode *N);
484 /// Return true if the specified
485 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
486 /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
487 bool isVEXTRACT256Index(SDNode *N);
489 /// Return true if the specified
490 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
491 /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
492 bool isVINSERT256Index(SDNode *N);
494 /// Return the appropriate
495 /// immediate to extract the specified EXTRACT_SUBVECTOR index
496 /// with VEXTRACTF128, VEXTRACTI128 instructions.
497 unsigned getExtractVEXTRACT128Immediate(SDNode *N);
499 /// Return the appropriate
500 /// immediate to insert at the specified INSERT_SUBVECTOR index
501 /// with VINSERTF128, VINSERT128 instructions.
502 unsigned getInsertVINSERT128Immediate(SDNode *N);
504 /// Return the appropriate
505 /// immediate to extract the specified EXTRACT_SUBVECTOR index
506 /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
507 unsigned getExtractVEXTRACT256Immediate(SDNode *N);
509 /// Return the appropriate
510 /// immediate to insert at the specified INSERT_SUBVECTOR index
511 /// with VINSERTF64x4, VINSERTI64x4 instructions.
512 unsigned getInsertVINSERT256Immediate(SDNode *N);
514 /// Returns true if Elt is a constant zero or floating point constant +0.0.
515 bool isZeroNode(SDValue Elt);
517 /// Returns true of the given offset can be
518 /// fit into displacement field of the instruction.
519 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
520 bool hasSymbolicDisplacement = true);
523 /// Determines whether the callee is required to pop its
524 /// own arguments. Callee pop is necessary to support tail calls.
525 bool isCalleePop(CallingConv::ID CallingConv,
526 bool is64Bit, bool IsVarArg, bool TailCallOpt);
528 /// AVX512 static rounding constants. These need to match the values in
530 enum STATIC_ROUNDING {
539 //===--------------------------------------------------------------------===//
540 // X86 Implementation of the TargetLowering interface
541 class X86TargetLowering final : public TargetLowering {
543 explicit X86TargetLowering(const X86TargetMachine &TM);
545 unsigned getJumpTableEncoding() const override;
547 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i8; }
550 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
551 const MachineBasicBlock *MBB, unsigned uid,
552 MCContext &Ctx) const override;
554 /// Returns relocation base for the given PIC jumptable.
555 SDValue getPICJumpTableRelocBase(SDValue Table,
556 SelectionDAG &DAG) const override;
558 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
559 unsigned JTI, MCContext &Ctx) const override;
561 /// Return the desired alignment for ByVal aggregate
562 /// function arguments in the caller parameter area. For X86, aggregates
563 /// that contains are placed at 16-byte boundaries while the rest are at
564 /// 4-byte boundaries.
565 unsigned getByValTypeAlignment(Type *Ty) const override;
567 /// Returns the target specific optimal type for load
568 /// and store operations as a result of memset, memcpy, and memmove
569 /// lowering. If DstAlign is zero that means it's safe to destination
570 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
571 /// means there isn't a need to check it against alignment requirement,
572 /// probably because the source does not need to be loaded. If 'IsMemset' is
573 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
574 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
575 /// source is constant so it does not need to be loaded.
576 /// It returns EVT::Other if the type should be determined using generic
577 /// target-independent logic.
578 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
579 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
580 MachineFunction &MF) const override;
582 /// Returns true if it's safe to use load / store of the
583 /// specified type to expand memcpy / memset inline. This is mostly true
584 /// for all types except for some special cases. For example, on X86
585 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
586 /// also does type conversion. Note the specified type doesn't have to be
587 /// legal as the hook is used before type legalization.
588 bool isSafeMemOpType(MVT VT) const override;
590 /// Returns true if the target allows
591 /// unaligned memory accesses. of the specified type. Returns whether it
592 /// is "fast" by reference in the second argument.
593 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
594 bool *Fast) const override;
596 /// Provide custom lowering hooks for some operations.
598 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
600 /// Replace the results of node with an illegal result
601 /// type with new values built out of custom code.
603 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
604 SelectionDAG &DAG) const override;
607 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
609 /// Return true if the target has native support for
610 /// the specified value type and it is 'desirable' to use the type for the
611 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
612 /// instruction encodings are longer and some i16 instructions are slow.
613 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
615 /// Return true if the target has native support for the
616 /// specified value type and it is 'desirable' to use the type. e.g. On x86
617 /// i16 is legal, but undesirable since i16 instruction encodings are longer
618 /// and some i16 instructions are slow.
619 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
622 EmitInstrWithCustomInserter(MachineInstr *MI,
623 MachineBasicBlock *MBB) const override;
626 /// This method returns the name of a target specific DAG node.
627 const char *getTargetNodeName(unsigned Opcode) const override;
629 /// Return the value type to use for ISD::SETCC.
630 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
632 /// Determine which of the bits specified in Mask are known to be either
633 /// zero or one and return them in the KnownZero/KnownOne bitsets.
634 void computeKnownBitsForTargetNode(const SDValue Op,
637 const SelectionDAG &DAG,
638 unsigned Depth = 0) const override;
640 /// Determine the number of bits in the operation that are sign bits.
641 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
642 const SelectionDAG &DAG,
643 unsigned Depth) const override;
645 bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
646 int64_t &Offset) const override;
648 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
650 bool ExpandInlineAsm(CallInst *CI) const override;
653 getConstraintType(const std::string &Constraint) const override;
655 /// Examine constraint string and operand type and determine a weight value.
656 /// The operand object must already have been set up with the operand type.
658 getSingleConstraintMatchWeight(AsmOperandInfo &info,
659 const char *constraint) const override;
661 const char *LowerXConstraint(EVT ConstraintVT) const override;
663 /// Lower the specified operand into the Ops vector. If it is invalid, don't
664 /// add anything to Ops. If hasMemory is true it means one of the asm
665 /// constraint of the inline asm instruction being processed is 'm'.
666 void LowerAsmOperandForConstraint(SDValue Op,
667 std::string &Constraint,
668 std::vector<SDValue> &Ops,
669 SelectionDAG &DAG) const override;
671 /// Given a physical register constraint
672 /// (e.g. {edx}), return the register number and the register class for the
673 /// register. This should only be used for C_Register constraints. On
674 /// error, this returns a register number of 0.
675 std::pair<unsigned, const TargetRegisterClass*>
676 getRegForInlineAsmConstraint(const std::string &Constraint,
677 MVT VT) const override;
679 /// Return true if the addressing mode represented
680 /// by AM is legal for this target, for a load/store of the specified type.
681 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
683 /// Return true if the specified immediate is legal
684 /// icmp immediate, that is the target has icmp instructions which can
685 /// compare a register against the immediate without having to materialize
686 /// the immediate into a register.
687 bool isLegalICmpImmediate(int64_t Imm) const override;
689 /// Return true if the specified immediate is legal
690 /// add immediate, that is the target has add instructions which can
691 /// add a register and the immediate without having to materialize
692 /// the immediate into a register.
693 bool isLegalAddImmediate(int64_t Imm) const override;
695 /// \brief Return the cost of the scaling factor used in the addressing
696 /// mode represented by AM for this target, for a load/store
697 /// of the specified type.
698 /// If the AM is supported, the return value must be >= 0.
699 /// If the AM is not supported, it returns a negative value.
700 int getScalingFactorCost(const AddrMode &AM, Type *Ty) const override;
702 bool isVectorShiftByScalarCheap(Type *Ty) const override;
704 /// Return true if it's free to truncate a value of
705 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
706 /// register EAX to i16 by referencing its sub-register AX.
707 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
708 bool isTruncateFree(EVT VT1, EVT VT2) const override;
710 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
712 /// Return true if any actual instruction that defines a
713 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
714 /// register. This does not necessarily include registers defined in
715 /// unknown ways, such as incoming arguments, or copies from unknown
716 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
717 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
718 /// all instructions that define 32-bit values implicit zero-extend the
719 /// result out to 64 bits.
720 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
721 bool isZExtFree(EVT VT1, EVT VT2) const override;
722 bool isZExtFree(SDValue Val, EVT VT2) const override;
724 /// Return true if an FMA operation is faster than a pair of fmul and fadd
725 /// instructions. fmuladd intrinsics will be expanded to FMAs when this
726 /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
727 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
729 /// Return true if it's profitable to narrow
730 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
731 /// from i32 to i8 but not from i32 to i16.
732 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
734 /// Returns true if the target can instruction select the
735 /// specified FP immediate natively. If false, the legalizer will
736 /// materialize the FP immediate as a load from a constant pool.
737 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
739 /// Targets can use this to indicate that they only support *some*
740 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
741 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
743 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
744 EVT VT) const override;
746 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
747 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to
748 /// replace a VAND with a constant pool entry.
749 bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
750 EVT VT) const override;
752 /// If true, then instruction selection should
753 /// seek to shrink the FP constant of the specified type to a smaller type
754 /// in order to save space and / or reduce runtime.
755 bool ShouldShrinkFPConstant(EVT VT) const override {
756 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
757 // expensive than a straight movsd. On the other hand, it's important to
758 // shrink long double fp constant since fldt is very slow.
759 return !X86ScalarSSEf64 || VT == MVT::f80;
762 const X86Subtarget* getSubtarget() const {
766 /// Return true if the specified scalar FP type is computed in an SSE
767 /// register, not on the X87 floating point stack.
768 bool isScalarFPTypeInSSEReg(EVT VT) const {
769 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
770 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
773 /// Return true if the target uses the MSVC _ftol2 routine for fptoui.
774 bool isTargetFTOL() const;
776 /// Return true if the MSVC _ftol2 routine should be used for fptoui to the
778 bool isIntegerTypeFTOL(EVT VT) const {
779 return isTargetFTOL() && VT == MVT::i64;
782 /// \brief Returns true if it is beneficial to convert a load of a constant
783 /// to just the constant itself.
784 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
785 Type *Ty) const override;
787 /// Intel processors have a unified instruction and data cache
788 const char * getClearCacheBuiltinName() const override {
789 return nullptr; // nothing to do, move along.
792 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
794 /// This method returns a target specific FastISel object,
795 /// or null if the target does not support "fast" ISel.
796 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
797 const TargetLibraryInfo *libInfo) const override;
799 /// Return true if the target stores stack protector cookies at a fixed
800 /// offset in some non-standard address space, and populates the address
801 /// space and offset as appropriate.
802 bool getStackCookieLocation(unsigned &AddressSpace,
803 unsigned &Offset) const override;
805 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
806 SelectionDAG &DAG) const;
808 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
810 /// \brief Reset the operation actions based on target options.
811 void resetOperationActions() override;
813 bool useLoadStackGuardNode() const override;
814 /// \brief Customize the preferred legalization strategy for certain types.
815 LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
818 std::pair<const TargetRegisterClass*, uint8_t>
819 findRepresentativeClass(MVT VT) const override;
822 /// Keep a pointer to the X86Subtarget around so that we can
823 /// make the right decision when generating code for different targets.
824 const X86Subtarget *Subtarget;
825 const DataLayout *TD;
827 /// Used to store the TargetOptions so that we don't waste time resetting
828 /// the operation actions unless we have to.
831 /// Select between SSE or x87 floating point ops.
832 /// When SSE is available, use it for f32 operations.
833 /// When SSE2 is available, use it for f64 operations.
834 bool X86ScalarSSEf32;
835 bool X86ScalarSSEf64;
837 /// A list of legal FP immediates.
838 std::vector<APFloat> LegalFPImmediates;
840 /// Indicate that this x86 target can instruction
841 /// select the specified FP immediate natively.
842 void addLegalFPImmediate(const APFloat& Imm) {
843 LegalFPImmediates.push_back(Imm);
846 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
847 CallingConv::ID CallConv, bool isVarArg,
848 const SmallVectorImpl<ISD::InputArg> &Ins,
849 SDLoc dl, SelectionDAG &DAG,
850 SmallVectorImpl<SDValue> &InVals) const;
851 SDValue LowerMemArgument(SDValue Chain,
852 CallingConv::ID CallConv,
853 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
854 SDLoc dl, SelectionDAG &DAG,
855 const CCValAssign &VA, MachineFrameInfo *MFI,
857 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
858 SDLoc dl, SelectionDAG &DAG,
859 const CCValAssign &VA,
860 ISD::ArgFlagsTy Flags) const;
862 // Call lowering helpers.
864 /// Check whether the call is eligible for tail call optimization. Targets
865 /// that want to do tail call optimization should implement this function.
866 bool IsEligibleForTailCallOptimization(SDValue Callee,
867 CallingConv::ID CalleeCC,
869 bool isCalleeStructRet,
870 bool isCallerStructRet,
872 const SmallVectorImpl<ISD::OutputArg> &Outs,
873 const SmallVectorImpl<SDValue> &OutVals,
874 const SmallVectorImpl<ISD::InputArg> &Ins,
875 SelectionDAG& DAG) const;
876 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
877 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
878 SDValue Chain, bool IsTailCall, bool Is64Bit,
879 int FPDiff, SDLoc dl) const;
881 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
882 SelectionDAG &DAG) const;
884 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
886 bool isReplace) const;
888 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
889 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
890 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
891 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
892 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
893 SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const;
894 SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const;
896 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
897 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
898 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
899 SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
900 int64_t Offset, SelectionDAG &DAG) const;
901 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
902 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
903 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
904 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
905 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
906 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
907 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
908 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
909 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
910 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
911 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
912 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
913 SDLoc dl, SelectionDAG &DAG) const;
914 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
915 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
916 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
917 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
918 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
919 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
920 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
921 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
922 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
923 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
924 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
925 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
926 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
927 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
928 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
929 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
930 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
931 SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
934 LowerFormalArguments(SDValue Chain,
935 CallingConv::ID CallConv, bool isVarArg,
936 const SmallVectorImpl<ISD::InputArg> &Ins,
937 SDLoc dl, SelectionDAG &DAG,
938 SmallVectorImpl<SDValue> &InVals) const override;
939 SDValue LowerCall(CallLoweringInfo &CLI,
940 SmallVectorImpl<SDValue> &InVals) const override;
942 SDValue LowerReturn(SDValue Chain,
943 CallingConv::ID CallConv, bool isVarArg,
944 const SmallVectorImpl<ISD::OutputArg> &Outs,
945 const SmallVectorImpl<SDValue> &OutVals,
946 SDLoc dl, SelectionDAG &DAG) const override;
948 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
950 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
952 EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
953 ISD::NodeType ExtendKind) const override;
955 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
957 const SmallVectorImpl<ISD::OutputArg> &Outs,
958 LLVMContext &Context) const override;
960 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
962 bool shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
963 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
964 bool shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
967 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
969 bool needsCmpXchgNb(const Type *MemType) const;
971 /// Utility function to emit atomic-load-arith operations (and, or, xor,
972 /// nand, max, min, umax, umin). It takes the corresponding instruction to
973 /// expand, the associated machine basic block, and the associated X86
974 /// opcodes for reg/reg.
975 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
976 MachineBasicBlock *MBB) const;
978 /// Utility function to emit atomic-load-arith operations (and, or, xor,
979 /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
980 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
981 MachineBasicBlock *MBB) const;
983 // Utility function to emit the low-level va_arg code for X86-64.
984 MachineBasicBlock *EmitVAARG64WithCustomInserter(
986 MachineBasicBlock *MBB) const;
988 /// Utility function to emit the xmm reg save portion of va_start.
989 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
990 MachineInstr *BInstr,
991 MachineBasicBlock *BB) const;
993 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
994 MachineBasicBlock *BB) const;
996 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
997 MachineBasicBlock *BB) const;
999 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
1000 MachineBasicBlock *BB) const;
1002 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
1003 MachineBasicBlock *BB) const;
1005 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
1006 MachineBasicBlock *BB) const;
1008 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
1009 MachineBasicBlock *MBB) const;
1011 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
1012 MachineBasicBlock *MBB) const;
1014 MachineBasicBlock *emitFMA3Instr(MachineInstr *MI,
1015 MachineBasicBlock *MBB) const;
1017 /// Emit nodes that will be selected as "test Op0,Op0", or something
1018 /// equivalent, for use with the given x86 condition code.
1019 SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl,
1020 SelectionDAG &DAG) const;
1022 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
1023 /// equivalent, for use with the given x86 condition code.
1024 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl,
1025 SelectionDAG &DAG) const;
1027 /// Convert a comparison if required by the subtarget.
1028 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
1030 /// Use rsqrt* to speed up sqrt calculations.
1031 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1032 unsigned &RefinementSteps,
1033 bool &UseOneConstNR) const override;
1037 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1038 const TargetLibraryInfo *libInfo);
1042 #endif // X86ISELLOWERING_H