1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
29 // X86 Specific DAG Nodes
31 // Start the numbering where the builtin ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 /// BSF - Bit scan forward.
35 /// BSR - Bit scan reverse.
39 /// SHLD, SHRD - Double shift instructions. These correspond to
40 /// X86::SHLDxx and X86::SHRDxx instructions.
44 /// FAND - Bitwise logical AND of floating point values. This corresponds
45 /// to X86::ANDPS or X86::ANDPD.
48 /// FOR - Bitwise logical OR of floating point values. This corresponds
49 /// to X86::ORPS or X86::ORPD.
52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
53 /// to X86::XORPS or X86::XORPD.
56 /// FSRL - Bitwise logical right shift of floating point values. These
57 /// corresponds to X86::PSRLDQ.
60 /// CALL - These operations represent an abstract X86 call
61 /// instruction, which includes a bunch of information. In particular the
62 /// operands of these node are:
64 /// #0 - The incoming token chain
66 /// #2 - The number of arg bytes the caller pushes on the stack.
67 /// #3 - The number of arg bytes the callee pops off the stack.
68 /// #4 - The value to pass in AL/AX/EAX (optional)
69 /// #5 - The value to pass in DL/DX/EDX (optional)
71 /// The result values of these nodes are:
73 /// #0 - The outgoing token chain
74 /// #1 - The first register result value (optional)
75 /// #2 - The second register result value (optional)
79 /// RDTSC_DAG - This operation implements the lowering for
83 /// X86 compare and logical compare instructions.
86 /// X86 bit-test instructions.
89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
90 /// operand, usually produced by a CMP instruction.
93 // Same as SETCC except it's materialized with a sbb and the value is all
94 // one's or all zero's.
95 SETCC_CARRY, // R = carry_bit ? ~0 : 0
97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
98 /// Operands are two FP values to compare; result is a mask of
99 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
102 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
103 /// result in an integer GPR. Needs masking for scalar result.
106 /// X86 conditional moves. Operand 0 and operand 1 are the two values
107 /// to select from. Operand 2 is the condition code, and operand 3 is the
108 /// flag operand produced by a CMP or TEST instruction. It also writes a
112 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
113 /// is the block to branch if condition is true, operand 2 is the
114 /// condition code, and operand 3 is the flag operand produced by a CMP
115 /// or TEST instruction.
118 /// Return with a flag operand. Operand 0 is the chain operand, operand
119 /// 1 is the number of bytes of stack to pop.
122 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
125 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
128 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
129 /// at function entry, used for PIC code.
132 /// Wrapper - A wrapper node for TargetConstantPool,
133 /// TargetExternalSymbol, and TargetGlobalAddress.
136 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
137 /// relative displacements.
140 /// MOVQ2DQ - Copies a 64-bit value from an MMX vector to the low word
141 /// of an XMM vector, with the high word zero filled.
144 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
145 /// to an MMX vector. If you think this is too close to the previous
146 /// mnemonic, so do I; blame Intel.
149 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
150 /// i32, corresponds to X86::PEXTRB.
153 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
154 /// i32, corresponds to X86::PEXTRW.
157 /// INSERTPS - Insert any element of a 4 x float vector into any element
158 /// of a destination 4 x floatvector.
161 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
162 /// corresponds to X86::PINSRB.
165 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
166 /// corresponds to X86::PINSRW.
169 /// PSHUFB - Shuffle 16 8-bit values within a vector.
172 /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
175 /// PSIGNB/W/D - Copy integer sign.
176 PSIGNB, PSIGNW, PSIGND,
178 /// BLENDVXX family of opcodes
183 /// FMAX, FMIN - Floating point max and min.
187 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
188 /// approximation. Note that these typically require refinement
189 /// in order to obtain suitable precision.
192 // TLSADDR - Thread Local Storage.
195 // TLSCALL - Thread Local Storage. When calling to an OS provided
196 // thunk at the address from an earlier relocation.
199 // EH_RETURN - Exception Handling helpers.
202 /// TC_RETURN - Tail call return.
204 /// operand #1 callee (register or absolute)
205 /// operand #2 stack adjustment
206 /// operand #3 optional in flag
209 // VZEXT_MOVL - Vector move low and zero extend.
212 // VSHL, VSRL - Vector logical left / right shift.
215 // CMPPD, CMPPS - Vector double/float comparison.
216 // CMPPD, CMPPS - Vector double/float comparison.
219 // PCMP* - Vector integer comparisons.
220 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
221 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
223 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
224 ADD, SUB, ADC, SBB, SMUL,
225 INC, DEC, OR, XOR, AND,
227 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
229 // MUL_IMM - X86 specific multiply by immediate.
232 // PTEST - Vector bitwise comparisons
235 // TESTP - Vector packed fp sign bitwise comparisons
238 // Several flavors of instructions with vector shuffle behaviors.
283 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
284 // according to %al. An operator is needed so that this can be expanded
285 // with control flow.
286 VASTART_SAVE_XMM_REGS,
288 // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
291 // SEG_ALLOCA - For allocating variable amounts of stack space when using
292 // segmented stacks. Check if the current stacklet has enough space, and
293 // falls back to heap allocation if not.
302 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
303 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
304 // Atomic 64-bit binary operations.
305 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
313 // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
318 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
321 // FNSTCW16m - Store FP control world into i16 memory.
324 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
325 /// integer destination in memory and a FP reg source. This corresponds
326 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
327 /// has two inputs (token chain and address) and two outputs (int value
328 /// and token chain).
333 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
334 /// integer source in memory and FP reg result. This corresponds to the
335 /// X86::FILD*m instructions. It has three inputs (token chain, address,
336 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
337 /// also produces a flag).
341 /// FLD - This instruction implements an extending load to FP stack slots.
342 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
343 /// operand, ptr to load from, and a ValueType node indicating the type
347 /// FST - This instruction implements a truncating store to FP stack
348 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
349 /// chain operand, value to store, address, and a ValueType to store it
353 /// VAARG_64 - This instruction grabs the address of the next argument
354 /// from a va_list. (reads and modifies the va_list in memory)
357 // WARNING: Do not add anything in the end unless you want the node to
358 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
359 // thought as target memory ops!
363 /// Define some predicates that are used for node matching.
365 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
366 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
367 bool isPSHUFDMask(ShuffleVectorSDNode *N);
369 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
370 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
371 bool isPSHUFHWMask(ShuffleVectorSDNode *N);
373 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
374 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
375 bool isPSHUFLWMask(ShuffleVectorSDNode *N);
377 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
378 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
379 bool isSHUFPMask(ShuffleVectorSDNode *N);
381 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
382 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
383 bool isMOVHLPSMask(ShuffleVectorSDNode *N);
385 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
386 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
388 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N);
390 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
391 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}.
392 bool isMOVLPMask(ShuffleVectorSDNode *N);
394 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
395 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}.
396 /// as well as MOVLHPS.
397 bool isMOVLHPSMask(ShuffleVectorSDNode *N);
399 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
400 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
401 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
403 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
404 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
405 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
407 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
408 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
410 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N);
412 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
413 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
415 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N);
417 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
418 /// specifies a shuffle of elements that is suitable for input to MOVSS,
419 /// MOVSD, and MOVD, i.e. setting the lowest element.
420 bool isMOVLMask(ShuffleVectorSDNode *N);
422 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
423 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
424 bool isMOVSHDUPMask(ShuffleVectorSDNode *N, const X86Subtarget *Subtarget);
426 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
427 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
428 bool isMOVSLDUPMask(ShuffleVectorSDNode *N, const X86Subtarget *Subtarget);
430 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
431 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
432 bool isMOVDDUPMask(ShuffleVectorSDNode *N);
434 /// isVEXTRACTF128Index - Return true if the specified
435 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
436 /// suitable for input to VEXTRACTF128.
437 bool isVEXTRACTF128Index(SDNode *N);
439 /// isVINSERTF128Index - Return true if the specified
440 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
441 /// suitable for input to VINSERTF128.
442 bool isVINSERTF128Index(SDNode *N);
444 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
445 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
447 unsigned getShuffleSHUFImmediate(SDNode *N);
449 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
450 /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction.
451 unsigned getShufflePSHUFHWImmediate(SDNode *N);
453 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
454 /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction.
455 unsigned getShufflePSHUFLWImmediate(SDNode *N);
457 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
458 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
459 unsigned getShufflePALIGNRImmediate(SDNode *N);
461 /// getExtractVEXTRACTF128Immediate - Return the appropriate
462 /// immediate to extract the specified EXTRACT_SUBVECTOR index
463 /// with VEXTRACTF128 instructions.
464 unsigned getExtractVEXTRACTF128Immediate(SDNode *N);
466 /// getInsertVINSERTF128Immediate - Return the appropriate
467 /// immediate to insert at the specified INSERT_SUBVECTOR index
468 /// with VINSERTF128 instructions.
469 unsigned getInsertVINSERTF128Immediate(SDNode *N);
471 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
473 bool isZeroNode(SDValue Elt);
475 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
476 /// fit into displacement field of the instruction.
477 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
478 bool hasSymbolicDisplacement = true);
481 /// isCalleePop - Determines whether the callee is required to pop its
482 /// own arguments. Callee pop is necessary to support tail calls.
483 bool isCalleePop(CallingConv::ID CallingConv,
484 bool is64Bit, bool IsVarArg, bool TailCallOpt);
487 //===--------------------------------------------------------------------===//
488 // X86TargetLowering - X86 Implementation of the TargetLowering interface
489 class X86TargetLowering : public TargetLowering {
491 explicit X86TargetLowering(X86TargetMachine &TM);
493 virtual unsigned getJumpTableEncoding() const;
495 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
497 virtual const MCExpr *
498 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
499 const MachineBasicBlock *MBB, unsigned uid,
500 MCContext &Ctx) const;
502 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
504 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
505 SelectionDAG &DAG) const;
506 virtual const MCExpr *
507 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
508 unsigned JTI, MCContext &Ctx) const;
510 /// getStackPtrReg - Return the stack pointer register we are using: either
512 unsigned getStackPtrReg() const { return X86StackPtr; }
514 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
515 /// function arguments in the caller parameter area. For X86, aggregates
516 /// that contains are placed at 16-byte boundaries while the rest are at
517 /// 4-byte boundaries.
518 virtual unsigned getByValTypeAlignment(Type *Ty) const;
520 /// getOptimalMemOpType - Returns the target specific optimal type for load
521 /// and store operations as a result of memset, memcpy, and memmove
522 /// lowering. If DstAlign is zero that means it's safe to destination
523 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
524 /// means there isn't a need to check it against alignment requirement,
525 /// probably because the source does not need to be loaded. If
526 /// 'NonScalarIntSafe' is true, that means it's safe to return a
527 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
528 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
529 /// constant so it does not need to be loaded.
530 /// It returns EVT::Other if the type should be determined using generic
531 /// target-independent logic.
533 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
534 bool NonScalarIntSafe, bool MemcpyStrSrc,
535 MachineFunction &MF) const;
537 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
538 /// unaligned memory accesses. of the specified type.
539 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
543 /// LowerOperation - Provide custom lowering hooks for some operations.
545 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
547 /// ReplaceNodeResults - Replace the results of node with an illegal result
548 /// type with new values built out of custom code.
550 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
551 SelectionDAG &DAG) const;
554 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
556 /// isTypeDesirableForOp - Return true if the target has native support for
557 /// the specified value type and it is 'desirable' to use the type for the
558 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
559 /// instruction encodings are longer and some i16 instructions are slow.
560 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
562 /// isTypeDesirable - Return true if the target has native support for the
563 /// specified value type and it is 'desirable' to use the type. e.g. On x86
564 /// i16 is legal, but undesirable since i16 instruction encodings are longer
565 /// and some i16 instructions are slow.
566 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
568 virtual MachineBasicBlock *
569 EmitInstrWithCustomInserter(MachineInstr *MI,
570 MachineBasicBlock *MBB) const;
573 /// getTargetNodeName - This method returns the name of a target specific
575 virtual const char *getTargetNodeName(unsigned Opcode) const;
577 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
578 virtual EVT getSetCCResultType(EVT VT) const;
580 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
581 /// in Mask are known to be either zero or one and return them in the
582 /// KnownZero/KnownOne bitsets.
583 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
587 const SelectionDAG &DAG,
588 unsigned Depth = 0) const;
590 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
591 // operation that are sign bits.
592 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
593 unsigned Depth) const;
596 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
598 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
600 virtual bool ExpandInlineAsm(CallInst *CI) const;
602 ConstraintType getConstraintType(const std::string &Constraint) const;
604 /// Examine constraint string and operand type and determine a weight value.
605 /// The operand object must already have been set up with the operand type.
606 virtual ConstraintWeight getSingleConstraintMatchWeight(
607 AsmOperandInfo &info, const char *constraint) const;
609 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
611 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
612 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
613 /// true it means one of the asm constraint of the inline asm instruction
614 /// being processed is 'm'.
615 virtual void LowerAsmOperandForConstraint(SDValue Op,
616 std::string &Constraint,
617 std::vector<SDValue> &Ops,
618 SelectionDAG &DAG) const;
620 /// getRegForInlineAsmConstraint - Given a physical register constraint
621 /// (e.g. {edx}), return the register number and the register class for the
622 /// register. This should only be used for C_Register constraints. On
623 /// error, this returns a register number of 0.
624 std::pair<unsigned, const TargetRegisterClass*>
625 getRegForInlineAsmConstraint(const std::string &Constraint,
628 /// isLegalAddressingMode - Return true if the addressing mode represented
629 /// by AM is legal for this target, for a load/store of the specified type.
630 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
632 /// isTruncateFree - Return true if it's free to truncate a value of
633 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
634 /// register EAX to i16 by referencing its sub-register AX.
635 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
636 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
638 /// isZExtFree - Return true if any actual instruction that defines a
639 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
640 /// register. This does not necessarily include registers defined in
641 /// unknown ways, such as incoming arguments, or copies from unknown
642 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
643 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
644 /// all instructions that define 32-bit values implicit zero-extend the
645 /// result out to 64 bits.
646 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
647 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
649 /// isNarrowingProfitable - Return true if it's profitable to narrow
650 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
651 /// from i32 to i8 but not from i32 to i16.
652 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
654 /// isFPImmLegal - Returns true if the target can instruction select the
655 /// specified FP immediate natively. If false, the legalizer will
656 /// materialize the FP immediate as a load from a constant pool.
657 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
659 /// isShuffleMaskLegal - Targets can use this to indicate that they only
660 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
661 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
662 /// values are assumed to be legal.
663 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
666 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
667 /// used by Targets can use this to indicate if there is a suitable
668 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
670 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
673 /// ShouldShrinkFPConstant - If true, then instruction selection should
674 /// seek to shrink the FP constant of the specified type to a smaller type
675 /// in order to save space and / or reduce runtime.
676 virtual bool ShouldShrinkFPConstant(EVT VT) const {
677 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
678 // expensive than a straight movsd. On the other hand, it's important to
679 // shrink long double fp constant since fldt is very slow.
680 return !X86ScalarSSEf64 || VT == MVT::f80;
683 const X86Subtarget* getSubtarget() const {
687 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
688 /// computed in an SSE register, not on the X87 floating point stack.
689 bool isScalarFPTypeInSSEReg(EVT VT) const {
690 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
691 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
694 /// createFastISel - This method returns a target specific FastISel object,
695 /// or null if the target does not support "fast" ISel.
696 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
698 /// getStackCookieLocation - Return true if the target stores stack
699 /// protector cookies at a fixed offset in some non-standard address
700 /// space, and populates the address space and offset as
702 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
704 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
705 SelectionDAG &DAG) const;
708 std::pair<const TargetRegisterClass*, uint8_t>
709 findRepresentativeClass(EVT VT) const;
712 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
713 /// make the right decision when generating code for different targets.
714 const X86Subtarget *Subtarget;
715 const X86RegisterInfo *RegInfo;
716 const TargetData *TD;
718 /// X86StackPtr - X86 physical register used as stack ptr.
719 unsigned X86StackPtr;
721 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
722 /// floating point ops.
723 /// When SSE is available, use it for f32 operations.
724 /// When SSE2 is available, use it for f64 operations.
725 bool X86ScalarSSEf32;
726 bool X86ScalarSSEf64;
728 /// LegalFPImmediates - A list of legal fp immediates.
729 std::vector<APFloat> LegalFPImmediates;
731 /// addLegalFPImmediate - Indicate that this x86 target can instruction
732 /// select the specified FP immediate natively.
733 void addLegalFPImmediate(const APFloat& Imm) {
734 LegalFPImmediates.push_back(Imm);
737 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
738 CallingConv::ID CallConv, bool isVarArg,
739 const SmallVectorImpl<ISD::InputArg> &Ins,
740 DebugLoc dl, SelectionDAG &DAG,
741 SmallVectorImpl<SDValue> &InVals) const;
742 SDValue LowerMemArgument(SDValue Chain,
743 CallingConv::ID CallConv,
744 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
745 DebugLoc dl, SelectionDAG &DAG,
746 const CCValAssign &VA, MachineFrameInfo *MFI,
748 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
749 DebugLoc dl, SelectionDAG &DAG,
750 const CCValAssign &VA,
751 ISD::ArgFlagsTy Flags) const;
753 // Call lowering helpers.
755 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
756 /// for tail call optimization. Targets which want to do tail call
757 /// optimization should implement this function.
758 bool IsEligibleForTailCallOptimization(SDValue Callee,
759 CallingConv::ID CalleeCC,
761 bool isCalleeStructRet,
762 bool isCallerStructRet,
763 const SmallVectorImpl<ISD::OutputArg> &Outs,
764 const SmallVectorImpl<SDValue> &OutVals,
765 const SmallVectorImpl<ISD::InputArg> &Ins,
766 SelectionDAG& DAG) const;
767 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
768 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
769 SDValue Chain, bool IsTailCall, bool Is64Bit,
770 int FPDiff, DebugLoc dl) const;
772 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
773 SelectionDAG &DAG) const;
775 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
776 bool isSigned) const;
778 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
779 SelectionDAG &DAG) const;
780 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
781 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
782 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
783 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
784 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
785 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
786 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
787 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
788 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
789 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
790 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
791 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
792 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
793 int64_t Offset, SelectionDAG &DAG) const;
794 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
795 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
796 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
797 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
798 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const;
799 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
800 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
801 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
802 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
803 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
804 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
805 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
806 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
807 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
808 SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const;
809 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
810 DebugLoc dl, SelectionDAG &DAG) const;
811 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
812 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
813 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
814 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
815 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
816 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
817 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
818 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
819 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
820 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
821 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
822 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
823 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
824 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
825 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
826 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
827 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
828 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
829 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
830 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
831 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
832 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
833 SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) const;
834 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
835 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
836 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
838 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
839 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
840 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
841 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const;
842 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
843 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
845 // Utility functions to help LowerVECTOR_SHUFFLE
846 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const;
849 LowerFormalArguments(SDValue Chain,
850 CallingConv::ID CallConv, bool isVarArg,
851 const SmallVectorImpl<ISD::InputArg> &Ins,
852 DebugLoc dl, SelectionDAG &DAG,
853 SmallVectorImpl<SDValue> &InVals) const;
855 LowerCall(SDValue Chain, SDValue Callee,
856 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
857 const SmallVectorImpl<ISD::OutputArg> &Outs,
858 const SmallVectorImpl<SDValue> &OutVals,
859 const SmallVectorImpl<ISD::InputArg> &Ins,
860 DebugLoc dl, SelectionDAG &DAG,
861 SmallVectorImpl<SDValue> &InVals) const;
864 LowerReturn(SDValue Chain,
865 CallingConv::ID CallConv, bool isVarArg,
866 const SmallVectorImpl<ISD::OutputArg> &Outs,
867 const SmallVectorImpl<SDValue> &OutVals,
868 DebugLoc dl, SelectionDAG &DAG) const;
870 virtual bool isUsedByReturnOnly(SDNode *N) const;
872 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
875 getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
876 ISD::NodeType ExtendKind) const;
879 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
881 const SmallVectorImpl<ISD::OutputArg> &Outs,
882 LLVMContext &Context) const;
884 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
885 SelectionDAG &DAG, unsigned NewOp) const;
887 /// Utility function to emit string processing sse4.2 instructions
888 /// that return in xmm0.
889 /// This takes the instruction to expand, the associated machine basic
890 /// block, the number of args, and whether or not the second arg is
891 /// in memory or not.
892 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
893 unsigned argNum, bool inMem) const;
895 /// Utility functions to emit monitor and mwait instructions. These
896 /// need to make sure that the arguments to the intrinsic are in the
897 /// correct registers.
898 MachineBasicBlock *EmitMonitor(MachineInstr *MI,
899 MachineBasicBlock *BB) const;
900 MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const;
902 /// Utility function to emit atomic bitwise operations (and, or, xor).
903 /// It takes the bitwise instruction to expand, the associated machine basic
904 /// block, and the associated X86 opcodes for reg/reg and reg/imm.
905 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
906 MachineInstr *BInstr,
907 MachineBasicBlock *BB,
914 TargetRegisterClass *RC,
915 bool invSrc = false) const;
917 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
918 MachineInstr *BInstr,
919 MachineBasicBlock *BB,
924 bool invSrc = false) const;
926 /// Utility function to emit atomic min and max. It takes the min/max
927 /// instruction to expand, the associated basic block, and the associated
928 /// cmov opcode for moving the min or max value.
929 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
930 MachineBasicBlock *BB,
931 unsigned cmovOpc) const;
933 // Utility function to emit the low-level va_arg code for X86-64.
934 MachineBasicBlock *EmitVAARG64WithCustomInserter(
936 MachineBasicBlock *MBB) const;
938 /// Utility function to emit the xmm reg save portion of va_start.
939 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
940 MachineInstr *BInstr,
941 MachineBasicBlock *BB) const;
943 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
944 MachineBasicBlock *BB) const;
946 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
947 MachineBasicBlock *BB) const;
949 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
950 MachineBasicBlock *BB,
953 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
954 MachineBasicBlock *BB) const;
956 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
957 MachineBasicBlock *BB) const;
959 /// Emit nodes that will be selected as "test Op0,Op0", or something
960 /// equivalent, for use with the given x86 condition code.
961 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
963 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
964 /// equivalent, for use with the given x86 condition code.
965 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
966 SelectionDAG &DAG) const;
970 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
974 #endif // X86ISELLOWERING_H