1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
29 // X86 Specific DAG Nodes
31 // Start the numbering where the builtin ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 /// BSF - Bit scan forward.
35 /// BSR - Bit scan reverse.
39 /// SHLD, SHRD - Double shift instructions. These correspond to
40 /// X86::SHLDxx and X86::SHRDxx instructions.
44 /// FAND - Bitwise logical AND of floating point values. This corresponds
45 /// to X86::ANDPS or X86::ANDPD.
48 /// FOR - Bitwise logical OR of floating point values. This corresponds
49 /// to X86::ORPS or X86::ORPD.
52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
53 /// to X86::XORPS or X86::XORPD.
56 /// FSRL - Bitwise logical right shift of floating point values. These
57 /// corresponds to X86::PSRLDQ.
60 /// CALL - These operations represent an abstract X86 call
61 /// instruction, which includes a bunch of information. In particular the
62 /// operands of these node are:
64 /// #0 - The incoming token chain
66 /// #2 - The number of arg bytes the caller pushes on the stack.
67 /// #3 - The number of arg bytes the callee pops off the stack.
68 /// #4 - The value to pass in AL/AX/EAX (optional)
69 /// #5 - The value to pass in DL/DX/EDX (optional)
71 /// The result values of these nodes are:
73 /// #0 - The outgoing token chain
74 /// #1 - The first register result value (optional)
75 /// #2 - The second register result value (optional)
79 /// RDTSC_DAG - This operation implements the lowering for
83 /// X86 compare and logical compare instructions.
86 /// X86 bit-test instructions.
89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
90 /// operand, usually produced by a CMP instruction.
93 // Same as SETCC except it's materialized with a sbb and the value is all
94 // one's or all zero's.
95 SETCC_CARRY, // R = carry_bit ? ~0 : 0
97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
98 /// Operands are two FP values to compare; result is a mask of
99 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
102 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
103 /// result in an integer GPR. Needs masking for scalar result.
106 /// X86 conditional moves. Operand 0 and operand 1 are the two values
107 /// to select from. Operand 2 is the condition code, and operand 3 is the
108 /// flag operand produced by a CMP or TEST instruction. It also writes a
112 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
113 /// is the block to branch if condition is true, operand 2 is the
114 /// condition code, and operand 3 is the flag operand produced by a CMP
115 /// or TEST instruction.
118 /// Return with a flag operand. Operand 0 is the chain operand, operand
119 /// 1 is the number of bytes of stack to pop.
122 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
125 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
128 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
129 /// at function entry, used for PIC code.
132 /// Wrapper - A wrapper node for TargetConstantPool,
133 /// TargetExternalSymbol, and TargetGlobalAddress.
136 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
137 /// relative displacements.
140 /// MOVQ2DQ - Copies a 64-bit value from an MMX vector to the low word
141 /// of an XMM vector, with the high word zero filled.
144 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
145 /// to an MMX vector. If you think this is too close to the previous
146 /// mnemonic, so do I; blame Intel.
149 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
150 /// i32, corresponds to X86::PEXTRB.
153 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
154 /// i32, corresponds to X86::PEXTRW.
157 /// INSERTPS - Insert any element of a 4 x float vector into any element
158 /// of a destination 4 x floatvector.
161 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
162 /// corresponds to X86::PINSRB.
165 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
166 /// corresponds to X86::PINSRW.
169 /// PSHUFB - Shuffle 16 8-bit values within a vector.
172 /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
175 /// PSIGNB/W/D - Copy integer sign.
176 PSIGNB, PSIGNW, PSIGND,
178 /// BLEND family of opcodes
181 /// FHADD - Floating point horizontal add.
184 /// FHSUB - Floating point horizontal sub.
187 /// FMAX, FMIN - Floating point max and min.
191 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
192 /// approximation. Note that these typically require refinement
193 /// in order to obtain suitable precision.
196 // TLSADDR - Thread Local Storage.
199 // TLSCALL - Thread Local Storage. When calling to an OS provided
200 // thunk at the address from an earlier relocation.
203 // EH_RETURN - Exception Handling helpers.
206 /// TC_RETURN - Tail call return.
208 /// operand #1 callee (register or absolute)
209 /// operand #2 stack adjustment
210 /// operand #3 optional in flag
213 // VZEXT_MOVL - Vector move low and zero extend.
216 // VSHL, VSRL - Vector logical left / right shift.
219 // CMPPD, CMPPS - Vector double/float comparison.
220 // CMPPD, CMPPS - Vector double/float comparison.
223 // PCMP* - Vector integer comparisons.
224 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
225 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
227 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
228 ADD, SUB, ADC, SBB, SMUL,
229 INC, DEC, OR, XOR, AND,
231 ANDN, // ANDN - Bitwise AND NOT with FLAGS results.
233 BLSI, // BLSI - Extract lowest set isolated bit
234 BLSMSK, // BLSMSK - Get mask up to lowest set bit
235 BLSR, // BLSR - Reset lowest set bit
237 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
239 // MUL_IMM - X86 specific multiply by immediate.
242 // PTEST - Vector bitwise comparisons
245 // TESTP - Vector packed fp sign bitwise comparisons
248 // Several flavors of instructions with vector shuffle behaviors.
293 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
294 // according to %al. An operator is needed so that this can be expanded
295 // with control flow.
296 VASTART_SAVE_XMM_REGS,
298 // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
301 // SEG_ALLOCA - For allocating variable amounts of stack space when using
302 // segmented stacks. Check if the current stacklet has enough space, and
303 // falls back to heap allocation if not.
312 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
313 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
314 // Atomic 64-bit binary operations.
315 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
323 // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
328 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
331 // FNSTCW16m - Store FP control world into i16 memory.
334 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
335 /// integer destination in memory and a FP reg source. This corresponds
336 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
337 /// has two inputs (token chain and address) and two outputs (int value
338 /// and token chain).
343 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
344 /// integer source in memory and FP reg result. This corresponds to the
345 /// X86::FILD*m instructions. It has three inputs (token chain, address,
346 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
347 /// also produces a flag).
351 /// FLD - This instruction implements an extending load to FP stack slots.
352 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
353 /// operand, ptr to load from, and a ValueType node indicating the type
357 /// FST - This instruction implements a truncating store to FP stack
358 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
359 /// chain operand, value to store, address, and a ValueType to store it
363 /// VAARG_64 - This instruction grabs the address of the next argument
364 /// from a va_list. (reads and modifies the va_list in memory)
367 // WARNING: Do not add anything in the end unless you want the node to
368 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
369 // thought as target memory ops!
373 /// Define some predicates that are used for node matching.
375 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
376 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
377 bool isPSHUFDMask(ShuffleVectorSDNode *N);
379 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
380 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
381 bool isPSHUFHWMask(ShuffleVectorSDNode *N);
383 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
384 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
385 bool isPSHUFLWMask(ShuffleVectorSDNode *N);
387 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
388 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
389 bool isSHUFPMask(ShuffleVectorSDNode *N);
391 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
392 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
393 bool isMOVHLPSMask(ShuffleVectorSDNode *N);
395 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
396 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
398 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N);
400 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
401 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}.
402 bool isMOVLPMask(ShuffleVectorSDNode *N);
404 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
405 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}.
406 /// as well as MOVLHPS.
407 bool isMOVLHPSMask(ShuffleVectorSDNode *N);
409 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
410 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
411 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
413 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
414 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
415 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
417 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
418 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
420 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N);
422 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
423 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
425 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N);
427 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
428 /// specifies a shuffle of elements that is suitable for input to MOVSS,
429 /// MOVSD, and MOVD, i.e. setting the lowest element.
430 bool isMOVLMask(ShuffleVectorSDNode *N);
432 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
433 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
434 bool isMOVSHDUPMask(ShuffleVectorSDNode *N, const X86Subtarget *Subtarget);
436 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
437 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
438 bool isMOVSLDUPMask(ShuffleVectorSDNode *N, const X86Subtarget *Subtarget);
440 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
441 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
442 bool isMOVDDUPMask(ShuffleVectorSDNode *N);
444 /// isVEXTRACTF128Index - Return true if the specified
445 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
446 /// suitable for input to VEXTRACTF128.
447 bool isVEXTRACTF128Index(SDNode *N);
449 /// isVINSERTF128Index - Return true if the specified
450 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
451 /// suitable for input to VINSERTF128.
452 bool isVINSERTF128Index(SDNode *N);
454 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
455 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
457 unsigned getShuffleSHUFImmediate(SDNode *N);
459 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
460 /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction.
461 unsigned getShufflePSHUFHWImmediate(SDNode *N);
463 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
464 /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction.
465 unsigned getShufflePSHUFLWImmediate(SDNode *N);
467 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
468 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
469 unsigned getShufflePALIGNRImmediate(SDNode *N);
471 /// getExtractVEXTRACTF128Immediate - Return the appropriate
472 /// immediate to extract the specified EXTRACT_SUBVECTOR index
473 /// with VEXTRACTF128 instructions.
474 unsigned getExtractVEXTRACTF128Immediate(SDNode *N);
476 /// getInsertVINSERTF128Immediate - Return the appropriate
477 /// immediate to insert at the specified INSERT_SUBVECTOR index
478 /// with VINSERTF128 instructions.
479 unsigned getInsertVINSERTF128Immediate(SDNode *N);
481 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
483 bool isZeroNode(SDValue Elt);
485 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
486 /// fit into displacement field of the instruction.
487 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
488 bool hasSymbolicDisplacement = true);
491 /// isCalleePop - Determines whether the callee is required to pop its
492 /// own arguments. Callee pop is necessary to support tail calls.
493 bool isCalleePop(CallingConv::ID CallingConv,
494 bool is64Bit, bool IsVarArg, bool TailCallOpt);
497 //===--------------------------------------------------------------------===//
498 // X86TargetLowering - X86 Implementation of the TargetLowering interface
499 class X86TargetLowering : public TargetLowering {
501 explicit X86TargetLowering(X86TargetMachine &TM);
503 virtual unsigned getJumpTableEncoding() const;
505 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
507 virtual const MCExpr *
508 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
509 const MachineBasicBlock *MBB, unsigned uid,
510 MCContext &Ctx) const;
512 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
514 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
515 SelectionDAG &DAG) const;
516 virtual const MCExpr *
517 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
518 unsigned JTI, MCContext &Ctx) const;
520 /// getStackPtrReg - Return the stack pointer register we are using: either
522 unsigned getStackPtrReg() const { return X86StackPtr; }
524 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
525 /// function arguments in the caller parameter area. For X86, aggregates
526 /// that contains are placed at 16-byte boundaries while the rest are at
527 /// 4-byte boundaries.
528 virtual unsigned getByValTypeAlignment(Type *Ty) const;
530 /// getOptimalMemOpType - Returns the target specific optimal type for load
531 /// and store operations as a result of memset, memcpy, and memmove
532 /// lowering. If DstAlign is zero that means it's safe to destination
533 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
534 /// means there isn't a need to check it against alignment requirement,
535 /// probably because the source does not need to be loaded. If
536 /// 'IsZeroVal' is true, that means it's safe to return a
537 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
538 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
539 /// constant so it does not need to be loaded.
540 /// It returns EVT::Other if the type should be determined using generic
541 /// target-independent logic.
543 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
544 bool IsZeroVal, bool MemcpyStrSrc,
545 MachineFunction &MF) const;
547 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
548 /// unaligned memory accesses. of the specified type.
549 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
553 /// LowerOperation - Provide custom lowering hooks for some operations.
555 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
557 /// ReplaceNodeResults - Replace the results of node with an illegal result
558 /// type with new values built out of custom code.
560 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
561 SelectionDAG &DAG) const;
564 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
566 /// isTypeDesirableForOp - Return true if the target has native support for
567 /// the specified value type and it is 'desirable' to use the type for the
568 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
569 /// instruction encodings are longer and some i16 instructions are slow.
570 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
572 /// isTypeDesirable - Return true if the target has native support for the
573 /// specified value type and it is 'desirable' to use the type. e.g. On x86
574 /// i16 is legal, but undesirable since i16 instruction encodings are longer
575 /// and some i16 instructions are slow.
576 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
578 virtual MachineBasicBlock *
579 EmitInstrWithCustomInserter(MachineInstr *MI,
580 MachineBasicBlock *MBB) const;
583 /// getTargetNodeName - This method returns the name of a target specific
585 virtual const char *getTargetNodeName(unsigned Opcode) const;
587 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
588 virtual EVT getSetCCResultType(EVT VT) const;
590 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
591 /// in Mask are known to be either zero or one and return them in the
592 /// KnownZero/KnownOne bitsets.
593 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
597 const SelectionDAG &DAG,
598 unsigned Depth = 0) const;
600 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
601 // operation that are sign bits.
602 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
603 unsigned Depth) const;
606 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
608 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
610 virtual bool ExpandInlineAsm(CallInst *CI) const;
612 ConstraintType getConstraintType(const std::string &Constraint) const;
614 /// Examine constraint string and operand type and determine a weight value.
615 /// The operand object must already have been set up with the operand type.
616 virtual ConstraintWeight getSingleConstraintMatchWeight(
617 AsmOperandInfo &info, const char *constraint) const;
619 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
621 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
622 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
623 /// true it means one of the asm constraint of the inline asm instruction
624 /// being processed is 'm'.
625 virtual void LowerAsmOperandForConstraint(SDValue Op,
626 std::string &Constraint,
627 std::vector<SDValue> &Ops,
628 SelectionDAG &DAG) const;
630 /// getRegForInlineAsmConstraint - Given a physical register constraint
631 /// (e.g. {edx}), return the register number and the register class for the
632 /// register. This should only be used for C_Register constraints. On
633 /// error, this returns a register number of 0.
634 std::pair<unsigned, const TargetRegisterClass*>
635 getRegForInlineAsmConstraint(const std::string &Constraint,
638 /// isLegalAddressingMode - Return true if the addressing mode represented
639 /// by AM is legal for this target, for a load/store of the specified type.
640 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
642 /// isTruncateFree - Return true if it's free to truncate a value of
643 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
644 /// register EAX to i16 by referencing its sub-register AX.
645 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
646 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
648 /// isZExtFree - Return true if any actual instruction that defines a
649 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
650 /// register. This does not necessarily include registers defined in
651 /// unknown ways, such as incoming arguments, or copies from unknown
652 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
653 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
654 /// all instructions that define 32-bit values implicit zero-extend the
655 /// result out to 64 bits.
656 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
657 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
659 /// isNarrowingProfitable - Return true if it's profitable to narrow
660 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
661 /// from i32 to i8 but not from i32 to i16.
662 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
664 /// isFPImmLegal - Returns true if the target can instruction select the
665 /// specified FP immediate natively. If false, the legalizer will
666 /// materialize the FP immediate as a load from a constant pool.
667 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
669 /// isShuffleMaskLegal - Targets can use this to indicate that they only
670 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
671 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
672 /// values are assumed to be legal.
673 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
676 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
677 /// used by Targets can use this to indicate if there is a suitable
678 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
680 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
683 /// ShouldShrinkFPConstant - If true, then instruction selection should
684 /// seek to shrink the FP constant of the specified type to a smaller type
685 /// in order to save space and / or reduce runtime.
686 virtual bool ShouldShrinkFPConstant(EVT VT) const {
687 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
688 // expensive than a straight movsd. On the other hand, it's important to
689 // shrink long double fp constant since fldt is very slow.
690 return !X86ScalarSSEf64 || VT == MVT::f80;
693 const X86Subtarget* getSubtarget() const {
697 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
698 /// computed in an SSE register, not on the X87 floating point stack.
699 bool isScalarFPTypeInSSEReg(EVT VT) const {
700 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
701 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
704 /// createFastISel - This method returns a target specific FastISel object,
705 /// or null if the target does not support "fast" ISel.
706 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
708 /// getStackCookieLocation - Return true if the target stores stack
709 /// protector cookies at a fixed offset in some non-standard address
710 /// space, and populates the address space and offset as
712 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
714 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
715 SelectionDAG &DAG) const;
718 std::pair<const TargetRegisterClass*, uint8_t>
719 findRepresentativeClass(EVT VT) const;
722 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
723 /// make the right decision when generating code for different targets.
724 const X86Subtarget *Subtarget;
725 const X86RegisterInfo *RegInfo;
726 const TargetData *TD;
728 /// X86StackPtr - X86 physical register used as stack ptr.
729 unsigned X86StackPtr;
731 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
732 /// floating point ops.
733 /// When SSE is available, use it for f32 operations.
734 /// When SSE2 is available, use it for f64 operations.
735 bool X86ScalarSSEf32;
736 bool X86ScalarSSEf64;
738 /// LegalFPImmediates - A list of legal fp immediates.
739 std::vector<APFloat> LegalFPImmediates;
741 /// addLegalFPImmediate - Indicate that this x86 target can instruction
742 /// select the specified FP immediate natively.
743 void addLegalFPImmediate(const APFloat& Imm) {
744 LegalFPImmediates.push_back(Imm);
747 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
748 CallingConv::ID CallConv, bool isVarArg,
749 const SmallVectorImpl<ISD::InputArg> &Ins,
750 DebugLoc dl, SelectionDAG &DAG,
751 SmallVectorImpl<SDValue> &InVals) const;
752 SDValue LowerMemArgument(SDValue Chain,
753 CallingConv::ID CallConv,
754 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
755 DebugLoc dl, SelectionDAG &DAG,
756 const CCValAssign &VA, MachineFrameInfo *MFI,
758 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
759 DebugLoc dl, SelectionDAG &DAG,
760 const CCValAssign &VA,
761 ISD::ArgFlagsTy Flags) const;
763 // Call lowering helpers.
765 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
766 /// for tail call optimization. Targets which want to do tail call
767 /// optimization should implement this function.
768 bool IsEligibleForTailCallOptimization(SDValue Callee,
769 CallingConv::ID CalleeCC,
771 bool isCalleeStructRet,
772 bool isCallerStructRet,
773 const SmallVectorImpl<ISD::OutputArg> &Outs,
774 const SmallVectorImpl<SDValue> &OutVals,
775 const SmallVectorImpl<ISD::InputArg> &Ins,
776 SelectionDAG& DAG) const;
777 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
778 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
779 SDValue Chain, bool IsTailCall, bool Is64Bit,
780 int FPDiff, DebugLoc dl) const;
782 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
783 SelectionDAG &DAG) const;
785 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
786 bool isSigned) const;
788 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
789 SelectionDAG &DAG) const;
790 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
791 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
792 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
793 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
794 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
795 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
796 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
797 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
798 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
799 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
800 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
801 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
802 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
803 int64_t Offset, SelectionDAG &DAG) const;
804 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
805 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
806 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
807 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
808 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const;
809 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
810 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
811 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
812 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
813 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
814 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
815 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
816 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
817 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
818 SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const;
819 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
820 DebugLoc dl, SelectionDAG &DAG) const;
821 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
822 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
823 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
824 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
825 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
826 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
827 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
828 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
829 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
830 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
831 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
832 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
833 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
834 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
835 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
836 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
837 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
838 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
839 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
840 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
841 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
842 SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) const;
843 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
844 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
845 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
847 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
848 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
849 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
850 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const;
851 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
852 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
854 // Utility functions to help LowerVECTOR_SHUFFLE
855 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const;
858 LowerFormalArguments(SDValue Chain,
859 CallingConv::ID CallConv, bool isVarArg,
860 const SmallVectorImpl<ISD::InputArg> &Ins,
861 DebugLoc dl, SelectionDAG &DAG,
862 SmallVectorImpl<SDValue> &InVals) const;
864 LowerCall(SDValue Chain, SDValue Callee,
865 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
866 const SmallVectorImpl<ISD::OutputArg> &Outs,
867 const SmallVectorImpl<SDValue> &OutVals,
868 const SmallVectorImpl<ISD::InputArg> &Ins,
869 DebugLoc dl, SelectionDAG &DAG,
870 SmallVectorImpl<SDValue> &InVals) const;
873 LowerReturn(SDValue Chain,
874 CallingConv::ID CallConv, bool isVarArg,
875 const SmallVectorImpl<ISD::OutputArg> &Outs,
876 const SmallVectorImpl<SDValue> &OutVals,
877 DebugLoc dl, SelectionDAG &DAG) const;
879 virtual bool isUsedByReturnOnly(SDNode *N) const;
881 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
884 getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
885 ISD::NodeType ExtendKind) const;
888 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
890 const SmallVectorImpl<ISD::OutputArg> &Outs,
891 LLVMContext &Context) const;
893 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
894 SelectionDAG &DAG, unsigned NewOp) const;
896 /// Utility function to emit string processing sse4.2 instructions
897 /// that return in xmm0.
898 /// This takes the instruction to expand, the associated machine basic
899 /// block, the number of args, and whether or not the second arg is
900 /// in memory or not.
901 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
902 unsigned argNum, bool inMem) const;
904 /// Utility functions to emit monitor and mwait instructions. These
905 /// need to make sure that the arguments to the intrinsic are in the
906 /// correct registers.
907 MachineBasicBlock *EmitMonitor(MachineInstr *MI,
908 MachineBasicBlock *BB) const;
909 MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const;
911 /// Utility function to emit atomic bitwise operations (and, or, xor).
912 /// It takes the bitwise instruction to expand, the associated machine basic
913 /// block, and the associated X86 opcodes for reg/reg and reg/imm.
914 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
915 MachineInstr *BInstr,
916 MachineBasicBlock *BB,
923 TargetRegisterClass *RC,
924 bool invSrc = false) const;
926 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
927 MachineInstr *BInstr,
928 MachineBasicBlock *BB,
933 bool invSrc = false) const;
935 /// Utility function to emit atomic min and max. It takes the min/max
936 /// instruction to expand, the associated basic block, and the associated
937 /// cmov opcode for moving the min or max value.
938 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
939 MachineBasicBlock *BB,
940 unsigned cmovOpc) const;
942 // Utility function to emit the low-level va_arg code for X86-64.
943 MachineBasicBlock *EmitVAARG64WithCustomInserter(
945 MachineBasicBlock *MBB) const;
947 /// Utility function to emit the xmm reg save portion of va_start.
948 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
949 MachineInstr *BInstr,
950 MachineBasicBlock *BB) const;
952 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
953 MachineBasicBlock *BB) const;
955 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
956 MachineBasicBlock *BB) const;
958 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
959 MachineBasicBlock *BB,
962 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
963 MachineBasicBlock *BB) const;
965 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
966 MachineBasicBlock *BB) const;
968 /// Emit nodes that will be selected as "test Op0,Op0", or something
969 /// equivalent, for use with the given x86 condition code.
970 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
972 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
973 /// equivalent, for use with the given x86 condition code.
974 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
975 SelectionDAG &DAG) const;
979 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
983 #endif // X86ISELLOWERING_H