1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
29 // X86 Specific DAG Nodes
31 // Start the numbering where the builtin ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 /// BSF - Bit scan forward.
35 /// BSR - Bit scan reverse.
39 /// SHLD, SHRD - Double shift instructions. These correspond to
40 /// X86::SHLDxx and X86::SHRDxx instructions.
44 /// FAND - Bitwise logical AND of floating point values. This corresponds
45 /// to X86::ANDPS or X86::ANDPD.
48 /// FOR - Bitwise logical OR of floating point values. This corresponds
49 /// to X86::ORPS or X86::ORPD.
52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
53 /// to X86::XORPS or X86::XORPD.
56 /// FSRL - Bitwise logical right shift of floating point values. These
57 /// corresponds to X86::PSRLDQ.
60 /// CALL - These operations represent an abstract X86 call
61 /// instruction, which includes a bunch of information. In particular the
62 /// operands of these node are:
64 /// #0 - The incoming token chain
66 /// #2 - The number of arg bytes the caller pushes on the stack.
67 /// #3 - The number of arg bytes the callee pops off the stack.
68 /// #4 - The value to pass in AL/AX/EAX (optional)
69 /// #5 - The value to pass in DL/DX/EDX (optional)
71 /// The result values of these nodes are:
73 /// #0 - The outgoing token chain
74 /// #1 - The first register result value (optional)
75 /// #2 - The second register result value (optional)
79 /// RDTSC_DAG - This operation implements the lowering for
83 /// X86 compare and logical compare instructions.
86 /// X86 bit-test instructions.
89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
90 /// operand, usually produced by a CMP instruction.
93 // Same as SETCC except it's materialized with a sbb and the value is all
94 // one's or all zero's.
95 SETCC_CARRY, // R = carry_bit ? ~0 : 0
97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
98 /// Operands are two FP values to compare; result is a mask of
99 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
102 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
103 /// result in an integer GPR. Needs masking for scalar result.
106 /// X86 conditional moves. Operand 0 and operand 1 are the two values
107 /// to select from. Operand 2 is the condition code, and operand 3 is the
108 /// flag operand produced by a CMP or TEST instruction. It also writes a
112 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
113 /// is the block to branch if condition is true, operand 2 is the
114 /// condition code, and operand 3 is the flag operand produced by a CMP
115 /// or TEST instruction.
118 /// Return with a flag operand. Operand 0 is the chain operand, operand
119 /// 1 is the number of bytes of stack to pop.
122 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
125 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
128 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
129 /// at function entry, used for PIC code.
132 /// Wrapper - A wrapper node for TargetConstantPool,
133 /// TargetExternalSymbol, and TargetGlobalAddress.
136 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
137 /// relative displacements.
140 /// MOVQ2DQ - Copies a 64-bit value from an MMX vector to the low word
141 /// of an XMM vector, with the high word zero filled.
144 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
145 /// to an MMX vector. If you think this is too close to the previous
146 /// mnemonic, so do I; blame Intel.
149 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
150 /// i32, corresponds to X86::PEXTRB.
153 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
154 /// i32, corresponds to X86::PEXTRW.
157 /// INSERTPS - Insert any element of a 4 x float vector into any element
158 /// of a destination 4 x floatvector.
161 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
162 /// corresponds to X86::PINSRB.
165 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
166 /// corresponds to X86::PINSRW.
169 /// PSHUFB - Shuffle 16 8-bit values within a vector.
172 /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
175 /// PSIGN - Copy integer sign.
178 /// BLENDV - Blend where the selector is an XMM.
181 /// BLENDxx - Blend where the selector is an immediate.
186 /// HADD - Integer horizontal add.
189 /// HSUB - Integer horizontal sub.
192 /// FHADD - Floating point horizontal add.
195 /// FHSUB - Floating point horizontal sub.
198 /// FMAX, FMIN - Floating point max and min.
202 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
203 /// approximation. Note that these typically require refinement
204 /// in order to obtain suitable precision.
207 // TLSADDR - Thread Local Storage.
210 // TLSBASEADDR - Thread Local Storage. A call to get the start address
211 // of the TLS block for the current module.
214 // TLSCALL - Thread Local Storage. When calling to an OS provided
215 // thunk at the address from an earlier relocation.
218 // EH_RETURN - Exception Handling helpers.
221 /// TC_RETURN - Tail call return.
223 /// operand #1 callee (register or absolute)
224 /// operand #2 stack adjustment
225 /// operand #3 optional in flag
228 // VZEXT_MOVL - Vector move low and zero extend.
231 // VSEXT_MOVL - Vector move low and sign extend.
234 // VSHL, VSRL - 128-bit vector logical left / right shift
237 // VSHL, VSRL, VSRA - Vector shift elements
240 // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate
243 // CMPP - Vector packed double/float comparison.
246 // PCMP* - Vector integer comparisons.
249 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
250 ADD, SUB, ADC, SBB, SMUL,
251 INC, DEC, OR, XOR, AND,
253 ANDN, // ANDN - Bitwise AND NOT with FLAGS results.
255 BLSI, // BLSI - Extract lowest set isolated bit
256 BLSMSK, // BLSMSK - Get mask up to lowest set bit
257 BLSR, // BLSR - Reset lowest set bit
259 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
261 // MUL_IMM - X86 specific multiply by immediate.
264 // PTEST - Vector bitwise comparisons
267 // TESTP - Vector packed fp sign bitwise comparisons
270 // Several flavors of instructions with vector shuffle behaviors.
294 // PMULUDQ - Vector multiply packed unsigned doubleword integers
305 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
306 // according to %al. An operator is needed so that this can be expanded
307 // with control flow.
308 VASTART_SAVE_XMM_REGS,
310 // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
313 // SEG_ALLOCA - For allocating variable amounts of stack space when using
314 // segmented stacks. Check if the current stacklet has enough space, and
315 // falls back to heap allocation if not.
318 // WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui.
327 // FNSTSW16r - Store FP status word into i16 register.
330 // SAHF - Store contents of %ah into %eflags.
333 // RDRAND - Get a random integer and indicate whether it is valid in CF.
336 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
337 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
338 // Atomic 64-bit binary operations.
339 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
347 // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
352 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
355 // FNSTCW16m - Store FP control world into i16 memory.
358 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
359 /// integer destination in memory and a FP reg source. This corresponds
360 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
361 /// has two inputs (token chain and address) and two outputs (int value
362 /// and token chain).
367 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
368 /// integer source in memory and FP reg result. This corresponds to the
369 /// X86::FILD*m instructions. It has three inputs (token chain, address,
370 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
371 /// also produces a flag).
375 /// FLD - This instruction implements an extending load to FP stack slots.
376 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
377 /// operand, ptr to load from, and a ValueType node indicating the type
381 /// FST - This instruction implements a truncating store to FP stack
382 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
383 /// chain operand, value to store, address, and a ValueType to store it
387 /// VAARG_64 - This instruction grabs the address of the next argument
388 /// from a va_list. (reads and modifies the va_list in memory)
391 // WARNING: Do not add anything in the end unless you want the node to
392 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
393 // thought as target memory ops!
397 /// Define some predicates that are used for node matching.
399 /// isVEXTRACTF128Index - Return true if the specified
400 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
401 /// suitable for input to VEXTRACTF128.
402 bool isVEXTRACTF128Index(SDNode *N);
404 /// isVINSERTF128Index - Return true if the specified
405 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
406 /// suitable for input to VINSERTF128.
407 bool isVINSERTF128Index(SDNode *N);
409 /// getExtractVEXTRACTF128Immediate - Return the appropriate
410 /// immediate to extract the specified EXTRACT_SUBVECTOR index
411 /// with VEXTRACTF128 instructions.
412 unsigned getExtractVEXTRACTF128Immediate(SDNode *N);
414 /// getInsertVINSERTF128Immediate - Return the appropriate
415 /// immediate to insert at the specified INSERT_SUBVECTOR index
416 /// with VINSERTF128 instructions.
417 unsigned getInsertVINSERTF128Immediate(SDNode *N);
419 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
421 bool isZeroNode(SDValue Elt);
423 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
424 /// fit into displacement field of the instruction.
425 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
426 bool hasSymbolicDisplacement = true);
429 /// isCalleePop - Determines whether the callee is required to pop its
430 /// own arguments. Callee pop is necessary to support tail calls.
431 bool isCalleePop(CallingConv::ID CallingConv,
432 bool is64Bit, bool IsVarArg, bool TailCallOpt);
435 //===--------------------------------------------------------------------===//
436 // X86TargetLowering - X86 Implementation of the TargetLowering interface
437 class X86TargetLowering : public TargetLowering {
439 explicit X86TargetLowering(X86TargetMachine &TM);
441 virtual unsigned getJumpTableEncoding() const;
443 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
445 virtual const MCExpr *
446 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
447 const MachineBasicBlock *MBB, unsigned uid,
448 MCContext &Ctx) const;
450 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
452 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
453 SelectionDAG &DAG) const;
454 virtual const MCExpr *
455 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
456 unsigned JTI, MCContext &Ctx) const;
458 /// getStackPtrReg - Return the stack pointer register we are using: either
460 unsigned getStackPtrReg() const { return X86StackPtr; }
462 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
463 /// function arguments in the caller parameter area. For X86, aggregates
464 /// that contains are placed at 16-byte boundaries while the rest are at
465 /// 4-byte boundaries.
466 virtual unsigned getByValTypeAlignment(Type *Ty) const;
468 /// getOptimalMemOpType - Returns the target specific optimal type for load
469 /// and store operations as a result of memset, memcpy, and memmove
470 /// lowering. If DstAlign is zero that means it's safe to destination
471 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
472 /// means there isn't a need to check it against alignment requirement,
473 /// probably because the source does not need to be loaded. If
474 /// 'IsZeroVal' is true, that means it's safe to return a
475 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
476 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
477 /// constant so it does not need to be loaded.
478 /// It returns EVT::Other if the type should be determined using generic
479 /// target-independent logic.
481 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
482 bool IsZeroVal, bool MemcpyStrSrc,
483 MachineFunction &MF) const;
485 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
486 /// unaligned memory accesses. of the specified type.
487 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
491 /// LowerOperation - Provide custom lowering hooks for some operations.
493 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
495 /// ReplaceNodeResults - Replace the results of node with an illegal result
496 /// type with new values built out of custom code.
498 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
499 SelectionDAG &DAG) const;
502 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
504 /// isTypeDesirableForOp - Return true if the target has native support for
505 /// the specified value type and it is 'desirable' to use the type for the
506 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
507 /// instruction encodings are longer and some i16 instructions are slow.
508 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
510 /// isTypeDesirable - Return true if the target has native support for the
511 /// specified value type and it is 'desirable' to use the type. e.g. On x86
512 /// i16 is legal, but undesirable since i16 instruction encodings are longer
513 /// and some i16 instructions are slow.
514 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
516 virtual MachineBasicBlock *
517 EmitInstrWithCustomInserter(MachineInstr *MI,
518 MachineBasicBlock *MBB) const;
521 /// getTargetNodeName - This method returns the name of a target specific
523 virtual const char *getTargetNodeName(unsigned Opcode) const;
525 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
526 virtual EVT getSetCCResultType(EVT VT) const;
528 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
529 /// in Mask are known to be either zero or one and return them in the
530 /// KnownZero/KnownOne bitsets.
531 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
534 const SelectionDAG &DAG,
535 unsigned Depth = 0) const;
537 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
538 // operation that are sign bits.
539 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
540 unsigned Depth) const;
543 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
545 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
547 virtual bool ExpandInlineAsm(CallInst *CI) const;
549 ConstraintType getConstraintType(const std::string &Constraint) const;
551 /// Examine constraint string and operand type and determine a weight value.
552 /// The operand object must already have been set up with the operand type.
553 virtual ConstraintWeight getSingleConstraintMatchWeight(
554 AsmOperandInfo &info, const char *constraint) const;
556 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
558 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
559 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
560 /// true it means one of the asm constraint of the inline asm instruction
561 /// being processed is 'm'.
562 virtual void LowerAsmOperandForConstraint(SDValue Op,
563 std::string &Constraint,
564 std::vector<SDValue> &Ops,
565 SelectionDAG &DAG) const;
567 /// getRegForInlineAsmConstraint - Given a physical register constraint
568 /// (e.g. {edx}), return the register number and the register class for the
569 /// register. This should only be used for C_Register constraints. On
570 /// error, this returns a register number of 0.
571 std::pair<unsigned, const TargetRegisterClass*>
572 getRegForInlineAsmConstraint(const std::string &Constraint,
575 /// isLegalAddressingMode - Return true if the addressing mode represented
576 /// by AM is legal for this target, for a load/store of the specified type.
577 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
579 /// isLegalICmpImmediate - Return true if the specified immediate is legal
580 /// icmp immediate, that is the target has icmp instructions which can
581 /// compare a register against the immediate without having to materialize
582 /// the immediate into a register.
583 virtual bool isLegalICmpImmediate(int64_t Imm) const;
585 /// isLegalAddImmediate - Return true if the specified immediate is legal
586 /// add immediate, that is the target has add instructions which can
587 /// add a register and the immediate without having to materialize
588 /// the immediate into a register.
589 virtual bool isLegalAddImmediate(int64_t Imm) const;
591 /// isTruncateFree - Return true if it's free to truncate a value of
592 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
593 /// register EAX to i16 by referencing its sub-register AX.
594 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
595 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
597 /// isZExtFree - Return true if any actual instruction that defines a
598 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
599 /// register. This does not necessarily include registers defined in
600 /// unknown ways, such as incoming arguments, or copies from unknown
601 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
602 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
603 /// all instructions that define 32-bit values implicit zero-extend the
604 /// result out to 64 bits.
605 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
606 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
608 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
609 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
610 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
611 /// is expanded to mul + add.
612 virtual bool isFMAFasterThanMulAndAdd(EVT) const { return true; }
614 /// isNarrowingProfitable - Return true if it's profitable to narrow
615 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
616 /// from i32 to i8 but not from i32 to i16.
617 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
619 /// isFPImmLegal - Returns true if the target can instruction select the
620 /// specified FP immediate natively. If false, the legalizer will
621 /// materialize the FP immediate as a load from a constant pool.
622 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
624 /// isShuffleMaskLegal - Targets can use this to indicate that they only
625 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
626 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
627 /// values are assumed to be legal.
628 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
631 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
632 /// used by Targets can use this to indicate if there is a suitable
633 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
635 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
638 /// ShouldShrinkFPConstant - If true, then instruction selection should
639 /// seek to shrink the FP constant of the specified type to a smaller type
640 /// in order to save space and / or reduce runtime.
641 virtual bool ShouldShrinkFPConstant(EVT VT) const {
642 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
643 // expensive than a straight movsd. On the other hand, it's important to
644 // shrink long double fp constant since fldt is very slow.
645 return !X86ScalarSSEf64 || VT == MVT::f80;
648 const X86Subtarget* getSubtarget() const {
652 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
653 /// computed in an SSE register, not on the X87 floating point stack.
654 bool isScalarFPTypeInSSEReg(EVT VT) const {
655 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
656 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
659 /// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine
661 bool isTargetFTOL() const {
662 return Subtarget->isTargetWindows() && !Subtarget->is64Bit();
665 /// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be
666 /// used for fptoui to the given type.
667 bool isIntegerTypeFTOL(EVT VT) const {
668 return isTargetFTOL() && VT == MVT::i64;
671 /// createFastISel - This method returns a target specific FastISel object,
672 /// or null if the target does not support "fast" ISel.
673 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
675 /// getStackCookieLocation - Return true if the target stores stack
676 /// protector cookies at a fixed offset in some non-standard address
677 /// space, and populates the address space and offset as
679 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
681 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
682 SelectionDAG &DAG) const;
685 std::pair<const TargetRegisterClass*, uint8_t>
686 findRepresentativeClass(EVT VT) const;
689 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
690 /// make the right decision when generating code for different targets.
691 const X86Subtarget *Subtarget;
692 const X86RegisterInfo *RegInfo;
693 const TargetData *TD;
695 /// X86StackPtr - X86 physical register used as stack ptr.
696 unsigned X86StackPtr;
698 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
699 /// floating point ops.
700 /// When SSE is available, use it for f32 operations.
701 /// When SSE2 is available, use it for f64 operations.
702 bool X86ScalarSSEf32;
703 bool X86ScalarSSEf64;
705 /// LegalFPImmediates - A list of legal fp immediates.
706 std::vector<APFloat> LegalFPImmediates;
708 /// addLegalFPImmediate - Indicate that this x86 target can instruction
709 /// select the specified FP immediate natively.
710 void addLegalFPImmediate(const APFloat& Imm) {
711 LegalFPImmediates.push_back(Imm);
714 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
715 CallingConv::ID CallConv, bool isVarArg,
716 const SmallVectorImpl<ISD::InputArg> &Ins,
717 DebugLoc dl, SelectionDAG &DAG,
718 SmallVectorImpl<SDValue> &InVals) const;
719 SDValue LowerMemArgument(SDValue Chain,
720 CallingConv::ID CallConv,
721 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
722 DebugLoc dl, SelectionDAG &DAG,
723 const CCValAssign &VA, MachineFrameInfo *MFI,
725 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
726 DebugLoc dl, SelectionDAG &DAG,
727 const CCValAssign &VA,
728 ISD::ArgFlagsTy Flags) const;
730 // Call lowering helpers.
732 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
733 /// for tail call optimization. Targets which want to do tail call
734 /// optimization should implement this function.
735 bool IsEligibleForTailCallOptimization(SDValue Callee,
736 CallingConv::ID CalleeCC,
738 bool isCalleeStructRet,
739 bool isCallerStructRet,
740 const SmallVectorImpl<ISD::OutputArg> &Outs,
741 const SmallVectorImpl<SDValue> &OutVals,
742 const SmallVectorImpl<ISD::InputArg> &Ins,
743 SelectionDAG& DAG) const;
744 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
745 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
746 SDValue Chain, bool IsTailCall, bool Is64Bit,
747 int FPDiff, DebugLoc dl) const;
749 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
750 SelectionDAG &DAG) const;
752 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
754 bool isReplace) const;
756 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
757 SelectionDAG &DAG) const;
758 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
759 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
760 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
761 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
762 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
763 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
764 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
765 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
766 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
767 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
768 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
769 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
770 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
771 int64_t Offset, SelectionDAG &DAG) const;
772 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
773 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
774 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
775 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
776 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const;
777 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
778 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
779 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
780 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
781 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
782 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
783 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
784 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
785 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
786 SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const;
787 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
788 DebugLoc dl, SelectionDAG &DAG) const;
789 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
790 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
791 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
792 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
793 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
794 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
795 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
796 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
797 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
798 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
799 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
800 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
801 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
802 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
803 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
804 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
805 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
806 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
807 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
808 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
809 SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const;
810 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
811 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
812 SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) const;
813 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
814 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
815 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
817 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
818 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
819 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
820 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const;
821 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
822 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
823 SDValue PerformTruncateCombine(SDNode* N, SelectionDAG &DAG, DAGCombinerInfo &DCI) const;
825 // Utility functions to help LowerVECTOR_SHUFFLE
826 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const;
827 SDValue LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const;
828 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const;
831 LowerFormalArguments(SDValue Chain,
832 CallingConv::ID CallConv, bool isVarArg,
833 const SmallVectorImpl<ISD::InputArg> &Ins,
834 DebugLoc dl, SelectionDAG &DAG,
835 SmallVectorImpl<SDValue> &InVals) const;
837 LowerCall(CallLoweringInfo &CLI,
838 SmallVectorImpl<SDValue> &InVals) const;
841 LowerReturn(SDValue Chain,
842 CallingConv::ID CallConv, bool isVarArg,
843 const SmallVectorImpl<ISD::OutputArg> &Outs,
844 const SmallVectorImpl<SDValue> &OutVals,
845 DebugLoc dl, SelectionDAG &DAG) const;
847 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
849 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
852 getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
853 ISD::NodeType ExtendKind) const;
856 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
858 const SmallVectorImpl<ISD::OutputArg> &Outs,
859 LLVMContext &Context) const;
861 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
862 SelectionDAG &DAG, unsigned NewOp) const;
864 /// Utility function to emit string processing sse4.2 instructions
865 /// that return in xmm0.
866 /// This takes the instruction to expand, the associated machine basic
867 /// block, the number of args, and whether or not the second arg is
868 /// in memory or not.
869 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
870 unsigned argNum, bool inMem) const;
872 /// Utility functions to emit monitor and mwait instructions. These
873 /// need to make sure that the arguments to the intrinsic are in the
874 /// correct registers.
875 MachineBasicBlock *EmitMonitor(MachineInstr *MI,
876 MachineBasicBlock *BB) const;
877 MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const;
879 /// Utility function to emit atomic bitwise operations (and, or, xor).
880 /// It takes the bitwise instruction to expand, the associated machine basic
881 /// block, and the associated X86 opcodes for reg/reg and reg/imm.
882 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
883 MachineInstr *BInstr,
884 MachineBasicBlock *BB,
891 const TargetRegisterClass *RC,
892 bool Invert = false) const;
894 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
895 MachineInstr *BInstr,
896 MachineBasicBlock *BB,
901 bool Invert = false) const;
903 /// Utility function to emit atomic min and max. It takes the min/max
904 /// instruction to expand, the associated basic block, and the associated
905 /// cmov opcode for moving the min or max value.
906 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
907 MachineBasicBlock *BB,
908 unsigned cmovOpc) const;
910 // Utility function to emit the low-level va_arg code for X86-64.
911 MachineBasicBlock *EmitVAARG64WithCustomInserter(
913 MachineBasicBlock *MBB) const;
915 /// Utility function to emit the xmm reg save portion of va_start.
916 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
917 MachineInstr *BInstr,
918 MachineBasicBlock *BB) const;
920 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
921 MachineBasicBlock *BB) const;
923 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
924 MachineBasicBlock *BB) const;
926 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
927 MachineBasicBlock *BB,
930 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
931 MachineBasicBlock *BB) const;
933 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
934 MachineBasicBlock *BB) const;
936 /// Emit nodes that will be selected as "test Op0,Op0", or something
937 /// equivalent, for use with the given x86 condition code.
938 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
940 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
941 /// equivalent, for use with the given x86 condition code.
942 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
943 SelectionDAG &DAG) const;
945 /// Convert a comparison if required by the subtarget.
946 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
950 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
954 #endif // X86ISELLOWERING_H