1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
28 // X86 Specific DAG Nodes
30 // Start the numbering where the builtin ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 /// BSF - Bit scan forward.
34 /// BSR - Bit scan reverse.
38 /// SHLD, SHRD - Double shift instructions. These correspond to
39 /// X86::SHLDxx and X86::SHRDxx instructions.
43 /// FAND - Bitwise logical AND of floating point values. This corresponds
44 /// to X86::ANDPS or X86::ANDPD.
47 /// FOR - Bitwise logical OR of floating point values. This corresponds
48 /// to X86::ORPS or X86::ORPD.
51 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
52 /// to X86::XORPS or X86::XORPD.
55 /// FSRL - Bitwise logical right shift of floating point values. These
56 /// corresponds to X86::PSRLDQ.
59 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
60 /// integer source in memory and FP reg result. This corresponds to the
61 /// X86::FILD*m instructions. It has three inputs (token chain, address,
62 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
63 /// also produces a flag).
67 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
68 /// integer destination in memory and a FP reg source. This corresponds
69 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
70 /// has two inputs (token chain and address) and two outputs (int value
76 /// FLD - This instruction implements an extending load to FP stack slots.
77 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
78 /// operand, ptr to load from, and a ValueType node indicating the type
82 /// FST - This instruction implements a truncating store to FP stack
83 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
84 /// chain operand, value to store, address, and a ValueType to store it
88 /// CALL - These operations represent an abstract X86 call
89 /// instruction, which includes a bunch of information. In particular the
90 /// operands of these node are:
92 /// #0 - The incoming token chain
94 /// #2 - The number of arg bytes the caller pushes on the stack.
95 /// #3 - The number of arg bytes the callee pops off the stack.
96 /// #4 - The value to pass in AL/AX/EAX (optional)
97 /// #5 - The value to pass in DL/DX/EDX (optional)
99 /// The result values of these nodes are:
101 /// #0 - The outgoing token chain
102 /// #1 - The first register result value (optional)
103 /// #2 - The second register result value (optional)
107 /// RDTSC_DAG - This operation implements the lowering for
111 /// X86 compare and logical compare instructions.
114 /// X86 bit-test instructions.
117 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the flag
118 /// operand produced by a CMP instruction.
121 /// X86 conditional moves. Operand 0 and operand 1 are the two values
122 /// to select from. Operand 2 is the condition code, and operand 3 is the
123 /// flag operand produced by a CMP or TEST instruction. It also writes a
127 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
128 /// is the block to branch if condition is true, operand 2 is the
129 /// condition code, and operand 3 is the flag operand produced by a CMP
130 /// or TEST instruction.
133 /// Return with a flag operand. Operand 0 is the chain operand, operand
134 /// 1 is the number of bytes of stack to pop.
137 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
140 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
143 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
144 /// at function entry, used for PIC code.
147 /// Wrapper - A wrapper node for TargetConstantPool,
148 /// TargetExternalSymbol, and TargetGlobalAddress.
151 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
152 /// relative displacements.
155 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
156 /// i32, corresponds to X86::PEXTRB.
159 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
160 /// i32, corresponds to X86::PEXTRW.
163 /// INSERTPS - Insert any element of a 4 x float vector into any element
164 /// of a destination 4 x floatvector.
167 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
168 /// corresponds to X86::PINSRB.
171 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
172 /// corresponds to X86::PINSRW.
175 /// PSHUFB - Shuffle 16 8-bit values within a vector.
178 /// FMAX, FMIN - Floating point max and min.
182 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
183 /// approximation. Note that these typically require refinement
184 /// in order to obtain suitable precision.
187 // TLSADDR - Thread Local Storage.
190 // SegmentBaseAddress - The address segment:0
193 // EH_RETURN - Exception Handling helpers.
196 /// TC_RETURN - Tail call return.
198 /// operand #1 callee (register or absolute)
199 /// operand #2 stack adjustment
200 /// operand #3 optional in flag
203 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
207 // FNSTCW16m - Store FP control world into i16 memory.
210 // VZEXT_MOVL - Vector move low and zero extend.
213 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
216 // VSHL, VSRL - Vector logical left / right shift.
219 // CMPPD, CMPPS - Vector double/float comparison.
220 // CMPPD, CMPPS - Vector double/float comparison.
223 // PCMP* - Vector integer comparisons.
224 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
225 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
227 // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results.
228 ADD, SUB, SMUL, UMUL,
229 INC, DEC, OR, XOR, AND,
231 // MUL_IMM - X86 specific multiply by immediate.
234 // PTEST - Vector bitwise comparisons
237 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
238 // according to %al. An operator is needed so that this can be expanded
239 // with control flow.
240 VASTART_SAVE_XMM_REGS,
242 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
243 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
244 // Atomic 64-bit binary operations.
245 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
255 /// Define some predicates that are used for node matching.
257 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
258 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
259 bool isPSHUFDMask(ShuffleVectorSDNode *N);
261 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
262 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
263 bool isPSHUFHWMask(ShuffleVectorSDNode *N);
265 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
266 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
267 bool isPSHUFLWMask(ShuffleVectorSDNode *N);
269 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
270 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
271 bool isSHUFPMask(ShuffleVectorSDNode *N);
273 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
274 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
275 bool isMOVHLPSMask(ShuffleVectorSDNode *N);
277 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
278 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
280 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N);
282 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
283 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}.
284 bool isMOVLPMask(ShuffleVectorSDNode *N);
286 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
287 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}.
288 /// as well as MOVLHPS.
289 bool isMOVHPMask(ShuffleVectorSDNode *N);
291 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
292 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
293 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
295 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
296 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
297 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
299 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
300 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
302 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N);
304 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
305 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
307 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N);
309 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
310 /// specifies a shuffle of elements that is suitable for input to MOVSS,
311 /// MOVSD, and MOVD, i.e. setting the lowest element.
312 bool isMOVLMask(ShuffleVectorSDNode *N);
314 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
315 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
316 bool isMOVSHDUPMask(ShuffleVectorSDNode *N);
318 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
319 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
320 bool isMOVSLDUPMask(ShuffleVectorSDNode *N);
322 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
323 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
324 bool isMOVDDUPMask(ShuffleVectorSDNode *N);
326 /// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand
327 /// specifies a shuffle of elements that is suitable for input to PALIGNR.
328 bool isPALIGNRMask(ShuffleVectorSDNode *N);
330 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
331 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
333 unsigned getShuffleSHUFImmediate(SDNode *N);
335 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
336 /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction.
337 unsigned getShufflePSHUFHWImmediate(SDNode *N);
339 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
340 /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction.
341 unsigned getShufflePSHUFLWImmediate(SDNode *N);
343 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
344 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
345 unsigned getShufflePALIGNRImmediate(SDNode *N);
347 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
349 bool isZeroNode(SDValue Elt);
351 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
352 /// fit into displacement field of the instruction.
353 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
354 bool hasSymbolicDisplacement = true);
357 //===--------------------------------------------------------------------===//
358 // X86TargetLowering - X86 Implementation of the TargetLowering interface
359 class X86TargetLowering : public TargetLowering {
360 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
361 int RegSaveFrameIndex; // X86-64 vararg func register save area.
362 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
363 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
364 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
365 int BytesCallerReserves; // Number of arg bytes caller makes.
368 explicit X86TargetLowering(X86TargetMachine &TM);
370 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
372 SDValue getPICJumpTableRelocBase(SDValue Table,
373 SelectionDAG &DAG) const;
375 // Return the number of bytes that a function should pop when it returns (in
376 // addition to the space used by the return address).
378 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
380 // Return the number of bytes that the caller reserves for arguments passed
382 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
384 /// getStackPtrReg - Return the stack pointer register we are using: either
386 unsigned getStackPtrReg() const { return X86StackPtr; }
388 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
389 /// function arguments in the caller parameter area. For X86, aggregates
390 /// that contains are placed at 16-byte boundaries while the rest are at
391 /// 4-byte boundaries.
392 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
394 /// getOptimalMemOpType - Returns the target specific optimal type for load
395 /// and store operations as a result of memset, memcpy, and memmove
396 /// lowering. It returns EVT::iAny if SelectionDAG should be responsible for
398 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
399 bool isSrcConst, bool isSrcStr,
400 SelectionDAG &DAG) const;
402 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
403 /// unaligned memory accesses. of the specified type.
404 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
408 /// LowerOperation - Provide custom lowering hooks for some operations.
410 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
412 /// ReplaceNodeResults - Replace the results of node with an illegal result
413 /// type with new values built out of custom code.
415 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
419 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
421 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
422 MachineBasicBlock *MBB,
423 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
426 /// getTargetNodeName - This method returns the name of a target specific
428 virtual const char *getTargetNodeName(unsigned Opcode) const;
430 /// getSetCCResultType - Return the ISD::SETCC ValueType
431 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
433 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
434 /// in Mask are known to be either zero or one and return them in the
435 /// KnownZero/KnownOne bitsets.
436 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
440 const SelectionDAG &DAG,
441 unsigned Depth = 0) const;
444 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
446 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG);
448 virtual bool ExpandInlineAsm(CallInst *CI) const;
450 ConstraintType getConstraintType(const std::string &Constraint) const;
452 std::vector<unsigned>
453 getRegClassForInlineAsmConstraint(const std::string &Constraint,
456 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
458 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
459 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
460 /// true it means one of the asm constraint of the inline asm instruction
461 /// being processed is 'm'.
462 virtual void LowerAsmOperandForConstraint(SDValue Op,
463 char ConstraintLetter,
465 std::vector<SDValue> &Ops,
466 SelectionDAG &DAG) const;
468 /// getRegForInlineAsmConstraint - Given a physical register constraint
469 /// (e.g. {edx}), return the register number and the register class for the
470 /// register. This should only be used for C_Register constraints. On
471 /// error, this returns a register number of 0.
472 std::pair<unsigned, const TargetRegisterClass*>
473 getRegForInlineAsmConstraint(const std::string &Constraint,
476 /// isLegalAddressingMode - Return true if the addressing mode represented
477 /// by AM is legal for this target, for a load/store of the specified type.
478 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
480 /// isTruncateFree - Return true if it's free to truncate a value of
481 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
482 /// register EAX to i16 by referencing its sub-register AX.
483 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
484 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
486 /// isZExtFree - Return true if any actual instruction that defines a
487 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
488 /// register. This does not necessarily include registers defined in
489 /// unknown ways, such as incoming arguments, or copies from unknown
490 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
491 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
492 /// all instructions that define 32-bit values implicit zero-extend the
493 /// result out to 64 bits.
494 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const;
495 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
497 /// isNarrowingProfitable - Return true if it's profitable to narrow
498 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
499 /// from i32 to i8 but not from i32 to i16.
500 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
502 /// isFPImmLegal - Returns true if the target can instruction select the
503 /// specified FP immediate natively. If false, the legalizer will
504 /// materialize the FP immediate as a load from a constant pool.
505 virtual bool isFPImmLegal(const APFloat &Imm) const;
507 /// isShuffleMaskLegal - Targets can use this to indicate that they only
508 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
509 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
510 /// values are assumed to be legal.
511 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
514 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
515 /// used by Targets can use this to indicate if there is a suitable
516 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
518 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
521 /// ShouldShrinkFPConstant - If true, then instruction selection should
522 /// seek to shrink the FP constant of the specified type to a smaller type
523 /// in order to save space and / or reduce runtime.
524 virtual bool ShouldShrinkFPConstant(EVT VT) const {
525 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
526 // expensive than a straight movsd. On the other hand, it's important to
527 // shrink long double fp constant since fldt is very slow.
528 return !X86ScalarSSEf64 || VT == MVT::f80;
531 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
532 /// for tail call optimization. Targets which want to do tail call
533 /// optimization should implement this function.
535 IsEligibleForTailCallOptimization(SDValue Callee,
536 CallingConv::ID CalleeCC,
538 const SmallVectorImpl<ISD::InputArg> &Ins,
539 SelectionDAG& DAG) const;
541 virtual const X86Subtarget* getSubtarget() {
545 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
546 /// computed in an SSE register, not on the X87 floating point stack.
547 bool isScalarFPTypeInSSEReg(EVT VT) const {
548 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
549 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
552 /// getWidenVectorType: given a vector type, returns the type to widen
553 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
554 /// If there is no vector type that we want to widen to, returns EVT::Other
555 /// When and were to widen is target dependent based on the cost of
556 /// scalarizing vs using the wider vector type.
557 virtual EVT getWidenVectorType(EVT VT) const;
559 /// createFastISel - This method returns a target specific FastISel object,
560 /// or null if the target does not support "fast" ISel.
562 createFastISel(MachineFunction &mf,
563 MachineModuleInfo *mmi, DwarfWriter *dw,
564 DenseMap<const Value *, unsigned> &,
565 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
566 DenseMap<const AllocaInst *, int> &
568 , SmallSet<Instruction*, 8> &
572 /// getFunctionAlignment - Return the Log2 alignment of this function.
573 virtual unsigned getFunctionAlignment(const Function *F) const;
576 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
577 /// make the right decision when generating code for different targets.
578 const X86Subtarget *Subtarget;
579 const X86RegisterInfo *RegInfo;
580 const TargetData *TD;
582 /// X86StackPtr - X86 physical register used as stack ptr.
583 unsigned X86StackPtr;
585 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
586 /// floating point ops.
587 /// When SSE is available, use it for f32 operations.
588 /// When SSE2 is available, use it for f64 operations.
589 bool X86ScalarSSEf32;
590 bool X86ScalarSSEf64;
592 /// LegalFPImmediates - A list of legal fp immediates.
593 std::vector<APFloat> LegalFPImmediates;
595 /// addLegalFPImmediate - Indicate that this x86 target can instruction
596 /// select the specified FP immediate natively.
597 void addLegalFPImmediate(const APFloat& Imm) {
598 LegalFPImmediates.push_back(Imm);
601 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
602 CallingConv::ID CallConv, bool isVarArg,
603 const SmallVectorImpl<ISD::InputArg> &Ins,
604 DebugLoc dl, SelectionDAG &DAG,
605 SmallVectorImpl<SDValue> &InVals);
606 SDValue LowerMemArgument(SDValue Chain,
607 CallingConv::ID CallConv,
608 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
609 DebugLoc dl, SelectionDAG &DAG,
610 const CCValAssign &VA, MachineFrameInfo *MFI,
612 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
613 DebugLoc dl, SelectionDAG &DAG,
614 const CCValAssign &VA,
615 ISD::ArgFlagsTy Flags);
617 // Call lowering helpers.
618 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv);
619 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
620 SDValue Chain, bool IsTailCall, bool Is64Bit,
621 int FPDiff, DebugLoc dl);
623 CCAssignFn *CCAssignFnForNode(CallingConv::ID CallConv) const;
624 NameDecorationStyle NameDecorationForCallConv(CallingConv::ID CallConv);
625 unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG);
627 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
630 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG);
631 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG);
632 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG);
633 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
634 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG);
635 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
636 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
637 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
638 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
639 int64_t Offset, SelectionDAG &DAG) const;
640 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
641 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
642 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG);
643 SDValue LowerShift(SDValue Op, SelectionDAG &DAG);
644 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
646 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
647 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG);
648 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG);
649 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG);
650 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG);
651 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG);
652 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG);
653 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG);
654 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG);
655 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
656 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG);
657 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG);
658 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG);
659 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG);
660 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
661 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
662 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG);
663 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG);
664 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG);
665 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
666 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
667 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
668 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG);
669 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG);
670 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG);
671 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
672 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG);
673 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG);
674 SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG);
675 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG);
677 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG);
678 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG);
679 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG);
682 LowerFormalArguments(SDValue Chain,
683 CallingConv::ID CallConv, bool isVarArg,
684 const SmallVectorImpl<ISD::InputArg> &Ins,
685 DebugLoc dl, SelectionDAG &DAG,
686 SmallVectorImpl<SDValue> &InVals);
688 LowerCall(SDValue Chain, SDValue Callee,
689 CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
690 const SmallVectorImpl<ISD::OutputArg> &Outs,
691 const SmallVectorImpl<ISD::InputArg> &Ins,
692 DebugLoc dl, SelectionDAG &DAG,
693 SmallVectorImpl<SDValue> &InVals);
696 LowerReturn(SDValue Chain,
697 CallingConv::ID CallConv, bool isVarArg,
698 const SmallVectorImpl<ISD::OutputArg> &Outs,
699 DebugLoc dl, SelectionDAG &DAG);
701 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
702 SelectionDAG &DAG, unsigned NewOp);
704 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
706 SDValue Dst, SDValue Src,
707 SDValue Size, unsigned Align,
708 const Value *DstSV, uint64_t DstSVOff);
709 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
711 SDValue Dst, SDValue Src,
712 SDValue Size, unsigned Align,
714 const Value *DstSV, uint64_t DstSVOff,
715 const Value *SrcSV, uint64_t SrcSVOff);
717 /// Utility function to emit string processing sse4.2 instructions
718 /// that return in xmm0.
719 /// This takes the instruction to expand, the associated machine basic
720 /// block, the number of args, and whether or not the second arg is
721 /// in memory or not.
722 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
723 unsigned argNum, bool inMem) const;
725 /// Utility function to emit atomic bitwise operations (and, or, xor).
726 /// It takes the bitwise instruction to expand, the associated machine basic
727 /// block, and the associated X86 opcodes for reg/reg and reg/imm.
728 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
729 MachineInstr *BInstr,
730 MachineBasicBlock *BB,
738 TargetRegisterClass *RC,
739 bool invSrc = false) const;
741 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
742 MachineInstr *BInstr,
743 MachineBasicBlock *BB,
748 bool invSrc = false) const;
750 /// Utility function to emit atomic min and max. It takes the min/max
751 /// instruction to expand, the associated basic block, and the associated
752 /// cmov opcode for moving the min or max value.
753 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
754 MachineBasicBlock *BB,
755 unsigned cmovOpc) const;
757 /// Utility function to emit the xmm reg save portion of va_start.
758 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
759 MachineInstr *BInstr,
760 MachineBasicBlock *BB) const;
762 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
763 MachineBasicBlock *BB,
764 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
766 /// Emit nodes that will be selected as "test Op0,Op0", or something
767 /// equivalent, for use with the given x86 condition code.
768 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG);
770 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
771 /// equivalent, for use with the given x86 condition code.
772 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
777 FastISel *createFastISel(MachineFunction &mf,
778 MachineModuleInfo *mmi, DwarfWriter *dw,
779 DenseMap<const Value *, unsigned> &,
780 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
781 DenseMap<const AllocaInst *, int> &
783 , SmallSet<Instruction*, 8> &
789 #endif // X86ISELLOWERING_H