1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
29 // X86 Specific DAG Nodes
31 // Start the numbering where the builtin ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 /// BSF - Bit scan forward.
35 /// BSR - Bit scan reverse.
39 /// SHLD, SHRD - Double shift instructions. These correspond to
40 /// X86::SHLDxx and X86::SHRDxx instructions.
44 /// FAND - Bitwise logical AND of floating point values. This corresponds
45 /// to X86::ANDPS or X86::ANDPD.
48 /// FOR - Bitwise logical OR of floating point values. This corresponds
49 /// to X86::ORPS or X86::ORPD.
52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
53 /// to X86::XORPS or X86::XORPD.
56 /// FSRL - Bitwise logical right shift of floating point values. These
57 /// corresponds to X86::PSRLDQ.
60 /// CALL - These operations represent an abstract X86 call
61 /// instruction, which includes a bunch of information. In particular the
62 /// operands of these node are:
64 /// #0 - The incoming token chain
66 /// #2 - The number of arg bytes the caller pushes on the stack.
67 /// #3 - The number of arg bytes the callee pops off the stack.
68 /// #4 - The value to pass in AL/AX/EAX (optional)
69 /// #5 - The value to pass in DL/DX/EDX (optional)
71 /// The result values of these nodes are:
73 /// #0 - The outgoing token chain
74 /// #1 - The first register result value (optional)
75 /// #2 - The second register result value (optional)
79 /// RDTSC_DAG - This operation implements the lowering for
83 /// X86 compare and logical compare instructions.
86 /// X86 bit-test instructions.
89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
90 /// operand, usually produced by a CMP instruction.
93 // Same as SETCC except it's materialized with a sbb and the value is all
94 // one's or all zero's.
95 SETCC_CARRY, // R = carry_bit ? ~0 : 0
97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
98 /// Operands are two FP values to compare; result is a mask of
99 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
102 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
103 /// result in an integer GPR. Needs masking for scalar result.
106 /// X86 conditional moves. Operand 0 and operand 1 are the two values
107 /// to select from. Operand 2 is the condition code, and operand 3 is the
108 /// flag operand produced by a CMP or TEST instruction. It also writes a
112 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
113 /// is the block to branch if condition is true, operand 2 is the
114 /// condition code, and operand 3 is the flag operand produced by a CMP
115 /// or TEST instruction.
118 /// Return with a flag operand. Operand 0 is the chain operand, operand
119 /// 1 is the number of bytes of stack to pop.
122 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
125 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
128 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
129 /// at function entry, used for PIC code.
132 /// Wrapper - A wrapper node for TargetConstantPool,
133 /// TargetExternalSymbol, and TargetGlobalAddress.
136 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
137 /// relative displacements.
140 /// MOVQ2DQ - Copies a 64-bit value from an MMX vector to the low word
141 /// of an XMM vector, with the high word zero filled.
144 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
145 /// to an MMX vector. If you think this is too close to the previous
146 /// mnemonic, so do I; blame Intel.
149 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
150 /// i32, corresponds to X86::PEXTRB.
153 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
154 /// i32, corresponds to X86::PEXTRW.
157 /// INSERTPS - Insert any element of a 4 x float vector into any element
158 /// of a destination 4 x floatvector.
161 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
162 /// corresponds to X86::PINSRB.
165 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
166 /// corresponds to X86::PINSRW.
169 /// PSHUFB - Shuffle 16 8-bit values within a vector.
172 /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
175 /// PSIGNB/W/D - Copy integer sign.
176 PSIGNB, PSIGNW, PSIGND,
178 /// BLEND family of opcodes
181 /// FMAX, FMIN - Floating point max and min.
185 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
186 /// approximation. Note that these typically require refinement
187 /// in order to obtain suitable precision.
190 // TLSADDR - Thread Local Storage.
193 // TLSCALL - Thread Local Storage. When calling to an OS provided
194 // thunk at the address from an earlier relocation.
197 // EH_RETURN - Exception Handling helpers.
200 /// TC_RETURN - Tail call return.
202 /// operand #1 callee (register or absolute)
203 /// operand #2 stack adjustment
204 /// operand #3 optional in flag
207 // VZEXT_MOVL - Vector move low and zero extend.
210 // VSHL, VSRL - Vector logical left / right shift.
213 // CMPPD, CMPPS - Vector double/float comparison.
214 // CMPPD, CMPPS - Vector double/float comparison.
217 // PCMP* - Vector integer comparisons.
218 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
219 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
221 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
222 ADD, SUB, ADC, SBB, SMUL,
223 INC, DEC, OR, XOR, AND,
225 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
227 // MUL_IMM - X86 specific multiply by immediate.
230 // PTEST - Vector bitwise comparisons
233 // TESTP - Vector packed fp sign bitwise comparisons
236 // Several flavors of instructions with vector shuffle behaviors.
281 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
282 // according to %al. An operator is needed so that this can be expanded
283 // with control flow.
284 VASTART_SAVE_XMM_REGS,
286 // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
289 // SEG_ALLOCA - For allocating variable amounts of stack space when using
290 // segmented stacks. Check if the current stacklet has enough space, and
291 // falls back to heap allocation if not.
300 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
301 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
302 // Atomic 64-bit binary operations.
303 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
311 // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
316 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
319 // FNSTCW16m - Store FP control world into i16 memory.
322 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
323 /// integer destination in memory and a FP reg source. This corresponds
324 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
325 /// has two inputs (token chain and address) and two outputs (int value
326 /// and token chain).
331 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
332 /// integer source in memory and FP reg result. This corresponds to the
333 /// X86::FILD*m instructions. It has three inputs (token chain, address,
334 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
335 /// also produces a flag).
339 /// FLD - This instruction implements an extending load to FP stack slots.
340 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
341 /// operand, ptr to load from, and a ValueType node indicating the type
345 /// FST - This instruction implements a truncating store to FP stack
346 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
347 /// chain operand, value to store, address, and a ValueType to store it
351 /// VAARG_64 - This instruction grabs the address of the next argument
352 /// from a va_list. (reads and modifies the va_list in memory)
355 // WARNING: Do not add anything in the end unless you want the node to
356 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
357 // thought as target memory ops!
361 /// Define some predicates that are used for node matching.
363 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
364 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
365 bool isPSHUFDMask(ShuffleVectorSDNode *N);
367 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
368 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
369 bool isPSHUFHWMask(ShuffleVectorSDNode *N);
371 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
372 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
373 bool isPSHUFLWMask(ShuffleVectorSDNode *N);
375 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
376 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
377 bool isSHUFPMask(ShuffleVectorSDNode *N);
379 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
380 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
381 bool isMOVHLPSMask(ShuffleVectorSDNode *N);
383 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
384 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
386 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N);
388 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
389 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}.
390 bool isMOVLPMask(ShuffleVectorSDNode *N);
392 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
393 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}.
394 /// as well as MOVLHPS.
395 bool isMOVLHPSMask(ShuffleVectorSDNode *N);
397 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
398 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
399 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
401 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
402 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
403 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
405 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
406 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
408 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N);
410 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
411 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
413 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N);
415 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
416 /// specifies a shuffle of elements that is suitable for input to MOVSS,
417 /// MOVSD, and MOVD, i.e. setting the lowest element.
418 bool isMOVLMask(ShuffleVectorSDNode *N);
420 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
421 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
422 bool isMOVSHDUPMask(ShuffleVectorSDNode *N, const X86Subtarget *Subtarget);
424 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
425 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
426 bool isMOVSLDUPMask(ShuffleVectorSDNode *N, const X86Subtarget *Subtarget);
428 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
429 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
430 bool isMOVDDUPMask(ShuffleVectorSDNode *N);
432 /// isVEXTRACTF128Index - Return true if the specified
433 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
434 /// suitable for input to VEXTRACTF128.
435 bool isVEXTRACTF128Index(SDNode *N);
437 /// isVINSERTF128Index - Return true if the specified
438 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
439 /// suitable for input to VINSERTF128.
440 bool isVINSERTF128Index(SDNode *N);
442 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
443 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
445 unsigned getShuffleSHUFImmediate(SDNode *N);
447 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
448 /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction.
449 unsigned getShufflePSHUFHWImmediate(SDNode *N);
451 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
452 /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction.
453 unsigned getShufflePSHUFLWImmediate(SDNode *N);
455 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
456 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
457 unsigned getShufflePALIGNRImmediate(SDNode *N);
459 /// getExtractVEXTRACTF128Immediate - Return the appropriate
460 /// immediate to extract the specified EXTRACT_SUBVECTOR index
461 /// with VEXTRACTF128 instructions.
462 unsigned getExtractVEXTRACTF128Immediate(SDNode *N);
464 /// getInsertVINSERTF128Immediate - Return the appropriate
465 /// immediate to insert at the specified INSERT_SUBVECTOR index
466 /// with VINSERTF128 instructions.
467 unsigned getInsertVINSERTF128Immediate(SDNode *N);
469 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
471 bool isZeroNode(SDValue Elt);
473 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
474 /// fit into displacement field of the instruction.
475 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
476 bool hasSymbolicDisplacement = true);
479 /// isCalleePop - Determines whether the callee is required to pop its
480 /// own arguments. Callee pop is necessary to support tail calls.
481 bool isCalleePop(CallingConv::ID CallingConv,
482 bool is64Bit, bool IsVarArg, bool TailCallOpt);
485 //===--------------------------------------------------------------------===//
486 // X86TargetLowering - X86 Implementation of the TargetLowering interface
487 class X86TargetLowering : public TargetLowering {
489 explicit X86TargetLowering(X86TargetMachine &TM);
491 virtual unsigned getJumpTableEncoding() const;
493 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
495 virtual const MCExpr *
496 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
497 const MachineBasicBlock *MBB, unsigned uid,
498 MCContext &Ctx) const;
500 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
502 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
503 SelectionDAG &DAG) const;
504 virtual const MCExpr *
505 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
506 unsigned JTI, MCContext &Ctx) const;
508 /// getStackPtrReg - Return the stack pointer register we are using: either
510 unsigned getStackPtrReg() const { return X86StackPtr; }
512 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
513 /// function arguments in the caller parameter area. For X86, aggregates
514 /// that contains are placed at 16-byte boundaries while the rest are at
515 /// 4-byte boundaries.
516 virtual unsigned getByValTypeAlignment(Type *Ty) const;
518 /// getOptimalMemOpType - Returns the target specific optimal type for load
519 /// and store operations as a result of memset, memcpy, and memmove
520 /// lowering. If DstAlign is zero that means it's safe to destination
521 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
522 /// means there isn't a need to check it against alignment requirement,
523 /// probably because the source does not need to be loaded. If
524 /// 'NonScalarIntSafe' is true, that means it's safe to return a
525 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
526 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
527 /// constant so it does not need to be loaded.
528 /// It returns EVT::Other if the type should be determined using generic
529 /// target-independent logic.
531 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
532 bool NonScalarIntSafe, bool MemcpyStrSrc,
533 MachineFunction &MF) const;
535 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
536 /// unaligned memory accesses. of the specified type.
537 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
541 /// LowerOperation - Provide custom lowering hooks for some operations.
543 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
545 /// ReplaceNodeResults - Replace the results of node with an illegal result
546 /// type with new values built out of custom code.
548 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
549 SelectionDAG &DAG) const;
552 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
554 /// isTypeDesirableForOp - Return true if the target has native support for
555 /// the specified value type and it is 'desirable' to use the type for the
556 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
557 /// instruction encodings are longer and some i16 instructions are slow.
558 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
560 /// isTypeDesirable - Return true if the target has native support for the
561 /// specified value type and it is 'desirable' to use the type. e.g. On x86
562 /// i16 is legal, but undesirable since i16 instruction encodings are longer
563 /// and some i16 instructions are slow.
564 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
566 virtual MachineBasicBlock *
567 EmitInstrWithCustomInserter(MachineInstr *MI,
568 MachineBasicBlock *MBB) const;
571 /// getTargetNodeName - This method returns the name of a target specific
573 virtual const char *getTargetNodeName(unsigned Opcode) const;
575 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
576 virtual EVT getSetCCResultType(EVT VT) const;
578 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
579 /// in Mask are known to be either zero or one and return them in the
580 /// KnownZero/KnownOne bitsets.
581 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
585 const SelectionDAG &DAG,
586 unsigned Depth = 0) const;
588 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
589 // operation that are sign bits.
590 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
591 unsigned Depth) const;
594 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
596 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
598 virtual bool ExpandInlineAsm(CallInst *CI) const;
600 ConstraintType getConstraintType(const std::string &Constraint) const;
602 /// Examine constraint string and operand type and determine a weight value.
603 /// The operand object must already have been set up with the operand type.
604 virtual ConstraintWeight getSingleConstraintMatchWeight(
605 AsmOperandInfo &info, const char *constraint) const;
607 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
609 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
610 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
611 /// true it means one of the asm constraint of the inline asm instruction
612 /// being processed is 'm'.
613 virtual void LowerAsmOperandForConstraint(SDValue Op,
614 std::string &Constraint,
615 std::vector<SDValue> &Ops,
616 SelectionDAG &DAG) const;
618 /// getRegForInlineAsmConstraint - Given a physical register constraint
619 /// (e.g. {edx}), return the register number and the register class for the
620 /// register. This should only be used for C_Register constraints. On
621 /// error, this returns a register number of 0.
622 std::pair<unsigned, const TargetRegisterClass*>
623 getRegForInlineAsmConstraint(const std::string &Constraint,
626 /// isLegalAddressingMode - Return true if the addressing mode represented
627 /// by AM is legal for this target, for a load/store of the specified type.
628 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
630 /// isTruncateFree - Return true if it's free to truncate a value of
631 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
632 /// register EAX to i16 by referencing its sub-register AX.
633 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
634 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
636 /// isZExtFree - Return true if any actual instruction that defines a
637 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
638 /// register. This does not necessarily include registers defined in
639 /// unknown ways, such as incoming arguments, or copies from unknown
640 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
641 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
642 /// all instructions that define 32-bit values implicit zero-extend the
643 /// result out to 64 bits.
644 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
645 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
647 /// isNarrowingProfitable - Return true if it's profitable to narrow
648 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
649 /// from i32 to i8 but not from i32 to i16.
650 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
652 /// isFPImmLegal - Returns true if the target can instruction select the
653 /// specified FP immediate natively. If false, the legalizer will
654 /// materialize the FP immediate as a load from a constant pool.
655 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
657 /// isShuffleMaskLegal - Targets can use this to indicate that they only
658 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
659 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
660 /// values are assumed to be legal.
661 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
664 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
665 /// used by Targets can use this to indicate if there is a suitable
666 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
668 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
671 /// ShouldShrinkFPConstant - If true, then instruction selection should
672 /// seek to shrink the FP constant of the specified type to a smaller type
673 /// in order to save space and / or reduce runtime.
674 virtual bool ShouldShrinkFPConstant(EVT VT) const {
675 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
676 // expensive than a straight movsd. On the other hand, it's important to
677 // shrink long double fp constant since fldt is very slow.
678 return !X86ScalarSSEf64 || VT == MVT::f80;
681 const X86Subtarget* getSubtarget() const {
685 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
686 /// computed in an SSE register, not on the X87 floating point stack.
687 bool isScalarFPTypeInSSEReg(EVT VT) const {
688 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
689 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
692 /// createFastISel - This method returns a target specific FastISel object,
693 /// or null if the target does not support "fast" ISel.
694 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
696 /// getStackCookieLocation - Return true if the target stores stack
697 /// protector cookies at a fixed offset in some non-standard address
698 /// space, and populates the address space and offset as
700 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
702 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
703 SelectionDAG &DAG) const;
706 std::pair<const TargetRegisterClass*, uint8_t>
707 findRepresentativeClass(EVT VT) const;
710 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
711 /// make the right decision when generating code for different targets.
712 const X86Subtarget *Subtarget;
713 const X86RegisterInfo *RegInfo;
714 const TargetData *TD;
716 /// X86StackPtr - X86 physical register used as stack ptr.
717 unsigned X86StackPtr;
719 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
720 /// floating point ops.
721 /// When SSE is available, use it for f32 operations.
722 /// When SSE2 is available, use it for f64 operations.
723 bool X86ScalarSSEf32;
724 bool X86ScalarSSEf64;
726 /// LegalFPImmediates - A list of legal fp immediates.
727 std::vector<APFloat> LegalFPImmediates;
729 /// addLegalFPImmediate - Indicate that this x86 target can instruction
730 /// select the specified FP immediate natively.
731 void addLegalFPImmediate(const APFloat& Imm) {
732 LegalFPImmediates.push_back(Imm);
735 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
736 CallingConv::ID CallConv, bool isVarArg,
737 const SmallVectorImpl<ISD::InputArg> &Ins,
738 DebugLoc dl, SelectionDAG &DAG,
739 SmallVectorImpl<SDValue> &InVals) const;
740 SDValue LowerMemArgument(SDValue Chain,
741 CallingConv::ID CallConv,
742 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
743 DebugLoc dl, SelectionDAG &DAG,
744 const CCValAssign &VA, MachineFrameInfo *MFI,
746 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
747 DebugLoc dl, SelectionDAG &DAG,
748 const CCValAssign &VA,
749 ISD::ArgFlagsTy Flags) const;
751 // Call lowering helpers.
753 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
754 /// for tail call optimization. Targets which want to do tail call
755 /// optimization should implement this function.
756 bool IsEligibleForTailCallOptimization(SDValue Callee,
757 CallingConv::ID CalleeCC,
759 bool isCalleeStructRet,
760 bool isCallerStructRet,
761 const SmallVectorImpl<ISD::OutputArg> &Outs,
762 const SmallVectorImpl<SDValue> &OutVals,
763 const SmallVectorImpl<ISD::InputArg> &Ins,
764 SelectionDAG& DAG) const;
765 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
766 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
767 SDValue Chain, bool IsTailCall, bool Is64Bit,
768 int FPDiff, DebugLoc dl) const;
770 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
771 SelectionDAG &DAG) const;
773 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
774 bool isSigned) const;
776 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
777 SelectionDAG &DAG) const;
778 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
779 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
780 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
781 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
782 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
783 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
784 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
785 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
786 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
787 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
788 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
789 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
790 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
791 int64_t Offset, SelectionDAG &DAG) const;
792 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
793 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
794 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
795 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
796 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const;
797 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
798 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
799 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
800 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
801 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
802 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
803 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
804 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
805 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
806 SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const;
807 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
808 DebugLoc dl, SelectionDAG &DAG) const;
809 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
810 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
811 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
812 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
813 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
814 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
815 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
816 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
817 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
818 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
819 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
820 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
821 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
822 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
823 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
824 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
825 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
826 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
827 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
828 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
829 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
830 SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) const;
831 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
832 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
833 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
835 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
836 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
837 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
838 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const;
839 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
840 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
842 // Utility functions to help LowerVECTOR_SHUFFLE
843 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const;
846 LowerFormalArguments(SDValue Chain,
847 CallingConv::ID CallConv, bool isVarArg,
848 const SmallVectorImpl<ISD::InputArg> &Ins,
849 DebugLoc dl, SelectionDAG &DAG,
850 SmallVectorImpl<SDValue> &InVals) const;
852 LowerCall(SDValue Chain, SDValue Callee,
853 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
854 const SmallVectorImpl<ISD::OutputArg> &Outs,
855 const SmallVectorImpl<SDValue> &OutVals,
856 const SmallVectorImpl<ISD::InputArg> &Ins,
857 DebugLoc dl, SelectionDAG &DAG,
858 SmallVectorImpl<SDValue> &InVals) const;
861 LowerReturn(SDValue Chain,
862 CallingConv::ID CallConv, bool isVarArg,
863 const SmallVectorImpl<ISD::OutputArg> &Outs,
864 const SmallVectorImpl<SDValue> &OutVals,
865 DebugLoc dl, SelectionDAG &DAG) const;
867 virtual bool isUsedByReturnOnly(SDNode *N) const;
869 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
872 getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
873 ISD::NodeType ExtendKind) const;
876 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
878 const SmallVectorImpl<ISD::OutputArg> &Outs,
879 LLVMContext &Context) const;
881 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
882 SelectionDAG &DAG, unsigned NewOp) const;
884 /// Utility function to emit string processing sse4.2 instructions
885 /// that return in xmm0.
886 /// This takes the instruction to expand, the associated machine basic
887 /// block, the number of args, and whether or not the second arg is
888 /// in memory or not.
889 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
890 unsigned argNum, bool inMem) const;
892 /// Utility functions to emit monitor and mwait instructions. These
893 /// need to make sure that the arguments to the intrinsic are in the
894 /// correct registers.
895 MachineBasicBlock *EmitMonitor(MachineInstr *MI,
896 MachineBasicBlock *BB) const;
897 MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const;
899 /// Utility function to emit atomic bitwise operations (and, or, xor).
900 /// It takes the bitwise instruction to expand, the associated machine basic
901 /// block, and the associated X86 opcodes for reg/reg and reg/imm.
902 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
903 MachineInstr *BInstr,
904 MachineBasicBlock *BB,
911 TargetRegisterClass *RC,
912 bool invSrc = false) const;
914 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
915 MachineInstr *BInstr,
916 MachineBasicBlock *BB,
921 bool invSrc = false) const;
923 /// Utility function to emit atomic min and max. It takes the min/max
924 /// instruction to expand, the associated basic block, and the associated
925 /// cmov opcode for moving the min or max value.
926 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
927 MachineBasicBlock *BB,
928 unsigned cmovOpc) const;
930 // Utility function to emit the low-level va_arg code for X86-64.
931 MachineBasicBlock *EmitVAARG64WithCustomInserter(
933 MachineBasicBlock *MBB) const;
935 /// Utility function to emit the xmm reg save portion of va_start.
936 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
937 MachineInstr *BInstr,
938 MachineBasicBlock *BB) const;
940 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
941 MachineBasicBlock *BB) const;
943 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
944 MachineBasicBlock *BB) const;
946 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
947 MachineBasicBlock *BB,
950 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
951 MachineBasicBlock *BB) const;
953 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
954 MachineBasicBlock *BB) const;
956 /// Emit nodes that will be selected as "test Op0,Op0", or something
957 /// equivalent, for use with the given x86 condition code.
958 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
960 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
961 /// equivalent, for use with the given x86 condition code.
962 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
963 SelectionDAG &DAG) const;
967 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
971 #endif // X86ISELLOWERING_H