1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
25 // X86 Specific DAG Nodes
27 // Start the numbering where the builtin ops leave off.
28 FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
30 /// SHLD, SHRD - Double shift instructions. These correspond to
31 /// X86::SHLDxx and X86::SHRDxx instructions.
35 /// FAND - Bitwise logical AND of floating point values. This corresponds
36 /// to X86::ANDPS or X86::ANDPD.
39 /// FOR - Bitwise logical OR of floating point values. This corresponds
40 /// to X86::ORPS or X86::ORPD.
43 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
44 /// to X86::XORPS or X86::XORPD.
47 /// FSRL - Bitwise logical right shift of floating point values. These
48 /// corresponds to X86::PSRLDQ.
51 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
52 /// integer source in memory and FP reg result. This corresponds to the
53 /// X86::FILD*m instructions. It has three inputs (token chain, address,
54 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
55 /// also produces a flag).
59 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
60 /// integer destination in memory and a FP reg source. This corresponds
61 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
62 /// has two inputs (token chain and address) and two outputs (int value
68 /// FLD - This instruction implements an extending load to FP stack slots.
69 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
70 /// operand, ptr to load from, and a ValueType node indicating the type
74 /// FST - This instruction implements a truncating store to FP stack
75 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
76 /// chain operand, value to store, address, and a ValueType to store it
80 /// FP_GET_RESULT - This corresponds to FpGETRESULT pseudo instruction
81 /// which copies from ST(0) to the destination. It takes a chain and
82 /// writes a RFP result and a chain.
85 /// FP_SET_RESULT - This corresponds to FpSETRESULT pseudo instruction
86 /// which copies the source operand to ST(0). It takes a chain+value and
87 /// returns a chain and a flag.
90 /// CALL/TAILCALL - These operations represent an abstract X86 call
91 /// instruction, which includes a bunch of information. In particular the
92 /// operands of these node are:
94 /// #0 - The incoming token chain
96 /// #2 - The number of arg bytes the caller pushes on the stack.
97 /// #3 - The number of arg bytes the callee pops off the stack.
98 /// #4 - The value to pass in AL/AX/EAX (optional)
99 /// #5 - The value to pass in DL/DX/EDX (optional)
101 /// The result values of these nodes are:
103 /// #0 - The outgoing token chain
104 /// #1 - The first register result value (optional)
105 /// #2 - The second register result value (optional)
107 /// The CALL vs TAILCALL distinction boils down to whether the callee is
108 /// known not to modify the caller's stack frame, as is standard with
113 /// RDTSC_DAG - This operation implements the lowering for
117 /// X86 compare and logical compare instructions.
118 CMP, TEST, COMI, UCOMI,
120 /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
121 /// operand produced by a CMP instruction.
124 /// X86 conditional moves. Operand 1 and operand 2 are the two values
125 /// to select from (operand 1 is a R/W operand). Operand 3 is the
126 /// condition code, and operand 4 is the flag operand produced by a CMP
127 /// or TEST instruction. It also writes a flag result.
130 /// X86 conditional branches. Operand 1 is the chain operand, operand 2
131 /// is the block to branch if condition is true, operand 3 is the
132 /// condition code, and operand 4 is the flag operand produced by a CMP
133 /// or TEST instruction.
136 /// Return with a flag operand. Operand 1 is the chain operand, operand
137 /// 2 is the number of bytes of stack to pop.
140 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
143 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
146 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
147 /// at function entry, used for PIC code.
150 /// Wrapper - A wrapper node for TargetConstantPool,
151 /// TargetExternalSymbol, and TargetGlobalAddress.
154 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
155 /// relative displacements.
158 /// S2VEC - X86 version of SCALAR_TO_VECTOR. The destination base does not
159 /// have to match the operand type.
162 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
163 /// i32, corresponds to X86::PEXTRW.
166 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
167 /// corresponds to X86::PINSRW.
170 /// FMAX, FMIN - Floating point max and min.
174 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
175 /// approximation. Note that these typically require refinement
176 /// in order to obtain suitable precision.
179 // Thread Local Storage
180 TLSADDR, THREAD_POINTER,
182 // Exception Handling helpers
187 /// Define some predicates that are used for node matching.
189 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
190 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
191 bool isPSHUFDMask(SDNode *N);
193 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
194 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
195 bool isPSHUFHWMask(SDNode *N);
197 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
198 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
199 bool isPSHUFLWMask(SDNode *N);
201 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
202 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
203 bool isSHUFPMask(SDNode *N);
205 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
206 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
207 bool isMOVHLPSMask(SDNode *N);
209 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
210 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
212 bool isMOVHLPS_v_undef_Mask(SDNode *N);
214 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
215 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
216 bool isMOVLPMask(SDNode *N);
218 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
219 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
220 /// as well as MOVLHPS.
221 bool isMOVHPMask(SDNode *N);
223 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
224 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
225 bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false);
227 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
228 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
229 bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false);
231 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
232 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
234 bool isUNPCKL_v_undef_Mask(SDNode *N);
236 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
237 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
239 bool isUNPCKH_v_undef_Mask(SDNode *N);
241 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
242 /// specifies a shuffle of elements that is suitable for input to MOVSS,
243 /// MOVSD, and MOVD, i.e. setting the lowest element.
244 bool isMOVLMask(SDNode *N);
246 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
247 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
248 bool isMOVSHDUPMask(SDNode *N);
250 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
251 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
252 bool isMOVSLDUPMask(SDNode *N);
254 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
255 /// specifies a splat of a single element.
256 bool isSplatMask(SDNode *N);
258 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
259 /// specifies a splat of zero element.
260 bool isSplatLoMask(SDNode *N);
262 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
263 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
265 unsigned getShuffleSHUFImmediate(SDNode *N);
267 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
268 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
270 unsigned getShufflePSHUFHWImmediate(SDNode *N);
272 /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
273 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
275 unsigned getShufflePSHUFLWImmediate(SDNode *N);
278 //===--------------------------------------------------------------------===//
279 // X86TargetLowering - X86 Implementation of the TargetLowering interface
280 class X86TargetLowering : public TargetLowering {
281 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
282 int RegSaveFrameIndex; // X86-64 vararg func register save area.
283 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
284 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
285 int ReturnAddrIndex; // FrameIndex for return slot.
286 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
287 int BytesCallerReserves; // Number of arg bytes caller makes.
289 explicit X86TargetLowering(TargetMachine &TM);
291 // Return the number of bytes that a function should pop when it returns (in
292 // addition to the space used by the return address).
294 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
296 // Return the number of bytes that the caller reserves for arguments passed
298 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
300 /// getStackPtrReg - Return the stack pointer register we are using: either
302 unsigned getStackPtrReg() const { return X86StackPtr; }
304 /// LowerOperation - Provide custom lowering hooks for some operations.
306 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
308 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
310 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
311 MachineBasicBlock *MBB);
313 /// getTargetNodeName - This method returns the name of a target specific
315 virtual const char *getTargetNodeName(unsigned Opcode) const;
317 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
318 /// in Mask are known to be either zero or one and return them in the
319 /// KnownZero/KnownOne bitsets.
320 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
324 const SelectionDAG &DAG,
325 unsigned Depth = 0) const;
327 SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
329 ConstraintType getConstraintType(const std::string &Constraint) const;
331 std::vector<unsigned>
332 getRegClassForInlineAsmConstraint(const std::string &Constraint,
333 MVT::ValueType VT) const;
334 /// isOperandValidForConstraint - Return the specified operand (possibly
335 /// modified) if the specified SDOperand is valid for the specified target
336 /// constraint letter, otherwise return null.
337 SDOperand isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
340 /// getRegForInlineAsmConstraint - Given a physical register constraint
341 /// (e.g. {edx}), return the register number and the register class for the
342 /// register. This should only be used for C_Register constraints. On
343 /// error, this returns a register number of 0.
344 std::pair<unsigned, const TargetRegisterClass*>
345 getRegForInlineAsmConstraint(const std::string &Constraint,
346 MVT::ValueType VT) const;
348 /// isLegalAddressingMode - Return true if the addressing mode represented
349 /// by AM is legal for this target, for a load/store of the specified type.
350 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
352 /// isShuffleMaskLegal - Targets can use this to indicate that they only
353 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
354 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
355 /// values are assumed to be legal.
356 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
358 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
359 /// used by Targets can use this to indicate if there is a suitable
360 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
362 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
364 SelectionDAG &DAG) const;
366 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
367 /// make the right decision when generating code for different targets.
368 const X86Subtarget *Subtarget;
369 const MRegisterInfo *RegInfo;
371 /// X86StackPtr - X86 physical register used as stack ptr.
372 unsigned X86StackPtr;
374 /// X86ScalarSSE - Select between SSE2 or x87 floating point ops.
377 SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall,
378 unsigned CallingConv, SelectionDAG &DAG);
380 // C and StdCall Calling Convention implementation.
381 SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
382 bool isStdCall = false);
383 SDOperand LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC);
385 // X86-64 C Calling Convention implementation.
386 SDOperand LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG);
387 SDOperand LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,unsigned CC);
389 // Fast and FastCall Calling Convention implementation.
390 SDOperand LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG);
391 SDOperand LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC);
393 SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
394 SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
395 SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
396 SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
397 SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
398 SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
399 SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
400 SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
401 SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG);
402 SDOperand LowerShift(SDOperand Op, SelectionDAG &DAG);
403 SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
404 SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
405 SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
406 SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
407 SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG);
408 SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG, SDOperand Chain);
409 SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
410 SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
411 SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
412 SDOperand LowerMEMCPY(SDOperand Op, SelectionDAG &DAG);
413 SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
414 SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
415 SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
416 SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG);
417 SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
418 SDOperand LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG);
419 SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
420 SDOperand LowerVACOPY(SDOperand Op, SelectionDAG &DAG);
421 SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
422 SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
423 SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
424 SDOperand LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, SelectionDAG &DAG);
425 SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG);
426 SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG);
430 #endif // X86ISELLOWERING_H