1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86MachineFunctionInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Target/TargetOptions.h"
29 // X86 Specific DAG Nodes
31 // Start the numbering where the builtin ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 /// BSF - Bit scan forward.
35 /// BSR - Bit scan reverse.
39 /// SHLD, SHRD - Double shift instructions. These correspond to
40 /// X86::SHLDxx and X86::SHRDxx instructions.
44 /// FAND - Bitwise logical AND of floating point values. This corresponds
45 /// to X86::ANDPS or X86::ANDPD.
48 /// FOR - Bitwise logical OR of floating point values. This corresponds
49 /// to X86::ORPS or X86::ORPD.
52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
53 /// to X86::XORPS or X86::XORPD.
56 /// FSRL - Bitwise logical right shift of floating point values. These
57 /// corresponds to X86::PSRLDQ.
60 /// CALL - These operations represent an abstract X86 call
61 /// instruction, which includes a bunch of information. In particular the
62 /// operands of these node are:
64 /// #0 - The incoming token chain
66 /// #2 - The number of arg bytes the caller pushes on the stack.
67 /// #3 - The number of arg bytes the callee pops off the stack.
68 /// #4 - The value to pass in AL/AX/EAX (optional)
69 /// #5 - The value to pass in DL/DX/EDX (optional)
71 /// The result values of these nodes are:
73 /// #0 - The outgoing token chain
74 /// #1 - The first register result value (optional)
75 /// #2 - The second register result value (optional)
79 /// RDTSC_DAG - This operation implements the lowering for
83 /// X86 compare and logical compare instructions.
86 /// X86 bit-test instructions.
89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
90 /// operand, usually produced by a CMP instruction.
93 // Same as SETCC except it's materialized with a sbb and the value is all
94 // one's or all zero's.
95 SETCC_CARRY, // R = carry_bit ? ~0 : 0
97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
98 /// Operands are two FP values to compare; result is a mask of
99 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
102 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
103 /// result in an integer GPR. Needs masking for scalar result.
106 /// X86 conditional moves. Operand 0 and operand 1 are the two values
107 /// to select from. Operand 2 is the condition code, and operand 3 is the
108 /// flag operand produced by a CMP or TEST instruction. It also writes a
112 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
113 /// is the block to branch if condition is true, operand 2 is the
114 /// condition code, and operand 3 is the flag operand produced by a CMP
115 /// or TEST instruction.
118 /// Return with a flag operand. Operand 0 is the chain operand, operand
119 /// 1 is the number of bytes of stack to pop.
122 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
125 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
128 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
129 /// at function entry, used for PIC code.
132 /// Wrapper - A wrapper node for TargetConstantPool,
133 /// TargetExternalSymbol, and TargetGlobalAddress.
136 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
137 /// relative displacements.
140 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
141 /// to an MMX vector. If you think this is too close to the previous
142 /// mnemonic, so do I; blame Intel.
145 /// MMX_MOVD2W - Copies a 32-bit value from the low word of a MMX
149 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
150 /// i32, corresponds to X86::PEXTRB.
153 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
154 /// i32, corresponds to X86::PEXTRW.
157 /// INSERTPS - Insert any element of a 4 x float vector into any element
158 /// of a destination 4 x floatvector.
161 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
162 /// corresponds to X86::PINSRB.
165 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
166 /// corresponds to X86::PINSRW.
169 /// PSHUFB - Shuffle 16 8-bit values within a vector.
172 /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
175 /// PSIGN - Copy integer sign.
178 /// BLENDV - Blend where the selector is a register.
181 /// BLENDI - Blend where the selector is an immediate.
184 // SUBUS - Integer sub with unsigned saturation.
187 /// HADD - Integer horizontal add.
190 /// HSUB - Integer horizontal sub.
193 /// FHADD - Floating point horizontal add.
196 /// FHSUB - Floating point horizontal sub.
199 /// UMAX, UMIN - Unsigned integer max and min.
202 /// SMAX, SMIN - Signed integer max and min.
205 /// FMAX, FMIN - Floating point max and min.
209 /// FMAXC, FMINC - Commutative FMIN and FMAX.
212 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
213 /// approximation. Note that these typically require refinement
214 /// in order to obtain suitable precision.
217 // TLSADDR - Thread Local Storage.
220 // TLSBASEADDR - Thread Local Storage. A call to get the start address
221 // of the TLS block for the current module.
224 // TLSCALL - Thread Local Storage. When calling to an OS provided
225 // thunk at the address from an earlier relocation.
228 // EH_RETURN - Exception Handling helpers.
231 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
234 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
237 /// TC_RETURN - Tail call return.
239 /// operand #1 callee (register or absolute)
240 /// operand #2 stack adjustment
241 /// operand #3 optional in flag
244 // VZEXT_MOVL - Vector move low and zero extend.
247 // VSEXT_MOVL - Vector move low and sign extend.
250 // VZEXT - Vector integer zero-extend.
253 // VSEXT - Vector integer signed-extend.
256 // VFPEXT - Vector FP extend.
259 // VFPROUND - Vector FP round.
262 // VSHL, VSRL - 128-bit vector logical left / right shift
265 // VSHL, VSRL, VSRA - Vector shift elements
268 // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate
271 // CMPP - Vector packed double/float comparison.
274 // PCMP* - Vector integer comparisons.
277 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
278 ADD, SUB, ADC, SBB, SMUL,
279 INC, DEC, OR, XOR, AND,
281 BLSI, // BLSI - Extract lowest set isolated bit
282 BLSMSK, // BLSMSK - Get mask up to lowest set bit
283 BLSR, // BLSR - Reset lowest set bit
285 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
287 // MUL_IMM - X86 specific multiply by immediate.
290 // PTEST - Vector bitwise comparisons
293 // TESTP - Vector packed fp sign bitwise comparisons
296 // Several flavors of instructions with vector shuffle behaviors.
320 // PMULUDQ - Vector multiply packed unsigned doubleword integers
331 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
332 // according to %al. An operator is needed so that this can be expanded
333 // with control flow.
334 VASTART_SAVE_XMM_REGS,
336 // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
339 // SEG_ALLOCA - For allocating variable amounts of stack space when using
340 // segmented stacks. Check if the current stacklet has enough space, and
341 // falls back to heap allocation if not.
344 // WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui.
353 // FNSTSW16r - Store FP status word into i16 register.
356 // SAHF - Store contents of %ah into %eflags.
359 // RDRAND - Get a random integer and indicate whether it is valid in CF.
366 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
367 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
368 // Atomic 64-bit binary operations.
369 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
381 // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
386 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
389 // FNSTCW16m - Store FP control world into i16 memory.
392 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
393 /// integer destination in memory and a FP reg source. This corresponds
394 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
395 /// has two inputs (token chain and address) and two outputs (int value
396 /// and token chain).
401 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
402 /// integer source in memory and FP reg result. This corresponds to the
403 /// X86::FILD*m instructions. It has three inputs (token chain, address,
404 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
405 /// also produces a flag).
409 /// FLD - This instruction implements an extending load to FP stack slots.
410 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
411 /// operand, ptr to load from, and a ValueType node indicating the type
415 /// FST - This instruction implements a truncating store to FP stack
416 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
417 /// chain operand, value to store, address, and a ValueType to store it
421 /// VAARG_64 - This instruction grabs the address of the next argument
422 /// from a va_list. (reads and modifies the va_list in memory)
425 // WARNING: Do not add anything in the end unless you want the node to
426 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
427 // thought as target memory ops!
431 /// Define some predicates that are used for node matching.
433 /// isVEXTRACTF128Index - Return true if the specified
434 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
435 /// suitable for input to VEXTRACTF128.
436 bool isVEXTRACTF128Index(SDNode *N);
438 /// isVINSERTF128Index - Return true if the specified
439 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
440 /// suitable for input to VINSERTF128.
441 bool isVINSERTF128Index(SDNode *N);
443 /// getExtractVEXTRACTF128Immediate - Return the appropriate
444 /// immediate to extract the specified EXTRACT_SUBVECTOR index
445 /// with VEXTRACTF128 instructions.
446 unsigned getExtractVEXTRACTF128Immediate(SDNode *N);
448 /// getInsertVINSERTF128Immediate - Return the appropriate
449 /// immediate to insert at the specified INSERT_SUBVECTOR index
450 /// with VINSERTF128 instructions.
451 unsigned getInsertVINSERTF128Immediate(SDNode *N);
453 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
455 bool isZeroNode(SDValue Elt);
457 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
458 /// fit into displacement field of the instruction.
459 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
460 bool hasSymbolicDisplacement = true);
463 /// isCalleePop - Determines whether the callee is required to pop its
464 /// own arguments. Callee pop is necessary to support tail calls.
465 bool isCalleePop(CallingConv::ID CallingConv,
466 bool is64Bit, bool IsVarArg, bool TailCallOpt);
469 //===--------------------------------------------------------------------===//
470 // X86TargetLowering - X86 Implementation of the TargetLowering interface
471 class X86TargetLowering : public TargetLowering {
473 explicit X86TargetLowering(X86TargetMachine &TM);
475 virtual unsigned getJumpTableEncoding() const;
477 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
479 virtual const MCExpr *
480 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
481 const MachineBasicBlock *MBB, unsigned uid,
482 MCContext &Ctx) const;
484 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
486 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
487 SelectionDAG &DAG) const;
488 virtual const MCExpr *
489 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
490 unsigned JTI, MCContext &Ctx) const;
492 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
493 /// function arguments in the caller parameter area. For X86, aggregates
494 /// that contains are placed at 16-byte boundaries while the rest are at
495 /// 4-byte boundaries.
496 virtual unsigned getByValTypeAlignment(Type *Ty) const;
498 /// getOptimalMemOpType - Returns the target specific optimal type for load
499 /// and store operations as a result of memset, memcpy, and memmove
500 /// lowering. If DstAlign is zero that means it's safe to destination
501 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
502 /// means there isn't a need to check it against alignment requirement,
503 /// probably because the source does not need to be loaded. If 'IsMemset' is
504 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
505 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
506 /// source is constant so it does not need to be loaded.
507 /// It returns EVT::Other if the type should be determined using generic
508 /// target-independent logic.
510 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
511 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
512 MachineFunction &MF) const;
514 /// isSafeMemOpType - Returns true if it's safe to use load / store of the
515 /// specified type to expand memcpy / memset inline. This is mostly true
516 /// for all types except for some special cases. For example, on X86
517 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
518 /// also does type conversion. Note the specified type doesn't have to be
519 /// legal as the hook is used before type legalization.
520 virtual bool isSafeMemOpType(MVT VT) const;
522 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
523 /// unaligned memory accesses. of the specified type. Returns whether it
524 /// is "fast" by reference in the second argument.
525 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
527 /// LowerOperation - Provide custom lowering hooks for some operations.
529 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
531 /// ReplaceNodeResults - Replace the results of node with an illegal result
532 /// type with new values built out of custom code.
534 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
535 SelectionDAG &DAG) const;
538 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
540 /// isTypeDesirableForOp - Return true if the target has native support for
541 /// the specified value type and it is 'desirable' to use the type for the
542 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
543 /// instruction encodings are longer and some i16 instructions are slow.
544 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
546 /// isTypeDesirable - Return true if the target has native support for the
547 /// specified value type and it is 'desirable' to use the type. e.g. On x86
548 /// i16 is legal, but undesirable since i16 instruction encodings are longer
549 /// and some i16 instructions are slow.
550 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
552 virtual MachineBasicBlock *
553 EmitInstrWithCustomInserter(MachineInstr *MI,
554 MachineBasicBlock *MBB) const;
557 /// getTargetNodeName - This method returns the name of a target specific
559 virtual const char *getTargetNodeName(unsigned Opcode) const;
561 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
562 virtual EVT getSetCCResultType(EVT VT) const;
564 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
565 /// in Mask are known to be either zero or one and return them in the
566 /// KnownZero/KnownOne bitsets.
567 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
570 const SelectionDAG &DAG,
571 unsigned Depth = 0) const;
573 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
574 // operation that are sign bits.
575 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
576 unsigned Depth) const;
579 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
581 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
583 virtual bool ExpandInlineAsm(CallInst *CI) const;
585 ConstraintType getConstraintType(const std::string &Constraint) const;
587 /// Examine constraint string and operand type and determine a weight value.
588 /// The operand object must already have been set up with the operand type.
589 virtual ConstraintWeight getSingleConstraintMatchWeight(
590 AsmOperandInfo &info, const char *constraint) const;
592 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
594 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
595 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
596 /// true it means one of the asm constraint of the inline asm instruction
597 /// being processed is 'm'.
598 virtual void LowerAsmOperandForConstraint(SDValue Op,
599 std::string &Constraint,
600 std::vector<SDValue> &Ops,
601 SelectionDAG &DAG) const;
603 /// getRegForInlineAsmConstraint - Given a physical register constraint
604 /// (e.g. {edx}), return the register number and the register class for the
605 /// register. This should only be used for C_Register constraints. On
606 /// error, this returns a register number of 0.
607 std::pair<unsigned, const TargetRegisterClass*>
608 getRegForInlineAsmConstraint(const std::string &Constraint,
611 /// isLegalAddressingMode - Return true if the addressing mode represented
612 /// by AM is legal for this target, for a load/store of the specified type.
613 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
615 /// isLegalICmpImmediate - Return true if the specified immediate is legal
616 /// icmp immediate, that is the target has icmp instructions which can
617 /// compare a register against the immediate without having to materialize
618 /// the immediate into a register.
619 virtual bool isLegalICmpImmediate(int64_t Imm) const;
621 /// isLegalAddImmediate - Return true if the specified immediate is legal
622 /// add immediate, that is the target has add instructions which can
623 /// add a register and the immediate without having to materialize
624 /// the immediate into a register.
625 virtual bool isLegalAddImmediate(int64_t Imm) const;
627 /// isTruncateFree - Return true if it's free to truncate a value of
628 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
629 /// register EAX to i16 by referencing its sub-register AX.
630 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
631 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
633 /// isZExtFree - Return true if any actual instruction that defines a
634 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
635 /// register. This does not necessarily include registers defined in
636 /// unknown ways, such as incoming arguments, or copies from unknown
637 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
638 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
639 /// all instructions that define 32-bit values implicit zero-extend the
640 /// result out to 64 bits.
641 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
642 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
643 virtual bool isZExtFree(SDValue Val, EVT VT2) const;
645 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
646 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
647 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
648 /// is expanded to mul + add.
649 virtual bool isFMAFasterThanMulAndAdd(EVT) const { return true; }
651 /// isNarrowingProfitable - Return true if it's profitable to narrow
652 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
653 /// from i32 to i8 but not from i32 to i16.
654 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
656 /// isFPImmLegal - Returns true if the target can instruction select the
657 /// specified FP immediate natively. If false, the legalizer will
658 /// materialize the FP immediate as a load from a constant pool.
659 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
661 /// isShuffleMaskLegal - Targets can use this to indicate that they only
662 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
663 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
664 /// values are assumed to be legal.
665 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
668 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
669 /// used by Targets can use this to indicate if there is a suitable
670 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
672 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
675 /// ShouldShrinkFPConstant - If true, then instruction selection should
676 /// seek to shrink the FP constant of the specified type to a smaller type
677 /// in order to save space and / or reduce runtime.
678 virtual bool ShouldShrinkFPConstant(EVT VT) const {
679 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
680 // expensive than a straight movsd. On the other hand, it's important to
681 // shrink long double fp constant since fldt is very slow.
682 return !X86ScalarSSEf64 || VT == MVT::f80;
685 const X86Subtarget* getSubtarget() const {
689 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
690 /// computed in an SSE register, not on the X87 floating point stack.
691 bool isScalarFPTypeInSSEReg(EVT VT) const {
692 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
693 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
696 /// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine
698 bool isTargetFTOL() const {
699 return Subtarget->isTargetWindows() && !Subtarget->is64Bit();
702 /// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be
703 /// used for fptoui to the given type.
704 bool isIntegerTypeFTOL(EVT VT) const {
705 return isTargetFTOL() && VT == MVT::i64;
708 /// createFastISel - This method returns a target specific FastISel object,
709 /// or null if the target does not support "fast" ISel.
710 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
711 const TargetLibraryInfo *libInfo) const;
713 /// getStackCookieLocation - Return true if the target stores stack
714 /// protector cookies at a fixed offset in some non-standard address
715 /// space, and populates the address space and offset as
717 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
719 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
720 SelectionDAG &DAG) const;
723 std::pair<const TargetRegisterClass*, uint8_t>
724 findRepresentativeClass(MVT VT) const;
727 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
728 /// make the right decision when generating code for different targets.
729 const X86Subtarget *Subtarget;
730 const X86RegisterInfo *RegInfo;
731 const DataLayout *TD;
733 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
734 /// floating point ops.
735 /// When SSE is available, use it for f32 operations.
736 /// When SSE2 is available, use it for f64 operations.
737 bool X86ScalarSSEf32;
738 bool X86ScalarSSEf64;
740 /// LegalFPImmediates - A list of legal fp immediates.
741 std::vector<APFloat> LegalFPImmediates;
743 /// addLegalFPImmediate - Indicate that this x86 target can instruction
744 /// select the specified FP immediate natively.
745 void addLegalFPImmediate(const APFloat& Imm) {
746 LegalFPImmediates.push_back(Imm);
749 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
750 CallingConv::ID CallConv, bool isVarArg,
751 const SmallVectorImpl<ISD::InputArg> &Ins,
752 DebugLoc dl, SelectionDAG &DAG,
753 SmallVectorImpl<SDValue> &InVals) const;
754 SDValue LowerMemArgument(SDValue Chain,
755 CallingConv::ID CallConv,
756 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
757 DebugLoc dl, SelectionDAG &DAG,
758 const CCValAssign &VA, MachineFrameInfo *MFI,
760 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
761 DebugLoc dl, SelectionDAG &DAG,
762 const CCValAssign &VA,
763 ISD::ArgFlagsTy Flags) const;
765 // Call lowering helpers.
767 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
768 /// for tail call optimization. Targets which want to do tail call
769 /// optimization should implement this function.
770 bool IsEligibleForTailCallOptimization(SDValue Callee,
771 CallingConv::ID CalleeCC,
773 bool isCalleeStructRet,
774 bool isCallerStructRet,
776 const SmallVectorImpl<ISD::OutputArg> &Outs,
777 const SmallVectorImpl<SDValue> &OutVals,
778 const SmallVectorImpl<ISD::InputArg> &Ins,
779 SelectionDAG& DAG) const;
780 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
781 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
782 SDValue Chain, bool IsTailCall, bool Is64Bit,
783 int FPDiff, DebugLoc dl) const;
785 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
786 SelectionDAG &DAG) const;
788 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
790 bool isReplace) const;
792 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
793 SelectionDAG &DAG) const;
794 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
795 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
796 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
797 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
798 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
799 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
800 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
801 int64_t Offset, SelectionDAG &DAG) const;
802 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
803 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
804 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
805 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
806 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const;
807 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
808 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
809 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
810 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
811 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
812 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
813 SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
814 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
815 SDValue LowerANY_EXTEND(SDValue Op, SelectionDAG &DAG) const;
816 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
817 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
818 SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
819 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
820 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
821 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
822 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
823 DebugLoc dl, SelectionDAG &DAG) const;
824 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
825 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
826 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
827 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
828 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
829 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
830 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
831 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
832 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
833 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
834 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
835 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
836 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
837 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
838 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
839 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
840 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
841 SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
843 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
845 // Utility functions to help LowerVECTOR_SHUFFLE & LowerBUILD_VECTOR
846 SDValue LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const;
847 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const;
848 SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const;
850 SDValue LowerVectorAllZeroTest(SDValue Op, SelectionDAG &DAG) const;
852 SDValue LowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const;
855 LowerFormalArguments(SDValue Chain,
856 CallingConv::ID CallConv, bool isVarArg,
857 const SmallVectorImpl<ISD::InputArg> &Ins,
858 DebugLoc dl, SelectionDAG &DAG,
859 SmallVectorImpl<SDValue> &InVals) const;
861 LowerCall(CallLoweringInfo &CLI,
862 SmallVectorImpl<SDValue> &InVals) const;
865 LowerReturn(SDValue Chain,
866 CallingConv::ID CallConv, bool isVarArg,
867 const SmallVectorImpl<ISD::OutputArg> &Outs,
868 const SmallVectorImpl<SDValue> &OutVals,
869 DebugLoc dl, SelectionDAG &DAG) const;
871 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
873 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
876 getTypeForExtArgOrReturn(MVT VT, ISD::NodeType ExtendKind) const;
879 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
881 const SmallVectorImpl<ISD::OutputArg> &Outs,
882 LLVMContext &Context) const;
884 /// Utility function to emit atomic-load-arith operations (and, or, xor,
885 /// nand, max, min, umax, umin). It takes the corresponding instruction to
886 /// expand, the associated machine basic block, and the associated X86
887 /// opcodes for reg/reg.
888 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
889 MachineBasicBlock *MBB) const;
891 /// Utility function to emit atomic-load-arith operations (and, or, xor,
892 /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
893 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
894 MachineBasicBlock *MBB) const;
896 // Utility function to emit the low-level va_arg code for X86-64.
897 MachineBasicBlock *EmitVAARG64WithCustomInserter(
899 MachineBasicBlock *MBB) const;
901 /// Utility function to emit the xmm reg save portion of va_start.
902 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
903 MachineInstr *BInstr,
904 MachineBasicBlock *BB) const;
906 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
907 MachineBasicBlock *BB) const;
909 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
910 MachineBasicBlock *BB) const;
912 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
913 MachineBasicBlock *BB,
916 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
917 MachineBasicBlock *BB) const;
919 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
920 MachineBasicBlock *BB) const;
922 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
923 MachineBasicBlock *MBB) const;
925 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
926 MachineBasicBlock *MBB) const;
928 /// Emit nodes that will be selected as "test Op0,Op0", or something
929 /// equivalent, for use with the given x86 condition code.
930 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
932 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
933 /// equivalent, for use with the given x86 condition code.
934 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
935 SelectionDAG &DAG) const;
937 /// Convert a comparison if required by the subtarget.
938 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
942 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
943 const TargetLibraryInfo *libInfo);
947 #endif // X86ISELLOWERING_H