1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetOptions.h"
25 class X86TargetMachine;
28 // X86 Specific DAG Nodes
29 enum NodeType : unsigned {
30 // Start the numbering where the builtin ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
38 /// Double shift instructions. These correspond to
39 /// X86::SHLDxx and X86::SHRDxx instructions.
43 /// Bitwise logical AND of floating point values. This corresponds
44 /// to X86::ANDPS or X86::ANDPD.
47 /// Bitwise logical OR of floating point values. This corresponds
48 /// to X86::ORPS or X86::ORPD.
51 /// Bitwise logical XOR of floating point values. This corresponds
52 /// to X86::XORPS or X86::XORPD.
55 /// Bitwise logical ANDNOT of floating point values. This
56 /// corresponds to X86::ANDNPS or X86::ANDNPD.
59 /// These operations represent an abstract X86 call
60 /// instruction, which includes a bunch of information. In particular the
61 /// operands of these node are:
63 /// #0 - The incoming token chain
65 /// #2 - The number of arg bytes the caller pushes on the stack.
66 /// #3 - The number of arg bytes the callee pops off the stack.
67 /// #4 - The value to pass in AL/AX/EAX (optional)
68 /// #5 - The value to pass in DL/DX/EDX (optional)
70 /// The result values of these nodes are:
72 /// #0 - The outgoing token chain
73 /// #1 - The first register result value (optional)
74 /// #2 - The second register result value (optional)
78 /// This operation implements the lowering for readcyclecounter
81 /// X86 Read Time-Stamp Counter and Processor ID.
84 /// X86 Read Performance Monitoring Counters.
87 /// X86 compare and logical compare instructions.
90 /// X86 bit-test instructions.
93 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
94 /// operand, usually produced by a CMP instruction.
100 // Same as SETCC except it's materialized with a sbb and the value is all
101 // one's or all zero's.
102 SETCC_CARRY, // R = carry_bit ? ~0 : 0
104 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
105 /// Operands are two FP values to compare; result is a mask of
106 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
109 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
110 /// result in an integer GPR. Needs masking for scalar result.
113 /// X86 conditional moves. Operand 0 and operand 1 are the two values
114 /// to select from. Operand 2 is the condition code, and operand 3 is the
115 /// flag operand produced by a CMP or TEST instruction. It also writes a
119 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
120 /// is the block to branch if condition is true, operand 2 is the
121 /// condition code, and operand 3 is the flag operand produced by a CMP
122 /// or TEST instruction.
125 /// Return with a flag operand. Operand 0 is the chain operand, operand
126 /// 1 is the number of bytes of stack to pop.
129 /// Repeat fill, corresponds to X86::REP_STOSx.
132 /// Repeat move, corresponds to X86::REP_MOVSx.
135 /// On Darwin, this node represents the result of the popl
136 /// at function entry, used for PIC code.
139 /// A wrapper node for TargetConstantPool,
140 /// TargetExternalSymbol, and TargetGlobalAddress.
143 /// Special wrapper used under X86-64 PIC mode for RIP
144 /// relative displacements.
147 /// Copies a 64-bit value from the low word of an XMM vector
148 /// to an MMX vector. If you think this is too close to the previous
149 /// mnemonic, so do I; blame Intel.
152 /// Copies a 32-bit value from the low word of a MMX
156 /// Copies a GPR into the low 32-bit word of a MMX vector
157 /// and zero out the high word.
160 /// Extract an 8-bit value from a vector and zero extend it to
161 /// i32, corresponds to X86::PEXTRB.
164 /// Extract a 16-bit value from a vector and zero extend it to
165 /// i32, corresponds to X86::PEXTRW.
168 /// Insert any element of a 4 x float vector into any element
169 /// of a destination 4 x floatvector.
172 /// Insert the lower 8-bits of a 32-bit value to a vector,
173 /// corresponds to X86::PINSRB.
176 /// Insert the lower 16-bits of a 32-bit value to a vector,
177 /// corresponds to X86::PINSRW.
180 /// Shuffle 16 8-bit values within a vector.
183 /// Compute Sum of Absolute Differences.
186 /// Bitwise Logical AND NOT of Packed FP values.
189 /// Copy integer sign.
192 /// Blend where the selector is an immediate.
195 /// Blend where the condition has been shrunk.
196 /// This is used to emphasize that the condition mask is
197 /// no more valid for generic VSELECT optimizations.
200 /// Combined add and sub on an FP vector.
203 // FP vector ops with rounding mode.
212 // FP vector get exponent
216 // Integer add/sub with unsigned saturation.
219 // Integer add/sub with signed saturation.
222 // Unsigned Integer average
224 /// Integer horizontal add.
227 /// Integer horizontal sub.
230 /// Floating point horizontal add.
233 /// Floating point horizontal sub.
236 // Integer absolute value
239 /// Floating point max and min.
242 /// Commutative FMIN and FMAX.
245 /// Floating point reciprocal-sqrt and reciprocal approximation.
246 /// Note that these typically require refinement
247 /// in order to obtain suitable precision.
250 // Thread Local Storage.
253 // Thread Local Storage. A call to get the start address
254 // of the TLS block for the current module.
257 // Thread Local Storage. When calling to an OS provided
258 // thunk at the address from an earlier relocation.
261 // Exception Handling helpers.
266 // SjLj exception handling setjmp.
269 // SjLj exception handling longjmp.
272 /// Tail call return. See X86TargetLowering::LowerCall for
273 /// the list of operands.
276 // Vector move to low scalar and zero higher vector elements.
279 // Vector integer zero-extend.
282 // Vector integer signed-extend.
285 // Vector integer truncate.
287 // Vector integer truncate with unsigned/signed saturation.
296 // Vector signed/unsigned integer to double.
299 // 128-bit vector logical left / right shift
302 // Vector shift elements
305 // Vector shift elements by immediate
308 // Vector packed double/float comparison.
311 // Vector integer comparisons.
313 // Vector integer comparisons, the result is in a mask vector.
316 /// Vector comparison generating mask bits for fp and
317 /// integer signed and unsigned data types.
320 // Vector comparison with rounding mode for FP values
323 // Arithmetic operations with FLAGS results.
324 ADD, SUB, ADC, SBB, SMUL,
325 INC, DEC, OR, XOR, AND,
327 BEXTR, // Bit field extract
329 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
331 // 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS
334 // 8-bit divrem that zero-extend the high result (AH).
338 // X86-specific multiply by immediate.
341 // Vector bitwise comparisons.
344 // Vector packed fp sign bitwise comparisons.
347 // Vector "test" in AVX-512, the result is in a mask vector.
351 // OR/AND test for masks
354 // Several flavors of instructions with vector shuffle behaviors.
359 // AVX512 inter-lane alignr
365 //Shuffle Packed Values at 128-bit granularity
386 //Fix Up Special Packed Float32/64 values
388 //Range Restriction Calculation For Packed Pairs of Float32/64 values
390 // Reduce - Perform Reduction Transformation on scalar\packed FP
392 // RndScale - Round FP Values To Include A Given Number Of Fraction Bits
394 // Broadcast scalar to vector
396 // Broadcast subvector to vector
398 // Insert/Extract vector element
402 /// SSE4A Extraction and Insertion.
405 // Vector multiply packed unsigned doubleword integers
407 // Vector multiply packed signed doubleword integers
409 // Vector Multiply Packed UnsignedIntegers with Round and Scale
411 // Multiply and Add Packed Integers
412 VPMADDUBSW, VPMADDWD,
420 // FMA with rounding mode
428 // Compress and expand
432 //Convert Unsigned/Integer to Scalar Floating-Point Value
437 // Vector float/double to signed/unsigned integer.
438 FP_TO_SINT_RND, FP_TO_UINT_RND,
439 // Save xmm argument registers to the stack, according to %al. An operator
440 // is needed so that this can be expanded with control flow.
441 VASTART_SAVE_XMM_REGS,
443 // Windows's _chkstk call to do stack probing.
446 // For allocating variable amounts of stack space when using
447 // segmented stacks. Check if the current stacklet has enough space, and
448 // falls back to heap allocation if not.
457 // Store FP status word into i16 register.
460 // Store contents of %ah into %eflags.
463 // Get a random integer and indicate whether it is valid in CF.
466 // Get a NIST SP800-90B & C compliant random integer and
467 // indicate whether it is valid in CF.
473 // Test if in transactional execution.
477 RSQRT28, RCP28, EXP2,
480 LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
484 // Load, scalar_to_vector, and zero extend.
487 // Store FP control world into i16 memory.
490 /// This instruction implements FP_TO_SINT with the
491 /// integer destination in memory and a FP reg source. This corresponds
492 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
493 /// has two inputs (token chain and address) and two outputs (int value
494 /// and token chain).
499 /// This instruction implements SINT_TO_FP with the
500 /// integer source in memory and FP reg result. This corresponds to the
501 /// X86::FILD*m instructions. It has three inputs (token chain, address,
502 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
503 /// also produces a flag).
507 /// This instruction implements an extending load to FP stack slots.
508 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
509 /// operand, ptr to load from, and a ValueType node indicating the type
513 /// This instruction implements a truncating store to FP stack
514 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
515 /// chain operand, value to store, address, and a ValueType to store it
519 /// This instruction grabs the address of the next argument
520 /// from a va_list. (reads and modifies the va_list in memory)
523 // WARNING: Do not add anything in the end unless you want the node to
524 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
525 // thought as target memory ops!
529 /// Define some predicates that are used for node matching.
531 /// Return true if the specified
532 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
533 /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
534 bool isVEXTRACT128Index(SDNode *N);
536 /// Return true if the specified
537 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
538 /// suitable for input to VINSERTF128, VINSERTI128 instructions.
539 bool isVINSERT128Index(SDNode *N);
541 /// Return true if the specified
542 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
543 /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
544 bool isVEXTRACT256Index(SDNode *N);
546 /// Return true if the specified
547 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
548 /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
549 bool isVINSERT256Index(SDNode *N);
551 /// Return the appropriate
552 /// immediate to extract the specified EXTRACT_SUBVECTOR index
553 /// with VEXTRACTF128, VEXTRACTI128 instructions.
554 unsigned getExtractVEXTRACT128Immediate(SDNode *N);
556 /// Return the appropriate
557 /// immediate to insert at the specified INSERT_SUBVECTOR index
558 /// with VINSERTF128, VINSERT128 instructions.
559 unsigned getInsertVINSERT128Immediate(SDNode *N);
561 /// Return the appropriate
562 /// immediate to extract the specified EXTRACT_SUBVECTOR index
563 /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
564 unsigned getExtractVEXTRACT256Immediate(SDNode *N);
566 /// Return the appropriate
567 /// immediate to insert at the specified INSERT_SUBVECTOR index
568 /// with VINSERTF64x4, VINSERTI64x4 instructions.
569 unsigned getInsertVINSERT256Immediate(SDNode *N);
571 /// Returns true if Elt is a constant zero or floating point constant +0.0.
572 bool isZeroNode(SDValue Elt);
574 /// Returns true of the given offset can be
575 /// fit into displacement field of the instruction.
576 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
577 bool hasSymbolicDisplacement = true);
580 /// Determines whether the callee is required to pop its
581 /// own arguments. Callee pop is necessary to support tail calls.
582 bool isCalleePop(CallingConv::ID CallingConv,
583 bool is64Bit, bool IsVarArg, bool TailCallOpt);
585 /// AVX512 static rounding constants. These need to match the values in
587 enum STATIC_ROUNDING {
596 //===--------------------------------------------------------------------===//
597 // X86 Implementation of the TargetLowering interface
598 class X86TargetLowering final : public TargetLowering {
600 explicit X86TargetLowering(const X86TargetMachine &TM,
601 const X86Subtarget &STI);
603 unsigned getJumpTableEncoding() const override;
604 bool useSoftFloat() const override;
606 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
611 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
612 const MachineBasicBlock *MBB, unsigned uid,
613 MCContext &Ctx) const override;
615 /// Returns relocation base for the given PIC jumptable.
616 SDValue getPICJumpTableRelocBase(SDValue Table,
617 SelectionDAG &DAG) const override;
619 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
620 unsigned JTI, MCContext &Ctx) const override;
622 /// Return the desired alignment for ByVal aggregate
623 /// function arguments in the caller parameter area. For X86, aggregates
624 /// that contains are placed at 16-byte boundaries while the rest are at
625 /// 4-byte boundaries.
626 unsigned getByValTypeAlignment(Type *Ty,
627 const DataLayout &DL) const override;
629 /// Returns the target specific optimal type for load
630 /// and store operations as a result of memset, memcpy, and memmove
631 /// lowering. If DstAlign is zero that means it's safe to destination
632 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
633 /// means there isn't a need to check it against alignment requirement,
634 /// probably because the source does not need to be loaded. If 'IsMemset' is
635 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
636 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
637 /// source is constant so it does not need to be loaded.
638 /// It returns EVT::Other if the type should be determined using generic
639 /// target-independent logic.
640 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
641 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
642 MachineFunction &MF) const override;
644 /// Returns true if it's safe to use load / store of the
645 /// specified type to expand memcpy / memset inline. This is mostly true
646 /// for all types except for some special cases. For example, on X86
647 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
648 /// also does type conversion. Note the specified type doesn't have to be
649 /// legal as the hook is used before type legalization.
650 bool isSafeMemOpType(MVT VT) const override;
652 /// Returns true if the target allows unaligned memory accesses of the
653 /// specified type. Returns whether it is "fast" in the last argument.
654 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
655 bool *Fast) const override;
657 /// Provide custom lowering hooks for some operations.
659 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
661 /// Replace the results of node with an illegal result
662 /// type with new values built out of custom code.
664 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
665 SelectionDAG &DAG) const override;
668 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
670 /// Return true if the target has native support for
671 /// the specified value type and it is 'desirable' to use the type for the
672 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
673 /// instruction encodings are longer and some i16 instructions are slow.
674 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
676 /// Return true if the target has native support for the
677 /// specified value type and it is 'desirable' to use the type. e.g. On x86
678 /// i16 is legal, but undesirable since i16 instruction encodings are longer
679 /// and some i16 instructions are slow.
680 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
683 EmitInstrWithCustomInserter(MachineInstr *MI,
684 MachineBasicBlock *MBB) const override;
687 /// This method returns the name of a target specific DAG node.
688 const char *getTargetNodeName(unsigned Opcode) const override;
690 bool isCheapToSpeculateCttz() const override;
692 bool isCheapToSpeculateCtlz() const override;
694 /// Return the value type to use for ISD::SETCC.
695 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
696 EVT VT) const override;
698 /// Determine which of the bits specified in Mask are known to be either
699 /// zero or one and return them in the KnownZero/KnownOne bitsets.
700 void computeKnownBitsForTargetNode(const SDValue Op,
703 const SelectionDAG &DAG,
704 unsigned Depth = 0) const override;
706 /// Determine the number of bits in the operation that are sign bits.
707 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
708 const SelectionDAG &DAG,
709 unsigned Depth) const override;
711 bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
712 int64_t &Offset) const override;
714 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
716 bool ExpandInlineAsm(CallInst *CI) const override;
718 ConstraintType getConstraintType(StringRef Constraint) const override;
720 /// Examine constraint string and operand type and determine a weight value.
721 /// The operand object must already have been set up with the operand type.
723 getSingleConstraintMatchWeight(AsmOperandInfo &info,
724 const char *constraint) const override;
726 const char *LowerXConstraint(EVT ConstraintVT) const override;
728 /// Lower the specified operand into the Ops vector. If it is invalid, don't
729 /// add anything to Ops. If hasMemory is true it means one of the asm
730 /// constraint of the inline asm instruction being processed is 'm'.
731 void LowerAsmOperandForConstraint(SDValue Op,
732 std::string &Constraint,
733 std::vector<SDValue> &Ops,
734 SelectionDAG &DAG) const override;
737 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
738 if (ConstraintCode == "i")
739 return InlineAsm::Constraint_i;
740 else if (ConstraintCode == "o")
741 return InlineAsm::Constraint_o;
742 else if (ConstraintCode == "v")
743 return InlineAsm::Constraint_v;
744 else if (ConstraintCode == "X")
745 return InlineAsm::Constraint_X;
746 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
749 /// Given a physical register constraint
750 /// (e.g. {edx}), return the register number and the register class for the
751 /// register. This should only be used for C_Register constraints. On
752 /// error, this returns a register number of 0.
753 std::pair<unsigned, const TargetRegisterClass *>
754 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
755 StringRef Constraint, MVT VT) const override;
757 /// Return true if the addressing mode represented
758 /// by AM is legal for this target, for a load/store of the specified type.
759 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
760 Type *Ty, unsigned AS) const override;
762 /// Return true if the specified immediate is legal
763 /// icmp immediate, that is the target has icmp instructions which can
764 /// compare a register against the immediate without having to materialize
765 /// the immediate into a register.
766 bool isLegalICmpImmediate(int64_t Imm) const override;
768 /// Return true if the specified immediate is legal
769 /// add immediate, that is the target has add instructions which can
770 /// add a register and the immediate without having to materialize
771 /// the immediate into a register.
772 bool isLegalAddImmediate(int64_t Imm) const override;
774 /// \brief Return the cost of the scaling factor used in the addressing
775 /// mode represented by AM for this target, for a load/store
776 /// of the specified type.
777 /// If the AM is supported, the return value must be >= 0.
778 /// If the AM is not supported, it returns a negative value.
779 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
780 unsigned AS) const override;
782 bool isVectorShiftByScalarCheap(Type *Ty) const override;
784 /// Return true if it's free to truncate a value of
785 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
786 /// register EAX to i16 by referencing its sub-register AX.
787 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
788 bool isTruncateFree(EVT VT1, EVT VT2) const override;
790 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
792 /// Return true if any actual instruction that defines a
793 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
794 /// register. This does not necessarily include registers defined in
795 /// unknown ways, such as incoming arguments, or copies from unknown
796 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
797 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
798 /// all instructions that define 32-bit values implicit zero-extend the
799 /// result out to 64 bits.
800 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
801 bool isZExtFree(EVT VT1, EVT VT2) const override;
802 bool isZExtFree(SDValue Val, EVT VT2) const override;
804 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
805 /// extend node) is profitable.
806 bool isVectorLoadExtDesirable(SDValue) const override;
808 /// Return true if an FMA operation is faster than a pair of fmul and fadd
809 /// instructions. fmuladd intrinsics will be expanded to FMAs when this
810 /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
811 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
813 /// Return true if it's profitable to narrow
814 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
815 /// from i32 to i8 but not from i32 to i16.
816 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
818 /// Returns true if the target can instruction select the
819 /// specified FP immediate natively. If false, the legalizer will
820 /// materialize the FP immediate as a load from a constant pool.
821 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
823 /// Targets can use this to indicate that they only support *some*
824 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
825 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
827 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
828 EVT VT) const override;
830 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
831 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to
832 /// replace a VAND with a constant pool entry.
833 bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
834 EVT VT) const override;
836 /// If true, then instruction selection should
837 /// seek to shrink the FP constant of the specified type to a smaller type
838 /// in order to save space and / or reduce runtime.
839 bool ShouldShrinkFPConstant(EVT VT) const override {
840 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
841 // expensive than a straight movsd. On the other hand, it's important to
842 // shrink long double fp constant since fldt is very slow.
843 return !X86ScalarSSEf64 || VT == MVT::f80;
846 /// Return true if we believe it is correct and profitable to reduce the
847 /// load node to a smaller type.
848 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
849 EVT NewVT) const override;
851 /// Return true if the specified scalar FP type is computed in an SSE
852 /// register, not on the X87 floating point stack.
853 bool isScalarFPTypeInSSEReg(EVT VT) const {
854 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
855 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
858 /// \brief Returns true if it is beneficial to convert a load of a constant
859 /// to just the constant itself.
860 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
861 Type *Ty) const override;
863 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
865 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
867 /// Intel processors have a unified instruction and data cache
868 const char * getClearCacheBuiltinName() const override {
869 return nullptr; // nothing to do, move along.
872 unsigned getRegisterByName(const char* RegName, EVT VT,
873 SelectionDAG &DAG) const override;
875 /// This method returns a target specific FastISel object,
876 /// or null if the target does not support "fast" ISel.
877 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
878 const TargetLibraryInfo *libInfo) const override;
880 /// Return true if the target stores stack protector cookies at a fixed
881 /// offset in some non-standard address space, and populates the address
882 /// space and offset as appropriate.
883 bool getStackCookieLocation(unsigned &AddressSpace,
884 unsigned &Offset) const override;
886 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
887 SelectionDAG &DAG) const;
889 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
891 bool useLoadStackGuardNode() const override;
892 /// \brief Customize the preferred legalization strategy for certain types.
893 LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
895 bool isIntDivCheap(EVT VT, AttributeSet Attr) const override;
898 std::pair<const TargetRegisterClass *, uint8_t>
899 findRepresentativeClass(const TargetRegisterInfo *TRI,
900 MVT VT) const override;
903 /// Keep a pointer to the X86Subtarget around so that we can
904 /// make the right decision when generating code for different targets.
905 const X86Subtarget *Subtarget;
906 const DataLayout *TD;
908 /// Select between SSE or x87 floating point ops.
909 /// When SSE is available, use it for f32 operations.
910 /// When SSE2 is available, use it for f64 operations.
911 bool X86ScalarSSEf32;
912 bool X86ScalarSSEf64;
914 /// A list of legal FP immediates.
915 std::vector<APFloat> LegalFPImmediates;
917 /// Indicate that this x86 target can instruction
918 /// select the specified FP immediate natively.
919 void addLegalFPImmediate(const APFloat& Imm) {
920 LegalFPImmediates.push_back(Imm);
923 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
924 CallingConv::ID CallConv, bool isVarArg,
925 const SmallVectorImpl<ISD::InputArg> &Ins,
926 SDLoc dl, SelectionDAG &DAG,
927 SmallVectorImpl<SDValue> &InVals) const;
928 SDValue LowerMemArgument(SDValue Chain,
929 CallingConv::ID CallConv,
930 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
931 SDLoc dl, SelectionDAG &DAG,
932 const CCValAssign &VA, MachineFrameInfo *MFI,
934 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
935 SDLoc dl, SelectionDAG &DAG,
936 const CCValAssign &VA,
937 ISD::ArgFlagsTy Flags) const;
939 // Call lowering helpers.
941 /// Check whether the call is eligible for tail call optimization. Targets
942 /// that want to do tail call optimization should implement this function.
943 bool IsEligibleForTailCallOptimization(SDValue Callee,
944 CallingConv::ID CalleeCC,
946 bool isCalleeStructRet,
947 bool isCallerStructRet,
949 const SmallVectorImpl<ISD::OutputArg> &Outs,
950 const SmallVectorImpl<SDValue> &OutVals,
951 const SmallVectorImpl<ISD::InputArg> &Ins,
952 SelectionDAG& DAG) const;
953 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
954 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
955 SDValue Chain, bool IsTailCall, bool Is64Bit,
956 int FPDiff, SDLoc dl) const;
958 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
959 SelectionDAG &DAG) const;
961 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
963 bool isReplace) const;
965 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
966 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
967 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
968 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
969 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
970 SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const;
971 SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const;
973 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
974 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
975 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
976 SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
977 int64_t Offset, SelectionDAG &DAG) const;
978 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
979 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
980 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
981 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
982 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
983 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
984 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
985 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
986 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
987 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
988 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
989 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
990 SDLoc dl, SelectionDAG &DAG) const;
991 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
992 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
993 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
994 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
995 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
996 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
997 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
998 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
999 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1000 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1001 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1002 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
1003 SDValue LowerCATCHRET(SDValue Op, SelectionDAG &DAG) const;
1004 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1005 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1006 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1007 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1008 SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
1009 SDValue LowerGC_TRANSITION_START(SDValue Op, SelectionDAG &DAG) const;
1010 SDValue LowerGC_TRANSITION_END(SDValue Op, SelectionDAG &DAG) const;
1013 LowerFormalArguments(SDValue Chain,
1014 CallingConv::ID CallConv, bool isVarArg,
1015 const SmallVectorImpl<ISD::InputArg> &Ins,
1016 SDLoc dl, SelectionDAG &DAG,
1017 SmallVectorImpl<SDValue> &InVals) const override;
1018 SDValue LowerCall(CallLoweringInfo &CLI,
1019 SmallVectorImpl<SDValue> &InVals) const override;
1021 SDValue LowerReturn(SDValue Chain,
1022 CallingConv::ID CallConv, bool isVarArg,
1023 const SmallVectorImpl<ISD::OutputArg> &Outs,
1024 const SmallVectorImpl<SDValue> &OutVals,
1025 SDLoc dl, SelectionDAG &DAG) const override;
1027 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1029 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
1031 EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1032 ISD::NodeType ExtendKind) const override;
1034 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1036 const SmallVectorImpl<ISD::OutputArg> &Outs,
1037 LLVMContext &Context) const override;
1039 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1041 bool shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
1042 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
1043 TargetLoweringBase::AtomicRMWExpansionKind
1044 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
1047 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
1049 bool needsCmpXchgNb(Type *MemType) const;
1051 /// Utility function to emit atomic-load-arith operations (and, or, xor,
1052 /// nand, max, min, umax, umin). It takes the corresponding instruction to
1053 /// expand, the associated machine basic block, and the associated X86
1054 /// opcodes for reg/reg.
1055 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
1056 MachineBasicBlock *MBB) const;
1058 /// Utility function to emit atomic-load-arith operations (and, or, xor,
1059 /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
1060 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
1061 MachineBasicBlock *MBB) const;
1063 // Utility function to emit the low-level va_arg code for X86-64.
1064 MachineBasicBlock *EmitVAARG64WithCustomInserter(
1066 MachineBasicBlock *MBB) const;
1068 /// Utility function to emit the xmm reg save portion of va_start.
1069 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
1070 MachineInstr *BInstr,
1071 MachineBasicBlock *BB) const;
1073 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
1074 MachineBasicBlock *BB) const;
1076 MachineBasicBlock *EmitLoweredAtomicFP(MachineInstr *I,
1077 MachineBasicBlock *BB) const;
1079 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
1080 MachineBasicBlock *BB) const;
1082 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
1083 MachineBasicBlock *BB) const;
1085 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
1086 MachineBasicBlock *BB) const;
1088 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
1089 MachineBasicBlock *BB) const;
1091 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
1092 MachineBasicBlock *MBB) const;
1094 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
1095 MachineBasicBlock *MBB) const;
1097 MachineBasicBlock *emitFMA3Instr(MachineInstr *MI,
1098 MachineBasicBlock *MBB) const;
1100 /// Emit nodes that will be selected as "test Op0,Op0", or something
1101 /// equivalent, for use with the given x86 condition code.
1102 SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl,
1103 SelectionDAG &DAG) const;
1105 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
1106 /// equivalent, for use with the given x86 condition code.
1107 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl,
1108 SelectionDAG &DAG) const;
1110 /// Convert a comparison if required by the subtarget.
1111 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
1113 /// Use rsqrt* to speed up sqrt calculations.
1114 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1115 unsigned &RefinementSteps,
1116 bool &UseOneConstNR) const override;
1118 /// Use rcp* to speed up fdiv calculations.
1119 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1120 unsigned &RefinementSteps) const override;
1122 /// Reassociate floating point divisions into multiply by reciprocal.
1123 unsigned combineRepeatedFPDivisors() const override;
1127 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1128 const TargetLibraryInfo *libInfo);
1132 #endif // X86ISELLOWERING_H