1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
27 // X86 Specific DAG Nodes
29 // Start the numbering where the builtin ops leave off.
30 FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
32 /// BSF - Bit scan forward.
33 /// BSR - Bit scan reverse.
37 /// SHLD, SHRD - Double shift instructions. These correspond to
38 /// X86::SHLDxx and X86::SHRDxx instructions.
42 /// FAND - Bitwise logical AND of floating point values. This corresponds
43 /// to X86::ANDPS or X86::ANDPD.
46 /// FOR - Bitwise logical OR of floating point values. This corresponds
47 /// to X86::ORPS or X86::ORPD.
50 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
51 /// to X86::XORPS or X86::XORPD.
54 /// FSRL - Bitwise logical right shift of floating point values. These
55 /// corresponds to X86::PSRLDQ.
58 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
59 /// integer source in memory and FP reg result. This corresponds to the
60 /// X86::FILD*m instructions. It has three inputs (token chain, address,
61 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
62 /// also produces a flag).
66 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
67 /// integer destination in memory and a FP reg source. This corresponds
68 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
69 /// has two inputs (token chain and address) and two outputs (int value
75 /// FLD - This instruction implements an extending load to FP stack slots.
76 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
77 /// operand, ptr to load from, and a ValueType node indicating the type
81 /// FST - This instruction implements a truncating store to FP stack
82 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
83 /// chain operand, value to store, address, and a ValueType to store it
87 /// CALL/TAILCALL - These operations represent an abstract X86 call
88 /// instruction, which includes a bunch of information. In particular the
89 /// operands of these node are:
91 /// #0 - The incoming token chain
93 /// #2 - The number of arg bytes the caller pushes on the stack.
94 /// #3 - The number of arg bytes the callee pops off the stack.
95 /// #4 - The value to pass in AL/AX/EAX (optional)
96 /// #5 - The value to pass in DL/DX/EDX (optional)
98 /// The result values of these nodes are:
100 /// #0 - The outgoing token chain
101 /// #1 - The first register result value (optional)
102 /// #2 - The second register result value (optional)
104 /// The CALL vs TAILCALL distinction boils down to whether the callee is
105 /// known not to modify the caller's stack frame, as is standard with
110 /// RDTSC_DAG - This operation implements the lowering for
114 /// X86 compare and logical compare instructions.
117 /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
118 /// operand produced by a CMP instruction.
121 /// X86 conditional moves. Operand 1 and operand 2 are the two values
122 /// to select from (operand 1 is a R/W operand). Operand 3 is the
123 /// condition code, and operand 4 is the flag operand produced by a CMP
124 /// or TEST instruction. It also writes a flag result.
127 /// X86 conditional branches. Operand 1 is the chain operand, operand 2
128 /// is the block to branch if condition is true, operand 3 is the
129 /// condition code, and operand 4 is the flag operand produced by a CMP
130 /// or TEST instruction.
133 /// Return with a flag operand. Operand 1 is the chain operand, operand
134 /// 2 is the number of bytes of stack to pop.
137 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
140 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
143 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
144 /// at function entry, used for PIC code.
147 /// Wrapper - A wrapper node for TargetConstantPool,
148 /// TargetExternalSymbol, and TargetGlobalAddress.
151 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
152 /// relative displacements.
155 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
156 /// i32, corresponds to X86::PEXTRB.
159 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
160 /// i32, corresponds to X86::PEXTRW.
163 /// INSERTPS - Insert any element of a 4 x float vector into any element
164 /// of a destination 4 x floatvector.
167 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
168 /// corresponds to X86::PINSRB.
171 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
172 /// corresponds to X86::PINSRW.
175 /// FMAX, FMIN - Floating point max and min.
179 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
180 /// approximation. Note that these typically require refinement
181 /// in order to obtain suitable precision.
184 // Thread Local Storage
185 TLSADDR, THREAD_POINTER,
187 // Exception Handling helpers
190 /// TC_RETURN - Tail call return.
192 /// operand #1 callee (register or absolute)
193 /// operand #2 stack adjustment
194 /// operand #3 optional in flag
201 // Store FP control world into i16 memory
206 /// Define some predicates that are used for node matching.
208 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
209 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
210 bool isPSHUFDMask(SDNode *N);
212 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
213 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
214 bool isPSHUFHWMask(SDNode *N);
216 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
217 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
218 bool isPSHUFLWMask(SDNode *N);
220 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
221 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
222 bool isSHUFPMask(SDNode *N);
224 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
225 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
226 bool isMOVHLPSMask(SDNode *N);
228 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
229 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
231 bool isMOVHLPS_v_undef_Mask(SDNode *N);
233 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
234 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
235 bool isMOVLPMask(SDNode *N);
237 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
238 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
239 /// as well as MOVLHPS.
240 bool isMOVHPMask(SDNode *N);
242 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
243 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
244 bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false);
246 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
247 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
248 bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false);
250 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
251 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
253 bool isUNPCKL_v_undef_Mask(SDNode *N);
255 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
256 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
258 bool isUNPCKH_v_undef_Mask(SDNode *N);
260 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
261 /// specifies a shuffle of elements that is suitable for input to MOVSS,
262 /// MOVSD, and MOVD, i.e. setting the lowest element.
263 bool isMOVLMask(SDNode *N);
265 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
266 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
267 bool isMOVSHDUPMask(SDNode *N);
269 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
270 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
271 bool isMOVSLDUPMask(SDNode *N);
273 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
274 /// specifies a splat of a single element.
275 bool isSplatMask(SDNode *N);
277 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
278 /// specifies a splat of zero element.
279 bool isSplatLoMask(SDNode *N);
281 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
282 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
284 unsigned getShuffleSHUFImmediate(SDNode *N);
286 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
287 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
289 unsigned getShufflePSHUFHWImmediate(SDNode *N);
291 /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
292 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
294 unsigned getShufflePSHUFLWImmediate(SDNode *N);
297 //===--------------------------------------------------------------------===//
298 // X86TargetLowering - X86 Implementation of the TargetLowering interface
299 class X86TargetLowering : public TargetLowering {
300 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
301 int RegSaveFrameIndex; // X86-64 vararg func register save area.
302 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
303 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
304 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
305 int BytesCallerReserves; // Number of arg bytes caller makes.
308 explicit X86TargetLowering(TargetMachine &TM);
310 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
312 SDOperand getPICJumpTableRelocBase(SDOperand Table,
313 SelectionDAG &DAG) const;
315 // Return the number of bytes that a function should pop when it returns (in
316 // addition to the space used by the return address).
318 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
320 // Return the number of bytes that the caller reserves for arguments passed
322 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
324 /// getStackPtrReg - Return the stack pointer register we are using: either
326 unsigned getStackPtrReg() const { return X86StackPtr; }
328 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
329 /// function arguments in the caller parameter area. For X86, aggregates
330 /// that contains are placed at 16-byte boundaries while the rest are at
331 /// 4-byte boundaries.
332 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
334 /// LowerOperation - Provide custom lowering hooks for some operations.
336 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
338 /// ExpandOperation - Custom lower the specified operation, splitting the
339 /// value into two pieces.
341 virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG);
344 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
346 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
347 MachineBasicBlock *MBB);
349 /// getTargetNodeName - This method returns the name of a target specific
351 virtual const char *getTargetNodeName(unsigned Opcode) const;
353 /// getSetCCResultType - Return the ISD::SETCC ValueType
354 virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
356 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
357 /// in Mask are known to be either zero or one and return them in the
358 /// KnownZero/KnownOne bitsets.
359 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
363 const SelectionDAG &DAG,
364 unsigned Depth = 0) const;
366 SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
368 ConstraintType getConstraintType(const std::string &Constraint) const;
370 std::vector<unsigned>
371 getRegClassForInlineAsmConstraint(const std::string &Constraint,
372 MVT::ValueType VT) const;
374 virtual const char *LowerXConstraint(MVT::ValueType ConstraintVT) const;
376 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
377 /// vector. If it is invalid, don't add anything to Ops.
378 virtual void LowerAsmOperandForConstraint(SDOperand Op,
379 char ConstraintLetter,
380 std::vector<SDOperand> &Ops,
381 SelectionDAG &DAG) const;
383 /// getRegForInlineAsmConstraint - Given a physical register constraint
384 /// (e.g. {edx}), return the register number and the register class for the
385 /// register. This should only be used for C_Register constraints. On
386 /// error, this returns a register number of 0.
387 std::pair<unsigned, const TargetRegisterClass*>
388 getRegForInlineAsmConstraint(const std::string &Constraint,
389 MVT::ValueType VT) const;
391 /// isLegalAddressingMode - Return true if the addressing mode represented
392 /// by AM is legal for this target, for a load/store of the specified type.
393 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
395 /// isTruncateFree - Return true if it's free to truncate a value of
396 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
397 /// register EAX to i16 by referencing its sub-register AX.
398 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
399 virtual bool isTruncateFree(MVT::ValueType VT1, MVT::ValueType VT2) const;
401 /// isShuffleMaskLegal - Targets can use this to indicate that they only
402 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
403 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
404 /// values are assumed to be legal.
405 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
407 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
408 /// used by Targets can use this to indicate if there is a suitable
409 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
411 virtual bool isVectorClearMaskLegal(const std::vector<SDOperand> &BVOps,
413 SelectionDAG &DAG) const;
415 /// ShouldShrinkFPConstant - If true, then instruction selection should
416 /// seek to shrink the FP constant of the specified type to a smaller type
417 /// in order to save space and / or reduce runtime.
418 virtual bool ShouldShrinkFPConstant(MVT::ValueType VT) const {
419 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
420 // expensive than a straight movsd. On the other hand, it's important to
421 // shrink long double fp constant since fldt is very slow.
422 return !X86ScalarSSEf64 || VT == MVT::f80;
425 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
426 /// for tail call optimization. Target which want to do tail call
427 /// optimization should implement this function.
428 virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
430 SelectionDAG &DAG) const;
432 virtual const X86Subtarget* getSubtarget() {
436 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
437 /// computed in an SSE register, not on the X87 floating point stack.
438 bool isScalarFPTypeInSSEReg(MVT::ValueType VT) const {
439 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
440 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
444 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
445 /// make the right decision when generating code for different targets.
446 const X86Subtarget *Subtarget;
447 const TargetRegisterInfo *RegInfo;
449 /// X86StackPtr - X86 physical register used as stack ptr.
450 unsigned X86StackPtr;
452 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
453 /// floating point ops.
454 /// When SSE is available, use it for f32 operations.
455 /// When SSE2 is available, use it for f64 operations.
456 bool X86ScalarSSEf32;
457 bool X86ScalarSSEf64;
459 SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall,
460 unsigned CallingConv, SelectionDAG &DAG);
462 SDOperand LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
463 const CCValAssign &VA, MachineFrameInfo *MFI,
464 unsigned CC, SDOperand Root, unsigned i);
466 SDOperand LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
467 const SDOperand &StackPtr,
468 const CCValAssign &VA, SDOperand Chain,
471 // Call lowering helpers.
472 bool IsCalleePop(SDOperand Op);
473 bool CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall);
474 bool CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall);
475 SDOperand EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDOperand &OutRetAddr,
476 SDOperand Chain, bool IsTailCall, bool Is64Bit,
479 bool CopyTailCallByValClobberedRegToVirtReg(bool containsByValArg,
480 SmallVector< std::pair<unsigned, unsigned>,8> &TailCallByValClobberedVRegs,
481 SmallVector<MVT::ValueType, 8> &TailCallByValClobberedVRegTypes,
482 std::pair<unsigned, SDOperand> &RegToPass,
488 CCAssignFn *CCAssignFnForNode(SDOperand Op) const;
489 NameDecorationStyle NameDecorationForFORMAL_ARGUMENTS(SDOperand Op);
490 unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG);
492 std::pair<SDOperand,SDOperand> FP_TO_SINTHelper(SDOperand Op,
495 SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
496 SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
497 SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
498 SDOperand LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG);
499 SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
500 SDOperand LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG);
501 SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
502 SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
503 SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
504 SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
505 SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG);
506 SDOperand LowerShift(SDOperand Op, SelectionDAG &DAG);
507 SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
508 SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
509 SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
510 SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
511 SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG);
512 SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
513 SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
514 SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
515 SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
516 SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
517 SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
518 SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
519 SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG);
520 SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
521 SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
522 SDOperand LowerVACOPY(SDOperand Op, SelectionDAG &DAG);
523 SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
524 SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
525 SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
526 SDOperand LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, SelectionDAG &DAG);
527 SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG);
528 SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG);
529 SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG);
530 SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG);
531 SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG);
532 SDOperand LowerLCS(SDOperand Op, SelectionDAG &DAG);
533 SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
534 SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG);
535 SDNode *ExpandATOMIC_LCS(SDNode *N, SelectionDAG &DAG);
537 SDOperand EmitTargetCodeForMemset(SelectionDAG &DAG,
539 SDOperand Dst, SDOperand Src,
540 SDOperand Size, unsigned Align,
541 const Value *DstSV, uint64_t DstOff);
542 SDOperand EmitTargetCodeForMemcpy(SelectionDAG &DAG,
544 SDOperand Dst, SDOperand Src,
545 SDOperand Size, unsigned Align,
547 const Value *DstSV, uint64_t DstOff,
548 const Value *SrcSV, uint64_t SrcOff);
552 #endif // X86ISELLOWERING_H