1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
27 // X86 Specific DAG Nodes
29 // Start the numbering where the builtin ops leave off.
30 FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
32 /// BSF - Bit scan forward.
33 /// BSR - Bit scan reverse.
37 /// SHLD, SHRD - Double shift instructions. These correspond to
38 /// X86::SHLDxx and X86::SHRDxx instructions.
42 /// FAND - Bitwise logical AND of floating point values. This corresponds
43 /// to X86::ANDPS or X86::ANDPD.
46 /// FOR - Bitwise logical OR of floating point values. This corresponds
47 /// to X86::ORPS or X86::ORPD.
50 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
51 /// to X86::XORPS or X86::XORPD.
54 /// FSRL - Bitwise logical right shift of floating point values. These
55 /// corresponds to X86::PSRLDQ.
58 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
59 /// integer source in memory and FP reg result. This corresponds to the
60 /// X86::FILD*m instructions. It has three inputs (token chain, address,
61 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
62 /// also produces a flag).
66 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
67 /// integer destination in memory and a FP reg source. This corresponds
68 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
69 /// has two inputs (token chain and address) and two outputs (int value
75 /// FLD - This instruction implements an extending load to FP stack slots.
76 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
77 /// operand, ptr to load from, and a ValueType node indicating the type
81 /// FST - This instruction implements a truncating store to FP stack
82 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
83 /// chain operand, value to store, address, and a ValueType to store it
87 /// FP_GET_RESULT - This corresponds to FpGETRESULT pseudo instruction
88 /// which copies from ST(0) to the destination. It takes a chain and
89 /// writes a RFP result and a chain.
92 /// FP_GET_RESULT2 - Same as FP_GET_RESULT except it copies two values
96 /// FP_SET_RESULT - This corresponds to FpSETRESULT pseudo instruction
97 /// which copies the source operand to ST(0). It takes a chain+value and
98 /// returns a chain and a flag.
101 /// CALL/TAILCALL - These operations represent an abstract X86 call
102 /// instruction, which includes a bunch of information. In particular the
103 /// operands of these node are:
105 /// #0 - The incoming token chain
107 /// #2 - The number of arg bytes the caller pushes on the stack.
108 /// #3 - The number of arg bytes the callee pops off the stack.
109 /// #4 - The value to pass in AL/AX/EAX (optional)
110 /// #5 - The value to pass in DL/DX/EDX (optional)
112 /// The result values of these nodes are:
114 /// #0 - The outgoing token chain
115 /// #1 - The first register result value (optional)
116 /// #2 - The second register result value (optional)
118 /// The CALL vs TAILCALL distinction boils down to whether the callee is
119 /// known not to modify the caller's stack frame, as is standard with
124 /// RDTSC_DAG - This operation implements the lowering for
128 /// X86 compare and logical compare instructions.
131 /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
132 /// operand produced by a CMP instruction.
135 /// X86 conditional moves. Operand 1 and operand 2 are the two values
136 /// to select from (operand 1 is a R/W operand). Operand 3 is the
137 /// condition code, and operand 4 is the flag operand produced by a CMP
138 /// or TEST instruction. It also writes a flag result.
141 /// X86 conditional branches. Operand 1 is the chain operand, operand 2
142 /// is the block to branch if condition is true, operand 3 is the
143 /// condition code, and operand 4 is the flag operand produced by a CMP
144 /// or TEST instruction.
147 /// Return with a flag operand. Operand 1 is the chain operand, operand
148 /// 2 is the number of bytes of stack to pop.
151 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
154 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
157 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
158 /// at function entry, used for PIC code.
161 /// Wrapper - A wrapper node for TargetConstantPool,
162 /// TargetExternalSymbol, and TargetGlobalAddress.
165 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
166 /// relative displacements.
169 /// S2VEC - X86 version of SCALAR_TO_VECTOR. The destination base does not
170 /// have to match the operand type.
173 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
174 /// i32, corresponds to X86::PEXTRW.
177 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
178 /// corresponds to X86::PINSRW.
181 /// FMAX, FMIN - Floating point max and min.
185 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
186 /// approximation. Note that these typically require refinement
187 /// in order to obtain suitable precision.
190 // Thread Local Storage
191 TLSADDR, THREAD_POINTER,
193 // Exception Handling helpers
198 // operand #1 callee (register or absolute)
199 // operand #2 stack adjustment
200 // operand #3 optional in flag
203 // Store FP control world into i16 memory
208 /// Define some predicates that are used for node matching.
210 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
211 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
212 bool isPSHUFDMask(SDNode *N);
214 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
215 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
216 bool isPSHUFHWMask(SDNode *N);
218 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
219 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
220 bool isPSHUFLWMask(SDNode *N);
222 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
223 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
224 bool isSHUFPMask(SDNode *N);
226 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
227 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
228 bool isMOVHLPSMask(SDNode *N);
230 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
231 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
233 bool isMOVHLPS_v_undef_Mask(SDNode *N);
235 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
236 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
237 bool isMOVLPMask(SDNode *N);
239 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
240 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
241 /// as well as MOVLHPS.
242 bool isMOVHPMask(SDNode *N);
244 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
245 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
246 bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false);
248 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
249 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
250 bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false);
252 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
253 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
255 bool isUNPCKL_v_undef_Mask(SDNode *N);
257 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
258 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
260 bool isUNPCKH_v_undef_Mask(SDNode *N);
262 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
263 /// specifies a shuffle of elements that is suitable for input to MOVSS,
264 /// MOVSD, and MOVD, i.e. setting the lowest element.
265 bool isMOVLMask(SDNode *N);
267 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
268 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
269 bool isMOVSHDUPMask(SDNode *N);
271 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
272 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
273 bool isMOVSLDUPMask(SDNode *N);
275 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
276 /// specifies a splat of a single element.
277 bool isSplatMask(SDNode *N);
279 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
280 /// specifies a splat of zero element.
281 bool isSplatLoMask(SDNode *N);
283 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
284 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
286 unsigned getShuffleSHUFImmediate(SDNode *N);
288 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
289 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
291 unsigned getShufflePSHUFHWImmediate(SDNode *N);
293 /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
294 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
296 unsigned getShufflePSHUFLWImmediate(SDNode *N);
300 /// X86_64SRet - These represent different ways to implement x86_64 struct
301 /// returns call results.
303 InMemory, // Really is sret, returns in memory.
304 InGPR64, // Returns in a pair of 64-bit integer registers.
305 InSSE, // Returns in a pair of SSE registers.
306 InX87 // Returns in a pair of f80 X87 registers.
310 //===--------------------------------------------------------------------===//
311 // X86TargetLowering - X86 Implementation of the TargetLowering interface
312 class X86TargetLowering : public TargetLowering {
313 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
314 int RegSaveFrameIndex; // X86-64 vararg func register save area.
315 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
316 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
317 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
318 int BytesCallerReserves; // Number of arg bytes caller makes.
321 explicit X86TargetLowering(TargetMachine &TM);
323 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
325 SDOperand getPICJumpTableRelocBase(SDOperand Table,
326 SelectionDAG &DAG) const;
328 // Return the number of bytes that a function should pop when it returns (in
329 // addition to the space used by the return address).
331 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
333 // Return the number of bytes that the caller reserves for arguments passed
335 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
337 /// getStackPtrReg - Return the stack pointer register we are using: either
339 unsigned getStackPtrReg() const { return X86StackPtr; }
341 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
342 /// function arguments in the caller parameter area. For X86, aggregates
343 /// that contains are placed at 16-byte boundaries while the rest are at
344 /// 4-byte boundaries.
345 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
347 /// LowerOperation - Provide custom lowering hooks for some operations.
349 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
351 /// ExpandOperation - Custom lower the specified operation, splitting the
352 /// value into two pieces.
354 virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG);
357 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
359 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
360 MachineBasicBlock *MBB);
362 /// getTargetNodeName - This method returns the name of a target specific
364 virtual const char *getTargetNodeName(unsigned Opcode) const;
366 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
367 /// in Mask are known to be either zero or one and return them in the
368 /// KnownZero/KnownOne bitsets.
369 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
373 const SelectionDAG &DAG,
374 unsigned Depth = 0) const;
376 SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
378 ConstraintType getConstraintType(const std::string &Constraint) const;
380 std::vector<unsigned>
381 getRegClassForInlineAsmConstraint(const std::string &Constraint,
382 MVT::ValueType VT) const;
384 virtual void lowerXConstraint(MVT::ValueType ConstraintVT,
387 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
388 /// vector. If it is invalid, don't add anything to Ops.
389 virtual void LowerAsmOperandForConstraint(SDOperand Op,
390 char ConstraintLetter,
391 std::vector<SDOperand> &Ops,
394 /// getRegForInlineAsmConstraint - Given a physical register constraint
395 /// (e.g. {edx}), return the register number and the register class for the
396 /// register. This should only be used for C_Register constraints. On
397 /// error, this returns a register number of 0.
398 std::pair<unsigned, const TargetRegisterClass*>
399 getRegForInlineAsmConstraint(const std::string &Constraint,
400 MVT::ValueType VT) const;
402 /// isLegalAddressingMode - Return true if the addressing mode represented
403 /// by AM is legal for this target, for a load/store of the specified type.
404 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
406 /// isTruncateFree - Return true if it's free to truncate a value of
407 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
408 /// register EAX to i16 by referencing its sub-register AX.
409 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
410 virtual bool isTruncateFree(MVT::ValueType VT1, MVT::ValueType VT2) const;
412 /// isShuffleMaskLegal - Targets can use this to indicate that they only
413 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
414 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
415 /// values are assumed to be legal.
416 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
418 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
419 /// used by Targets can use this to indicate if there is a suitable
420 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
422 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
424 SelectionDAG &DAG) const;
426 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
427 /// for tail call optimization. Target which want to do tail call
428 /// optimization should implement this function.
429 virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
431 SelectionDAG &DAG) const;
433 virtual const TargetSubtarget* getSubtarget() {
434 return static_cast<const TargetSubtarget*>(Subtarget);
437 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
438 /// computed in an SSE register, not on the X87 floating point stack.
439 bool isScalarFPTypeInSSEReg(MVT::ValueType VT) const {
440 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
441 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
445 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
446 /// make the right decision when generating code for different targets.
447 const X86Subtarget *Subtarget;
448 const MRegisterInfo *RegInfo;
450 /// X86StackPtr - X86 physical register used as stack ptr.
451 unsigned X86StackPtr;
453 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
454 /// floating point ops.
455 /// When SSE is available, use it for f32 operations.
456 /// When SSE2 is available, use it for f64 operations.
457 bool X86ScalarSSEf32;
458 bool X86ScalarSSEf64;
460 X86::X86_64SRet ClassifyX86_64SRetCallReturn(const Function *Fn);
462 void X86_64AnalyzeSRetCallOperands(SDNode*, CCAssignFn*, CCState&);
464 SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall,
465 unsigned CallingConv, SelectionDAG &DAG);
467 SDNode *LowerCallResultToTwo64BitRegs(SDOperand Chain, SDOperand InFlag,
468 SDNode *TheCall, unsigned Reg1,
469 unsigned Reg2, MVT::ValueType VT,
472 SDNode *LowerCallResultToTwoX87Regs(SDOperand Chain, SDOperand InFlag,
473 SDNode *TheCall, SelectionDAG &DAG);
475 SDOperand LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
476 const CCValAssign &VA, MachineFrameInfo *MFI,
477 SDOperand Root, unsigned i);
479 SDOperand LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
480 const SDOperand &StackPtr,
481 const CCValAssign &VA, SDOperand Chain,
484 // Call lowering helpers.
485 bool IsCalleePop(SDOperand Op);
486 CCAssignFn *CCAssignFnForNode(SDOperand Op) const;
487 NameDecorationStyle NameDecorationForFORMAL_ARGUMENTS(SDOperand Op);
488 unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG);
490 std::pair<SDOperand,SDOperand> FP_TO_SINTHelper(SDOperand Op,
493 SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
494 SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
495 SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
496 SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
497 SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
498 SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
499 SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
500 SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
501 SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG);
502 SDOperand LowerShift(SDOperand Op, SelectionDAG &DAG);
503 SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
504 SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
505 SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
506 SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
507 SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG);
508 SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
509 SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
510 SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
511 SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
512 SDOperand LowerMEMCPYInline(SDOperand Dest, SDOperand Source,
513 SDOperand Chain, unsigned Size, unsigned Align,
515 SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
516 SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
517 SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
518 SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG);
519 SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
520 SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
521 SDOperand LowerVACOPY(SDOperand Op, SelectionDAG &DAG);
522 SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
523 SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
524 SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
525 SDOperand LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, SelectionDAG &DAG);
526 SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG);
527 SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG);
528 SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG);
529 SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG);
530 SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG);
531 SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
532 SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG);
536 #endif // X86ISELLOWERING_H