1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetOptions.h"
25 class X86TargetMachine;
28 // X86 Specific DAG Nodes
29 enum NodeType : unsigned {
30 // Start the numbering where the builtin ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
38 /// Double shift instructions. These correspond to
39 /// X86::SHLDxx and X86::SHRDxx instructions.
43 /// Bitwise logical AND of floating point values. This corresponds
44 /// to X86::ANDPS or X86::ANDPD.
47 /// Bitwise logical OR of floating point values. This corresponds
48 /// to X86::ORPS or X86::ORPD.
51 /// Bitwise logical XOR of floating point values. This corresponds
52 /// to X86::XORPS or X86::XORPD.
55 /// Bitwise logical ANDNOT of floating point values. This
56 /// corresponds to X86::ANDNPS or X86::ANDNPD.
59 /// These operations represent an abstract X86 call
60 /// instruction, which includes a bunch of information. In particular the
61 /// operands of these node are:
63 /// #0 - The incoming token chain
65 /// #2 - The number of arg bytes the caller pushes on the stack.
66 /// #3 - The number of arg bytes the callee pops off the stack.
67 /// #4 - The value to pass in AL/AX/EAX (optional)
68 /// #5 - The value to pass in DL/DX/EDX (optional)
70 /// The result values of these nodes are:
72 /// #0 - The outgoing token chain
73 /// #1 - The first register result value (optional)
74 /// #2 - The second register result value (optional)
78 /// This operation implements the lowering for readcyclecounter
81 /// X86 Read Time-Stamp Counter and Processor ID.
84 /// X86 Read Performance Monitoring Counters.
87 /// X86 compare and logical compare instructions.
90 /// X86 bit-test instructions.
93 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
94 /// operand, usually produced by a CMP instruction.
100 // Same as SETCC except it's materialized with a sbb and the value is all
101 // one's or all zero's.
102 SETCC_CARRY, // R = carry_bit ? ~0 : 0
104 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
105 /// Operands are two FP values to compare; result is a mask of
106 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
109 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
110 /// result in an integer GPR. Needs masking for scalar result.
113 /// X86 conditional moves. Operand 0 and operand 1 are the two values
114 /// to select from. Operand 2 is the condition code, and operand 3 is the
115 /// flag operand produced by a CMP or TEST instruction. It also writes a
119 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
120 /// is the block to branch if condition is true, operand 2 is the
121 /// condition code, and operand 3 is the flag operand produced by a CMP
122 /// or TEST instruction.
125 /// Return with a flag operand. Operand 0 is the chain operand, operand
126 /// 1 is the number of bytes of stack to pop.
129 /// Repeat fill, corresponds to X86::REP_STOSx.
132 /// Repeat move, corresponds to X86::REP_MOVSx.
135 /// On Darwin, this node represents the result of the popl
136 /// at function entry, used for PIC code.
139 /// A wrapper node for TargetConstantPool,
140 /// TargetExternalSymbol, and TargetGlobalAddress.
143 /// Special wrapper used under X86-64 PIC mode for RIP
144 /// relative displacements.
147 /// Copies a 64-bit value from the low word of an XMM vector
148 /// to an MMX vector. If you think this is too close to the previous
149 /// mnemonic, so do I; blame Intel.
152 /// Copies a 32-bit value from the low word of a MMX
156 /// Copies a GPR into the low 32-bit word of a MMX vector
157 /// and zero out the high word.
160 /// Extract an 8-bit value from a vector and zero extend it to
161 /// i32, corresponds to X86::PEXTRB.
164 /// Extract a 16-bit value from a vector and zero extend it to
165 /// i32, corresponds to X86::PEXTRW.
168 /// Insert any element of a 4 x float vector into any element
169 /// of a destination 4 x floatvector.
172 /// Insert the lower 8-bits of a 32-bit value to a vector,
173 /// corresponds to X86::PINSRB.
176 /// Insert the lower 16-bits of a 32-bit value to a vector,
177 /// corresponds to X86::PINSRW.
180 /// Shuffle 16 8-bit values within a vector.
183 /// Compute Sum of Absolute Differences.
186 /// Bitwise Logical AND NOT of Packed FP values.
189 /// Copy integer sign.
192 /// Blend where the selector is an immediate.
195 /// Blend where the condition has been shrunk.
196 /// This is used to emphasize that the condition mask is
197 /// no more valid for generic VSELECT optimizations.
200 /// Combined add and sub on an FP vector.
203 // FP vector ops with rounding mode.
212 // FP vector get exponent
216 // Integer add/sub with unsigned saturation.
219 // Integer add/sub with signed saturation.
222 // Unsigned Integer average
224 /// Integer horizontal add.
227 /// Integer horizontal sub.
230 /// Floating point horizontal add.
233 /// Floating point horizontal sub.
236 // Integer absolute value
239 /// Floating point max and min.
242 /// Commutative FMIN and FMAX.
245 /// Floating point reciprocal-sqrt and reciprocal approximation.
246 /// Note that these typically require refinement
247 /// in order to obtain suitable precision.
250 // Thread Local Storage.
253 // Thread Local Storage. A call to get the start address
254 // of the TLS block for the current module.
257 // Thread Local Storage. When calling to an OS provided
258 // thunk at the address from an earlier relocation.
261 // Exception Handling helpers.
264 // SjLj exception handling setjmp.
267 // SjLj exception handling longjmp.
270 /// Tail call return. See X86TargetLowering::LowerCall for
271 /// the list of operands.
274 // Vector move to low scalar and zero higher vector elements.
277 // Vector integer zero-extend.
280 // Vector integer signed-extend.
283 // Vector integer truncate.
285 // Vector integer truncate with unsigned/signed saturation.
294 // Vector signed/unsigned integer to double.
297 // 128-bit vector logical left / right shift
300 // Vector shift elements
303 // Vector shift elements by immediate
306 // Vector packed double/float comparison.
309 // Vector integer comparisons.
311 // Vector integer comparisons, the result is in a mask vector.
314 /// Vector comparison generating mask bits for fp and
315 /// integer signed and unsigned data types.
318 // Vector comparison with rounding mode for FP values
321 // Arithmetic operations with FLAGS results.
322 ADD, SUB, ADC, SBB, SMUL,
323 INC, DEC, OR, XOR, AND,
325 BEXTR, // Bit field extract
327 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
329 // 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS
332 // 8-bit divrem that zero-extend the high result (AH).
336 // X86-specific multiply by immediate.
339 // Vector bitwise comparisons.
342 // Vector packed fp sign bitwise comparisons.
345 // Vector "test" in AVX-512, the result is in a mask vector.
349 // OR/AND test for masks
352 // Several flavors of instructions with vector shuffle behaviors.
357 // AVX512 inter-lane alignr
363 //Shuffle Packed Values at 128-bit granularity
384 //Fix Up Special Packed Float32/64 values
386 //Range Restriction Calculation For Packed Pairs of Float32/64 values
388 // Reduce - Perform Reduction Transformation on scalar\packed FP
390 // RndScale - Round FP Values To Include A Given Number Of Fraction Bits
392 // Broadcast scalar to vector
394 // Broadcast subvector to vector
396 // Insert/Extract vector element
400 /// SSE4A Extraction and Insertion.
403 // Vector multiply packed unsigned doubleword integers
405 // Vector multiply packed signed doubleword integers
407 // Vector Multiply Packed UnsignedIntegers with Round and Scale
409 // Multiply and Add Packed Integers
410 VPMADDUBSW, VPMADDWD,
418 // FMA with rounding mode
426 // Compress and expand
430 //Convert Unsigned/Integer to Scalar Floating-Point Value
435 // Vector float/double to signed/unsigned integer.
436 FP_TO_SINT_RND, FP_TO_UINT_RND,
437 // Save xmm argument registers to the stack, according to %al. An operator
438 // is needed so that this can be expanded with control flow.
439 VASTART_SAVE_XMM_REGS,
441 // Windows's _chkstk call to do stack probing.
444 // For allocating variable amounts of stack space when using
445 // segmented stacks. Check if the current stacklet has enough space, and
446 // falls back to heap allocation if not.
449 // Windows's _ftol2 runtime routine to do fptoui.
458 // Store FP status word into i16 register.
461 // Store contents of %ah into %eflags.
464 // Get a random integer and indicate whether it is valid in CF.
467 // Get a NIST SP800-90B & C compliant random integer and
468 // indicate whether it is valid in CF.
474 // Test if in transactional execution.
478 RSQRT28, RCP28, EXP2,
481 LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
485 // Load, scalar_to_vector, and zero extend.
488 // Store FP control world into i16 memory.
491 /// This instruction implements FP_TO_SINT with the
492 /// integer destination in memory and a FP reg source. This corresponds
493 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
494 /// has two inputs (token chain and address) and two outputs (int value
495 /// and token chain).
500 /// This instruction implements SINT_TO_FP with the
501 /// integer source in memory and FP reg result. This corresponds to the
502 /// X86::FILD*m instructions. It has three inputs (token chain, address,
503 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
504 /// also produces a flag).
508 /// This instruction implements an extending load to FP stack slots.
509 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
510 /// operand, ptr to load from, and a ValueType node indicating the type
514 /// This instruction implements a truncating store to FP stack
515 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
516 /// chain operand, value to store, address, and a ValueType to store it
520 /// This instruction grabs the address of the next argument
521 /// from a va_list. (reads and modifies the va_list in memory)
524 // WARNING: Do not add anything in the end unless you want the node to
525 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
526 // thought as target memory ops!
530 /// Define some predicates that are used for node matching.
532 /// Return true if the specified
533 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
534 /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
535 bool isVEXTRACT128Index(SDNode *N);
537 /// Return true if the specified
538 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
539 /// suitable for input to VINSERTF128, VINSERTI128 instructions.
540 bool isVINSERT128Index(SDNode *N);
542 /// Return true if the specified
543 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
544 /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
545 bool isVEXTRACT256Index(SDNode *N);
547 /// Return true if the specified
548 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
549 /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
550 bool isVINSERT256Index(SDNode *N);
552 /// Return the appropriate
553 /// immediate to extract the specified EXTRACT_SUBVECTOR index
554 /// with VEXTRACTF128, VEXTRACTI128 instructions.
555 unsigned getExtractVEXTRACT128Immediate(SDNode *N);
557 /// Return the appropriate
558 /// immediate to insert at the specified INSERT_SUBVECTOR index
559 /// with VINSERTF128, VINSERT128 instructions.
560 unsigned getInsertVINSERT128Immediate(SDNode *N);
562 /// Return the appropriate
563 /// immediate to extract the specified EXTRACT_SUBVECTOR index
564 /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
565 unsigned getExtractVEXTRACT256Immediate(SDNode *N);
567 /// Return the appropriate
568 /// immediate to insert at the specified INSERT_SUBVECTOR index
569 /// with VINSERTF64x4, VINSERTI64x4 instructions.
570 unsigned getInsertVINSERT256Immediate(SDNode *N);
572 /// Returns true if Elt is a constant zero or floating point constant +0.0.
573 bool isZeroNode(SDValue Elt);
575 /// Returns true of the given offset can be
576 /// fit into displacement field of the instruction.
577 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
578 bool hasSymbolicDisplacement = true);
581 /// Determines whether the callee is required to pop its
582 /// own arguments. Callee pop is necessary to support tail calls.
583 bool isCalleePop(CallingConv::ID CallingConv,
584 bool is64Bit, bool IsVarArg, bool TailCallOpt);
586 /// AVX512 static rounding constants. These need to match the values in
588 enum STATIC_ROUNDING {
597 //===--------------------------------------------------------------------===//
598 // X86 Implementation of the TargetLowering interface
599 class X86TargetLowering final : public TargetLowering {
601 explicit X86TargetLowering(const X86TargetMachine &TM,
602 const X86Subtarget &STI);
604 unsigned getJumpTableEncoding() const override;
605 bool useSoftFloat() const override;
607 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
612 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
613 const MachineBasicBlock *MBB, unsigned uid,
614 MCContext &Ctx) const override;
616 /// Returns relocation base for the given PIC jumptable.
617 SDValue getPICJumpTableRelocBase(SDValue Table,
618 SelectionDAG &DAG) const override;
620 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
621 unsigned JTI, MCContext &Ctx) const override;
623 /// Return the desired alignment for ByVal aggregate
624 /// function arguments in the caller parameter area. For X86, aggregates
625 /// that contains are placed at 16-byte boundaries while the rest are at
626 /// 4-byte boundaries.
627 unsigned getByValTypeAlignment(Type *Ty,
628 const DataLayout &DL) const override;
630 /// Returns the target specific optimal type for load
631 /// and store operations as a result of memset, memcpy, and memmove
632 /// lowering. If DstAlign is zero that means it's safe to destination
633 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
634 /// means there isn't a need to check it against alignment requirement,
635 /// probably because the source does not need to be loaded. If 'IsMemset' is
636 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
637 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
638 /// source is constant so it does not need to be loaded.
639 /// It returns EVT::Other if the type should be determined using generic
640 /// target-independent logic.
641 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
642 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
643 MachineFunction &MF) const override;
645 /// Returns true if it's safe to use load / store of the
646 /// specified type to expand memcpy / memset inline. This is mostly true
647 /// for all types except for some special cases. For example, on X86
648 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
649 /// also does type conversion. Note the specified type doesn't have to be
650 /// legal as the hook is used before type legalization.
651 bool isSafeMemOpType(MVT VT) const override;
653 /// Returns true if the target allows unaligned memory accesses of the
654 /// specified type. Returns whether it is "fast" in the last argument.
655 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
656 bool *Fast) const override;
658 /// Provide custom lowering hooks for some operations.
660 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
662 /// Replace the results of node with an illegal result
663 /// type with new values built out of custom code.
665 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
666 SelectionDAG &DAG) const override;
669 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
671 /// Return true if the target has native support for
672 /// the specified value type and it is 'desirable' to use the type for the
673 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
674 /// instruction encodings are longer and some i16 instructions are slow.
675 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
677 /// Return true if the target has native support for the
678 /// specified value type and it is 'desirable' to use the type. e.g. On x86
679 /// i16 is legal, but undesirable since i16 instruction encodings are longer
680 /// and some i16 instructions are slow.
681 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
684 EmitInstrWithCustomInserter(MachineInstr *MI,
685 MachineBasicBlock *MBB) const override;
688 /// This method returns the name of a target specific DAG node.
689 const char *getTargetNodeName(unsigned Opcode) const override;
691 bool isCheapToSpeculateCttz() const override;
693 bool isCheapToSpeculateCtlz() const override;
695 /// Return the value type to use for ISD::SETCC.
696 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
697 EVT VT) const override;
699 /// Determine which of the bits specified in Mask are known to be either
700 /// zero or one and return them in the KnownZero/KnownOne bitsets.
701 void computeKnownBitsForTargetNode(const SDValue Op,
704 const SelectionDAG &DAG,
705 unsigned Depth = 0) const override;
707 /// Determine the number of bits in the operation that are sign bits.
708 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
709 const SelectionDAG &DAG,
710 unsigned Depth) const override;
712 bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
713 int64_t &Offset) const override;
715 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
717 bool ExpandInlineAsm(CallInst *CI) const override;
719 ConstraintType getConstraintType(StringRef Constraint) const override;
721 /// Examine constraint string and operand type and determine a weight value.
722 /// The operand object must already have been set up with the operand type.
724 getSingleConstraintMatchWeight(AsmOperandInfo &info,
725 const char *constraint) const override;
727 const char *LowerXConstraint(EVT ConstraintVT) const override;
729 /// Lower the specified operand into the Ops vector. If it is invalid, don't
730 /// add anything to Ops. If hasMemory is true it means one of the asm
731 /// constraint of the inline asm instruction being processed is 'm'.
732 void LowerAsmOperandForConstraint(SDValue Op,
733 std::string &Constraint,
734 std::vector<SDValue> &Ops,
735 SelectionDAG &DAG) const override;
738 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
739 if (ConstraintCode == "i")
740 return InlineAsm::Constraint_i;
741 else if (ConstraintCode == "o")
742 return InlineAsm::Constraint_o;
743 else if (ConstraintCode == "v")
744 return InlineAsm::Constraint_v;
745 else if (ConstraintCode == "X")
746 return InlineAsm::Constraint_X;
747 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
750 /// Given a physical register constraint
751 /// (e.g. {edx}), return the register number and the register class for the
752 /// register. This should only be used for C_Register constraints. On
753 /// error, this returns a register number of 0.
754 std::pair<unsigned, const TargetRegisterClass *>
755 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
756 StringRef Constraint, MVT VT) const override;
758 /// Return true if the addressing mode represented
759 /// by AM is legal for this target, for a load/store of the specified type.
760 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
761 Type *Ty, unsigned AS) const override;
763 /// Return true if the specified immediate is legal
764 /// icmp immediate, that is the target has icmp instructions which can
765 /// compare a register against the immediate without having to materialize
766 /// the immediate into a register.
767 bool isLegalICmpImmediate(int64_t Imm) const override;
769 /// Return true if the specified immediate is legal
770 /// add immediate, that is the target has add instructions which can
771 /// add a register and the immediate without having to materialize
772 /// the immediate into a register.
773 bool isLegalAddImmediate(int64_t Imm) const override;
775 /// \brief Return the cost of the scaling factor used in the addressing
776 /// mode represented by AM for this target, for a load/store
777 /// of the specified type.
778 /// If the AM is supported, the return value must be >= 0.
779 /// If the AM is not supported, it returns a negative value.
780 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
781 unsigned AS) const override;
783 bool isVectorShiftByScalarCheap(Type *Ty) const override;
785 /// Return true if it's free to truncate a value of
786 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
787 /// register EAX to i16 by referencing its sub-register AX.
788 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
789 bool isTruncateFree(EVT VT1, EVT VT2) const override;
791 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
793 /// Return true if any actual instruction that defines a
794 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
795 /// register. This does not necessarily include registers defined in
796 /// unknown ways, such as incoming arguments, or copies from unknown
797 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
798 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
799 /// all instructions that define 32-bit values implicit zero-extend the
800 /// result out to 64 bits.
801 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
802 bool isZExtFree(EVT VT1, EVT VT2) const override;
803 bool isZExtFree(SDValue Val, EVT VT2) const override;
805 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
806 /// extend node) is profitable.
807 bool isVectorLoadExtDesirable(SDValue) const override;
809 /// Return true if an FMA operation is faster than a pair of fmul and fadd
810 /// instructions. fmuladd intrinsics will be expanded to FMAs when this
811 /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
812 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
814 /// Return true if it's profitable to narrow
815 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
816 /// from i32 to i8 but not from i32 to i16.
817 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
819 /// Returns true if the target can instruction select the
820 /// specified FP immediate natively. If false, the legalizer will
821 /// materialize the FP immediate as a load from a constant pool.
822 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
824 /// Targets can use this to indicate that they only support *some*
825 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
826 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
828 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
829 EVT VT) const override;
831 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
832 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to
833 /// replace a VAND with a constant pool entry.
834 bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
835 EVT VT) const override;
837 /// If true, then instruction selection should
838 /// seek to shrink the FP constant of the specified type to a smaller type
839 /// in order to save space and / or reduce runtime.
840 bool ShouldShrinkFPConstant(EVT VT) const override {
841 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
842 // expensive than a straight movsd. On the other hand, it's important to
843 // shrink long double fp constant since fldt is very slow.
844 return !X86ScalarSSEf64 || VT == MVT::f80;
847 /// Return true if we believe it is correct and profitable to reduce the
848 /// load node to a smaller type.
849 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
850 EVT NewVT) const override;
852 /// Return true if the specified scalar FP type is computed in an SSE
853 /// register, not on the X87 floating point stack.
854 bool isScalarFPTypeInSSEReg(EVT VT) const {
855 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
856 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
859 /// Return true if the target uses the MSVC _ftol2 routine for fptoui.
860 bool isTargetFTOL() const;
862 /// Return true if the MSVC _ftol2 routine should be used for fptoui to the
864 bool isIntegerTypeFTOL(EVT VT) const {
865 return isTargetFTOL() && VT == MVT::i64;
868 /// \brief Returns true if it is beneficial to convert a load of a constant
869 /// to just the constant itself.
870 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
871 Type *Ty) const override;
873 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
875 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
877 /// Intel processors have a unified instruction and data cache
878 const char * getClearCacheBuiltinName() const override {
879 return nullptr; // nothing to do, move along.
882 unsigned getRegisterByName(const char* RegName, EVT VT,
883 SelectionDAG &DAG) const override;
885 /// This method returns a target specific FastISel object,
886 /// or null if the target does not support "fast" ISel.
887 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
888 const TargetLibraryInfo *libInfo) const override;
890 /// Return true if the target stores stack protector cookies at a fixed
891 /// offset in some non-standard address space, and populates the address
892 /// space and offset as appropriate.
893 bool getStackCookieLocation(unsigned &AddressSpace,
894 unsigned &Offset) const override;
896 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
897 SelectionDAG &DAG) const;
899 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
901 bool useLoadStackGuardNode() const override;
902 /// \brief Customize the preferred legalization strategy for certain types.
903 LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
906 std::pair<const TargetRegisterClass *, uint8_t>
907 findRepresentativeClass(const TargetRegisterInfo *TRI,
908 MVT VT) const override;
911 /// Keep a pointer to the X86Subtarget around so that we can
912 /// make the right decision when generating code for different targets.
913 const X86Subtarget *Subtarget;
914 const DataLayout *TD;
916 /// Select between SSE or x87 floating point ops.
917 /// When SSE is available, use it for f32 operations.
918 /// When SSE2 is available, use it for f64 operations.
919 bool X86ScalarSSEf32;
920 bool X86ScalarSSEf64;
922 /// A list of legal FP immediates.
923 std::vector<APFloat> LegalFPImmediates;
925 /// Indicate that this x86 target can instruction
926 /// select the specified FP immediate natively.
927 void addLegalFPImmediate(const APFloat& Imm) {
928 LegalFPImmediates.push_back(Imm);
931 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
932 CallingConv::ID CallConv, bool isVarArg,
933 const SmallVectorImpl<ISD::InputArg> &Ins,
934 SDLoc dl, SelectionDAG &DAG,
935 SmallVectorImpl<SDValue> &InVals) const;
936 SDValue LowerMemArgument(SDValue Chain,
937 CallingConv::ID CallConv,
938 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
939 SDLoc dl, SelectionDAG &DAG,
940 const CCValAssign &VA, MachineFrameInfo *MFI,
942 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
943 SDLoc dl, SelectionDAG &DAG,
944 const CCValAssign &VA,
945 ISD::ArgFlagsTy Flags) const;
947 // Call lowering helpers.
949 /// Check whether the call is eligible for tail call optimization. Targets
950 /// that want to do tail call optimization should implement this function.
951 bool IsEligibleForTailCallOptimization(SDValue Callee,
952 CallingConv::ID CalleeCC,
954 bool isCalleeStructRet,
955 bool isCallerStructRet,
957 const SmallVectorImpl<ISD::OutputArg> &Outs,
958 const SmallVectorImpl<SDValue> &OutVals,
959 const SmallVectorImpl<ISD::InputArg> &Ins,
960 SelectionDAG& DAG) const;
961 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
962 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
963 SDValue Chain, bool IsTailCall, bool Is64Bit,
964 int FPDiff, SDLoc dl) const;
966 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
967 SelectionDAG &DAG) const;
969 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
971 bool isReplace) const;
973 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
974 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
975 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
976 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
977 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
978 SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const;
979 SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const;
981 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
982 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
983 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
984 SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
985 int64_t Offset, SelectionDAG &DAG) const;
986 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
987 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
988 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
989 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
990 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
991 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
992 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
993 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
994 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
995 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
996 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
997 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
998 SDLoc dl, SelectionDAG &DAG) const;
999 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1000 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
1001 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
1002 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
1003 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1004 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1005 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1006 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1007 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1008 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1009 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1010 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
1011 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1012 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1013 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1014 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1015 SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
1016 SDValue LowerGC_TRANSITION_START(SDValue Op, SelectionDAG &DAG) const;
1017 SDValue LowerGC_TRANSITION_END(SDValue Op, SelectionDAG &DAG) const;
1020 LowerFormalArguments(SDValue Chain,
1021 CallingConv::ID CallConv, bool isVarArg,
1022 const SmallVectorImpl<ISD::InputArg> &Ins,
1023 SDLoc dl, SelectionDAG &DAG,
1024 SmallVectorImpl<SDValue> &InVals) const override;
1025 SDValue LowerCall(CallLoweringInfo &CLI,
1026 SmallVectorImpl<SDValue> &InVals) const override;
1028 SDValue LowerReturn(SDValue Chain,
1029 CallingConv::ID CallConv, bool isVarArg,
1030 const SmallVectorImpl<ISD::OutputArg> &Outs,
1031 const SmallVectorImpl<SDValue> &OutVals,
1032 SDLoc dl, SelectionDAG &DAG) const override;
1034 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1036 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
1038 EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1039 ISD::NodeType ExtendKind) const override;
1041 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1043 const SmallVectorImpl<ISD::OutputArg> &Outs,
1044 LLVMContext &Context) const override;
1046 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1048 bool shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
1049 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
1050 TargetLoweringBase::AtomicRMWExpansionKind
1051 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
1054 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
1056 bool needsCmpXchgNb(Type *MemType) const;
1058 /// Utility function to emit atomic-load-arith operations (and, or, xor,
1059 /// nand, max, min, umax, umin). It takes the corresponding instruction to
1060 /// expand, the associated machine basic block, and the associated X86
1061 /// opcodes for reg/reg.
1062 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
1063 MachineBasicBlock *MBB) const;
1065 /// Utility function to emit atomic-load-arith operations (and, or, xor,
1066 /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
1067 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
1068 MachineBasicBlock *MBB) const;
1070 // Utility function to emit the low-level va_arg code for X86-64.
1071 MachineBasicBlock *EmitVAARG64WithCustomInserter(
1073 MachineBasicBlock *MBB) const;
1075 /// Utility function to emit the xmm reg save portion of va_start.
1076 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
1077 MachineInstr *BInstr,
1078 MachineBasicBlock *BB) const;
1080 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
1081 MachineBasicBlock *BB) const;
1083 MachineBasicBlock *EmitLoweredAtomicFP(MachineInstr *I,
1084 MachineBasicBlock *BB) const;
1086 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
1087 MachineBasicBlock *BB) const;
1089 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
1090 MachineBasicBlock *BB) const;
1092 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
1093 MachineBasicBlock *BB) const;
1095 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
1096 MachineBasicBlock *BB) const;
1098 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
1099 MachineBasicBlock *MBB) const;
1101 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
1102 MachineBasicBlock *MBB) const;
1104 MachineBasicBlock *emitFMA3Instr(MachineInstr *MI,
1105 MachineBasicBlock *MBB) const;
1107 /// Emit nodes that will be selected as "test Op0,Op0", or something
1108 /// equivalent, for use with the given x86 condition code.
1109 SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl,
1110 SelectionDAG &DAG) const;
1112 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
1113 /// equivalent, for use with the given x86 condition code.
1114 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl,
1115 SelectionDAG &DAG) const;
1117 /// Convert a comparison if required by the subtarget.
1118 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
1120 /// Use rsqrt* to speed up sqrt calculations.
1121 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1122 unsigned &RefinementSteps,
1123 bool &UseOneConstNR) const override;
1125 /// Use rcp* to speed up fdiv calculations.
1126 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1127 unsigned &RefinementSteps) const override;
1129 /// Reassociate floating point divisions into multiply by reciprocal.
1130 unsigned combineRepeatedFPDivisors() const override;
1134 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1135 const TargetLibraryInfo *libInfo);
1139 #endif // X86ISELLOWERING_H