1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
24 // X86 Specific DAG Nodes
26 // Start the numbering where the builtin ops leave off.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
29 /// ADD_FLAG, SUB_FLAG - Same as ISD::ADD and ISD::SUB except it also
30 /// produces a flag result.
34 /// ADC, SBB - Add with carry and subtraction with borrow. These
35 /// correspond to X86::ADCxx and X86::SBBxx instructions.
39 /// SHLD, SHRD - Double shift instructions. These correspond to
40 /// X86::SHLDxx and X86::SHRDxx instructions.
44 /// FAND - Bitwise logical AND of floating point values. This corresponds
45 /// to X86::ANDPS or X86::ANDPD.
48 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
49 /// to X86::XORPS or X86::XORPD.
52 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
53 /// integer source in memory and FP reg result. This corresponds to the
54 /// X86::FILD*m instructions. It has three inputs (token chain, address,
55 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
56 /// also produces a flag).
60 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
61 /// integer destination in memory and a FP reg source. This corresponds
62 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
63 /// has two inputs (token chain and address) and two outputs (int value and
69 /// FLD - This instruction implements an extending load to FP stack slots.
70 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
71 /// operand, ptr to load from, and a ValueType node indicating the type
75 /// FST - This instruction implements a truncating store to FP stack
76 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
77 /// chain operand, value to store, address, and a ValueType to store it
81 /// FP_SET_RESULT - This corresponds to FpGETRESULT pseudo instrcuction
82 /// which copies from ST(0) to the destination. It takes a chain and writes
83 /// a RFP result and a chain.
86 /// FP_SET_RESULT - This corresponds to FpSETRESULT pseudo instrcuction
87 /// which copies the source operand to ST(0). It takes a chain and writes
88 /// a chain and a flag.
91 /// CALL/TAILCALL - These operations represent an abstract X86 call
92 /// instruction, which includes a bunch of information. In particular the
93 /// operands of these node are:
95 /// #0 - The incoming token chain
97 /// #2 - The number of arg bytes the caller pushes on the stack.
98 /// #3 - The number of arg bytes the callee pops off the stack.
99 /// #4 - The value to pass in AL/AX/EAX (optional)
100 /// #5 - The value to pass in DL/DX/EDX (optional)
102 /// The result values of these nodes are:
104 /// #0 - The outgoing token chain
105 /// #1 - The first register result value (optional)
106 /// #2 - The second register result value (optional)
108 /// The CALL vs TAILCALL distinction boils down to whether the callee is
109 /// known not to modify the caller's stack frame, as is standard with
114 /// RDTSC_DAG - This operation implements the lowering for
118 /// X86 compare and logical compare instructions.
121 /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
122 /// operand produced by a CMP instruction.
125 /// X86 conditional moves. Operand 1 and operand 2 are the two values
126 /// to select from (operand 1 is a R/W operand). Operand 3 is the condition
127 /// code, and operand 4 is the flag operand produced by a CMP or TEST
128 /// instruction. It also writes a flag result.
131 /// X86 conditional branches. Operand 1 is the chain operand, operand 2
132 /// is the block to branch if condition is true, operand 3 is the
133 /// condition code, and operand 4 is the flag operand produced by a CMP
134 /// or TEST instruction.
137 /// Return with a flag operand. Operand 1 is the chain operand, operand
138 /// 2 is the number of bytes of stack to pop.
141 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
144 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
147 /// LOAD_PACK Load a 128-bit packed float / double value. It has the same
148 /// operands as a normal load.
152 // X86 specific condition code. These correspond to X86_*_COND in
153 // X86InstrInfo.td. They must be kept in synch.
175 //===----------------------------------------------------------------------===//
176 // X86TargetLowering - X86 Implementation of the TargetLowering interface
177 class X86TargetLowering : public TargetLowering {
178 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
179 int ReturnAddrIndex; // FrameIndex for return slot.
180 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
181 int BytesCallerReserves; // Number of arg bytes caller makes.
183 X86TargetLowering(TargetMachine &TM);
185 // Return the number of bytes that a function should pop when it returns (in
186 // addition to the space used by the return address).
188 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
190 // Return the number of bytes that the caller reserves for arguments passed
192 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
194 /// LowerOperation - Provide custom lowering hooks for some operations.
196 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
198 /// LowerArguments - This hook must be implemented to indicate how we should
199 /// lower the arguments for the specified function, into the specified DAG.
200 virtual std::vector<SDOperand>
201 LowerArguments(Function &F, SelectionDAG &DAG);
203 /// LowerCallTo - This hook lowers an abstract call to a function into an
205 virtual std::pair<SDOperand, SDOperand>
206 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
207 bool isTailCall, SDOperand Callee, ArgListTy &Args,
210 virtual std::pair<SDOperand, SDOperand>
211 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
214 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
215 MachineBasicBlock *MBB);
217 /// getTargetNodeName - This method returns the name of a target specific
219 virtual const char *getTargetNodeName(unsigned Opcode) const;
221 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
222 /// be zero. Op is expected to be a target specific node. Used by DAG
224 virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op,
225 uint64_t Mask) const;
227 SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
229 std::vector<unsigned>
230 getRegForInlineAsmConstraint(const std::string &Constraint) const;
232 // C Calling Convention implementation.
233 std::vector<SDOperand> LowerCCCArguments(Function &F, SelectionDAG &DAG);
234 std::pair<SDOperand, SDOperand>
235 LowerCCCCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
237 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
239 // Fast Calling Convention implementation.
240 std::vector<SDOperand> LowerFastCCArguments(Function &F, SelectionDAG &DAG);
241 std::pair<SDOperand, SDOperand>
242 LowerFastCCCallTo(SDOperand Chain, const Type *RetTy, bool isTailCall,
243 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
245 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
246 /// make the right decision when generating code for different targets.
247 const X86Subtarget *Subtarget;
249 /// X86ScalarSSE - Select between SSE2 or x87 floating point ops.
254 #endif // X86ISELLOWERING_H