1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
24 // X86 Specific DAG Nodes
26 // Start the numbering where the builtin ops leave off.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
29 /// SHLD, SHRD - Double shift instructions. These correspond to
30 /// X86::SHLDxx and X86::SHRDxx instructions.
34 /// FAND - Bitwise logical AND of floating point values. This corresponds
35 /// to X86::ANDPS or X86::ANDPD.
38 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
39 /// to X86::XORPS or X86::XORPD.
42 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
43 /// integer source in memory and FP reg result. This corresponds to the
44 /// X86::FILD*m instructions. It has three inputs (token chain, address,
45 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
46 /// also produces a flag).
50 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
51 /// integer destination in memory and a FP reg source. This corresponds
52 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
53 /// has two inputs (token chain and address) and two outputs (int value and
59 /// FLD - This instruction implements an extending load to FP stack slots.
60 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
61 /// operand, ptr to load from, and a ValueType node indicating the type
65 /// FST - This instruction implements a truncating store to FP stack
66 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
67 /// chain operand, value to store, address, and a ValueType to store it
71 /// FP_SET_RESULT - This corresponds to FpGETRESULT pseudo instrcuction
72 /// which copies from ST(0) to the destination. It takes a chain and writes
73 /// a RFP result and a chain.
76 /// FP_SET_RESULT - This corresponds to FpSETRESULT pseudo instrcuction
77 /// which copies the source operand to ST(0). It takes a chain and writes
78 /// a chain and a flag.
81 /// CALL/TAILCALL - These operations represent an abstract X86 call
82 /// instruction, which includes a bunch of information. In particular the
83 /// operands of these node are:
85 /// #0 - The incoming token chain
87 /// #2 - The number of arg bytes the caller pushes on the stack.
88 /// #3 - The number of arg bytes the callee pops off the stack.
89 /// #4 - The value to pass in AL/AX/EAX (optional)
90 /// #5 - The value to pass in DL/DX/EDX (optional)
92 /// The result values of these nodes are:
94 /// #0 - The outgoing token chain
95 /// #1 - The first register result value (optional)
96 /// #2 - The second register result value (optional)
98 /// The CALL vs TAILCALL distinction boils down to whether the callee is
99 /// known not to modify the caller's stack frame, as is standard with
104 /// RDTSC_DAG - This operation implements the lowering for
108 /// X86 compare and logical compare instructions.
109 CMP, TEST, COMI, UCOMI,
111 /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
112 /// operand produced by a CMP instruction.
115 /// X86 conditional moves. Operand 1 and operand 2 are the two values
116 /// to select from (operand 1 is a R/W operand). Operand 3 is the condition
117 /// code, and operand 4 is the flag operand produced by a CMP or TEST
118 /// instruction. It also writes a flag result.
121 /// X86 conditional branches. Operand 1 is the chain operand, operand 2
122 /// is the block to branch if condition is true, operand 3 is the
123 /// condition code, and operand 4 is the flag operand produced by a CMP
124 /// or TEST instruction.
127 /// Return with a flag operand. Operand 1 is the chain operand, operand
128 /// 2 is the number of bytes of stack to pop.
131 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
134 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
137 /// LOAD_PACK Load a 128-bit packed float / double value. It has the same
138 /// operands as a normal load.
141 /// LOAD_UA Load an unaligned 128-bit value. It has the same operands as
145 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
146 /// at function entry, used for PIC code.
149 /// TCPWrapper - A wrapper node for TargetConstantPool,
150 /// TargetExternalSymbol, and TargetGlobalAddress.
153 /// S2VEC - X86 version of SCALAR_TO_VECTOR. The destination base does not
154 /// have to match the operand type.
157 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
158 /// i32, corresponds to X86::PEXTRW.
161 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
162 /// corresponds to X86::PINSRW.
166 // X86 specific condition code. These correspond to X86_*_COND in
167 // X86InstrInfo.td. They must be kept in synch.
189 /// Define some predicates that are used for node matching.
191 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
192 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
193 bool isPSHUFDMask(SDNode *N);
195 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
196 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
197 bool isPSHUFHWMask(SDNode *N);
199 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
200 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
201 bool isPSHUFLWMask(SDNode *N);
203 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
204 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
205 bool isSHUFPMask(SDNode *N);
207 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
208 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
209 bool isMOVHLPSMask(SDNode *N);
211 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
212 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
213 bool isMOVLPMask(SDNode *N);
215 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
216 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
217 /// as well as MOVLHPS.
218 bool isMOVHPMask(SDNode *N);
220 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
221 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
222 bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false);
224 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
225 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
226 bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false);
228 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
229 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
231 bool isUNPCKL_v_undef_Mask(SDNode *N);
233 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
234 /// specifies a shuffle of elements that is suitable for input to MOVSS,
235 /// MOVSD, and MOVD, i.e. setting the lowest element.
236 bool isMOVLMask(SDNode *N);
238 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
239 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
240 bool isMOVSHDUPMask(SDNode *N);
242 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
243 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
244 bool isMOVSLDUPMask(SDNode *N);
246 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
247 /// specifies a splat of a single element.
248 bool isSplatMask(SDNode *N);
250 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
251 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
253 unsigned getShuffleSHUFImmediate(SDNode *N);
255 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
256 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
258 unsigned getShufflePSHUFHWImmediate(SDNode *N);
260 /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
261 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
263 unsigned getShufflePSHUFLWImmediate(SDNode *N);
266 //===----------------------------------------------------------------------===//
267 // X86TargetLowering - X86 Implementation of the TargetLowering interface
268 class X86TargetLowering : public TargetLowering {
269 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
270 int RegSaveFrameIndex; // X86-64 vararg func register save area.
271 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
272 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
273 int ReturnAddrIndex; // FrameIndex for return slot.
274 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
275 int BytesCallerReserves; // Number of arg bytes caller makes.
277 X86TargetLowering(TargetMachine &TM);
279 // Return the number of bytes that a function should pop when it returns (in
280 // addition to the space used by the return address).
282 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
284 // Return the number of bytes that the caller reserves for arguments passed
286 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
288 /// LowerOperation - Provide custom lowering hooks for some operations.
290 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
292 virtual std::pair<SDOperand, SDOperand>
293 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
296 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
298 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
299 MachineBasicBlock *MBB);
301 /// getTargetNodeName - This method returns the name of a target specific
303 virtual const char *getTargetNodeName(unsigned Opcode) const;
305 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
306 /// in Mask are known to be either zero or one and return them in the
307 /// KnownZero/KnownOne bitsets.
308 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
312 unsigned Depth = 0) const;
314 SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
316 ConstraintType getConstraintType(char ConstraintLetter) const;
318 std::vector<unsigned>
319 getRegClassForInlineAsmConstraint(const std::string &Constraint,
320 MVT::ValueType VT) const;
322 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
323 /// {edx}), return the register number and the register class for the
324 /// register. This should only be used for C_Register constraints. On error,
325 /// this returns a register number of 0.
326 std::pair<unsigned, const TargetRegisterClass*>
327 getRegForInlineAsmConstraint(const std::string &Constraint,
328 MVT::ValueType VT) const;
330 /// isLegalAddressImmediate - Return true if the integer value or
331 /// GlobalValue can be used as the offset of the target addressing mode.
332 virtual bool isLegalAddressImmediate(int64_t V) const;
333 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
335 /// isShuffleMaskLegal - Targets can use this to indicate that they only
336 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
337 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
338 /// are assumed to be legal.
339 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
341 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
342 /// used by Targets can use this to indicate if there is a suitable
343 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
345 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
347 SelectionDAG &DAG) const;
349 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
350 /// make the right decision when generating code for different targets.
351 const X86Subtarget *Subtarget;
353 /// X86StackPtr - X86 physical register used as stack ptr.
354 unsigned X86StackPtr;
356 /// X86ScalarSSE - Select between SSE2 or x87 floating point ops.
359 // C Calling Convention implementation.
360 SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG);
361 SDOperand LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG);
363 // X86-64 C Calling Convention implementation.
364 SDOperand LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG);
365 SDOperand LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG);
367 // Fast Calling Convention implementation.
368 SDOperand LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG);
369 SDOperand LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
372 // StdCall Calling Convention implementation.
373 SDOperand LowerStdCallCCArguments(SDOperand Op, SelectionDAG &DAG);
374 SDOperand LowerStdCallCCCallTo(SDOperand Op, SelectionDAG &DAG);
376 // FastCall Calling Convention implementation.
377 SDOperand LowerFastCallCCArguments(SDOperand Op, SelectionDAG &DAG);
379 SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
380 SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
381 SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
382 SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
383 SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
384 SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
385 SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
386 SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG);
387 SDOperand LowerShift(SDOperand Op, SelectionDAG &DAG);
388 SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
389 SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
390 SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
391 SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
392 SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG, SDOperand Chain);
393 SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
394 SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
395 SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
396 SDOperand LowerMEMCPY(SDOperand Op, SelectionDAG &DAG);
397 SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
398 SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
399 SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
400 SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
401 SDOperand LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG);
402 SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
403 SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
407 // FASTCC_NUM_INT_ARGS_INREGS - This is the max number of integer arguments
408 // to pass in registers. 0 is none, 1 is is "use EAX", 2 is "use EAX and
409 // EDX". Anything more is illegal.
411 // FIXME: The linscan register allocator currently has problem with
412 // coalescing. At the time of this writing, whenever it decides to coalesce
413 // a physreg with a virtreg, this increases the size of the physreg's live
414 // range, and the live range cannot ever be reduced. This causes problems if
415 // too many physregs are coaleced with virtregs, which can cause the register
416 // allocator to wedge itself.
418 // This code triggers this problem more often if we pass args in registers,
419 // so disable it until this is fixed.
421 #define FASTCC_NUM_INT_ARGS_INREGS 0
423 #endif // X86ISELLOWERING_H