1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
29 // X86 Specific DAG Nodes
31 // Start the numbering where the builtin ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 /// BSF - Bit scan forward.
35 /// BSR - Bit scan reverse.
39 /// SHLD, SHRD - Double shift instructions. These correspond to
40 /// X86::SHLDxx and X86::SHRDxx instructions.
44 /// FAND - Bitwise logical AND of floating point values. This corresponds
45 /// to X86::ANDPS or X86::ANDPD.
48 /// FOR - Bitwise logical OR of floating point values. This corresponds
49 /// to X86::ORPS or X86::ORPD.
52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
53 /// to X86::XORPS or X86::XORPD.
56 /// FSRL - Bitwise logical right shift of floating point values. These
57 /// corresponds to X86::PSRLDQ.
60 /// CALL - These operations represent an abstract X86 call
61 /// instruction, which includes a bunch of information. In particular the
62 /// operands of these node are:
64 /// #0 - The incoming token chain
66 /// #2 - The number of arg bytes the caller pushes on the stack.
67 /// #3 - The number of arg bytes the callee pops off the stack.
68 /// #4 - The value to pass in AL/AX/EAX (optional)
69 /// #5 - The value to pass in DL/DX/EDX (optional)
71 /// The result values of these nodes are:
73 /// #0 - The outgoing token chain
74 /// #1 - The first register result value (optional)
75 /// #2 - The second register result value (optional)
79 /// RDTSC_DAG - This operation implements the lowering for
83 /// X86 compare and logical compare instructions.
86 /// X86 bit-test instructions.
89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
90 /// operand, usually produced by a CMP instruction.
93 // Same as SETCC except it's materialized with a sbb and the value is all
94 // one's or all zero's.
95 SETCC_CARRY, // R = carry_bit ? ~0 : 0
97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
98 /// Operands are two FP values to compare; result is a mask of
99 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
102 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
103 /// result in an integer GPR. Needs masking for scalar result.
106 /// X86 conditional moves. Operand 0 and operand 1 are the two values
107 /// to select from. Operand 2 is the condition code, and operand 3 is the
108 /// flag operand produced by a CMP or TEST instruction. It also writes a
112 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
113 /// is the block to branch if condition is true, operand 2 is the
114 /// condition code, and operand 3 is the flag operand produced by a CMP
115 /// or TEST instruction.
118 /// Return with a flag operand. Operand 0 is the chain operand, operand
119 /// 1 is the number of bytes of stack to pop.
122 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
125 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
128 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
129 /// at function entry, used for PIC code.
132 /// Wrapper - A wrapper node for TargetConstantPool,
133 /// TargetExternalSymbol, and TargetGlobalAddress.
136 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
137 /// relative displacements.
140 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
141 /// to an MMX vector. If you think this is too close to the previous
142 /// mnemonic, so do I; blame Intel.
145 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
146 /// i32, corresponds to X86::PEXTRB.
149 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
150 /// i32, corresponds to X86::PEXTRW.
153 /// INSERTPS - Insert any element of a 4 x float vector into any element
154 /// of a destination 4 x floatvector.
157 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
158 /// corresponds to X86::PINSRB.
161 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
162 /// corresponds to X86::PINSRW.
165 /// PSHUFB - Shuffle 16 8-bit values within a vector.
168 /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
171 /// PSIGN - Copy integer sign.
174 /// BLENDV - Blend where the selector is an XMM.
177 /// BLENDxx - Blend where the selector is an immediate.
182 /// HADD - Integer horizontal add.
185 /// HSUB - Integer horizontal sub.
188 /// FHADD - Floating point horizontal add.
191 /// FHSUB - Floating point horizontal sub.
194 /// FMAX, FMIN - Floating point max and min.
198 /// FMAXC, FMINC - Commutative FMIN and FMAX.
201 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
202 /// approximation. Note that these typically require refinement
203 /// in order to obtain suitable precision.
206 // TLSADDR - Thread Local Storage.
209 // TLSBASEADDR - Thread Local Storage. A call to get the start address
210 // of the TLS block for the current module.
213 // TLSCALL - Thread Local Storage. When calling to an OS provided
214 // thunk at the address from an earlier relocation.
217 // EH_RETURN - Exception Handling helpers.
220 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
223 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
226 /// TC_RETURN - Tail call return.
228 /// operand #1 callee (register or absolute)
229 /// operand #2 stack adjustment
230 /// operand #3 optional in flag
233 // VZEXT_MOVL - Vector move low and zero extend.
236 // VSEXT_MOVL - Vector move low and sign extend.
239 // VFPEXT - Vector FP extend.
242 // VFPROUND - Vector FP round.
245 // VSHL, VSRL - 128-bit vector logical left / right shift
248 // VSHL, VSRL, VSRA - Vector shift elements
251 // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate
254 // CMPP - Vector packed double/float comparison.
257 // PCMP* - Vector integer comparisons.
260 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
261 ADD, SUB, ADC, SBB, SMUL,
262 INC, DEC, OR, XOR, AND,
264 ANDN, // ANDN - Bitwise AND NOT with FLAGS results.
266 BLSI, // BLSI - Extract lowest set isolated bit
267 BLSMSK, // BLSMSK - Get mask up to lowest set bit
268 BLSR, // BLSR - Reset lowest set bit
270 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
272 // MUL_IMM - X86 specific multiply by immediate.
275 // PTEST - Vector bitwise comparisons
278 // TESTP - Vector packed fp sign bitwise comparisons
281 // Several flavors of instructions with vector shuffle behaviors.
305 // PMULUDQ - Vector multiply packed unsigned doubleword integers
316 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
317 // according to %al. An operator is needed so that this can be expanded
318 // with control flow.
319 VASTART_SAVE_XMM_REGS,
321 // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
324 // SEG_ALLOCA - For allocating variable amounts of stack space when using
325 // segmented stacks. Check if the current stacklet has enough space, and
326 // falls back to heap allocation if not.
329 // WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui.
338 // FNSTSW16r - Store FP status word into i16 register.
341 // SAHF - Store contents of %ah into %eflags.
344 // RDRAND - Get a random integer and indicate whether it is valid in CF.
351 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
352 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
353 // Atomic 64-bit binary operations.
354 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
366 // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
371 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
374 // FNSTCW16m - Store FP control world into i16 memory.
377 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
378 /// integer destination in memory and a FP reg source. This corresponds
379 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
380 /// has two inputs (token chain and address) and two outputs (int value
381 /// and token chain).
386 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
387 /// integer source in memory and FP reg result. This corresponds to the
388 /// X86::FILD*m instructions. It has three inputs (token chain, address,
389 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
390 /// also produces a flag).
394 /// FLD - This instruction implements an extending load to FP stack slots.
395 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
396 /// operand, ptr to load from, and a ValueType node indicating the type
400 /// FST - This instruction implements a truncating store to FP stack
401 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
402 /// chain operand, value to store, address, and a ValueType to store it
406 /// VAARG_64 - This instruction grabs the address of the next argument
407 /// from a va_list. (reads and modifies the va_list in memory)
410 // WARNING: Do not add anything in the end unless you want the node to
411 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
412 // thought as target memory ops!
416 /// Define some predicates that are used for node matching.
418 /// isVEXTRACTF128Index - Return true if the specified
419 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
420 /// suitable for input to VEXTRACTF128.
421 bool isVEXTRACTF128Index(SDNode *N);
423 /// isVINSERTF128Index - Return true if the specified
424 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
425 /// suitable for input to VINSERTF128.
426 bool isVINSERTF128Index(SDNode *N);
428 /// getExtractVEXTRACTF128Immediate - Return the appropriate
429 /// immediate to extract the specified EXTRACT_SUBVECTOR index
430 /// with VEXTRACTF128 instructions.
431 unsigned getExtractVEXTRACTF128Immediate(SDNode *N);
433 /// getInsertVINSERTF128Immediate - Return the appropriate
434 /// immediate to insert at the specified INSERT_SUBVECTOR index
435 /// with VINSERTF128 instructions.
436 unsigned getInsertVINSERTF128Immediate(SDNode *N);
438 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
440 bool isZeroNode(SDValue Elt);
442 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
443 /// fit into displacement field of the instruction.
444 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
445 bool hasSymbolicDisplacement = true);
448 /// isCalleePop - Determines whether the callee is required to pop its
449 /// own arguments. Callee pop is necessary to support tail calls.
450 bool isCalleePop(CallingConv::ID CallingConv,
451 bool is64Bit, bool IsVarArg, bool TailCallOpt);
454 //===--------------------------------------------------------------------===//
455 // X86TargetLowering - X86 Implementation of the TargetLowering interface
456 class X86TargetLowering : public TargetLowering {
458 explicit X86TargetLowering(X86TargetMachine &TM);
460 virtual unsigned getJumpTableEncoding() const;
462 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
464 virtual const MCExpr *
465 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
466 const MachineBasicBlock *MBB, unsigned uid,
467 MCContext &Ctx) const;
469 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
471 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
472 SelectionDAG &DAG) const;
473 virtual const MCExpr *
474 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
475 unsigned JTI, MCContext &Ctx) const;
477 /// getStackPtrReg - Return the stack pointer register we are using: either
479 unsigned getStackPtrReg() const { return X86StackPtr; }
481 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
482 /// function arguments in the caller parameter area. For X86, aggregates
483 /// that contains are placed at 16-byte boundaries while the rest are at
484 /// 4-byte boundaries.
485 virtual unsigned getByValTypeAlignment(Type *Ty) const;
487 /// getOptimalMemOpType - Returns the target specific optimal type for load
488 /// and store operations as a result of memset, memcpy, and memmove
489 /// lowering. If DstAlign is zero that means it's safe to destination
490 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
491 /// means there isn't a need to check it against alignment requirement,
492 /// probably because the source does not need to be loaded. If
493 /// 'IsZeroVal' is true, that means it's safe to return a
494 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
495 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
496 /// constant so it does not need to be loaded.
497 /// It returns EVT::Other if the type should be determined using generic
498 /// target-independent logic.
500 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
501 bool IsZeroVal, bool MemcpyStrSrc,
502 MachineFunction &MF) const;
504 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
505 /// unaligned memory accesses. of the specified type.
506 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
510 /// LowerOperation - Provide custom lowering hooks for some operations.
512 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
514 /// ReplaceNodeResults - Replace the results of node with an illegal result
515 /// type with new values built out of custom code.
517 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
518 SelectionDAG &DAG) const;
521 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
523 /// isTypeDesirableForOp - Return true if the target has native support for
524 /// the specified value type and it is 'desirable' to use the type for the
525 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
526 /// instruction encodings are longer and some i16 instructions are slow.
527 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
529 /// isTypeDesirable - Return true if the target has native support for the
530 /// specified value type and it is 'desirable' to use the type. e.g. On x86
531 /// i16 is legal, but undesirable since i16 instruction encodings are longer
532 /// and some i16 instructions are slow.
533 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
535 virtual MachineBasicBlock *
536 EmitInstrWithCustomInserter(MachineInstr *MI,
537 MachineBasicBlock *MBB) const;
540 /// getTargetNodeName - This method returns the name of a target specific
542 virtual const char *getTargetNodeName(unsigned Opcode) const;
544 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
545 virtual EVT getSetCCResultType(EVT VT) const;
547 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
548 /// in Mask are known to be either zero or one and return them in the
549 /// KnownZero/KnownOne bitsets.
550 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
553 const SelectionDAG &DAG,
554 unsigned Depth = 0) const;
556 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
557 // operation that are sign bits.
558 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
559 unsigned Depth) const;
562 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
564 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
566 virtual bool ExpandInlineAsm(CallInst *CI) const;
568 ConstraintType getConstraintType(const std::string &Constraint) const;
570 /// Examine constraint string and operand type and determine a weight value.
571 /// The operand object must already have been set up with the operand type.
572 virtual ConstraintWeight getSingleConstraintMatchWeight(
573 AsmOperandInfo &info, const char *constraint) const;
575 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
577 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
578 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
579 /// true it means one of the asm constraint of the inline asm instruction
580 /// being processed is 'm'.
581 virtual void LowerAsmOperandForConstraint(SDValue Op,
582 std::string &Constraint,
583 std::vector<SDValue> &Ops,
584 SelectionDAG &DAG) const;
586 /// getRegForInlineAsmConstraint - Given a physical register constraint
587 /// (e.g. {edx}), return the register number and the register class for the
588 /// register. This should only be used for C_Register constraints. On
589 /// error, this returns a register number of 0.
590 std::pair<unsigned, const TargetRegisterClass*>
591 getRegForInlineAsmConstraint(const std::string &Constraint,
594 /// isLegalAddressingMode - Return true if the addressing mode represented
595 /// by AM is legal for this target, for a load/store of the specified type.
596 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
598 /// isLegalICmpImmediate - Return true if the specified immediate is legal
599 /// icmp immediate, that is the target has icmp instructions which can
600 /// compare a register against the immediate without having to materialize
601 /// the immediate into a register.
602 virtual bool isLegalICmpImmediate(int64_t Imm) const;
604 /// isLegalAddImmediate - Return true if the specified immediate is legal
605 /// add immediate, that is the target has add instructions which can
606 /// add a register and the immediate without having to materialize
607 /// the immediate into a register.
608 virtual bool isLegalAddImmediate(int64_t Imm) const;
610 /// isTruncateFree - Return true if it's free to truncate a value of
611 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
612 /// register EAX to i16 by referencing its sub-register AX.
613 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
614 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
616 /// isZExtFree - Return true if any actual instruction that defines a
617 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
618 /// register. This does not necessarily include registers defined in
619 /// unknown ways, such as incoming arguments, or copies from unknown
620 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
621 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
622 /// all instructions that define 32-bit values implicit zero-extend the
623 /// result out to 64 bits.
624 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
625 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
627 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
628 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
629 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
630 /// is expanded to mul + add.
631 virtual bool isFMAFasterThanMulAndAdd(EVT) const { return true; }
633 /// isNarrowingProfitable - Return true if it's profitable to narrow
634 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
635 /// from i32 to i8 but not from i32 to i16.
636 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
638 /// isFPImmLegal - Returns true if the target can instruction select the
639 /// specified FP immediate natively. If false, the legalizer will
640 /// materialize the FP immediate as a load from a constant pool.
641 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
643 /// isShuffleMaskLegal - Targets can use this to indicate that they only
644 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
645 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
646 /// values are assumed to be legal.
647 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
650 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
651 /// used by Targets can use this to indicate if there is a suitable
652 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
654 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
657 /// ShouldShrinkFPConstant - If true, then instruction selection should
658 /// seek to shrink the FP constant of the specified type to a smaller type
659 /// in order to save space and / or reduce runtime.
660 virtual bool ShouldShrinkFPConstant(EVT VT) const {
661 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
662 // expensive than a straight movsd. On the other hand, it's important to
663 // shrink long double fp constant since fldt is very slow.
664 return !X86ScalarSSEf64 || VT == MVT::f80;
667 const X86Subtarget* getSubtarget() const {
671 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
672 /// computed in an SSE register, not on the X87 floating point stack.
673 bool isScalarFPTypeInSSEReg(EVT VT) const {
674 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
675 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
678 /// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine
680 bool isTargetFTOL() const {
681 return Subtarget->isTargetWindows() && !Subtarget->is64Bit();
684 /// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be
685 /// used for fptoui to the given type.
686 bool isIntegerTypeFTOL(EVT VT) const {
687 return isTargetFTOL() && VT == MVT::i64;
690 /// createFastISel - This method returns a target specific FastISel object,
691 /// or null if the target does not support "fast" ISel.
692 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
693 const TargetLibraryInfo *libInfo) const;
695 /// getStackCookieLocation - Return true if the target stores stack
696 /// protector cookies at a fixed offset in some non-standard address
697 /// space, and populates the address space and offset as
699 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
701 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
702 SelectionDAG &DAG) const;
705 std::pair<const TargetRegisterClass*, uint8_t>
706 findRepresentativeClass(EVT VT) const;
709 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
710 /// make the right decision when generating code for different targets.
711 const X86Subtarget *Subtarget;
712 const X86RegisterInfo *RegInfo;
713 const DataLayout *TD;
715 /// X86StackPtr - X86 physical register used as stack ptr.
716 unsigned X86StackPtr;
718 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
719 /// floating point ops.
720 /// When SSE is available, use it for f32 operations.
721 /// When SSE2 is available, use it for f64 operations.
722 bool X86ScalarSSEf32;
723 bool X86ScalarSSEf64;
725 /// LegalFPImmediates - A list of legal fp immediates.
726 std::vector<APFloat> LegalFPImmediates;
728 /// addLegalFPImmediate - Indicate that this x86 target can instruction
729 /// select the specified FP immediate natively.
730 void addLegalFPImmediate(const APFloat& Imm) {
731 LegalFPImmediates.push_back(Imm);
734 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
735 CallingConv::ID CallConv, bool isVarArg,
736 const SmallVectorImpl<ISD::InputArg> &Ins,
737 DebugLoc dl, SelectionDAG &DAG,
738 SmallVectorImpl<SDValue> &InVals) const;
739 SDValue LowerMemArgument(SDValue Chain,
740 CallingConv::ID CallConv,
741 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
742 DebugLoc dl, SelectionDAG &DAG,
743 const CCValAssign &VA, MachineFrameInfo *MFI,
745 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
746 DebugLoc dl, SelectionDAG &DAG,
747 const CCValAssign &VA,
748 ISD::ArgFlagsTy Flags) const;
750 // Call lowering helpers.
752 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
753 /// for tail call optimization. Targets which want to do tail call
754 /// optimization should implement this function.
755 bool IsEligibleForTailCallOptimization(SDValue Callee,
756 CallingConv::ID CalleeCC,
758 bool isCalleeStructRet,
759 bool isCallerStructRet,
761 const SmallVectorImpl<ISD::OutputArg> &Outs,
762 const SmallVectorImpl<SDValue> &OutVals,
763 const SmallVectorImpl<ISD::InputArg> &Ins,
764 SelectionDAG& DAG) const;
765 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
766 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
767 SDValue Chain, bool IsTailCall, bool Is64Bit,
768 int FPDiff, DebugLoc dl) const;
770 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
771 SelectionDAG &DAG) const;
773 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
775 bool isReplace) const;
777 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
778 SelectionDAG &DAG) const;
779 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
780 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
781 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
782 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
783 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
784 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
785 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
786 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
787 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
788 int64_t Offset, SelectionDAG &DAG) const;
789 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
790 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
791 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
792 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
793 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const;
794 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
795 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
796 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
797 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
798 SDValue lowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
799 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
800 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
801 SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
802 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
803 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
804 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
805 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
806 DebugLoc dl, SelectionDAG &DAG) const;
807 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
808 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
809 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
810 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
811 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
812 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
813 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
814 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
815 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
816 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
817 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
818 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
819 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
820 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
821 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
822 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
823 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
824 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
826 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
828 // Utility functions to help LowerVECTOR_SHUFFLE
829 SDValue LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const;
830 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const;
832 SDValue LowerVectorAllZeroTest(SDValue Op, SelectionDAG &DAG) const;
835 LowerFormalArguments(SDValue Chain,
836 CallingConv::ID CallConv, bool isVarArg,
837 const SmallVectorImpl<ISD::InputArg> &Ins,
838 DebugLoc dl, SelectionDAG &DAG,
839 SmallVectorImpl<SDValue> &InVals) const;
841 LowerCall(CallLoweringInfo &CLI,
842 SmallVectorImpl<SDValue> &InVals) const;
845 LowerReturn(SDValue Chain,
846 CallingConv::ID CallConv, bool isVarArg,
847 const SmallVectorImpl<ISD::OutputArg> &Outs,
848 const SmallVectorImpl<SDValue> &OutVals,
849 DebugLoc dl, SelectionDAG &DAG) const;
851 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
853 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
856 getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
857 ISD::NodeType ExtendKind) const;
860 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
862 const SmallVectorImpl<ISD::OutputArg> &Outs,
863 LLVMContext &Context) const;
865 /// Utility function to emit string processing sse4.2 instructions
866 /// that return in xmm0.
867 /// This takes the instruction to expand, the associated machine basic
868 /// block, the number of args, and whether or not the second arg is
869 /// in memory or not.
870 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
871 unsigned argNum, bool inMem) const;
873 /// Utility functions to emit monitor and mwait instructions. These
874 /// need to make sure that the arguments to the intrinsic are in the
875 /// correct registers.
876 MachineBasicBlock *EmitMonitor(MachineInstr *MI,
877 MachineBasicBlock *BB) const;
878 MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const;
880 /// Utility function to emit atomic-load-arith operations (and, or, xor,
881 /// nand, max, min, umax, umin). It takes the corresponding instruction to
882 /// expand, the associated machine basic block, and the associated X86
883 /// opcodes for reg/reg.
884 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
885 MachineBasicBlock *MBB) const;
887 /// Utility function to emit atomic-load-arith operations (and, or, xor,
888 /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
889 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
890 MachineBasicBlock *MBB) const;
892 // Utility function to emit the low-level va_arg code for X86-64.
893 MachineBasicBlock *EmitVAARG64WithCustomInserter(
895 MachineBasicBlock *MBB) const;
897 /// Utility function to emit the xmm reg save portion of va_start.
898 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
899 MachineInstr *BInstr,
900 MachineBasicBlock *BB) const;
902 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
903 MachineBasicBlock *BB) const;
905 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
906 MachineBasicBlock *BB) const;
908 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
909 MachineBasicBlock *BB,
912 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
913 MachineBasicBlock *BB) const;
915 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
916 MachineBasicBlock *BB) const;
918 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
919 MachineBasicBlock *MBB) const;
921 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
922 MachineBasicBlock *MBB) const;
924 /// Emit nodes that will be selected as "test Op0,Op0", or something
925 /// equivalent, for use with the given x86 condition code.
926 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
928 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
929 /// equivalent, for use with the given x86 condition code.
930 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
931 SelectionDAG &DAG) const;
933 /// Convert a comparison if required by the subtarget.
934 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
938 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
939 const TargetLibraryInfo *libInfo);
943 #endif // X86ISELLOWERING_H