1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
24 // X86 Specific DAG Nodes
26 // Start the numbering where the builtin ops leave off.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
29 /// SHLD, SHRD - Double shift instructions. These correspond to
30 /// X86::SHLDxx and X86::SHRDxx instructions.
34 /// FAND - Bitwise logical AND of floating point values. This corresponds
35 /// to X86::ANDPS or X86::ANDPD.
38 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
39 /// to X86::XORPS or X86::XORPD.
42 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
43 /// integer source in memory and FP reg result. This corresponds to the
44 /// X86::FILD*m instructions. It has three inputs (token chain, address,
45 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
46 /// also produces a flag).
50 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
51 /// integer destination in memory and a FP reg source. This corresponds
52 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
53 /// has two inputs (token chain and address) and two outputs (int value
59 /// FLD - This instruction implements an extending load to FP stack slots.
60 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
61 /// operand, ptr to load from, and a ValueType node indicating the type
65 /// FST - This instruction implements a truncating store to FP stack
66 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
67 /// chain operand, value to store, address, and a ValueType to store it
71 /// FP_SET_RESULT - This corresponds to FpGETRESULT pseudo instrcuction
72 /// which copies from ST(0) to the destination. It takes a chain and writes
73 /// a RFP result and a chain.
76 /// FP_SET_RESULT - This corresponds to FpSETRESULT pseudo instrcuction
77 /// which copies the source operand to ST(0). It takes a chain and writes
78 /// a chain and a flag.
81 /// CALL/TAILCALL - These operations represent an abstract X86 call
82 /// instruction, which includes a bunch of information. In particular the
83 /// operands of these node are:
85 /// #0 - The incoming token chain
87 /// #2 - The number of arg bytes the caller pushes on the stack.
88 /// #3 - The number of arg bytes the callee pops off the stack.
89 /// #4 - The value to pass in AL/AX/EAX (optional)
90 /// #5 - The value to pass in DL/DX/EDX (optional)
92 /// The result values of these nodes are:
94 /// #0 - The outgoing token chain
95 /// #1 - The first register result value (optional)
96 /// #2 - The second register result value (optional)
98 /// The CALL vs TAILCALL distinction boils down to whether the callee is
99 /// known not to modify the caller's stack frame, as is standard with
104 /// RDTSC_DAG - This operation implements the lowering for
108 /// X86 compare and logical compare instructions.
109 CMP, TEST, COMI, UCOMI,
111 /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
112 /// operand produced by a CMP instruction.
115 /// X86 conditional moves. Operand 1 and operand 2 are the two values
116 /// to select from (operand 1 is a R/W operand). Operand 3 is the
117 /// condition code, and operand 4 is the flag operand produced by a CMP
118 /// or TEST instruction. It also writes a flag result.
121 /// X86 conditional branches. Operand 1 is the chain operand, operand 2
122 /// is the block to branch if condition is true, operand 3 is the
123 /// condition code, and operand 4 is the flag operand produced by a CMP
124 /// or TEST instruction.
127 /// Return with a flag operand. Operand 1 is the chain operand, operand
128 /// 2 is the number of bytes of stack to pop.
131 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
134 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
137 /// LOAD_PACK Load a 128-bit packed float / double value. It has the same
138 /// operands as a normal load.
141 /// LOAD_UA Load an unaligned 128-bit value. It has the same operands as
145 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
146 /// at function entry, used for PIC code.
149 /// Wrapper - A wrapper node for TargetConstantPool,
150 /// TargetExternalSymbol, and TargetGlobalAddress.
153 /// S2VEC - X86 version of SCALAR_TO_VECTOR. The destination base does not
154 /// have to match the operand type.
157 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
158 /// i32, corresponds to X86::PEXTRW.
161 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
162 /// corresponds to X86::PINSRW.
167 /// Define some predicates that are used for node matching.
169 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
170 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
171 bool isPSHUFDMask(SDNode *N);
173 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
174 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
175 bool isPSHUFHWMask(SDNode *N);
177 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
178 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
179 bool isPSHUFLWMask(SDNode *N);
181 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
182 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
183 bool isSHUFPMask(SDNode *N);
185 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
186 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
187 bool isMOVHLPSMask(SDNode *N);
189 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
190 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
191 bool isMOVLPMask(SDNode *N);
193 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
194 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
195 /// as well as MOVLHPS.
196 bool isMOVHPMask(SDNode *N);
198 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
199 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
200 bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false);
202 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
203 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
204 bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false);
206 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
207 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
209 bool isUNPCKL_v_undef_Mask(SDNode *N);
211 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
212 /// specifies a shuffle of elements that is suitable for input to MOVSS,
213 /// MOVSD, and MOVD, i.e. setting the lowest element.
214 bool isMOVLMask(SDNode *N);
216 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
217 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
218 bool isMOVSHDUPMask(SDNode *N);
220 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
221 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
222 bool isMOVSLDUPMask(SDNode *N);
224 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
225 /// specifies a splat of a single element.
226 bool isSplatMask(SDNode *N);
228 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
229 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
231 unsigned getShuffleSHUFImmediate(SDNode *N);
233 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
234 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
236 unsigned getShufflePSHUFHWImmediate(SDNode *N);
238 /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
239 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
241 unsigned getShufflePSHUFLWImmediate(SDNode *N);
244 //===--------------------------------------------------------------------===//
245 // X86TargetLowering - X86 Implementation of the TargetLowering interface
246 class X86TargetLowering : public TargetLowering {
247 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
248 int RegSaveFrameIndex; // X86-64 vararg func register save area.
249 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
250 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
251 int ReturnAddrIndex; // FrameIndex for return slot.
252 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
253 int BytesCallerReserves; // Number of arg bytes caller makes.
255 X86TargetLowering(TargetMachine &TM);
257 // Return the number of bytes that a function should pop when it returns (in
258 // addition to the space used by the return address).
260 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
262 // Return the number of bytes that the caller reserves for arguments passed
264 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
266 /// LowerOperation - Provide custom lowering hooks for some operations.
268 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
270 virtual std::pair<SDOperand, SDOperand>
271 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
274 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
276 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
277 MachineBasicBlock *MBB);
279 /// getTargetNodeName - This method returns the name of a target specific
281 virtual const char *getTargetNodeName(unsigned Opcode) const;
283 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
284 /// in Mask are known to be either zero or one and return them in the
285 /// KnownZero/KnownOne bitsets.
286 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
290 unsigned Depth = 0) const;
292 SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
294 ConstraintType getConstraintType(char ConstraintLetter) const;
296 std::vector<unsigned>
297 getRegClassForInlineAsmConstraint(const std::string &Constraint,
298 MVT::ValueType VT) const;
300 /// getRegForInlineAsmConstraint - Given a physical register constraint
301 /// (e.g. {edx}), return the register number and the register class for the
302 /// register. This should only be used for C_Register constraints. On
303 /// error, this returns a register number of 0.
304 std::pair<unsigned, const TargetRegisterClass*>
305 getRegForInlineAsmConstraint(const std::string &Constraint,
306 MVT::ValueType VT) const;
308 /// isLegalAddressImmediate - Return true if the integer value or
309 /// GlobalValue can be used as the offset of the target addressing mode.
310 virtual bool isLegalAddressImmediate(int64_t V) const;
311 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
313 /// isShuffleMaskLegal - Targets can use this to indicate that they only
314 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
315 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
316 /// values are assumed to be legal.
317 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
319 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
320 /// used by Targets can use this to indicate if there is a suitable
321 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
323 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
325 SelectionDAG &DAG) const;
327 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
328 /// make the right decision when generating code for different targets.
329 const X86Subtarget *Subtarget;
331 /// X86StackPtr - X86 physical register used as stack ptr.
332 unsigned X86StackPtr;
334 /// X86ScalarSSE - Select between SSE2 or x87 floating point ops.
337 // C Calling Convention implementation.
338 SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG);
339 SDOperand LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG);
341 // X86-64 C Calling Convention implementation.
342 SDOperand LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG);
343 SDOperand LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG);
345 // Fast Calling Convention implementation.
346 SDOperand LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG);
347 SDOperand LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
350 // StdCall Calling Convention implementation.
351 SDOperand LowerStdCallCCArguments(SDOperand Op, SelectionDAG &DAG);
352 SDOperand LowerStdCallCCCallTo(SDOperand Op, SelectionDAG &DAG);
354 // FastCall Calling Convention implementation.
355 SDOperand LowerFastCallCCArguments(SDOperand Op, SelectionDAG &DAG);
357 SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
358 SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
359 SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
360 SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
361 SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
362 SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
363 SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
364 SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG);
365 SDOperand LowerShift(SDOperand Op, SelectionDAG &DAG);
366 SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
367 SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
368 SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
369 SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
370 SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG, SDOperand Chain);
371 SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
372 SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
373 SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
374 SDOperand LowerMEMCPY(SDOperand Op, SelectionDAG &DAG);
375 SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
376 SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
377 SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
378 SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
379 SDOperand LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG);
380 SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
381 SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
385 // FASTCC_NUM_INT_ARGS_INREGS - This is the max number of integer arguments
386 // to pass in registers. 0 is none, 1 is is "use EAX", 2 is "use EAX and
387 // EDX". Anything more is illegal.
389 // FIXME: The linscan register allocator currently has problem with
390 // coalescing. At the time of this writing, whenever it decides to coalesce
391 // a physreg with a virtreg, this increases the size of the physreg's live
392 // range, and the live range cannot ever be reduced. This causes problems if
393 // too many physregs are coaleced with virtregs, which can cause the register
394 // allocator to wedge itself.
396 // This code triggers this problem more often if we pass args in registers,
397 // so disable it until this is fixed.
399 #define FASTCC_NUM_INT_ARGS_INREGS 0
401 #endif // X86ISELLOWERING_H