1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetOptions.h"
25 class X86TargetMachine;
28 // X86 Specific DAG Nodes
30 // Start the numbering where the builtin ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 /// BSF - Bit scan forward.
34 /// BSR - Bit scan reverse.
38 /// SHLD, SHRD - Double shift instructions. These correspond to
39 /// X86::SHLDxx and X86::SHRDxx instructions.
43 /// FAND - Bitwise logical AND of floating point values. This corresponds
44 /// to X86::ANDPS or X86::ANDPD.
47 /// FOR - Bitwise logical OR of floating point values. This corresponds
48 /// to X86::ORPS or X86::ORPD.
51 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
52 /// to X86::XORPS or X86::XORPD.
55 /// FANDN - Bitwise logical ANDNOT of floating point values. This
56 /// corresponds to X86::ANDNPS or X86::ANDNPD.
59 /// FSRL - Bitwise logical right shift of floating point values. These
60 /// corresponds to X86::PSRLDQ.
63 /// CALL - These operations represent an abstract X86 call
64 /// instruction, which includes a bunch of information. In particular the
65 /// operands of these node are:
67 /// #0 - The incoming token chain
69 /// #2 - The number of arg bytes the caller pushes on the stack.
70 /// #3 - The number of arg bytes the callee pops off the stack.
71 /// #4 - The value to pass in AL/AX/EAX (optional)
72 /// #5 - The value to pass in DL/DX/EDX (optional)
74 /// The result values of these nodes are:
76 /// #0 - The outgoing token chain
77 /// #1 - The first register result value (optional)
78 /// #2 - The second register result value (optional)
82 /// RDTSC_DAG - This operation implements the lowering for
86 /// X86 Read Time-Stamp Counter and Processor ID.
89 /// X86 Read Performance Monitoring Counters.
92 /// X86 compare and logical compare instructions.
95 /// X86 bit-test instructions.
98 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
99 /// operand, usually produced by a CMP instruction.
105 // Same as SETCC except it's materialized with a sbb and the value is all
106 // one's or all zero's.
107 SETCC_CARRY, // R = carry_bit ? ~0 : 0
109 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
110 /// Operands are two FP values to compare; result is a mask of
111 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
114 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
115 /// result in an integer GPR. Needs masking for scalar result.
118 /// X86 conditional moves. Operand 0 and operand 1 are the two values
119 /// to select from. Operand 2 is the condition code, and operand 3 is the
120 /// flag operand produced by a CMP or TEST instruction. It also writes a
124 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
125 /// is the block to branch if condition is true, operand 2 is the
126 /// condition code, and operand 3 is the flag operand produced by a CMP
127 /// or TEST instruction.
130 /// Return with a flag operand. Operand 0 is the chain operand, operand
131 /// 1 is the number of bytes of stack to pop.
134 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
137 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
140 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
141 /// at function entry, used for PIC code.
144 /// Wrapper - A wrapper node for TargetConstantPool,
145 /// TargetExternalSymbol, and TargetGlobalAddress.
148 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
149 /// relative displacements.
152 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
153 /// to an MMX vector. If you think this is too close to the previous
154 /// mnemonic, so do I; blame Intel.
157 /// MMX_MOVD2W - Copies a 32-bit value from the low word of a MMX
161 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
162 /// i32, corresponds to X86::PEXTRB.
165 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
166 /// i32, corresponds to X86::PEXTRW.
169 /// INSERTPS - Insert any element of a 4 x float vector into any element
170 /// of a destination 4 x floatvector.
173 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
174 /// corresponds to X86::PINSRB.
177 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
178 /// corresponds to X86::PINSRW.
181 /// PSHUFB - Shuffle 16 8-bit values within a vector.
184 /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
187 /// PSIGN - Copy integer sign.
190 /// BLENDV - Blend where the selector is a register.
193 /// BLENDI - Blend where the selector is an immediate.
196 // SUBUS - Integer sub with unsigned saturation.
199 /// HADD - Integer horizontal add.
202 /// HSUB - Integer horizontal sub.
205 /// FHADD - Floating point horizontal add.
208 /// FHSUB - Floating point horizontal sub.
211 /// UMAX, UMIN - Unsigned integer max and min.
214 /// SMAX, SMIN - Signed integer max and min.
217 /// FMAX, FMIN - Floating point max and min.
221 /// FMAXC, FMINC - Commutative FMIN and FMAX.
224 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
225 /// approximation. Note that these typically require refinement
226 /// in order to obtain suitable precision.
229 // TLSADDR - Thread Local Storage.
232 // TLSBASEADDR - Thread Local Storage. A call to get the start address
233 // of the TLS block for the current module.
236 // TLSCALL - Thread Local Storage. When calling to an OS provided
237 // thunk at the address from an earlier relocation.
240 // EH_RETURN - Exception Handling helpers.
243 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
246 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
249 /// TC_RETURN - Tail call return. See X86TargetLowering::LowerCall for
250 /// the list of operands.
253 // VZEXT_MOVL - Vector move to low scalar and zero higher vector elements.
256 // VZEXT - Vector integer zero-extend.
259 // VSEXT - Vector integer signed-extend.
262 // VTRUNC - Vector integer truncate.
265 // VTRUNC - Vector integer truncate with mask.
268 // VFPEXT - Vector FP extend.
271 // VFPROUND - Vector FP round.
274 // VSHL, VSRL - 128-bit vector logical left / right shift
277 // VSHL, VSRL, VSRA - Vector shift elements
280 // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate
283 // CMPP - Vector packed double/float comparison.
286 // PCMP* - Vector integer comparisons.
288 // PCMP*M - Vector integer comparisons, the result is in a mask vector.
291 /// CMPM, CMPMU - Vector comparison generating mask bits for fp and
292 /// integer signed and unsigned data types.
296 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
297 ADD, SUB, ADC, SBB, SMUL,
298 INC, DEC, OR, XOR, AND,
300 BEXTR, // BEXTR - Bit field extract
302 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
304 // MUL_IMM - X86 specific multiply by immediate.
307 // PTEST - Vector bitwise comparisons.
310 // TESTP - Vector packed fp sign bitwise comparisons.
313 // TESTM, TESTNM - Vector "test" in AVX-512, the result is in a mask vector.
317 // OR/AND test for masks
320 // Several flavors of instructions with vector shuffle behaviors.
325 // AVX512 inter-lane alignr
352 // Insert/Extract vector element
356 // PMULUDQ - Vector multiply packed unsigned doubleword integers
358 // PMULUDQ - Vector multiply packed signed doubleword integers
369 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
370 // according to %al. An operator is needed so that this can be expanded
371 // with control flow.
372 VASTART_SAVE_XMM_REGS,
374 // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
377 // SEG_ALLOCA - For allocating variable amounts of stack space when using
378 // segmented stacks. Check if the current stacklet has enough space, and
379 // falls back to heap allocation if not.
382 // WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui.
391 // FNSTSW16r - Store FP status word into i16 register.
394 // SAHF - Store contents of %ah into %eflags.
397 // RDRAND - Get a random integer and indicate whether it is valid in CF.
400 // RDSEED - Get a NIST SP800-90B & C compliant random integer and
401 // indicate whether it is valid in CF.
408 // XTEST - Test if in transactional execution.
411 // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
412 LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
416 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
419 // FNSTCW16m - Store FP control world into i16 memory.
422 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
423 /// integer destination in memory and a FP reg source. This corresponds
424 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
425 /// has two inputs (token chain and address) and two outputs (int value
426 /// and token chain).
431 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
432 /// integer source in memory and FP reg result. This corresponds to the
433 /// X86::FILD*m instructions. It has three inputs (token chain, address,
434 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
435 /// also produces a flag).
439 /// FLD - This instruction implements an extending load to FP stack slots.
440 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
441 /// operand, ptr to load from, and a ValueType node indicating the type
445 /// FST - This instruction implements a truncating store to FP stack
446 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
447 /// chain operand, value to store, address, and a ValueType to store it
451 /// VAARG_64 - This instruction grabs the address of the next argument
452 /// from a va_list. (reads and modifies the va_list in memory)
455 // WARNING: Do not add anything in the end unless you want the node to
456 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
457 // thought as target memory ops!
461 /// Define some predicates that are used for node matching.
463 /// isVEXTRACT128Index - Return true if the specified
464 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
465 /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
466 bool isVEXTRACT128Index(SDNode *N);
468 /// isVINSERT128Index - Return true if the specified
469 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
470 /// suitable for input to VINSERTF128, VINSERTI128 instructions.
471 bool isVINSERT128Index(SDNode *N);
473 /// isVEXTRACT256Index - Return true if the specified
474 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
475 /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
476 bool isVEXTRACT256Index(SDNode *N);
478 /// isVINSERT256Index - Return true if the specified
479 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
480 /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
481 bool isVINSERT256Index(SDNode *N);
483 /// getExtractVEXTRACT128Immediate - Return the appropriate
484 /// immediate to extract the specified EXTRACT_SUBVECTOR index
485 /// with VEXTRACTF128, VEXTRACTI128 instructions.
486 unsigned getExtractVEXTRACT128Immediate(SDNode *N);
488 /// getInsertVINSERT128Immediate - Return the appropriate
489 /// immediate to insert at the specified INSERT_SUBVECTOR index
490 /// with VINSERTF128, VINSERT128 instructions.
491 unsigned getInsertVINSERT128Immediate(SDNode *N);
493 /// getExtractVEXTRACT256Immediate - Return the appropriate
494 /// immediate to extract the specified EXTRACT_SUBVECTOR index
495 /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
496 unsigned getExtractVEXTRACT256Immediate(SDNode *N);
498 /// getInsertVINSERT256Immediate - Return the appropriate
499 /// immediate to insert at the specified INSERT_SUBVECTOR index
500 /// with VINSERTF64x4, VINSERTI64x4 instructions.
501 unsigned getInsertVINSERT256Immediate(SDNode *N);
503 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
505 bool isZeroNode(SDValue Elt);
507 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
508 /// fit into displacement field of the instruction.
509 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
510 bool hasSymbolicDisplacement = true);
513 /// isCalleePop - Determines whether the callee is required to pop its
514 /// own arguments. Callee pop is necessary to support tail calls.
515 bool isCalleePop(CallingConv::ID CallingConv,
516 bool is64Bit, bool IsVarArg, bool TailCallOpt);
518 /// AVX512 static rounding constants. These need to match the values in
520 enum STATIC_ROUNDING {
529 //===--------------------------------------------------------------------===//
530 // X86TargetLowering - X86 Implementation of the TargetLowering interface
531 class X86TargetLowering final : public TargetLowering {
533 explicit X86TargetLowering(X86TargetMachine &TM);
535 unsigned getJumpTableEncoding() const override;
537 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i8; }
540 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
541 const MachineBasicBlock *MBB, unsigned uid,
542 MCContext &Ctx) const override;
544 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
546 SDValue getPICJumpTableRelocBase(SDValue Table,
547 SelectionDAG &DAG) const override;
549 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
550 unsigned JTI, MCContext &Ctx) const override;
552 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
553 /// function arguments in the caller parameter area. For X86, aggregates
554 /// that contains are placed at 16-byte boundaries while the rest are at
555 /// 4-byte boundaries.
556 unsigned getByValTypeAlignment(Type *Ty) const override;
558 /// getOptimalMemOpType - Returns the target specific optimal type for load
559 /// and store operations as a result of memset, memcpy, and memmove
560 /// lowering. If DstAlign is zero that means it's safe to destination
561 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
562 /// means there isn't a need to check it against alignment requirement,
563 /// probably because the source does not need to be loaded. If 'IsMemset' is
564 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
565 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
566 /// source is constant so it does not need to be loaded.
567 /// It returns EVT::Other if the type should be determined using generic
568 /// target-independent logic.
569 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
570 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
571 MachineFunction &MF) const override;
573 /// isSafeMemOpType - Returns true if it's safe to use load / store of the
574 /// specified type to expand memcpy / memset inline. This is mostly true
575 /// for all types except for some special cases. For example, on X86
576 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
577 /// also does type conversion. Note the specified type doesn't have to be
578 /// legal as the hook is used before type legalization.
579 bool isSafeMemOpType(MVT VT) const override;
581 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
582 /// unaligned memory accesses. of the specified type. Returns whether it
583 /// is "fast" by reference in the second argument.
584 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
585 bool *Fast) const override;
587 /// LowerOperation - Provide custom lowering hooks for some operations.
589 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
591 /// ReplaceNodeResults - Replace the results of node with an illegal result
592 /// type with new values built out of custom code.
594 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
595 SelectionDAG &DAG) const override;
598 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
600 /// isTypeDesirableForOp - Return true if the target has native support for
601 /// the specified value type and it is 'desirable' to use the type for the
602 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
603 /// instruction encodings are longer and some i16 instructions are slow.
604 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
606 /// isTypeDesirable - Return true if the target has native support for the
607 /// specified value type and it is 'desirable' to use the type. e.g. On x86
608 /// i16 is legal, but undesirable since i16 instruction encodings are longer
609 /// and some i16 instructions are slow.
610 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
613 EmitInstrWithCustomInserter(MachineInstr *MI,
614 MachineBasicBlock *MBB) const override;
617 /// getTargetNodeName - This method returns the name of a target specific
619 const char *getTargetNodeName(unsigned Opcode) const override;
621 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
622 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
624 /// computeKnownBitsForTargetNode - Determine which of the bits specified
625 /// in Mask are known to be either zero or one and return them in the
626 /// KnownZero/KnownOne bitsets.
627 void computeKnownBitsForTargetNode(const SDValue Op,
630 const SelectionDAG &DAG,
631 unsigned Depth = 0) const override;
633 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
634 // operation that are sign bits.
635 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
636 const SelectionDAG &DAG,
637 unsigned Depth) const override;
639 bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
640 int64_t &Offset) const override;
642 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
644 bool ExpandInlineAsm(CallInst *CI) const override;
647 getConstraintType(const std::string &Constraint) const override;
649 /// Examine constraint string and operand type and determine a weight value.
650 /// The operand object must already have been set up with the operand type.
652 getSingleConstraintMatchWeight(AsmOperandInfo &info,
653 const char *constraint) const override;
655 const char *LowerXConstraint(EVT ConstraintVT) const override;
657 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
658 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
659 /// true it means one of the asm constraint of the inline asm instruction
660 /// being processed is 'm'.
661 void LowerAsmOperandForConstraint(SDValue Op,
662 std::string &Constraint,
663 std::vector<SDValue> &Ops,
664 SelectionDAG &DAG) const override;
666 /// getRegForInlineAsmConstraint - Given a physical register constraint
667 /// (e.g. {edx}), return the register number and the register class for the
668 /// register. This should only be used for C_Register constraints. On
669 /// error, this returns a register number of 0.
670 std::pair<unsigned, const TargetRegisterClass*>
671 getRegForInlineAsmConstraint(const std::string &Constraint,
672 MVT VT) const override;
674 /// isLegalAddressingMode - Return true if the addressing mode represented
675 /// by AM is legal for this target, for a load/store of the specified type.
676 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
678 /// isLegalICmpImmediate - Return true if the specified immediate is legal
679 /// icmp immediate, that is the target has icmp instructions which can
680 /// compare a register against the immediate without having to materialize
681 /// the immediate into a register.
682 bool isLegalICmpImmediate(int64_t Imm) const override;
684 /// isLegalAddImmediate - Return true if the specified immediate is legal
685 /// add immediate, that is the target has add instructions which can
686 /// add a register and the immediate without having to materialize
687 /// the immediate into a register.
688 bool isLegalAddImmediate(int64_t Imm) const override;
690 /// \brief Return the cost of the scaling factor used in the addressing
691 /// mode represented by AM for this target, for a load/store
692 /// of the specified type.
693 /// If the AM is supported, the return value must be >= 0.
694 /// If the AM is not supported, it returns a negative value.
695 int getScalingFactorCost(const AddrMode &AM, Type *Ty) const override;
697 bool isVectorShiftByScalarCheap(Type *Ty) const override;
699 /// isTruncateFree - Return true if it's free to truncate a value of
700 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
701 /// register EAX to i16 by referencing its sub-register AX.
702 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
703 bool isTruncateFree(EVT VT1, EVT VT2) const override;
705 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
707 /// isZExtFree - Return true if any actual instruction that defines a
708 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
709 /// register. This does not necessarily include registers defined in
710 /// unknown ways, such as incoming arguments, or copies from unknown
711 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
712 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
713 /// all instructions that define 32-bit values implicit zero-extend the
714 /// result out to 64 bits.
715 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
716 bool isZExtFree(EVT VT1, EVT VT2) const override;
717 bool isZExtFree(SDValue Val, EVT VT2) const override;
719 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
720 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
721 /// expanded to FMAs when this method returns true, otherwise fmuladd is
722 /// expanded to fmul + fadd.
723 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
725 /// isNarrowingProfitable - Return true if it's profitable to narrow
726 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
727 /// from i32 to i8 but not from i32 to i16.
728 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
730 /// isFPImmLegal - Returns true if the target can instruction select the
731 /// specified FP immediate natively. If false, the legalizer will
732 /// materialize the FP immediate as a load from a constant pool.
733 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
735 /// isShuffleMaskLegal - Targets can use this to indicate that they only
736 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
737 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
738 /// values are assumed to be legal.
739 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
740 EVT VT) const override;
742 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
743 /// used by Targets can use this to indicate if there is a suitable
744 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
746 bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
747 EVT VT) const override;
749 /// ShouldShrinkFPConstant - If true, then instruction selection should
750 /// seek to shrink the FP constant of the specified type to a smaller type
751 /// in order to save space and / or reduce runtime.
752 bool ShouldShrinkFPConstant(EVT VT) const override {
753 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
754 // expensive than a straight movsd. On the other hand, it's important to
755 // shrink long double fp constant since fldt is very slow.
756 return !X86ScalarSSEf64 || VT == MVT::f80;
759 const X86Subtarget* getSubtarget() const {
763 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
764 /// computed in an SSE register, not on the X87 floating point stack.
765 bool isScalarFPTypeInSSEReg(EVT VT) const {
766 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
767 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
770 /// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine
772 bool isTargetFTOL() const;
774 /// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be
775 /// used for fptoui to the given type.
776 bool isIntegerTypeFTOL(EVT VT) const {
777 return isTargetFTOL() && VT == MVT::i64;
780 /// \brief Returns true if it is beneficial to convert a load of a constant
781 /// to just the constant itself.
782 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
783 Type *Ty) const override;
785 /// Intel processors have a unified instruction and data cache
786 const char * getClearCacheBuiltinName() const override {
787 return nullptr; // nothing to do, move along.
790 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
792 /// createFastISel - This method returns a target specific FastISel object,
793 /// or null if the target does not support "fast" ISel.
794 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
795 const TargetLibraryInfo *libInfo) const override;
797 /// getStackCookieLocation - Return true if the target stores stack
798 /// protector cookies at a fixed offset in some non-standard address
799 /// space, and populates the address space and offset as
801 bool getStackCookieLocation(unsigned &AddressSpace,
802 unsigned &Offset) const override;
804 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
805 SelectionDAG &DAG) const;
807 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
809 /// \brief Reset the operation actions based on target options.
810 void resetOperationActions() override;
812 bool useLoadStackGuardNode() const override;
813 /// \brief Customize the preferred legalization strategy for certain types.
814 LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
817 std::pair<const TargetRegisterClass*, uint8_t>
818 findRepresentativeClass(MVT VT) const override;
821 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
822 /// make the right decision when generating code for different targets.
823 const X86Subtarget *Subtarget;
824 const DataLayout *TD;
826 /// Used to store the TargetOptions so that we don't waste time resetting
827 /// the operation actions unless we have to.
830 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
831 /// floating point ops.
832 /// When SSE is available, use it for f32 operations.
833 /// When SSE2 is available, use it for f64 operations.
834 bool X86ScalarSSEf32;
835 bool X86ScalarSSEf64;
837 /// LegalFPImmediates - A list of legal fp immediates.
838 std::vector<APFloat> LegalFPImmediates;
840 /// addLegalFPImmediate - Indicate that this x86 target can instruction
841 /// select the specified FP immediate natively.
842 void addLegalFPImmediate(const APFloat& Imm) {
843 LegalFPImmediates.push_back(Imm);
846 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
847 CallingConv::ID CallConv, bool isVarArg,
848 const SmallVectorImpl<ISD::InputArg> &Ins,
849 SDLoc dl, SelectionDAG &DAG,
850 SmallVectorImpl<SDValue> &InVals) const;
851 SDValue LowerMemArgument(SDValue Chain,
852 CallingConv::ID CallConv,
853 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
854 SDLoc dl, SelectionDAG &DAG,
855 const CCValAssign &VA, MachineFrameInfo *MFI,
857 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
858 SDLoc dl, SelectionDAG &DAG,
859 const CCValAssign &VA,
860 ISD::ArgFlagsTy Flags) const;
862 // Call lowering helpers.
864 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
865 /// for tail call optimization. Targets which want to do tail call
866 /// optimization should implement this function.
867 bool IsEligibleForTailCallOptimization(SDValue Callee,
868 CallingConv::ID CalleeCC,
870 bool isCalleeStructRet,
871 bool isCallerStructRet,
873 const SmallVectorImpl<ISD::OutputArg> &Outs,
874 const SmallVectorImpl<SDValue> &OutVals,
875 const SmallVectorImpl<ISD::InputArg> &Ins,
876 SelectionDAG& DAG) const;
877 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
878 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
879 SDValue Chain, bool IsTailCall, bool Is64Bit,
880 int FPDiff, SDLoc dl) const;
882 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
883 SelectionDAG &DAG) const;
885 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
887 bool isReplace) const;
889 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
890 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
891 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
892 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
893 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
894 SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const;
895 SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const;
897 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
898 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
899 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
900 SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
901 int64_t Offset, SelectionDAG &DAG) const;
902 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
903 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
904 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
905 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
906 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
907 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
908 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
909 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
910 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
911 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
912 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
913 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
914 SDLoc dl, SelectionDAG &DAG) const;
915 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
916 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
917 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
918 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
919 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
920 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
921 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
922 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
923 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
924 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
925 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
926 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
927 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
928 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
929 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
930 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
931 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
932 SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
935 LowerFormalArguments(SDValue Chain,
936 CallingConv::ID CallConv, bool isVarArg,
937 const SmallVectorImpl<ISD::InputArg> &Ins,
938 SDLoc dl, SelectionDAG &DAG,
939 SmallVectorImpl<SDValue> &InVals) const override;
940 SDValue LowerCall(CallLoweringInfo &CLI,
941 SmallVectorImpl<SDValue> &InVals) const override;
943 SDValue LowerReturn(SDValue Chain,
944 CallingConv::ID CallConv, bool isVarArg,
945 const SmallVectorImpl<ISD::OutputArg> &Outs,
946 const SmallVectorImpl<SDValue> &OutVals,
947 SDLoc dl, SelectionDAG &DAG) const override;
949 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
951 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
953 EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
954 ISD::NodeType ExtendKind) const override;
956 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
958 const SmallVectorImpl<ISD::OutputArg> &Outs,
959 LLVMContext &Context) const override;
961 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
963 /// Utility function to emit atomic-load-arith operations (and, or, xor,
964 /// nand, max, min, umax, umin). It takes the corresponding instruction to
965 /// expand, the associated machine basic block, and the associated X86
966 /// opcodes for reg/reg.
967 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
968 MachineBasicBlock *MBB) const;
970 /// Utility function to emit atomic-load-arith operations (and, or, xor,
971 /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
972 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
973 MachineBasicBlock *MBB) const;
975 // Utility function to emit the low-level va_arg code for X86-64.
976 MachineBasicBlock *EmitVAARG64WithCustomInserter(
978 MachineBasicBlock *MBB) const;
980 /// Utility function to emit the xmm reg save portion of va_start.
981 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
982 MachineInstr *BInstr,
983 MachineBasicBlock *BB) const;
985 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
986 MachineBasicBlock *BB) const;
988 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
989 MachineBasicBlock *BB) const;
991 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
992 MachineBasicBlock *BB,
995 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
996 MachineBasicBlock *BB) const;
998 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
999 MachineBasicBlock *BB) const;
1001 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
1002 MachineBasicBlock *MBB) const;
1004 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
1005 MachineBasicBlock *MBB) const;
1007 MachineBasicBlock *emitFMA3Instr(MachineInstr *MI,
1008 MachineBasicBlock *MBB) const;
1010 /// Emit nodes that will be selected as "test Op0,Op0", or something
1011 /// equivalent, for use with the given x86 condition code.
1012 SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl,
1013 SelectionDAG &DAG) const;
1015 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
1016 /// equivalent, for use with the given x86 condition code.
1017 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl,
1018 SelectionDAG &DAG) const;
1020 /// Convert a comparison if required by the subtarget.
1021 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
1025 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1026 const TargetLibraryInfo *libInfo);
1030 #endif // X86ISELLOWERING_H