1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86MachineFunctionInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Target/TargetOptions.h"
29 // X86 Specific DAG Nodes
31 // Start the numbering where the builtin ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 /// BSF - Bit scan forward.
35 /// BSR - Bit scan reverse.
39 /// SHLD, SHRD - Double shift instructions. These correspond to
40 /// X86::SHLDxx and X86::SHRDxx instructions.
44 /// FAND - Bitwise logical AND of floating point values. This corresponds
45 /// to X86::ANDPS or X86::ANDPD.
48 /// FOR - Bitwise logical OR of floating point values. This corresponds
49 /// to X86::ORPS or X86::ORPD.
52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
53 /// to X86::XORPS or X86::XORPD.
56 /// FANDN - Bitwise logical ANDNOT of floating point values. This
57 /// corresponds to X86::ANDNPS or X86::ANDNPD.
60 /// FSRL - Bitwise logical right shift of floating point values. These
61 /// corresponds to X86::PSRLDQ.
64 /// CALL - These operations represent an abstract X86 call
65 /// instruction, which includes a bunch of information. In particular the
66 /// operands of these node are:
68 /// #0 - The incoming token chain
70 /// #2 - The number of arg bytes the caller pushes on the stack.
71 /// #3 - The number of arg bytes the callee pops off the stack.
72 /// #4 - The value to pass in AL/AX/EAX (optional)
73 /// #5 - The value to pass in DL/DX/EDX (optional)
75 /// The result values of these nodes are:
77 /// #0 - The outgoing token chain
78 /// #1 - The first register result value (optional)
79 /// #2 - The second register result value (optional)
83 /// RDTSC_DAG - This operation implements the lowering for
87 /// X86 compare and logical compare instructions.
90 /// X86 bit-test instructions.
93 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
94 /// operand, usually produced by a CMP instruction.
100 // Same as SETCC except it's materialized with a sbb and the value is all
101 // one's or all zero's.
102 SETCC_CARRY, // R = carry_bit ? ~0 : 0
104 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
105 /// Operands are two FP values to compare; result is a mask of
106 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
109 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
110 /// result in an integer GPR. Needs masking for scalar result.
113 /// X86 conditional moves. Operand 0 and operand 1 are the two values
114 /// to select from. Operand 2 is the condition code, and operand 3 is the
115 /// flag operand produced by a CMP or TEST instruction. It also writes a
119 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
120 /// is the block to branch if condition is true, operand 2 is the
121 /// condition code, and operand 3 is the flag operand produced by a CMP
122 /// or TEST instruction.
125 /// Return with a flag operand. Operand 0 is the chain operand, operand
126 /// 1 is the number of bytes of stack to pop.
129 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
132 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
135 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
136 /// at function entry, used for PIC code.
139 /// Wrapper - A wrapper node for TargetConstantPool,
140 /// TargetExternalSymbol, and TargetGlobalAddress.
143 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
144 /// relative displacements.
147 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
148 /// to an MMX vector. If you think this is too close to the previous
149 /// mnemonic, so do I; blame Intel.
152 /// MMX_MOVD2W - Copies a 32-bit value from the low word of a MMX
156 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
157 /// i32, corresponds to X86::PEXTRB.
160 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
161 /// i32, corresponds to X86::PEXTRW.
164 /// INSERTPS - Insert any element of a 4 x float vector into any element
165 /// of a destination 4 x floatvector.
168 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
169 /// corresponds to X86::PINSRB.
172 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
173 /// corresponds to X86::PINSRW.
176 /// PSHUFB - Shuffle 16 8-bit values within a vector.
179 /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
182 /// PSIGN - Copy integer sign.
185 /// BLENDV - Blend where the selector is a register.
188 /// BLENDI - Blend where the selector is an immediate.
191 // SUBUS - Integer sub with unsigned saturation.
194 /// HADD - Integer horizontal add.
197 /// HSUB - Integer horizontal sub.
200 /// FHADD - Floating point horizontal add.
203 /// FHSUB - Floating point horizontal sub.
206 /// UMAX, UMIN - Unsigned integer max and min.
209 /// SMAX, SMIN - Signed integer max and min.
212 /// FMAX, FMIN - Floating point max and min.
216 /// FMAXC, FMINC - Commutative FMIN and FMAX.
219 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
220 /// approximation. Note that these typically require refinement
221 /// in order to obtain suitable precision.
224 // TLSADDR - Thread Local Storage.
227 // TLSBASEADDR - Thread Local Storage. A call to get the start address
228 // of the TLS block for the current module.
231 // TLSCALL - Thread Local Storage. When calling to an OS provided
232 // thunk at the address from an earlier relocation.
235 // EH_RETURN - Exception Handling helpers.
238 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
241 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
244 /// TC_RETURN - Tail call return. See X86TargetLowering::LowerCall for
245 /// the list of operands.
248 // VZEXT_MOVL - Vector move low and zero extend.
251 // VSEXT_MOVL - Vector move low and sign extend.
254 // VZEXT - Vector integer zero-extend.
257 // VSEXT - Vector integer signed-extend.
260 // VTRUNC - Vector integer truncate.
263 // VTRUNC - Vector integer truncate with mask.
266 // VFPEXT - Vector FP extend.
269 // VFPROUND - Vector FP round.
272 // VSHL, VSRL - 128-bit vector logical left / right shift
275 // VSHL, VSRL, VSRA - Vector shift elements
278 // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate
281 // CMPP - Vector packed double/float comparison.
284 // PCMP* - Vector integer comparisons.
286 // PCMP*M - Vector integer comparisons, the result is in a mask vector.
289 /// CMPM, CMPMU - Vector comparison generating mask bits for fp and
290 /// integer signed and unsigned data types.
294 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
295 ADD, SUB, ADC, SBB, SMUL,
296 INC, DEC, OR, XOR, AND,
298 BLSI, // BLSI - Extract lowest set isolated bit
299 BLSMSK, // BLSMSK - Get mask up to lowest set bit
300 BLSR, // BLSR - Reset lowest set bit
301 BZHI, // BZHI - Zero high bits
302 BEXTR, // BEXTR - Bit field extract
304 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
306 // MUL_IMM - X86 specific multiply by immediate.
309 // PTEST - Vector bitwise comparisons.
312 // TESTP - Vector packed fp sign bitwise comparisons.
315 // TESTM - Vector "test" in AVX-512, the result is in a mask vector.
318 // OR/AND test for masks
321 // Several flavors of instructions with vector shuffle behaviors.
350 // PMULUDQ - Vector multiply packed unsigned doubleword integers
361 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
362 // according to %al. An operator is needed so that this can be expanded
363 // with control flow.
364 VASTART_SAVE_XMM_REGS,
366 // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
369 // SEG_ALLOCA - For allocating variable amounts of stack space when using
370 // segmented stacks. Check if the current stacklet has enough space, and
371 // falls back to heap allocation if not.
374 // WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui.
383 // FNSTSW16r - Store FP status word into i16 register.
386 // SAHF - Store contents of %ah into %eflags.
389 // RDRAND - Get a random integer and indicate whether it is valid in CF.
392 // RDSEED - Get a NIST SP800-90B & C compliant random integer and
393 // indicate whether it is valid in CF.
400 // XTEST - Test if in transactional execution.
403 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
404 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
405 // Atomic 64-bit binary operations.
406 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
418 // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
423 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
426 // FNSTCW16m - Store FP control world into i16 memory.
429 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
430 /// integer destination in memory and a FP reg source. This corresponds
431 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
432 /// has two inputs (token chain and address) and two outputs (int value
433 /// and token chain).
438 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
439 /// integer source in memory and FP reg result. This corresponds to the
440 /// X86::FILD*m instructions. It has three inputs (token chain, address,
441 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
442 /// also produces a flag).
446 /// FLD - This instruction implements an extending load to FP stack slots.
447 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
448 /// operand, ptr to load from, and a ValueType node indicating the type
452 /// FST - This instruction implements a truncating store to FP stack
453 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
454 /// chain operand, value to store, address, and a ValueType to store it
458 /// VAARG_64 - This instruction grabs the address of the next argument
459 /// from a va_list. (reads and modifies the va_list in memory)
462 // WARNING: Do not add anything in the end unless you want the node to
463 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
464 // thought as target memory ops!
468 /// Define some predicates that are used for node matching.
470 /// isVEXTRACT128Index - Return true if the specified
471 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
472 /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
473 bool isVEXTRACT128Index(SDNode *N);
475 /// isVINSERT128Index - Return true if the specified
476 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
477 /// suitable for input to VINSERTF128, VINSERTI128 instructions.
478 bool isVINSERT128Index(SDNode *N);
480 /// isVEXTRACT256Index - Return true if the specified
481 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
482 /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
483 bool isVEXTRACT256Index(SDNode *N);
485 /// isVINSERT256Index - Return true if the specified
486 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
487 /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
488 bool isVINSERT256Index(SDNode *N);
490 /// getExtractVEXTRACT128Immediate - Return the appropriate
491 /// immediate to extract the specified EXTRACT_SUBVECTOR index
492 /// with VEXTRACTF128, VEXTRACTI128 instructions.
493 unsigned getExtractVEXTRACT128Immediate(SDNode *N);
495 /// getInsertVINSERT128Immediate - Return the appropriate
496 /// immediate to insert at the specified INSERT_SUBVECTOR index
497 /// with VINSERTF128, VINSERT128 instructions.
498 unsigned getInsertVINSERT128Immediate(SDNode *N);
500 /// getExtractVEXTRACT256Immediate - Return the appropriate
501 /// immediate to extract the specified EXTRACT_SUBVECTOR index
502 /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
503 unsigned getExtractVEXTRACT256Immediate(SDNode *N);
505 /// getInsertVINSERT256Immediate - Return the appropriate
506 /// immediate to insert at the specified INSERT_SUBVECTOR index
507 /// with VINSERTF64x4, VINSERTI64x4 instructions.
508 unsigned getInsertVINSERT256Immediate(SDNode *N);
510 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
512 bool isZeroNode(SDValue Elt);
514 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
515 /// fit into displacement field of the instruction.
516 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
517 bool hasSymbolicDisplacement = true);
520 /// isCalleePop - Determines whether the callee is required to pop its
521 /// own arguments. Callee pop is necessary to support tail calls.
522 bool isCalleePop(CallingConv::ID CallingConv,
523 bool is64Bit, bool IsVarArg, bool TailCallOpt);
526 //===--------------------------------------------------------------------===//
527 // X86TargetLowering - X86 Implementation of the TargetLowering interface
528 class X86TargetLowering : public TargetLowering {
530 explicit X86TargetLowering(X86TargetMachine &TM);
532 virtual unsigned getJumpTableEncoding() const;
534 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
536 virtual const MCExpr *
537 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
538 const MachineBasicBlock *MBB, unsigned uid,
539 MCContext &Ctx) const;
541 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
543 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
544 SelectionDAG &DAG) const;
545 virtual const MCExpr *
546 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
547 unsigned JTI, MCContext &Ctx) const;
549 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
550 /// function arguments in the caller parameter area. For X86, aggregates
551 /// that contains are placed at 16-byte boundaries while the rest are at
552 /// 4-byte boundaries.
553 virtual unsigned getByValTypeAlignment(Type *Ty) const;
555 /// getOptimalMemOpType - Returns the target specific optimal type for load
556 /// and store operations as a result of memset, memcpy, and memmove
557 /// lowering. If DstAlign is zero that means it's safe to destination
558 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
559 /// means there isn't a need to check it against alignment requirement,
560 /// probably because the source does not need to be loaded. If 'IsMemset' is
561 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
562 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
563 /// source is constant so it does not need to be loaded.
564 /// It returns EVT::Other if the type should be determined using generic
565 /// target-independent logic.
567 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
568 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
569 MachineFunction &MF) const;
571 /// isSafeMemOpType - Returns true if it's safe to use load / store of the
572 /// specified type to expand memcpy / memset inline. This is mostly true
573 /// for all types except for some special cases. For example, on X86
574 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
575 /// also does type conversion. Note the specified type doesn't have to be
576 /// legal as the hook is used before type legalization.
577 virtual bool isSafeMemOpType(MVT VT) const;
579 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
580 /// unaligned memory accesses. of the specified type. Returns whether it
581 /// is "fast" by reference in the second argument.
582 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
584 /// LowerOperation - Provide custom lowering hooks for some operations.
586 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
588 /// ReplaceNodeResults - Replace the results of node with an illegal result
589 /// type with new values built out of custom code.
591 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
592 SelectionDAG &DAG) const;
595 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
597 /// isTypeDesirableForOp - Return true if the target has native support for
598 /// the specified value type and it is 'desirable' to use the type for the
599 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
600 /// instruction encodings are longer and some i16 instructions are slow.
601 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
603 /// isTypeDesirable - Return true if the target has native support for the
604 /// specified value type and it is 'desirable' to use the type. e.g. On x86
605 /// i16 is legal, but undesirable since i16 instruction encodings are longer
606 /// and some i16 instructions are slow.
607 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
609 virtual MachineBasicBlock *
610 EmitInstrWithCustomInserter(MachineInstr *MI,
611 MachineBasicBlock *MBB) const;
614 /// getTargetNodeName - This method returns the name of a target specific
616 virtual const char *getTargetNodeName(unsigned Opcode) const;
618 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
619 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
621 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
622 /// in Mask are known to be either zero or one and return them in the
623 /// KnownZero/KnownOne bitsets.
624 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
627 const SelectionDAG &DAG,
628 unsigned Depth = 0) const;
630 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
631 // operation that are sign bits.
632 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
633 unsigned Depth) const;
636 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
638 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
640 virtual bool ExpandInlineAsm(CallInst *CI) const;
642 ConstraintType getConstraintType(const std::string &Constraint) const;
644 /// Examine constraint string and operand type and determine a weight value.
645 /// The operand object must already have been set up with the operand type.
646 virtual ConstraintWeight getSingleConstraintMatchWeight(
647 AsmOperandInfo &info, const char *constraint) const;
649 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
651 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
652 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
653 /// true it means one of the asm constraint of the inline asm instruction
654 /// being processed is 'm'.
655 virtual void LowerAsmOperandForConstraint(SDValue Op,
656 std::string &Constraint,
657 std::vector<SDValue> &Ops,
658 SelectionDAG &DAG) const;
660 /// getRegForInlineAsmConstraint - Given a physical register constraint
661 /// (e.g. {edx}), return the register number and the register class for the
662 /// register. This should only be used for C_Register constraints. On
663 /// error, this returns a register number of 0.
664 std::pair<unsigned, const TargetRegisterClass*>
665 getRegForInlineAsmConstraint(const std::string &Constraint,
668 /// isLegalAddressingMode - Return true if the addressing mode represented
669 /// by AM is legal for this target, for a load/store of the specified type.
670 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
672 /// isLegalICmpImmediate - Return true if the specified immediate is legal
673 /// icmp immediate, that is the target has icmp instructions which can
674 /// compare a register against the immediate without having to materialize
675 /// the immediate into a register.
676 virtual bool isLegalICmpImmediate(int64_t Imm) const;
678 /// isLegalAddImmediate - Return true if the specified immediate is legal
679 /// add immediate, that is the target has add instructions which can
680 /// add a register and the immediate without having to materialize
681 /// the immediate into a register.
682 virtual bool isLegalAddImmediate(int64_t Imm) const;
684 /// isTruncateFree - Return true if it's free to truncate a value of
685 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
686 /// register EAX to i16 by referencing its sub-register AX.
687 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
688 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
690 virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const;
692 /// isZExtFree - Return true if any actual instruction that defines a
693 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
694 /// register. This does not necessarily include registers defined in
695 /// unknown ways, such as incoming arguments, or copies from unknown
696 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
697 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
698 /// all instructions that define 32-bit values implicit zero-extend the
699 /// result out to 64 bits.
700 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
701 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
702 virtual bool isZExtFree(SDValue Val, EVT VT2) const;
704 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
705 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
706 /// expanded to FMAs when this method returns true, otherwise fmuladd is
707 /// expanded to fmul + fadd.
708 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
710 /// isNarrowingProfitable - Return true if it's profitable to narrow
711 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
712 /// from i32 to i8 but not from i32 to i16.
713 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
715 /// isFPImmLegal - Returns true if the target can instruction select the
716 /// specified FP immediate natively. If false, the legalizer will
717 /// materialize the FP immediate as a load from a constant pool.
718 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
720 /// isShuffleMaskLegal - Targets can use this to indicate that they only
721 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
722 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
723 /// values are assumed to be legal.
724 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
727 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
728 /// used by Targets can use this to indicate if there is a suitable
729 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
731 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
734 /// ShouldShrinkFPConstant - If true, then instruction selection should
735 /// seek to shrink the FP constant of the specified type to a smaller type
736 /// in order to save space and / or reduce runtime.
737 virtual bool ShouldShrinkFPConstant(EVT VT) const {
738 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
739 // expensive than a straight movsd. On the other hand, it's important to
740 // shrink long double fp constant since fldt is very slow.
741 return !X86ScalarSSEf64 || VT == MVT::f80;
744 const X86Subtarget* getSubtarget() const {
748 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
749 /// computed in an SSE register, not on the X87 floating point stack.
750 bool isScalarFPTypeInSSEReg(EVT VT) const {
751 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
752 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
755 /// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine
757 bool isTargetFTOL() const {
758 return Subtarget->isTargetWindows() && !Subtarget->is64Bit();
761 /// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be
762 /// used for fptoui to the given type.
763 bool isIntegerTypeFTOL(EVT VT) const {
764 return isTargetFTOL() && VT == MVT::i64;
767 /// createFastISel - This method returns a target specific FastISel object,
768 /// or null if the target does not support "fast" ISel.
769 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
770 const TargetLibraryInfo *libInfo) const;
772 /// getStackCookieLocation - Return true if the target stores stack
773 /// protector cookies at a fixed offset in some non-standard address
774 /// space, and populates the address space and offset as
776 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
778 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
779 SelectionDAG &DAG) const;
781 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const LLVM_OVERRIDE;
783 /// \brief Reset the operation actions based on target options.
784 virtual void resetOperationActions();
787 std::pair<const TargetRegisterClass*, uint8_t>
788 findRepresentativeClass(MVT VT) const;
791 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
792 /// make the right decision when generating code for different targets.
793 const X86Subtarget *Subtarget;
794 const DataLayout *TD;
796 /// Used to store the TargetOptions so that we don't waste time resetting
797 /// the operation actions unless we have to.
800 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
801 /// floating point ops.
802 /// When SSE is available, use it for f32 operations.
803 /// When SSE2 is available, use it for f64 operations.
804 bool X86ScalarSSEf32;
805 bool X86ScalarSSEf64;
807 /// LegalFPImmediates - A list of legal fp immediates.
808 std::vector<APFloat> LegalFPImmediates;
810 /// addLegalFPImmediate - Indicate that this x86 target can instruction
811 /// select the specified FP immediate natively.
812 void addLegalFPImmediate(const APFloat& Imm) {
813 LegalFPImmediates.push_back(Imm);
816 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
817 CallingConv::ID CallConv, bool isVarArg,
818 const SmallVectorImpl<ISD::InputArg> &Ins,
819 SDLoc dl, SelectionDAG &DAG,
820 SmallVectorImpl<SDValue> &InVals) const;
821 SDValue LowerMemArgument(SDValue Chain,
822 CallingConv::ID CallConv,
823 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
824 SDLoc dl, SelectionDAG &DAG,
825 const CCValAssign &VA, MachineFrameInfo *MFI,
827 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
828 SDLoc dl, SelectionDAG &DAG,
829 const CCValAssign &VA,
830 ISD::ArgFlagsTy Flags) const;
832 // Call lowering helpers.
834 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
835 /// for tail call optimization. Targets which want to do tail call
836 /// optimization should implement this function.
837 bool IsEligibleForTailCallOptimization(SDValue Callee,
838 CallingConv::ID CalleeCC,
840 bool isCalleeStructRet,
841 bool isCallerStructRet,
843 const SmallVectorImpl<ISD::OutputArg> &Outs,
844 const SmallVectorImpl<SDValue> &OutVals,
845 const SmallVectorImpl<ISD::InputArg> &Ins,
846 SelectionDAG& DAG) const;
847 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
848 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
849 SDValue Chain, bool IsTailCall, bool Is64Bit,
850 int FPDiff, SDLoc dl) const;
852 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
853 SelectionDAG &DAG) const;
855 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
857 bool isReplace) const;
859 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
860 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
861 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
862 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
863 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
864 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
865 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
866 SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
867 int64_t Offset, SelectionDAG &DAG) const;
868 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
869 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
870 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
871 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
872 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
873 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
874 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
875 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
876 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
877 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
878 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
879 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
880 SDLoc dl, SelectionDAG &DAG) const;
881 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
882 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
883 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
884 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
885 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
886 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
887 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
888 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
889 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
890 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
891 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
892 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
893 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
894 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
895 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
896 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
897 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
900 LowerFormalArguments(SDValue Chain,
901 CallingConv::ID CallConv, bool isVarArg,
902 const SmallVectorImpl<ISD::InputArg> &Ins,
903 SDLoc dl, SelectionDAG &DAG,
904 SmallVectorImpl<SDValue> &InVals) const;
906 LowerCall(CallLoweringInfo &CLI,
907 SmallVectorImpl<SDValue> &InVals) const;
910 LowerReturn(SDValue Chain,
911 CallingConv::ID CallConv, bool isVarArg,
912 const SmallVectorImpl<ISD::OutputArg> &Outs,
913 const SmallVectorImpl<SDValue> &OutVals,
914 SDLoc dl, SelectionDAG &DAG) const;
916 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
918 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
921 getTypeForExtArgOrReturn(MVT VT, ISD::NodeType ExtendKind) const;
924 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
926 const SmallVectorImpl<ISD::OutputArg> &Outs,
927 LLVMContext &Context) const;
929 virtual const uint16_t *getScratchRegisters(CallingConv::ID CC) const;
931 /// Utility function to emit atomic-load-arith operations (and, or, xor,
932 /// nand, max, min, umax, umin). It takes the corresponding instruction to
933 /// expand, the associated machine basic block, and the associated X86
934 /// opcodes for reg/reg.
935 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
936 MachineBasicBlock *MBB) const;
938 /// Utility function to emit atomic-load-arith operations (and, or, xor,
939 /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
940 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
941 MachineBasicBlock *MBB) const;
943 // Utility function to emit the low-level va_arg code for X86-64.
944 MachineBasicBlock *EmitVAARG64WithCustomInserter(
946 MachineBasicBlock *MBB) const;
948 /// Utility function to emit the xmm reg save portion of va_start.
949 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
950 MachineInstr *BInstr,
951 MachineBasicBlock *BB) const;
953 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
954 MachineBasicBlock *BB) const;
956 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
957 MachineBasicBlock *BB) const;
959 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
960 MachineBasicBlock *BB,
963 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
964 MachineBasicBlock *BB) const;
966 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
967 MachineBasicBlock *BB) const;
969 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
970 MachineBasicBlock *MBB) const;
972 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
973 MachineBasicBlock *MBB) const;
975 /// Emit nodes that will be selected as "test Op0,Op0", or something
976 /// equivalent, for use with the given x86 condition code.
977 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
979 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
980 /// equivalent, for use with the given x86 condition code.
981 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
982 SelectionDAG &DAG) const;
984 /// Convert a comparison if required by the subtarget.
985 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
989 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
990 const TargetLibraryInfo *libInfo);
994 #endif // X86ISELLOWERING_H