1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
29 // X86 Specific DAG Nodes
31 // Start the numbering where the builtin ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 /// BSF - Bit scan forward.
35 /// BSR - Bit scan reverse.
39 /// SHLD, SHRD - Double shift instructions. These correspond to
40 /// X86::SHLDxx and X86::SHRDxx instructions.
44 /// FAND - Bitwise logical AND of floating point values. This corresponds
45 /// to X86::ANDPS or X86::ANDPD.
48 /// FOR - Bitwise logical OR of floating point values. This corresponds
49 /// to X86::ORPS or X86::ORPD.
52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
53 /// to X86::XORPS or X86::XORPD.
56 /// FSRL - Bitwise logical right shift of floating point values. These
57 /// corresponds to X86::PSRLDQ.
60 /// CALL - These operations represent an abstract X86 call
61 /// instruction, which includes a bunch of information. In particular the
62 /// operands of these node are:
64 /// #0 - The incoming token chain
66 /// #2 - The number of arg bytes the caller pushes on the stack.
67 /// #3 - The number of arg bytes the callee pops off the stack.
68 /// #4 - The value to pass in AL/AX/EAX (optional)
69 /// #5 - The value to pass in DL/DX/EDX (optional)
71 /// The result values of these nodes are:
73 /// #0 - The outgoing token chain
74 /// #1 - The first register result value (optional)
75 /// #2 - The second register result value (optional)
79 /// RDTSC_DAG - This operation implements the lowering for
83 /// X86 compare and logical compare instructions.
86 /// X86 bit-test instructions.
89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
90 /// operand, usually produced by a CMP instruction.
93 // Same as SETCC except it's materialized with a sbb and the value is all
94 // one's or all zero's.
95 SETCC_CARRY, // R = carry_bit ? ~0 : 0
97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
98 /// Operands are two FP values to compare; result is a mask of
99 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
102 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
103 /// result in an integer GPR. Needs masking for scalar result.
106 /// X86 conditional moves. Operand 0 and operand 1 are the two values
107 /// to select from. Operand 2 is the condition code, and operand 3 is the
108 /// flag operand produced by a CMP or TEST instruction. It also writes a
112 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
113 /// is the block to branch if condition is true, operand 2 is the
114 /// condition code, and operand 3 is the flag operand produced by a CMP
115 /// or TEST instruction.
118 /// Return with a flag operand. Operand 0 is the chain operand, operand
119 /// 1 is the number of bytes of stack to pop.
122 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
125 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
128 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
129 /// at function entry, used for PIC code.
132 /// Wrapper - A wrapper node for TargetConstantPool,
133 /// TargetExternalSymbol, and TargetGlobalAddress.
136 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
137 /// relative displacements.
140 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
141 /// to an MMX vector. If you think this is too close to the previous
142 /// mnemonic, so do I; blame Intel.
145 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
146 /// i32, corresponds to X86::PEXTRB.
149 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
150 /// i32, corresponds to X86::PEXTRW.
153 /// INSERTPS - Insert any element of a 4 x float vector into any element
154 /// of a destination 4 x floatvector.
157 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
158 /// corresponds to X86::PINSRB.
161 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
162 /// corresponds to X86::PINSRW.
165 /// PSHUFB - Shuffle 16 8-bit values within a vector.
168 /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
171 /// PSIGN - Copy integer sign.
174 /// BLENDV - Blend where the selector is an XMM.
177 /// BLENDxx - Blend where the selector is an immediate.
182 /// HADD - Integer horizontal add.
185 /// HSUB - Integer horizontal sub.
188 /// FHADD - Floating point horizontal add.
191 /// FHSUB - Floating point horizontal sub.
194 /// FMAX, FMIN - Floating point max and min.
198 /// FMAXC, FMINC - Commutative FMIN and FMAX.
201 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
202 /// approximation. Note that these typically require refinement
203 /// in order to obtain suitable precision.
206 // TLSADDR - Thread Local Storage.
209 // TLSBASEADDR - Thread Local Storage. A call to get the start address
210 // of the TLS block for the current module.
213 // TLSCALL - Thread Local Storage. When calling to an OS provided
214 // thunk at the address from an earlier relocation.
217 // EH_RETURN - Exception Handling helpers.
220 /// TC_RETURN - Tail call return.
222 /// operand #1 callee (register or absolute)
223 /// operand #2 stack adjustment
224 /// operand #3 optional in flag
227 // VZEXT_MOVL - Vector move low and zero extend.
230 // VSEXT_MOVL - Vector move low and sign extend.
233 // VFPEXT - Vector FP extend.
236 // VSHL, VSRL - 128-bit vector logical left / right shift
239 // VSHL, VSRL, VSRA - Vector shift elements
242 // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate
245 // CMPP - Vector packed double/float comparison.
248 // PCMP* - Vector integer comparisons.
251 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
252 ADD, SUB, ADC, SBB, SMUL,
253 INC, DEC, OR, XOR, AND,
255 ANDN, // ANDN - Bitwise AND NOT with FLAGS results.
257 BLSI, // BLSI - Extract lowest set isolated bit
258 BLSMSK, // BLSMSK - Get mask up to lowest set bit
259 BLSR, // BLSR - Reset lowest set bit
261 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
263 // MUL_IMM - X86 specific multiply by immediate.
266 // PTEST - Vector bitwise comparisons
269 // TESTP - Vector packed fp sign bitwise comparisons
272 // Several flavors of instructions with vector shuffle behaviors.
296 // PMULUDQ - Vector multiply packed unsigned doubleword integers
307 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
308 // according to %al. An operator is needed so that this can be expanded
309 // with control flow.
310 VASTART_SAVE_XMM_REGS,
312 // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
315 // SEG_ALLOCA - For allocating variable amounts of stack space when using
316 // segmented stacks. Check if the current stacklet has enough space, and
317 // falls back to heap allocation if not.
320 // WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui.
329 // FNSTSW16r - Store FP status word into i16 register.
332 // SAHF - Store contents of %ah into %eflags.
335 // RDRAND - Get a random integer and indicate whether it is valid in CF.
342 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
343 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
344 // Atomic 64-bit binary operations.
345 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
353 // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
358 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
361 // FNSTCW16m - Store FP control world into i16 memory.
364 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
365 /// integer destination in memory and a FP reg source. This corresponds
366 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
367 /// has two inputs (token chain and address) and two outputs (int value
368 /// and token chain).
373 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
374 /// integer source in memory and FP reg result. This corresponds to the
375 /// X86::FILD*m instructions. It has three inputs (token chain, address,
376 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
377 /// also produces a flag).
381 /// FLD - This instruction implements an extending load to FP stack slots.
382 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
383 /// operand, ptr to load from, and a ValueType node indicating the type
387 /// FST - This instruction implements a truncating store to FP stack
388 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
389 /// chain operand, value to store, address, and a ValueType to store it
393 /// VAARG_64 - This instruction grabs the address of the next argument
394 /// from a va_list. (reads and modifies the va_list in memory)
397 // WARNING: Do not add anything in the end unless you want the node to
398 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
399 // thought as target memory ops!
403 /// Define some predicates that are used for node matching.
405 /// isVEXTRACTF128Index - Return true if the specified
406 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
407 /// suitable for input to VEXTRACTF128.
408 bool isVEXTRACTF128Index(SDNode *N);
410 /// isVINSERTF128Index - Return true if the specified
411 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
412 /// suitable for input to VINSERTF128.
413 bool isVINSERTF128Index(SDNode *N);
415 /// getExtractVEXTRACTF128Immediate - Return the appropriate
416 /// immediate to extract the specified EXTRACT_SUBVECTOR index
417 /// with VEXTRACTF128 instructions.
418 unsigned getExtractVEXTRACTF128Immediate(SDNode *N);
420 /// getInsertVINSERTF128Immediate - Return the appropriate
421 /// immediate to insert at the specified INSERT_SUBVECTOR index
422 /// with VINSERTF128 instructions.
423 unsigned getInsertVINSERTF128Immediate(SDNode *N);
425 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
427 bool isZeroNode(SDValue Elt);
429 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
430 /// fit into displacement field of the instruction.
431 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
432 bool hasSymbolicDisplacement = true);
435 /// isCalleePop - Determines whether the callee is required to pop its
436 /// own arguments. Callee pop is necessary to support tail calls.
437 bool isCalleePop(CallingConv::ID CallingConv,
438 bool is64Bit, bool IsVarArg, bool TailCallOpt);
441 //===--------------------------------------------------------------------===//
442 // X86TargetLowering - X86 Implementation of the TargetLowering interface
443 class X86TargetLowering : public TargetLowering {
445 explicit X86TargetLowering(X86TargetMachine &TM);
447 virtual unsigned getJumpTableEncoding() const;
449 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
451 virtual const MCExpr *
452 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
453 const MachineBasicBlock *MBB, unsigned uid,
454 MCContext &Ctx) const;
456 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
458 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
459 SelectionDAG &DAG) const;
460 virtual const MCExpr *
461 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
462 unsigned JTI, MCContext &Ctx) const;
464 /// getStackPtrReg - Return the stack pointer register we are using: either
466 unsigned getStackPtrReg() const { return X86StackPtr; }
468 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
469 /// function arguments in the caller parameter area. For X86, aggregates
470 /// that contains are placed at 16-byte boundaries while the rest are at
471 /// 4-byte boundaries.
472 virtual unsigned getByValTypeAlignment(Type *Ty) const;
474 /// getOptimalMemOpType - Returns the target specific optimal type for load
475 /// and store operations as a result of memset, memcpy, and memmove
476 /// lowering. If DstAlign is zero that means it's safe to destination
477 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
478 /// means there isn't a need to check it against alignment requirement,
479 /// probably because the source does not need to be loaded. If
480 /// 'IsZeroVal' is true, that means it's safe to return a
481 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
482 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
483 /// constant so it does not need to be loaded.
484 /// It returns EVT::Other if the type should be determined using generic
485 /// target-independent logic.
487 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
488 bool IsZeroVal, bool MemcpyStrSrc,
489 MachineFunction &MF) const;
491 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
492 /// unaligned memory accesses. of the specified type.
493 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
497 /// LowerOperation - Provide custom lowering hooks for some operations.
499 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
501 /// ReplaceNodeResults - Replace the results of node with an illegal result
502 /// type with new values built out of custom code.
504 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
505 SelectionDAG &DAG) const;
508 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
510 /// isTypeDesirableForOp - Return true if the target has native support for
511 /// the specified value type and it is 'desirable' to use the type for the
512 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
513 /// instruction encodings are longer and some i16 instructions are slow.
514 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
516 /// isTypeDesirable - Return true if the target has native support for the
517 /// specified value type and it is 'desirable' to use the type. e.g. On x86
518 /// i16 is legal, but undesirable since i16 instruction encodings are longer
519 /// and some i16 instructions are slow.
520 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
522 virtual MachineBasicBlock *
523 EmitInstrWithCustomInserter(MachineInstr *MI,
524 MachineBasicBlock *MBB) const;
527 /// getTargetNodeName - This method returns the name of a target specific
529 virtual const char *getTargetNodeName(unsigned Opcode) const;
531 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
532 virtual EVT getSetCCResultType(EVT VT) const;
534 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
535 /// in Mask are known to be either zero or one and return them in the
536 /// KnownZero/KnownOne bitsets.
537 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
540 const SelectionDAG &DAG,
541 unsigned Depth = 0) const;
543 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
544 // operation that are sign bits.
545 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
546 unsigned Depth) const;
549 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
551 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
553 virtual bool ExpandInlineAsm(CallInst *CI) const;
555 ConstraintType getConstraintType(const std::string &Constraint) const;
557 /// Examine constraint string and operand type and determine a weight value.
558 /// The operand object must already have been set up with the operand type.
559 virtual ConstraintWeight getSingleConstraintMatchWeight(
560 AsmOperandInfo &info, const char *constraint) const;
562 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
564 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
565 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
566 /// true it means one of the asm constraint of the inline asm instruction
567 /// being processed is 'm'.
568 virtual void LowerAsmOperandForConstraint(SDValue Op,
569 std::string &Constraint,
570 std::vector<SDValue> &Ops,
571 SelectionDAG &DAG) const;
573 /// getRegForInlineAsmConstraint - Given a physical register constraint
574 /// (e.g. {edx}), return the register number and the register class for the
575 /// register. This should only be used for C_Register constraints. On
576 /// error, this returns a register number of 0.
577 std::pair<unsigned, const TargetRegisterClass*>
578 getRegForInlineAsmConstraint(const std::string &Constraint,
581 /// isLegalAddressingMode - Return true if the addressing mode represented
582 /// by AM is legal for this target, for a load/store of the specified type.
583 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
585 /// isLegalICmpImmediate - Return true if the specified immediate is legal
586 /// icmp immediate, that is the target has icmp instructions which can
587 /// compare a register against the immediate without having to materialize
588 /// the immediate into a register.
589 virtual bool isLegalICmpImmediate(int64_t Imm) const;
591 /// isLegalAddImmediate - Return true if the specified immediate is legal
592 /// add immediate, that is the target has add instructions which can
593 /// add a register and the immediate without having to materialize
594 /// the immediate into a register.
595 virtual bool isLegalAddImmediate(int64_t Imm) const;
597 /// isTruncateFree - Return true if it's free to truncate a value of
598 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
599 /// register EAX to i16 by referencing its sub-register AX.
600 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
601 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
603 /// isZExtFree - Return true if any actual instruction that defines a
604 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
605 /// register. This does not necessarily include registers defined in
606 /// unknown ways, such as incoming arguments, or copies from unknown
607 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
608 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
609 /// all instructions that define 32-bit values implicit zero-extend the
610 /// result out to 64 bits.
611 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
612 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
614 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
615 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
616 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
617 /// is expanded to mul + add.
618 virtual bool isFMAFasterThanMulAndAdd(EVT) const { return true; }
620 /// isNarrowingProfitable - Return true if it's profitable to narrow
621 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
622 /// from i32 to i8 but not from i32 to i16.
623 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
625 /// isFPImmLegal - Returns true if the target can instruction select the
626 /// specified FP immediate natively. If false, the legalizer will
627 /// materialize the FP immediate as a load from a constant pool.
628 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
630 /// isShuffleMaskLegal - Targets can use this to indicate that they only
631 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
632 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
633 /// values are assumed to be legal.
634 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
637 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
638 /// used by Targets can use this to indicate if there is a suitable
639 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
641 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
644 /// ShouldShrinkFPConstant - If true, then instruction selection should
645 /// seek to shrink the FP constant of the specified type to a smaller type
646 /// in order to save space and / or reduce runtime.
647 virtual bool ShouldShrinkFPConstant(EVT VT) const {
648 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
649 // expensive than a straight movsd. On the other hand, it's important to
650 // shrink long double fp constant since fldt is very slow.
651 return !X86ScalarSSEf64 || VT == MVT::f80;
654 const X86Subtarget* getSubtarget() const {
658 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
659 /// computed in an SSE register, not on the X87 floating point stack.
660 bool isScalarFPTypeInSSEReg(EVT VT) const {
661 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
662 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
665 /// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine
667 bool isTargetFTOL() const {
668 return Subtarget->isTargetWindows() && !Subtarget->is64Bit();
671 /// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be
672 /// used for fptoui to the given type.
673 bool isIntegerTypeFTOL(EVT VT) const {
674 return isTargetFTOL() && VT == MVT::i64;
677 /// createFastISel - This method returns a target specific FastISel object,
678 /// or null if the target does not support "fast" ISel.
679 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
680 const TargetLibraryInfo *libInfo) const;
682 /// getStackCookieLocation - Return true if the target stores stack
683 /// protector cookies at a fixed offset in some non-standard address
684 /// space, and populates the address space and offset as
686 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
688 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
689 SelectionDAG &DAG) const;
692 std::pair<const TargetRegisterClass*, uint8_t>
693 findRepresentativeClass(EVT VT) const;
696 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
697 /// make the right decision when generating code for different targets.
698 const X86Subtarget *Subtarget;
699 const X86RegisterInfo *RegInfo;
700 const TargetData *TD;
702 /// X86StackPtr - X86 physical register used as stack ptr.
703 unsigned X86StackPtr;
705 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
706 /// floating point ops.
707 /// When SSE is available, use it for f32 operations.
708 /// When SSE2 is available, use it for f64 operations.
709 bool X86ScalarSSEf32;
710 bool X86ScalarSSEf64;
712 /// LegalFPImmediates - A list of legal fp immediates.
713 std::vector<APFloat> LegalFPImmediates;
715 /// addLegalFPImmediate - Indicate that this x86 target can instruction
716 /// select the specified FP immediate natively.
717 void addLegalFPImmediate(const APFloat& Imm) {
718 LegalFPImmediates.push_back(Imm);
721 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
722 CallingConv::ID CallConv, bool isVarArg,
723 const SmallVectorImpl<ISD::InputArg> &Ins,
724 DebugLoc dl, SelectionDAG &DAG,
725 SmallVectorImpl<SDValue> &InVals) const;
726 SDValue LowerMemArgument(SDValue Chain,
727 CallingConv::ID CallConv,
728 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
729 DebugLoc dl, SelectionDAG &DAG,
730 const CCValAssign &VA, MachineFrameInfo *MFI,
732 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
733 DebugLoc dl, SelectionDAG &DAG,
734 const CCValAssign &VA,
735 ISD::ArgFlagsTy Flags) const;
737 // Call lowering helpers.
739 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
740 /// for tail call optimization. Targets which want to do tail call
741 /// optimization should implement this function.
742 bool IsEligibleForTailCallOptimization(SDValue Callee,
743 CallingConv::ID CalleeCC,
745 bool isCalleeStructRet,
746 bool isCallerStructRet,
747 const SmallVectorImpl<ISD::OutputArg> &Outs,
748 const SmallVectorImpl<SDValue> &OutVals,
749 const SmallVectorImpl<ISD::InputArg> &Ins,
750 SelectionDAG& DAG) const;
751 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
752 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
753 SDValue Chain, bool IsTailCall, bool Is64Bit,
754 int FPDiff, DebugLoc dl) const;
756 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
757 SelectionDAG &DAG) const;
759 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
761 bool isReplace) const;
763 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
764 SelectionDAG &DAG) const;
765 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
766 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
767 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
768 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
769 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
770 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
771 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
772 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
773 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
774 int64_t Offset, SelectionDAG &DAG) const;
775 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
776 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
777 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
778 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
779 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const;
780 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
781 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
782 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
783 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
784 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
785 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
786 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
787 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
788 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
789 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
790 DebugLoc dl, SelectionDAG &DAG) const;
791 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
792 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
793 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
794 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
795 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
796 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
797 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
798 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
799 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
800 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
801 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
802 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
803 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
804 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
805 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
806 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
808 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
810 // Utility functions to help LowerVECTOR_SHUFFLE
811 SDValue LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const;
812 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const;
814 SDValue LowerVectorAllZeroTest(SDValue Op, SelectionDAG &DAG) const;
816 SDValue LowerVectorFpExtend(SDValue &Op, SelectionDAG &DAG) const;
819 LowerFormalArguments(SDValue Chain,
820 CallingConv::ID CallConv, bool isVarArg,
821 const SmallVectorImpl<ISD::InputArg> &Ins,
822 DebugLoc dl, SelectionDAG &DAG,
823 SmallVectorImpl<SDValue> &InVals) const;
825 LowerCall(CallLoweringInfo &CLI,
826 SmallVectorImpl<SDValue> &InVals) const;
829 LowerReturn(SDValue Chain,
830 CallingConv::ID CallConv, bool isVarArg,
831 const SmallVectorImpl<ISD::OutputArg> &Outs,
832 const SmallVectorImpl<SDValue> &OutVals,
833 DebugLoc dl, SelectionDAG &DAG) const;
835 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
837 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
840 getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
841 ISD::NodeType ExtendKind) const;
844 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
846 const SmallVectorImpl<ISD::OutputArg> &Outs,
847 LLVMContext &Context) const;
849 /// Utility function to emit string processing sse4.2 instructions
850 /// that return in xmm0.
851 /// This takes the instruction to expand, the associated machine basic
852 /// block, the number of args, and whether or not the second arg is
853 /// in memory or not.
854 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
855 unsigned argNum, bool inMem) const;
857 /// Utility functions to emit monitor and mwait instructions. These
858 /// need to make sure that the arguments to the intrinsic are in the
859 /// correct registers.
860 MachineBasicBlock *EmitMonitor(MachineInstr *MI,
861 MachineBasicBlock *BB) const;
862 MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const;
864 /// Utility function to emit atomic bitwise operations (and, or, xor).
865 /// It takes the bitwise instruction to expand, the associated machine basic
866 /// block, and the associated X86 opcodes for reg/reg and reg/imm.
867 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
868 MachineInstr *BInstr,
869 MachineBasicBlock *BB,
876 const TargetRegisterClass *RC,
877 bool Invert = false) const;
879 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
880 MachineInstr *BInstr,
881 MachineBasicBlock *BB,
886 bool Invert = false) const;
888 /// Utility function to emit atomic min and max. It takes the min/max
889 /// instruction to expand, the associated basic block, and the associated
890 /// cmov opcode for moving the min or max value.
891 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
892 MachineBasicBlock *BB,
893 unsigned cmovOpc) const;
895 // Utility function to emit the low-level va_arg code for X86-64.
896 MachineBasicBlock *EmitVAARG64WithCustomInserter(
898 MachineBasicBlock *MBB) const;
900 /// Utility function to emit the xmm reg save portion of va_start.
901 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
902 MachineInstr *BInstr,
903 MachineBasicBlock *BB) const;
905 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
906 MachineBasicBlock *BB) const;
908 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
909 MachineBasicBlock *BB) const;
911 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
912 MachineBasicBlock *BB,
915 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
916 MachineBasicBlock *BB) const;
918 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
919 MachineBasicBlock *BB) const;
921 /// Emit nodes that will be selected as "test Op0,Op0", or something
922 /// equivalent, for use with the given x86 condition code.
923 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
925 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
926 /// equivalent, for use with the given x86 condition code.
927 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
928 SelectionDAG &DAG) const;
930 /// Convert a comparison if required by the subtarget.
931 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
935 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
936 const TargetLibraryInfo *libInfo);
940 #endif // X86ISELLOWERING_H