1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
24 // X86 Specific DAG Nodes
26 // Start the numbering where the builtin ops leave off.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
29 /// SHLD, SHRD - Double shift instructions. These correspond to
30 /// X86::SHLDxx and X86::SHRDxx instructions.
34 /// FAND - Bitwise logical AND of floating point values. This corresponds
35 /// to X86::ANDPS or X86::ANDPD.
38 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
39 /// to X86::XORPS or X86::XORPD.
42 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
43 /// integer source in memory and FP reg result. This corresponds to the
44 /// X86::FILD*m instructions. It has three inputs (token chain, address,
45 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
46 /// also produces a flag).
50 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
51 /// integer destination in memory and a FP reg source. This corresponds
52 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
53 /// has two inputs (token chain and address) and two outputs (int value and
59 /// FLD - This instruction implements an extending load to FP stack slots.
60 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
61 /// operand, ptr to load from, and a ValueType node indicating the type
65 /// FST - This instruction implements a truncating store to FP stack
66 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
67 /// chain operand, value to store, address, and a ValueType to store it
71 /// FP_SET_RESULT - This corresponds to FpGETRESULT pseudo instrcuction
72 /// which copies from ST(0) to the destination. It takes a chain and writes
73 /// a RFP result and a chain.
76 /// FP_SET_RESULT - This corresponds to FpSETRESULT pseudo instrcuction
77 /// which copies the source operand to ST(0). It takes a chain and writes
78 /// a chain and a flag.
81 /// CALL/TAILCALL - These operations represent an abstract X86 call
82 /// instruction, which includes a bunch of information. In particular the
83 /// operands of these node are:
85 /// #0 - The incoming token chain
87 /// #2 - The number of arg bytes the caller pushes on the stack.
88 /// #3 - The number of arg bytes the callee pops off the stack.
89 /// #4 - The value to pass in AL/AX/EAX (optional)
90 /// #5 - The value to pass in DL/DX/EDX (optional)
92 /// The result values of these nodes are:
94 /// #0 - The outgoing token chain
95 /// #1 - The first register result value (optional)
96 /// #2 - The second register result value (optional)
98 /// The CALL vs TAILCALL distinction boils down to whether the callee is
99 /// known not to modify the caller's stack frame, as is standard with
104 /// RDTSC_DAG - This operation implements the lowering for
108 /// X86 compare and logical compare instructions.
109 CMP, TEST, COMI, UCOMI,
111 /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
112 /// operand produced by a CMP instruction.
115 /// X86 conditional moves. Operand 1 and operand 2 are the two values
116 /// to select from (operand 1 is a R/W operand). Operand 3 is the condition
117 /// code, and operand 4 is the flag operand produced by a CMP or TEST
118 /// instruction. It also writes a flag result.
121 /// X86 conditional branches. Operand 1 is the chain operand, operand 2
122 /// is the block to branch if condition is true, operand 3 is the
123 /// condition code, and operand 4 is the flag operand produced by a CMP
124 /// or TEST instruction.
127 /// Return with a flag operand. Operand 1 is the chain operand, operand
128 /// 2 is the number of bytes of stack to pop.
131 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
134 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
137 /// LOAD_PACK Load a 128-bit packed float / double value. It has the same
138 /// operands as a normal load.
141 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
142 /// at function entry, used for PIC code.
145 /// TCPWrapper - A wrapper node for TargetConstantPool,
146 /// TargetExternalSymbol, and TargetGlobalAddress.
149 /// S2VEC - X86 version of SCALAR_TO_VECTOR. The destination base does not
150 /// have to match the operand type.
153 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
154 /// i32, corresponds to X86::PEXTRW.
157 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
158 /// corresponds to X86::PINSRW.
162 // X86 specific condition code. These correspond to X86_*_COND in
163 // X86InstrInfo.td. They must be kept in synch.
185 /// Define some predicates that are used for node matching.
187 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
188 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
189 bool isPSHUFDMask(SDNode *N);
191 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
192 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
193 bool isPSHUFHWMask(SDNode *N);
195 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
196 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
197 bool isPSHUFLWMask(SDNode *N);
199 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
200 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
201 bool isSHUFPMask(SDNode *N);
203 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
204 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
205 bool isMOVHLPSMask(SDNode *N);
207 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
208 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
209 bool isMOVLPMask(SDNode *N);
211 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
212 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
213 /// as well as MOVLHPS.
214 bool isMOVHPMask(SDNode *N);
216 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
217 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
218 bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false);
220 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
221 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
222 bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false);
224 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
225 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
227 bool isUNPCKL_v_undef_Mask(SDNode *N);
229 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
230 /// specifies a shuffle of elements that is suitable for input to MOVSS,
231 /// MOVSD, and MOVD, i.e. setting the lowest element.
232 bool isMOVLMask(SDNode *N);
234 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
235 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
236 bool isMOVSHDUPMask(SDNode *N);
238 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
239 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
240 bool isMOVSLDUPMask(SDNode *N);
242 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
243 /// specifies a splat of a single element.
244 bool isSplatMask(SDNode *N);
246 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
247 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
249 unsigned getShuffleSHUFImmediate(SDNode *N);
251 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
252 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
254 unsigned getShufflePSHUFHWImmediate(SDNode *N);
256 /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
257 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
259 unsigned getShufflePSHUFLWImmediate(SDNode *N);
262 //===----------------------------------------------------------------------===//
263 // X86TargetLowering - X86 Implementation of the TargetLowering interface
264 class X86TargetLowering : public TargetLowering {
265 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
266 int ReturnAddrIndex; // FrameIndex for return slot.
267 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
268 int BytesCallerReserves; // Number of arg bytes caller makes.
270 X86TargetLowering(TargetMachine &TM);
272 // Return the number of bytes that a function should pop when it returns (in
273 // addition to the space used by the return address).
275 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
277 // Return the number of bytes that the caller reserves for arguments passed
279 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
281 /// LowerOperation - Provide custom lowering hooks for some operations.
283 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
285 virtual std::pair<SDOperand, SDOperand>
286 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
289 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
290 MachineBasicBlock *MBB);
292 /// getTargetNodeName - This method returns the name of a target specific
294 virtual const char *getTargetNodeName(unsigned Opcode) const;
296 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
297 /// in Mask are known to be either zero or one and return them in the
298 /// KnownZero/KnownOne bitsets.
299 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
303 unsigned Depth = 0) const;
305 SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
307 std::vector<unsigned>
308 getRegClassForInlineAsmConstraint(const std::string &Constraint,
309 MVT::ValueType VT) const;
311 /// isLegalAddressImmediate - Return true if the integer value or
312 /// GlobalValue can be used as the offset of the target addressing mode.
313 virtual bool isLegalAddressImmediate(int64_t V) const;
314 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
316 /// isShuffleMaskLegal - Targets can use this to indicate that they only
317 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
318 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
319 /// are assumed to be legal.
320 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
322 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
323 /// used by Targets can use this to indicate if there is a suitable
324 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
326 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
328 SelectionDAG &DAG) const;
330 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
331 /// make the right decision when generating code for different targets.
332 const X86Subtarget *Subtarget;
334 /// X86ScalarSSE - Select between SSE2 or x87 floating point ops.
337 // C Calling Convention implementation.
338 SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG);
339 SDOperand LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG);
341 // Fast Calling Convention implementation.
342 SDOperand LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG);
343 SDOperand LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG);
345 SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
346 SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
347 SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
348 SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
349 SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
350 SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
351 SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
352 SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG);
353 SDOperand LowerShift(SDOperand Op, SelectionDAG &DAG);
354 SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
355 SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
356 SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
357 SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
358 SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
359 SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
360 SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
361 SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
362 SDOperand LowerMEMCPY(SDOperand Op, SelectionDAG &DAG);
363 SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
364 SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
365 SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
366 SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
367 SDOperand LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG);
368 SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
369 SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
373 // FASTCC_NUM_INT_ARGS_INREGS - This is the max number of integer arguments
374 // to pass in registers. 0 is none, 1 is is "use EAX", 2 is "use EAX and
375 // EDX". Anything more is illegal.
377 // FIXME: The linscan register allocator currently has problem with
378 // coalescing. At the time of this writing, whenever it decides to coalesce
379 // a physreg with a virtreg, this increases the size of the physreg's live
380 // range, and the live range cannot ever be reduced. This causes problems if
381 // too many physregs are coaleced with virtregs, which can cause the register
382 // allocator to wedge itself.
384 // This code triggers this problem more often if we pass args in registers,
385 // so disable it until this is fixed.
387 #define FASTCC_NUM_INT_ARGS_INREGS 0
389 #endif // X86ISELLOWERING_H