1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
29 // X86 Specific DAG Nodes
31 // Start the numbering where the builtin ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 /// BSF - Bit scan forward.
35 /// BSR - Bit scan reverse.
39 /// SHLD, SHRD - Double shift instructions. These correspond to
40 /// X86::SHLDxx and X86::SHRDxx instructions.
44 /// FAND - Bitwise logical AND of floating point values. This corresponds
45 /// to X86::ANDPS or X86::ANDPD.
48 /// FOR - Bitwise logical OR of floating point values. This corresponds
49 /// to X86::ORPS or X86::ORPD.
52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
53 /// to X86::XORPS or X86::XORPD.
56 /// FSRL - Bitwise logical right shift of floating point values. These
57 /// corresponds to X86::PSRLDQ.
60 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
61 /// integer source in memory and FP reg result. This corresponds to the
62 /// X86::FILD*m instructions. It has three inputs (token chain, address,
63 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
64 /// also produces a flag).
68 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
69 /// integer destination in memory and a FP reg source. This corresponds
70 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
71 /// has two inputs (token chain and address) and two outputs (int value
77 /// FLD - This instruction implements an extending load to FP stack slots.
78 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
79 /// operand, ptr to load from, and a ValueType node indicating the type
83 /// FST - This instruction implements a truncating store to FP stack
84 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
85 /// chain operand, value to store, address, and a ValueType to store it
89 /// CALL - These operations represent an abstract X86 call
90 /// instruction, which includes a bunch of information. In particular the
91 /// operands of these node are:
93 /// #0 - The incoming token chain
95 /// #2 - The number of arg bytes the caller pushes on the stack.
96 /// #3 - The number of arg bytes the callee pops off the stack.
97 /// #4 - The value to pass in AL/AX/EAX (optional)
98 /// #5 - The value to pass in DL/DX/EDX (optional)
100 /// The result values of these nodes are:
102 /// #0 - The outgoing token chain
103 /// #1 - The first register result value (optional)
104 /// #2 - The second register result value (optional)
108 /// RDTSC_DAG - This operation implements the lowering for
112 /// X86 compare and logical compare instructions.
115 /// X86 bit-test instructions.
118 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the flag
119 /// operand produced by a CMP instruction.
122 // Same as SETCC except it's materialized with a sbb and the value is all
123 // one's or all zero's.
126 /// X86 conditional moves. Operand 0 and operand 1 are the two values
127 /// to select from. Operand 2 is the condition code, and operand 3 is the
128 /// flag operand produced by a CMP or TEST instruction. It also writes a
132 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
133 /// is the block to branch if condition is true, operand 2 is the
134 /// condition code, and operand 3 is the flag operand produced by a CMP
135 /// or TEST instruction.
138 /// Return with a flag operand. Operand 0 is the chain operand, operand
139 /// 1 is the number of bytes of stack to pop.
142 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
145 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
148 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
149 /// at function entry, used for PIC code.
152 /// Wrapper - A wrapper node for TargetConstantPool,
153 /// TargetExternalSymbol, and TargetGlobalAddress.
156 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
157 /// relative displacements.
160 /// MOVQ2DQ - Copies a 64-bit value from a vector to another vector.
161 /// Can be used to move a vector value from a MMX register to a XMM
165 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
166 /// i32, corresponds to X86::PEXTRB.
169 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
170 /// i32, corresponds to X86::PEXTRW.
173 /// INSERTPS - Insert any element of a 4 x float vector into any element
174 /// of a destination 4 x floatvector.
177 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
178 /// corresponds to X86::PINSRB.
181 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
182 /// corresponds to X86::PINSRW.
185 /// PSHUFB - Shuffle 16 8-bit values within a vector.
188 /// FMAX, FMIN - Floating point max and min.
192 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
193 /// approximation. Note that these typically require refinement
194 /// in order to obtain suitable precision.
197 // TLSADDR - Thread Local Storage.
200 // TLSCALL - Thread Local Storage. When calling to an OS provided
201 // thunk at the address from an earlier relocation.
204 // SegmentBaseAddress - The address segment:0
207 // EH_RETURN - Exception Handling helpers.
210 /// TC_RETURN - Tail call return.
212 /// operand #1 callee (register or absolute)
213 /// operand #2 stack adjustment
214 /// operand #3 optional in flag
217 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
221 // FNSTCW16m - Store FP control world into i16 memory.
224 // VZEXT_MOVL - Vector move low and zero extend.
227 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
230 // VSHL, VSRL - Vector logical left / right shift.
233 // CMPPD, CMPPS - Vector double/float comparison.
234 // CMPPD, CMPPS - Vector double/float comparison.
237 // PCMP* - Vector integer comparisons.
238 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
239 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
241 // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results.
242 ADD, SUB, SMUL, UMUL,
243 INC, DEC, OR, XOR, AND,
245 // MUL_IMM - X86 specific multiply by immediate.
248 // PTEST - Vector bitwise comparisons
251 // TESTP - Vector packed fp sign bitwise comparisons
254 // Several flavors of instructions with vector shuffle behaviors.
291 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
292 // according to %al. An operator is needed so that this can be expanded
293 // with control flow.
294 VASTART_SAVE_XMM_REGS,
296 // MINGW_ALLOCA - MingW's __alloca call to do stack probing.
299 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
300 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
301 // Atomic 64-bit binary operations.
302 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
316 // WARNING: Do not add anything in the end unless you want the node to
317 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
318 // thought as target memory ops!
322 /// Define some predicates that are used for node matching.
324 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
325 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
326 bool isPSHUFDMask(ShuffleVectorSDNode *N);
328 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
329 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
330 bool isPSHUFHWMask(ShuffleVectorSDNode *N);
332 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
333 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
334 bool isPSHUFLWMask(ShuffleVectorSDNode *N);
336 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
337 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
338 bool isSHUFPMask(ShuffleVectorSDNode *N);
340 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
341 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
342 bool isMOVHLPSMask(ShuffleVectorSDNode *N);
344 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
345 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
347 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N);
349 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
350 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}.
351 bool isMOVLPMask(ShuffleVectorSDNode *N);
353 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
354 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}.
355 /// as well as MOVLHPS.
356 bool isMOVLHPSMask(ShuffleVectorSDNode *N);
358 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
359 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
360 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
362 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
363 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
364 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
366 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
367 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
369 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N);
371 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
372 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
374 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N);
376 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
377 /// specifies a shuffle of elements that is suitable for input to MOVSS,
378 /// MOVSD, and MOVD, i.e. setting the lowest element.
379 bool isMOVLMask(ShuffleVectorSDNode *N);
381 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
382 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
383 bool isMOVSHDUPMask(ShuffleVectorSDNode *N);
385 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
386 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
387 bool isMOVSLDUPMask(ShuffleVectorSDNode *N);
389 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
390 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
391 bool isMOVDDUPMask(ShuffleVectorSDNode *N);
393 /// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand
394 /// specifies a shuffle of elements that is suitable for input to PALIGNR.
395 bool isPALIGNRMask(ShuffleVectorSDNode *N);
397 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
398 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
400 unsigned getShuffleSHUFImmediate(SDNode *N);
402 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
403 /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction.
404 unsigned getShufflePSHUFHWImmediate(SDNode *N);
406 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
407 /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction.
408 unsigned getShufflePSHUFLWImmediate(SDNode *N);
410 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
411 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
412 unsigned getShufflePALIGNRImmediate(SDNode *N);
414 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
416 bool isZeroNode(SDValue Elt);
418 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
419 /// fit into displacement field of the instruction.
420 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
421 bool hasSymbolicDisplacement = true);
424 //===--------------------------------------------------------------------===//
425 // X86TargetLowering - X86 Implementation of the TargetLowering interface
426 class X86TargetLowering : public TargetLowering {
428 explicit X86TargetLowering(X86TargetMachine &TM);
430 /// getPICBaseSymbol - Return the X86-32 PIC base.
431 MCSymbol *getPICBaseSymbol(const MachineFunction *MF, MCContext &Ctx) const;
433 virtual unsigned getJumpTableEncoding() const;
435 virtual const MCExpr *
436 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
437 const MachineBasicBlock *MBB, unsigned uid,
438 MCContext &Ctx) const;
440 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
442 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
443 SelectionDAG &DAG) const;
444 virtual const MCExpr *
445 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
446 unsigned JTI, MCContext &Ctx) const;
448 /// getStackPtrReg - Return the stack pointer register we are using: either
450 unsigned getStackPtrReg() const { return X86StackPtr; }
452 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
453 /// function arguments in the caller parameter area. For X86, aggregates
454 /// that contains are placed at 16-byte boundaries while the rest are at
455 /// 4-byte boundaries.
456 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
458 /// getOptimalMemOpType - Returns the target specific optimal type for load
459 /// and store operations as a result of memset, memcpy, and memmove
460 /// lowering. If DstAlign is zero that means it's safe to destination
461 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
462 /// means there isn't a need to check it against alignment requirement,
463 /// probably because the source does not need to be loaded. If
464 /// 'NonScalarIntSafe' is true, that means it's safe to return a
465 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
466 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
467 /// constant so it does not need to be loaded.
468 /// It returns EVT::Other if the type should be determined using generic
469 /// target-independent logic.
471 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
472 bool NonScalarIntSafe, bool MemcpyStrSrc,
473 MachineFunction &MF) const;
475 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
476 /// unaligned memory accesses. of the specified type.
477 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
481 /// LowerOperation - Provide custom lowering hooks for some operations.
483 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
485 /// ReplaceNodeResults - Replace the results of node with an illegal result
486 /// type with new values built out of custom code.
488 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
489 SelectionDAG &DAG) const;
492 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
494 /// isTypeDesirableForOp - Return true if the target has native support for
495 /// the specified value type and it is 'desirable' to use the type for the
496 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
497 /// instruction encodings are longer and some i16 instructions are slow.
498 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
500 /// isTypeDesirable - Return true if the target has native support for the
501 /// specified value type and it is 'desirable' to use the type. e.g. On x86
502 /// i16 is legal, but undesirable since i16 instruction encodings are longer
503 /// and some i16 instructions are slow.
504 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
506 virtual MachineBasicBlock *
507 EmitInstrWithCustomInserter(MachineInstr *MI,
508 MachineBasicBlock *MBB) const;
511 /// getTargetNodeName - This method returns the name of a target specific
513 virtual const char *getTargetNodeName(unsigned Opcode) const;
515 /// getSetCCResultType - Return the ISD::SETCC ValueType
516 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
518 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
519 /// in Mask are known to be either zero or one and return them in the
520 /// KnownZero/KnownOne bitsets.
521 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
525 const SelectionDAG &DAG,
526 unsigned Depth = 0) const;
529 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
531 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
533 virtual bool ExpandInlineAsm(CallInst *CI) const;
535 ConstraintType getConstraintType(const std::string &Constraint) const;
537 std::vector<unsigned>
538 getRegClassForInlineAsmConstraint(const std::string &Constraint,
541 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
543 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
544 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
545 /// true it means one of the asm constraint of the inline asm instruction
546 /// being processed is 'm'.
547 virtual void LowerAsmOperandForConstraint(SDValue Op,
548 char ConstraintLetter,
549 std::vector<SDValue> &Ops,
550 SelectionDAG &DAG) const;
552 /// getRegForInlineAsmConstraint - Given a physical register constraint
553 /// (e.g. {edx}), return the register number and the register class for the
554 /// register. This should only be used for C_Register constraints. On
555 /// error, this returns a register number of 0.
556 std::pair<unsigned, const TargetRegisterClass*>
557 getRegForInlineAsmConstraint(const std::string &Constraint,
560 /// isLegalAddressingMode - Return true if the addressing mode represented
561 /// by AM is legal for this target, for a load/store of the specified type.
562 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
564 /// isTruncateFree - Return true if it's free to truncate a value of
565 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
566 /// register EAX to i16 by referencing its sub-register AX.
567 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
568 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
570 /// isZExtFree - Return true if any actual instruction that defines a
571 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
572 /// register. This does not necessarily include registers defined in
573 /// unknown ways, such as incoming arguments, or copies from unknown
574 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
575 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
576 /// all instructions that define 32-bit values implicit zero-extend the
577 /// result out to 64 bits.
578 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const;
579 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
581 /// isNarrowingProfitable - Return true if it's profitable to narrow
582 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
583 /// from i32 to i8 but not from i32 to i16.
584 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
586 /// isFPImmLegal - Returns true if the target can instruction select the
587 /// specified FP immediate natively. If false, the legalizer will
588 /// materialize the FP immediate as a load from a constant pool.
589 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
591 /// isShuffleMaskLegal - Targets can use this to indicate that they only
592 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
593 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
594 /// values are assumed to be legal.
595 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
598 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
599 /// used by Targets can use this to indicate if there is a suitable
600 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
602 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
605 /// ShouldShrinkFPConstant - If true, then instruction selection should
606 /// seek to shrink the FP constant of the specified type to a smaller type
607 /// in order to save space and / or reduce runtime.
608 virtual bool ShouldShrinkFPConstant(EVT VT) const {
609 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
610 // expensive than a straight movsd. On the other hand, it's important to
611 // shrink long double fp constant since fldt is very slow.
612 return !X86ScalarSSEf64 || VT == MVT::f80;
615 const X86Subtarget* getSubtarget() const {
619 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
620 /// computed in an SSE register, not on the X87 floating point stack.
621 bool isScalarFPTypeInSSEReg(EVT VT) const {
622 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
623 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
626 /// createFastISel - This method returns a target specific FastISel object,
627 /// or null if the target does not support "fast" ISel.
628 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
630 /// getFunctionAlignment - Return the Log2 alignment of this function.
631 virtual unsigned getFunctionAlignment(const Function *F) const;
633 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
634 MachineFunction &MF) const;
636 /// getStackCookieLocation - Return true if the target stores stack
637 /// protector cookies at a fixed offset in some non-standard address
638 /// space, and populates the address space and offset as
640 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
643 std::pair<const TargetRegisterClass*, uint8_t>
644 findRepresentativeClass(EVT VT) const;
647 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
648 /// make the right decision when generating code for different targets.
649 const X86Subtarget *Subtarget;
650 const X86RegisterInfo *RegInfo;
651 const TargetData *TD;
653 /// X86StackPtr - X86 physical register used as stack ptr.
654 unsigned X86StackPtr;
656 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
657 /// floating point ops.
658 /// When SSE is available, use it for f32 operations.
659 /// When SSE2 is available, use it for f64 operations.
660 bool X86ScalarSSEf32;
661 bool X86ScalarSSEf64;
663 /// LegalFPImmediates - A list of legal fp immediates.
664 std::vector<APFloat> LegalFPImmediates;
666 /// addLegalFPImmediate - Indicate that this x86 target can instruction
667 /// select the specified FP immediate natively.
668 void addLegalFPImmediate(const APFloat& Imm) {
669 LegalFPImmediates.push_back(Imm);
672 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
673 CallingConv::ID CallConv, bool isVarArg,
674 const SmallVectorImpl<ISD::InputArg> &Ins,
675 DebugLoc dl, SelectionDAG &DAG,
676 SmallVectorImpl<SDValue> &InVals) const;
677 SDValue LowerMemArgument(SDValue Chain,
678 CallingConv::ID CallConv,
679 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
680 DebugLoc dl, SelectionDAG &DAG,
681 const CCValAssign &VA, MachineFrameInfo *MFI,
683 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
684 DebugLoc dl, SelectionDAG &DAG,
685 const CCValAssign &VA,
686 ISD::ArgFlagsTy Flags) const;
688 // Call lowering helpers.
690 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
691 /// for tail call optimization. Targets which want to do tail call
692 /// optimization should implement this function.
693 bool IsEligibleForTailCallOptimization(SDValue Callee,
694 CallingConv::ID CalleeCC,
696 bool isCalleeStructRet,
697 bool isCallerStructRet,
698 const SmallVectorImpl<ISD::OutputArg> &Outs,
699 const SmallVectorImpl<SDValue> &OutVals,
700 const SmallVectorImpl<ISD::InputArg> &Ins,
701 SelectionDAG& DAG) const;
702 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
703 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
704 SDValue Chain, bool IsTailCall, bool Is64Bit,
705 int FPDiff, DebugLoc dl) const;
707 CCAssignFn *CCAssignFnForNode(CallingConv::ID CallConv) const;
708 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
709 SelectionDAG &DAG) const;
711 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
712 bool isSigned) const;
714 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
715 SelectionDAG &DAG) const;
716 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
717 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
718 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
719 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
720 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
721 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
722 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
723 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
724 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
725 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
726 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
727 int64_t Offset, SelectionDAG &DAG) const;
728 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
729 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
730 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
731 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
732 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
733 SelectionDAG &DAG) const;
734 SDValue LowerBIT_CONVERT(SDValue op, SelectionDAG &DAG) const;
735 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
736 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
737 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
738 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
739 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
740 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
741 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
742 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
743 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
744 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
745 DebugLoc dl, SelectionDAG &DAG) const;
746 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
747 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
748 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
749 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
750 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
751 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
752 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
753 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
754 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
755 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
756 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
757 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
758 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
759 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
760 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
761 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
762 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
763 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
764 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
765 SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const;
766 SDValue LowerSHL(SDValue Op, SelectionDAG &DAG) const;
767 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
769 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
770 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
771 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
772 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const;
774 // Utility functions to help LowerVECTOR_SHUFFLE
775 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const;
778 LowerFormalArguments(SDValue Chain,
779 CallingConv::ID CallConv, bool isVarArg,
780 const SmallVectorImpl<ISD::InputArg> &Ins,
781 DebugLoc dl, SelectionDAG &DAG,
782 SmallVectorImpl<SDValue> &InVals) const;
784 LowerCall(SDValue Chain, SDValue Callee,
785 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
786 const SmallVectorImpl<ISD::OutputArg> &Outs,
787 const SmallVectorImpl<SDValue> &OutVals,
788 const SmallVectorImpl<ISD::InputArg> &Ins,
789 DebugLoc dl, SelectionDAG &DAG,
790 SmallVectorImpl<SDValue> &InVals) const;
793 LowerReturn(SDValue Chain,
794 CallingConv::ID CallConv, bool isVarArg,
795 const SmallVectorImpl<ISD::OutputArg> &Outs,
796 const SmallVectorImpl<SDValue> &OutVals,
797 DebugLoc dl, SelectionDAG &DAG) const;
800 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
801 const SmallVectorImpl<ISD::OutputArg> &Outs,
802 LLVMContext &Context) const;
804 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
805 SelectionDAG &DAG, unsigned NewOp) const;
807 /// Utility function to emit string processing sse4.2 instructions
808 /// that return in xmm0.
809 /// This takes the instruction to expand, the associated machine basic
810 /// block, the number of args, and whether or not the second arg is
811 /// in memory or not.
812 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
813 unsigned argNum, bool inMem) const;
815 /// Utility function to emit atomic bitwise operations (and, or, xor).
816 /// It takes the bitwise instruction to expand, the associated machine basic
817 /// block, and the associated X86 opcodes for reg/reg and reg/imm.
818 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
819 MachineInstr *BInstr,
820 MachineBasicBlock *BB,
827 TargetRegisterClass *RC,
828 bool invSrc = false) const;
830 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
831 MachineInstr *BInstr,
832 MachineBasicBlock *BB,
837 bool invSrc = false) const;
839 /// Utility function to emit atomic min and max. It takes the min/max
840 /// instruction to expand, the associated basic block, and the associated
841 /// cmov opcode for moving the min or max value.
842 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
843 MachineBasicBlock *BB,
844 unsigned cmovOpc) const;
846 /// Utility function to emit the xmm reg save portion of va_start.
847 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
848 MachineInstr *BInstr,
849 MachineBasicBlock *BB) const;
851 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
852 MachineBasicBlock *BB) const;
854 MachineBasicBlock *EmitLoweredMingwAlloca(MachineInstr *MI,
855 MachineBasicBlock *BB) const;
857 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
858 MachineBasicBlock *BB) const;
860 /// Emit nodes that will be selected as "test Op0,Op0", or something
861 /// equivalent, for use with the given x86 condition code.
862 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
864 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
865 /// equivalent, for use with the given x86 condition code.
866 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
867 SelectionDAG &DAG) const;
871 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
875 #endif // X86ISELLOWERING_H