1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
26 // X86 Specific DAG Nodes
28 // Start the numbering where the builtin ops leave off.
29 FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
31 /// BSF - Bit scan forward.
32 /// BSR - Bit scan reverse.
36 /// SHLD, SHRD - Double shift instructions. These correspond to
37 /// X86::SHLDxx and X86::SHRDxx instructions.
41 /// FAND - Bitwise logical AND of floating point values. This corresponds
42 /// to X86::ANDPS or X86::ANDPD.
45 /// FOR - Bitwise logical OR of floating point values. This corresponds
46 /// to X86::ORPS or X86::ORPD.
49 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
50 /// to X86::XORPS or X86::XORPD.
53 /// FSRL - Bitwise logical right shift of floating point values. These
54 /// corresponds to X86::PSRLDQ.
57 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
58 /// integer source in memory and FP reg result. This corresponds to the
59 /// X86::FILD*m instructions. It has three inputs (token chain, address,
60 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
61 /// also produces a flag).
65 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
66 /// integer destination in memory and a FP reg source. This corresponds
67 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
68 /// has two inputs (token chain and address) and two outputs (int value
74 /// FLD - This instruction implements an extending load to FP stack slots.
75 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
76 /// operand, ptr to load from, and a ValueType node indicating the type
80 /// FST - This instruction implements a truncating store to FP stack
81 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
82 /// chain operand, value to store, address, and a ValueType to store it
86 /// FP_GET_RESULT - This corresponds to FpGETRESULT pseudo instruction
87 /// which copies from ST(0) to the destination. It takes a chain and
88 /// writes a RFP result and a chain.
91 /// FP_SET_RESULT - This corresponds to FpSETRESULT pseudo instruction
92 /// which copies the source operand to ST(0). It takes a chain+value and
93 /// returns a chain and a flag.
96 /// CALL/TAILCALL - These operations represent an abstract X86 call
97 /// instruction, which includes a bunch of information. In particular the
98 /// operands of these node are:
100 /// #0 - The incoming token chain
102 /// #2 - The number of arg bytes the caller pushes on the stack.
103 /// #3 - The number of arg bytes the callee pops off the stack.
104 /// #4 - The value to pass in AL/AX/EAX (optional)
105 /// #5 - The value to pass in DL/DX/EDX (optional)
107 /// The result values of these nodes are:
109 /// #0 - The outgoing token chain
110 /// #1 - The first register result value (optional)
111 /// #2 - The second register result value (optional)
113 /// The CALL vs TAILCALL distinction boils down to whether the callee is
114 /// known not to modify the caller's stack frame, as is standard with
119 /// RDTSC_DAG - This operation implements the lowering for
123 /// X86 compare and logical compare instructions.
126 /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
127 /// operand produced by a CMP instruction.
130 /// X86 conditional moves. Operand 1 and operand 2 are the two values
131 /// to select from (operand 1 is a R/W operand). Operand 3 is the
132 /// condition code, and operand 4 is the flag operand produced by a CMP
133 /// or TEST instruction. It also writes a flag result.
136 /// X86 conditional branches. Operand 1 is the chain operand, operand 2
137 /// is the block to branch if condition is true, operand 3 is the
138 /// condition code, and operand 4 is the flag operand produced by a CMP
139 /// or TEST instruction.
142 /// Return with a flag operand. Operand 1 is the chain operand, operand
143 /// 2 is the number of bytes of stack to pop.
146 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
149 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
152 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
153 /// at function entry, used for PIC code.
156 /// Wrapper - A wrapper node for TargetConstantPool,
157 /// TargetExternalSymbol, and TargetGlobalAddress.
160 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
161 /// relative displacements.
164 /// S2VEC - X86 version of SCALAR_TO_VECTOR. The destination base does not
165 /// have to match the operand type.
168 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
169 /// i32, corresponds to X86::PEXTRW.
172 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
173 /// corresponds to X86::PINSRW.
176 /// FMAX, FMIN - Floating point max and min.
180 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
181 /// approximation. Note that these typically require refinement
182 /// in order to obtain suitable precision.
185 // Thread Local Storage
186 TLSADDR, THREAD_POINTER,
188 // Exception Handling helpers
193 // operand #1 callee (register or absolute)
194 // operand #2 stack adjustment
195 // operand #3 optional in flag
198 // Store FP control world into i16 memory
203 /// Define some predicates that are used for node matching.
205 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
206 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
207 bool isPSHUFDMask(SDNode *N);
209 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
210 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
211 bool isPSHUFHWMask(SDNode *N);
213 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
214 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
215 bool isPSHUFLWMask(SDNode *N);
217 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
218 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
219 bool isSHUFPMask(SDNode *N);
221 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
222 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
223 bool isMOVHLPSMask(SDNode *N);
225 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
226 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
228 bool isMOVHLPS_v_undef_Mask(SDNode *N);
230 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
231 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
232 bool isMOVLPMask(SDNode *N);
234 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
235 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
236 /// as well as MOVLHPS.
237 bool isMOVHPMask(SDNode *N);
239 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
240 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
241 bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false);
243 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
244 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
245 bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false);
247 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
248 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
250 bool isUNPCKL_v_undef_Mask(SDNode *N);
252 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
253 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
255 bool isUNPCKH_v_undef_Mask(SDNode *N);
257 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
258 /// specifies a shuffle of elements that is suitable for input to MOVSS,
259 /// MOVSD, and MOVD, i.e. setting the lowest element.
260 bool isMOVLMask(SDNode *N);
262 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
263 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
264 bool isMOVSHDUPMask(SDNode *N);
266 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
267 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
268 bool isMOVSLDUPMask(SDNode *N);
270 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
271 /// specifies a splat of a single element.
272 bool isSplatMask(SDNode *N);
274 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
275 /// specifies a splat of zero element.
276 bool isSplatLoMask(SDNode *N);
278 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
279 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
281 unsigned getShuffleSHUFImmediate(SDNode *N);
283 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
284 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
286 unsigned getShufflePSHUFHWImmediate(SDNode *N);
288 /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
289 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
291 unsigned getShufflePSHUFLWImmediate(SDNode *N);
294 //===--------------------------------------------------------------------===//
295 // X86TargetLowering - X86 Implementation of the TargetLowering interface
296 class X86TargetLowering : public TargetLowering {
297 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
298 int RegSaveFrameIndex; // X86-64 vararg func register save area.
299 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
300 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
301 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
302 int BytesCallerReserves; // Number of arg bytes caller makes.
305 explicit X86TargetLowering(TargetMachine &TM);
307 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
309 SDOperand getPICJumpTableRelocBase(SDOperand Table,
310 SelectionDAG &DAG) const;
312 // Return the number of bytes that a function should pop when it returns (in
313 // addition to the space used by the return address).
315 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
317 // Return the number of bytes that the caller reserves for arguments passed
319 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
321 /// getStackPtrReg - Return the stack pointer register we are using: either
323 unsigned getStackPtrReg() const { return X86StackPtr; }
325 /// LowerOperation - Provide custom lowering hooks for some operations.
327 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
329 /// ExpandOperation - Custom lower the specified operation, splitting the
330 /// value into two pieces.
332 virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG);
335 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
337 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
338 MachineBasicBlock *MBB);
340 /// getTargetNodeName - This method returns the name of a target specific
342 virtual const char *getTargetNodeName(unsigned Opcode) const;
344 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
345 /// in Mask are known to be either zero or one and return them in the
346 /// KnownZero/KnownOne bitsets.
347 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
351 const SelectionDAG &DAG,
352 unsigned Depth = 0) const;
354 SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
356 ConstraintType getConstraintType(const std::string &Constraint) const;
358 std::vector<unsigned>
359 getRegClassForInlineAsmConstraint(const std::string &Constraint,
360 MVT::ValueType VT) const;
362 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
363 /// vector. If it is invalid, don't add anything to Ops.
364 virtual void LowerAsmOperandForConstraint(SDOperand Op,
365 char ConstraintLetter,
366 std::vector<SDOperand> &Ops,
369 /// getRegForInlineAsmConstraint - Given a physical register constraint
370 /// (e.g. {edx}), return the register number and the register class for the
371 /// register. This should only be used for C_Register constraints. On
372 /// error, this returns a register number of 0.
373 std::pair<unsigned, const TargetRegisterClass*>
374 getRegForInlineAsmConstraint(const std::string &Constraint,
375 MVT::ValueType VT) const;
377 /// isLegalAddressingMode - Return true if the addressing mode represented
378 /// by AM is legal for this target, for a load/store of the specified type.
379 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
381 /// isTruncateFree - Return true if it's free to truncate a value of
382 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
383 /// register EAX to i16 by referencing its sub-register AX.
384 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
385 virtual bool isTruncateFree(MVT::ValueType VT1, MVT::ValueType VT2) const;
387 /// isShuffleMaskLegal - Targets can use this to indicate that they only
388 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
389 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
390 /// values are assumed to be legal.
391 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
393 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
394 /// used by Targets can use this to indicate if there is a suitable
395 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
397 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
399 SelectionDAG &DAG) const;
401 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
402 /// for tail call optimization. Target which want to do tail call
403 /// optimization should implement this function.
404 virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
406 SelectionDAG &DAG) const;
408 virtual const TargetSubtarget* getSubtarget() {
409 return static_cast<const TargetSubtarget*>(Subtarget);
413 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
414 /// make the right decision when generating code for different targets.
415 const X86Subtarget *Subtarget;
416 const MRegisterInfo *RegInfo;
418 /// X86StackPtr - X86 physical register used as stack ptr.
419 unsigned X86StackPtr;
421 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
422 /// floating point ops.
423 /// When SSE is available, use it for f32 operations.
424 /// When SSE2 is available, use it for f64 operations.
425 bool X86ScalarSSEf32;
426 bool X86ScalarSSEf64;
428 SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall,
429 unsigned CallingConv, SelectionDAG &DAG);
432 SDOperand LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
433 const CCValAssign &VA, MachineFrameInfo *MFI,
434 SDOperand Root, unsigned i);
436 SDOperand LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
437 const SDOperand &StackPtr,
438 const CCValAssign &VA, SDOperand Chain,
441 // C and StdCall Calling Convention implementation.
442 SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
443 bool isStdCall = false);
444 SDOperand LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC);
446 // X86-64 C Calling Convention implementation.
447 SDOperand LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG);
448 SDOperand LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,unsigned CC);
450 // fast calling convention (tail call) implementation for 32/64bit
451 SDOperand LowerX86_TailCallTo(SDOperand Op,
452 SelectionDAG & DAG, unsigned CC);
453 unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG);
454 // Fast and FastCall Calling Convention implementation.
455 SDOperand LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG);
456 SDOperand LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC);
458 std::pair<SDOperand,SDOperand> FP_TO_SINTHelper(SDOperand Op,
461 SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
462 SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
463 SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
464 SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
465 SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
466 SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
467 SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
468 SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
469 SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG);
470 SDOperand LowerShift(SDOperand Op, SelectionDAG &DAG);
471 SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
472 SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
473 SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
474 SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
475 SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG);
476 SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
477 SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
478 SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
479 SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
480 SDOperand LowerMEMCPYInline(SDOperand Dest, SDOperand Source,
481 SDOperand Chain, unsigned Size, unsigned Align,
483 SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
484 SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
485 SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
486 SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG);
487 SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
488 SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
489 SDOperand LowerVACOPY(SDOperand Op, SelectionDAG &DAG);
490 SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
491 SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
492 SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
493 SDOperand LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, SelectionDAG &DAG);
494 SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG);
495 SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG);
496 SDOperand LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG);
497 SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG);
498 SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG);
499 SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
500 SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG);
504 #endif // X86ISELLOWERING_H