1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
29 // X86 Specific DAG Nodes
31 // Start the numbering where the builtin ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 /// BSF - Bit scan forward.
35 /// BSR - Bit scan reverse.
39 /// SHLD, SHRD - Double shift instructions. These correspond to
40 /// X86::SHLDxx and X86::SHRDxx instructions.
44 /// FAND - Bitwise logical AND of floating point values. This corresponds
45 /// to X86::ANDPS or X86::ANDPD.
48 /// FOR - Bitwise logical OR of floating point values. This corresponds
49 /// to X86::ORPS or X86::ORPD.
52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
53 /// to X86::XORPS or X86::XORPD.
56 /// FSRL - Bitwise logical right shift of floating point values. These
57 /// corresponds to X86::PSRLDQ.
60 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
61 /// integer source in memory and FP reg result. This corresponds to the
62 /// X86::FILD*m instructions. It has three inputs (token chain, address,
63 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
64 /// also produces a flag).
68 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
69 /// integer destination in memory and a FP reg source. This corresponds
70 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
71 /// has two inputs (token chain and address) and two outputs (int value
77 /// FLD - This instruction implements an extending load to FP stack slots.
78 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
79 /// operand, ptr to load from, and a ValueType node indicating the type
83 /// FST - This instruction implements a truncating store to FP stack
84 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
85 /// chain operand, value to store, address, and a ValueType to store it
89 /// CALL - These operations represent an abstract X86 call
90 /// instruction, which includes a bunch of information. In particular the
91 /// operands of these node are:
93 /// #0 - The incoming token chain
95 /// #2 - The number of arg bytes the caller pushes on the stack.
96 /// #3 - The number of arg bytes the callee pops off the stack.
97 /// #4 - The value to pass in AL/AX/EAX (optional)
98 /// #5 - The value to pass in DL/DX/EDX (optional)
100 /// The result values of these nodes are:
102 /// #0 - The outgoing token chain
103 /// #1 - The first register result value (optional)
104 /// #2 - The second register result value (optional)
108 /// RDTSC_DAG - This operation implements the lowering for
112 /// X86 compare and logical compare instructions.
115 /// X86 bit-test instructions.
118 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the flag
119 /// operand produced by a CMP instruction.
122 // Same as SETCC except it's materialized with a sbb and the value is all
123 // one's or all zero's.
126 /// X86 conditional moves. Operand 0 and operand 1 are the two values
127 /// to select from. Operand 2 is the condition code, and operand 3 is the
128 /// flag operand produced by a CMP or TEST instruction. It also writes a
132 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
133 /// is the block to branch if condition is true, operand 2 is the
134 /// condition code, and operand 3 is the flag operand produced by a CMP
135 /// or TEST instruction.
138 /// Return with a flag operand. Operand 0 is the chain operand, operand
139 /// 1 is the number of bytes of stack to pop.
142 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
145 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
148 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
149 /// at function entry, used for PIC code.
152 /// Wrapper - A wrapper node for TargetConstantPool,
153 /// TargetExternalSymbol, and TargetGlobalAddress.
156 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
157 /// relative displacements.
160 /// MOVQ2DQ - Copies a 64-bit value from a vector to another vector.
161 /// Can be used to move a vector value from a MMX register to a XMM
165 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
166 /// i32, corresponds to X86::PEXTRB.
169 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
170 /// i32, corresponds to X86::PEXTRW.
173 /// INSERTPS - Insert any element of a 4 x float vector into any element
174 /// of a destination 4 x floatvector.
177 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
178 /// corresponds to X86::PINSRB.
181 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
182 /// corresponds to X86::PINSRW.
185 /// PSHUFB - Shuffle 16 8-bit values within a vector.
188 /// FMAX, FMIN - Floating point max and min.
192 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
193 /// approximation. Note that these typically require refinement
194 /// in order to obtain suitable precision.
197 // TLSADDR - Thread Local Storage.
200 // TLSCALL - Thread Local Storage. When calling to an OS provided
201 // thunk at the address from an earlier relocation.
204 // SegmentBaseAddress - The address segment:0
207 // EH_RETURN - Exception Handling helpers.
210 /// TC_RETURN - Tail call return.
212 /// operand #1 callee (register or absolute)
213 /// operand #2 stack adjustment
214 /// operand #3 optional in flag
217 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
221 // FNSTCW16m - Store FP control world into i16 memory.
224 // VZEXT_MOVL - Vector move low and zero extend.
227 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
230 // VSHL, VSRL - Vector logical left / right shift.
233 // CMPPD, CMPPS - Vector double/float comparison.
234 // CMPPD, CMPPS - Vector double/float comparison.
237 // PCMP* - Vector integer comparisons.
238 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
239 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
241 // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results.
242 ADD, SUB, SMUL, UMUL,
243 INC, DEC, OR, XOR, AND,
245 // MUL_IMM - X86 specific multiply by immediate.
248 // PTEST - Vector bitwise comparisons
251 // TESTP - Vector packed fp sign bitwise comparisons
254 // Several flavors of instructions with vector shuffle behaviors.
289 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
290 // according to %al. An operator is needed so that this can be expanded
291 // with control flow.
292 VASTART_SAVE_XMM_REGS,
294 // MINGW_ALLOCA - MingW's __alloca call to do stack probing.
297 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
298 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
299 // Atomic 64-bit binary operations.
300 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
314 // WARNING: Do not add anything in the end unless you want the node to
315 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
316 // thought as target memory ops!
320 /// Define some predicates that are used for node matching.
322 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
323 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
324 bool isPSHUFDMask(ShuffleVectorSDNode *N);
326 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
327 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
328 bool isPSHUFHWMask(ShuffleVectorSDNode *N);
330 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
331 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
332 bool isPSHUFLWMask(ShuffleVectorSDNode *N);
334 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
335 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
336 bool isSHUFPMask(ShuffleVectorSDNode *N);
338 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
339 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
340 bool isMOVHLPSMask(ShuffleVectorSDNode *N);
342 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
343 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
345 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N);
347 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
348 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}.
349 bool isMOVLPMask(ShuffleVectorSDNode *N);
351 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
352 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}.
353 /// as well as MOVLHPS.
354 bool isMOVLHPSMask(ShuffleVectorSDNode *N);
356 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
357 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
358 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
360 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
361 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
362 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
364 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
365 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
367 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N);
369 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
370 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
372 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N);
374 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
375 /// specifies a shuffle of elements that is suitable for input to MOVSS,
376 /// MOVSD, and MOVD, i.e. setting the lowest element.
377 bool isMOVLMask(ShuffleVectorSDNode *N);
379 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
380 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
381 bool isMOVSHDUPMask(ShuffleVectorSDNode *N);
383 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
384 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
385 bool isMOVSLDUPMask(ShuffleVectorSDNode *N);
387 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
388 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
389 bool isMOVDDUPMask(ShuffleVectorSDNode *N);
391 /// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand
392 /// specifies a shuffle of elements that is suitable for input to PALIGNR.
393 bool isPALIGNRMask(ShuffleVectorSDNode *N);
395 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
396 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
398 unsigned getShuffleSHUFImmediate(SDNode *N);
400 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
401 /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction.
402 unsigned getShufflePSHUFHWImmediate(SDNode *N);
404 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
405 /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction.
406 unsigned getShufflePSHUFLWImmediate(SDNode *N);
408 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
409 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
410 unsigned getShufflePALIGNRImmediate(SDNode *N);
412 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
414 bool isZeroNode(SDValue Elt);
416 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
417 /// fit into displacement field of the instruction.
418 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
419 bool hasSymbolicDisplacement = true);
422 //===--------------------------------------------------------------------===//
423 // X86TargetLowering - X86 Implementation of the TargetLowering interface
424 class X86TargetLowering : public TargetLowering {
426 explicit X86TargetLowering(X86TargetMachine &TM);
428 /// getPICBaseSymbol - Return the X86-32 PIC base.
429 MCSymbol *getPICBaseSymbol(const MachineFunction *MF, MCContext &Ctx) const;
431 virtual unsigned getJumpTableEncoding() const;
433 virtual const MCExpr *
434 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
435 const MachineBasicBlock *MBB, unsigned uid,
436 MCContext &Ctx) const;
438 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
440 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
441 SelectionDAG &DAG) const;
442 virtual const MCExpr *
443 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
444 unsigned JTI, MCContext &Ctx) const;
446 /// getStackPtrReg - Return the stack pointer register we are using: either
448 unsigned getStackPtrReg() const { return X86StackPtr; }
450 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
451 /// function arguments in the caller parameter area. For X86, aggregates
452 /// that contains are placed at 16-byte boundaries while the rest are at
453 /// 4-byte boundaries.
454 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
456 /// getOptimalMemOpType - Returns the target specific optimal type for load
457 /// and store operations as a result of memset, memcpy, and memmove
458 /// lowering. If DstAlign is zero that means it's safe to destination
459 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
460 /// means there isn't a need to check it against alignment requirement,
461 /// probably because the source does not need to be loaded. If
462 /// 'NonScalarIntSafe' is true, that means it's safe to return a
463 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
464 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
465 /// constant so it does not need to be loaded.
466 /// It returns EVT::Other if the type should be determined using generic
467 /// target-independent logic.
469 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
470 bool NonScalarIntSafe, bool MemcpyStrSrc,
471 MachineFunction &MF) const;
473 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
474 /// unaligned memory accesses. of the specified type.
475 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
479 /// LowerOperation - Provide custom lowering hooks for some operations.
481 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
483 /// ReplaceNodeResults - Replace the results of node with an illegal result
484 /// type with new values built out of custom code.
486 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
487 SelectionDAG &DAG) const;
490 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
492 /// isTypeDesirableForOp - Return true if the target has native support for
493 /// the specified value type and it is 'desirable' to use the type for the
494 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
495 /// instruction encodings are longer and some i16 instructions are slow.
496 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
498 /// isTypeDesirable - Return true if the target has native support for the
499 /// specified value type and it is 'desirable' to use the type. e.g. On x86
500 /// i16 is legal, but undesirable since i16 instruction encodings are longer
501 /// and some i16 instructions are slow.
502 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
504 virtual MachineBasicBlock *
505 EmitInstrWithCustomInserter(MachineInstr *MI,
506 MachineBasicBlock *MBB) const;
509 /// getTargetNodeName - This method returns the name of a target specific
511 virtual const char *getTargetNodeName(unsigned Opcode) const;
513 /// getSetCCResultType - Return the ISD::SETCC ValueType
514 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
516 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
517 /// in Mask are known to be either zero or one and return them in the
518 /// KnownZero/KnownOne bitsets.
519 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
523 const SelectionDAG &DAG,
524 unsigned Depth = 0) const;
527 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
529 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
531 virtual bool ExpandInlineAsm(CallInst *CI) const;
533 ConstraintType getConstraintType(const std::string &Constraint) const;
535 std::vector<unsigned>
536 getRegClassForInlineAsmConstraint(const std::string &Constraint,
539 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
541 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
542 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
543 /// true it means one of the asm constraint of the inline asm instruction
544 /// being processed is 'm'.
545 virtual void LowerAsmOperandForConstraint(SDValue Op,
546 char ConstraintLetter,
547 std::vector<SDValue> &Ops,
548 SelectionDAG &DAG) const;
550 /// getRegForInlineAsmConstraint - Given a physical register constraint
551 /// (e.g. {edx}), return the register number and the register class for the
552 /// register. This should only be used for C_Register constraints. On
553 /// error, this returns a register number of 0.
554 std::pair<unsigned, const TargetRegisterClass*>
555 getRegForInlineAsmConstraint(const std::string &Constraint,
558 /// isLegalAddressingMode - Return true if the addressing mode represented
559 /// by AM is legal for this target, for a load/store of the specified type.
560 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
562 /// isTruncateFree - Return true if it's free to truncate a value of
563 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
564 /// register EAX to i16 by referencing its sub-register AX.
565 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
566 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
568 /// isZExtFree - Return true if any actual instruction that defines a
569 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
570 /// register. This does not necessarily include registers defined in
571 /// unknown ways, such as incoming arguments, or copies from unknown
572 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
573 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
574 /// all instructions that define 32-bit values implicit zero-extend the
575 /// result out to 64 bits.
576 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const;
577 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
579 /// isNarrowingProfitable - Return true if it's profitable to narrow
580 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
581 /// from i32 to i8 but not from i32 to i16.
582 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
584 /// isFPImmLegal - Returns true if the target can instruction select the
585 /// specified FP immediate natively. If false, the legalizer will
586 /// materialize the FP immediate as a load from a constant pool.
587 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
589 /// isShuffleMaskLegal - Targets can use this to indicate that they only
590 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
591 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
592 /// values are assumed to be legal.
593 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
596 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
597 /// used by Targets can use this to indicate if there is a suitable
598 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
600 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
603 /// ShouldShrinkFPConstant - If true, then instruction selection should
604 /// seek to shrink the FP constant of the specified type to a smaller type
605 /// in order to save space and / or reduce runtime.
606 virtual bool ShouldShrinkFPConstant(EVT VT) const {
607 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
608 // expensive than a straight movsd. On the other hand, it's important to
609 // shrink long double fp constant since fldt is very slow.
610 return !X86ScalarSSEf64 || VT == MVT::f80;
613 const X86Subtarget* getSubtarget() const {
617 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
618 /// computed in an SSE register, not on the X87 floating point stack.
619 bool isScalarFPTypeInSSEReg(EVT VT) const {
620 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
621 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
624 /// createFastISel - This method returns a target specific FastISel object,
625 /// or null if the target does not support "fast" ISel.
626 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
628 /// getFunctionAlignment - Return the Log2 alignment of this function.
629 virtual unsigned getFunctionAlignment(const Function *F) const;
631 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
632 MachineFunction &MF) const;
634 /// getStackCookieLocation - Return true if the target stores stack
635 /// protector cookies at a fixed offset in some non-standard address
636 /// space, and populates the address space and offset as
638 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
641 std::pair<const TargetRegisterClass*, uint8_t>
642 findRepresentativeClass(EVT VT) const;
645 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
646 /// make the right decision when generating code for different targets.
647 const X86Subtarget *Subtarget;
648 const X86RegisterInfo *RegInfo;
649 const TargetData *TD;
651 /// X86StackPtr - X86 physical register used as stack ptr.
652 unsigned X86StackPtr;
654 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
655 /// floating point ops.
656 /// When SSE is available, use it for f32 operations.
657 /// When SSE2 is available, use it for f64 operations.
658 bool X86ScalarSSEf32;
659 bool X86ScalarSSEf64;
661 /// LegalFPImmediates - A list of legal fp immediates.
662 std::vector<APFloat> LegalFPImmediates;
664 /// addLegalFPImmediate - Indicate that this x86 target can instruction
665 /// select the specified FP immediate natively.
666 void addLegalFPImmediate(const APFloat& Imm) {
667 LegalFPImmediates.push_back(Imm);
670 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
671 CallingConv::ID CallConv, bool isVarArg,
672 const SmallVectorImpl<ISD::InputArg> &Ins,
673 DebugLoc dl, SelectionDAG &DAG,
674 SmallVectorImpl<SDValue> &InVals) const;
675 SDValue LowerMemArgument(SDValue Chain,
676 CallingConv::ID CallConv,
677 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
678 DebugLoc dl, SelectionDAG &DAG,
679 const CCValAssign &VA, MachineFrameInfo *MFI,
681 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
682 DebugLoc dl, SelectionDAG &DAG,
683 const CCValAssign &VA,
684 ISD::ArgFlagsTy Flags) const;
686 // Call lowering helpers.
688 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
689 /// for tail call optimization. Targets which want to do tail call
690 /// optimization should implement this function.
691 bool IsEligibleForTailCallOptimization(SDValue Callee,
692 CallingConv::ID CalleeCC,
694 bool isCalleeStructRet,
695 bool isCallerStructRet,
696 const SmallVectorImpl<ISD::OutputArg> &Outs,
697 const SmallVectorImpl<SDValue> &OutVals,
698 const SmallVectorImpl<ISD::InputArg> &Ins,
699 SelectionDAG& DAG) const;
700 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
701 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
702 SDValue Chain, bool IsTailCall, bool Is64Bit,
703 int FPDiff, DebugLoc dl) const;
705 CCAssignFn *CCAssignFnForNode(CallingConv::ID CallConv) const;
706 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
707 SelectionDAG &DAG) const;
709 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
710 bool isSigned) const;
712 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
713 SelectionDAG &DAG) const;
714 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
715 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
716 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
717 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
718 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
719 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
720 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
721 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
722 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
723 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
724 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
725 int64_t Offset, SelectionDAG &DAG) const;
726 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
727 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
728 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
729 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
730 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
731 SelectionDAG &DAG) const;
732 SDValue LowerBIT_CONVERT(SDValue op, SelectionDAG &DAG) const;
733 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
734 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
735 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
736 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
737 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
738 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
739 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
740 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
741 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
742 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
743 DebugLoc dl, SelectionDAG &DAG) const;
744 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
745 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
746 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
747 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
748 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
749 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
750 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
751 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
752 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
753 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
754 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
755 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
756 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
757 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
758 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
759 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
760 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
761 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
762 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
763 SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const;
764 SDValue LowerSHL(SDValue Op, SelectionDAG &DAG) const;
765 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
767 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
768 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
769 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
770 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const;
772 // Utility functions to help LowerVECTOR_SHUFFLE
773 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const;
776 LowerFormalArguments(SDValue Chain,
777 CallingConv::ID CallConv, bool isVarArg,
778 const SmallVectorImpl<ISD::InputArg> &Ins,
779 DebugLoc dl, SelectionDAG &DAG,
780 SmallVectorImpl<SDValue> &InVals) const;
782 LowerCall(SDValue Chain, SDValue Callee,
783 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
784 const SmallVectorImpl<ISD::OutputArg> &Outs,
785 const SmallVectorImpl<SDValue> &OutVals,
786 const SmallVectorImpl<ISD::InputArg> &Ins,
787 DebugLoc dl, SelectionDAG &DAG,
788 SmallVectorImpl<SDValue> &InVals) const;
791 LowerReturn(SDValue Chain,
792 CallingConv::ID CallConv, bool isVarArg,
793 const SmallVectorImpl<ISD::OutputArg> &Outs,
794 const SmallVectorImpl<SDValue> &OutVals,
795 DebugLoc dl, SelectionDAG &DAG) const;
798 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
799 const SmallVectorImpl<ISD::OutputArg> &Outs,
800 LLVMContext &Context) const;
802 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
803 SelectionDAG &DAG, unsigned NewOp) const;
805 /// Utility function to emit string processing sse4.2 instructions
806 /// that return in xmm0.
807 /// This takes the instruction to expand, the associated machine basic
808 /// block, the number of args, and whether or not the second arg is
809 /// in memory or not.
810 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
811 unsigned argNum, bool inMem) const;
813 /// Utility function to emit atomic bitwise operations (and, or, xor).
814 /// It takes the bitwise instruction to expand, the associated machine basic
815 /// block, and the associated X86 opcodes for reg/reg and reg/imm.
816 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
817 MachineInstr *BInstr,
818 MachineBasicBlock *BB,
825 TargetRegisterClass *RC,
826 bool invSrc = false) const;
828 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
829 MachineInstr *BInstr,
830 MachineBasicBlock *BB,
835 bool invSrc = false) const;
837 /// Utility function to emit atomic min and max. It takes the min/max
838 /// instruction to expand, the associated basic block, and the associated
839 /// cmov opcode for moving the min or max value.
840 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
841 MachineBasicBlock *BB,
842 unsigned cmovOpc) const;
844 /// Utility function to emit the xmm reg save portion of va_start.
845 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
846 MachineInstr *BInstr,
847 MachineBasicBlock *BB) const;
849 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
850 MachineBasicBlock *BB) const;
852 MachineBasicBlock *EmitLoweredMingwAlloca(MachineInstr *MI,
853 MachineBasicBlock *BB) const;
855 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
856 MachineBasicBlock *BB) const;
858 /// Emit nodes that will be selected as "test Op0,Op0", or something
859 /// equivalent, for use with the given x86 condition code.
860 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
862 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
863 /// equivalent, for use with the given x86 condition code.
864 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
865 SelectionDAG &DAG) const;
869 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
873 #endif // X86ISELLOWERING_H