1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
29 // X86 Specific DAG Nodes
31 // Start the numbering where the builtin ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 /// BSF - Bit scan forward.
35 /// BSR - Bit scan reverse.
39 /// SHLD, SHRD - Double shift instructions. These correspond to
40 /// X86::SHLDxx and X86::SHRDxx instructions.
44 /// FAND - Bitwise logical AND of floating point values. This corresponds
45 /// to X86::ANDPS or X86::ANDPD.
48 /// FOR - Bitwise logical OR of floating point values. This corresponds
49 /// to X86::ORPS or X86::ORPD.
52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
53 /// to X86::XORPS or X86::XORPD.
56 /// FSRL - Bitwise logical right shift of floating point values. These
57 /// corresponds to X86::PSRLDQ.
60 /// CALL - These operations represent an abstract X86 call
61 /// instruction, which includes a bunch of information. In particular the
62 /// operands of these node are:
64 /// #0 - The incoming token chain
66 /// #2 - The number of arg bytes the caller pushes on the stack.
67 /// #3 - The number of arg bytes the callee pops off the stack.
68 /// #4 - The value to pass in AL/AX/EAX (optional)
69 /// #5 - The value to pass in DL/DX/EDX (optional)
71 /// The result values of these nodes are:
73 /// #0 - The outgoing token chain
74 /// #1 - The first register result value (optional)
75 /// #2 - The second register result value (optional)
79 /// RDTSC_DAG - This operation implements the lowering for
83 /// X86 compare and logical compare instructions.
86 /// X86 bit-test instructions.
89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
90 /// operand, usually produced by a CMP instruction.
93 // Same as SETCC except it's materialized with a sbb and the value is all
94 // one's or all zero's.
95 SETCC_CARRY, // R = carry_bit ? ~0 : 0
97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
98 /// Operands are two FP values to compare; result is a mask of
99 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
102 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
103 /// result in an integer GPR. Needs masking for scalar result.
106 /// X86 conditional moves. Operand 0 and operand 1 are the two values
107 /// to select from. Operand 2 is the condition code, and operand 3 is the
108 /// flag operand produced by a CMP or TEST instruction. It also writes a
112 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
113 /// is the block to branch if condition is true, operand 2 is the
114 /// condition code, and operand 3 is the flag operand produced by a CMP
115 /// or TEST instruction.
118 /// Return with a flag operand. Operand 0 is the chain operand, operand
119 /// 1 is the number of bytes of stack to pop.
122 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
125 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
128 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
129 /// at function entry, used for PIC code.
132 /// Wrapper - A wrapper node for TargetConstantPool,
133 /// TargetExternalSymbol, and TargetGlobalAddress.
136 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
137 /// relative displacements.
140 /// MOVQ2DQ - Copies a 64-bit value from an MMX vector to the low word
141 /// of an XMM vector, with the high word zero filled.
144 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
145 /// to an MMX vector. If you think this is too close to the previous
146 /// mnemonic, so do I; blame Intel.
149 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
150 /// i32, corresponds to X86::PEXTRB.
153 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
154 /// i32, corresponds to X86::PEXTRW.
157 /// INSERTPS - Insert any element of a 4 x float vector into any element
158 /// of a destination 4 x floatvector.
161 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
162 /// corresponds to X86::PINSRB.
165 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
166 /// corresponds to X86::PINSRW.
169 /// PSHUFB - Shuffle 16 8-bit values within a vector.
172 /// PANDN - and with not'd value.
175 /// PSIGNB/W/D - Copy integer sign.
176 PSIGNB, PSIGNW, PSIGND,
178 /// PBLENDVB - Variable blend
181 /// FMAX, FMIN - Floating point max and min.
185 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
186 /// approximation. Note that these typically require refinement
187 /// in order to obtain suitable precision.
190 // TLSADDR - Thread Local Storage.
193 // TLSCALL - Thread Local Storage. When calling to an OS provided
194 // thunk at the address from an earlier relocation.
197 // EH_RETURN - Exception Handling helpers.
200 /// TC_RETURN - Tail call return.
202 /// operand #1 callee (register or absolute)
203 /// operand #2 stack adjustment
204 /// operand #3 optional in flag
207 // VZEXT_MOVL - Vector move low and zero extend.
210 // VSHL, VSRL - Vector logical left / right shift.
213 // CMPPD, CMPPS - Vector double/float comparison.
214 // CMPPD, CMPPS - Vector double/float comparison.
217 // PCMP* - Vector integer comparisons.
218 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
219 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
221 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
222 ADD, SUB, ADC, SBB, SMUL,
223 INC, DEC, OR, XOR, AND,
225 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
227 // MUL_IMM - X86 specific multiply by immediate.
230 // PTEST - Vector bitwise comparisons
233 // TESTP - Vector packed fp sign bitwise comparisons
236 // Several flavors of instructions with vector shuffle behaviors.
275 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
276 // according to %al. An operator is needed so that this can be expanded
277 // with control flow.
278 VASTART_SAVE_XMM_REGS,
280 // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
289 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
290 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
291 // Atomic 64-bit binary operations.
292 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
300 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
304 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
307 // FNSTCW16m - Store FP control world into i16 memory.
310 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
311 /// integer destination in memory and a FP reg source. This corresponds
312 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
313 /// has two inputs (token chain and address) and two outputs (int value
314 /// and token chain).
319 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
320 /// integer source in memory and FP reg result. This corresponds to the
321 /// X86::FILD*m instructions. It has three inputs (token chain, address,
322 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
323 /// also produces a flag).
327 /// FLD - This instruction implements an extending load to FP stack slots.
328 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
329 /// operand, ptr to load from, and a ValueType node indicating the type
333 /// FST - This instruction implements a truncating store to FP stack
334 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
335 /// chain operand, value to store, address, and a ValueType to store it
339 /// VAARG_64 - This instruction grabs the address of the next argument
340 /// from a va_list. (reads and modifies the va_list in memory)
343 // WARNING: Do not add anything in the end unless you want the node to
344 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
345 // thought as target memory ops!
349 /// Define some predicates that are used for node matching.
351 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
352 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
353 bool isPSHUFDMask(ShuffleVectorSDNode *N);
355 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
356 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
357 bool isPSHUFHWMask(ShuffleVectorSDNode *N);
359 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
360 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
361 bool isPSHUFLWMask(ShuffleVectorSDNode *N);
363 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
364 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
365 bool isSHUFPMask(ShuffleVectorSDNode *N);
367 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
368 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
369 bool isMOVHLPSMask(ShuffleVectorSDNode *N);
371 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
372 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
374 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N);
376 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
377 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}.
378 bool isMOVLPMask(ShuffleVectorSDNode *N);
380 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
381 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}.
382 /// as well as MOVLHPS.
383 bool isMOVLHPSMask(ShuffleVectorSDNode *N);
385 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
386 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
387 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
389 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
390 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
391 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
393 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
394 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
396 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N);
398 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
399 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
401 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N);
403 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
404 /// specifies a shuffle of elements that is suitable for input to MOVSS,
405 /// MOVSD, and MOVD, i.e. setting the lowest element.
406 bool isMOVLMask(ShuffleVectorSDNode *N);
408 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
409 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
410 bool isMOVSHDUPMask(ShuffleVectorSDNode *N);
412 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
413 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
414 bool isMOVSLDUPMask(ShuffleVectorSDNode *N);
416 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
417 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
418 bool isMOVDDUPMask(ShuffleVectorSDNode *N);
420 /// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand
421 /// specifies a shuffle of elements that is suitable for input to PALIGNR.
422 bool isPALIGNRMask(ShuffleVectorSDNode *N);
424 /// isVEXTRACTF128Index - Return true if the specified
425 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
426 /// suitable for input to VEXTRACTF128.
427 bool isVEXTRACTF128Index(SDNode *N);
429 /// isVINSERTF128Index - Return true if the specified
430 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
431 /// suitable for input to VINSERTF128.
432 bool isVINSERTF128Index(SDNode *N);
434 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
435 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
437 unsigned getShuffleSHUFImmediate(SDNode *N);
439 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
440 /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction.
441 unsigned getShufflePSHUFHWImmediate(SDNode *N);
443 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
444 /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction.
445 unsigned getShufflePSHUFLWImmediate(SDNode *N);
447 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
448 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
449 unsigned getShufflePALIGNRImmediate(SDNode *N);
451 /// getExtractVEXTRACTF128Immediate - Return the appropriate
452 /// immediate to extract the specified EXTRACT_SUBVECTOR index
453 /// with VEXTRACTF128 instructions.
454 unsigned getExtractVEXTRACTF128Immediate(SDNode *N);
456 /// getInsertVINSERTF128Immediate - Return the appropriate
457 /// immediate to insert at the specified INSERT_SUBVECTOR index
458 /// with VINSERTF128 instructions.
459 unsigned getInsertVINSERTF128Immediate(SDNode *N);
461 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
463 bool isZeroNode(SDValue Elt);
465 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
466 /// fit into displacement field of the instruction.
467 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
468 bool hasSymbolicDisplacement = true);
471 //===--------------------------------------------------------------------===//
472 // X86TargetLowering - X86 Implementation of the TargetLowering interface
473 class X86TargetLowering : public TargetLowering {
475 explicit X86TargetLowering(X86TargetMachine &TM);
477 virtual unsigned getJumpTableEncoding() const;
479 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
481 virtual const MCExpr *
482 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
483 const MachineBasicBlock *MBB, unsigned uid,
484 MCContext &Ctx) const;
486 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
488 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
489 SelectionDAG &DAG) const;
490 virtual const MCExpr *
491 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
492 unsigned JTI, MCContext &Ctx) const;
494 /// getStackPtrReg - Return the stack pointer register we are using: either
496 unsigned getStackPtrReg() const { return X86StackPtr; }
498 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
499 /// function arguments in the caller parameter area. For X86, aggregates
500 /// that contains are placed at 16-byte boundaries while the rest are at
501 /// 4-byte boundaries.
502 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
504 /// getOptimalMemOpType - Returns the target specific optimal type for load
505 /// and store operations as a result of memset, memcpy, and memmove
506 /// lowering. If DstAlign is zero that means it's safe to destination
507 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
508 /// means there isn't a need to check it against alignment requirement,
509 /// probably because the source does not need to be loaded. If
510 /// 'NonScalarIntSafe' is true, that means it's safe to return a
511 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
512 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
513 /// constant so it does not need to be loaded.
514 /// It returns EVT::Other if the type should be determined using generic
515 /// target-independent logic.
517 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
518 bool NonScalarIntSafe, bool MemcpyStrSrc,
519 MachineFunction &MF) const;
521 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
522 /// unaligned memory accesses. of the specified type.
523 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
527 /// LowerOperation - Provide custom lowering hooks for some operations.
529 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
531 /// ReplaceNodeResults - Replace the results of node with an illegal result
532 /// type with new values built out of custom code.
534 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
535 SelectionDAG &DAG) const;
538 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
540 /// isTypeDesirableForOp - Return true if the target has native support for
541 /// the specified value type and it is 'desirable' to use the type for the
542 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
543 /// instruction encodings are longer and some i16 instructions are slow.
544 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
546 /// isTypeDesirable - Return true if the target has native support for the
547 /// specified value type and it is 'desirable' to use the type. e.g. On x86
548 /// i16 is legal, but undesirable since i16 instruction encodings are longer
549 /// and some i16 instructions are slow.
550 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
552 virtual MachineBasicBlock *
553 EmitInstrWithCustomInserter(MachineInstr *MI,
554 MachineBasicBlock *MBB) const;
557 /// getTargetNodeName - This method returns the name of a target specific
559 virtual const char *getTargetNodeName(unsigned Opcode) const;
561 /// getSetCCResultType - Return the ISD::SETCC ValueType
562 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
564 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
565 /// in Mask are known to be either zero or one and return them in the
566 /// KnownZero/KnownOne bitsets.
567 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
571 const SelectionDAG &DAG,
572 unsigned Depth = 0) const;
574 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
575 // operation that are sign bits.
576 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
577 unsigned Depth) const;
580 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
582 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
584 virtual bool ExpandInlineAsm(CallInst *CI) const;
586 ConstraintType getConstraintType(const std::string &Constraint) const;
588 /// Examine constraint string and operand type and determine a weight value.
589 /// The operand object must already have been set up with the operand type.
590 virtual ConstraintWeight getSingleConstraintMatchWeight(
591 AsmOperandInfo &info, const char *constraint) const;
593 std::vector<unsigned>
594 getRegClassForInlineAsmConstraint(const std::string &Constraint,
597 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
599 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
600 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
601 /// true it means one of the asm constraint of the inline asm instruction
602 /// being processed is 'm'.
603 virtual void LowerAsmOperandForConstraint(SDValue Op,
604 std::string &Constraint,
605 std::vector<SDValue> &Ops,
606 SelectionDAG &DAG) const;
608 /// getRegForInlineAsmConstraint - Given a physical register constraint
609 /// (e.g. {edx}), return the register number and the register class for the
610 /// register. This should only be used for C_Register constraints. On
611 /// error, this returns a register number of 0.
612 std::pair<unsigned, const TargetRegisterClass*>
613 getRegForInlineAsmConstraint(const std::string &Constraint,
616 /// isLegalAddressingMode - Return true if the addressing mode represented
617 /// by AM is legal for this target, for a load/store of the specified type.
618 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
620 /// isTruncateFree - Return true if it's free to truncate a value of
621 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
622 /// register EAX to i16 by referencing its sub-register AX.
623 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
624 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
626 /// isZExtFree - Return true if any actual instruction that defines a
627 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
628 /// register. This does not necessarily include registers defined in
629 /// unknown ways, such as incoming arguments, or copies from unknown
630 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
631 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
632 /// all instructions that define 32-bit values implicit zero-extend the
633 /// result out to 64 bits.
634 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const;
635 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
637 /// isNarrowingProfitable - Return true if it's profitable to narrow
638 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
639 /// from i32 to i8 but not from i32 to i16.
640 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
642 /// isFPImmLegal - Returns true if the target can instruction select the
643 /// specified FP immediate natively. If false, the legalizer will
644 /// materialize the FP immediate as a load from a constant pool.
645 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
647 /// isShuffleMaskLegal - Targets can use this to indicate that they only
648 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
649 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
650 /// values are assumed to be legal.
651 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
654 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
655 /// used by Targets can use this to indicate if there is a suitable
656 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
658 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
661 /// ShouldShrinkFPConstant - If true, then instruction selection should
662 /// seek to shrink the FP constant of the specified type to a smaller type
663 /// in order to save space and / or reduce runtime.
664 virtual bool ShouldShrinkFPConstant(EVT VT) const {
665 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
666 // expensive than a straight movsd. On the other hand, it's important to
667 // shrink long double fp constant since fldt is very slow.
668 return !X86ScalarSSEf64 || VT == MVT::f80;
671 const X86Subtarget* getSubtarget() const {
675 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
676 /// computed in an SSE register, not on the X87 floating point stack.
677 bool isScalarFPTypeInSSEReg(EVT VT) const {
678 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
679 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
682 /// createFastISel - This method returns a target specific FastISel object,
683 /// or null if the target does not support "fast" ISel.
684 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
686 /// getStackCookieLocation - Return true if the target stores stack
687 /// protector cookies at a fixed offset in some non-standard address
688 /// space, and populates the address space and offset as
690 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
692 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
693 SelectionDAG &DAG) const;
696 std::pair<const TargetRegisterClass*, uint8_t>
697 findRepresentativeClass(EVT VT) const;
700 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
701 /// make the right decision when generating code for different targets.
702 const X86Subtarget *Subtarget;
703 const X86RegisterInfo *RegInfo;
704 const TargetData *TD;
706 /// X86StackPtr - X86 physical register used as stack ptr.
707 unsigned X86StackPtr;
709 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
710 /// floating point ops.
711 /// When SSE is available, use it for f32 operations.
712 /// When SSE2 is available, use it for f64 operations.
713 bool X86ScalarSSEf32;
714 bool X86ScalarSSEf64;
716 /// LegalFPImmediates - A list of legal fp immediates.
717 std::vector<APFloat> LegalFPImmediates;
719 /// addLegalFPImmediate - Indicate that this x86 target can instruction
720 /// select the specified FP immediate natively.
721 void addLegalFPImmediate(const APFloat& Imm) {
722 LegalFPImmediates.push_back(Imm);
725 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
726 CallingConv::ID CallConv, bool isVarArg,
727 const SmallVectorImpl<ISD::InputArg> &Ins,
728 DebugLoc dl, SelectionDAG &DAG,
729 SmallVectorImpl<SDValue> &InVals) const;
730 SDValue LowerMemArgument(SDValue Chain,
731 CallingConv::ID CallConv,
732 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
733 DebugLoc dl, SelectionDAG &DAG,
734 const CCValAssign &VA, MachineFrameInfo *MFI,
736 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
737 DebugLoc dl, SelectionDAG &DAG,
738 const CCValAssign &VA,
739 ISD::ArgFlagsTy Flags) const;
741 // Call lowering helpers.
743 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
744 /// for tail call optimization. Targets which want to do tail call
745 /// optimization should implement this function.
746 bool IsEligibleForTailCallOptimization(SDValue Callee,
747 CallingConv::ID CalleeCC,
749 bool isCalleeStructRet,
750 bool isCallerStructRet,
751 const SmallVectorImpl<ISD::OutputArg> &Outs,
752 const SmallVectorImpl<SDValue> &OutVals,
753 const SmallVectorImpl<ISD::InputArg> &Ins,
754 SelectionDAG& DAG) const;
755 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
756 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
757 SDValue Chain, bool IsTailCall, bool Is64Bit,
758 int FPDiff, DebugLoc dl) const;
760 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
761 SelectionDAG &DAG) const;
763 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
764 bool isSigned) const;
766 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
767 SelectionDAG &DAG) const;
768 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
769 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
770 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
771 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
772 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
773 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
774 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
775 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
776 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
777 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
778 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
779 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
780 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
781 int64_t Offset, SelectionDAG &DAG) const;
782 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
783 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
784 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
785 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
786 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const;
787 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
788 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
789 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
790 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
791 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
792 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
793 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
794 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
795 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
796 SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const;
797 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
798 DebugLoc dl, SelectionDAG &DAG) const;
799 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
800 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
801 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
802 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
803 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
804 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
805 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
806 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
807 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
808 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
809 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
810 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
811 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
812 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
813 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
814 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
815 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
816 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
817 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
818 SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const;
819 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
820 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
822 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
823 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
824 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
825 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const;
827 // Utility functions to help LowerVECTOR_SHUFFLE
828 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const;
831 LowerFormalArguments(SDValue Chain,
832 CallingConv::ID CallConv, bool isVarArg,
833 const SmallVectorImpl<ISD::InputArg> &Ins,
834 DebugLoc dl, SelectionDAG &DAG,
835 SmallVectorImpl<SDValue> &InVals) const;
837 LowerCall(SDValue Chain, SDValue Callee,
838 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
839 const SmallVectorImpl<ISD::OutputArg> &Outs,
840 const SmallVectorImpl<SDValue> &OutVals,
841 const SmallVectorImpl<ISD::InputArg> &Ins,
842 DebugLoc dl, SelectionDAG &DAG,
843 SmallVectorImpl<SDValue> &InVals) const;
846 LowerReturn(SDValue Chain,
847 CallingConv::ID CallConv, bool isVarArg,
848 const SmallVectorImpl<ISD::OutputArg> &Outs,
849 const SmallVectorImpl<SDValue> &OutVals,
850 DebugLoc dl, SelectionDAG &DAG) const;
852 virtual bool isUsedByReturnOnly(SDNode *N) const;
854 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
857 getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
858 ISD::NodeType ExtendKind) const;
861 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
863 const SmallVectorImpl<ISD::OutputArg> &Outs,
864 LLVMContext &Context) const;
866 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
867 SelectionDAG &DAG, unsigned NewOp) const;
869 /// Utility function to emit string processing sse4.2 instructions
870 /// that return in xmm0.
871 /// This takes the instruction to expand, the associated machine basic
872 /// block, the number of args, and whether or not the second arg is
873 /// in memory or not.
874 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
875 unsigned argNum, bool inMem) const;
877 /// Utility functions to emit monitor and mwait instructions. These
878 /// need to make sure that the arguments to the intrinsic are in the
879 /// correct registers.
880 MachineBasicBlock *EmitMonitor(MachineInstr *MI,
881 MachineBasicBlock *BB) const;
882 MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const;
884 /// Utility function to emit atomic bitwise operations (and, or, xor).
885 /// It takes the bitwise instruction to expand, the associated machine basic
886 /// block, and the associated X86 opcodes for reg/reg and reg/imm.
887 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
888 MachineInstr *BInstr,
889 MachineBasicBlock *BB,
896 TargetRegisterClass *RC,
897 bool invSrc = false) const;
899 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
900 MachineInstr *BInstr,
901 MachineBasicBlock *BB,
906 bool invSrc = false) const;
908 /// Utility function to emit atomic min and max. It takes the min/max
909 /// instruction to expand, the associated basic block, and the associated
910 /// cmov opcode for moving the min or max value.
911 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
912 MachineBasicBlock *BB,
913 unsigned cmovOpc) const;
915 // Utility function to emit the low-level va_arg code for X86-64.
916 MachineBasicBlock *EmitVAARG64WithCustomInserter(
918 MachineBasicBlock *MBB) const;
920 /// Utility function to emit the xmm reg save portion of va_start.
921 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
922 MachineInstr *BInstr,
923 MachineBasicBlock *BB) const;
925 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
926 MachineBasicBlock *BB) const;
928 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
929 MachineBasicBlock *BB) const;
931 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
932 MachineBasicBlock *BB) const;
934 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
935 MachineBasicBlock *BB) const;
937 /// Emit nodes that will be selected as "test Op0,Op0", or something
938 /// equivalent, for use with the given x86 condition code.
939 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
941 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
942 /// equivalent, for use with the given x86 condition code.
943 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
944 SelectionDAG &DAG) const;
948 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
952 #endif // X86ISELLOWERING_H