1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86MachineFunctionInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Target/TargetOptions.h"
29 // X86 Specific DAG Nodes
31 // Start the numbering where the builtin ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 /// BSF - Bit scan forward.
35 /// BSR - Bit scan reverse.
39 /// SHLD, SHRD - Double shift instructions. These correspond to
40 /// X86::SHLDxx and X86::SHRDxx instructions.
44 /// FAND - Bitwise logical AND of floating point values. This corresponds
45 /// to X86::ANDPS or X86::ANDPD.
48 /// FOR - Bitwise logical OR of floating point values. This corresponds
49 /// to X86::ORPS or X86::ORPD.
52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
53 /// to X86::XORPS or X86::XORPD.
56 /// FANDN - Bitwise logical ANDNOT of floating point values. This
57 /// corresponds to X86::ANDNPS or X86::ANDNPD.
60 /// FSRL - Bitwise logical right shift of floating point values. These
61 /// corresponds to X86::PSRLDQ.
64 /// CALL - These operations represent an abstract X86 call
65 /// instruction, which includes a bunch of information. In particular the
66 /// operands of these node are:
68 /// #0 - The incoming token chain
70 /// #2 - The number of arg bytes the caller pushes on the stack.
71 /// #3 - The number of arg bytes the callee pops off the stack.
72 /// #4 - The value to pass in AL/AX/EAX (optional)
73 /// #5 - The value to pass in DL/DX/EDX (optional)
75 /// The result values of these nodes are:
77 /// #0 - The outgoing token chain
78 /// #1 - The first register result value (optional)
79 /// #2 - The second register result value (optional)
83 /// RDTSC_DAG - This operation implements the lowering for
87 /// X86 compare and logical compare instructions.
90 /// X86 bit-test instructions.
93 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
94 /// operand, usually produced by a CMP instruction.
100 // Same as SETCC except it's materialized with a sbb and the value is all
101 // one's or all zero's.
102 SETCC_CARRY, // R = carry_bit ? ~0 : 0
104 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
105 /// Operands are two FP values to compare; result is a mask of
106 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
109 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
110 /// result in an integer GPR. Needs masking for scalar result.
113 /// X86 conditional moves. Operand 0 and operand 1 are the two values
114 /// to select from. Operand 2 is the condition code, and operand 3 is the
115 /// flag operand produced by a CMP or TEST instruction. It also writes a
119 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
120 /// is the block to branch if condition is true, operand 2 is the
121 /// condition code, and operand 3 is the flag operand produced by a CMP
122 /// or TEST instruction.
125 /// Return with a flag operand. Operand 0 is the chain operand, operand
126 /// 1 is the number of bytes of stack to pop.
129 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
132 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
135 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
136 /// at function entry, used for PIC code.
139 /// Wrapper - A wrapper node for TargetConstantPool,
140 /// TargetExternalSymbol, and TargetGlobalAddress.
143 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
144 /// relative displacements.
147 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
148 /// to an MMX vector. If you think this is too close to the previous
149 /// mnemonic, so do I; blame Intel.
152 /// MMX_MOVD2W - Copies a 32-bit value from the low word of a MMX
156 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
157 /// i32, corresponds to X86::PEXTRB.
160 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
161 /// i32, corresponds to X86::PEXTRW.
164 /// INSERTPS - Insert any element of a 4 x float vector into any element
165 /// of a destination 4 x floatvector.
168 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
169 /// corresponds to X86::PINSRB.
172 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
173 /// corresponds to X86::PINSRW.
176 /// PSHUFB - Shuffle 16 8-bit values within a vector.
179 /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
182 /// PSIGN - Copy integer sign.
185 /// BLENDV - Blend where the selector is a register.
188 /// BLENDI - Blend where the selector is an immediate.
191 // SUBUS - Integer sub with unsigned saturation.
194 /// HADD - Integer horizontal add.
197 /// HSUB - Integer horizontal sub.
200 /// FHADD - Floating point horizontal add.
203 /// FHSUB - Floating point horizontal sub.
206 /// UMAX, UMIN - Unsigned integer max and min.
209 /// SMAX, SMIN - Signed integer max and min.
212 /// FMAX, FMIN - Floating point max and min.
216 /// FMAXC, FMINC - Commutative FMIN and FMAX.
219 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
220 /// approximation. Note that these typically require refinement
221 /// in order to obtain suitable precision.
224 // TLSADDR - Thread Local Storage.
227 // TLSBASEADDR - Thread Local Storage. A call to get the start address
228 // of the TLS block for the current module.
231 // TLSCALL - Thread Local Storage. When calling to an OS provided
232 // thunk at the address from an earlier relocation.
235 // EH_RETURN - Exception Handling helpers.
238 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
241 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
244 /// TC_RETURN - Tail call return. See X86TargetLowering::LowerCall for
245 /// the list of operands.
248 // VZEXT_MOVL - Vector move low and zero extend.
251 // VSEXT_MOVL - Vector move low and sign extend.
254 // VZEXT - Vector integer zero-extend.
257 // VSEXT - Vector integer signed-extend.
260 // VTRUNC - Vector integer truncate.
263 // VTRUNC - Vector integer truncate with mask.
266 // VFPEXT - Vector FP extend.
269 // VFPROUND - Vector FP round.
272 // VSHL, VSRL - 128-bit vector logical left / right shift
275 // VSHL, VSRL, VSRA - Vector shift elements
278 // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate
281 // CMPP - Vector packed double/float comparison.
284 // PCMP* - Vector integer comparisons.
286 // PCMP*M - Vector integer comparisons, the result is in a mask vector.
289 /// CMPM, CMPMU - Vector comparison generating mask bits for fp and
290 /// integer signed and unsigned data types.
294 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
295 ADD, SUB, ADC, SBB, SMUL,
296 INC, DEC, OR, XOR, AND,
298 BLSI, // BLSI - Extract lowest set isolated bit
299 BLSMSK, // BLSMSK - Get mask up to lowest set bit
300 BLSR, // BLSR - Reset lowest set bit
301 BZHI, // BZHI - Zero high bits
302 BEXTR, // BEXTR - Bit field extract
304 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
306 // MUL_IMM - X86 specific multiply by immediate.
309 // PTEST - Vector bitwise comparisons.
312 // TESTP - Vector packed fp sign bitwise comparisons.
315 // TESTM - Vector "test" in AVX-512, the result is in a mask vector.
318 // OR/AND test for masks
321 // Several flavors of instructions with vector shuffle behaviors.
349 // PMULUDQ - Vector multiply packed unsigned doubleword integers
360 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
361 // according to %al. An operator is needed so that this can be expanded
362 // with control flow.
363 VASTART_SAVE_XMM_REGS,
365 // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
368 // SEG_ALLOCA - For allocating variable amounts of stack space when using
369 // segmented stacks. Check if the current stacklet has enough space, and
370 // falls back to heap allocation if not.
373 // WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui.
382 // FNSTSW16r - Store FP status word into i16 register.
385 // SAHF - Store contents of %ah into %eflags.
388 // RDRAND - Get a random integer and indicate whether it is valid in CF.
391 // RDSEED - Get a NIST SP800-90B & C compliant random integer and
392 // indicate whether it is valid in CF.
399 // XTEST - Test if in transactional execution.
402 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
403 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
404 // Atomic 64-bit binary operations.
405 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
417 // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
422 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
425 // FNSTCW16m - Store FP control world into i16 memory.
428 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
429 /// integer destination in memory and a FP reg source. This corresponds
430 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
431 /// has two inputs (token chain and address) and two outputs (int value
432 /// and token chain).
437 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
438 /// integer source in memory and FP reg result. This corresponds to the
439 /// X86::FILD*m instructions. It has three inputs (token chain, address,
440 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
441 /// also produces a flag).
445 /// FLD - This instruction implements an extending load to FP stack slots.
446 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
447 /// operand, ptr to load from, and a ValueType node indicating the type
451 /// FST - This instruction implements a truncating store to FP stack
452 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
453 /// chain operand, value to store, address, and a ValueType to store it
457 /// VAARG_64 - This instruction grabs the address of the next argument
458 /// from a va_list. (reads and modifies the va_list in memory)
461 // WARNING: Do not add anything in the end unless you want the node to
462 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
463 // thought as target memory ops!
467 /// Define some predicates that are used for node matching.
469 /// isVEXTRACT128Index - Return true if the specified
470 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
471 /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
472 bool isVEXTRACT128Index(SDNode *N);
474 /// isVINSERT128Index - Return true if the specified
475 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
476 /// suitable for input to VINSERTF128, VINSERTI128 instructions.
477 bool isVINSERT128Index(SDNode *N);
479 /// isVEXTRACT256Index - Return true if the specified
480 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
481 /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
482 bool isVEXTRACT256Index(SDNode *N);
484 /// isVINSERT256Index - Return true if the specified
485 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
486 /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
487 bool isVINSERT256Index(SDNode *N);
489 /// getExtractVEXTRACT128Immediate - Return the appropriate
490 /// immediate to extract the specified EXTRACT_SUBVECTOR index
491 /// with VEXTRACTF128, VEXTRACTI128 instructions.
492 unsigned getExtractVEXTRACT128Immediate(SDNode *N);
494 /// getInsertVINSERT128Immediate - Return the appropriate
495 /// immediate to insert at the specified INSERT_SUBVECTOR index
496 /// with VINSERTF128, VINSERT128 instructions.
497 unsigned getInsertVINSERT128Immediate(SDNode *N);
499 /// getExtractVEXTRACT256Immediate - Return the appropriate
500 /// immediate to extract the specified EXTRACT_SUBVECTOR index
501 /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
502 unsigned getExtractVEXTRACT256Immediate(SDNode *N);
504 /// getInsertVINSERT256Immediate - Return the appropriate
505 /// immediate to insert at the specified INSERT_SUBVECTOR index
506 /// with VINSERTF64x4, VINSERTI64x4 instructions.
507 unsigned getInsertVINSERT256Immediate(SDNode *N);
509 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
511 bool isZeroNode(SDValue Elt);
513 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
514 /// fit into displacement field of the instruction.
515 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
516 bool hasSymbolicDisplacement = true);
519 /// isCalleePop - Determines whether the callee is required to pop its
520 /// own arguments. Callee pop is necessary to support tail calls.
521 bool isCalleePop(CallingConv::ID CallingConv,
522 bool is64Bit, bool IsVarArg, bool TailCallOpt);
525 //===--------------------------------------------------------------------===//
526 // X86TargetLowering - X86 Implementation of the TargetLowering interface
527 class X86TargetLowering : public TargetLowering {
529 explicit X86TargetLowering(X86TargetMachine &TM);
531 virtual unsigned getJumpTableEncoding() const;
533 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
535 virtual const MCExpr *
536 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
537 const MachineBasicBlock *MBB, unsigned uid,
538 MCContext &Ctx) const;
540 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
542 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
543 SelectionDAG &DAG) const;
544 virtual const MCExpr *
545 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
546 unsigned JTI, MCContext &Ctx) const;
548 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
549 /// function arguments in the caller parameter area. For X86, aggregates
550 /// that contains are placed at 16-byte boundaries while the rest are at
551 /// 4-byte boundaries.
552 virtual unsigned getByValTypeAlignment(Type *Ty) const;
554 /// getOptimalMemOpType - Returns the target specific optimal type for load
555 /// and store operations as a result of memset, memcpy, and memmove
556 /// lowering. If DstAlign is zero that means it's safe to destination
557 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
558 /// means there isn't a need to check it against alignment requirement,
559 /// probably because the source does not need to be loaded. If 'IsMemset' is
560 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
561 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
562 /// source is constant so it does not need to be loaded.
563 /// It returns EVT::Other if the type should be determined using generic
564 /// target-independent logic.
566 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
567 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
568 MachineFunction &MF) const;
570 /// isSafeMemOpType - Returns true if it's safe to use load / store of the
571 /// specified type to expand memcpy / memset inline. This is mostly true
572 /// for all types except for some special cases. For example, on X86
573 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
574 /// also does type conversion. Note the specified type doesn't have to be
575 /// legal as the hook is used before type legalization.
576 virtual bool isSafeMemOpType(MVT VT) const;
578 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
579 /// unaligned memory accesses. of the specified type. Returns whether it
580 /// is "fast" by reference in the second argument.
581 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
583 /// LowerOperation - Provide custom lowering hooks for some operations.
585 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
587 /// ReplaceNodeResults - Replace the results of node with an illegal result
588 /// type with new values built out of custom code.
590 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
591 SelectionDAG &DAG) const;
594 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
596 /// isTypeDesirableForOp - Return true if the target has native support for
597 /// the specified value type and it is 'desirable' to use the type for the
598 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
599 /// instruction encodings are longer and some i16 instructions are slow.
600 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
602 /// isTypeDesirable - Return true if the target has native support for the
603 /// specified value type and it is 'desirable' to use the type. e.g. On x86
604 /// i16 is legal, but undesirable since i16 instruction encodings are longer
605 /// and some i16 instructions are slow.
606 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
608 virtual MachineBasicBlock *
609 EmitInstrWithCustomInserter(MachineInstr *MI,
610 MachineBasicBlock *MBB) const;
613 /// getTargetNodeName - This method returns the name of a target specific
615 virtual const char *getTargetNodeName(unsigned Opcode) const;
617 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
618 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
620 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
621 /// in Mask are known to be either zero or one and return them in the
622 /// KnownZero/KnownOne bitsets.
623 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
626 const SelectionDAG &DAG,
627 unsigned Depth = 0) const;
629 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
630 // operation that are sign bits.
631 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
632 unsigned Depth) const;
635 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
637 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
639 virtual bool ExpandInlineAsm(CallInst *CI) const;
641 ConstraintType getConstraintType(const std::string &Constraint) const;
643 /// Examine constraint string and operand type and determine a weight value.
644 /// The operand object must already have been set up with the operand type.
645 virtual ConstraintWeight getSingleConstraintMatchWeight(
646 AsmOperandInfo &info, const char *constraint) const;
648 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
650 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
651 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
652 /// true it means one of the asm constraint of the inline asm instruction
653 /// being processed is 'm'.
654 virtual void LowerAsmOperandForConstraint(SDValue Op,
655 std::string &Constraint,
656 std::vector<SDValue> &Ops,
657 SelectionDAG &DAG) const;
659 /// getRegForInlineAsmConstraint - Given a physical register constraint
660 /// (e.g. {edx}), return the register number and the register class for the
661 /// register. This should only be used for C_Register constraints. On
662 /// error, this returns a register number of 0.
663 std::pair<unsigned, const TargetRegisterClass*>
664 getRegForInlineAsmConstraint(const std::string &Constraint,
667 /// isLegalAddressingMode - Return true if the addressing mode represented
668 /// by AM is legal for this target, for a load/store of the specified type.
669 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
671 /// isLegalICmpImmediate - Return true if the specified immediate is legal
672 /// icmp immediate, that is the target has icmp instructions which can
673 /// compare a register against the immediate without having to materialize
674 /// the immediate into a register.
675 virtual bool isLegalICmpImmediate(int64_t Imm) const;
677 /// isLegalAddImmediate - Return true if the specified immediate is legal
678 /// add immediate, that is the target has add instructions which can
679 /// add a register and the immediate without having to materialize
680 /// the immediate into a register.
681 virtual bool isLegalAddImmediate(int64_t Imm) const;
683 /// isTruncateFree - Return true if it's free to truncate a value of
684 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
685 /// register EAX to i16 by referencing its sub-register AX.
686 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
687 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
689 virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const;
691 /// isZExtFree - Return true if any actual instruction that defines a
692 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
693 /// register. This does not necessarily include registers defined in
694 /// unknown ways, such as incoming arguments, or copies from unknown
695 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
696 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
697 /// all instructions that define 32-bit values implicit zero-extend the
698 /// result out to 64 bits.
699 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
700 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
701 virtual bool isZExtFree(SDValue Val, EVT VT2) const;
703 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
704 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
705 /// expanded to FMAs when this method returns true, otherwise fmuladd is
706 /// expanded to fmul + fadd.
707 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
709 /// isNarrowingProfitable - Return true if it's profitable to narrow
710 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
711 /// from i32 to i8 but not from i32 to i16.
712 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
714 /// isFPImmLegal - Returns true if the target can instruction select the
715 /// specified FP immediate natively. If false, the legalizer will
716 /// materialize the FP immediate as a load from a constant pool.
717 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
719 /// isShuffleMaskLegal - Targets can use this to indicate that they only
720 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
721 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
722 /// values are assumed to be legal.
723 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
726 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
727 /// used by Targets can use this to indicate if there is a suitable
728 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
730 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
733 /// ShouldShrinkFPConstant - If true, then instruction selection should
734 /// seek to shrink the FP constant of the specified type to a smaller type
735 /// in order to save space and / or reduce runtime.
736 virtual bool ShouldShrinkFPConstant(EVT VT) const {
737 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
738 // expensive than a straight movsd. On the other hand, it's important to
739 // shrink long double fp constant since fldt is very slow.
740 return !X86ScalarSSEf64 || VT == MVT::f80;
743 const X86Subtarget* getSubtarget() const {
747 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
748 /// computed in an SSE register, not on the X87 floating point stack.
749 bool isScalarFPTypeInSSEReg(EVT VT) const {
750 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
751 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
754 /// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine
756 bool isTargetFTOL() const {
757 return Subtarget->isTargetWindows() && !Subtarget->is64Bit();
760 /// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be
761 /// used for fptoui to the given type.
762 bool isIntegerTypeFTOL(EVT VT) const {
763 return isTargetFTOL() && VT == MVT::i64;
766 /// createFastISel - This method returns a target specific FastISel object,
767 /// or null if the target does not support "fast" ISel.
768 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
769 const TargetLibraryInfo *libInfo) const;
771 /// getStackCookieLocation - Return true if the target stores stack
772 /// protector cookies at a fixed offset in some non-standard address
773 /// space, and populates the address space and offset as
775 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
777 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
778 SelectionDAG &DAG) const;
780 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const LLVM_OVERRIDE;
782 /// \brief Reset the operation actions based on target options.
783 virtual void resetOperationActions();
786 std::pair<const TargetRegisterClass*, uint8_t>
787 findRepresentativeClass(MVT VT) const;
790 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
791 /// make the right decision when generating code for different targets.
792 const X86Subtarget *Subtarget;
793 const DataLayout *TD;
795 /// Used to store the TargetOptions so that we don't waste time resetting
796 /// the operation actions unless we have to.
799 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
800 /// floating point ops.
801 /// When SSE is available, use it for f32 operations.
802 /// When SSE2 is available, use it for f64 operations.
803 bool X86ScalarSSEf32;
804 bool X86ScalarSSEf64;
806 /// LegalFPImmediates - A list of legal fp immediates.
807 std::vector<APFloat> LegalFPImmediates;
809 /// addLegalFPImmediate - Indicate that this x86 target can instruction
810 /// select the specified FP immediate natively.
811 void addLegalFPImmediate(const APFloat& Imm) {
812 LegalFPImmediates.push_back(Imm);
815 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
816 CallingConv::ID CallConv, bool isVarArg,
817 const SmallVectorImpl<ISD::InputArg> &Ins,
818 SDLoc dl, SelectionDAG &DAG,
819 SmallVectorImpl<SDValue> &InVals) const;
820 SDValue LowerMemArgument(SDValue Chain,
821 CallingConv::ID CallConv,
822 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
823 SDLoc dl, SelectionDAG &DAG,
824 const CCValAssign &VA, MachineFrameInfo *MFI,
826 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
827 SDLoc dl, SelectionDAG &DAG,
828 const CCValAssign &VA,
829 ISD::ArgFlagsTy Flags) const;
831 // Call lowering helpers.
833 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
834 /// for tail call optimization. Targets which want to do tail call
835 /// optimization should implement this function.
836 bool IsEligibleForTailCallOptimization(SDValue Callee,
837 CallingConv::ID CalleeCC,
839 bool isCalleeStructRet,
840 bool isCallerStructRet,
842 const SmallVectorImpl<ISD::OutputArg> &Outs,
843 const SmallVectorImpl<SDValue> &OutVals,
844 const SmallVectorImpl<ISD::InputArg> &Ins,
845 SelectionDAG& DAG) const;
846 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
847 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
848 SDValue Chain, bool IsTailCall, bool Is64Bit,
849 int FPDiff, SDLoc dl) const;
851 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
852 SelectionDAG &DAG) const;
854 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
856 bool isReplace) const;
858 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
859 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
860 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
861 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
862 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
863 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
864 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
865 SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
866 int64_t Offset, SelectionDAG &DAG) const;
867 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
868 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
869 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
870 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
871 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
872 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
873 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
874 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
875 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
876 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
877 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
878 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
879 SDLoc dl, SelectionDAG &DAG) const;
880 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
881 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
882 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
883 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
884 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
885 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
886 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
887 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
888 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
889 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
890 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
891 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
892 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
893 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
894 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
895 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
896 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
899 LowerFormalArguments(SDValue Chain,
900 CallingConv::ID CallConv, bool isVarArg,
901 const SmallVectorImpl<ISD::InputArg> &Ins,
902 SDLoc dl, SelectionDAG &DAG,
903 SmallVectorImpl<SDValue> &InVals) const;
905 LowerCall(CallLoweringInfo &CLI,
906 SmallVectorImpl<SDValue> &InVals) const;
909 LowerReturn(SDValue Chain,
910 CallingConv::ID CallConv, bool isVarArg,
911 const SmallVectorImpl<ISD::OutputArg> &Outs,
912 const SmallVectorImpl<SDValue> &OutVals,
913 SDLoc dl, SelectionDAG &DAG) const;
915 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
917 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
920 getTypeForExtArgOrReturn(MVT VT, ISD::NodeType ExtendKind) const;
923 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
925 const SmallVectorImpl<ISD::OutputArg> &Outs,
926 LLVMContext &Context) const;
928 virtual const uint16_t *getScratchRegisters(CallingConv::ID CC) const;
930 /// Utility function to emit atomic-load-arith operations (and, or, xor,
931 /// nand, max, min, umax, umin). It takes the corresponding instruction to
932 /// expand, the associated machine basic block, and the associated X86
933 /// opcodes for reg/reg.
934 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
935 MachineBasicBlock *MBB) const;
937 /// Utility function to emit atomic-load-arith operations (and, or, xor,
938 /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
939 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
940 MachineBasicBlock *MBB) const;
942 // Utility function to emit the low-level va_arg code for X86-64.
943 MachineBasicBlock *EmitVAARG64WithCustomInserter(
945 MachineBasicBlock *MBB) const;
947 /// Utility function to emit the xmm reg save portion of va_start.
948 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
949 MachineInstr *BInstr,
950 MachineBasicBlock *BB) const;
952 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
953 MachineBasicBlock *BB) const;
955 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
956 MachineBasicBlock *BB) const;
958 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
959 MachineBasicBlock *BB,
962 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
963 MachineBasicBlock *BB) const;
965 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
966 MachineBasicBlock *BB) const;
968 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
969 MachineBasicBlock *MBB) const;
971 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
972 MachineBasicBlock *MBB) const;
974 /// Emit nodes that will be selected as "test Op0,Op0", or something
975 /// equivalent, for use with the given x86 condition code.
976 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
978 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
979 /// equivalent, for use with the given x86 condition code.
980 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
981 SelectionDAG &DAG) const;
983 /// Convert a comparison if required by the subtarget.
984 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
988 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
989 const TargetLibraryInfo *libInfo);
993 #endif // X86ISELLOWERING_H