1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetOptions.h"
25 class X86TargetMachine;
28 // X86 Specific DAG Nodes
30 // Start the numbering where the builtin ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 /// BSF - Bit scan forward.
34 /// BSR - Bit scan reverse.
38 /// SHLD, SHRD - Double shift instructions. These correspond to
39 /// X86::SHLDxx and X86::SHRDxx instructions.
43 /// FAND - Bitwise logical AND of floating point values. This corresponds
44 /// to X86::ANDPS or X86::ANDPD.
47 /// FOR - Bitwise logical OR of floating point values. This corresponds
48 /// to X86::ORPS or X86::ORPD.
51 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
52 /// to X86::XORPS or X86::XORPD.
55 /// FANDN - Bitwise logical ANDNOT of floating point values. This
56 /// corresponds to X86::ANDNPS or X86::ANDNPD.
59 /// FSRL - Bitwise logical right shift of floating point values. These
60 /// corresponds to X86::PSRLDQ.
63 /// CALL - These operations represent an abstract X86 call
64 /// instruction, which includes a bunch of information. In particular the
65 /// operands of these node are:
67 /// #0 - The incoming token chain
69 /// #2 - The number of arg bytes the caller pushes on the stack.
70 /// #3 - The number of arg bytes the callee pops off the stack.
71 /// #4 - The value to pass in AL/AX/EAX (optional)
72 /// #5 - The value to pass in DL/DX/EDX (optional)
74 /// The result values of these nodes are:
76 /// #0 - The outgoing token chain
77 /// #1 - The first register result value (optional)
78 /// #2 - The second register result value (optional)
82 /// RDTSC_DAG - This operation implements the lowering for
86 /// X86 Read Time-Stamp Counter and Processor ID.
89 /// X86 Read Performance Monitoring Counters.
92 /// X86 compare and logical compare instructions.
95 /// X86 bit-test instructions.
98 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
99 /// operand, usually produced by a CMP instruction.
105 // Same as SETCC except it's materialized with a sbb and the value is all
106 // one's or all zero's.
107 SETCC_CARRY, // R = carry_bit ? ~0 : 0
109 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
110 /// Operands are two FP values to compare; result is a mask of
111 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
114 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
115 /// result in an integer GPR. Needs masking for scalar result.
118 /// X86 conditional moves. Operand 0 and operand 1 are the two values
119 /// to select from. Operand 2 is the condition code, and operand 3 is the
120 /// flag operand produced by a CMP or TEST instruction. It also writes a
124 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
125 /// is the block to branch if condition is true, operand 2 is the
126 /// condition code, and operand 3 is the flag operand produced by a CMP
127 /// or TEST instruction.
130 /// Return with a flag operand. Operand 0 is the chain operand, operand
131 /// 1 is the number of bytes of stack to pop.
134 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
137 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
140 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
141 /// at function entry, used for PIC code.
144 /// Wrapper - A wrapper node for TargetConstantPool,
145 /// TargetExternalSymbol, and TargetGlobalAddress.
148 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
149 /// relative displacements.
152 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
153 /// to an MMX vector. If you think this is too close to the previous
154 /// mnemonic, so do I; blame Intel.
157 /// MMX_MOVD2W - Copies a 32-bit value from the low word of a MMX
161 /// MMX_MOVW2D - Copies a GPR into the low 32-bit word of a MMX vector
162 /// and zero out the high word.
165 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
166 /// i32, corresponds to X86::PEXTRB.
169 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
170 /// i32, corresponds to X86::PEXTRW.
173 /// INSERTPS - Insert any element of a 4 x float vector into any element
174 /// of a destination 4 x floatvector.
177 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
178 /// corresponds to X86::PINSRB.
181 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
182 /// corresponds to X86::PINSRW.
185 /// PSHUFB - Shuffle 16 8-bit values within a vector.
188 /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
191 /// PSIGN - Copy integer sign.
194 /// BLENDI - Blend where the selector is an immediate.
197 /// SHRUNKBLEND - Blend where the condition has been shrunk.
198 /// This is used to emphasize that the condition mask is
199 /// no more valid for generic VSELECT optimizations.
202 /// ADDSUB - Combined add and sub on an FP vector.
205 // SUBUS - Integer sub with unsigned saturation.
208 /// HADD - Integer horizontal add.
211 /// HSUB - Integer horizontal sub.
214 /// FHADD - Floating point horizontal add.
217 /// FHSUB - Floating point horizontal sub.
220 /// UMAX, UMIN - Unsigned integer max and min.
223 /// SMAX, SMIN - Signed integer max and min.
226 /// FMAX, FMIN - Floating point max and min.
230 /// FMAXC, FMINC - Commutative FMIN and FMAX.
233 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
234 /// approximation. Note that these typically require refinement
235 /// in order to obtain suitable precision.
238 // TLSADDR - Thread Local Storage.
241 // TLSBASEADDR - Thread Local Storage. A call to get the start address
242 // of the TLS block for the current module.
245 // TLSCALL - Thread Local Storage. When calling to an OS provided
246 // thunk at the address from an earlier relocation.
249 // EH_RETURN - Exception Handling helpers.
252 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
255 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
258 /// TC_RETURN - Tail call return. See X86TargetLowering::LowerCall for
259 /// the list of operands.
262 // VZEXT_MOVL - Vector move to low scalar and zero higher vector elements.
265 // VZEXT - Vector integer zero-extend.
268 // VSEXT - Vector integer signed-extend.
271 // VTRUNC - Vector integer truncate.
274 // VTRUNC - Vector integer truncate with mask.
277 // VFPEXT - Vector FP extend.
280 // VFPROUND - Vector FP round.
283 // VSHL, VSRL - 128-bit vector logical left / right shift
286 // VSHL, VSRL, VSRA - Vector shift elements
289 // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate
292 // CMPP - Vector packed double/float comparison.
295 // PCMP* - Vector integer comparisons.
297 // PCMP*M - Vector integer comparisons, the result is in a mask vector.
300 /// CMPM, CMPMU - Vector comparison generating mask bits for fp and
301 /// integer signed and unsigned data types.
305 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
306 ADD, SUB, ADC, SBB, SMUL,
307 INC, DEC, OR, XOR, AND,
309 BEXTR, // BEXTR - Bit field extract
311 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
313 // 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS
316 // 8-bit divrem that zero-extend the high result (AH).
320 // MUL_IMM - X86 specific multiply by immediate.
323 // PTEST - Vector bitwise comparisons.
326 // TESTP - Vector packed fp sign bitwise comparisons.
329 // TESTM, TESTNM - Vector "test" in AVX-512, the result is in a mask vector.
333 // OR/AND test for masks
336 // Several flavors of instructions with vector shuffle behaviors.
341 // AVX512 inter-lane alignr
369 // Insert/Extract vector element
373 // Vector multiply packed unsigned doubleword integers
375 // Vector multiply packed signed doubleword integers
385 // FMA with rounding mode
393 // Compress and expand
397 // Save xmm argument registers to the stack, according to %al. An operator
398 // is needed so that this can be expanded with control flow.
399 VASTART_SAVE_XMM_REGS,
401 // Windows's _chkstk call to do stack probing.
404 // For allocating variable amounts of stack space when using
405 // segmented stacks. Check if the current stacklet has enough space, and
406 // falls back to heap allocation if not.
409 // Windows's _ftol2 runtime routine to do fptoui.
418 // Store FP status word into i16 register.
421 // Store contents of %ah into %eflags.
424 // Get a random integer and indicate whether it is valid in CF.
427 // Get a NIST SP800-90B & C compliant random integer and
428 // indicate whether it is valid in CF.
434 // Test if in transactional execution.
438 RSQRT28, RCP28, EXP2,
441 LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
445 // Load, scalar_to_vector, and zero extend.
448 // Store FP control world into i16 memory.
451 /// This instruction implements FP_TO_SINT with the
452 /// integer destination in memory and a FP reg source. This corresponds
453 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
454 /// has two inputs (token chain and address) and two outputs (int value
455 /// and token chain).
460 /// This instruction implements SINT_TO_FP with the
461 /// integer source in memory and FP reg result. This corresponds to the
462 /// X86::FILD*m instructions. It has three inputs (token chain, address,
463 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
464 /// also produces a flag).
468 /// This instruction implements an extending load to FP stack slots.
469 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
470 /// operand, ptr to load from, and a ValueType node indicating the type
474 /// This instruction implements a truncating store to FP stack
475 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
476 /// chain operand, value to store, address, and a ValueType to store it
480 /// This instruction grabs the address of the next argument
481 /// from a va_list. (reads and modifies the va_list in memory)
484 // WARNING: Do not add anything in the end unless you want the node to
485 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
486 // thought as target memory ops!
490 /// Define some predicates that are used for node matching.
492 /// Return true if the specified
493 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
494 /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
495 bool isVEXTRACT128Index(SDNode *N);
497 /// Return true if the specified
498 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
499 /// suitable for input to VINSERTF128, VINSERTI128 instructions.
500 bool isVINSERT128Index(SDNode *N);
502 /// Return true if the specified
503 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
504 /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
505 bool isVEXTRACT256Index(SDNode *N);
507 /// Return true if the specified
508 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
509 /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
510 bool isVINSERT256Index(SDNode *N);
512 /// Return the appropriate
513 /// immediate to extract the specified EXTRACT_SUBVECTOR index
514 /// with VEXTRACTF128, VEXTRACTI128 instructions.
515 unsigned getExtractVEXTRACT128Immediate(SDNode *N);
517 /// Return the appropriate
518 /// immediate to insert at the specified INSERT_SUBVECTOR index
519 /// with VINSERTF128, VINSERT128 instructions.
520 unsigned getInsertVINSERT128Immediate(SDNode *N);
522 /// Return the appropriate
523 /// immediate to extract the specified EXTRACT_SUBVECTOR index
524 /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
525 unsigned getExtractVEXTRACT256Immediate(SDNode *N);
527 /// Return the appropriate
528 /// immediate to insert at the specified INSERT_SUBVECTOR index
529 /// with VINSERTF64x4, VINSERTI64x4 instructions.
530 unsigned getInsertVINSERT256Immediate(SDNode *N);
532 /// Returns true if Elt is a constant zero or floating point constant +0.0.
533 bool isZeroNode(SDValue Elt);
535 /// Returns true of the given offset can be
536 /// fit into displacement field of the instruction.
537 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
538 bool hasSymbolicDisplacement = true);
541 /// Determines whether the callee is required to pop its
542 /// own arguments. Callee pop is necessary to support tail calls.
543 bool isCalleePop(CallingConv::ID CallingConv,
544 bool is64Bit, bool IsVarArg, bool TailCallOpt);
546 /// AVX512 static rounding constants. These need to match the values in
548 enum STATIC_ROUNDING {
557 //===--------------------------------------------------------------------===//
558 // X86 Implementation of the TargetLowering interface
559 class X86TargetLowering final : public TargetLowering {
561 explicit X86TargetLowering(const X86TargetMachine &TM,
562 const X86Subtarget &STI);
564 unsigned getJumpTableEncoding() const override;
566 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i8; }
569 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
570 const MachineBasicBlock *MBB, unsigned uid,
571 MCContext &Ctx) const override;
573 /// Returns relocation base for the given PIC jumptable.
574 SDValue getPICJumpTableRelocBase(SDValue Table,
575 SelectionDAG &DAG) const override;
577 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
578 unsigned JTI, MCContext &Ctx) const override;
580 /// Return the desired alignment for ByVal aggregate
581 /// function arguments in the caller parameter area. For X86, aggregates
582 /// that contains are placed at 16-byte boundaries while the rest are at
583 /// 4-byte boundaries.
584 unsigned getByValTypeAlignment(Type *Ty) const override;
586 /// Returns the target specific optimal type for load
587 /// and store operations as a result of memset, memcpy, and memmove
588 /// lowering. If DstAlign is zero that means it's safe to destination
589 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
590 /// means there isn't a need to check it against alignment requirement,
591 /// probably because the source does not need to be loaded. If 'IsMemset' is
592 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
593 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
594 /// source is constant so it does not need to be loaded.
595 /// It returns EVT::Other if the type should be determined using generic
596 /// target-independent logic.
597 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
598 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
599 MachineFunction &MF) const override;
601 /// Returns true if it's safe to use load / store of the
602 /// specified type to expand memcpy / memset inline. This is mostly true
603 /// for all types except for some special cases. For example, on X86
604 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
605 /// also does type conversion. Note the specified type doesn't have to be
606 /// legal as the hook is used before type legalization.
607 bool isSafeMemOpType(MVT VT) const override;
609 /// Returns true if the target allows
610 /// unaligned memory accesses. of the specified type. Returns whether it
611 /// is "fast" by reference in the second argument.
612 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
613 bool *Fast) const override;
615 /// Provide custom lowering hooks for some operations.
617 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
619 /// Replace the results of node with an illegal result
620 /// type with new values built out of custom code.
622 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
623 SelectionDAG &DAG) const override;
626 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
628 /// Return true if the target has native support for
629 /// the specified value type and it is 'desirable' to use the type for the
630 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
631 /// instruction encodings are longer and some i16 instructions are slow.
632 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
634 /// Return true if the target has native support for the
635 /// specified value type and it is 'desirable' to use the type. e.g. On x86
636 /// i16 is legal, but undesirable since i16 instruction encodings are longer
637 /// and some i16 instructions are slow.
638 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
641 EmitInstrWithCustomInserter(MachineInstr *MI,
642 MachineBasicBlock *MBB) const override;
645 /// This method returns the name of a target specific DAG node.
646 const char *getTargetNodeName(unsigned Opcode) const override;
648 bool isCheapToSpeculateCttz() const override;
650 bool isCheapToSpeculateCtlz() const override;
652 /// Return the value type to use for ISD::SETCC.
653 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
655 /// Determine which of the bits specified in Mask are known to be either
656 /// zero or one and return them in the KnownZero/KnownOne bitsets.
657 void computeKnownBitsForTargetNode(const SDValue Op,
660 const SelectionDAG &DAG,
661 unsigned Depth = 0) const override;
663 /// Determine the number of bits in the operation that are sign bits.
664 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
665 const SelectionDAG &DAG,
666 unsigned Depth) const override;
668 bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
669 int64_t &Offset) const override;
671 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
673 bool ExpandInlineAsm(CallInst *CI) const override;
676 getConstraintType(const std::string &Constraint) const override;
678 /// Examine constraint string and operand type and determine a weight value.
679 /// The operand object must already have been set up with the operand type.
681 getSingleConstraintMatchWeight(AsmOperandInfo &info,
682 const char *constraint) const override;
684 const char *LowerXConstraint(EVT ConstraintVT) const override;
686 /// Lower the specified operand into the Ops vector. If it is invalid, don't
687 /// add anything to Ops. If hasMemory is true it means one of the asm
688 /// constraint of the inline asm instruction being processed is 'm'.
689 void LowerAsmOperandForConstraint(SDValue Op,
690 std::string &Constraint,
691 std::vector<SDValue> &Ops,
692 SelectionDAG &DAG) const override;
694 /// Given a physical register constraint
695 /// (e.g. {edx}), return the register number and the register class for the
696 /// register. This should only be used for C_Register constraints. On
697 /// error, this returns a register number of 0.
698 std::pair<unsigned, const TargetRegisterClass*>
699 getRegForInlineAsmConstraint(const std::string &Constraint,
700 MVT VT) const override;
702 /// Return true if the addressing mode represented
703 /// by AM is legal for this target, for a load/store of the specified type.
704 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
706 /// Return true if the specified immediate is legal
707 /// icmp immediate, that is the target has icmp instructions which can
708 /// compare a register against the immediate without having to materialize
709 /// the immediate into a register.
710 bool isLegalICmpImmediate(int64_t Imm) const override;
712 /// Return true if the specified immediate is legal
713 /// add immediate, that is the target has add instructions which can
714 /// add a register and the immediate without having to materialize
715 /// the immediate into a register.
716 bool isLegalAddImmediate(int64_t Imm) const override;
718 /// \brief Return the cost of the scaling factor used in the addressing
719 /// mode represented by AM for this target, for a load/store
720 /// of the specified type.
721 /// If the AM is supported, the return value must be >= 0.
722 /// If the AM is not supported, it returns a negative value.
723 int getScalingFactorCost(const AddrMode &AM, Type *Ty) const override;
725 bool isVectorShiftByScalarCheap(Type *Ty) const override;
727 /// Return true if it's free to truncate a value of
728 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
729 /// register EAX to i16 by referencing its sub-register AX.
730 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
731 bool isTruncateFree(EVT VT1, EVT VT2) const override;
733 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
735 /// Return true if any actual instruction that defines a
736 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
737 /// register. This does not necessarily include registers defined in
738 /// unknown ways, such as incoming arguments, or copies from unknown
739 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
740 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
741 /// all instructions that define 32-bit values implicit zero-extend the
742 /// result out to 64 bits.
743 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
744 bool isZExtFree(EVT VT1, EVT VT2) const override;
745 bool isZExtFree(SDValue Val, EVT VT2) const override;
747 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
748 /// extend node) is profitable.
749 bool isVectorLoadExtDesirable(SDValue) const override;
751 /// Return true if an FMA operation is faster than a pair of fmul and fadd
752 /// instructions. fmuladd intrinsics will be expanded to FMAs when this
753 /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
754 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
756 /// Return true if it's profitable to narrow
757 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
758 /// from i32 to i8 but not from i32 to i16.
759 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
761 /// Returns true if the target can instruction select the
762 /// specified FP immediate natively. If false, the legalizer will
763 /// materialize the FP immediate as a load from a constant pool.
764 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
766 /// Targets can use this to indicate that they only support *some*
767 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
768 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
770 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
771 EVT VT) const override;
773 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
774 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to
775 /// replace a VAND with a constant pool entry.
776 bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
777 EVT VT) const override;
779 /// If true, then instruction selection should
780 /// seek to shrink the FP constant of the specified type to a smaller type
781 /// in order to save space and / or reduce runtime.
782 bool ShouldShrinkFPConstant(EVT VT) const override {
783 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
784 // expensive than a straight movsd. On the other hand, it's important to
785 // shrink long double fp constant since fldt is very slow.
786 return !X86ScalarSSEf64 || VT == MVT::f80;
789 /// Return true if we believe it is correct and profitable to reduce the
790 /// load node to a smaller type.
791 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
792 EVT NewVT) const override;
794 /// Return true if the specified scalar FP type is computed in an SSE
795 /// register, not on the X87 floating point stack.
796 bool isScalarFPTypeInSSEReg(EVT VT) const {
797 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
798 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
801 /// Return true if the target uses the MSVC _ftol2 routine for fptoui.
802 bool isTargetFTOL() const;
804 /// Return true if the MSVC _ftol2 routine should be used for fptoui to the
806 bool isIntegerTypeFTOL(EVT VT) const {
807 return isTargetFTOL() && VT == MVT::i64;
810 /// \brief Returns true if it is beneficial to convert a load of a constant
811 /// to just the constant itself.
812 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
813 Type *Ty) const override;
815 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
817 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
819 /// Intel processors have a unified instruction and data cache
820 const char * getClearCacheBuiltinName() const override {
821 return nullptr; // nothing to do, move along.
824 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
826 /// This method returns a target specific FastISel object,
827 /// or null if the target does not support "fast" ISel.
828 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
829 const TargetLibraryInfo *libInfo) const override;
831 /// Return true if the target stores stack protector cookies at a fixed
832 /// offset in some non-standard address space, and populates the address
833 /// space and offset as appropriate.
834 bool getStackCookieLocation(unsigned &AddressSpace,
835 unsigned &Offset) const override;
837 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
838 SelectionDAG &DAG) const;
840 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
842 bool useLoadStackGuardNode() const override;
843 /// \brief Customize the preferred legalization strategy for certain types.
844 LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
847 std::pair<const TargetRegisterClass*, uint8_t>
848 findRepresentativeClass(MVT VT) const override;
851 /// Keep a pointer to the X86Subtarget around so that we can
852 /// make the right decision when generating code for different targets.
853 const X86Subtarget *Subtarget;
854 const DataLayout *TD;
856 /// Select between SSE or x87 floating point ops.
857 /// When SSE is available, use it for f32 operations.
858 /// When SSE2 is available, use it for f64 operations.
859 bool X86ScalarSSEf32;
860 bool X86ScalarSSEf64;
862 /// A list of legal FP immediates.
863 std::vector<APFloat> LegalFPImmediates;
865 /// Indicate that this x86 target can instruction
866 /// select the specified FP immediate natively.
867 void addLegalFPImmediate(const APFloat& Imm) {
868 LegalFPImmediates.push_back(Imm);
871 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
872 CallingConv::ID CallConv, bool isVarArg,
873 const SmallVectorImpl<ISD::InputArg> &Ins,
874 SDLoc dl, SelectionDAG &DAG,
875 SmallVectorImpl<SDValue> &InVals) const;
876 SDValue LowerMemArgument(SDValue Chain,
877 CallingConv::ID CallConv,
878 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
879 SDLoc dl, SelectionDAG &DAG,
880 const CCValAssign &VA, MachineFrameInfo *MFI,
882 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
883 SDLoc dl, SelectionDAG &DAG,
884 const CCValAssign &VA,
885 ISD::ArgFlagsTy Flags) const;
887 // Call lowering helpers.
889 /// Check whether the call is eligible for tail call optimization. Targets
890 /// that want to do tail call optimization should implement this function.
891 bool IsEligibleForTailCallOptimization(SDValue Callee,
892 CallingConv::ID CalleeCC,
894 bool isCalleeStructRet,
895 bool isCallerStructRet,
897 const SmallVectorImpl<ISD::OutputArg> &Outs,
898 const SmallVectorImpl<SDValue> &OutVals,
899 const SmallVectorImpl<ISD::InputArg> &Ins,
900 SelectionDAG& DAG) const;
901 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
902 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
903 SDValue Chain, bool IsTailCall, bool Is64Bit,
904 int FPDiff, SDLoc dl) const;
906 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
907 SelectionDAG &DAG) const;
909 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
911 bool isReplace) const;
913 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
914 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
915 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
916 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
917 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
918 SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const;
919 SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const;
921 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
922 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
923 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
924 SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
925 int64_t Offset, SelectionDAG &DAG) const;
926 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
927 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
928 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
929 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
930 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
931 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
932 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
933 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
934 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
935 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
936 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
937 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
938 SDLoc dl, SelectionDAG &DAG) const;
939 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
940 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
941 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
942 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
943 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
944 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
945 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
946 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
947 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
948 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
949 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
950 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
951 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
952 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
953 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
954 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
955 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
956 SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
959 LowerFormalArguments(SDValue Chain,
960 CallingConv::ID CallConv, bool isVarArg,
961 const SmallVectorImpl<ISD::InputArg> &Ins,
962 SDLoc dl, SelectionDAG &DAG,
963 SmallVectorImpl<SDValue> &InVals) const override;
964 SDValue LowerCall(CallLoweringInfo &CLI,
965 SmallVectorImpl<SDValue> &InVals) const override;
967 SDValue LowerReturn(SDValue Chain,
968 CallingConv::ID CallConv, bool isVarArg,
969 const SmallVectorImpl<ISD::OutputArg> &Outs,
970 const SmallVectorImpl<SDValue> &OutVals,
971 SDLoc dl, SelectionDAG &DAG) const override;
973 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
975 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
977 EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
978 ISD::NodeType ExtendKind) const override;
980 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
982 const SmallVectorImpl<ISD::OutputArg> &Outs,
983 LLVMContext &Context) const override;
985 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
987 bool shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
988 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
989 bool shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
992 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
994 bool needsCmpXchgNb(const Type *MemType) const;
996 /// Utility function to emit atomic-load-arith operations (and, or, xor,
997 /// nand, max, min, umax, umin). It takes the corresponding instruction to
998 /// expand, the associated machine basic block, and the associated X86
999 /// opcodes for reg/reg.
1000 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
1001 MachineBasicBlock *MBB) const;
1003 /// Utility function to emit atomic-load-arith operations (and, or, xor,
1004 /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
1005 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
1006 MachineBasicBlock *MBB) const;
1008 // Utility function to emit the low-level va_arg code for X86-64.
1009 MachineBasicBlock *EmitVAARG64WithCustomInserter(
1011 MachineBasicBlock *MBB) const;
1013 /// Utility function to emit the xmm reg save portion of va_start.
1014 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
1015 MachineInstr *BInstr,
1016 MachineBasicBlock *BB) const;
1018 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
1019 MachineBasicBlock *BB) const;
1021 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
1022 MachineBasicBlock *BB) const;
1024 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
1025 MachineBasicBlock *BB) const;
1027 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
1028 MachineBasicBlock *BB) const;
1030 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
1031 MachineBasicBlock *BB) const;
1033 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
1034 MachineBasicBlock *MBB) const;
1036 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
1037 MachineBasicBlock *MBB) const;
1039 MachineBasicBlock *emitFMA3Instr(MachineInstr *MI,
1040 MachineBasicBlock *MBB) const;
1042 /// Emit nodes that will be selected as "test Op0,Op0", or something
1043 /// equivalent, for use with the given x86 condition code.
1044 SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl,
1045 SelectionDAG &DAG) const;
1047 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
1048 /// equivalent, for use with the given x86 condition code.
1049 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl,
1050 SelectionDAG &DAG) const;
1052 /// Convert a comparison if required by the subtarget.
1053 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
1055 /// Use rsqrt* to speed up sqrt calculations.
1056 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1057 unsigned &RefinementSteps,
1058 bool &UseOneConstNR) const override;
1060 /// Use rcp* to speed up fdiv calculations.
1061 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1062 unsigned &RefinementSteps) const override;
1066 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1067 const TargetLibraryInfo *libInfo);
1071 #endif // X86ISELLOWERING_H