1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetOptions.h"
25 class X86TargetMachine;
28 // X86 Specific DAG Nodes
29 enum NodeType : unsigned {
30 // Start the numbering where the builtin ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
38 /// Double shift instructions. These correspond to
39 /// X86::SHLDxx and X86::SHRDxx instructions.
43 /// Bitwise logical AND of floating point values. This corresponds
44 /// to X86::ANDPS or X86::ANDPD.
47 /// Bitwise logical OR of floating point values. This corresponds
48 /// to X86::ORPS or X86::ORPD.
51 /// Bitwise logical XOR of floating point values. This corresponds
52 /// to X86::XORPS or X86::XORPD.
55 /// Bitwise logical ANDNOT of floating point values. This
56 /// corresponds to X86::ANDNPS or X86::ANDNPD.
59 /// These operations represent an abstract X86 call
60 /// instruction, which includes a bunch of information. In particular the
61 /// operands of these node are:
63 /// #0 - The incoming token chain
65 /// #2 - The number of arg bytes the caller pushes on the stack.
66 /// #3 - The number of arg bytes the callee pops off the stack.
67 /// #4 - The value to pass in AL/AX/EAX (optional)
68 /// #5 - The value to pass in DL/DX/EDX (optional)
70 /// The result values of these nodes are:
72 /// #0 - The outgoing token chain
73 /// #1 - The first register result value (optional)
74 /// #2 - The second register result value (optional)
78 /// This operation implements the lowering for readcyclecounter
81 /// X86 Read Time-Stamp Counter and Processor ID.
84 /// X86 Read Performance Monitoring Counters.
87 /// X86 compare and logical compare instructions.
90 /// X86 bit-test instructions.
93 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
94 /// operand, usually produced by a CMP instruction.
100 // Same as SETCC except it's materialized with a sbb and the value is all
101 // one's or all zero's.
102 SETCC_CARRY, // R = carry_bit ? ~0 : 0
104 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
105 /// Operands are two FP values to compare; result is a mask of
106 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
109 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
110 /// result in an integer GPR. Needs masking for scalar result.
113 /// X86 conditional moves. Operand 0 and operand 1 are the two values
114 /// to select from. Operand 2 is the condition code, and operand 3 is the
115 /// flag operand produced by a CMP or TEST instruction. It also writes a
119 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
120 /// is the block to branch if condition is true, operand 2 is the
121 /// condition code, and operand 3 is the flag operand produced by a CMP
122 /// or TEST instruction.
125 /// Return with a flag operand. Operand 0 is the chain operand, operand
126 /// 1 is the number of bytes of stack to pop.
129 /// Repeat fill, corresponds to X86::REP_STOSx.
132 /// Repeat move, corresponds to X86::REP_MOVSx.
135 /// On Darwin, this node represents the result of the popl
136 /// at function entry, used for PIC code.
139 /// A wrapper node for TargetConstantPool,
140 /// TargetExternalSymbol, and TargetGlobalAddress.
143 /// Special wrapper used under X86-64 PIC mode for RIP
144 /// relative displacements.
147 /// Copies a 64-bit value from the low word of an XMM vector
148 /// to an MMX vector. If you think this is too close to the previous
149 /// mnemonic, so do I; blame Intel.
152 /// Copies a 32-bit value from the low word of a MMX
156 /// Copies a GPR into the low 32-bit word of a MMX vector
157 /// and zero out the high word.
160 /// Extract an 8-bit value from a vector and zero extend it to
161 /// i32, corresponds to X86::PEXTRB.
164 /// Extract a 16-bit value from a vector and zero extend it to
165 /// i32, corresponds to X86::PEXTRW.
168 /// Insert any element of a 4 x float vector into any element
169 /// of a destination 4 x floatvector.
172 /// Insert the lower 8-bits of a 32-bit value to a vector,
173 /// corresponds to X86::PINSRB.
176 /// Insert the lower 16-bits of a 32-bit value to a vector,
177 /// corresponds to X86::PINSRW.
180 /// Shuffle 16 8-bit values within a vector.
183 /// Compute Sum of Absolute Differences.
185 /// Compute Double Block Packed Sum-Absolute-Differences
188 /// Bitwise Logical AND NOT of Packed FP values.
191 /// Copy integer sign.
194 /// Blend where the selector is an immediate.
197 /// Blend where the condition has been shrunk.
198 /// This is used to emphasize that the condition mask is
199 /// no more valid for generic VSELECT optimizations.
202 /// Combined add and sub on an FP vector.
205 // FP vector ops with rounding mode.
214 // FP vector get exponent
216 // Extract Normalized Mantissas
220 // Integer add/sub with unsigned saturation.
223 // Integer add/sub with signed saturation.
226 // Unsigned Integer average
228 /// Integer horizontal add.
231 /// Integer horizontal sub.
234 /// Floating point horizontal add.
237 /// Floating point horizontal sub.
240 // Integer absolute value
243 // Detect Conflicts Within a Vector
246 /// Floating point max and min.
249 /// Commutative FMIN and FMAX.
252 /// Floating point reciprocal-sqrt and reciprocal approximation.
253 /// Note that these typically require refinement
254 /// in order to obtain suitable precision.
257 // Thread Local Storage.
260 // Thread Local Storage. A call to get the start address
261 // of the TLS block for the current module.
264 // Thread Local Storage. When calling to an OS provided
265 // thunk at the address from an earlier relocation.
268 // Exception Handling helpers.
271 // CATCHRET - Represents a return from a catch block funclet. Used for
272 // MSVC compatible exception handling. Takes a chain operand and RAX.
275 // CLEANUPRET - Represents a return from a cleanup block funclet. Used
276 // for MSVC compatible exception handling. Takes only a chain operand.
279 // SjLj exception handling setjmp.
282 // SjLj exception handling longjmp.
285 /// Tail call return. See X86TargetLowering::LowerCall for
286 /// the list of operands.
289 // Vector move to low scalar and zero higher vector elements.
292 // Vector integer zero-extend.
295 // Vector integer signed-extend.
298 // Vector integer truncate.
300 // Vector integer truncate with unsigned/signed saturation.
309 // Vector signed/unsigned integer to double.
312 // 128-bit vector logical left / right shift
315 // Vector shift elements
318 // Vector shift elements by immediate
321 // Vector packed double/float comparison.
324 // Vector integer comparisons.
326 // Vector integer comparisons, the result is in a mask vector.
329 /// Vector comparison generating mask bits for fp and
330 /// integer signed and unsigned data types.
333 // Vector comparison with rounding mode for FP values
336 // Arithmetic operations with FLAGS results.
337 ADD, SUB, ADC, SBB, SMUL,
338 INC, DEC, OR, XOR, AND,
340 BEXTR, // Bit field extract
342 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
344 // 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS
347 // 8-bit divrem that zero-extend the high result (AH).
351 // X86-specific multiply by immediate.
354 // Vector bitwise comparisons.
357 // Vector packed fp sign bitwise comparisons.
360 // Vector "test" in AVX-512, the result is in a mask vector.
364 // OR/AND test for masks
368 // Several flavors of instructions with vector shuffle behaviors.
373 // AVX512 inter-lane alignr
379 //Shuffle Packed Values at 128-bit granularity
400 //Fix Up Special Packed Float32/64 values
402 //Range Restriction Calculation For Packed Pairs of Float32/64 values
404 // Reduce - Perform Reduction Transformation on scalar\packed FP
406 // RndScale - Round FP Values To Include A Given Number Of Fraction Bits
408 // Broadcast scalar to vector
410 // Broadcast subvector to vector
412 // Insert/Extract vector element
416 /// SSE4A Extraction and Insertion.
419 // Vector multiply packed unsigned doubleword integers
421 // Vector multiply packed signed doubleword integers
423 // Vector Multiply Packed UnsignedIntegers with Round and Scale
425 // Multiply and Add Packed Integers
426 VPMADDUBSW, VPMADDWD,
434 // FMA with rounding mode
442 // Compress and expand
446 //Convert Unsigned/Integer to Scalar Floating-Point Value
451 // Vector float/double to signed/unsigned integer.
452 FP_TO_SINT_RND, FP_TO_UINT_RND,
453 // Save xmm argument registers to the stack, according to %al. An operator
454 // is needed so that this can be expanded with control flow.
455 VASTART_SAVE_XMM_REGS,
457 // Windows's _chkstk call to do stack probing.
460 // For allocating variable amounts of stack space when using
461 // segmented stacks. Check if the current stacklet has enough space, and
462 // falls back to heap allocation if not.
471 // Store FP status word into i16 register.
474 // Store contents of %ah into %eflags.
477 // Get a random integer and indicate whether it is valid in CF.
480 // Get a NIST SP800-90B & C compliant random integer and
481 // indicate whether it is valid in CF.
487 // Test if in transactional execution.
491 RSQRT28, RCP28, EXP2,
494 LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
498 // Load, scalar_to_vector, and zero extend.
501 // Store FP control world into i16 memory.
504 /// This instruction implements FP_TO_SINT with the
505 /// integer destination in memory and a FP reg source. This corresponds
506 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
507 /// has two inputs (token chain and address) and two outputs (int value
508 /// and token chain).
513 /// This instruction implements SINT_TO_FP with the
514 /// integer source in memory and FP reg result. This corresponds to the
515 /// X86::FILD*m instructions. It has three inputs (token chain, address,
516 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
517 /// also produces a flag).
521 /// This instruction implements an extending load to FP stack slots.
522 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
523 /// operand, ptr to load from, and a ValueType node indicating the type
527 /// This instruction implements a truncating store to FP stack
528 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
529 /// chain operand, value to store, address, and a ValueType to store it
533 /// This instruction grabs the address of the next argument
534 /// from a va_list. (reads and modifies the va_list in memory)
537 // WARNING: Do not add anything in the end unless you want the node to
538 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
539 // thought as target memory ops!
543 /// Define some predicates that are used for node matching.
545 /// Return true if the specified
546 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
547 /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
548 bool isVEXTRACT128Index(SDNode *N);
550 /// Return true if the specified
551 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
552 /// suitable for input to VINSERTF128, VINSERTI128 instructions.
553 bool isVINSERT128Index(SDNode *N);
555 /// Return true if the specified
556 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
557 /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
558 bool isVEXTRACT256Index(SDNode *N);
560 /// Return true if the specified
561 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
562 /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
563 bool isVINSERT256Index(SDNode *N);
565 /// Return the appropriate
566 /// immediate to extract the specified EXTRACT_SUBVECTOR index
567 /// with VEXTRACTF128, VEXTRACTI128 instructions.
568 unsigned getExtractVEXTRACT128Immediate(SDNode *N);
570 /// Return the appropriate
571 /// immediate to insert at the specified INSERT_SUBVECTOR index
572 /// with VINSERTF128, VINSERT128 instructions.
573 unsigned getInsertVINSERT128Immediate(SDNode *N);
575 /// Return the appropriate
576 /// immediate to extract the specified EXTRACT_SUBVECTOR index
577 /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
578 unsigned getExtractVEXTRACT256Immediate(SDNode *N);
580 /// Return the appropriate
581 /// immediate to insert at the specified INSERT_SUBVECTOR index
582 /// with VINSERTF64x4, VINSERTI64x4 instructions.
583 unsigned getInsertVINSERT256Immediate(SDNode *N);
585 /// Returns true if Elt is a constant zero or floating point constant +0.0.
586 bool isZeroNode(SDValue Elt);
588 /// Returns true of the given offset can be
589 /// fit into displacement field of the instruction.
590 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
591 bool hasSymbolicDisplacement = true);
594 /// Determines whether the callee is required to pop its
595 /// own arguments. Callee pop is necessary to support tail calls.
596 bool isCalleePop(CallingConv::ID CallingConv,
597 bool is64Bit, bool IsVarArg, bool TailCallOpt);
599 /// AVX512 static rounding constants. These need to match the values in
601 enum STATIC_ROUNDING {
610 //===--------------------------------------------------------------------===//
611 // X86 Implementation of the TargetLowering interface
612 class X86TargetLowering final : public TargetLowering {
614 explicit X86TargetLowering(const X86TargetMachine &TM,
615 const X86Subtarget &STI);
617 unsigned getJumpTableEncoding() const override;
618 bool useSoftFloat() const override;
620 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
625 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
626 const MachineBasicBlock *MBB, unsigned uid,
627 MCContext &Ctx) const override;
629 /// Returns relocation base for the given PIC jumptable.
630 SDValue getPICJumpTableRelocBase(SDValue Table,
631 SelectionDAG &DAG) const override;
633 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
634 unsigned JTI, MCContext &Ctx) const override;
636 /// Return the desired alignment for ByVal aggregate
637 /// function arguments in the caller parameter area. For X86, aggregates
638 /// that contains are placed at 16-byte boundaries while the rest are at
639 /// 4-byte boundaries.
640 unsigned getByValTypeAlignment(Type *Ty,
641 const DataLayout &DL) const override;
643 /// Returns the target specific optimal type for load
644 /// and store operations as a result of memset, memcpy, and memmove
645 /// lowering. If DstAlign is zero that means it's safe to destination
646 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
647 /// means there isn't a need to check it against alignment requirement,
648 /// probably because the source does not need to be loaded. If 'IsMemset' is
649 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
650 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
651 /// source is constant so it does not need to be loaded.
652 /// It returns EVT::Other if the type should be determined using generic
653 /// target-independent logic.
654 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
655 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
656 MachineFunction &MF) const override;
658 /// Returns true if it's safe to use load / store of the
659 /// specified type to expand memcpy / memset inline. This is mostly true
660 /// for all types except for some special cases. For example, on X86
661 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
662 /// also does type conversion. Note the specified type doesn't have to be
663 /// legal as the hook is used before type legalization.
664 bool isSafeMemOpType(MVT VT) const override;
666 /// Returns true if the target allows unaligned memory accesses of the
667 /// specified type. Returns whether it is "fast" in the last argument.
668 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
669 bool *Fast) const override;
671 /// Provide custom lowering hooks for some operations.
673 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
675 /// Replace the results of node with an illegal result
676 /// type with new values built out of custom code.
678 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
679 SelectionDAG &DAG) const override;
682 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
684 /// Return true if the target has native support for
685 /// the specified value type and it is 'desirable' to use the type for the
686 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
687 /// instruction encodings are longer and some i16 instructions are slow.
688 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
690 /// Return true if the target has native support for the
691 /// specified value type and it is 'desirable' to use the type. e.g. On x86
692 /// i16 is legal, but undesirable since i16 instruction encodings are longer
693 /// and some i16 instructions are slow.
694 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
697 EmitInstrWithCustomInserter(MachineInstr *MI,
698 MachineBasicBlock *MBB) const override;
701 /// This method returns the name of a target specific DAG node.
702 const char *getTargetNodeName(unsigned Opcode) const override;
704 bool isCheapToSpeculateCttz() const override;
706 bool isCheapToSpeculateCtlz() const override;
708 /// Return the value type to use for ISD::SETCC.
709 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
710 EVT VT) const override;
712 /// Determine which of the bits specified in Mask are known to be either
713 /// zero or one and return them in the KnownZero/KnownOne bitsets.
714 void computeKnownBitsForTargetNode(const SDValue Op,
717 const SelectionDAG &DAG,
718 unsigned Depth = 0) const override;
720 /// Determine the number of bits in the operation that are sign bits.
721 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
722 const SelectionDAG &DAG,
723 unsigned Depth) const override;
725 bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
726 int64_t &Offset) const override;
728 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
730 bool ExpandInlineAsm(CallInst *CI) const override;
732 ConstraintType getConstraintType(StringRef Constraint) const override;
734 /// Examine constraint string and operand type and determine a weight value.
735 /// The operand object must already have been set up with the operand type.
737 getSingleConstraintMatchWeight(AsmOperandInfo &info,
738 const char *constraint) const override;
740 const char *LowerXConstraint(EVT ConstraintVT) const override;
742 /// Lower the specified operand into the Ops vector. If it is invalid, don't
743 /// add anything to Ops. If hasMemory is true it means one of the asm
744 /// constraint of the inline asm instruction being processed is 'm'.
745 void LowerAsmOperandForConstraint(SDValue Op,
746 std::string &Constraint,
747 std::vector<SDValue> &Ops,
748 SelectionDAG &DAG) const override;
751 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
752 if (ConstraintCode == "i")
753 return InlineAsm::Constraint_i;
754 else if (ConstraintCode == "o")
755 return InlineAsm::Constraint_o;
756 else if (ConstraintCode == "v")
757 return InlineAsm::Constraint_v;
758 else if (ConstraintCode == "X")
759 return InlineAsm::Constraint_X;
760 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
763 /// Given a physical register constraint
764 /// (e.g. {edx}), return the register number and the register class for the
765 /// register. This should only be used for C_Register constraints. On
766 /// error, this returns a register number of 0.
767 std::pair<unsigned, const TargetRegisterClass *>
768 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
769 StringRef Constraint, MVT VT) const override;
771 /// Return true if the addressing mode represented
772 /// by AM is legal for this target, for a load/store of the specified type.
773 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
774 Type *Ty, unsigned AS) const override;
776 /// Return true if the specified immediate is legal
777 /// icmp immediate, that is the target has icmp instructions which can
778 /// compare a register against the immediate without having to materialize
779 /// the immediate into a register.
780 bool isLegalICmpImmediate(int64_t Imm) const override;
782 /// Return true if the specified immediate is legal
783 /// add immediate, that is the target has add instructions which can
784 /// add a register and the immediate without having to materialize
785 /// the immediate into a register.
786 bool isLegalAddImmediate(int64_t Imm) const override;
788 /// \brief Return the cost of the scaling factor used in the addressing
789 /// mode represented by AM for this target, for a load/store
790 /// of the specified type.
791 /// If the AM is supported, the return value must be >= 0.
792 /// If the AM is not supported, it returns a negative value.
793 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
794 unsigned AS) const override;
796 bool isVectorShiftByScalarCheap(Type *Ty) const override;
798 /// Return true if it's free to truncate a value of
799 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
800 /// register EAX to i16 by referencing its sub-register AX.
801 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
802 bool isTruncateFree(EVT VT1, EVT VT2) const override;
804 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
806 /// Return true if any actual instruction that defines a
807 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
808 /// register. This does not necessarily include registers defined in
809 /// unknown ways, such as incoming arguments, or copies from unknown
810 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
811 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
812 /// all instructions that define 32-bit values implicit zero-extend the
813 /// result out to 64 bits.
814 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
815 bool isZExtFree(EVT VT1, EVT VT2) const override;
816 bool isZExtFree(SDValue Val, EVT VT2) const override;
818 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
819 /// extend node) is profitable.
820 bool isVectorLoadExtDesirable(SDValue) const override;
822 /// Return true if an FMA operation is faster than a pair of fmul and fadd
823 /// instructions. fmuladd intrinsics will be expanded to FMAs when this
824 /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
825 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
827 /// Return true if it's profitable to narrow
828 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
829 /// from i32 to i8 but not from i32 to i16.
830 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
832 /// Returns true if the target can instruction select the
833 /// specified FP immediate natively. If false, the legalizer will
834 /// materialize the FP immediate as a load from a constant pool.
835 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
837 /// Targets can use this to indicate that they only support *some*
838 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
839 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
841 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
842 EVT VT) const override;
844 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
845 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to
846 /// replace a VAND with a constant pool entry.
847 bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
848 EVT VT) const override;
850 /// If true, then instruction selection should
851 /// seek to shrink the FP constant of the specified type to a smaller type
852 /// in order to save space and / or reduce runtime.
853 bool ShouldShrinkFPConstant(EVT VT) const override {
854 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
855 // expensive than a straight movsd. On the other hand, it's important to
856 // shrink long double fp constant since fldt is very slow.
857 return !X86ScalarSSEf64 || VT == MVT::f80;
860 /// Return true if we believe it is correct and profitable to reduce the
861 /// load node to a smaller type.
862 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
863 EVT NewVT) const override;
865 /// Return true if the specified scalar FP type is computed in an SSE
866 /// register, not on the X87 floating point stack.
867 bool isScalarFPTypeInSSEReg(EVT VT) const {
868 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
869 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
872 /// \brief Returns true if it is beneficial to convert a load of a constant
873 /// to just the constant itself.
874 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
875 Type *Ty) const override;
877 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
879 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
881 /// Intel processors have a unified instruction and data cache
882 const char * getClearCacheBuiltinName() const override {
883 return nullptr; // nothing to do, move along.
886 unsigned getRegisterByName(const char* RegName, EVT VT,
887 SelectionDAG &DAG) const override;
889 /// This method returns a target specific FastISel object,
890 /// or null if the target does not support "fast" ISel.
891 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
892 const TargetLibraryInfo *libInfo) const override;
894 /// Return true if the target stores stack protector cookies at a fixed
895 /// offset in some non-standard address space, and populates the address
896 /// space and offset as appropriate.
897 bool getStackCookieLocation(unsigned &AddressSpace,
898 unsigned &Offset) const override;
900 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
901 SelectionDAG &DAG) const;
903 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
905 bool useLoadStackGuardNode() const override;
906 /// \brief Customize the preferred legalization strategy for certain types.
907 LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
909 bool isIntDivCheap(EVT VT, AttributeSet Attr) const override;
912 std::pair<const TargetRegisterClass *, uint8_t>
913 findRepresentativeClass(const TargetRegisterInfo *TRI,
914 MVT VT) const override;
917 /// Keep a pointer to the X86Subtarget around so that we can
918 /// make the right decision when generating code for different targets.
919 const X86Subtarget *Subtarget;
920 const DataLayout *TD;
922 /// Select between SSE or x87 floating point ops.
923 /// When SSE is available, use it for f32 operations.
924 /// When SSE2 is available, use it for f64 operations.
925 bool X86ScalarSSEf32;
926 bool X86ScalarSSEf64;
928 /// A list of legal FP immediates.
929 std::vector<APFloat> LegalFPImmediates;
931 /// Indicate that this x86 target can instruction
932 /// select the specified FP immediate natively.
933 void addLegalFPImmediate(const APFloat& Imm) {
934 LegalFPImmediates.push_back(Imm);
937 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
938 CallingConv::ID CallConv, bool isVarArg,
939 const SmallVectorImpl<ISD::InputArg> &Ins,
940 SDLoc dl, SelectionDAG &DAG,
941 SmallVectorImpl<SDValue> &InVals) const;
942 SDValue LowerMemArgument(SDValue Chain,
943 CallingConv::ID CallConv,
944 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
945 SDLoc dl, SelectionDAG &DAG,
946 const CCValAssign &VA, MachineFrameInfo *MFI,
948 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
949 SDLoc dl, SelectionDAG &DAG,
950 const CCValAssign &VA,
951 ISD::ArgFlagsTy Flags) const;
953 // Call lowering helpers.
955 /// Check whether the call is eligible for tail call optimization. Targets
956 /// that want to do tail call optimization should implement this function.
957 bool IsEligibleForTailCallOptimization(SDValue Callee,
958 CallingConv::ID CalleeCC,
960 bool isCalleeStructRet,
961 bool isCallerStructRet,
963 const SmallVectorImpl<ISD::OutputArg> &Outs,
964 const SmallVectorImpl<SDValue> &OutVals,
965 const SmallVectorImpl<ISD::InputArg> &Ins,
966 SelectionDAG& DAG) const;
967 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
968 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
969 SDValue Chain, bool IsTailCall, bool Is64Bit,
970 int FPDiff, SDLoc dl) const;
972 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
973 SelectionDAG &DAG) const;
975 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
977 bool isReplace) const;
979 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
980 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
981 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
982 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
983 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
984 SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const;
985 SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const;
987 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
988 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
989 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
990 SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
991 int64_t Offset, SelectionDAG &DAG) const;
992 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
993 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
994 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
995 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
996 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
997 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
998 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
999 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
1000 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1001 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
1002 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
1003 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
1004 SDLoc dl, SelectionDAG &DAG) const;
1005 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1006 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
1007 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
1008 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
1009 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1010 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1011 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1012 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1013 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1014 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1015 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1016 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
1017 SDValue LowerCATCHRET(SDValue Op, SelectionDAG &DAG) const;
1018 SDValue LowerCLEANUPRET(SDValue Op, SelectionDAG &DAG) const;
1019 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1020 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1021 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1022 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1023 SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
1024 SDValue LowerGC_TRANSITION_START(SDValue Op, SelectionDAG &DAG) const;
1025 SDValue LowerGC_TRANSITION_END(SDValue Op, SelectionDAG &DAG) const;
1028 LowerFormalArguments(SDValue Chain,
1029 CallingConv::ID CallConv, bool isVarArg,
1030 const SmallVectorImpl<ISD::InputArg> &Ins,
1031 SDLoc dl, SelectionDAG &DAG,
1032 SmallVectorImpl<SDValue> &InVals) const override;
1033 SDValue LowerCall(CallLoweringInfo &CLI,
1034 SmallVectorImpl<SDValue> &InVals) const override;
1036 SDValue LowerReturn(SDValue Chain,
1037 CallingConv::ID CallConv, bool isVarArg,
1038 const SmallVectorImpl<ISD::OutputArg> &Outs,
1039 const SmallVectorImpl<SDValue> &OutVals,
1040 SDLoc dl, SelectionDAG &DAG) const override;
1042 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1044 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
1046 EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1047 ISD::NodeType ExtendKind) const override;
1049 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1051 const SmallVectorImpl<ISD::OutputArg> &Outs,
1052 LLVMContext &Context) const override;
1054 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1056 TargetLoweringBase::AtomicExpansionKind
1057 shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
1058 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
1059 TargetLoweringBase::AtomicExpansionKind
1060 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
1063 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
1065 bool needsCmpXchgNb(Type *MemType) const;
1067 /// Utility function to emit atomic-load-arith operations (and, or, xor,
1068 /// nand, max, min, umax, umin). It takes the corresponding instruction to
1069 /// expand, the associated machine basic block, and the associated X86
1070 /// opcodes for reg/reg.
1071 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
1072 MachineBasicBlock *MBB) const;
1074 /// Utility function to emit atomic-load-arith operations (and, or, xor,
1075 /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
1076 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
1077 MachineBasicBlock *MBB) const;
1079 // Utility function to emit the low-level va_arg code for X86-64.
1080 MachineBasicBlock *EmitVAARG64WithCustomInserter(
1082 MachineBasicBlock *MBB) const;
1084 /// Utility function to emit the xmm reg save portion of va_start.
1085 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
1086 MachineInstr *BInstr,
1087 MachineBasicBlock *BB) const;
1089 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
1090 MachineBasicBlock *BB) const;
1092 MachineBasicBlock *EmitLoweredAtomicFP(MachineInstr *I,
1093 MachineBasicBlock *BB) const;
1095 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
1096 MachineBasicBlock *BB) const;
1098 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
1099 MachineBasicBlock *BB) const;
1101 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
1102 MachineBasicBlock *BB) const;
1104 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
1105 MachineBasicBlock *BB) const;
1107 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
1108 MachineBasicBlock *MBB) const;
1110 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
1111 MachineBasicBlock *MBB) const;
1113 MachineBasicBlock *emitFMA3Instr(MachineInstr *MI,
1114 MachineBasicBlock *MBB) const;
1116 /// Emit nodes that will be selected as "test Op0,Op0", or something
1117 /// equivalent, for use with the given x86 condition code.
1118 SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl,
1119 SelectionDAG &DAG) const;
1121 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
1122 /// equivalent, for use with the given x86 condition code.
1123 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl,
1124 SelectionDAG &DAG) const;
1126 /// Convert a comparison if required by the subtarget.
1127 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
1129 /// Use rsqrt* to speed up sqrt calculations.
1130 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1131 unsigned &RefinementSteps,
1132 bool &UseOneConstNR) const override;
1134 /// Use rcp* to speed up fdiv calculations.
1135 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1136 unsigned &RefinementSteps) const override;
1138 /// Reassociate floating point divisions into multiply by reciprocal.
1139 unsigned combineRepeatedFPDivisors() const override;
1143 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1144 const TargetLibraryInfo *libInfo);
1148 #endif // X86ISELLOWERING_H