1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetOptions.h"
25 class X86TargetMachine;
28 // X86 Specific DAG Nodes
29 enum NodeType : unsigned {
30 // Start the numbering where the builtin ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
38 /// Double shift instructions. These correspond to
39 /// X86::SHLDxx and X86::SHRDxx instructions.
43 /// Bitwise logical AND of floating point values. This corresponds
44 /// to X86::ANDPS or X86::ANDPD.
47 /// Bitwise logical OR of floating point values. This corresponds
48 /// to X86::ORPS or X86::ORPD.
51 /// Bitwise logical XOR of floating point values. This corresponds
52 /// to X86::XORPS or X86::XORPD.
55 /// Bitwise logical ANDNOT of floating point values. This
56 /// corresponds to X86::ANDNPS or X86::ANDNPD.
59 /// These operations represent an abstract X86 call
60 /// instruction, which includes a bunch of information. In particular the
61 /// operands of these node are:
63 /// #0 - The incoming token chain
65 /// #2 - The number of arg bytes the caller pushes on the stack.
66 /// #3 - The number of arg bytes the callee pops off the stack.
67 /// #4 - The value to pass in AL/AX/EAX (optional)
68 /// #5 - The value to pass in DL/DX/EDX (optional)
70 /// The result values of these nodes are:
72 /// #0 - The outgoing token chain
73 /// #1 - The first register result value (optional)
74 /// #2 - The second register result value (optional)
78 /// This operation implements the lowering for readcyclecounter
81 /// X86 Read Time-Stamp Counter and Processor ID.
84 /// X86 Read Performance Monitoring Counters.
87 /// X86 compare and logical compare instructions.
90 /// X86 bit-test instructions.
93 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
94 /// operand, usually produced by a CMP instruction.
100 // Same as SETCC except it's materialized with a sbb and the value is all
101 // one's or all zero's.
102 SETCC_CARRY, // R = carry_bit ? ~0 : 0
104 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
105 /// Operands are two FP values to compare; result is a mask of
106 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
109 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
110 /// result in an integer GPR. Needs masking for scalar result.
113 /// X86 conditional moves. Operand 0 and operand 1 are the two values
114 /// to select from. Operand 2 is the condition code, and operand 3 is the
115 /// flag operand produced by a CMP or TEST instruction. It also writes a
119 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
120 /// is the block to branch if condition is true, operand 2 is the
121 /// condition code, and operand 3 is the flag operand produced by a CMP
122 /// or TEST instruction.
125 /// Return with a flag operand. Operand 0 is the chain operand, operand
126 /// 1 is the number of bytes of stack to pop.
129 /// Return from interrupt. Operand 0 is the number of bytes to pop.
132 /// Repeat fill, corresponds to X86::REP_STOSx.
135 /// Repeat move, corresponds to X86::REP_MOVSx.
138 /// On Darwin, this node represents the result of the popl
139 /// at function entry, used for PIC code.
142 /// A wrapper node for TargetConstantPool,
143 /// TargetExternalSymbol, and TargetGlobalAddress.
146 /// Special wrapper used under X86-64 PIC mode for RIP
147 /// relative displacements.
150 /// Copies a 64-bit value from the low word of an XMM vector
151 /// to an MMX vector. If you think this is too close to the previous
152 /// mnemonic, so do I; blame Intel.
155 /// Copies a 32-bit value from the low word of a MMX
159 /// Copies a GPR into the low 32-bit word of a MMX vector
160 /// and zero out the high word.
163 /// Extract an 8-bit value from a vector and zero extend it to
164 /// i32, corresponds to X86::PEXTRB.
167 /// Extract a 16-bit value from a vector and zero extend it to
168 /// i32, corresponds to X86::PEXTRW.
171 /// Insert any element of a 4 x float vector into any element
172 /// of a destination 4 x floatvector.
175 /// Insert the lower 8-bits of a 32-bit value to a vector,
176 /// corresponds to X86::PINSRB.
179 /// Insert the lower 16-bits of a 32-bit value to a vector,
180 /// corresponds to X86::PINSRW.
183 /// Shuffle 16 8-bit values within a vector.
186 /// Compute Sum of Absolute Differences.
188 /// Compute Double Block Packed Sum-Absolute-Differences
191 /// Bitwise Logical AND NOT of Packed FP values.
194 /// Copy integer sign.
197 /// Blend where the selector is an immediate.
200 /// Blend where the condition has been shrunk.
201 /// This is used to emphasize that the condition mask is
202 /// no more valid for generic VSELECT optimizations.
205 /// Combined add and sub on an FP vector.
208 // FP vector ops with rounding mode.
217 // FP vector get exponent
219 // Extract Normalized Mantissas
223 // Integer add/sub with unsigned saturation.
226 // Integer add/sub with signed saturation.
229 // Unsigned Integer average
231 /// Integer horizontal add.
234 /// Integer horizontal sub.
237 /// Floating point horizontal add.
240 /// Floating point horizontal sub.
243 // Integer absolute value
246 // Detect Conflicts Within a Vector
249 /// Floating point max and min.
252 /// Commutative FMIN and FMAX.
255 /// Floating point reciprocal-sqrt and reciprocal approximation.
256 /// Note that these typically require refinement
257 /// in order to obtain suitable precision.
260 // Thread Local Storage.
263 // Thread Local Storage. A call to get the start address
264 // of the TLS block for the current module.
267 // Thread Local Storage. When calling to an OS provided
268 // thunk at the address from an earlier relocation.
271 // Exception Handling helpers.
274 // SjLj exception handling setjmp.
277 // SjLj exception handling longjmp.
280 /// Tail call return. See X86TargetLowering::LowerCall for
281 /// the list of operands.
284 // Vector move to low scalar and zero higher vector elements.
287 // Vector integer zero-extend.
290 // Vector integer signed-extend.
293 // Vector integer truncate.
295 // Vector integer truncate with unsigned/signed saturation.
304 // Vector signed/unsigned integer to double.
307 // Convert a vector to mask, set bits base on MSB.
310 // 128-bit vector logical left / right shift
313 // Vector shift elements
316 // Vector shift elements by immediate
319 // Vector packed double/float comparison.
322 // Vector integer comparisons.
324 // Vector integer comparisons, the result is in a mask vector.
327 /// Vector comparison generating mask bits for fp and
328 /// integer signed and unsigned data types.
331 // Vector comparison with rounding mode for FP values
334 // Arithmetic operations with FLAGS results.
335 ADD, SUB, ADC, SBB, SMUL,
336 INC, DEC, OR, XOR, AND,
338 BEXTR, // Bit field extract
340 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
342 // 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS
345 // 8-bit divrem that zero-extend the high result (AH).
349 // X86-specific multiply by immediate.
352 // Vector bitwise comparisons.
355 // Vector packed fp sign bitwise comparisons.
358 // Vector "test" in AVX-512, the result is in a mask vector.
362 // OR/AND test for masks
366 // Several flavors of instructions with vector shuffle behaviors.
371 // AVX512 inter-lane alignr
377 //Shuffle Packed Values at 128-bit granularity
398 // Bitwise ternary logic
400 // Fix Up Special Packed Float32/64 values
402 // Range Restriction Calculation For Packed Pairs of Float32/64 values
404 // Reduce - Perform Reduction Transformation on scalar\packed FP
406 // RndScale - Round FP Values To Include A Given Number Of Fraction Bits
408 // VFPCLASS - Tests Types Of a FP Values for packed types.
410 // VFPCLASSS - Tests Types Of a FP Values for scalar types.
412 // Broadcast scalar to vector
414 // Broadcast mask to vector
416 // Broadcast subvector to vector
418 // Insert/Extract vector element
422 /// SSE4A Extraction and Insertion.
425 // XOP variable/immediate rotations
427 // XOP arithmetic/logical shifts
429 // XOP signed/unsigned integer comparisons
432 // Vector multiply packed unsigned doubleword integers
434 // Vector multiply packed signed doubleword integers
436 // Vector Multiply Packed UnsignedIntegers with Round and Scale
438 // Multiply and Add Packed Integers
439 VPMADDUBSW, VPMADDWD,
447 // FMA with rounding mode
455 // Compress and expand
459 //Convert Unsigned/Integer to Scalar Floating-Point Value
464 // Vector float/double to signed/unsigned integer.
465 FP_TO_SINT_RND, FP_TO_UINT_RND,
466 // Save xmm argument registers to the stack, according to %al. An operator
467 // is needed so that this can be expanded with control flow.
468 VASTART_SAVE_XMM_REGS,
470 // Windows's _chkstk call to do stack probing.
473 // For allocating variable amounts of stack space when using
474 // segmented stacks. Check if the current stacklet has enough space, and
475 // falls back to heap allocation if not.
484 // Store FP status word into i16 register.
487 // Store contents of %ah into %eflags.
490 // Get a random integer and indicate whether it is valid in CF.
493 // Get a NIST SP800-90B & C compliant random integer and
494 // indicate whether it is valid in CF.
500 // Test if in transactional execution.
504 RSQRT28, RCP28, EXP2,
507 LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
511 // Load, scalar_to_vector, and zero extend.
514 // Store FP control world into i16 memory.
517 /// This instruction implements FP_TO_SINT with the
518 /// integer destination in memory and a FP reg source. This corresponds
519 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
520 /// has two inputs (token chain and address) and two outputs (int value
521 /// and token chain).
526 /// This instruction implements SINT_TO_FP with the
527 /// integer source in memory and FP reg result. This corresponds to the
528 /// X86::FILD*m instructions. It has three inputs (token chain, address,
529 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
530 /// also produces a flag).
534 /// This instruction implements an extending load to FP stack slots.
535 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
536 /// operand, ptr to load from, and a ValueType node indicating the type
540 /// This instruction implements a truncating store to FP stack
541 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
542 /// chain operand, value to store, address, and a ValueType to store it
546 /// This instruction grabs the address of the next argument
547 /// from a va_list. (reads and modifies the va_list in memory)
550 // WARNING: Do not add anything in the end unless you want the node to
551 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
552 // thought as target memory ops!
556 /// Define some predicates that are used for node matching.
558 /// Return true if the specified
559 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
560 /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
561 bool isVEXTRACT128Index(SDNode *N);
563 /// Return true if the specified
564 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
565 /// suitable for input to VINSERTF128, VINSERTI128 instructions.
566 bool isVINSERT128Index(SDNode *N);
568 /// Return true if the specified
569 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
570 /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
571 bool isVEXTRACT256Index(SDNode *N);
573 /// Return true if the specified
574 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
575 /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
576 bool isVINSERT256Index(SDNode *N);
578 /// Return the appropriate
579 /// immediate to extract the specified EXTRACT_SUBVECTOR index
580 /// with VEXTRACTF128, VEXTRACTI128 instructions.
581 unsigned getExtractVEXTRACT128Immediate(SDNode *N);
583 /// Return the appropriate
584 /// immediate to insert at the specified INSERT_SUBVECTOR index
585 /// with VINSERTF128, VINSERT128 instructions.
586 unsigned getInsertVINSERT128Immediate(SDNode *N);
588 /// Return the appropriate
589 /// immediate to extract the specified EXTRACT_SUBVECTOR index
590 /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
591 unsigned getExtractVEXTRACT256Immediate(SDNode *N);
593 /// Return the appropriate
594 /// immediate to insert at the specified INSERT_SUBVECTOR index
595 /// with VINSERTF64x4, VINSERTI64x4 instructions.
596 unsigned getInsertVINSERT256Immediate(SDNode *N);
598 /// Returns true if Elt is a constant zero or floating point constant +0.0.
599 bool isZeroNode(SDValue Elt);
601 /// Returns true of the given offset can be
602 /// fit into displacement field of the instruction.
603 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
604 bool hasSymbolicDisplacement = true);
607 /// Determines whether the callee is required to pop its
608 /// own arguments. Callee pop is necessary to support tail calls.
609 bool isCalleePop(CallingConv::ID CallingConv,
610 bool is64Bit, bool IsVarArg, bool TailCallOpt);
614 //===--------------------------------------------------------------------===//
615 // X86 Implementation of the TargetLowering interface
616 class X86TargetLowering final : public TargetLowering {
618 explicit X86TargetLowering(const X86TargetMachine &TM,
619 const X86Subtarget &STI);
621 unsigned getJumpTableEncoding() const override;
622 bool useSoftFloat() const override;
624 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
629 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
630 const MachineBasicBlock *MBB, unsigned uid,
631 MCContext &Ctx) const override;
633 /// Returns relocation base for the given PIC jumptable.
634 SDValue getPICJumpTableRelocBase(SDValue Table,
635 SelectionDAG &DAG) const override;
637 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
638 unsigned JTI, MCContext &Ctx) const override;
640 /// Return the desired alignment for ByVal aggregate
641 /// function arguments in the caller parameter area. For X86, aggregates
642 /// that contains are placed at 16-byte boundaries while the rest are at
643 /// 4-byte boundaries.
644 unsigned getByValTypeAlignment(Type *Ty,
645 const DataLayout &DL) const override;
647 /// Returns the target specific optimal type for load
648 /// and store operations as a result of memset, memcpy, and memmove
649 /// lowering. If DstAlign is zero that means it's safe to destination
650 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
651 /// means there isn't a need to check it against alignment requirement,
652 /// probably because the source does not need to be loaded. If 'IsMemset' is
653 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
654 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
655 /// source is constant so it does not need to be loaded.
656 /// It returns EVT::Other if the type should be determined using generic
657 /// target-independent logic.
658 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
659 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
660 MachineFunction &MF) const override;
662 /// Returns true if it's safe to use load / store of the
663 /// specified type to expand memcpy / memset inline. This is mostly true
664 /// for all types except for some special cases. For example, on X86
665 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
666 /// also does type conversion. Note the specified type doesn't have to be
667 /// legal as the hook is used before type legalization.
668 bool isSafeMemOpType(MVT VT) const override;
670 /// Returns true if the target allows unaligned memory accesses of the
671 /// specified type. Returns whether it is "fast" in the last argument.
672 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
673 bool *Fast) const override;
675 /// Provide custom lowering hooks for some operations.
677 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
679 /// Replace the results of node with an illegal result
680 /// type with new values built out of custom code.
682 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
683 SelectionDAG &DAG) const override;
686 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
688 /// Return true if the target has native support for
689 /// the specified value type and it is 'desirable' to use the type for the
690 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
691 /// instruction encodings are longer and some i16 instructions are slow.
692 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
694 /// Return true if the target has native support for the
695 /// specified value type and it is 'desirable' to use the type. e.g. On x86
696 /// i16 is legal, but undesirable since i16 instruction encodings are longer
697 /// and some i16 instructions are slow.
698 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
701 EmitInstrWithCustomInserter(MachineInstr *MI,
702 MachineBasicBlock *MBB) const override;
705 /// This method returns the name of a target specific DAG node.
706 const char *getTargetNodeName(unsigned Opcode) const override;
708 bool isCheapToSpeculateCttz() const override;
710 bool isCheapToSpeculateCtlz() const override;
712 /// Return the value type to use for ISD::SETCC.
713 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
714 EVT VT) const override;
716 /// Determine which of the bits specified in Mask are known to be either
717 /// zero or one and return them in the KnownZero/KnownOne bitsets.
718 void computeKnownBitsForTargetNode(const SDValue Op,
721 const SelectionDAG &DAG,
722 unsigned Depth = 0) const override;
724 /// Determine the number of bits in the operation that are sign bits.
725 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
726 const SelectionDAG &DAG,
727 unsigned Depth) const override;
729 bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
730 int64_t &Offset) const override;
732 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
734 bool ExpandInlineAsm(CallInst *CI) const override;
736 ConstraintType getConstraintType(StringRef Constraint) const override;
738 /// Examine constraint string and operand type and determine a weight value.
739 /// The operand object must already have been set up with the operand type.
741 getSingleConstraintMatchWeight(AsmOperandInfo &info,
742 const char *constraint) const override;
744 const char *LowerXConstraint(EVT ConstraintVT) const override;
746 /// Lower the specified operand into the Ops vector. If it is invalid, don't
747 /// add anything to Ops. If hasMemory is true it means one of the asm
748 /// constraint of the inline asm instruction being processed is 'm'.
749 void LowerAsmOperandForConstraint(SDValue Op,
750 std::string &Constraint,
751 std::vector<SDValue> &Ops,
752 SelectionDAG &DAG) const override;
755 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
756 if (ConstraintCode == "i")
757 return InlineAsm::Constraint_i;
758 else if (ConstraintCode == "o")
759 return InlineAsm::Constraint_o;
760 else if (ConstraintCode == "v")
761 return InlineAsm::Constraint_v;
762 else if (ConstraintCode == "X")
763 return InlineAsm::Constraint_X;
764 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
767 /// Given a physical register constraint
768 /// (e.g. {edx}), return the register number and the register class for the
769 /// register. This should only be used for C_Register constraints. On
770 /// error, this returns a register number of 0.
771 std::pair<unsigned, const TargetRegisterClass *>
772 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
773 StringRef Constraint, MVT VT) const override;
775 /// Return true if the addressing mode represented
776 /// by AM is legal for this target, for a load/store of the specified type.
777 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
778 Type *Ty, unsigned AS) const override;
780 /// Return true if the specified immediate is legal
781 /// icmp immediate, that is the target has icmp instructions which can
782 /// compare a register against the immediate without having to materialize
783 /// the immediate into a register.
784 bool isLegalICmpImmediate(int64_t Imm) const override;
786 /// Return true if the specified immediate is legal
787 /// add immediate, that is the target has add instructions which can
788 /// add a register and the immediate without having to materialize
789 /// the immediate into a register.
790 bool isLegalAddImmediate(int64_t Imm) const override;
792 /// \brief Return the cost of the scaling factor used in the addressing
793 /// mode represented by AM for this target, for a load/store
794 /// of the specified type.
795 /// If the AM is supported, the return value must be >= 0.
796 /// If the AM is not supported, it returns a negative value.
797 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
798 unsigned AS) const override;
800 bool isVectorShiftByScalarCheap(Type *Ty) const override;
802 /// Return true if it's free to truncate a value of
803 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
804 /// register EAX to i16 by referencing its sub-register AX.
805 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
806 bool isTruncateFree(EVT VT1, EVT VT2) const override;
808 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
810 /// Return true if any actual instruction that defines a
811 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
812 /// register. This does not necessarily include registers defined in
813 /// unknown ways, such as incoming arguments, or copies from unknown
814 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
815 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
816 /// all instructions that define 32-bit values implicit zero-extend the
817 /// result out to 64 bits.
818 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
819 bool isZExtFree(EVT VT1, EVT VT2) const override;
820 bool isZExtFree(SDValue Val, EVT VT2) const override;
822 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
823 /// extend node) is profitable.
824 bool isVectorLoadExtDesirable(SDValue) const override;
826 /// Return true if an FMA operation is faster than a pair of fmul and fadd
827 /// instructions. fmuladd intrinsics will be expanded to FMAs when this
828 /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
829 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
831 /// Return true if it's profitable to narrow
832 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
833 /// from i32 to i8 but not from i32 to i16.
834 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
836 /// Returns true if the target can instruction select the
837 /// specified FP immediate natively. If false, the legalizer will
838 /// materialize the FP immediate as a load from a constant pool.
839 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
841 /// Targets can use this to indicate that they only support *some*
842 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
843 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
845 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
846 EVT VT) const override;
848 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
849 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to
850 /// replace a VAND with a constant pool entry.
851 bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
852 EVT VT) const override;
854 /// If true, then instruction selection should
855 /// seek to shrink the FP constant of the specified type to a smaller type
856 /// in order to save space and / or reduce runtime.
857 bool ShouldShrinkFPConstant(EVT VT) const override {
858 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
859 // expensive than a straight movsd. On the other hand, it's important to
860 // shrink long double fp constant since fldt is very slow.
861 return !X86ScalarSSEf64 || VT == MVT::f80;
864 /// Return true if we believe it is correct and profitable to reduce the
865 /// load node to a smaller type.
866 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
867 EVT NewVT) const override;
869 /// Return true if the specified scalar FP type is computed in an SSE
870 /// register, not on the X87 floating point stack.
871 bool isScalarFPTypeInSSEReg(EVT VT) const {
872 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
873 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
876 /// \brief Returns true if it is beneficial to convert a load of a constant
877 /// to just the constant itself.
878 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
879 Type *Ty) const override;
881 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
883 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
885 /// Intel processors have a unified instruction and data cache
886 const char * getClearCacheBuiltinName() const override {
887 return nullptr; // nothing to do, move along.
890 unsigned getRegisterByName(const char* RegName, EVT VT,
891 SelectionDAG &DAG) const override;
893 /// If a physical register, this returns the register that receives the
894 /// exception address on entry to an EH pad.
896 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
898 /// If a physical register, this returns the register that receives the
899 /// exception typeid on entry to a landing pad.
901 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
903 /// This method returns a target specific FastISel object,
904 /// or null if the target does not support "fast" ISel.
905 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
906 const TargetLibraryInfo *libInfo) const override;
908 /// Return true if the target stores stack protector cookies at a fixed
909 /// offset in some non-standard address space, and populates the address
910 /// space and offset as appropriate.
911 bool getStackCookieLocation(unsigned &AddressSpace,
912 unsigned &Offset) const override;
914 /// Return true if the target stores SafeStack pointer at a fixed offset in
915 /// some non-standard address space, and populates the address space and
916 /// offset as appropriate.
917 Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
919 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
920 SelectionDAG &DAG) const;
922 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
924 bool useLoadStackGuardNode() const override;
925 /// \brief Customize the preferred legalization strategy for certain types.
926 LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
928 bool isIntDivCheap(EVT VT, AttributeSet Attr) const override;
931 std::pair<const TargetRegisterClass *, uint8_t>
932 findRepresentativeClass(const TargetRegisterInfo *TRI,
933 MVT VT) const override;
936 /// Keep a pointer to the X86Subtarget around so that we can
937 /// make the right decision when generating code for different targets.
938 const X86Subtarget *Subtarget;
940 /// Select between SSE or x87 floating point ops.
941 /// When SSE is available, use it for f32 operations.
942 /// When SSE2 is available, use it for f64 operations.
943 bool X86ScalarSSEf32;
944 bool X86ScalarSSEf64;
946 /// A list of legal FP immediates.
947 std::vector<APFloat> LegalFPImmediates;
949 /// Indicate that this x86 target can instruction
950 /// select the specified FP immediate natively.
951 void addLegalFPImmediate(const APFloat& Imm) {
952 LegalFPImmediates.push_back(Imm);
955 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
956 CallingConv::ID CallConv, bool isVarArg,
957 const SmallVectorImpl<ISD::InputArg> &Ins,
958 SDLoc dl, SelectionDAG &DAG,
959 SmallVectorImpl<SDValue> &InVals) const;
960 SDValue LowerMemArgument(SDValue Chain,
961 CallingConv::ID CallConv,
962 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
963 SDLoc dl, SelectionDAG &DAG,
964 const CCValAssign &VA, MachineFrameInfo *MFI,
966 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
967 SDLoc dl, SelectionDAG &DAG,
968 const CCValAssign &VA,
969 ISD::ArgFlagsTy Flags) const;
971 // Call lowering helpers.
973 /// Check whether the call is eligible for tail call optimization. Targets
974 /// that want to do tail call optimization should implement this function.
975 bool IsEligibleForTailCallOptimization(SDValue Callee,
976 CallingConv::ID CalleeCC,
978 bool isCalleeStructRet,
979 bool isCallerStructRet,
981 const SmallVectorImpl<ISD::OutputArg> &Outs,
982 const SmallVectorImpl<SDValue> &OutVals,
983 const SmallVectorImpl<ISD::InputArg> &Ins,
984 SelectionDAG& DAG) const;
985 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
986 SDValue Chain, bool IsTailCall, bool Is64Bit,
987 int FPDiff, SDLoc dl) const;
989 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
990 SelectionDAG &DAG) const;
992 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
994 bool isReplace) const;
996 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
997 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
998 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
999 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1000 SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const;
1001 SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const;
1003 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1004 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1005 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1006 SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
1007 int64_t Offset, SelectionDAG &DAG) const;
1008 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1009 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1010 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
1011 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1012 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1013 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
1014 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
1015 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
1016 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1017 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
1018 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
1019 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
1020 SDLoc dl, SelectionDAG &DAG) const;
1021 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1022 SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) const;
1023 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
1024 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
1025 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1026 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1027 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1028 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1029 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1030 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1031 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1032 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
1033 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1034 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1035 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1036 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1037 SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
1038 SDValue LowerGC_TRANSITION_START(SDValue Op, SelectionDAG &DAG) const;
1039 SDValue LowerGC_TRANSITION_END(SDValue Op, SelectionDAG &DAG) const;
1042 LowerFormalArguments(SDValue Chain,
1043 CallingConv::ID CallConv, bool isVarArg,
1044 const SmallVectorImpl<ISD::InputArg> &Ins,
1045 SDLoc dl, SelectionDAG &DAG,
1046 SmallVectorImpl<SDValue> &InVals) const override;
1047 SDValue LowerCall(CallLoweringInfo &CLI,
1048 SmallVectorImpl<SDValue> &InVals) const override;
1050 SDValue LowerReturn(SDValue Chain,
1051 CallingConv::ID CallConv, bool isVarArg,
1052 const SmallVectorImpl<ISD::OutputArg> &Outs,
1053 const SmallVectorImpl<SDValue> &OutVals,
1054 SDLoc dl, SelectionDAG &DAG) const override;
1056 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1058 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
1060 EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1061 ISD::NodeType ExtendKind) const override;
1063 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1065 const SmallVectorImpl<ISD::OutputArg> &Outs,
1066 LLVMContext &Context) const override;
1068 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1070 TargetLoweringBase::AtomicExpansionKind
1071 shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
1072 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
1073 TargetLoweringBase::AtomicExpansionKind
1074 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
1077 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
1079 bool needsCmpXchgNb(Type *MemType) const;
1081 // Utility function to emit the low-level va_arg code for X86-64.
1082 MachineBasicBlock *EmitVAARG64WithCustomInserter(
1084 MachineBasicBlock *MBB) const;
1086 /// Utility function to emit the xmm reg save portion of va_start.
1087 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
1088 MachineInstr *BInstr,
1089 MachineBasicBlock *BB) const;
1091 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
1092 MachineBasicBlock *BB) const;
1094 MachineBasicBlock *EmitLoweredAtomicFP(MachineInstr *I,
1095 MachineBasicBlock *BB) const;
1097 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
1098 MachineBasicBlock *BB) const;
1100 MachineBasicBlock *EmitLoweredCatchRet(MachineInstr *MI,
1101 MachineBasicBlock *BB) const;
1103 MachineBasicBlock *EmitLoweredCatchPad(MachineInstr *MI,
1104 MachineBasicBlock *BB) const;
1106 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
1107 MachineBasicBlock *BB) const;
1109 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
1110 MachineBasicBlock *BB) const;
1112 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
1113 MachineBasicBlock *MBB) const;
1115 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
1116 MachineBasicBlock *MBB) const;
1118 MachineBasicBlock *emitFMA3Instr(MachineInstr *MI,
1119 MachineBasicBlock *MBB) const;
1121 /// Emit nodes that will be selected as "test Op0,Op0", or something
1122 /// equivalent, for use with the given x86 condition code.
1123 SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl,
1124 SelectionDAG &DAG) const;
1126 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
1127 /// equivalent, for use with the given x86 condition code.
1128 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl,
1129 SelectionDAG &DAG) const;
1131 /// Convert a comparison if required by the subtarget.
1132 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
1134 /// Use rsqrt* to speed up sqrt calculations.
1135 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1136 unsigned &RefinementSteps,
1137 bool &UseOneConstNR) const override;
1139 /// Use rcp* to speed up fdiv calculations.
1140 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1141 unsigned &RefinementSteps) const override;
1143 /// Reassociate floating point divisions into multiply by reciprocal.
1144 unsigned combineRepeatedFPDivisors() const override;
1148 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1149 const TargetLibraryInfo *libInfo);
1153 #endif // X86ISELLOWERING_H