1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
24 // X86 Specific DAG Nodes
26 // Start the numbering where the builtin ops leave off.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
29 /// SHLD, SHRD - Double shift instructions. These correspond to
30 /// X86::SHLDxx and X86::SHRDxx instructions.
34 /// FAND - Bitwise logical AND of floating point values. This corresponds
35 /// to X86::ANDPS or X86::ANDPD.
38 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
39 /// to X86::XORPS or X86::XORPD.
42 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
43 /// integer source in memory and FP reg result. This corresponds to the
44 /// X86::FILD*m instructions. It has three inputs (token chain, address,
45 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
46 /// also produces a flag).
50 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
51 /// integer destination in memory and a FP reg source. This corresponds
52 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
53 /// has two inputs (token chain and address) and two outputs (int value and
59 /// FLD - This instruction implements an extending load to FP stack slots.
60 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
61 /// operand, ptr to load from, and a ValueType node indicating the type
65 /// FST - This instruction implements a truncating store to FP stack
66 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
67 /// chain operand, value to store, address, and a ValueType to store it
71 /// FP_SET_RESULT - This corresponds to FpGETRESULT pseudo instrcuction
72 /// which copies from ST(0) to the destination. It takes a chain and writes
73 /// a RFP result and a chain.
76 /// FP_SET_RESULT - This corresponds to FpSETRESULT pseudo instrcuction
77 /// which copies the source operand to ST(0). It takes a chain and writes
78 /// a chain and a flag.
81 /// CALL/TAILCALL - These operations represent an abstract X86 call
82 /// instruction, which includes a bunch of information. In particular the
83 /// operands of these node are:
85 /// #0 - The incoming token chain
87 /// #2 - The number of arg bytes the caller pushes on the stack.
88 /// #3 - The number of arg bytes the callee pops off the stack.
89 /// #4 - The value to pass in AL/AX/EAX (optional)
90 /// #5 - The value to pass in DL/DX/EDX (optional)
92 /// The result values of these nodes are:
94 /// #0 - The outgoing token chain
95 /// #1 - The first register result value (optional)
96 /// #2 - The second register result value (optional)
98 /// The CALL vs TAILCALL distinction boils down to whether the callee is
99 /// known not to modify the caller's stack frame, as is standard with
104 /// RDTSC_DAG - This operation implements the lowering for
108 /// X86 compare and logical compare instructions.
111 /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
112 /// operand produced by a CMP instruction.
115 /// X86 conditional moves. Operand 1 and operand 2 are the two values
116 /// to select from (operand 1 is a R/W operand). Operand 3 is the condition
117 /// code, and operand 4 is the flag operand produced by a CMP or TEST
118 /// instruction. It also writes a flag result.
121 /// X86 conditional branches. Operand 1 is the chain operand, operand 2
122 /// is the block to branch if condition is true, operand 3 is the
123 /// condition code, and operand 4 is the flag operand produced by a CMP
124 /// or TEST instruction.
127 /// Return with a flag operand. Operand 1 is the chain operand, operand
128 /// 2 is the number of bytes of stack to pop.
131 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
134 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
137 /// LOAD_PACK Load a 128-bit packed float / double value. It has the same
138 /// operands as a normal load.
141 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
142 /// at function entry, used for PIC code.
145 /// TCPWrapper - A wrapper node for TargetConstantPool,
146 /// TargetExternalSymbol, and TargetGlobalAddress.
149 /// S2VEC - X86 version of SCALAR_TO_VECTOR. The destination base does not
150 /// have to match the operand type.
153 /// ZEXT_S2VEC - SCALAR_TO_VECTOR with zero extension. The destination base
154 /// does not have to match the operand type.
157 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
158 /// i32, corresponds to X86::PEXTRW.
161 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
162 /// corresponds to X86::PINSRW.
166 // X86 specific condition code. These correspond to X86_*_COND in
167 // X86InstrInfo.td. They must be kept in synch.
189 /// Define some predicates that are used for node matching.
191 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
192 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
193 bool isPSHUFDMask(SDNode *N);
195 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
196 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
197 bool isPSHUFHWMask(SDNode *N);
199 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
200 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
201 bool isPSHUFLWMask(SDNode *N);
203 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
204 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
205 bool isSHUFPMask(SDNode *N);
207 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
208 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
209 bool isMOVLHPSMask(SDNode *N);
211 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
212 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
213 bool isMOVHLPSMask(SDNode *N);
215 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
216 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
217 bool isUNPCKLMask(SDNode *N);
219 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
220 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
221 bool isUNPCKHMask(SDNode *N);
223 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
224 /// specifies a splat of a single element.
225 bool isSplatMask(SDNode *N);
227 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
228 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
230 unsigned getShuffleSHUFImmediate(SDNode *N);
232 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
233 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
235 unsigned getShufflePSHUFHWImmediate(SDNode *N);
237 /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
238 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
240 unsigned getShufflePSHUFLWImmediate(SDNode *N);
243 //===----------------------------------------------------------------------===//
244 // X86TargetLowering - X86 Implementation of the TargetLowering interface
245 class X86TargetLowering : public TargetLowering {
246 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
247 int ReturnAddrIndex; // FrameIndex for return slot.
248 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
249 int BytesCallerReserves; // Number of arg bytes caller makes.
251 X86TargetLowering(TargetMachine &TM);
253 // Return the number of bytes that a function should pop when it returns (in
254 // addition to the space used by the return address).
256 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
258 // Return the number of bytes that the caller reserves for arguments passed
260 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
262 /// LowerOperation - Provide custom lowering hooks for some operations.
264 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
266 /// LowerArguments - This hook must be implemented to indicate how we should
267 /// lower the arguments for the specified function, into the specified DAG.
268 virtual std::vector<SDOperand>
269 LowerArguments(Function &F, SelectionDAG &DAG);
271 /// LowerCallTo - This hook lowers an abstract call to a function into an
273 virtual std::pair<SDOperand, SDOperand>
274 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
275 bool isTailCall, SDOperand Callee, ArgListTy &Args,
278 virtual std::pair<SDOperand, SDOperand>
279 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
282 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
283 MachineBasicBlock *MBB);
285 /// getTargetNodeName - This method returns the name of a target specific
287 virtual const char *getTargetNodeName(unsigned Opcode) const;
289 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
290 /// in Mask are known to be either zero or one and return them in the
291 /// KnownZero/KnownOne bitsets.
292 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
296 unsigned Depth = 0) const;
298 SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
300 std::vector<unsigned>
301 getRegClassForInlineAsmConstraint(const std::string &Constraint,
302 MVT::ValueType VT) const;
304 /// isLegalAddressImmediate - Return true if the integer value or
305 /// GlobalValue can be used as the offset of the target addressing mode.
306 virtual bool isLegalAddressImmediate(int64_t V) const;
307 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
309 /// isShuffleMaskLegal - Targets can use this to indicate that they only
310 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
311 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
312 /// are assumed to be legal.
313 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
315 // C Calling Convention implementation.
316 std::vector<SDOperand> LowerCCCArguments(Function &F, SelectionDAG &DAG);
317 std::pair<SDOperand, SDOperand>
318 LowerCCCCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
320 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
322 // Fast Calling Convention implementation.
323 std::vector<SDOperand> LowerFastCCArguments(Function &F, SelectionDAG &DAG);
324 std::pair<SDOperand, SDOperand>
325 LowerFastCCCallTo(SDOperand Chain, const Type *RetTy, bool isTailCall,
326 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
328 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
329 /// make the right decision when generating code for different targets.
330 const X86Subtarget *Subtarget;
332 /// X86ScalarSSE - Select between SSE2 or x87 floating point ops.
337 #endif // X86ISELLOWERING_H