1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetOptions.h"
25 class X86TargetMachine;
28 // X86 Specific DAG Nodes
30 // Start the numbering where the builtin ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 /// BSF - Bit scan forward.
34 /// BSR - Bit scan reverse.
38 /// SHLD, SHRD - Double shift instructions. These correspond to
39 /// X86::SHLDxx and X86::SHRDxx instructions.
43 /// FAND - Bitwise logical AND of floating point values. This corresponds
44 /// to X86::ANDPS or X86::ANDPD.
47 /// FOR - Bitwise logical OR of floating point values. This corresponds
48 /// to X86::ORPS or X86::ORPD.
51 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
52 /// to X86::XORPS or X86::XORPD.
55 /// FANDN - Bitwise logical ANDNOT of floating point values. This
56 /// corresponds to X86::ANDNPS or X86::ANDNPD.
59 /// FSRL - Bitwise logical right shift of floating point values. These
60 /// corresponds to X86::PSRLDQ.
63 /// CALL - These operations represent an abstract X86 call
64 /// instruction, which includes a bunch of information. In particular the
65 /// operands of these node are:
67 /// #0 - The incoming token chain
69 /// #2 - The number of arg bytes the caller pushes on the stack.
70 /// #3 - The number of arg bytes the callee pops off the stack.
71 /// #4 - The value to pass in AL/AX/EAX (optional)
72 /// #5 - The value to pass in DL/DX/EDX (optional)
74 /// The result values of these nodes are:
76 /// #0 - The outgoing token chain
77 /// #1 - The first register result value (optional)
78 /// #2 - The second register result value (optional)
82 /// RDTSC_DAG - This operation implements the lowering for
86 /// X86 Read Time-Stamp Counter and Processor ID.
89 /// X86 compare and logical compare instructions.
92 /// X86 bit-test instructions.
95 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
96 /// operand, usually produced by a CMP instruction.
102 // Same as SETCC except it's materialized with a sbb and the value is all
103 // one's or all zero's.
104 SETCC_CARRY, // R = carry_bit ? ~0 : 0
106 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
107 /// Operands are two FP values to compare; result is a mask of
108 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
111 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
112 /// result in an integer GPR. Needs masking for scalar result.
115 /// X86 conditional moves. Operand 0 and operand 1 are the two values
116 /// to select from. Operand 2 is the condition code, and operand 3 is the
117 /// flag operand produced by a CMP or TEST instruction. It also writes a
121 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
122 /// is the block to branch if condition is true, operand 2 is the
123 /// condition code, and operand 3 is the flag operand produced by a CMP
124 /// or TEST instruction.
127 /// Return with a flag operand. Operand 0 is the chain operand, operand
128 /// 1 is the number of bytes of stack to pop.
131 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
134 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
137 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
138 /// at function entry, used for PIC code.
141 /// Wrapper - A wrapper node for TargetConstantPool,
142 /// TargetExternalSymbol, and TargetGlobalAddress.
145 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
146 /// relative displacements.
149 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
150 /// to an MMX vector. If you think this is too close to the previous
151 /// mnemonic, so do I; blame Intel.
154 /// MMX_MOVD2W - Copies a 32-bit value from the low word of a MMX
158 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
159 /// i32, corresponds to X86::PEXTRB.
162 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
163 /// i32, corresponds to X86::PEXTRW.
166 /// INSERTPS - Insert any element of a 4 x float vector into any element
167 /// of a destination 4 x floatvector.
170 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
171 /// corresponds to X86::PINSRB.
174 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
175 /// corresponds to X86::PINSRW.
178 /// PSHUFB - Shuffle 16 8-bit values within a vector.
181 /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
184 /// PSIGN - Copy integer sign.
187 /// BLENDV - Blend where the selector is a register.
190 /// BLENDI - Blend where the selector is an immediate.
193 // SUBUS - Integer sub with unsigned saturation.
196 /// HADD - Integer horizontal add.
199 /// HSUB - Integer horizontal sub.
202 /// FHADD - Floating point horizontal add.
205 /// FHSUB - Floating point horizontal sub.
208 /// UMAX, UMIN - Unsigned integer max and min.
211 /// SMAX, SMIN - Signed integer max and min.
214 /// FMAX, FMIN - Floating point max and min.
218 /// FMAXC, FMINC - Commutative FMIN and FMAX.
221 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
222 /// approximation. Note that these typically require refinement
223 /// in order to obtain suitable precision.
226 // TLSADDR - Thread Local Storage.
229 // TLSBASEADDR - Thread Local Storage. A call to get the start address
230 // of the TLS block for the current module.
233 // TLSCALL - Thread Local Storage. When calling to an OS provided
234 // thunk at the address from an earlier relocation.
237 // EH_RETURN - Exception Handling helpers.
240 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
243 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
246 /// TC_RETURN - Tail call return. See X86TargetLowering::LowerCall for
247 /// the list of operands.
250 // VZEXT_MOVL - Vector move to low scalar and zero higher vector elements.
253 // VZEXT - Vector integer zero-extend.
256 // VSEXT - Vector integer signed-extend.
259 // VTRUNC - Vector integer truncate.
262 // VTRUNC - Vector integer truncate with mask.
265 // VFPEXT - Vector FP extend.
268 // VFPROUND - Vector FP round.
271 // VSHL, VSRL - 128-bit vector logical left / right shift
274 // VSHL, VSRL, VSRA - Vector shift elements
277 // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate
280 // CMPP - Vector packed double/float comparison.
283 // PCMP* - Vector integer comparisons.
285 // PCMP*M - Vector integer comparisons, the result is in a mask vector.
288 /// CMPM, CMPMU - Vector comparison generating mask bits for fp and
289 /// integer signed and unsigned data types.
293 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
294 ADD, SUB, ADC, SBB, SMUL,
295 INC, DEC, OR, XOR, AND,
297 BEXTR, // BEXTR - Bit field extract
299 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
301 // MUL_IMM - X86 specific multiply by immediate.
304 // PTEST - Vector bitwise comparisons.
307 // TESTP - Vector packed fp sign bitwise comparisons.
310 // TESTM, TESTNM - Vector "test" in AVX-512, the result is in a mask vector.
314 // OR/AND test for masks
317 // Several flavors of instructions with vector shuffle behaviors.
344 // Insert/Extract vector element
348 // PMULUDQ - Vector multiply packed unsigned doubleword integers
350 // PMULUDQ - Vector multiply packed signed doubleword integers
361 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
362 // according to %al. An operator is needed so that this can be expanded
363 // with control flow.
364 VASTART_SAVE_XMM_REGS,
366 // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
369 // SEG_ALLOCA - For allocating variable amounts of stack space when using
370 // segmented stacks. Check if the current stacklet has enough space, and
371 // falls back to heap allocation if not.
374 // WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui.
383 // FNSTSW16r - Store FP status word into i16 register.
386 // SAHF - Store contents of %ah into %eflags.
389 // RDRAND - Get a random integer and indicate whether it is valid in CF.
392 // RDSEED - Get a NIST SP800-90B & C compliant random integer and
393 // indicate whether it is valid in CF.
400 // XTEST - Test if in transactional execution.
403 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
404 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
405 // Atomic 64-bit binary operations.
406 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
418 // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
423 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
426 // FNSTCW16m - Store FP control world into i16 memory.
429 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
430 /// integer destination in memory and a FP reg source. This corresponds
431 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
432 /// has two inputs (token chain and address) and two outputs (int value
433 /// and token chain).
438 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
439 /// integer source in memory and FP reg result. This corresponds to the
440 /// X86::FILD*m instructions. It has three inputs (token chain, address,
441 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
442 /// also produces a flag).
446 /// FLD - This instruction implements an extending load to FP stack slots.
447 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
448 /// operand, ptr to load from, and a ValueType node indicating the type
452 /// FST - This instruction implements a truncating store to FP stack
453 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
454 /// chain operand, value to store, address, and a ValueType to store it
458 /// VAARG_64 - This instruction grabs the address of the next argument
459 /// from a va_list. (reads and modifies the va_list in memory)
462 // WARNING: Do not add anything in the end unless you want the node to
463 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
464 // thought as target memory ops!
468 /// Define some predicates that are used for node matching.
470 /// isVEXTRACT128Index - Return true if the specified
471 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
472 /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
473 bool isVEXTRACT128Index(SDNode *N);
475 /// isVINSERT128Index - Return true if the specified
476 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
477 /// suitable for input to VINSERTF128, VINSERTI128 instructions.
478 bool isVINSERT128Index(SDNode *N);
480 /// isVEXTRACT256Index - Return true if the specified
481 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
482 /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
483 bool isVEXTRACT256Index(SDNode *N);
485 /// isVINSERT256Index - Return true if the specified
486 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
487 /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
488 bool isVINSERT256Index(SDNode *N);
490 /// getExtractVEXTRACT128Immediate - Return the appropriate
491 /// immediate to extract the specified EXTRACT_SUBVECTOR index
492 /// with VEXTRACTF128, VEXTRACTI128 instructions.
493 unsigned getExtractVEXTRACT128Immediate(SDNode *N);
495 /// getInsertVINSERT128Immediate - Return the appropriate
496 /// immediate to insert at the specified INSERT_SUBVECTOR index
497 /// with VINSERTF128, VINSERT128 instructions.
498 unsigned getInsertVINSERT128Immediate(SDNode *N);
500 /// getExtractVEXTRACT256Immediate - Return the appropriate
501 /// immediate to extract the specified EXTRACT_SUBVECTOR index
502 /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
503 unsigned getExtractVEXTRACT256Immediate(SDNode *N);
505 /// getInsertVINSERT256Immediate - Return the appropriate
506 /// immediate to insert at the specified INSERT_SUBVECTOR index
507 /// with VINSERTF64x4, VINSERTI64x4 instructions.
508 unsigned getInsertVINSERT256Immediate(SDNode *N);
510 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
512 bool isZeroNode(SDValue Elt);
514 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
515 /// fit into displacement field of the instruction.
516 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
517 bool hasSymbolicDisplacement = true);
520 /// isCalleePop - Determines whether the callee is required to pop its
521 /// own arguments. Callee pop is necessary to support tail calls.
522 bool isCalleePop(CallingConv::ID CallingConv,
523 bool is64Bit, bool IsVarArg, bool TailCallOpt);
526 //===--------------------------------------------------------------------===//
527 // X86TargetLowering - X86 Implementation of the TargetLowering interface
528 class X86TargetLowering final : public TargetLowering {
530 explicit X86TargetLowering(X86TargetMachine &TM);
532 unsigned getJumpTableEncoding() const override;
534 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i8; }
537 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
538 const MachineBasicBlock *MBB, unsigned uid,
539 MCContext &Ctx) const override;
541 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
543 SDValue getPICJumpTableRelocBase(SDValue Table,
544 SelectionDAG &DAG) const override;
546 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
547 unsigned JTI, MCContext &Ctx) const override;
549 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
550 /// function arguments in the caller parameter area. For X86, aggregates
551 /// that contains are placed at 16-byte boundaries while the rest are at
552 /// 4-byte boundaries.
553 unsigned getByValTypeAlignment(Type *Ty) const override;
555 /// getOptimalMemOpType - Returns the target specific optimal type for load
556 /// and store operations as a result of memset, memcpy, and memmove
557 /// lowering. If DstAlign is zero that means it's safe to destination
558 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
559 /// means there isn't a need to check it against alignment requirement,
560 /// probably because the source does not need to be loaded. If 'IsMemset' is
561 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
562 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
563 /// source is constant so it does not need to be loaded.
564 /// It returns EVT::Other if the type should be determined using generic
565 /// target-independent logic.
566 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
567 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
568 MachineFunction &MF) const override;
570 /// isSafeMemOpType - Returns true if it's safe to use load / store of the
571 /// specified type to expand memcpy / memset inline. This is mostly true
572 /// for all types except for some special cases. For example, on X86
573 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
574 /// also does type conversion. Note the specified type doesn't have to be
575 /// legal as the hook is used before type legalization.
576 bool isSafeMemOpType(MVT VT) const override;
578 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
579 /// unaligned memory accesses. of the specified type. Returns whether it
580 /// is "fast" by reference in the second argument.
581 bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS,
582 bool *Fast) const override;
584 /// LowerOperation - Provide custom lowering hooks for some operations.
586 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
588 /// ReplaceNodeResults - Replace the results of node with an illegal result
589 /// type with new values built out of custom code.
591 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
592 SelectionDAG &DAG) const override;
595 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
597 /// isTypeDesirableForOp - Return true if the target has native support for
598 /// the specified value type and it is 'desirable' to use the type for the
599 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
600 /// instruction encodings are longer and some i16 instructions are slow.
601 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
603 /// isTypeDesirable - Return true if the target has native support for the
604 /// specified value type and it is 'desirable' to use the type. e.g. On x86
605 /// i16 is legal, but undesirable since i16 instruction encodings are longer
606 /// and some i16 instructions are slow.
607 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
610 EmitInstrWithCustomInserter(MachineInstr *MI,
611 MachineBasicBlock *MBB) const override;
614 /// getTargetNodeName - This method returns the name of a target specific
616 const char *getTargetNodeName(unsigned Opcode) const override;
618 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
619 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
621 /// computeKnownBitsForTargetNode - Determine which of the bits specified
622 /// in Mask are known to be either zero or one and return them in the
623 /// KnownZero/KnownOne bitsets.
624 void computeKnownBitsForTargetNode(const SDValue Op,
627 const SelectionDAG &DAG,
628 unsigned Depth = 0) const override;
630 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
631 // operation that are sign bits.
632 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
633 const SelectionDAG &DAG,
634 unsigned Depth) const override;
636 bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
637 int64_t &Offset) const override;
639 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
641 bool ExpandInlineAsm(CallInst *CI) const override;
644 getConstraintType(const std::string &Constraint) const override;
646 /// Examine constraint string and operand type and determine a weight value.
647 /// The operand object must already have been set up with the operand type.
649 getSingleConstraintMatchWeight(AsmOperandInfo &info,
650 const char *constraint) const override;
652 const char *LowerXConstraint(EVT ConstraintVT) const override;
654 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
655 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
656 /// true it means one of the asm constraint of the inline asm instruction
657 /// being processed is 'm'.
658 void LowerAsmOperandForConstraint(SDValue Op,
659 std::string &Constraint,
660 std::vector<SDValue> &Ops,
661 SelectionDAG &DAG) const override;
663 /// getRegForInlineAsmConstraint - Given a physical register constraint
664 /// (e.g. {edx}), return the register number and the register class for the
665 /// register. This should only be used for C_Register constraints. On
666 /// error, this returns a register number of 0.
667 std::pair<unsigned, const TargetRegisterClass*>
668 getRegForInlineAsmConstraint(const std::string &Constraint,
669 MVT VT) const override;
671 /// isLegalAddressingMode - Return true if the addressing mode represented
672 /// by AM is legal for this target, for a load/store of the specified type.
673 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
675 /// isLegalICmpImmediate - Return true if the specified immediate is legal
676 /// icmp immediate, that is the target has icmp instructions which can
677 /// compare a register against the immediate without having to materialize
678 /// the immediate into a register.
679 bool isLegalICmpImmediate(int64_t Imm) const override;
681 /// isLegalAddImmediate - Return true if the specified immediate is legal
682 /// add immediate, that is the target has add instructions which can
683 /// add a register and the immediate without having to materialize
684 /// the immediate into a register.
685 bool isLegalAddImmediate(int64_t Imm) const override;
687 /// \brief Return the cost of the scaling factor used in the addressing
688 /// mode represented by AM for this target, for a load/store
689 /// of the specified type.
690 /// If the AM is supported, the return value must be >= 0.
691 /// If the AM is not supported, it returns a negative value.
692 int getScalingFactorCost(const AddrMode &AM, Type *Ty) const override;
694 bool isVectorShiftByScalarCheap(Type *Ty) const override;
696 /// isTruncateFree - Return true if it's free to truncate a value of
697 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
698 /// register EAX to i16 by referencing its sub-register AX.
699 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
700 bool isTruncateFree(EVT VT1, EVT VT2) const override;
702 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
704 /// isZExtFree - Return true if any actual instruction that defines a
705 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
706 /// register. This does not necessarily include registers defined in
707 /// unknown ways, such as incoming arguments, or copies from unknown
708 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
709 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
710 /// all instructions that define 32-bit values implicit zero-extend the
711 /// result out to 64 bits.
712 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
713 bool isZExtFree(EVT VT1, EVT VT2) const override;
714 bool isZExtFree(SDValue Val, EVT VT2) const override;
716 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
717 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
718 /// expanded to FMAs when this method returns true, otherwise fmuladd is
719 /// expanded to fmul + fadd.
720 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
722 /// isNarrowingProfitable - Return true if it's profitable to narrow
723 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
724 /// from i32 to i8 but not from i32 to i16.
725 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
727 /// isFPImmLegal - Returns true if the target can instruction select the
728 /// specified FP immediate natively. If false, the legalizer will
729 /// materialize the FP immediate as a load from a constant pool.
730 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
732 /// isShuffleMaskLegal - Targets can use this to indicate that they only
733 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
734 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
735 /// values are assumed to be legal.
736 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
737 EVT VT) const override;
739 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
740 /// used by Targets can use this to indicate if there is a suitable
741 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
743 bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
744 EVT VT) const override;
746 /// ShouldShrinkFPConstant - If true, then instruction selection should
747 /// seek to shrink the FP constant of the specified type to a smaller type
748 /// in order to save space and / or reduce runtime.
749 bool ShouldShrinkFPConstant(EVT VT) const override {
750 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
751 // expensive than a straight movsd. On the other hand, it's important to
752 // shrink long double fp constant since fldt is very slow.
753 return !X86ScalarSSEf64 || VT == MVT::f80;
756 const X86Subtarget* getSubtarget() const {
760 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
761 /// computed in an SSE register, not on the X87 floating point stack.
762 bool isScalarFPTypeInSSEReg(EVT VT) const {
763 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
764 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
767 /// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine
769 bool isTargetFTOL() const {
770 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();
773 /// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be
774 /// used for fptoui to the given type.
775 bool isIntegerTypeFTOL(EVT VT) const {
776 return isTargetFTOL() && VT == MVT::i64;
779 /// \brief Returns true if it is beneficial to convert a load of a constant
780 /// to just the constant itself.
781 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
782 Type *Ty) const override;
784 /// Intel processors have a unified instruction and data cache
785 const char * getClearCacheBuiltinName() const override {
786 return nullptr; // nothing to do, move along.
789 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
791 /// createFastISel - This method returns a target specific FastISel object,
792 /// or null if the target does not support "fast" ISel.
793 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
794 const TargetLibraryInfo *libInfo) const override;
796 /// getStackCookieLocation - Return true if the target stores stack
797 /// protector cookies at a fixed offset in some non-standard address
798 /// space, and populates the address space and offset as
800 bool getStackCookieLocation(unsigned &AddressSpace,
801 unsigned &Offset) const override;
803 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
804 SelectionDAG &DAG) const;
806 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
808 /// \brief Reset the operation actions based on target options.
809 void resetOperationActions() override;
812 std::pair<const TargetRegisterClass*, uint8_t>
813 findRepresentativeClass(MVT VT) const override;
816 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
817 /// make the right decision when generating code for different targets.
818 const X86Subtarget *Subtarget;
819 const DataLayout *TD;
821 /// Used to store the TargetOptions so that we don't waste time resetting
822 /// the operation actions unless we have to.
825 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
826 /// floating point ops.
827 /// When SSE is available, use it for f32 operations.
828 /// When SSE2 is available, use it for f64 operations.
829 bool X86ScalarSSEf32;
830 bool X86ScalarSSEf64;
832 /// LegalFPImmediates - A list of legal fp immediates.
833 std::vector<APFloat> LegalFPImmediates;
835 /// addLegalFPImmediate - Indicate that this x86 target can instruction
836 /// select the specified FP immediate natively.
837 void addLegalFPImmediate(const APFloat& Imm) {
838 LegalFPImmediates.push_back(Imm);
841 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
842 CallingConv::ID CallConv, bool isVarArg,
843 const SmallVectorImpl<ISD::InputArg> &Ins,
844 SDLoc dl, SelectionDAG &DAG,
845 SmallVectorImpl<SDValue> &InVals) const;
846 SDValue LowerMemArgument(SDValue Chain,
847 CallingConv::ID CallConv,
848 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
849 SDLoc dl, SelectionDAG &DAG,
850 const CCValAssign &VA, MachineFrameInfo *MFI,
852 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
853 SDLoc dl, SelectionDAG &DAG,
854 const CCValAssign &VA,
855 ISD::ArgFlagsTy Flags) const;
857 // Call lowering helpers.
859 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
860 /// for tail call optimization. Targets which want to do tail call
861 /// optimization should implement this function.
862 bool IsEligibleForTailCallOptimization(SDValue Callee,
863 CallingConv::ID CalleeCC,
865 bool isCalleeStructRet,
866 bool isCallerStructRet,
868 const SmallVectorImpl<ISD::OutputArg> &Outs,
869 const SmallVectorImpl<SDValue> &OutVals,
870 const SmallVectorImpl<ISD::InputArg> &Ins,
871 SelectionDAG& DAG) const;
872 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
873 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
874 SDValue Chain, bool IsTailCall, bool Is64Bit,
875 int FPDiff, SDLoc dl) const;
877 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
878 SelectionDAG &DAG) const;
880 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
882 bool isReplace) const;
884 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
885 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
886 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
887 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
888 SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const;
889 SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const;
891 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
892 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
893 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
894 SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
895 int64_t Offset, SelectionDAG &DAG) const;
896 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
897 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
898 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
899 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
900 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
901 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
902 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
903 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
904 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
905 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
906 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
907 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
908 SDLoc dl, SelectionDAG &DAG) const;
909 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
910 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
911 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
912 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
913 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
914 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
915 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
916 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
917 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
918 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
919 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
920 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
921 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
922 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
923 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
924 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
925 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
926 SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
929 LowerFormalArguments(SDValue Chain,
930 CallingConv::ID CallConv, bool isVarArg,
931 const SmallVectorImpl<ISD::InputArg> &Ins,
932 SDLoc dl, SelectionDAG &DAG,
933 SmallVectorImpl<SDValue> &InVals) const override;
934 SDValue LowerCall(CallLoweringInfo &CLI,
935 SmallVectorImpl<SDValue> &InVals) const override;
937 SDValue LowerReturn(SDValue Chain,
938 CallingConv::ID CallConv, bool isVarArg,
939 const SmallVectorImpl<ISD::OutputArg> &Outs,
940 const SmallVectorImpl<SDValue> &OutVals,
941 SDLoc dl, SelectionDAG &DAG) const override;
943 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
945 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
947 MVT getTypeForExtArgOrReturn(MVT VT,
948 ISD::NodeType ExtendKind) const override;
950 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
952 const SmallVectorImpl<ISD::OutputArg> &Outs,
953 LLVMContext &Context) const override;
955 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
957 /// Utility function to emit atomic-load-arith operations (and, or, xor,
958 /// nand, max, min, umax, umin). It takes the corresponding instruction to
959 /// expand, the associated machine basic block, and the associated X86
960 /// opcodes for reg/reg.
961 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
962 MachineBasicBlock *MBB) const;
964 /// Utility function to emit atomic-load-arith operations (and, or, xor,
965 /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
966 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
967 MachineBasicBlock *MBB) const;
969 // Utility function to emit the low-level va_arg code for X86-64.
970 MachineBasicBlock *EmitVAARG64WithCustomInserter(
972 MachineBasicBlock *MBB) const;
974 /// Utility function to emit the xmm reg save portion of va_start.
975 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
976 MachineInstr *BInstr,
977 MachineBasicBlock *BB) const;
979 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
980 MachineBasicBlock *BB) const;
982 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
983 MachineBasicBlock *BB) const;
985 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
986 MachineBasicBlock *BB,
989 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
990 MachineBasicBlock *BB) const;
992 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
993 MachineBasicBlock *BB) const;
995 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
996 MachineBasicBlock *MBB) const;
998 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
999 MachineBasicBlock *MBB) const;
1001 MachineBasicBlock *emitFMA3Instr(MachineInstr *MI,
1002 MachineBasicBlock *MBB) const;
1004 /// Emit nodes that will be selected as "test Op0,Op0", or something
1005 /// equivalent, for use with the given x86 condition code.
1006 SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl,
1007 SelectionDAG &DAG) const;
1009 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
1010 /// equivalent, for use with the given x86 condition code.
1011 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl,
1012 SelectionDAG &DAG) const;
1014 /// Convert a comparison if required by the subtarget.
1015 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
1019 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1020 const TargetLibraryInfo *libInfo);
1024 #endif // X86ISELLOWERING_H