1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
27 // X86 Specific DAG Nodes
29 // Start the numbering where the builtin ops leave off.
30 FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
32 /// BSF - Bit scan forward.
33 /// BSR - Bit scan reverse.
37 /// SHLD, SHRD - Double shift instructions. These correspond to
38 /// X86::SHLDxx and X86::SHRDxx instructions.
42 /// FAND - Bitwise logical AND of floating point values. This corresponds
43 /// to X86::ANDPS or X86::ANDPD.
46 /// FOR - Bitwise logical OR of floating point values. This corresponds
47 /// to X86::ORPS or X86::ORPD.
50 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
51 /// to X86::XORPS or X86::XORPD.
54 /// FSRL - Bitwise logical right shift of floating point values. These
55 /// corresponds to X86::PSRLDQ.
58 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
59 /// integer source in memory and FP reg result. This corresponds to the
60 /// X86::FILD*m instructions. It has three inputs (token chain, address,
61 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
62 /// also produces a flag).
66 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
67 /// integer destination in memory and a FP reg source. This corresponds
68 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
69 /// has two inputs (token chain and address) and two outputs (int value
75 /// FLD - This instruction implements an extending load to FP stack slots.
76 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
77 /// operand, ptr to load from, and a ValueType node indicating the type
81 /// FST - This instruction implements a truncating store to FP stack
82 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
83 /// chain operand, value to store, address, and a ValueType to store it
87 /// FP_GET_RESULT - This corresponds to FpGETRESULT pseudo instruction
88 /// which copies from ST(0) to the destination. It takes a chain and
89 /// writes a RFP result and a chain.
92 /// FP_SET_RESULT - This corresponds to FpSETRESULT pseudo instruction
93 /// which copies the source operand to ST(0). It takes a chain+value and
94 /// returns a chain and a flag.
97 /// CALL/TAILCALL - These operations represent an abstract X86 call
98 /// instruction, which includes a bunch of information. In particular the
99 /// operands of these node are:
101 /// #0 - The incoming token chain
103 /// #2 - The number of arg bytes the caller pushes on the stack.
104 /// #3 - The number of arg bytes the callee pops off the stack.
105 /// #4 - The value to pass in AL/AX/EAX (optional)
106 /// #5 - The value to pass in DL/DX/EDX (optional)
108 /// The result values of these nodes are:
110 /// #0 - The outgoing token chain
111 /// #1 - The first register result value (optional)
112 /// #2 - The second register result value (optional)
114 /// The CALL vs TAILCALL distinction boils down to whether the callee is
115 /// known not to modify the caller's stack frame, as is standard with
120 /// RDTSC_DAG - This operation implements the lowering for
124 /// X86 compare and logical compare instructions.
127 /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
128 /// operand produced by a CMP instruction.
131 /// X86 conditional moves. Operand 1 and operand 2 are the two values
132 /// to select from (operand 1 is a R/W operand). Operand 3 is the
133 /// condition code, and operand 4 is the flag operand produced by a CMP
134 /// or TEST instruction. It also writes a flag result.
137 /// X86 conditional branches. Operand 1 is the chain operand, operand 2
138 /// is the block to branch if condition is true, operand 3 is the
139 /// condition code, and operand 4 is the flag operand produced by a CMP
140 /// or TEST instruction.
143 /// Return with a flag operand. Operand 1 is the chain operand, operand
144 /// 2 is the number of bytes of stack to pop.
147 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
150 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
153 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
154 /// at function entry, used for PIC code.
157 /// Wrapper - A wrapper node for TargetConstantPool,
158 /// TargetExternalSymbol, and TargetGlobalAddress.
161 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
162 /// relative displacements.
165 /// S2VEC - X86 version of SCALAR_TO_VECTOR. The destination base does not
166 /// have to match the operand type.
169 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
170 /// i32, corresponds to X86::PEXTRW.
173 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
174 /// corresponds to X86::PINSRW.
177 /// FMAX, FMIN - Floating point max and min.
181 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
182 /// approximation. Note that these typically require refinement
183 /// in order to obtain suitable precision.
186 // Thread Local Storage
187 TLSADDR, THREAD_POINTER,
189 // Exception Handling helpers
194 // operand #1 callee (register or absolute)
195 // operand #2 stack adjustment
196 // operand #3 optional in flag
199 // Store FP control world into i16 memory
204 /// Define some predicates that are used for node matching.
206 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
207 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
208 bool isPSHUFDMask(SDNode *N);
210 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
211 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
212 bool isPSHUFHWMask(SDNode *N);
214 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
215 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
216 bool isPSHUFLWMask(SDNode *N);
218 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
219 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
220 bool isSHUFPMask(SDNode *N);
222 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
223 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
224 bool isMOVHLPSMask(SDNode *N);
226 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
227 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
229 bool isMOVHLPS_v_undef_Mask(SDNode *N);
231 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
232 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
233 bool isMOVLPMask(SDNode *N);
235 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
236 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
237 /// as well as MOVLHPS.
238 bool isMOVHPMask(SDNode *N);
240 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
241 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
242 bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false);
244 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
245 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
246 bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false);
248 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
249 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
251 bool isUNPCKL_v_undef_Mask(SDNode *N);
253 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
254 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
256 bool isUNPCKH_v_undef_Mask(SDNode *N);
258 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
259 /// specifies a shuffle of elements that is suitable for input to MOVSS,
260 /// MOVSD, and MOVD, i.e. setting the lowest element.
261 bool isMOVLMask(SDNode *N);
263 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
264 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
265 bool isMOVSHDUPMask(SDNode *N);
267 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
268 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
269 bool isMOVSLDUPMask(SDNode *N);
271 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
272 /// specifies a splat of a single element.
273 bool isSplatMask(SDNode *N);
275 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
276 /// specifies a splat of zero element.
277 bool isSplatLoMask(SDNode *N);
279 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
280 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
282 unsigned getShuffleSHUFImmediate(SDNode *N);
284 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
285 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
287 unsigned getShufflePSHUFHWImmediate(SDNode *N);
289 /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
290 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
292 unsigned getShufflePSHUFLWImmediate(SDNode *N);
295 //===--------------------------------------------------------------------===//
296 // X86TargetLowering - X86 Implementation of the TargetLowering interface
297 class X86TargetLowering : public TargetLowering {
298 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
299 int RegSaveFrameIndex; // X86-64 vararg func register save area.
300 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
301 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
302 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
303 int BytesCallerReserves; // Number of arg bytes caller makes.
306 explicit X86TargetLowering(TargetMachine &TM);
308 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
310 SDOperand getPICJumpTableRelocBase(SDOperand Table,
311 SelectionDAG &DAG) const;
313 // Return the number of bytes that a function should pop when it returns (in
314 // addition to the space used by the return address).
316 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
318 // Return the number of bytes that the caller reserves for arguments passed
320 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
322 /// getStackPtrReg - Return the stack pointer register we are using: either
324 unsigned getStackPtrReg() const { return X86StackPtr; }
326 /// LowerOperation - Provide custom lowering hooks for some operations.
328 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
330 /// ExpandOperation - Custom lower the specified operation, splitting the
331 /// value into two pieces.
333 virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG);
336 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
338 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
339 MachineBasicBlock *MBB);
341 /// getTargetNodeName - This method returns the name of a target specific
343 virtual const char *getTargetNodeName(unsigned Opcode) const;
345 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
346 /// in Mask are known to be either zero or one and return them in the
347 /// KnownZero/KnownOne bitsets.
348 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
352 const SelectionDAG &DAG,
353 unsigned Depth = 0) const;
355 SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
357 ConstraintType getConstraintType(const std::string &Constraint) const;
359 std::vector<unsigned>
360 getRegClassForInlineAsmConstraint(const std::string &Constraint,
361 MVT::ValueType VT) const;
363 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
364 /// vector. If it is invalid, don't add anything to Ops.
365 virtual void LowerAsmOperandForConstraint(SDOperand Op,
366 char ConstraintLetter,
367 std::vector<SDOperand> &Ops,
370 /// getRegForInlineAsmConstraint - Given a physical register constraint
371 /// (e.g. {edx}), return the register number and the register class for the
372 /// register. This should only be used for C_Register constraints. On
373 /// error, this returns a register number of 0.
374 std::pair<unsigned, const TargetRegisterClass*>
375 getRegForInlineAsmConstraint(const std::string &Constraint,
376 MVT::ValueType VT) const;
378 /// isLegalAddressingMode - Return true if the addressing mode represented
379 /// by AM is legal for this target, for a load/store of the specified type.
380 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
382 /// isTruncateFree - Return true if it's free to truncate a value of
383 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
384 /// register EAX to i16 by referencing its sub-register AX.
385 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
386 virtual bool isTruncateFree(MVT::ValueType VT1, MVT::ValueType VT2) const;
388 /// isShuffleMaskLegal - Targets can use this to indicate that they only
389 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
390 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
391 /// values are assumed to be legal.
392 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
394 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
395 /// used by Targets can use this to indicate if there is a suitable
396 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
398 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
400 SelectionDAG &DAG) const;
402 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
403 /// for tail call optimization. Target which want to do tail call
404 /// optimization should implement this function.
405 virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
407 SelectionDAG &DAG) const;
409 virtual const TargetSubtarget* getSubtarget() {
410 return static_cast<const TargetSubtarget*>(Subtarget);
414 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
415 /// make the right decision when generating code for different targets.
416 const X86Subtarget *Subtarget;
417 const MRegisterInfo *RegInfo;
419 /// X86StackPtr - X86 physical register used as stack ptr.
420 unsigned X86StackPtr;
422 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
423 /// floating point ops.
424 /// When SSE is available, use it for f32 operations.
425 /// When SSE2 is available, use it for f64 operations.
426 bool X86ScalarSSEf32;
427 bool X86ScalarSSEf64;
429 SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall,
430 unsigned CallingConv, SelectionDAG &DAG);
433 SDOperand LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
434 const CCValAssign &VA, MachineFrameInfo *MFI,
435 SDOperand Root, unsigned i);
437 SDOperand LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
438 const SDOperand &StackPtr,
439 const CCValAssign &VA, SDOperand Chain,
442 // Call lowering helpers.
443 bool IsCalleePop(SDOperand Op);
444 CCAssignFn *CCAssignFnForNode(SDOperand Op) const;
445 NameDecorationStyle NameDecorationForFORMAL_ARGUMENTS(SDOperand Op);
446 unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG);
448 std::pair<SDOperand,SDOperand> FP_TO_SINTHelper(SDOperand Op,
451 SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
452 SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
453 SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
454 SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
455 SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
456 SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
457 SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
458 SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
459 SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG);
460 SDOperand LowerShift(SDOperand Op, SelectionDAG &DAG);
461 SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
462 SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
463 SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
464 SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
465 SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG);
466 SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
467 SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
468 SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
469 SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
470 SDOperand LowerMEMCPYInline(SDOperand Dest, SDOperand Source,
471 SDOperand Chain, unsigned Size, unsigned Align,
473 SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
474 SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
475 SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
476 SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG);
477 SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
478 SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
479 SDOperand LowerVACOPY(SDOperand Op, SelectionDAG &DAG);
480 SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
481 SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
482 SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
483 SDOperand LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, SelectionDAG &DAG);
484 SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG);
485 SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG);
486 SDOperand LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG);
487 SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG);
488 SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG);
489 SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
490 SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG);
494 #endif // X86ISELLOWERING_H